/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the AArch64 target                         *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 105;
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(AArch64InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(AArch64InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static AArch64InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static AArch64InstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(2),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_s8,
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_s128,
  GILLT_v2s32,
  GILLT_v2s64,
  GILLT_v4s16,
  GILLT_v4s32,
  GILLT_v8s8,
  GILLT_v8s16,
  GILLT_v16s8,
  GILLT_nxv1s1,
  GILLT_nxv2s1,
  GILLT_nxv2s16,
  GILLT_nxv2s32,
  GILLT_nxv2s64,
  GILLT_nxv4s1,
  GILLT_nxv4s16,
  GILLT_nxv4s32,
  GILLT_nxv8s1,
  GILLT_nxv8s16,
  GILLT_nxv16s1,
  GILLT_nxv16s8,
};
const static size_t NumTypeObjects = 24;
const static LLT TypeObjects[] = {
  LLT::scalar(8),
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::scalar(128),
  LLT::vector(ElementCount::getFixed(2), 32),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(4), 16),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(8), 8),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(16), 8),
  LLT::vector(ElementCount::getScalable(1), 1),
  LLT::vector(ElementCount::getScalable(2), 1),
  LLT::vector(ElementCount::getScalable(2), 16),
  LLT::vector(ElementCount::getScalable(2), 32),
  LLT::vector(ElementCount::getScalable(2), 64),
  LLT::vector(ElementCount::getScalable(4), 1),
  LLT::vector(ElementCount::getScalable(4), 16),
  LLT::vector(ElementCount::getScalable(4), 32),
  LLT::vector(ElementCount::getScalable(8), 1),
  LLT::vector(ElementCount::getScalable(8), 16),
  LLT::vector(ElementCount::getScalable(16), 1),
  LLT::vector(ElementCount::getScalable(16), 8),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_HasPAuthBit = 6,
  Feature_HasJSBit = 8,
  Feature_HasComplxNumBit = 70,
  Feature_HasRCPC_IMMOBit = 92,
  Feature_HasFPARMv8Bit = 7,
  Feature_HasNEONBit = 5,
  Feature_HasSM4Bit = 69,
  Feature_HasSHA3Bit = 68,
  Feature_HasSHA2Bit = 18,
  Feature_HasAESBit = 17,
  Feature_HasDotProdBit = 2,
  Feature_HasCRCBit = 9,
  Feature_HasCSSCBit = 19,
  Feature_HasNoCSSCBit = 33,
  Feature_HasLSEBit = 34,
  Feature_HasNoLSEBit = 104,
  Feature_HasRDMBit = 15,
  Feature_HasFullFP16Bit = 12,
  Feature_HasNoFullFP16Bit = 89,
  Feature_HasFP16FMLBit = 4,
  Feature_HasFuseAESBit = 83,
  Feature_HasSVEBit = 27,
  Feature_HasSVE2Bit = 28,
  Feature_HasSVE2p1Bit = 48,
  Feature_HasSVEAESBit = 30,
  Feature_HasSVESM4Bit = 31,
  Feature_HasSVESHA3Bit = 102,
  Feature_HasSVEBitPermBit = 42,
  Feature_HasSMEandIsNonStreamingSafeBit = 61,
  Feature_HasSMEBit = 54,
  Feature_HasSMEF64F64Bit = 56,
  Feature_HasSMEF16F16Bit = 58,
  Feature_HasSMEI16I64Bit = 59,
  Feature_HasSME2andIsNonStreamingSafeBit = 65,
  Feature_HasSME2Bit = 63,
  Feature_HasSME2p1Bit = 67,
  Feature_HasFP8Bit = 20,
  Feature_HasFAMINMAXBit = 21,
  Feature_HasFP8FMABit = 22,
  Feature_HasSSVE_FP8FMABit = 51,
  Feature_HasFP8DOT2Bit = 23,
  Feature_HasSSVE_FP8DOT2Bit = 46,
  Feature_HasFP8DOT4Bit = 24,
  Feature_HasSSVE_FP8DOT4Bit = 52,
  Feature_HasLUTBit = 53,
  Feature_HasSME_LUTv2Bit = 66,
  Feature_HasSMEF8F16Bit = 57,
  Feature_HasSMEF8F32Bit = 55,
  Feature_HasSME_MOP4Bit = 60,
  Feature_HasSME_TMOPBit = 64,
  Feature_HasCMPBRBit = 90,
  Feature_HasF8F32MMBit = 26,
  Feature_HasF8F16MMBit = 25,
  Feature_HasFPRCVTBit = 13,
  Feature_HasLSFEBit = 35,
  Feature_HasSVE_F16F32MMBit = 100,
  Feature_HasSVE_or_SMEBit = 0,
  Feature_HasNonStreamingSVE_or_SME2p1Bit = 101,
  Feature_HasNonStreamingSVE_or_SME2p2Bit = 44,
  Feature_HasNonStreamingSVE_or_SSVE_AESBit = 29,
  Feature_HasNonStreamingSVE_or_SSVE_BitPermBit = 41,
  Feature_HasNonStreamingSVE_or_SSVE_FEXPABit = 45,
  Feature_HasSVE2_or_SMEBit = 37,
  Feature_HasNonStreamingSVE2_or_SME2Bit = 50,
  Feature_HasSVE2p1_or_SMEBit = 62,
  Feature_HasSVE2p1_or_SME2Bit = 40,
  Feature_HasSVE2p1_or_SME2p1Bit = 49,
  Feature_HasSVE2p1_or_StreamingSME2Bit = 32,
  Feature_HasSVE2p2_or_SME2p2Bit = 36,
  Feature_HasNonStreamingSVE2p2_or_SME2p2Bit = 43,
  Feature_HasSMEF16F16_or_SMEF8F16Bit = 103,
  Feature_HasNEONandIsStreamingSafeBit = 16,
  Feature_HasNEONandIsSME2p2StreamingSafeBit = 78,
  Feature_HasRCPCBit = 91,
  Feature_HasFRInt3264Bit = 14,
  Feature_HasMTEBit = 10,
  Feature_HasMatMulInt8Bit = 3,
  Feature_HasMatMulFP32Bit = 99,
  Feature_HasMatMulFP64Bit = 47,
  Feature_HasLS64Bit = 86,
  Feature_HasHBCBit = 11,
  Feature_HasRCPC3Bit = 87,
  Feature_HasGCSBit = 1,
  Feature_HasCPABit = 88,
  Feature_IsLEBit = 76,
  Feature_IsBEBit = 82,
  Feature_UseExperimentalZeroingPseudosBit = 39,
  Feature_UseAlternateSExtLoadCVTF32Bit = 81,
  Feature_UseScalarIncVLBit = 38,
  Feature_NoUseScalarIncVLBit = 95,
  Feature_HasFastIncVLBit = 96,
  Feature_UseSVEFPLD1RBit = 94,
  Feature_UseLDAPURBit = 93,
  Feature_AllowMisalignedMemAccessesBit = 97,
  Feature_UseWzrToVecMoveBit = 79,
  Feature_AllowUnpredicatedLdStLowerBit = 98,
  Feature_NotForCodeSizeBit = 80,
  Feature_UseSTRQroBit = 77,
  Feature_TailCallX16X17Bit = 72,
  Feature_TailCallX17Bit = 84,
  Feature_TailCallNotX16Bit = 85,
  Feature_TailCallAnyBit = 71,
  Feature_SLSBLRMitigationBit = 75,
  Feature_NoSLSBLRMitigationBit = 74,
  Feature_OptimizedGISelOrOtherSelectorBit = 73,
};

PredicateBitset AArch64InstructionSelector::
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const {
  PredicateBitset Features{};
  if (Subtarget->hasPAuth())
    Features.set(Feature_HasPAuthBit);
  if (Subtarget->hasJS())
    Features.set(Feature_HasJSBit);
  if (Subtarget->hasComplxNum())
    Features.set(Feature_HasComplxNumBit);
  if (Subtarget->hasRCPC_IMMO())
    Features.set(Feature_HasRCPC_IMMOBit);
  if (Subtarget->hasFPARMv8())
    Features.set(Feature_HasFPARMv8Bit);
  if (Subtarget->isNeonAvailable())
    Features.set(Feature_HasNEONBit);
  if (Subtarget->hasSM4())
    Features.set(Feature_HasSM4Bit);
  if (Subtarget->hasSHA3())
    Features.set(Feature_HasSHA3Bit);
  if (Subtarget->hasSHA2())
    Features.set(Feature_HasSHA2Bit);
  if (Subtarget->hasAES())
    Features.set(Feature_HasAESBit);
  if (Subtarget->hasDotProd())
    Features.set(Feature_HasDotProdBit);
  if (Subtarget->hasCRC())
    Features.set(Feature_HasCRCBit);
  if (Subtarget->hasCSSC())
    Features.set(Feature_HasCSSCBit);
  if (!Subtarget->hasCSSC())
    Features.set(Feature_HasNoCSSCBit);
  if (Subtarget->hasLSE())
    Features.set(Feature_HasLSEBit);
  if (!Subtarget->hasLSE())
    Features.set(Feature_HasNoLSEBit);
  if (Subtarget->hasRDM())
    Features.set(Feature_HasRDMBit);
  if (Subtarget->hasFullFP16())
    Features.set(Feature_HasFullFP16Bit);
  if (!Subtarget->hasFullFP16())
    Features.set(Feature_HasNoFullFP16Bit);
  if (Subtarget->hasFP16FML())
    Features.set(Feature_HasFP16FMLBit);
  if (Subtarget->hasFuseAES())
    Features.set(Feature_HasFuseAESBit);
  if (Subtarget->isSVEAvailable())
    Features.set(Feature_HasSVEBit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2())
    Features.set(Feature_HasSVE2Bit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVE2p1())
    Features.set(Feature_HasSVE2p1Bit);
  if (Subtarget->hasSVEAES())
    Features.set(Feature_HasSVEAESBit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVESM4())
    Features.set(Feature_HasSVESM4Bit);
  if (Subtarget->hasSVESHA3())
    Features.set(Feature_HasSVESHA3Bit);
  if (Subtarget->hasSVEBitPerm())
    Features.set(Feature_HasSVEBitPermBit);
  if (Subtarget->hasSME())
    Features.set(Feature_HasSMEandIsNonStreamingSafeBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME())
    Features.set(Feature_HasSMEBit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF64F64())
    Features.set(Feature_HasSMEF64F64Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF16F16())
    Features.set(Feature_HasSMEF16F16Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEI16I64())
    Features.set(Feature_HasSMEI16I64Bit);
  if (Subtarget->hasSME2())
    Features.set(Feature_HasSME2andIsNonStreamingSafeBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME2())
    Features.set(Feature_HasSME2Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSME2p1())
    Features.set(Feature_HasSME2p1Bit);
  if (Subtarget->hasFP8())
    Features.set(Feature_HasFP8Bit);
  if (Subtarget->hasFAMINMAX())
    Features.set(Feature_HasFAMINMAXBit);
  if (Subtarget->hasFP8FMA())
    Features.set(Feature_HasFP8FMABit);
  if (Subtarget->hasSSVE_FP8FMA() || (Subtarget->hasSVE2() && Subtarget->hasFP8FMA()))
    Features.set(Feature_HasSSVE_FP8FMABit);
  if (Subtarget->hasFP8DOT2())
    Features.set(Feature_HasFP8DOT2Bit);
  if (Subtarget->hasSSVE_FP8DOT2() || (Subtarget->hasSVE2() && Subtarget->hasFP8DOT2()))
    Features.set(Feature_HasSSVE_FP8DOT2Bit);
  if (Subtarget->hasFP8DOT4())
    Features.set(Feature_HasFP8DOT4Bit);
  if (Subtarget->hasSSVE_FP8DOT4() || (Subtarget->hasSVE2() && Subtarget->hasFP8DOT4()))
    Features.set(Feature_HasSSVE_FP8DOT4Bit);
  if (Subtarget->hasLUT())
    Features.set(Feature_HasLUTBit);
  if (Subtarget->isStreaming() && Subtarget->hasSME_LUTv2())
    Features.set(Feature_HasSME_LUTv2Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF8F16())
    Features.set(Feature_HasSMEF8F16Bit);
  if (Subtarget->isStreaming() && Subtarget->hasSMEF8F32())
    Features.set(Feature_HasSMEF8F32Bit);
  if ((Subtarget->isStreaming() && Subtarget->hasSME_MOP4()))
    Features.set(Feature_HasSME_MOP4Bit);
  if ((Subtarget->isStreaming() && Subtarget->hasSME_TMOP()))
    Features.set(Feature_HasSME_TMOPBit);
  if (Subtarget->hasCMPBR())
    Features.set(Feature_HasCMPBRBit);
  if (Subtarget->hasF8F32MM())
    Features.set(Feature_HasF8F32MMBit);
  if (Subtarget->hasF8F16MM())
    Features.set(Feature_HasF8F16MMBit);
  if (Subtarget->hasFPRCVT())
    Features.set(Feature_HasFPRCVTBit);
  if (Subtarget->hasLSFE())
    Features.set(Feature_HasLSFEBit);
  if (Subtarget->isSVEAvailable() && Subtarget->hasSVE_F16F32MM())
    Features.set(Feature_HasSVE_F16F32MMBit);
  if (Subtarget->isSVEorStreamingSVEAvailable())
    Features.set(Feature_HasSVE_or_SMEBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1()))
    Features.set(Feature_HasNonStreamingSVE_or_SME2p1Bit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNonStreamingSVE_or_SME2p2Bit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_AESBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_BitPermBit);
  if (Subtarget->isSVEAvailable() ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA()))
    Features.set(Feature_HasNonStreamingSVE_or_SSVE_FEXPABit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME()))
    Features.set(Feature_HasSVE2_or_SMEBit);
  if ((Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2()))
    Features.set(Feature_HasNonStreamingSVE2_or_SME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME()))
    Features.set(Feature_HasSVE2p1_or_SMEBit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2()))
    Features.set(Feature_HasSVE2p1_or_SME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2p1()))
    Features.set(Feature_HasSVE2p1_or_SME2p1Bit);
  if ((Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVE2p1()) ||(Subtarget->isStreaming() && Subtarget->hasSME2()))
    Features.set(Feature_HasSVE2p1_or_StreamingSME2Bit);
  if (Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2()))
    Features.set(Feature_HasSVE2p2_or_SME2p2Bit);
  if ((Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNonStreamingSVE2p2_or_SME2p2Bit);
  if (Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16()))
    Features.set(Feature_HasSMEF16F16_or_SMEF8F16Bit);
  if (Subtarget->hasNEON())
    Features.set(Feature_HasNEONandIsStreamingSafeBit);
  if (Subtarget->isNeonAvailable() || (Subtarget->hasNEON() && Subtarget->hasSME2p2()))
    Features.set(Feature_HasNEONandIsSME2p2StreamingSafeBit);
  if (Subtarget->hasRCPC())
    Features.set(Feature_HasRCPCBit);
  if (Subtarget->hasFRInt3264())
    Features.set(Feature_HasFRInt3264Bit);
  if (Subtarget->hasMTE())
    Features.set(Feature_HasMTEBit);
  if (Subtarget->hasMatMulInt8())
    Features.set(Feature_HasMatMulInt8Bit);
  if (Subtarget->hasMatMulFP32())
    Features.set(Feature_HasMatMulFP32Bit);
  if (Subtarget->hasMatMulFP64())
    Features.set(Feature_HasMatMulFP64Bit);
  if (Subtarget->hasLS64())
    Features.set(Feature_HasLS64Bit);
  if (Subtarget->hasHBC())
    Features.set(Feature_HasHBCBit);
  if (Subtarget->hasRCPC3())
    Features.set(Feature_HasRCPC3Bit);
  if (Subtarget->hasGCS())
    Features.set(Feature_HasGCSBit);
  if (Subtarget->hasCPA())
    Features.set(Feature_HasCPABit);
  if (Subtarget->isLittleEndian())
    Features.set(Feature_IsLEBit);
  if (!Subtarget->isLittleEndian())
    Features.set(Feature_IsBEBit);
  if (Subtarget->useExperimentalZeroingPseudos())
    Features.set(Feature_UseExperimentalZeroingPseudosBit);
  if (Subtarget->useAlternateSExtLoadCVTF32Pattern())
    Features.set(Feature_UseAlternateSExtLoadCVTF32Bit);
  if (Subtarget->useScalarIncVL())
    Features.set(Feature_UseScalarIncVLBit);
  if (!Subtarget->useScalarIncVL())
    Features.set(Feature_NoUseScalarIncVLBit);
  if (!Subtarget->hasDisableFastIncVL())
    Features.set(Feature_HasFastIncVLBit);
  if (!Subtarget->noSVEFPLD1R())
    Features.set(Feature_UseSVEFPLD1RBit);
  if (!Subtarget->avoidLDAPUR())
    Features.set(Feature_UseLDAPURBit);
  if (!Subtarget->requiresStrictAlign())
    Features.set(Feature_AllowMisalignedMemAccessesBit);
  if (Subtarget->useWzrToVecMove())
    Features.set(Feature_UseWzrToVecMoveBit);
  if (!Subtarget->disableUnpredicatedLdStLower())
    Features.set(Feature_AllowUnpredicatedLdStLowerBit);
  return Features;
}

void AArch64InstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AArch64Subtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset AArch64InstructionSelector::
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features{};
  if (!shouldOptForSize(MF))
    Features.set(Feature_NotForCodeSizeBit);
  if (!Subtarget->isSTRQroSlow() || shouldOptForSize(MF))
    Features.set(Feature_UseSTRQroBit);
  if (  MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallX16X17Bit);
  if ( MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallX17Bit);
  if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallNotX16Bit);
  if ( !MF->getInfo<AArch64FunctionInfo>()->branchTargetEnforcement() && !MF->getInfo<AArch64FunctionInfo>()->branchProtectionPAuthLR() )
    Features.set(Feature_TailCallAnyBit);
  if ( MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
    Features.set(Feature_SLSBLRMitigationBit);
  if ( !MF->getSubtarget<AArch64Subtarget>().hardenSlsBlr() )
    Features.set(Feature_NoSLSBLRMitigationBit);
  if (!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized())
    Features.set(Feature_OptimizedGISelOrOtherSelectorBit);
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HasAES,
  GIFBS_HasCPA,
  GIFBS_HasCRC,
  GIFBS_HasCSSC,
  GIFBS_HasDotProd,
  GIFBS_HasFP8,
  GIFBS_HasFP8DOT2,
  GIFBS_HasFP8DOT4,
  GIFBS_HasFP8FMA,
  GIFBS_HasFPARMv8,
  GIFBS_HasFPRCVT,
  GIFBS_HasFRInt3264,
  GIFBS_HasFullFP16,
  GIFBS_HasFuseAES,
  GIFBS_HasGCS,
  GIFBS_HasLSE,
  GIFBS_HasLSFE,
  GIFBS_HasLUT,
  GIFBS_HasMTE,
  GIFBS_HasMatMulInt8,
  GIFBS_HasNEON,
  GIFBS_HasNEONandIsSME2p2StreamingSafe,
  GIFBS_HasNEONandIsStreamingSafe,
  GIFBS_HasNoCSSC,
  GIFBS_HasNoFullFP16,
  GIFBS_HasNoLSE,
  GIFBS_HasNonStreamingSVE2p2_or_SME2p2,
  GIFBS_HasNonStreamingSVE_or_SME2p2,
  GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA,
  GIFBS_HasPAuth,
  GIFBS_HasRCPC,
  GIFBS_HasRCPC_IMMO,
  GIFBS_HasRDM,
  GIFBS_HasSHA2,
  GIFBS_HasSHA3,
  GIFBS_HasSM4,
  GIFBS_HasSME,
  GIFBS_HasSME2,
  GIFBS_HasSMEF16F16,
  GIFBS_HasSMEF64F64,
  GIFBS_HasSMEF8F16,
  GIFBS_HasSMEF8F32,
  GIFBS_HasSMEI16I64,
  GIFBS_HasSME_MOP4,
  GIFBS_HasSMEandIsNonStreamingSafe,
  GIFBS_HasSSVE_FP8DOT2,
  GIFBS_HasSSVE_FP8DOT4,
  GIFBS_HasSSVE_FP8FMA,
  GIFBS_HasSVE,
  GIFBS_HasSVE2,
  GIFBS_HasSVE2_or_SME,
  GIFBS_HasSVE2p1_or_SME,
  GIFBS_HasSVE2p1_or_SME2,
  GIFBS_HasSVE2p1_or_SME2p1,
  GIFBS_HasSVE2p2_or_SME2p2,
  GIFBS_HasSVESM4,
  GIFBS_HasSVE_F16F32MM,
  GIFBS_HasSVE_or_SME,
  GIFBS_IsBE,
  GIFBS_IsLE,
  GIFBS_OptimizedGISelOrOtherSelector,
  GIFBS_UseSTRQro,
  GIFBS_UseWzrToVecMove,
  GIFBS_HasComplxNum_HasNEON,
  GIFBS_HasF8F16MM_HasNEON,
  GIFBS_HasF8F16MM_HasSVE2,
  GIFBS_HasF8F32MM_HasNEON,
  GIFBS_HasF8F32MM_HasSVE2,
  GIFBS_HasFAMINMAX_HasNEON,
  GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasFP16FML_HasNEON,
  GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasFPARMv8_HasJS,
  GIFBS_HasFPRCVT_HasNEON,
  GIFBS_HasFullFP16_HasNEON,
  GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe,
  GIFBS_HasFullFP16_HasNEONandIsStreamingSafe,
  GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2,
  GIFBS_HasMatMulFP32_HasSVE,
  GIFBS_HasMatMulFP64_HasSVE,
  GIFBS_HasMatMulFP64_HasSVE_or_SME,
  GIFBS_HasMatMulInt8_HasSVE,
  GIFBS_HasMatMulInt8_HasSVE_or_SME,
  GIFBS_HasNEON_HasRCPC3,
  GIFBS_HasNEON_HasRDM,
  GIFBS_HasNonStreamingSVE_or_SME2p1_HasSVESHA3,
  GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES,
  GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm,
  GIFBS_HasRCPC_IMMO_UseLDAPUR,
  GIFBS_HasSMEF16F16_HasSME_MOP4,
  GIFBS_HasSMEF64F64_HasSME_MOP4,
  GIFBS_HasSMEF8F16_HasSME_MOP4,
  GIFBS_HasSMEF8F32_HasSME_MOP4,
  GIFBS_HasSMEI16I64_HasSME_MOP4,
  GIFBS_HasSVE_or_SME_IsLE,
  GIFBS_HasSVE_or_SME_UseScalarIncVL,
  GIFBS_IsLE_UseSTRQro,
  GIFBS_HasComplxNum_HasFullFP16_HasNEON,
  GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32,
  GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HasAESBit, },
  {Feature_HasCPABit, },
  {Feature_HasCRCBit, },
  {Feature_HasCSSCBit, },
  {Feature_HasDotProdBit, },
  {Feature_HasFP8Bit, },
  {Feature_HasFP8DOT2Bit, },
  {Feature_HasFP8DOT4Bit, },
  {Feature_HasFP8FMABit, },
  {Feature_HasFPARMv8Bit, },
  {Feature_HasFPRCVTBit, },
  {Feature_HasFRInt3264Bit, },
  {Feature_HasFullFP16Bit, },
  {Feature_HasFuseAESBit, },
  {Feature_HasGCSBit, },
  {Feature_HasLSEBit, },
  {Feature_HasLSFEBit, },
  {Feature_HasLUTBit, },
  {Feature_HasMTEBit, },
  {Feature_HasMatMulInt8Bit, },
  {Feature_HasNEONBit, },
  {Feature_HasNEONandIsSME2p2StreamingSafeBit, },
  {Feature_HasNEONandIsStreamingSafeBit, },
  {Feature_HasNoCSSCBit, },
  {Feature_HasNoFullFP16Bit, },
  {Feature_HasNoLSEBit, },
  {Feature_HasNonStreamingSVE2p2_or_SME2p2Bit, },
  {Feature_HasNonStreamingSVE_or_SME2p2Bit, },
  {Feature_HasNonStreamingSVE_or_SSVE_FEXPABit, },
  {Feature_HasPAuthBit, },
  {Feature_HasRCPCBit, },
  {Feature_HasRCPC_IMMOBit, },
  {Feature_HasRDMBit, },
  {Feature_HasSHA2Bit, },
  {Feature_HasSHA3Bit, },
  {Feature_HasSM4Bit, },
  {Feature_HasSMEBit, },
  {Feature_HasSME2Bit, },
  {Feature_HasSMEF16F16Bit, },
  {Feature_HasSMEF64F64Bit, },
  {Feature_HasSMEF8F16Bit, },
  {Feature_HasSMEF8F32Bit, },
  {Feature_HasSMEI16I64Bit, },
  {Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEandIsNonStreamingSafeBit, },
  {Feature_HasSSVE_FP8DOT2Bit, },
  {Feature_HasSSVE_FP8DOT4Bit, },
  {Feature_HasSSVE_FP8FMABit, },
  {Feature_HasSVEBit, },
  {Feature_HasSVE2Bit, },
  {Feature_HasSVE2_or_SMEBit, },
  {Feature_HasSVE2p1_or_SMEBit, },
  {Feature_HasSVE2p1_or_SME2Bit, },
  {Feature_HasSVE2p1_or_SME2p1Bit, },
  {Feature_HasSVE2p2_or_SME2p2Bit, },
  {Feature_HasSVESM4Bit, },
  {Feature_HasSVE_F16F32MMBit, },
  {Feature_HasSVE_or_SMEBit, },
  {Feature_IsBEBit, },
  {Feature_IsLEBit, },
  {Feature_OptimizedGISelOrOtherSelectorBit, },
  {Feature_UseSTRQroBit, },
  {Feature_UseWzrToVecMoveBit, },
  {Feature_HasComplxNumBit, Feature_HasNEONBit, },
  {Feature_HasF8F16MMBit, Feature_HasNEONBit, },
  {Feature_HasF8F16MMBit, Feature_HasSVE2Bit, },
  {Feature_HasF8F32MMBit, Feature_HasNEONBit, },
  {Feature_HasF8F32MMBit, Feature_HasSVE2Bit, },
  {Feature_HasFAMINMAXBit, Feature_HasNEONBit, },
  {Feature_HasFAMINMAXBit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasFP16FMLBit, Feature_HasNEONBit, },
  {Feature_HasFP8Bit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasFPARMv8Bit, Feature_HasJSBit, },
  {Feature_HasFPRCVTBit, Feature_HasNEONBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONandIsSME2p2StreamingSafeBit, },
  {Feature_HasFullFP16Bit, Feature_HasNEONandIsStreamingSafeBit, },
  {Feature_HasLUTBit, Feature_HasNonStreamingSVE2_or_SME2Bit, },
  {Feature_HasMatMulFP32Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulFP64Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulFP64Bit, Feature_HasSVE_or_SMEBit, },
  {Feature_HasMatMulInt8Bit, Feature_HasSVEBit, },
  {Feature_HasMatMulInt8Bit, Feature_HasSVE_or_SMEBit, },
  {Feature_HasNEONBit, Feature_HasRCPC3Bit, },
  {Feature_HasNEONBit, Feature_HasRDMBit, },
  {Feature_HasNonStreamingSVE_or_SME2p1Bit, Feature_HasSVESHA3Bit, },
  {Feature_HasNonStreamingSVE_or_SSVE_AESBit, Feature_HasSVEAESBit, },
  {Feature_HasNonStreamingSVE_or_SSVE_BitPermBit, Feature_HasSVEBitPermBit, },
  {Feature_HasRCPC_IMMOBit, Feature_UseLDAPURBit, },
  {Feature_HasSMEF16F16Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF64F64Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF8F16Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEF8F32Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSMEI16I64Bit, Feature_HasSME_MOP4Bit, },
  {Feature_HasSVE_or_SMEBit, Feature_IsLEBit, },
  {Feature_HasSVE_or_SMEBit, Feature_UseScalarIncVLBit, },
  {Feature_IsLEBit, Feature_UseSTRQroBit, },
  {Feature_HasComplxNumBit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
  {Feature_HasNEONBit, Feature_NotForCodeSizeBit, Feature_UseAlternateSExtLoadCVTF32Bit, },
  {Feature_AllowMisalignedMemAccessesBit, Feature_AllowUnpredicatedLdStLowerBit, Feature_HasSVE_or_SMEBit, Feature_IsLEBit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
  GICP_gi_addsub_shifted_imm32,
  GICP_gi_addsub_shifted_imm64,
  GICP_gi_am_indexed128,
  GICP_gi_am_indexed16,
  GICP_gi_am_indexed32,
  GICP_gi_am_indexed64,
  GICP_gi_am_indexed8,
  GICP_gi_am_unscaled128,
  GICP_gi_am_unscaled16,
  GICP_gi_am_unscaled32,
  GICP_gi_am_unscaled64,
  GICP_gi_am_unscaled8,
  GICP_gi_arith_extended_reg32_i32,
  GICP_gi_arith_extended_reg32_i64,
  GICP_gi_arith_extended_reg32to64_i64,
  GICP_gi_arith_shifted_reg32,
  GICP_gi_arith_shifted_reg64,
  GICP_gi_extract_high_v16i8,
  GICP_gi_extract_high_v4f32,
  GICP_gi_extract_high_v4i32,
  GICP_gi_extract_high_v8f16,
  GICP_gi_extract_high_v8i16,
  GICP_gi_logical_shifted_reg32,
  GICP_gi_logical_shifted_reg64,
  GICP_gi_neg_addsub_shifted_imm32,
  GICP_gi_neg_addsub_shifted_imm64,
  GICP_gi_ro_Windexed128,
  GICP_gi_ro_Windexed16,
  GICP_gi_ro_Windexed32,
  GICP_gi_ro_Windexed64,
  GICP_gi_ro_Windexed8,
  GICP_gi_ro_Xindexed128,
  GICP_gi_ro_Xindexed16,
  GICP_gi_ro_Xindexed32,
  GICP_gi_ro_Xindexed64,
  GICP_gi_ro_Xindexed8,
};
// See constructor for table contents

AArch64InstructionSelector::ComplexMatcherMemFn
AArch64InstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm32
  &AArch64InstructionSelector::selectArithImmed, // gi_addsub_shifted_imm64
  &AArch64InstructionSelector::selectAddrModeIndexed<128>, // gi_am_indexed128
  &AArch64InstructionSelector::selectAddrModeIndexed<16>, // gi_am_indexed16
  &AArch64InstructionSelector::selectAddrModeIndexed<32>, // gi_am_indexed32
  &AArch64InstructionSelector::selectAddrModeIndexed<64>, // gi_am_indexed64
  &AArch64InstructionSelector::selectAddrModeIndexed<8>, // gi_am_indexed8
  &AArch64InstructionSelector::selectAddrModeUnscaled128, // gi_am_unscaled128
  &AArch64InstructionSelector::selectAddrModeUnscaled16, // gi_am_unscaled16
  &AArch64InstructionSelector::selectAddrModeUnscaled32, // gi_am_unscaled32
  &AArch64InstructionSelector::selectAddrModeUnscaled64, // gi_am_unscaled64
  &AArch64InstructionSelector::selectAddrModeUnscaled8, // gi_am_unscaled8
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i32
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32_i64
  &AArch64InstructionSelector::selectArithExtendedRegister, // gi_arith_extended_reg32to64_i64
  &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg32
  &AArch64InstructionSelector::selectArithShiftedRegister, // gi_arith_shifted_reg64
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v16i8
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4f32
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v4i32
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8f16
  &AArch64InstructionSelector::selectExtractHigh, // gi_extract_high_v8i16
  &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg32
  &AArch64InstructionSelector::selectLogicalShiftedRegister, // gi_logical_shifted_reg64
  &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm32
  &AArch64InstructionSelector::selectNegArithImmed, // gi_neg_addsub_shifted_imm64
  &AArch64InstructionSelector::selectAddrModeWRO<128>, // gi_ro_Windexed128
  &AArch64InstructionSelector::selectAddrModeWRO<16>, // gi_ro_Windexed16
  &AArch64InstructionSelector::selectAddrModeWRO<32>, // gi_ro_Windexed32
  &AArch64InstructionSelector::selectAddrModeWRO<64>, // gi_ro_Windexed64
  &AArch64InstructionSelector::selectAddrModeWRO<8>, // gi_ro_Windexed8
  &AArch64InstructionSelector::selectAddrModeXRO<128>, // gi_ro_Xindexed128
  &AArch64InstructionSelector::selectAddrModeXRO<16>, // gi_ro_Xindexed16
  &AArch64InstructionSelector::selectAddrModeXRO<32>, // gi_ro_Xindexed32
  &AArch64InstructionSelector::selectAddrModeXRO<64>, // gi_ro_Xindexed64
  &AArch64InstructionSelector::selectAddrModeXRO<8>, // gi_ro_Xindexed8
};

// PatFrag predicates.
enum {
  GICXXPred_MI_Predicate_add_and_or_is_add = GICXXPred_Invalid + 1,
  GICXXPred_MI_Predicate_ldaxr_1,
  GICXXPred_MI_Predicate_ldaxr_2,
  GICXXPred_MI_Predicate_ldaxr_4,
  GICXXPred_MI_Predicate_ldaxr_8,
  GICXXPred_MI_Predicate_ldxr_1,
  GICXXPred_MI_Predicate_ldxr_2,
  GICXXPred_MI_Predicate_ldxr_4,
  GICXXPred_MI_Predicate_ldxr_8,
  GICXXPred_MI_Predicate_or_disjoint,
  GICXXPred_MI_Predicate_stlxr_1,
  GICXXPred_MI_Predicate_stlxr_2,
  GICXXPred_MI_Predicate_stlxr_4,
  GICXXPred_MI_Predicate_stlxr_8,
  GICXXPred_MI_Predicate_stxr_1,
  GICXXPred_MI_Predicate_stxr_2,
  GICXXPred_MI_Predicate_stxr_4,
  GICXXPred_MI_Predicate_stxr_8,
  GICXXPred_MI_Predicate_trunc_isWorthFoldingALU,
};
bool AArch64InstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  switch (PredicateID) {
  case GICXXPred_MI_Predicate_add_and_or_is_add: {
    
         return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));
      
  }
  case GICXXPred_MI_Predicate_ldaxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_ldaxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_ldaxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_ldaxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_ldxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_ldxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_ldxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_ldxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_or_disjoint: {
    
        return MI.getFlag(MachineInstr::Disjoint);
      
  }
  case GICXXPred_MI_Predicate_stlxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_stlxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_stlxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_stlxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_stxr_1: {
     return isLoadStoreOfNumBytes(MI, 1); 
  }
  case GICXXPred_MI_Predicate_stxr_2: {
     return isLoadStoreOfNumBytes(MI, 2); 
  }
  case GICXXPred_MI_Predicate_stxr_4: {
     return isLoadStoreOfNumBytes(MI, 4); 
  }
  case GICXXPred_MI_Predicate_stxr_8: {
     return isLoadStoreOfNumBytes(MI, 8); 
  }
  case GICXXPred_MI_Predicate_trunc_isWorthFoldingALU: {
     return isWorthFoldingIntoExtendedReg(MI, MRI, false); 
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_MO_Predicate_top16Zero = GICXXPred_Invalid + 1,
  GICXXPred_MO_Predicate_top32Zero,
  GICXXPred_MO_Predicate_topbitsallzero32,
  GICXXPred_MO_Predicate_topbitsallzero64,
};
bool AArch64InstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
  const auto &Operands = State.RecordedOperands;
  Register Reg = MO.getReg();
  (void)Operands;
  (void)Reg;
  switch (PredicateID) {
  case GICXXPred_MO_Predicate_top16Zero: {
    
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16)); 
  }
  case GICXXPred_MO_Predicate_top32Zero: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32)); 
  }
  case GICXXPred_MO_Predicate_topbitsallzero32: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31)); 
  }
  case GICXXPred_MO_Predicate_topbitsallzero64: {
     
        return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63)); 
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_VectorIndex0 = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_VectorIndex0_timm,
  GICXXPred_I64_Predicate_VectorIndex1,
  GICXXPred_I64_Predicate_VectorIndex1_timm,
  GICXXPred_I64_Predicate_VectorIndex032b,
  GICXXPred_I64_Predicate_VectorIndex032b_timm,
  GICXXPred_I64_Predicate_VectorIndex132b,
  GICXXPred_I64_Predicate_VectorIndex132b_timm,
  GICXXPred_I64_Predicate_VectorIndexB,
  GICXXPred_I64_Predicate_VectorIndexB32b,
  GICXXPred_I64_Predicate_VectorIndexB32b_timm,
  GICXXPred_I64_Predicate_VectorIndexB_timm,
  GICXXPred_I64_Predicate_VectorIndexD,
  GICXXPred_I64_Predicate_VectorIndexD32b,
  GICXXPred_I64_Predicate_VectorIndexD32b_timm,
  GICXXPred_I64_Predicate_VectorIndexD_timm,
  GICXXPred_I64_Predicate_VectorIndexH,
  GICXXPred_I64_Predicate_VectorIndexH32b,
  GICXXPred_I64_Predicate_VectorIndexH32b_timm,
  GICXXPred_I64_Predicate_VectorIndexH_timm,
  GICXXPred_I64_Predicate_VectorIndexS,
  GICXXPred_I64_Predicate_VectorIndexS32b,
  GICXXPred_I64_Predicate_VectorIndexS32b_timm,
  GICXXPred_I64_Predicate_VectorIndexS_timm,
  GICXXPred_I64_Predicate_complexrotateop,
  GICXXPred_I64_Predicate_complexrotateopodd,
  GICXXPred_I64_Predicate_extq_timm32_0_1m8,
  GICXXPred_I64_Predicate_extq_timm32_0_3m4,
  GICXXPred_I64_Predicate_extq_timm32_0_7m2,
  GICXXPred_I64_Predicate_i64imm_32bit,
  GICXXPred_I64_Predicate_i64imm_32bit_tgt,
  GICXXPred_I64_Predicate_imm0_1,
  GICXXPred_I64_Predicate_imm0_3,
  GICXXPred_I64_Predicate_imm0_7,
  GICXXPred_I64_Predicate_imm0_15,
  GICXXPred_I64_Predicate_imm0_31,
  GICXXPred_I64_Predicate_imm0_63,
  GICXXPred_I64_Predicate_imm0_127,
  GICXXPred_I64_Predicate_imm0_127_64b,
  GICXXPred_I64_Predicate_imm0_255,
  GICXXPred_I64_Predicate_imm32_0_7,
  GICXXPred_I64_Predicate_imm32_0_15,
  GICXXPred_I64_Predicate_imm32_0_31,
  GICXXPred_I64_Predicate_imm64_0_65535,
  GICXXPred_I64_Predicate_maski8_or_more,
  GICXXPred_I64_Predicate_maski16_or_more,
  GICXXPred_I64_Predicate_rprfop,
  GICXXPred_I64_Predicate_s64imm_32bit,
  GICXXPred_I64_Predicate_simm4s1,
  GICXXPred_I64_Predicate_simm4s2,
  GICXXPred_I64_Predicate_simm4s3,
  GICXXPred_I64_Predicate_simm4s4,
  GICXXPred_I64_Predicate_simm4s16,
  GICXXPred_I64_Predicate_simm4s32,
  GICXXPred_I64_Predicate_simm5_8b,
  GICXXPred_I64_Predicate_simm5_8b_tgt,
  GICXXPred_I64_Predicate_simm5_16b,
  GICXXPred_I64_Predicate_simm5_16b_tgt,
  GICXXPred_I64_Predicate_simm5_32b,
  GICXXPred_I64_Predicate_simm5_32b_tgt,
  GICXXPred_I64_Predicate_simm5_64b,
  GICXXPred_I64_Predicate_simm5_64b_tgt,
  GICXXPred_I64_Predicate_simm6_32b,
  GICXXPred_I64_Predicate_simm6s1,
  GICXXPred_I64_Predicate_simm8_32b,
  GICXXPred_I64_Predicate_simm8_64b,
  GICXXPred_I64_Predicate_simm9,
  GICXXPred_I64_Predicate_sme_elm_idx0_0,
  GICXXPred_I64_Predicate_sme_elm_idx0_1,
  GICXXPred_I64_Predicate_sme_elm_idx0_3,
  GICXXPred_I64_Predicate_sme_elm_idx0_7,
  GICXXPred_I64_Predicate_sme_elm_idx0_15,
  GICXXPred_I64_Predicate_svcr_op,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_b,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_d,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_h,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_q,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_s,
  GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm,
  GICXXPred_I64_Predicate_sve_incdec_imm,
  GICXXPred_I64_Predicate_sve_pred_enum,
  GICXXPred_I64_Predicate_sve_prfop,
  GICXXPred_I64_Predicate_sve_vec_len_specifier_enum,
  GICXXPred_I64_Predicate_tbz_imm0_31_diag,
  GICXXPred_I64_Predicate_tbz_imm0_31_nodiag,
  GICXXPred_I64_Predicate_tbz_imm32_63,
  GICXXPred_I64_Predicate_timm0_1,
  GICXXPred_I64_Predicate_timm0_31,
  GICXXPred_I64_Predicate_timm0_63,
  GICXXPred_I64_Predicate_timm32_0_0,
  GICXXPred_I64_Predicate_timm32_0_1,
  GICXXPred_I64_Predicate_timm32_0_3,
  GICXXPred_I64_Predicate_timm32_0_7,
  GICXXPred_I64_Predicate_timm32_0_15,
  GICXXPred_I64_Predicate_timm32_0_31,
  GICXXPred_I64_Predicate_timm32_0_255,
  GICXXPred_I64_Predicate_timm32_0_65535,
  GICXXPred_I64_Predicate_timm32_1_1,
  GICXXPred_I64_Predicate_timm32_1_3,
  GICXXPred_I64_Predicate_timm32_1_7,
  GICXXPred_I64_Predicate_timm64_0_65535,
  GICXXPred_I64_Predicate_ubsan_trap_imm,
  GICXXPred_I64_Predicate_uimm0s2range,
  GICXXPred_I64_Predicate_uimm0s4range,
  GICXXPred_I64_Predicate_uimm1s2range,
  GICXXPred_I64_Predicate_uimm1s4range,
  GICXXPred_I64_Predicate_uimm2s2range,
  GICXXPred_I64_Predicate_uimm2s4range,
  GICXXPred_I64_Predicate_uimm3s2range,
  GICXXPred_I64_Predicate_uimm3s8,
  GICXXPred_I64_Predicate_uimm5s2,
  GICXXPred_I64_Predicate_uimm5s4,
  GICXXPred_I64_Predicate_uimm5s8,
  GICXXPred_I64_Predicate_uimm6,
  GICXXPred_I64_Predicate_uimm6_32b,
  GICXXPred_I64_Predicate_uimm6_64b,
  GICXXPred_I64_Predicate_uimm6s1,
  GICXXPred_I64_Predicate_uimm6s2,
  GICXXPred_I64_Predicate_uimm6s4,
  GICXXPred_I64_Predicate_uimm6s8,
  GICXXPred_I64_Predicate_uimm6s16,
  GICXXPred_I64_Predicate_uimm8_32b,
  GICXXPred_I64_Predicate_uimm8_64b,
  GICXXPred_I64_Predicate_uimm16,
  GICXXPred_I64_Predicate_vecshiftL8,
  GICXXPred_I64_Predicate_vecshiftL16,
  GICXXPred_I64_Predicate_vecshiftL32,
  GICXXPred_I64_Predicate_vecshiftL64,
  GICXXPred_I64_Predicate_vecshiftR8,
  GICXXPred_I64_Predicate_vecshiftR16,
  GICXXPred_I64_Predicate_vecshiftR16Narrow,
  GICXXPred_I64_Predicate_vecshiftR32,
  GICXXPred_I64_Predicate_vecshiftR32Narrow,
  GICXXPred_I64_Predicate_vecshiftR64,
  GICXXPred_I64_Predicate_vecshiftR64Narrow,
};
bool AArch64InstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_VectorIndex0: {
     return ((uint64_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex0_timm: {
     return ((uint64_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex1: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex1_timm: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex032b: {
     return ((uint32_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex032b_timm: {
     return ((uint32_t)Imm) == 0; 
  }
  case GICXXPred_I64_Predicate_VectorIndex132b: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndex132b_timm: {
     return ((uint64_t)Imm) == 1; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB32b: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB32b_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexB_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD32b: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD32b_timm: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexD_timm: {
     return ((uint64_t)Imm) < 2; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH32b: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH32b_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexH_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS32b: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS32b_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_VectorIndexS_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_complexrotateop: {
     return Imm >= 0 && Imm <= 270;  
  }
  case GICXXPred_I64_Predicate_complexrotateopodd: {
     return Imm >= 0 && Imm <= 270;  
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_1m8: {
    
      return ((uint32_t)Imm) < 2;
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_3m4: {
    
      return ((uint32_t)Imm) < 4;
  }
  case GICXXPred_I64_Predicate_extq_timm32_0_7m2: {
    
      return ((uint32_t)Imm) < 8;
  }
  case GICXXPred_I64_Predicate_i64imm_32bit: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  case GICXXPred_I64_Predicate_i64imm_32bit_tgt: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  case GICXXPred_I64_Predicate_imm0_1: {
    
      return ((uint64_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_imm0_3: {
    
      return ((uint64_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_imm0_7: {
    
      return ((uint64_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_imm0_15: {
    
      return ((uint64_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_imm0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_imm0_63: {
    
      return ((uint64_t)Imm) < 64;
    
  }
  case GICXXPred_I64_Predicate_imm0_127: {
    
      return ((uint32_t)Imm) < 128;
    
  }
  case GICXXPred_I64_Predicate_imm0_127_64b: {
    
      return ((uint64_t)Imm) < 128;
    
  }
  case GICXXPred_I64_Predicate_imm0_255: {
    
      return ((uint32_t)Imm) < 256;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_7: {
    
      return ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_15: {
    
      return ((uint32_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_imm32_0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_imm64_0_65535: {
    
      return ((uint64_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_maski8_or_more: {
     return (Imm & 0xff) == 0xff; 
  }
  case GICXXPred_I64_Predicate_maski16_or_more: {
     return (Imm & 0xffff) == 0xffff; 
  }
  case GICXXPred_I64_Predicate_rprfop: {
    
        return (((uint32_t)Imm) <= 63);
      
  }
  case GICXXPred_I64_Predicate_s64imm_32bit: {
    
      int64_t Imm64 = static_cast<int64_t>(Imm);
      return Imm64 >= std::numeric_limits<int32_t>::min() &&
             Imm64 <= std::numeric_limits<int32_t>::max();
    
    llvm_unreachable("s64imm_32bit should have returned");
  }
  case GICXXPred_I64_Predicate_simm4s1: {
     return Imm >=-8  && Imm <= 7; 
  }
  case GICXXPred_I64_Predicate_simm4s2: {
     return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s3: {
     return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s4: {
     return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s16: {
     return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm4s32: {
     return Imm >=-256  && Imm <= 224 && (Imm % 32) == 0x0; 
  }
  case GICXXPred_I64_Predicate_simm5_8b: {
     return (int8_t)Imm >= -16 && (int8_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_8b_tgt: {
     return (int8_t)Imm >= -16 && (int8_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_16b: {
     return (int16_t)Imm >= -16 && (int16_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_16b_tgt: {
     return (int16_t)Imm >= -16 && (int16_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_32b: {
     return Imm >= -16 && Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_32b_tgt: {
     return (int32_t)Imm >= -16 && (int32_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_64b: {
     return Imm >= -16 && Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm5_64b_tgt: {
     return (int64_t)Imm >= -16 && (int64_t)Imm < 16; 
  }
  case GICXXPred_I64_Predicate_simm6_32b: {
     return Imm >= -32 && Imm < 32; 
  }
  case GICXXPred_I64_Predicate_simm6s1: {
     return Imm >= -32 && Imm < 32; 
  }
  case GICXXPred_I64_Predicate_simm8_32b: {
     return Imm >= -128 && Imm < 128; 
  }
  case GICXXPred_I64_Predicate_simm8_64b: {
     return Imm >= -128 && Imm < 128; 
  }
  case GICXXPred_I64_Predicate_simm9: {
     return Imm >= -256 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_0: {
    
      return ((uint32_t)Imm) == 0;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_1: {
    
      return ((uint32_t)Imm) <= 1;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_3: {
    
      return ((uint32_t)Imm) <= 3;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_7: {
    
      return ((uint32_t)Imm) <= 7;
    
  }
  case GICXXPred_I64_Predicate_sme_elm_idx0_15: {
    
      return ((uint32_t)Imm) <= 15;
    
  }
  case GICXXPred_I64_Predicate_svcr_op: {
    
        return AArch64SVCR::lookupSVCRByEncoding(Imm) != nullptr;
      
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b: {
     return ((uint64_t)Imm) < 64; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_b_timm: {
     return ((uint64_t)Imm) < 64; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_d_timm: {
     return ((uint64_t)Imm) < 8; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h: {
     return ((uint64_t)Imm) < 32; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_h_timm: {
     return ((uint64_t)Imm) < 32; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_q_timm: {
     return ((uint64_t)Imm) < 4; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_sve_elm_idx_extdup_s_timm: {
     return ((uint64_t)Imm) < 16; 
  }
  case GICXXPred_I64_Predicate_sve_incdec_imm: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_sve_pred_enum: {
    
      return (((uint32_t)Imm) < 32);
      
  }
  case GICXXPred_I64_Predicate_sve_prfop: {
    
        return (((uint32_t)Imm) <= 15);
      
  }
  case GICXXPred_I64_Predicate_sve_vec_len_specifier_enum: {
    
      return (((uint32_t)Imm) < 2);
      
  }
  case GICXXPred_I64_Predicate_tbz_imm0_31_diag: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_tbz_imm0_31_nodiag: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_tbz_imm32_63: {
    
      return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
    
  }
  case GICXXPred_I64_Predicate_timm0_1: {
    
      return ((uint64_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_timm0_31: {
    
      return ((uint64_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_timm0_63: {
    
      return ((uint64_t)Imm) < 64;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_0: {
    
      return ((uint32_t)Imm) == 0;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_1: {
    
      return ((uint32_t)Imm) < 2;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_3: {
    
      return ((uint32_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_7: {
    
      return ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_15: {
    
      return ((uint32_t)Imm) < 16;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_31: {
    
      return ((uint32_t)Imm) < 32;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_255: {
    
      return ((uint32_t)Imm) < 256;
    
  }
  case GICXXPred_I64_Predicate_timm32_0_65535: {
    
      return ((uint32_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_1: {
    
        return ((uint32_t)Imm) == 1;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_3: {
    
      return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 4;
    
  }
  case GICXXPred_I64_Predicate_timm32_1_7: {
    
      return ((uint32_t)Imm) > 0 && ((uint32_t)Imm) < 8;
    
  }
  case GICXXPred_I64_Predicate_timm64_0_65535: {
    
      return ((uint64_t)Imm) < 65536;
    
  }
  case GICXXPred_I64_Predicate_ubsan_trap_imm: {
    
      return isUInt<8>(Imm);
    
  }
  case GICXXPred_I64_Predicate_uimm0s2range: {
     return Imm == 0; 
  }
  case GICXXPred_I64_Predicate_uimm0s4range: {
     return Imm == 0; 
  }
  case GICXXPred_I64_Predicate_uimm1s2range: {
     return Imm >= 0 && Imm <= 2 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm1s4range: {
     return Imm >= 0 && Imm <= 4 && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm2s2range: {
     return Imm >= 0 && Imm <= 6 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm2s4range: {
     return Imm >= 0 && Imm <= 12 && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm3s2range: {
     return Imm >= 0 && Imm <= 14 && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm3s8: {
     return Imm >= 0 && Imm <= 56 && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s2: {
     return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s4: {
     return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm5s8: {
     return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6_32b: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6_64b: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6s1: {
     return Imm >= 0 && Imm < 64; 
  }
  case GICXXPred_I64_Predicate_uimm6s2: {
     return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s4: {
     return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s8: {
     return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm6s16: {
     return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); 
  }
  case GICXXPred_I64_Predicate_uimm8_32b: {
     return Imm >= 0 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_uimm8_64b: {
     return Imm >= 0 && Imm < 256; 
  }
  case GICXXPred_I64_Predicate_uimm16: {
    return Imm >= 0 && Imm < 65536;
  }
  case GICXXPred_I64_Predicate_vecshiftL8: {
    
      return (((uint32_t)Imm) < 8);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL16: {
    
      return (((uint32_t)Imm) < 16);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL32: {
    
      return (((uint32_t)Imm) < 32);
    
  }
  case GICXXPred_I64_Predicate_vecshiftL64: {
    
      return (((uint32_t)Imm) < 64);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR8: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR16: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR16Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR32: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR32Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR64: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
    
  }
  case GICXXPred_I64_Predicate_vecshiftR64Narrow: {
    
      return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APFloat_Predicate_fpimm0 = GICXXPred_Invalid + 1,
  GICXXPred_APFloat_Predicate_fpimm16,
  GICXXPred_APFloat_Predicate_fpimm32,
  GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4,
  GICXXPred_APFloat_Predicate_fpimm64,
  GICXXPred_APFloat_Predicate_fpimm_half,
  GICXXPred_APFloat_Predicate_fpimm_minus0,
  GICXXPred_APFloat_Predicate_fpimm_one,
  GICXXPred_APFloat_Predicate_fpimm_two,
  GICXXPred_APFloat_Predicate_fpimmbf16,
  GICXXPred_APFloat_Predicate_simdimmtype10,
};
bool AArch64InstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APFloat_Predicate_fpimm0: {
    
      return Imm.isExactlyValue(+0.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm16: {
    
          return AArch64_AM::getFP16Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm32: {
    
          return AArch64_AM::getFP32Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4: {
    
          uint64_t Enc = Imm.bitcastToAPInt().getZExtValue();
          return Enc != 0 && AArch64_AM::isAdvSIMDModImmType4(Enc << 32 | Enc);
        
    llvm_unreachable("fpimm32SIMDModImmType4 should have returned");
  }
  case GICXXPred_APFloat_Predicate_fpimm64: {
    
          return AArch64_AM::getFP64Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_fpimm_half: {
    
      return Imm.isExactlyValue(+0.5);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_minus0: {
    
      return Imm.isExactlyValue(-0.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_one: {
    
      return Imm.isExactlyValue(+1.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_two: {
    
      return Imm.isExactlyValue(+2.0);
    
  }
  case GICXXPred_APFloat_Predicate_fpimmbf16: {
    
          return AArch64_AM::getFP16Imm(Imm) != -1;
        
  }
  case GICXXPred_APFloat_Predicate_simdimmtype10: {
    
          return AArch64_AM::isAdvSIMDModImmType10(
                     Imm.bitcastToAPInt().getZExtValue());
        
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APInt_Predicate_logical_imm32 = GICXXPred_Invalid + 1,
  GICXXPred_APInt_Predicate_logical_imm64,
};
bool AArch64InstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APInt_Predicate_logical_imm32: {
    
      return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
    
  }
  case GICXXPred_APInt_Predicate_logical_imm64: {
    
      return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool AArch64InstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("AArch64InstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
  GICR_renderFPImm16,
  GICR_renderFPImm32,
  GICR_renderFPImm32SIMDModImmType4,
  GICR_renderFPImm64,
  GICR_renderLogicalImm32,
  GICR_renderLogicalImm64,
  GICR_renderTruncImm,
  GICR_renderUbsanTrap,
};
AArch64InstructionSelector::CustomRendererFn
AArch64InstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
  &AArch64InstructionSelector::renderFPImm16,
  &AArch64InstructionSelector::renderFPImm32,
  &AArch64InstructionSelector::renderFPImm32SIMDModImmType4,
  &AArch64InstructionSelector::renderFPImm64,
  &AArch64InstructionSelector::renderLogicalImm32,
  &AArch64InstructionSelector::renderLogicalImm64,
  &AArch64InstructionSelector::renderTruncImm,
  &AArch64InstructionSelector::renderUbsanTrap,
};

bool AArch64InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

bool AArch64InstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("AArch64InstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24),  uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
#else
#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32),  uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#endif
const uint8_t *AArch64InstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
     /*      0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(938), /*)*//*default:*//*Label 173*/ GIMT_Encode4(473721),
     /*     10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(3542),
     /*     14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(40445),
     /*     18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(55430),
     /*     22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(58195),
     /*     26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(58277), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*     46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(58359),
     /*     50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(66569),
     /*     54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(92012),
     /*     58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(106466),
     /*     62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(106710),
     /*     66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(106954),
     /*     70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(107198),
     /*     74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(107442),
     /*     78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(107686), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(107930), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(118544), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(136477),
     /*    162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(136968),
     /*    166 */ /*TargetOpcode::G_INTRINSIC_LRINT*//*Label 18*/ GIMT_Encode4(137459),
     /*    170 */ /*TargetOpcode::G_INTRINSIC_LLRINT*//*Label 19*/ GIMT_Encode4(137979),
     /*    174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 20*/ GIMT_Encode4(138272),
     /*    178 */ /*TargetOpcode::G_READCYCLECOUNTER*//*Label 21*/ GIMT_Encode4(138763), GIMT_Encode4(0),
     /*    186 */ /*TargetOpcode::G_LOAD*//*Label 22*/ GIMT_Encode4(138796),
     /*    190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 23*/ GIMT_Encode4(147614),
     /*    194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 24*/ GIMT_Encode4(148664), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    210 */ /*TargetOpcode::G_STORE*//*Label 25*/ GIMT_Encode4(151713), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    222 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 26*/ GIMT_Encode4(165539),
     /*    226 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 27*/ GIMT_Encode4(166890),
     /*    230 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 28*/ GIMT_Encode4(167882),
     /*    234 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 29*/ GIMT_Encode4(168874),
     /*    238 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 30*/ GIMT_Encode4(170366), GIMT_Encode4(0),
     /*    246 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 31*/ GIMT_Encode4(171858),
     /*    250 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 32*/ GIMT_Encode4(172850),
     /*    254 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 33*/ GIMT_Encode4(173842),
     /*    258 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 34*/ GIMT_Encode4(174834),
     /*    262 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 35*/ GIMT_Encode4(175826),
     /*    266 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 36*/ GIMT_Encode4(176818),
     /*    270 */ /*TargetOpcode::G_ATOMICRMW_FADD*//*Label 37*/ GIMT_Encode4(177810), GIMT_Encode4(0),
     /*    278 */ /*TargetOpcode::G_ATOMICRMW_FMAX*//*Label 38*/ GIMT_Encode4(178515),
     /*    282 */ /*TargetOpcode::G_ATOMICRMW_FMIN*//*Label 39*/ GIMT_Encode4(179220),
     /*    286 */ /*TargetOpcode::G_ATOMICRMW_FMAXIMUM*//*Label 40*/ GIMT_Encode4(179925),
     /*    290 */ /*TargetOpcode::G_ATOMICRMW_FMINIMUM*//*Label 41*/ GIMT_Encode4(180630), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    310 */ /*TargetOpcode::G_FENCE*//*Label 42*/ GIMT_Encode4(181335), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    330 */ /*TargetOpcode::G_INTRINSIC*//*Label 43*/ GIMT_Encode4(181386),
     /*    334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 44*/ GIMT_Encode4(288979), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    346 */ /*TargetOpcode::G_ANYEXT*//*Label 45*/ GIMT_Encode4(300475),
     /*    350 */ /*TargetOpcode::G_TRUNC*//*Label 46*/ GIMT_Encode4(300765),
     /*    354 */ /*TargetOpcode::G_TRUNC_SSAT_S*//*Label 47*/ GIMT_Encode4(302184),
     /*    358 */ /*TargetOpcode::G_TRUNC_SSAT_U*//*Label 48*/ GIMT_Encode4(302615),
     /*    362 */ /*TargetOpcode::G_TRUNC_USAT_U*//*Label 49*/ GIMT_Encode4(303046),
     /*    366 */ /*TargetOpcode::G_CONSTANT*//*Label 50*/ GIMT_Encode4(303477),
     /*    370 */ /*TargetOpcode::G_FCONSTANT*//*Label 51*/ GIMT_Encode4(303597), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    382 */ /*TargetOpcode::G_SEXT*//*Label 52*/ GIMT_Encode4(303838),
     /*    386 */ /*TargetOpcode::G_SEXT_INREG*//*Label 53*/ GIMT_Encode4(305736),
     /*    390 */ /*TargetOpcode::G_ZEXT*//*Label 54*/ GIMT_Encode4(307390),
     /*    394 */ /*TargetOpcode::G_SHL*//*Label 55*/ GIMT_Encode4(310073),
     /*    398 */ /*TargetOpcode::G_LSHR*//*Label 56*/ GIMT_Encode4(310898),
     /*    402 */ /*TargetOpcode::G_ASHR*//*Label 57*/ GIMT_Encode4(311442), GIMT_Encode4(0),
     /*    410 */ /*TargetOpcode::G_FSHR*//*Label 58*/ GIMT_Encode4(312267),
     /*    414 */ /*TargetOpcode::G_ROTR*//*Label 59*/ GIMT_Encode4(312397), GIMT_Encode4(0),
     /*    422 */ /*TargetOpcode::G_ICMP*//*Label 60*/ GIMT_Encode4(312939), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    438 */ /*TargetOpcode::G_SELECT*//*Label 61*/ GIMT_Encode4(320716), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    482 */ /*TargetOpcode::G_UMULH*//*Label 62*/ GIMT_Encode4(321761),
     /*    486 */ /*TargetOpcode::G_SMULH*//*Label 63*/ GIMT_Encode4(322245),
     /*    490 */ /*TargetOpcode::G_UADDSAT*//*Label 64*/ GIMT_Encode4(322729),
     /*    494 */ /*TargetOpcode::G_SADDSAT*//*Label 65*/ GIMT_Encode4(323201),
     /*    498 */ /*TargetOpcode::G_USUBSAT*//*Label 66*/ GIMT_Encode4(325577),
     /*    502 */ /*TargetOpcode::G_SSUBSAT*//*Label 67*/ GIMT_Encode4(326049), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    546 */ /*TargetOpcode::G_FADD*//*Label 68*/ GIMT_Encode4(327439),
     /*    550 */ /*TargetOpcode::G_FSUB*//*Label 69*/ GIMT_Encode4(329237),
     /*    554 */ /*TargetOpcode::G_FMUL*//*Label 70*/ GIMT_Encode4(329975),
     /*    558 */ /*TargetOpcode::G_FMA*//*Label 71*/ GIMT_Encode4(334591), GIMT_Encode4(0),
     /*    566 */ /*TargetOpcode::G_FDIV*//*Label 72*/ GIMT_Encode4(350864), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    618 */ /*TargetOpcode::G_FNEG*//*Label 73*/ GIMT_Encode4(351480),
     /*    622 */ /*TargetOpcode::G_FPEXT*//*Label 74*/ GIMT_Encode4(354987),
     /*    626 */ /*TargetOpcode::G_FPTRUNC*//*Label 75*/ GIMT_Encode4(355235),
     /*    630 */ /*TargetOpcode::G_FPTOSI*//*Label 76*/ GIMT_Encode4(355423),
     /*    634 */ /*TargetOpcode::G_FPTOUI*//*Label 77*/ GIMT_Encode4(357231),
     /*    638 */ /*TargetOpcode::G_SITOFP*//*Label 78*/ GIMT_Encode4(359039),
     /*    642 */ /*TargetOpcode::G_UITOFP*//*Label 79*/ GIMT_Encode4(363937),
     /*    646 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 80*/ GIMT_Encode4(368763),
     /*    650 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 81*/ GIMT_Encode4(370200),
     /*    654 */ /*TargetOpcode::G_FABS*//*Label 82*/ GIMT_Encode4(371637), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    666 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 83*/ GIMT_Encode4(372494),
     /*    670 */ /*TargetOpcode::G_FMINNUM*//*Label 84*/ GIMT_Encode4(372776),
     /*    674 */ /*TargetOpcode::G_FMAXNUM*//*Label 85*/ GIMT_Encode4(373154),
     /*    678 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 86*/ GIMT_Encode4(373532),
     /*    682 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 87*/ GIMT_Encode4(373882),
     /*    686 */ /*TargetOpcode::G_FMINIMUM*//*Label 88*/ GIMT_Encode4(374232),
     /*    690 */ /*TargetOpcode::G_FMAXIMUM*//*Label 89*/ GIMT_Encode4(374935), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    734 */ /*TargetOpcode::G_PTR_ADD*//*Label 90*/ GIMT_Encode4(375638), GIMT_Encode4(0),
     /*    742 */ /*TargetOpcode::G_SMIN*//*Label 91*/ GIMT_Encode4(376138),
     /*    746 */ /*TargetOpcode::G_SMAX*//*Label 92*/ GIMT_Encode4(376542),
     /*    750 */ /*TargetOpcode::G_UMIN*//*Label 93*/ GIMT_Encode4(376946),
     /*    754 */ /*TargetOpcode::G_UMAX*//*Label 94*/ GIMT_Encode4(377350),
     /*    758 */ /*TargetOpcode::G_ABS*//*Label 95*/ GIMT_Encode4(377754),
     /*    762 */ /*TargetOpcode::G_LROUND*//*Label 96*/ GIMT_Encode4(378101),
     /*    766 */ /*TargetOpcode::G_LLROUND*//*Label 97*/ GIMT_Encode4(378417),
     /*    770 */ /*TargetOpcode::G_BR*//*Label 98*/ GIMT_Encode4(378608), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    786 */ /*TargetOpcode::G_EXTRACT_SUBVECTOR*//*Label 99*/ GIMT_Encode4(378624),
     /*    790 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 100*/ GIMT_Encode4(384172),
     /*    794 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 101*/ GIMT_Encode4(417109), GIMT_Encode4(0),
     /*    802 */ /*TargetOpcode::G_SPLAT_VECTOR*//*Label 102*/ GIMT_Encode4(420027), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    814 */ /*TargetOpcode::G_CTTZ*//*Label 103*/ GIMT_Encode4(422347), GIMT_Encode4(0),
     /*    822 */ /*TargetOpcode::G_CTLZ*//*Label 104*/ GIMT_Encode4(422499), GIMT_Encode4(0),
     /*    830 */ /*TargetOpcode::G_CTPOP*//*Label 105*/ GIMT_Encode4(423173),
     /*    834 */ /*TargetOpcode::G_BSWAP*//*Label 106*/ GIMT_Encode4(423333),
     /*    838 */ /*TargetOpcode::G_BITREVERSE*//*Label 107*/ GIMT_Encode4(423647),
     /*    842 */ /*TargetOpcode::G_FCEIL*//*Label 108*/ GIMT_Encode4(423801), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    890 */ /*TargetOpcode::G_FSQRT*//*Label 109*/ GIMT_Encode4(424292),
     /*    894 */ /*TargetOpcode::G_FFLOOR*//*Label 110*/ GIMT_Encode4(424592),
     /*    898 */ /*TargetOpcode::G_FRINT*//*Label 111*/ GIMT_Encode4(425083),
     /*    902 */ /*TargetOpcode::G_FNEARBYINT*//*Label 112*/ GIMT_Encode4(425574), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    930 */ /*TargetOpcode::G_STRICT_FADD*//*Label 113*/ GIMT_Encode4(426065),
     /*    934 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 114*/ GIMT_Encode4(427191),
     /*    938 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 115*/ GIMT_Encode4(427807),
     /*    942 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 116*/ GIMT_Encode4(431529), GIMT_Encode4(0),
     /*    950 */ /*TargetOpcode::G_STRICT_FMA*//*Label 117*/ GIMT_Encode4(432145),
     /*    954 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 118*/ GIMT_Encode4(447752), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    990 */ /*TargetOpcode::G_TRAP*//*Label 119*/ GIMT_Encode4(448052),
     /*    994 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 120*/ GIMT_Encode4(448066),
     /*    998 */ /*TargetOpcode::G_UBSANTRAP*//*Label 121*/ GIMT_Encode4(448087), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   1010 */ /*TargetOpcode::G_VECREDUCE_FADD*//*Label 122*/ GIMT_Encode4(448112), GIMT_Encode4(0),
     /*   1018 */ /*TargetOpcode::G_VECREDUCE_FMAX*//*Label 123*/ GIMT_Encode4(448422),
     /*   1022 */ /*TargetOpcode::G_VECREDUCE_FMIN*//*Label 124*/ GIMT_Encode4(448593),
     /*   1026 */ /*TargetOpcode::G_VECREDUCE_FMAXIMUM*//*Label 125*/ GIMT_Encode4(448764),
     /*   1030 */ /*TargetOpcode::G_VECREDUCE_FMINIMUM*//*Label 126*/ GIMT_Encode4(448935),
     /*   1034 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 127*/ GIMT_Encode4(449106), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   1054 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 128*/ GIMT_Encode4(450235),
     /*   1058 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 129*/ GIMT_Encode4(450438),
     /*   1062 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 130*/ GIMT_Encode4(450641),
     /*   1066 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 131*/ GIMT_Encode4(450844), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3374 */ /*AArch64::G_AARCH64_PREFETCH*//*Label 132*/ GIMT_Encode4(451047),
     /*   3378 */ /*AArch64::G_AARCH64_RANGE_PREFETCH*//*Label 133*/ GIMT_Encode4(451187), GIMT_Encode4(0),
     /*   3386 */ /*AArch64::G_BSP*//*Label 134*/ GIMT_Encode4(451227),
     /*   3390 */ /*AArch64::G_DUP*//*Label 135*/ GIMT_Encode4(452215),
     /*   3394 */ /*AArch64::G_DUPLANE16*//*Label 136*/ GIMT_Encode4(454195),
     /*   3398 */ /*AArch64::G_DUPLANE32*//*Label 137*/ GIMT_Encode4(454450),
     /*   3402 */ /*AArch64::G_DUPLANE64*//*Label 138*/ GIMT_Encode4(454705),
     /*   3406 */ /*AArch64::G_DUPLANE8*//*Label 139*/ GIMT_Encode4(454851),
     /*   3410 */ /*AArch64::G_EXT*//*Label 140*/ GIMT_Encode4(455030),
     /*   3414 */ /*AArch64::G_FCMEQ*//*Label 141*/ GIMT_Encode4(456680),
     /*   3418 */ /*AArch64::G_FCMGE*//*Label 142*/ GIMT_Encode4(457239),
     /*   3422 */ /*AArch64::G_FCMGT*//*Label 143*/ GIMT_Encode4(458331),
     /*   3426 */ /*AArch64::G_FPTRUNC_ODD*//*Label 144*/ GIMT_Encode4(459423),
     /*   3430 */ /*AArch64::G_PMULL*//*Label 145*/ GIMT_Encode4(459513),
     /*   3434 */ /*AArch64::G_REV16*//*Label 146*/ GIMT_Encode4(459646),
     /*   3438 */ /*AArch64::G_REV32*//*Label 147*/ GIMT_Encode4(459800),
     /*   3442 */ /*AArch64::G_REV64*//*Label 148*/ GIMT_Encode4(459976),
     /*   3446 */ /*AArch64::G_SADDLP*//*Label 149*/ GIMT_Encode4(460250),
     /*   3450 */ /*AArch64::G_SADDLV*//*Label 150*/ GIMT_Encode4(460456),
     /*   3454 */ /*AArch64::G_SDOT*//*Label 151*/ GIMT_Encode4(460855),
     /*   3458 */ /*AArch64::G_SITOF*//*Label 152*/ GIMT_Encode4(461225),
     /*   3462 */ /*AArch64::G_SLI*//*Label 153*/ GIMT_Encode4(461342),
     /*   3466 */ /*AArch64::G_SMULL*//*Label 154*/ GIMT_Encode4(461910),
     /*   3470 */ /*AArch64::G_SQSHLU_I*//*Label 155*/ GIMT_Encode4(463143),
     /*   3474 */ /*AArch64::G_SRI*//*Label 156*/ GIMT_Encode4(463531),
     /*   3478 */ /*AArch64::G_SRSHR_I*//*Label 157*/ GIMT_Encode4(464099),
     /*   3482 */ /*AArch64::G_TRN1*//*Label 158*/ GIMT_Encode4(464448),
     /*   3486 */ /*AArch64::G_TRN2*//*Label 159*/ GIMT_Encode4(465228),
     /*   3490 */ /*AArch64::G_UADDLP*//*Label 160*/ GIMT_Encode4(466008),
     /*   3494 */ /*AArch64::G_UADDLV*//*Label 161*/ GIMT_Encode4(466214),
     /*   3498 */ /*AArch64::G_UDOT*//*Label 162*/ GIMT_Encode4(467081),
     /*   3502 */ /*AArch64::G_UITOF*//*Label 163*/ GIMT_Encode4(467451),
     /*   3506 */ /*AArch64::G_UMULL*//*Label 164*/ GIMT_Encode4(467568),
     /*   3510 */ /*AArch64::G_URSHR_I*//*Label 165*/ GIMT_Encode4(468801),
     /*   3514 */ /*AArch64::G_USDOT*//*Label 166*/ GIMT_Encode4(469150),
     /*   3518 */ /*AArch64::G_UZP1*//*Label 167*/ GIMT_Encode4(469653),
     /*   3522 */ /*AArch64::G_UZP2*//*Label 168*/ GIMT_Encode4(470433),
     /*   3526 */ /*AArch64::G_VASHR*//*Label 169*/ GIMT_Encode4(471213),
     /*   3530 */ /*AArch64::G_VLSHR*//*Label 170*/ GIMT_Encode4(471812),
     /*   3534 */ /*AArch64::G_ZIP1*//*Label 171*/ GIMT_Encode4(472161),
     /*   3538 */ /*AArch64::G_ZIP2*//*Label 172*/ GIMT_Encode4(472941),
     /*   3542 */ // Label 0: @3542
     /*   3542 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 187*/ GIMT_Encode4(40444),
     /*   3553 */ /*GILLT_s32*//*Label 174*/ GIMT_Encode4(3641),
     /*   3557 */ /*GILLT_s64*//*Label 175*/ GIMT_Encode4(6686), GIMT_Encode4(0),
     /*   3565 */ /*GILLT_v2s32*//*Label 176*/ GIMT_Encode4(12854),
     /*   3569 */ /*GILLT_v2s64*//*Label 177*/ GIMT_Encode4(16846),
     /*   3573 */ /*GILLT_v4s16*//*Label 178*/ GIMT_Encode4(23124),
     /*   3577 */ /*GILLT_v4s32*//*Label 179*/ GIMT_Encode4(27006),
     /*   3581 */ /*GILLT_v8s8*//*Label 180*/ GIMT_Encode4(33658),
     /*   3585 */ /*GILLT_v8s16*//*Label 181*/ GIMT_Encode4(34892),
     /*   3589 */ /*GILLT_v16s8*//*Label 182*/ GIMT_Encode4(38944), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3609 */ /*GILLT_nxv2s64*//*Label 183*/ GIMT_Encode4(39994), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   3621 */ /*GILLT_nxv4s32*//*Label 184*/ GIMT_Encode4(40366), GIMT_Encode4(0),
     /*   3629 */ /*GILLT_nxv8s16*//*Label 185*/ GIMT_Encode4(40392), GIMT_Encode4(0),
     /*   3637 */ /*GILLT_nxv16s8*//*Label 186*/ GIMT_Encode4(40418),
     /*   3641 */ // Label 174: @3641
     /*   3641 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(6685),
     /*   3646 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*   3649 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*   3652 */   GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3685), // Rule ID 14263 //
     /*   3657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   3661 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   3665 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*   3672 */     // (add:{ *:[i32] } addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   3672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*   3675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   3677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   3679 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   3683 */     GIR_RootConstrainSelectedInstOperands,
     /*   3684 */     // GIR_Coverage, 14263,
     /*   3684 */     GIR_EraseRootFromParent_Done,
     /*   3685 */   // Label 189: @3685
     /*   3685 */   GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(3837), // Rule ID 14678 //
     /*   3690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   3701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   3705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   3709 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   3713 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   3717 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   3720 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   3725 */     // MIs[2] pattern
     /*   3725 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   3728 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   3733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3737 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   3739 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   3739 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   3742 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   3746 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3751 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   3753 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   3756 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   3760 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3765 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   3768 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   3772 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   3775 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3780 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3785 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3790 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   3793 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   3797 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3802 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   3805 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   3809 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   3812 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   3814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   3817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   3819 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   3826 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3831 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   3836 */     // GIR_Coverage, 14678,
     /*   3836 */     GIR_EraseRootFromParent_Done,
     /*   3837 */   // Label 190: @3837
     /*   3837 */   GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(3989), // Rule ID 16557 //
     /*   3842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   3853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   3857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   3861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   3865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   3869 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   3872 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   3877 */     // MIs[2] pattern
     /*   3877 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   3880 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   3885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3889 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   3891 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   3891 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   3894 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   3898 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3903 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   3905 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   3908 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   3912 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3917 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   3920 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   3924 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   3927 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3932 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   3937 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3942 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   3945 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   3949 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   3954 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   3957 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   3961 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   3964 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   3966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   3969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   3971 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   3978 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   3983 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   3988 */     // GIR_Coverage, 16557,
     /*   3988 */     GIR_EraseRootFromParent_Done,
     /*   3989 */   // Label 191: @3989
     /*   3989 */   GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(4141), // Rule ID 16569 //
     /*   3994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   3997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4021 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4024 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   4029 */     // MIs[2] pattern
     /*   4029 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4032 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4037 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4041 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4043 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4043 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4046 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4050 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4055 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4057 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4060 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4064 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4069 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4072 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   4076 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4079 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4084 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4089 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4094 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4097 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   4101 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4106 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4109 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4113 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4116 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4123 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4130 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4135 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4140 */     // GIR_Coverage, 16569,
     /*   4140 */     GIR_EraseRootFromParent_Done,
     /*   4141 */   // Label 192: @4141
     /*   4141 */   GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(4293), // Rule ID 16581 //
     /*   4146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4153 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4157 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4161 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4173 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4176 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   4181 */     // MIs[2] pattern
     /*   4181 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4184 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4189 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4193 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4195 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)), GPR32:{ *:[i32] }:$Rdn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4195 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4198 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4202 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4207 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4209 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4212 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4216 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4221 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4224 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rdn
     /*   4228 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4231 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4236 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4241 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4246 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4249 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   4253 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4258 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4261 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4265 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4275 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4282 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4287 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4292 */     // GIR_Coverage, 16581,
     /*   4292 */     GIR_EraseRootFromParent_Done,
     /*   4293 */   // Label 193: @4293
     /*   4293 */   GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(4326), // Rule ID 79 //
     /*   4298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   4302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   4306 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*   4313 */     // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   4313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*   4316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   4318 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   4320 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   4324 */     GIR_RootConstrainSelectedInstOperands,
     /*   4325 */     // GIR_Coverage, 79,
     /*   4325 */     GIR_EraseRootFromParent_Done,
     /*   4326 */   // Label 194: @4326
     /*   4326 */   GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(4478), // Rule ID 2695 //
     /*   4331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4338 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4354 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4358 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4362 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4365 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   4370 */     // MIs[2] pattern
     /*   4370 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4373 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4378 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4380 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4380 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4383 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4387 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4392 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4394 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4397 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4401 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4406 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4409 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4413 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4416 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4421 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4426 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4431 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4434 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   4438 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4443 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4446 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4450 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4453 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4460 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4467 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4472 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4477 */     // GIR_Coverage, 2695,
     /*   4477 */     GIR_EraseRootFromParent_Done,
     /*   4478 */   // Label 195: @4478
     /*   4478 */   GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(4630), // Rule ID 10687 //
     /*   4483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4498 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4502 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4514 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4517 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   4522 */     // MIs[2] pattern
     /*   4522 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4525 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4530 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4532 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4532 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4535 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4539 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4544 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4546 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4549 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4553 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4558 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4561 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4565 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4568 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4573 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4578 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4583 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4586 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   4590 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4595 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4598 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4602 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4605 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4612 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4619 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4624 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4629 */     // GIR_Coverage, 10687,
     /*   4629 */     GIR_EraseRootFromParent_Done,
     /*   4630 */   // Label 196: @4630
     /*   4630 */   GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(4782), // Rule ID 10699 //
     /*   4635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4642 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4654 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4658 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4662 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4666 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4669 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   4674 */     // MIs[2] pattern
     /*   4674 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4677 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4682 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4684 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4684 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4687 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4691 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4696 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4698 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4701 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4705 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4710 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4713 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4717 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4720 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4725 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4730 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4735 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4738 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   4742 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4747 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4750 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4754 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4757 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4764 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4771 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4776 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4781 */     // GIR_Coverage, 10699,
     /*   4781 */     GIR_EraseRootFromParent_Done,
     /*   4782 */   // Label 197: @4782
     /*   4782 */   GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(4934), // Rule ID 10711 //
     /*   4787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   4790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4794 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   4802 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4806 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4810 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   4814 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   4818 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*   4821 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   4826 */     // MIs[2] pattern
     /*   4826 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*   4829 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   4834 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   4836 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*   4836 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4839 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4843 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4848 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4850 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4853 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4857 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4862 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   4865 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*   4869 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   4872 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4877 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   4882 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4887 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   4890 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   4894 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4899 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   4902 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*   4906 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*   4909 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   4911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   4914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   4916 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   4923 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4928 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   4933 */     // GIR_Coverage, 10711,
     /*   4933 */     GIR_EraseRootFromParent_Done,
     /*   4934 */   // Label 198: @4934
     /*   4934 */   GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(5067), // Rule ID 14831 //
     /*   4939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   4947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   4951 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   4955 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_trunc_isWorthFoldingALU),
     /*   4959 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   4963 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   4965 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*   4972 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } arith_shifted_reg64:{ *:[i64] }:$Rm)<<P:Predicate_trunc_isWorthFoldingALU>>, GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (ADDXrs:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), arith_shifted_reg64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] })
     /*   4972 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   4975 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   4979 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4984 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   4986 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   4989 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   4993 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   4998 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5001 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5005 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5008 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5013 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5018 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*   5030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5035 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5038 */     GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), // Rm
     /*   5042 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5049 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5056 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5061 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5066 */     // GIR_Coverage, 14831,
     /*   5066 */     GIR_EraseRootFromParent_Done,
     /*   5067 */   // Label 199: @5067
     /*   5067 */   GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(5200), // Rule ID 4023 //
     /*   5072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5076 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5088 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5092 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_trunc_isWorthFoldingALU),
     /*   5096 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   5098 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*   5105 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } arith_shifted_reg64:{ *:[i64] }:$Rm)<<P:Predicate_trunc_isWorthFoldingALU>>)  =>  (EXTRACT_SUBREG:{ *:[i32] } (ADDXrs:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), arith_shifted_reg64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] })
     /*   5105 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5108 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5112 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5117 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5119 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5122 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5126 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5131 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5134 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   5138 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5141 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5146 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5151 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5156 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5159 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*   5163 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5168 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5171 */     GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), // Rm
     /*   5175 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5182 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5189 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5194 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5199 */     // GIR_Coverage, 4023,
     /*   5199 */     GIR_EraseRootFromParent_Done,
     /*   5200 */   // Label 200: @5200
     /*   5200 */   GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(5357), // Rule ID 16600 //
     /*   5205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5212 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5220 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5224 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5228 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5232 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5235 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5240 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*   5244 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5246 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5251 */     // MIs[2] pred
     /*   5251 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5256 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5260 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5262 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5262 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5265 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5269 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5274 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5276 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5279 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5283 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5288 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5291 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5295 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5298 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5303 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5308 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5313 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5316 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*   5320 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5325 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5329 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5332 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5339 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5346 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5351 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5356 */     // GIR_Coverage, 16600,
     /*   5356 */     GIR_EraseRootFromParent_Done,
     /*   5357 */   // Label 201: @5357
     /*   5357 */   GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(5514), // Rule ID 16601 //
     /*   5362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5369 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5373 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5377 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5389 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5392 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5397 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*   5401 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5403 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5408 */     // MIs[2] pred
     /*   5408 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5417 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5419 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5419 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5422 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5426 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5431 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5433 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5436 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5440 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5445 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5448 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5452 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5455 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5460 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5465 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5470 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5473 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*   5477 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5482 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5486 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5489 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5496 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5503 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5508 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5513 */     // GIR_Coverage, 16601,
     /*   5513 */     GIR_EraseRootFromParent_Done,
     /*   5514 */   // Label 202: @5514
     /*   5514 */   GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(5671), // Rule ID 16602 //
     /*   5519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5534 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5546 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5549 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5554 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*   5558 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5560 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5565 */     // MIs[2] pred
     /*   5565 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5574 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5576 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5576 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5579 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5583 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5588 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5590 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5593 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5597 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5602 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5605 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5609 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5612 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5617 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5622 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5627 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5630 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*   5634 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5639 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5643 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5646 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5653 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5660 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5665 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5670 */     // GIR_Coverage, 16602,
     /*   5670 */     GIR_EraseRootFromParent_Done,
     /*   5671 */   // Label 203: @5671
     /*   5671 */   GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(5828), // Rule ID 16603 //
     /*   5676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5683 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   5687 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5691 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5695 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5699 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5703 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5706 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5711 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*   5715 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5717 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5722 */     // MIs[2] pred
     /*   5722 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5731 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5733 */     // (add:{ *:[i32] } (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>), GPR32:{ *:[i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5733 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5736 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5740 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5745 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5747 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5750 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5754 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5759 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5762 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   5766 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5769 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5774 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5779 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5784 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5787 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*   5791 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5796 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5800 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5803 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5810 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5817 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5822 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5827 */     // GIR_Coverage, 16603,
     /*   5827 */     GIR_EraseRootFromParent_Done,
     /*   5828 */   // Label 204: @5828
     /*   5828 */   GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(5985), // Rule ID 10803 //
     /*   5833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5840 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   5848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   5852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   5856 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   5860 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   5864 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   5867 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   5872 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*   5876 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   5878 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   5883 */     // MIs[2] pred
     /*   5883 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   5888 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   5890 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   5890 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   5893 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   5897 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5902 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   5904 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   5907 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   5911 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5916 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   5919 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   5923 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   5926 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5931 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   5936 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5941 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   5944 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*   5948 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   5953 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   5957 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   5960 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   5962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   5965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   5967 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   5974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5979 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   5984 */     // GIR_Coverage, 10803,
     /*   5984 */     GIR_EraseRootFromParent_Done,
     /*   5985 */   // Label 205: @5985
     /*   5985 */   GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(6142), // Rule ID 10804 //
     /*   5990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   5993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   5997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   6005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   6009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   6013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   6021 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   6024 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   6029 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*   6033 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   6035 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   6040 */     // MIs[2] pred
     /*   6040 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   6045 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   6047 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   6047 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   6050 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   6054 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6059 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   6061 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   6064 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   6068 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6073 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   6076 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   6080 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   6083 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6088 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6093 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6098 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   6101 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*   6105 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6110 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   6114 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   6117 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6124 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   6131 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6136 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   6141 */     // GIR_Coverage, 10804,
     /*   6141 */     GIR_EraseRootFromParent_Done,
     /*   6142 */   // Label 206: @6142
     /*   6142 */   GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(6299), // Rule ID 10805 //
     /*   6147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   6150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6154 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   6162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   6166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   6170 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6174 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   6178 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   6181 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   6186 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*   6190 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   6192 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   6197 */     // MIs[2] pred
     /*   6197 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   6202 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   6204 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   6204 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   6207 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   6211 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6216 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   6218 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   6221 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   6225 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6230 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   6233 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   6237 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   6240 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6245 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6250 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6255 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   6258 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*   6262 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6267 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   6271 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   6274 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6281 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   6288 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6293 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   6298 */     // GIR_Coverage, 10805,
     /*   6298 */     GIR_EraseRootFromParent_Done,
     /*   6299 */   // Label 207: @6299
     /*   6299 */   GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(6456), // Rule ID 10806 //
     /*   6304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*   6307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6311 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   6319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*   6323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   6327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   6335 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*   6338 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*   6343 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*   6347 */     GIM_CheckHasOneUse, /*MI*/2,
     /*   6349 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*   6354 */     // MIs[2] pred
     /*   6354 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*   6359 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   6361 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*   6361 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*   6364 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   6368 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6373 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   6375 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*   6378 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   6382 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6387 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   6390 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*   6394 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*   6397 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6402 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*   6407 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6412 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*   6415 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*   6419 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6424 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*   6428 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   6431 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6438 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*   6445 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6450 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   6455 */     // GIR_Coverage, 10806,
     /*   6455 */     GIR_EraseRootFromParent_Done,
     /*   6456 */   // Label 208: @6456
     /*   6456 */   GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(6489), // Rule ID 14267 //
     /*   6461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6469 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*   6476 */     // (add:{ *:[i32] } arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend, GPR32sp:{ *:[i32] }:$Rn)  =>  (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
     /*   6476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
     /*   6479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6481 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6483 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*   6487 */     GIR_RootConstrainSelectedInstOperands,
     /*   6488 */     // GIR_Coverage, 14267,
     /*   6488 */     GIR_EraseRootFromParent_Done,
     /*   6489 */   // Label 209: @6489
     /*   6489 */   GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(6525), // Rule ID 14827 //
     /*   6494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*   6509 */     // (add:{ *:[i32] } neg_addsub_shifted_imm32:{ *:[i32] }:$imm, GPR32:{ *:[i32] }:$Rn)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   6509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*   6512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6516 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   6520 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*   6523 */     GIR_RootConstrainSelectedInstOperands,
     /*   6524 */     // GIR_Coverage, 14827,
     /*   6524 */     GIR_EraseRootFromParent_Done,
     /*   6525 */   // Label 210: @6525
     /*   6525 */   GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(6558), // Rule ID 85 //
     /*   6530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6534 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*   6538 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*   6545 */     // (add:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)  =>  (ADDWrx:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, arith_extended_reg32_i32:{ *:[i32] }:$Rm_and_extend)
     /*   6545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrx),
     /*   6548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6550 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6552 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*   6556 */     GIR_RootConstrainSelectedInstOperands,
     /*   6557 */     // GIR_Coverage, 85,
     /*   6557 */     GIR_EraseRootFromParent_Done,
     /*   6558 */   // Label 211: @6558
     /*   6558 */   GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(6594), // Rule ID 4015 //
     /*   6563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6571 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*   6578 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*   6578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*   6581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6583 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6585 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   6589 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*   6592 */     GIR_RootConstrainSelectedInstOperands,
     /*   6593 */     // GIR_Coverage, 4015,
     /*   6593 */     GIR_EraseRootFromParent_Done,
     /*   6594 */   // Label 212: @6594
     /*   6594 */   GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(6627), // Rule ID 14265 //
     /*   6599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6603 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6607 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*   6614 */     // (add:{ *:[i32] } arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*   6614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
     /*   6617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   6621 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*   6625 */     GIR_RootConstrainSelectedInstOperands,
     /*   6626 */     // GIR_Coverage, 14265,
     /*   6626 */     GIR_EraseRootFromParent_Done,
     /*   6627 */   // Label 213: @6627
     /*   6627 */   GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(6660), // Rule ID 83 //
     /*   6632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6636 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6640 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*   6647 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ADDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*   6647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWrs),
     /*   6650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   6652 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   6654 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*   6658 */     GIR_RootConstrainSelectedInstOperands,
     /*   6659 */     // GIR_Coverage, 83,
     /*   6659 */     GIR_EraseRootFromParent_Done,
     /*   6660 */   // Label 214: @6660
     /*   6660 */   GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(6684), // Rule ID 81 //
     /*   6665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6669 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6673 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   6677 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ADDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*   6677 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDWrr),
     /*   6682 */     GIR_RootConstrainSelectedInstOperands,
     /*   6683 */     // GIR_Coverage, 81,
     /*   6683 */     GIR_Done,
     /*   6684 */   // Label 215: @6684
     /*   6684 */   GIM_Reject,
     /*   6685 */ // Label 188: @6685
     /*   6685 */ GIM_Reject,
     /*   6686 */ // Label 175: @6686
     /*   6686 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(12853),
     /*   6691 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*   6694 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*   6697 */   GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(6833), // Rule ID 5976 //
     /*   6702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6706 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6710 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6714 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6718 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6722 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6726 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6730 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6735 */     // MIs[1] Operand 2
     /*   6735 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6746 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6750 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6754 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6758 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6762 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6766 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6770 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6775 */     // MIs[3] Operand 2
     /*   6775 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6786 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6788 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6788 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6791 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6795 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6800 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6804 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6808 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6815 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6822 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6827 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6832 */     // GIR_Coverage, 5976,
     /*   6832 */     GIR_EraseRootFromParent_Done,
     /*   6833 */   // Label 217: @6833
     /*   6833 */   GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(6969), // Rule ID 5975 //
     /*   6838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6854 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6858 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   6862 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6866 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6871 */     // MIs[1] Operand 2
     /*   6871 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   6882 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   6886 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6890 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6894 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   6898 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   6902 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   6906 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6911 */     // MIs[3] Operand 2
     /*   6911 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   6922 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   6924 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   6924 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   6927 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   6931 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   6936 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   6940 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   6944 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   6946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   6949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   6951 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   6958 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6963 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   6968 */     // GIR_Coverage, 5975,
     /*   6968 */     GIR_EraseRootFromParent_Done,
     /*   6969 */   // Label 218: @6969
     /*   6969 */   GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(7105), // Rule ID 5985 //
     /*   6974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   6978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   6982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   6986 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   6990 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   6994 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   6998 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7002 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7007 */     // MIs[1] Operand 2
     /*   7007 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   7018 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   7022 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   7026 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7030 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   7034 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7038 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7042 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7047 */     // MIs[3] Operand 2
     /*   7047 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   7058 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   7060 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   7060 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   7063 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv2i32_v2i64),
     /*   7067 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7072 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7076 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   7080 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   7087 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   7094 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7099 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7104 */     // GIR_Coverage, 5985,
     /*   7104 */     GIR_EraseRootFromParent_Done,
     /*   7105 */   // Label 219: @7105
     /*   7105 */   GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(7241), // Rule ID 5974 //
     /*   7110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7114 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7118 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   7122 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7126 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7130 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7134 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7138 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7143 */     // MIs[1] Operand 2
     /*   7143 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   7154 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   7158 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   7162 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7166 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   7170 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   7174 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7178 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7183 */     // MIs[3] Operand 2
     /*   7183 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   7194 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   7196 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   7196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   7199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   7203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7208 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7212 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   7216 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   7223 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   7230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7240 */     // GIR_Coverage, 5974,
     /*   7240 */     GIR_EraseRootFromParent_Done,
     /*   7241 */   // Label 220: @7241
     /*   7241 */   GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(7377), // Rule ID 5973 //
     /*   7246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7250 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7254 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   7258 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7262 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7266 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7270 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7274 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7279 */     // MIs[1] Operand 2
     /*   7279 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   7290 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*   7294 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   7298 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7302 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*   7306 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7310 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   7314 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7319 */     // MIs[3] Operand 2
     /*   7319 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*   7330 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*   7332 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   7332 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   7335 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*   7339 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7344 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7348 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*   7352 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   7359 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   7366 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7371 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7376 */     // GIR_Coverage, 5973,
     /*   7376 */     GIR_EraseRootFromParent_Done,
     /*   7377 */   // Label 221: @7377
     /*   7377 */   GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(7445), // Rule ID 7558 //
     /*   7382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7390 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7394 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7398 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7402 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7407 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /*   7411 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   7415 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7419 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   7423 */     // MIs[2] Rn
     /*   7423 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   7428 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /*   7432 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   7434 */     // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
     /*   7434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /*   7437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*   7443 */     GIR_RootConstrainSelectedInstOperands,
     /*   7444 */     // GIR_Coverage, 7558,
     /*   7444 */     GIR_EraseRootFromParent_Done,
     /*   7445 */   // Label 222: @7445
     /*   7445 */   GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(7513), // Rule ID 14995 //
     /*   7450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   7454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   7466 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   7475 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /*   7479 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*   7483 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*   7487 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*   7491 */     // MIs[2] Rn
     /*   7491 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*   7496 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /*   7500 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   7502 */     // (add:{ *:[i64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (ADDPv2i64p:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn)
     /*   7502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /*   7505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7507 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*   7511 */     GIR_RootConstrainSelectedInstOperands,
     /*   7512 */     // GIR_Coverage, 14995,
     /*   7512 */     GIR_EraseRootFromParent_Done,
     /*   7513 */   // Label 223: @7513
     /*   7513 */   GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(7546), // Rule ID 14264 //
     /*   7518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7526 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*   7533 */     // (add:{ *:[i64] } addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*   7533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*   7536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7538 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*   7540 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   7544 */     GIR_RootConstrainSelectedInstOperands,
     /*   7545 */     // GIR_Coverage, 14264,
     /*   7545 */     GIR_EraseRootFromParent_Done,
     /*   7546 */   // Label 224: @7546
     /*   7546 */   GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(7679), // Rule ID 4069 //
     /*   7551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7555 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7559 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7563 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7567 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   7579 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   7583 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7588 */     // MIs[2] Operand 2
     /*   7588 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*   7599 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7603 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7607 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7611 */     // MIs[3] Operand 1
     /*   7611 */     // No operand predicates
     /*   7611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7615 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7617 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7617 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   7620 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7624 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7629 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7634 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   7636 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7639 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7643 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7648 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   7654 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7659 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7669 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7672 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   7675 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7677 */     GIR_RootConstrainSelectedInstOperands,
     /*   7678 */     // GIR_Coverage, 4069,
     /*   7678 */     GIR_EraseRootFromParent_Done,
     /*   7679 */   // Label 225: @7679
     /*   7679 */   GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(7774), // Rule ID 4067 //
     /*   7684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7700 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7704 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7708 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   7712 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7716 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7721 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7725 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7729 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7733 */     // MIs[3] Operand 1
     /*   7733 */     // No operand predicates
     /*   7733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7737 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7739 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7739 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7742 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7746 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7751 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7756 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   7761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7767 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7772 */     GIR_RootConstrainSelectedInstOperands,
     /*   7773 */     // GIR_Coverage, 4067,
     /*   7773 */     GIR_EraseRootFromParent_Done,
     /*   7774 */   // Label 226: @7774
     /*   7774 */   GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(7869), // Rule ID 4068 //
     /*   7779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7783 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   7787 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7791 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7795 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7799 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7803 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   7807 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   7811 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   7816 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7820 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7824 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*   7828 */     // MIs[3] Operand 1
     /*   7828 */     // No operand predicates
     /*   7828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7832 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7834 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7834 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7837 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7841 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7846 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7851 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   7853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   7856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7858 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   7862 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   7865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   7867 */     GIR_RootConstrainSelectedInstOperands,
     /*   7868 */     // GIR_Coverage, 4068,
     /*   7868 */     GIR_EraseRootFromParent_Done,
     /*   7869 */   // Label 227: @7869
     /*   7869 */   GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(7902), // Rule ID 80 //
     /*   7874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7878 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*   7882 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*   7889 */     // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*   7889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*   7892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   7894 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*   7896 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*   7900 */     GIR_RootConstrainSelectedInstOperands,
     /*   7901 */     // GIR_Coverage, 80,
     /*   7901 */     GIR_EraseRootFromParent_Done,
     /*   7902 */   // Label 228: @7902
     /*   7902 */   GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(8035), // Rule ID 14838 //
     /*   7907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7911 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   7919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   7923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   7927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   7931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   7935 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*   7939 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*   7943 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   7948 */     // MIs[2] Operand 2
     /*   7948 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*   7959 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   7963 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   7967 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   7971 */     // MIs[3] Operand 1
     /*   7971 */     // No operand predicates
     /*   7971 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   7973 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   7973 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*   7976 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   7980 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   7985 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   7990 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*   7992 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   7995 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   7999 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8004 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8010 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8015 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   8023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8028 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*   8031 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8033 */     GIR_RootConstrainSelectedInstOperands,
     /*   8034 */     // GIR_Coverage, 14838,
     /*   8034 */     GIR_EraseRootFromParent_Done,
     /*   8035 */   // Label 229: @8035
     /*   8035 */   GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(8130), // Rule ID 14836 //
     /*   8040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8044 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8048 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8052 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8056 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8060 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8064 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8068 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8072 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8076 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8081 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8085 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   8089 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*   8093 */     // MIs[3] Operand 1
     /*   8093 */     // No operand predicates
     /*   8093 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8095 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   8095 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8098 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   8102 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8107 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   8112 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   8114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   8117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8123 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8126 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8128 */     GIR_RootConstrainSelectedInstOperands,
     /*   8129 */     // GIR_Coverage, 14836,
     /*   8129 */     GIR_EraseRootFromParent_Done,
     /*   8130 */   // Label 230: @8130
     /*   8130 */   GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(8225), // Rule ID 14837 //
     /*   8135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8139 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8151 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8155 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8167 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8171 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8176 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8180 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*   8184 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*   8188 */     // MIs[3] Operand 1
     /*   8188 */     // No operand predicates
     /*   8188 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8190 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*   8190 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8193 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*   8197 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8202 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*   8207 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   8209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8214 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8218 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8221 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8223 */     GIR_RootConstrainSelectedInstOperands,
     /*   8224 */     // GIR_Coverage, 14837,
     /*   8224 */     GIR_EraseRootFromParent_Done,
     /*   8225 */   // Label 231: @8225
     /*   8225 */   GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(8307), // Rule ID 14275 //
     /*   8230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8246 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8258 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8262 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8267 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8271 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8275 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8279 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8288 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8290 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   8293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8305 */     GIR_RootConstrainSelectedInstOperands,
     /*   8306 */     // GIR_Coverage, 14275,
     /*   8306 */     GIR_EraseRootFromParent_Done,
     /*   8307 */   // Label 232: @8307
     /*   8307 */   GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(8389), // Rule ID 14276 //
     /*   8312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8316 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8320 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8324 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8328 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8332 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8336 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8340 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8344 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8349 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8353 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8357 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8361 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8370 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8372 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8387 */     GIR_RootConstrainSelectedInstOperands,
     /*   8388 */     // GIR_Coverage, 14276,
     /*   8388 */     GIR_EraseRootFromParent_Done,
     /*   8389 */   // Label 233: @8389
     /*   8389 */   GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(8471), // Rule ID 111 //
     /*   8394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8398 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8414 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8418 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8422 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8426 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8430 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8435 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8439 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   8443 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8447 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8452 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8454 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*   8457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8459 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8467 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8469 */     GIR_RootConstrainSelectedInstOperands,
     /*   8470 */     // GIR_Coverage, 111,
     /*   8470 */     GIR_EraseRootFromParent_Done,
     /*   8471 */   // Label 234: @8471
     /*   8471 */   GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8553), // Rule ID 113 //
     /*   8476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8480 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8488 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8492 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8496 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8500 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8504 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8508 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8512 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8517 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*   8521 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8525 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*   8529 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8534 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*   8536 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8541 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   8545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*   8549 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   8551 */     GIR_RootConstrainSelectedInstOperands,
     /*   8552 */     // GIR_Coverage, 113,
     /*   8552 */     GIR_EraseRootFromParent_Done,
     /*   8553 */   // Label 235: @8553
     /*   8553 */   GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(8611), // Rule ID 14673 //
     /*   8558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8573 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8576 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   8581 */     // MIs[1] pattern
     /*   8581 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8584 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8593 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8595 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   8598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8606 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8609 */     GIR_RootConstrainSelectedInstOperands,
     /*   8610 */     // GIR_Coverage, 14673,
     /*   8610 */     GIR_EraseRootFromParent_Done,
     /*   8611 */   // Label 236: @8611
     /*   8611 */   GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(8669), // Rule ID 16552 //
     /*   8616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8631 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8634 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   8639 */     // MIs[1] pattern
     /*   8639 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8642 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8647 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8651 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8653 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   8656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8667 */     GIR_RootConstrainSelectedInstOperands,
     /*   8668 */     // GIR_Coverage, 16552,
     /*   8668 */     GIR_EraseRootFromParent_Done,
     /*   8669 */   // Label 237: @8669
     /*   8669 */   GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(8727), // Rule ID 16564 //
     /*   8674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8689 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8692 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   8697 */     // MIs[1] pattern
     /*   8697 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8700 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8709 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8711 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   8714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8722 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8725 */     GIR_RootConstrainSelectedInstOperands,
     /*   8726 */     // GIR_Coverage, 16564,
     /*   8726 */     GIR_EraseRootFromParent_Done,
     /*   8727 */   // Label 238: @8727
     /*   8727 */   GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(8785), // Rule ID 16576 //
     /*   8732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8739 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8743 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   8747 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   8750 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   8755 */     // MIs[1] pattern
     /*   8755 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   8758 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   8763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8767 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   8769 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern), GPR64:{ *:[i64] }:$Rdn)  =>  (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   8769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   8772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   8774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rdn
     /*   8776 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   8780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   8783 */     GIR_RootConstrainSelectedInstOperands,
     /*   8784 */     // GIR_Coverage, 16576,
     /*   8784 */     GIR_EraseRootFromParent_Done,
     /*   8785 */   // Label 239: @8785
     /*   8785 */   GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8882), // Rule ID 4084 //
     /*   8790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8806 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8810 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8815 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   8819 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8823 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8827 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8832 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8836 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8838 */     // (add:{ *:[i64] } (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8838 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8841 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8845 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8850 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8856 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8861 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8871 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   8878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8880 */     GIR_RootConstrainSelectedInstOperands,
     /*   8881 */     // GIR_Coverage, 4084,
     /*   8881 */     GIR_EraseRootFromParent_Done,
     /*   8882 */   // Label 240: @8882
     /*   8882 */   GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(8979), // Rule ID 14848 //
     /*   8887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8891 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   8895 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   8899 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   8903 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   8907 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   8911 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   8915 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   8919 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8924 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   8929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8933 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   8935 */     // (add:{ *:[i64] } (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   8935 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   8938 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   8942 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   8947 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   8953 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   8958 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   8966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   8968 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   8971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   8975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*   8977 */     GIR_RootConstrainSelectedInstOperands,
     /*   8978 */     // GIR_Coverage, 14848,
     /*   8978 */     GIR_EraseRootFromParent_Done,
     /*   8979 */   // Label 241: @8979
     /*   8979 */   GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(9037), // Rule ID 2692 //
     /*   8984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   8987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8991 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   8995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   8999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   9003 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   9006 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*   9011 */     // MIs[1] pattern
     /*   9011 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   9014 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   9019 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   9021 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   9021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCB_XPiI),
     /*   9024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   9026 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   9028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   9032 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   9035 */     GIR_RootConstrainSelectedInstOperands,
     /*   9036 */     // GIR_Coverage, 2692,
     /*   9036 */     GIR_EraseRootFromParent_Done,
     /*   9037 */   // Label 242: @9037
     /*   9037 */   GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9095), // Rule ID 10684 //
     /*   9042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   9045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   9061 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   9064 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*   9069 */     // MIs[1] pattern
     /*   9069 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   9072 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   9077 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   9079 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   9079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCH_XPiI),
     /*   9082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   9084 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   9086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   9090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   9093 */     GIR_RootConstrainSelectedInstOperands,
     /*   9094 */     // GIR_Coverage, 10684,
     /*   9094 */     GIR_EraseRootFromParent_Done,
     /*   9095 */   // Label 243: @9095
     /*   9095 */   GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(9153), // Rule ID 10696 //
     /*   9100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   9103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9107 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   9119 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   9122 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*   9127 */     // MIs[1] pattern
     /*   9127 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   9130 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   9135 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   9137 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   9137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCW_XPiI),
     /*   9140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   9142 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   9144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   9148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   9151 */     GIR_RootConstrainSelectedInstOperands,
     /*   9152 */     // GIR_Coverage, 10696,
     /*   9152 */     GIR_EraseRootFromParent_Done,
     /*   9153 */   // Label 244: @9153
     /*   9153 */   GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(9211), // Rule ID 10708 //
     /*   9158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*   9161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9165 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*   9177 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*   9180 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*   9185 */     // MIs[1] pattern
     /*   9185 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*   9188 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*   9193 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*   9195 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (INCD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*   9195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCD_XPiI),
     /*   9198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*   9200 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*   9202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*   9206 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*   9209 */     GIR_RootConstrainSelectedInstOperands,
     /*   9210 */     // GIR_Coverage, 10708,
     /*   9210 */     GIR_EraseRootFromParent_Done,
     /*   9211 */   // Label 245: @9211
     /*   9211 */   GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(9308), // Rule ID 14849 //
     /*   9216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9220 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   9232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   9236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   9240 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   9245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*   9249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   9253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   9257 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   9262 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9264 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   9264 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   9267 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9271 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9276 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   9282 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   9287 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   9295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   9297 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   9300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9304 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   9306 */     GIR_RootConstrainSelectedInstOperands,
     /*   9307 */     // GIR_Coverage, 14849,
     /*   9307 */     GIR_EraseRootFromParent_Done,
     /*   9308 */   // Label 246: @9308
     /*   9308 */   GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(9405), // Rule ID 14850 //
     /*   9313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*   9325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*   9329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*   9333 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*   9337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*   9345 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*   9349 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   9354 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*   9359 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9361 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*   9361 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*   9364 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9368 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9373 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*   9379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*   9384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*   9389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*   9392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*   9394 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*   9397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9401 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*   9403 */     GIR_RootConstrainSelectedInstOperands,
     /*   9404 */     // GIR_Coverage, 14850,
     /*   9404 */     GIR_EraseRootFromParent_Done,
     /*   9405 */   // Label 247: @9405
     /*   9405 */   GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(9568), // Rule ID 14958 //
     /*   9410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9426 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9430 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*   9434 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9438 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   9442 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9447 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9452 */     // MIs[1] Operand 2
     /*   9452 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9463 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9467 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9469 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9469 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9472 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9476 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9481 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9483 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9486 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9490 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9495 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9498 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*   9502 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9505 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9510 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9515 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9520 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9523 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*   9527 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9532 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9535 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   9539 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*   9543 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9550 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9557 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9562 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9567 */     // GIR_Coverage, 14958,
     /*   9567 */     GIR_EraseRootFromParent_Done,
     /*   9568 */   // Label 248: @9568
     /*   9568 */   GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(9731), // Rule ID 14955 //
     /*   9573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9589 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9593 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*   9597 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9601 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*   9605 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9610 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9615 */     // MIs[1] Operand 2
     /*   9615 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9626 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9630 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9632 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9632 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9635 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9639 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9644 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9646 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9649 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9653 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9658 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9661 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*   9665 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9668 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9673 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9678 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9683 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9686 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*   9690 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9695 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9698 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*   9702 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*   9706 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9713 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9720 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9725 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9730 */     // GIR_Coverage, 14955,
     /*   9730 */     GIR_EraseRootFromParent_Done,
     /*   9731 */   // Label 249: @9731
     /*   9731 */   GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(9881), // Rule ID 14964 //
     /*   9736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9740 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9744 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9748 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9752 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9756 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*   9760 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9764 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9769 */     // MIs[1] Operand 2
     /*   9769 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9784 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9786 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9786 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9789 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9793 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9798 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9800 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9803 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9807 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9812 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9815 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   9819 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9822 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9827 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9832 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9837 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9840 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*   9844 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9849 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*   9852 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*   9856 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*   9858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*   9861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*   9863 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*   9870 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9875 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9880 */     // GIR_Coverage, 14964,
     /*   9880 */     GIR_EraseRootFromParent_Done,
     /*   9881 */   // Label 250: @9881
     /*   9881 */   GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(10031), // Rule ID 14967 //
     /*   9886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*   9894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*   9898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*   9902 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*   9906 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*   9910 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*   9914 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9919 */     // MIs[1] Operand 2
     /*   9919 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*   9930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9934 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*   9936 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*   9936 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*   9939 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*   9943 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9948 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*   9950 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*   9953 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*   9957 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9962 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*   9965 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*   9969 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*   9972 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9977 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*   9982 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*   9987 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*   9990 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*   9994 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*   9999 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10002 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10006 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10013 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10020 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10025 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10030 */     // GIR_Coverage, 14967,
     /*  10030 */     GIR_EraseRootFromParent_Done,
     /*  10031 */   // Label 251: @10031
     /*  10031 */   GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(10181), // Rule ID 14963 //
     /*  10036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  10044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10052 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10056 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  10060 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10064 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10069 */     // MIs[1] Operand 2
     /*  10069 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10084 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10086 */     // (add:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v1i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10086 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10089 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10093 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10098 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10100 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10103 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10107 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10112 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10115 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  10119 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10122 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10127 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10132 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10137 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10140 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  10144 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10149 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10152 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10156 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10163 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10170 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10175 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10180 */     // GIR_Coverage, 14963,
     /*  10180 */     GIR_EraseRootFromParent_Done,
     /*  10181 */   // Label 252: @10181
     /*  10181 */   GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(10344), // Rule ID 5958 //
     /*  10186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10194 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10198 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10202 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10206 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10210 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  10214 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10218 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  10222 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10227 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10232 */     // MIs[1] Operand 2
     /*  10232 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10243 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10245 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10245 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10248 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10252 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10257 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10259 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10262 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10266 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10271 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10274 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  10278 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10281 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10286 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10291 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10296 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10299 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*  10303 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10308 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10311 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  10315 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  10319 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10326 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10333 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10338 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10343 */     // GIR_Coverage, 5958,
     /*  10343 */     GIR_EraseRootFromParent_Done,
     /*  10344 */   // Label 253: @10344
     /*  10344 */   GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(10507), // Rule ID 5955 //
     /*  10349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10353 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10369 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10373 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  10377 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10381 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  10385 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10390 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10395 */     // MIs[1] Operand 2
     /*  10395 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10406 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10408 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLALv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10408 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10411 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10415 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10420 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10422 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10425 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10429 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10434 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10437 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  10441 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10444 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10449 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10454 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10459 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10462 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  10466 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10471 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10474 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  10478 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  10482 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10489 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10496 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10501 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10506 */     // GIR_Coverage, 5955,
     /*  10506 */     GIR_EraseRootFromParent_Done,
     /*  10507 */   // Label 254: @10507
     /*  10507 */   GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(10657), // Rule ID 5982 //
     /*  10512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10516 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10528 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10532 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10536 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  10540 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10544 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10549 */     // MIs[1] Operand 2
     /*  10549 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10560 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10562 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10562 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10565 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10569 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10574 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10576 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10579 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10583 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10588 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10591 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10595 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10598 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10603 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10608 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10613 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10616 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  10620 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10625 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10628 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10632 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10639 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10646 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10651 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10656 */     // GIR_Coverage, 5982,
     /*  10656 */     GIR_EraseRootFromParent_Done,
     /*  10657 */   // Label 255: @10657
     /*  10657 */   GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(10807), // Rule ID 5988 //
     /*  10662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10666 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10682 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10686 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  10690 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10694 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10699 */     // MIs[1] Operand 2
     /*  10699 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10710 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10712 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10712 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10715 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10719 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10724 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10726 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10729 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10733 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10738 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10741 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10745 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10748 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10753 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10758 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10763 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10766 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  10770 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10775 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10778 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10782 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10789 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10796 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10801 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10806 */     // GIR_Coverage, 5988,
     /*  10806 */     GIR_EraseRootFromParent_Done,
     /*  10807 */   // Label 256: @10807
     /*  10807 */   GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(10957), // Rule ID 5981 //
     /*  10812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10816 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  10824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  10828 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  10832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  10836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  10840 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  10844 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10849 */     // MIs[1] Operand 2
     /*  10849 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  10860 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  10862 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UADDWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  10862 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  10865 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  10869 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  10876 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  10879 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  10883 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10888 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  10891 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  10895 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  10898 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10903 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10908 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10913 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  10916 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  10920 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  10925 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  10928 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  10932 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  10934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  10937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  10939 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  10946 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  10951 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  10956 */     // GIR_Coverage, 5981,
     /*  10956 */     GIR_EraseRootFromParent_Done,
     /*  10957 */   // Label 257: @10957
     /*  10957 */   GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(10990), // Rule ID 14268 //
     /*  10962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10966 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  10970 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  10977 */     // (add:{ *:[i64] } arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend, GPR64sp:{ *:[i64] }:$Rn)  =>  (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
     /*  10977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
     /*  10980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  10982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  10984 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*  10988 */     GIR_RootConstrainSelectedInstOperands,
     /*  10989 */     // GIR_Coverage, 14268,
     /*  10989 */     GIR_EraseRootFromParent_Done,
     /*  10990 */   // Label 258: @10990
     /*  10990 */   GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(11026), // Rule ID 14828 //
     /*  10995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  10999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11003 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  11010 */     // (add:{ *:[i64] } neg_addsub_shifted_imm64:{ *:[i64] }:$imm, GPR64:{ *:[i64] }:$Rn)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  11010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  11013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11017 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  11021 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  11024 */     GIR_RootConstrainSelectedInstOperands,
     /*  11025 */     // GIR_Coverage, 14828,
     /*  11025 */     GIR_EraseRootFromParent_Done,
     /*  11026 */   // Label 259: @11026
     /*  11026 */   GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(11138), // Rule ID 4083 //
     /*  11031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11035 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11039 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  11043 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11047 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  11051 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  11056 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  11061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11065 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11067 */     // (add:{ *:[i64] } (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm), GPR64:{ *:[i64] }:$Ra)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  11067 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  11070 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  11074 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  11079 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  11085 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  11090 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11095 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  11098 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  11102 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  11107 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  11113 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  11118 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  11126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11128 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  11131 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  11134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ra
     /*  11136 */     GIR_RootConstrainSelectedInstOperands,
     /*  11137 */     // GIR_Coverage, 4083,
     /*  11137 */     GIR_EraseRootFromParent_Done,
     /*  11138 */   // Label 260: @11138
     /*  11138 */   GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(11171), // Rule ID 86 //
     /*  11143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  11147 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  11151 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  11158 */     // (add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)  =>  (ADDXrx:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, arith_extended_reg32to64_i64:{ *:[i64] }:$Rm_and_extend)
     /*  11158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrx),
     /*  11161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11163 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11165 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_extend
     /*  11169 */     GIR_RootConstrainSelectedInstOperands,
     /*  11170 */     // GIR_Coverage, 86,
     /*  11170 */     GIR_EraseRootFromParent_Done,
     /*  11171 */   // Label 261: @11171
     /*  11171 */   GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(11207), // Rule ID 4016 //
     /*  11176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11180 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11184 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  11191 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  11191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  11194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11196 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11198 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  11202 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  11205 */     GIR_RootConstrainSelectedInstOperands,
     /*  11206 */     // GIR_Coverage, 4016,
     /*  11206 */     GIR_EraseRootFromParent_Done,
     /*  11207 */   // Label 262: @11207
     /*  11207 */   GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(11319), // Rule ID 14847 //
     /*  11212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11216 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  11228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  11232 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  11236 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  11241 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  11246 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11248 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  11248 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  11251 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  11255 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  11260 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  11266 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  11271 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11276 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  11279 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  11283 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  11288 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  11294 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  11299 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  11307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11309 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  11312 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  11315 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  11317 */     GIR_RootConstrainSelectedInstOperands,
     /*  11318 */     // GIR_Coverage, 14847,
     /*  11318 */     GIR_EraseRootFromParent_Done,
     /*  11319 */   // Label 263: @11319
     /*  11319 */   GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(11352), // Rule ID 14266 //
     /*  11324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11332 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  11339 */     // (add:{ *:[i64] } arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  11339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*  11342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11346 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  11350 */     GIR_RootConstrainSelectedInstOperands,
     /*  11351 */     // GIR_Coverage, 14266,
     /*  11351 */     GIR_EraseRootFromParent_Done,
     /*  11352 */   // Label 264: @11352
     /*  11352 */   GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(11415), // Rule ID 16592 //
     /*  11357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11372 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11375 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  11384 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11391 */     // MIs[1] pred
     /*  11391 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11400 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11402 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*  11405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11411 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11413 */     GIR_RootConstrainSelectedInstOperands,
     /*  11414 */     // GIR_Coverage, 16592,
     /*  11414 */     GIR_EraseRootFromParent_Done,
     /*  11415 */   // Label 265: @11415
     /*  11415 */   GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(11478), // Rule ID 16593 //
     /*  11420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11435 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11438 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11443 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  11447 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11449 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11454 */     // MIs[1] pred
     /*  11454 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11463 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11465 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*  11468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11476 */     GIR_RootConstrainSelectedInstOperands,
     /*  11477 */     // GIR_Coverage, 16593,
     /*  11477 */     GIR_EraseRootFromParent_Done,
     /*  11478 */   // Label 266: @11478
     /*  11478 */   GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(11541), // Rule ID 16594 //
     /*  11483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11498 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11501 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11506 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  11510 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11512 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11517 */     // MIs[1] pred
     /*  11517 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11526 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11528 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*  11531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11539 */     GIR_RootConstrainSelectedInstOperands,
     /*  11540 */     // GIR_Coverage, 16594,
     /*  11540 */     GIR_EraseRootFromParent_Done,
     /*  11541 */   // Label 267: @11541
     /*  11541 */   GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(11604), // Rule ID 16595 //
     /*  11546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11553 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11557 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11561 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11564 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11569 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  11573 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11575 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11580 */     // MIs[1] pred
     /*  11580 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11585 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11589 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11591 */     // (add:{ *:[i64] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>, GPR64:{ *:[i64] }:$Rn)  =>  (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*  11594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11596 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  11602 */     GIR_RootConstrainSelectedInstOperands,
     /*  11603 */     // GIR_Coverage, 16595,
     /*  11603 */     GIR_EraseRootFromParent_Done,
     /*  11604 */   // Label 268: @11604
     /*  11604 */   GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(11637), // Rule ID 84 //
     /*  11609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11613 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11617 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  11624 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ADDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  11624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXrs),
     /*  11627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  11629 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11631 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  11635 */     GIR_RootConstrainSelectedInstOperands,
     /*  11636 */     // GIR_Coverage, 84,
     /*  11636 */     GIR_EraseRootFromParent_Done,
     /*  11637 */   // Label 269: @11637
     /*  11637 */   GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(11700), // Rule ID 10795 //
     /*  11642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11649 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11653 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11657 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11661 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11664 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  11673 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11675 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11680 */     // MIs[1] pred
     /*  11680 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11685 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11687 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_B),
     /*  11690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11696 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11698 */     GIR_RootConstrainSelectedInstOperands,
     /*  11699 */     // GIR_Coverage, 10795,
     /*  11699 */     GIR_EraseRootFromParent_Done,
     /*  11700 */   // Label 270: @11700
     /*  11700 */   GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(11763), // Rule ID 10796 //
     /*  11705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11712 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11724 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11727 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  11736 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11738 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11743 */     // MIs[1] pred
     /*  11743 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11748 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11750 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_H),
     /*  11753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11759 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11761 */     GIR_RootConstrainSelectedInstOperands,
     /*  11762 */     // GIR_Coverage, 10796,
     /*  11762 */     GIR_EraseRootFromParent_Done,
     /*  11763 */   // Label 271: @11763
     /*  11763 */   GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(11826), // Rule ID 10797 //
     /*  11768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11775 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11787 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11790 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11795 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  11799 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11801 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11806 */     // MIs[1] pred
     /*  11806 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11811 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11813 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_S),
     /*  11816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11822 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11824 */     GIR_RootConstrainSelectedInstOperands,
     /*  11825 */     // GIR_Coverage, 10797,
     /*  11825 */     GIR_EraseRootFromParent_Done,
     /*  11826 */   // Label 272: @11826
     /*  11826 */   GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(11889), // Rule ID 10798 //
     /*  11831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  11834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  11842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  11846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11850 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  11853 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  11858 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  11862 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  11864 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  11869 */     // MIs[1] pred
     /*  11869 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  11874 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11876 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (INCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  11876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INCP_XP_D),
     /*  11879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  11881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  11885 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  11887 */     GIR_RootConstrainSelectedInstOperands,
     /*  11888 */     // GIR_Coverage, 10798,
     /*  11888 */     GIR_EraseRootFromParent_Done,
     /*  11889 */   // Label 273: @11889
     /*  11889 */   GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(11945), // Rule ID 14376 //
     /*  11894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11901 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11905 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11909 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11912 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  11917 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11921 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11926 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11930 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11932 */     // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 685:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  11935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11943 */     GIR_RootConstrainSelectedInstOperands,
     /*  11944 */     // GIR_Coverage, 14376,
     /*  11944 */     GIR_EraseRootFromParent_Done,
     /*  11945 */   // Label 274: @11945
     /*  11945 */   GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(12001), // Rule ID 14388 //
     /*  11950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  11953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  11961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  11965 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  11968 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  11973 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  11977 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  11986 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  11988 */     // (add:{ *:[v1i64] } (intrinsic_wo_chain:{ *:[v1i64] } 750:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  11988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  11991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  11993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  11995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  11999 */     GIR_RootConstrainSelectedInstOperands,
     /*  12000 */     // GIR_Coverage, 14388,
     /*  12000 */     GIR_EraseRootFromParent_Done,
     /*  12001 */   // Label 275: @12001
     /*  12001 */   GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(12065), // Rule ID 14580 //
     /*  12006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12013 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12017 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  12021 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12025 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12030 */     // MIs[1] imm
     /*  12030 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12033 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12042 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  12046 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12048 */     // (add:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  12051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12059 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12063 */     GIR_RootConstrainSelectedInstOperands,
     /*  12064 */     // GIR_Coverage, 14580,
     /*  12064 */     GIR_EraseRootFromParent_Done,
     /*  12065 */   // Label 276: @12065
     /*  12065 */   GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(12129), // Rule ID 14583 //
     /*  12070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  12085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12089 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12094 */     // MIs[1] imm
     /*  12094 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12097 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12106 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  12110 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12112 */     // (add:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  12115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12127 */     GIR_RootConstrainSelectedInstOperands,
     /*  12128 */     // GIR_Coverage, 14583,
     /*  12128 */     GIR_EraseRootFromParent_Done,
     /*  12129 */   // Label 277: @12129
     /*  12129 */   GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(12185), // Rule ID 1027 //
     /*  12134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12141 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  12153 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  12156 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  12161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12165 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12170 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12172 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 685:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  12175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12177 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  12183 */     GIR_RootConstrainSelectedInstOperands,
     /*  12184 */     // GIR_Coverage, 1027,
     /*  12184 */     GIR_EraseRootFromParent_Done,
     /*  12185 */   // Label 278: @12185
     /*  12185 */   GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(12241), // Rule ID 1088 //
     /*  12190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12197 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12201 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12205 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  12209 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  12212 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  12217 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12221 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12226 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12228 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (intrinsic_wo_chain:{ *:[v1i64] } 750:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  12231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12233 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12235 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  12239 */     GIR_RootConstrainSelectedInstOperands,
     /*  12240 */     // GIR_Coverage, 1088,
     /*  12240 */     GIR_EraseRootFromParent_Done,
     /*  12241 */   // Label 279: @12241
     /*  12241 */   GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(12305), // Rule ID 2152 //
     /*  12246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12253 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12257 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12261 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  12265 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12269 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12274 */     // MIs[1] imm
     /*  12274 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12277 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12282 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  12286 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12288 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  12291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12293 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12303 */     GIR_RootConstrainSelectedInstOperands,
     /*  12304 */     // GIR_Coverage, 2152,
     /*  12304 */     GIR_EraseRootFromParent_Done,
     /*  12305 */   // Label 280: @12305
     /*  12305 */   GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(12369), // Rule ID 2161 //
     /*  12310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  12329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12333 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12338 */     // MIs[1] imm
     /*  12338 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12341 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12346 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  12350 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12352 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  12355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12357 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12359 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12367 */     GIR_RootConstrainSelectedInstOperands,
     /*  12368 */     // GIR_Coverage, 2161,
     /*  12368 */     GIR_EraseRootFromParent_Done,
     /*  12369 */   // Label 281: @12369
     /*  12369 */   GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(12429), // Rule ID 14579 //
     /*  12374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12385 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  12389 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12393 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12398 */     // MIs[1] imm
     /*  12398 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12401 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12410 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12412 */     // (add:{ *:[v1i64] } (AArch64srshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)  =>  (SRSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAd),
     /*  12415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12423 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12427 */     GIR_RootConstrainSelectedInstOperands,
     /*  12428 */     // GIR_Coverage, 14579,
     /*  12428 */     GIR_EraseRootFromParent_Done,
     /*  12429 */   // Label 282: @12429
     /*  12429 */   GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(12489), // Rule ID 14582 //
     /*  12434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12441 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12445 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  12449 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12453 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12458 */     // MIs[1] imm
     /*  12458 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12461 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12466 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12472 */     // (add:{ *:[v1i64] } (AArch64urshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)  =>  (URSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAd),
     /*  12475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12479 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12487 */     GIR_RootConstrainSelectedInstOperands,
     /*  12488 */     // GIR_Coverage, 14582,
     /*  12488 */     GIR_EraseRootFromParent_Done,
     /*  12489 */   // Label 283: @12489
     /*  12489 */   GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(12549), // Rule ID 2150 //
     /*  12494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  12513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12522 */     // MIs[1] imm
     /*  12522 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12525 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12530 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12532 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64srshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))  =>  (SRSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAd),
     /*  12535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12537 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12543 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12547 */     GIR_RootConstrainSelectedInstOperands,
     /*  12548 */     // GIR_Coverage, 2150,
     /*  12548 */     GIR_EraseRootFromParent_Done,
     /*  12549 */   // Label 284: @12549
     /*  12549 */   GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(12609), // Rule ID 2159 //
     /*  12554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  12573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  12577 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12582 */     // MIs[1] imm
     /*  12582 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  12585 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  12590 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12592 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64urshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))  =>  (URSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  12592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAd),
     /*  12595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12597 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12599 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  12607 */     GIR_RootConstrainSelectedInstOperands,
     /*  12608 */     // GIR_Coverage, 2159,
     /*  12608 */     GIR_EraseRootFromParent_Done,
     /*  12609 */   // Label 285: @12609
     /*  12609 */   GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(12657), // Rule ID 14375 //
     /*  12614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12621 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12625 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  12629 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12633 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12638 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12642 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12644 */     // (add:{ *:[v1i64] } (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  12647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12649 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12651 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12655 */     GIR_RootConstrainSelectedInstOperands,
     /*  12656 */     // GIR_Coverage, 14375,
     /*  12656 */     GIR_EraseRootFromParent_Done,
     /*  12657 */   // Label 286: @12657
     /*  12657 */   GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(12705), // Rule ID 14387 //
     /*  12662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12673 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  12677 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12681 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12690 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12692 */     // (add:{ *:[v1i64] } (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn), V64:{ *:[v1i64] }:$Rd)  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  12695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12697 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  12699 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12703 */     GIR_RootConstrainSelectedInstOperands,
     /*  12704 */     // GIR_Coverage, 14387,
     /*  12704 */     GIR_EraseRootFromParent_Done,
     /*  12705 */   // Label 287: @12705
     /*  12705 */   GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(12753), // Rule ID 1026 //
     /*  12710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12713 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12717 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  12729 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12733 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12740 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn))  =>  (SADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv2i32_v1i64),
     /*  12743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12745 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12751 */     GIR_RootConstrainSelectedInstOperands,
     /*  12752 */     // GIR_Coverage, 1026,
     /*  12752 */     GIR_EraseRootFromParent_Done,
     /*  12753 */   // Label 288: @12753
     /*  12753 */   GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(12801), // Rule ID 1087 //
     /*  12758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  12773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  12777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12781 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12786 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  12788 */     // (add:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn))  =>  (UADALPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /*  12788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv2i32_v1i64),
     /*  12791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  12793 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  12795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  12799 */     GIR_RootConstrainSelectedInstOperands,
     /*  12800 */     // GIR_Coverage, 1087,
     /*  12800 */     GIR_EraseRootFromParent_Done,
     /*  12801 */   // Label 289: @12801
     /*  12801 */   GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(12825), // Rule ID 82 //
     /*  12806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  12818 */     // (add:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ADDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  12818 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDXrr),
     /*  12823 */     GIR_RootConstrainSelectedInstOperands,
     /*  12824 */     // GIR_Coverage, 82,
     /*  12824 */     GIR_Done,
     /*  12825 */   // Label 290: @12825
     /*  12825 */   GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(12852), // Rule ID 1613 //
     /*  12830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  12833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12837 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12845 */     // (add:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (ADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  12845 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv1i64),
     /*  12850 */     GIR_RootConstrainSelectedInstOperands,
     /*  12851 */     // GIR_Coverage, 1613,
     /*  12851 */     GIR_Done,
     /*  12852 */   // Label 291: @12852
     /*  12852 */   GIM_Reject,
     /*  12853 */ // Label 216: @12853
     /*  12853 */ GIM_Reject,
     /*  12854 */ // Label 176: @12854
     /*  12854 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(16845),
     /*  12859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12862 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12865 */   GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(13053), // Rule ID 7579 //
     /*  12870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  12874 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  12878 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /*  12882 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12886 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12890 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  12894 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12898 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  12902 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  12907 */     // MIs[2] Operand 2
     /*  12907 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  12918 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  12922 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12926 */     // MIs[3] Rn
     /*  12926 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12931 */     // MIs[3] Operand 2
     /*  12931 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(2),
     /*  12942 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  12946 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_ZIP2),
     /*  12950 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  12954 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  12958 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  12962 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12966 */     // MIs[5] Rn
     /*  12966 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12971 */     // MIs[5] Operand 2
     /*  12971 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(0),
     /*  12982 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6]
     /*  12986 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  12990 */     // MIs[6] Rn
     /*  12990 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  12995 */     // MIs[6] Operand 2
     /*  12995 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(2),
     /*  13006 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  13008 */     // (add:{ *:[v2i32] } (AArch64zip1:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })), (AArch64zip2:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /*  13008 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  13011 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  13015 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13020 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13024 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13028 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13035 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13042 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13047 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13052 */     // GIR_Coverage, 7579,
     /*  13052 */     GIR_EraseRootFromParent_Done,
     /*  13053 */   // Label 293: @13053
     /*  13053 */   GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(13241), // Rule ID 15006 //
     /*  13058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /*  13070 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  13074 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  13078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13086 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13090 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13095 */     // MIs[2] Operand 2
     /*  13095 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  13106 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  13110 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13114 */     // MIs[3] Rn
     /*  13114 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  13119 */     // MIs[3] Operand 2
     /*  13119 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(2),
     /*  13130 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  13134 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_ZIP1),
     /*  13138 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  13142 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  13146 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  13150 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13154 */     // MIs[5] Rn
     /*  13154 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  13159 */     // MIs[5] Operand 2
     /*  13159 */     GIM_CheckLiteralInt, /*MI*/5, /*Op*/2, GIMT_Encode8(0),
     /*  13170 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/4, /*OpIdx*/2, // MIs[6]
     /*  13174 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13178 */     // MIs[6] Rn
     /*  13178 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  13183 */     // MIs[6] Operand 2
     /*  13183 */     GIM_CheckLiteralInt, /*MI*/6, /*Op*/2, GIMT_Encode8(2),
     /*  13194 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  13196 */     // (add:{ *:[v2i32] } (AArch64zip2:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })), (AArch64zip1:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /*  13196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  13199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  13203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13208 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13212 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13216 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13223 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13240 */     // GIR_Coverage, 15006,
     /*  13240 */     GIR_EraseRootFromParent_Done,
     /*  13241 */   // Label 294: @13241
     /*  13241 */   GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(13377), // Rule ID 5972 //
     /*  13246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13250 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13254 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13258 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13262 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13266 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13270 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13274 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13279 */     // MIs[1] Operand 2
     /*  13279 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13290 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13294 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13298 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13302 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13306 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13310 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13314 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13319 */     // MIs[3] Operand 2
     /*  13319 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13330 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13332 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13332 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13335 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13339 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13344 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13348 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13352 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13359 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13366 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13371 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13376 */     // GIR_Coverage, 5972,
     /*  13376 */     GIR_EraseRootFromParent_Done,
     /*  13377 */   // Label 295: @13377
     /*  13377 */   GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(13513), // Rule ID 5971 //
     /*  13382 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13390 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13394 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13398 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13402 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13406 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13410 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13415 */     // MIs[1] Operand 2
     /*  13415 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13426 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13430 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13434 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13438 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13442 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13446 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13450 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13455 */     // MIs[3] Operand 2
     /*  13455 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13466 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13468 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13468 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13471 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13475 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13480 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13484 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13488 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13495 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13502 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13507 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13512 */     // GIR_Coverage, 5971,
     /*  13512 */     GIR_EraseRootFromParent_Done,
     /*  13513 */   // Label 296: @13513
     /*  13513 */   GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(13649), // Rule ID 5984 //
     /*  13518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13522 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13526 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13530 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13534 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13538 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  13542 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13546 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13551 */     // MIs[1] Operand 2
     /*  13551 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13562 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13566 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13570 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13574 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13578 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  13582 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13586 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13591 */     // MIs[3] Operand 2
     /*  13591 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13602 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13604 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13604 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13607 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i16_v4i32),
     /*  13611 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13616 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13620 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13624 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13631 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13638 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13648 */     // GIR_Coverage, 5984,
     /*  13648 */     GIR_EraseRootFromParent_Done,
     /*  13649 */   // Label 297: @13649
     /*  13649 */   GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(13785), // Rule ID 5970 //
     /*  13654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13678 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13682 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13687 */     // MIs[1] Operand 2
     /*  13687 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13698 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13702 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13706 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13710 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13714 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  13718 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13722 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13727 */     // MIs[3] Operand 2
     /*  13727 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13738 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13740 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13740 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13743 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13747 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13752 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13756 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13760 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13767 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13774 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13779 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13784 */     // GIR_Coverage, 5970,
     /*  13784 */     GIR_EraseRootFromParent_Done,
     /*  13785 */   // Label 298: @13785
     /*  13785 */   GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(13921), // Rule ID 5969 //
     /*  13790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13806 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13810 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13814 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13823 */     // MIs[1] Operand 2
     /*  13823 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13834 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  13838 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13842 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13846 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  13850 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  13854 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13858 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13863 */     // MIs[3] Operand 2
     /*  13863 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  13874 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  13876 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13876 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  13879 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  13883 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13888 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  13892 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  13896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  13898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  13901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  13903 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  13910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13915 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  13920 */     // GIR_Coverage, 5969,
     /*  13920 */     GIR_EraseRootFromParent_Done,
     /*  13921 */   // Label 299: @13921
     /*  13921 */   GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(14084), // Rule ID 14957 //
     /*  13926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13930 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  13934 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  13938 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  13942 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  13946 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  13950 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  13954 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  13958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13963 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13968 */     // MIs[1] Operand 2
     /*  13968 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  13979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  13983 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  13985 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  13985 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  13988 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  13992 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  13997 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  13999 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14002 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14006 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14011 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14014 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  14018 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14021 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14026 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14031 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14036 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14039 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  14043 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14048 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14051 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14055 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14059 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14066 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14073 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14078 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14083 */     // GIR_Coverage, 14957,
     /*  14083 */     GIR_EraseRootFromParent_Done,
     /*  14084 */   // Label 300: @14084
     /*  14084 */   GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(14247), // Rule ID 14954 //
     /*  14089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14109 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  14113 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14117 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  14121 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14126 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14131 */     // MIs[1] Operand 2
     /*  14131 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14142 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14146 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14148 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14148 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14151 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14155 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14160 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14162 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14165 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14169 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14174 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14177 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  14181 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14184 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14189 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14194 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14199 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14202 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  14206 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14211 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14214 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14218 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14222 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14229 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14236 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14241 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14246 */     // GIR_Coverage, 14954,
     /*  14246 */     GIR_EraseRootFromParent_Done,
     /*  14247 */   // Label 301: @14247
     /*  14247 */   GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(14397), // Rule ID 14962 //
     /*  14252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14260 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14264 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14268 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14272 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  14276 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14280 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14285 */     // MIs[1] Operand 2
     /*  14285 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14300 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14302 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14302 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14305 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14309 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14314 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14316 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14319 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14323 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14328 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14331 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  14335 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14338 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14343 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14348 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14353 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14356 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  14360 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14365 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14368 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14372 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14379 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14386 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14391 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14396 */     // GIR_Coverage, 14962,
     /*  14396 */     GIR_EraseRootFromParent_Done,
     /*  14397 */   // Label 302: @14397
     /*  14397 */   GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(14547), // Rule ID 14966 //
     /*  14402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14406 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14410 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14414 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14418 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14422 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  14426 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14430 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14435 */     // MIs[1] Operand 2
     /*  14435 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14446 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14452 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14452 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14455 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14459 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14464 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14466 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14469 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14473 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14478 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14481 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  14485 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14488 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14493 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14498 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14503 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14506 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  14510 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14515 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14518 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14522 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14529 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14536 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14541 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14546 */     // GIR_Coverage, 14966,
     /*  14546 */     GIR_EraseRootFromParent_Done,
     /*  14547 */   // Label 303: @14547
     /*  14547 */   GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(14697), // Rule ID 14961 //
     /*  14552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  14560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14564 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  14576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14580 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14585 */     // MIs[1] Operand 2
     /*  14585 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14600 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14602 */     // (add:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14602 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14605 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14609 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14614 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14616 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14619 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14623 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14628 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14631 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  14635 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14638 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14643 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14648 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14653 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14656 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  14660 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14665 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14668 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  14672 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14679 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14686 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14691 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14696 */     // GIR_Coverage, 14961,
     /*  14696 */     GIR_EraseRootFromParent_Done,
     /*  14697 */   // Label 304: @14697
     /*  14697 */   GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(14860), // Rule ID 5957 //
     /*  14702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14706 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14714 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14718 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14722 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14726 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  14730 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14734 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  14738 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14743 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14748 */     // MIs[1] Operand 2
     /*  14748 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14759 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14761 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14761 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14764 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14768 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14773 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14775 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14778 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14782 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14787 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14790 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  14794 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14797 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14802 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14807 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14812 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14815 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  14819 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14824 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14827 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14831 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14835 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  14837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  14840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  14842 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  14849 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14854 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14859 */     // GIR_Coverage, 5957,
     /*  14859 */     GIR_EraseRootFromParent_Done,
     /*  14860 */   // Label 305: @14860
     /*  14860 */   GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(15023), // Rule ID 5954 //
     /*  14865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14869 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14873 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  14877 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  14881 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  14885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  14889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  14893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  14897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  14901 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14906 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14911 */     // MIs[1] Operand 2
     /*  14911 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  14922 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  14924 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLALv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  14924 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  14927 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  14931 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14936 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  14938 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  14941 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  14945 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14950 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  14953 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  14957 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  14960 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14965 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  14970 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  14975 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  14978 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  14982 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  14987 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  14990 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  14994 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  14998 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  15000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  15003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15005 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  15012 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15017 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15022 */     // GIR_Coverage, 5954,
     /*  15022 */     GIR_EraseRootFromParent_Done,
     /*  15023 */   // Label 306: @15023
     /*  15023 */   GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(15173), // Rule ID 5980 //
     /*  15028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15032 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  15044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  15048 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  15052 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  15056 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15060 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15065 */     // MIs[1] Operand 2
     /*  15065 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  15076 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15078 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  15078 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  15081 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  15085 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15090 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  15092 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  15095 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  15099 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15104 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  15107 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  15111 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  15114 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15119 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15124 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15129 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  15132 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  15136 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15141 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  15144 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  15148 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  15150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  15153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15155 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  15162 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15167 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15172 */     // GIR_Coverage, 5980,
     /*  15172 */     GIR_EraseRootFromParent_Done,
     /*  15173 */   // Label 307: @15173
     /*  15173 */   GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(15323), // Rule ID 5987 //
     /*  15178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  15194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  15198 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  15202 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  15206 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15210 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15215 */     // MIs[1] Operand 2
     /*  15215 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  15226 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15228 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  15228 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  15231 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  15235 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15240 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  15242 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  15245 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  15249 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15254 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  15257 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  15261 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  15264 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15269 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15274 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15279 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  15282 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  15286 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15291 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  15294 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  15298 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  15300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  15303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15305 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  15312 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15317 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15322 */     // GIR_Coverage, 5987,
     /*  15322 */     GIR_EraseRootFromParent_Done,
     /*  15323 */   // Label 308: @15323
     /*  15323 */   GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(15473), // Rule ID 5979 //
     /*  15328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15332 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15336 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15340 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  15344 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  15348 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  15352 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  15356 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  15360 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15365 */     // MIs[1] Operand 2
     /*  15365 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  15376 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  15378 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UADDWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  15378 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  15381 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  15385 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15390 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  15392 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  15395 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  15399 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15404 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  15407 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  15411 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  15414 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15419 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15424 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15429 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  15432 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  15436 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  15441 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  15444 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  15448 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  15450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  15453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15455 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  15462 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15467 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  15472 */     // GIR_Coverage, 5979,
     /*  15472 */     GIR_EraseRootFromParent_Done,
     /*  15473 */   // Label 309: @15473
     /*  15473 */   GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(15529), // Rule ID 14372 //
     /*  15478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15493 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15496 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  15501 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15505 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15514 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15516 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15527 */     GIR_RootConstrainSelectedInstOperands,
     /*  15528 */     // GIR_Coverage, 14372,
     /*  15528 */     GIR_EraseRootFromParent_Done,
     /*  15529 */   // Label 310: @15529
     /*  15529 */   GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(15585), // Rule ID 14384 //
     /*  15534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15549 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15552 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  15557 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15561 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15566 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15570 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15572 */     // (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 750:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15579 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15583 */     GIR_RootConstrainSelectedInstOperands,
     /*  15584 */     // GIR_Coverage, 14384,
     /*  15584 */     GIR_EraseRootFromParent_Done,
     /*  15585 */   // Label 311: @15585
     /*  15585 */   GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(15649), // Rule ID 14600 //
     /*  15590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  15605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15609 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15614 */     // MIs[1] imm
     /*  15614 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  15617 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15622 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15626 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15630 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15632 */     // (add:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  15632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  15635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  15647 */     GIR_RootConstrainSelectedInstOperands,
     /*  15648 */     // GIR_Coverage, 14600,
     /*  15648 */     GIR_EraseRootFromParent_Done,
     /*  15649 */   // Label 312: @15649
     /*  15649 */   GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(15713), // Rule ID 14621 //
     /*  15654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  15669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15678 */     // MIs[1] imm
     /*  15678 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  15681 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15690 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15694 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15696 */     // (add:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  15696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  15699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  15703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  15711 */     GIR_RootConstrainSelectedInstOperands,
     /*  15712 */     // GIR_Coverage, 14621,
     /*  15712 */     GIR_EraseRootFromParent_Done,
     /*  15713 */   // Label 313: @15713
     /*  15713 */   GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(15769), // Rule ID 1023 //
     /*  15718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15725 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15729 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15733 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15737 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15740 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  15745 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15749 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15754 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15756 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  15759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15761 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15767 */     GIR_RootConstrainSelectedInstOperands,
     /*  15768 */     // GIR_Coverage, 1023,
     /*  15768 */     GIR_EraseRootFromParent_Done,
     /*  15769 */   // Label 314: @15769
     /*  15769 */   GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(15825), // Rule ID 1084 //
     /*  15774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15781 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  15793 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  15796 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  15801 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  15805 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15810 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15812 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 750:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  15812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  15815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15817 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15819 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  15823 */     GIR_RootConstrainSelectedInstOperands,
     /*  15824 */     // GIR_Coverage, 1084,
     /*  15824 */     GIR_EraseRootFromParent_Done,
     /*  15825 */   // Label 315: @15825
     /*  15825 */   GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(15889), // Rule ID 2269 //
     /*  15830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15837 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15841 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15845 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  15849 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15853 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15858 */     // MIs[1] imm
     /*  15858 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  15861 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15866 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15870 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15872 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  15872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  15875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15877 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  15887 */     GIR_RootConstrainSelectedInstOperands,
     /*  15888 */     // GIR_Coverage, 2269,
     /*  15888 */     GIR_EraseRootFromParent_Done,
     /*  15889 */   // Label 316: @15889
     /*  15889 */   GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(15953), // Rule ID 2328 //
     /*  15894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15901 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15905 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  15909 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  15913 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15917 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15922 */     // MIs[1] imm
     /*  15922 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  15925 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15930 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  15934 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15936 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  15936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  15939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  15941 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  15943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  15947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  15951 */     GIR_RootConstrainSelectedInstOperands,
     /*  15952 */     // GIR_Coverage, 2328,
     /*  15952 */     GIR_EraseRootFromParent_Done,
     /*  15953 */   // Label 317: @15953
     /*  15953 */   GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(16013), // Rule ID 14589 //
     /*  15958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  15961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  15969 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  15973 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  15977 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15982 */     // MIs[1] imm
     /*  15982 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  15985 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  15990 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  15994 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  15996 */     // (add:{ *:[v2i32] } (AArch64srshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)  =>  (SRSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  15996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv2i32_shift),
     /*  15999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16003 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  16011 */     GIR_RootConstrainSelectedInstOperands,
     /*  16012 */     // GIR_Coverage, 14589,
     /*  16012 */     GIR_EraseRootFromParent_Done,
     /*  16013 */   // Label 318: @16013
     /*  16013 */   GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(16073), // Rule ID 14610 //
     /*  16018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16025 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16029 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  16033 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16037 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16042 */     // MIs[1] imm
     /*  16042 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  16045 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  16050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16054 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16056 */     // (add:{ *:[v2i32] } (AArch64urshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)  =>  (URSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  16056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv2i32_shift),
     /*  16059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  16071 */     GIR_RootConstrainSelectedInstOperands,
     /*  16072 */     // GIR_Coverage, 14610,
     /*  16072 */     GIR_EraseRootFromParent_Done,
     /*  16073 */   // Label 319: @16073
     /*  16073 */   GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(16133), // Rule ID 2245 //
     /*  16078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16085 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16093 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  16097 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16101 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16106 */     // MIs[1] imm
     /*  16106 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  16109 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  16114 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16116 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64srshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))  =>  (SRSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  16116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv2i32_shift),
     /*  16119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16121 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16127 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  16131 */     GIR_RootConstrainSelectedInstOperands,
     /*  16132 */     // GIR_Coverage, 2245,
     /*  16132 */     GIR_EraseRootFromParent_Done,
     /*  16133 */   // Label 320: @16133
     /*  16133 */   GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(16193), // Rule ID 2304 //
     /*  16138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16145 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  16157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16161 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16166 */     // MIs[1] imm
     /*  16166 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  16169 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  16174 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16176 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64urshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))  =>  (URSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  16176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv2i32_shift),
     /*  16179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16181 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16187 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  16191 */     GIR_RootConstrainSelectedInstOperands,
     /*  16192 */     // GIR_Coverage, 2304,
     /*  16192 */     GIR_EraseRootFromParent_Done,
     /*  16193 */   // Label 321: @16193
     /*  16193 */   GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(16254), // Rule ID 14405 //
     /*  16198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16205 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16209 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  16213 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16217 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16221 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16237 */     // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  16237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  16240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  16252 */     GIR_RootConstrainSelectedInstOperands,
     /*  16253 */     // GIR_Coverage, 14405,
     /*  16253 */     GIR_EraseRootFromParent_Done,
     /*  16254 */   // Label 322: @16254
     /*  16254 */   GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(16315), // Rule ID 14411 //
     /*  16259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  16274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16278 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16282 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16287 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16292 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16298 */     // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V64:{ *:[v2i32] }:$Rd)  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  16298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
     /*  16301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16309 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  16313 */     GIR_RootConstrainSelectedInstOperands,
     /*  16314 */     // GIR_Coverage, 14411,
     /*  16314 */     GIR_EraseRootFromParent_Done,
     /*  16315 */   // Label 323: @16315
     /*  16315 */   GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(16409), // Rule ID 14970 //
     /*  16320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16328 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  16332 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16336 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16341 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16345 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16347 */     // (add:{ *:[v2i32] } (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vm), V64:{ *:[v2i32] }:$Vn)  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  16347 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  16350 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  16354 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  16359 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  16362 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  16364 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  16367 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  16371 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  16376 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  16383 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16388 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  16396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  16400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  16404 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  16407 */     GIR_RootConstrainSelectedInstOperands,
     /*  16408 */     // GIR_Coverage, 14970,
     /*  16408 */     GIR_EraseRootFromParent_Done,
     /*  16409 */   // Label 324: @16409
     /*  16409 */   GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(16457), // Rule ID 14371 //
     /*  16414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  16429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  16433 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16438 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16442 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16444 */     // (add:{ *:[v2i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  16444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  16447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16455 */     GIR_RootConstrainSelectedInstOperands,
     /*  16456 */     // GIR_Coverage, 14371,
     /*  16456 */     GIR_EraseRootFromParent_Done,
     /*  16457 */   // Label 325: @16457
     /*  16457 */   GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(16505), // Rule ID 14383 //
     /*  16462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16469 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16473 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  16477 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  16481 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16486 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16490 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16492 */     // (add:{ *:[v2i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn), V64:{ *:[v2i32] }:$Rd)  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  16492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  16495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16503 */     GIR_RootConstrainSelectedInstOperands,
     /*  16504 */     // GIR_Coverage, 14383,
     /*  16504 */     GIR_EraseRootFromParent_Done,
     /*  16505 */   // Label 326: @16505
     /*  16505 */   GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(16566), // Rule ID 1390 //
     /*  16510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16517 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  16529 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16533 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16542 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16547 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16549 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  16549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  16552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16554 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16556 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16560 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  16564 */     GIR_RootConstrainSelectedInstOperands,
     /*  16565 */     // GIR_Coverage, 1390,
     /*  16565 */     GIR_EraseRootFromParent_Done,
     /*  16566 */   // Label 327: @16566
     /*  16566 */   GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(16627), // Rule ID 1501 //
     /*  16571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16578 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16582 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16586 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  16590 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16594 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16598 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16603 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16608 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16610 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  16610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv2i32),
     /*  16613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16615 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16621 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  16625 */     GIR_RootConstrainSelectedInstOperands,
     /*  16626 */     // GIR_Coverage, 1501,
     /*  16626 */     GIR_EraseRootFromParent_Done,
     /*  16627 */   // Label 328: @16627
     /*  16627 */   GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(16721), // Rule ID 6663 //
     /*  16632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16636 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  16648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16657 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16659 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vn, (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vm))  =>  (SABAv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  16659 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  16662 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  16666 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  16671 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  16674 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  16676 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  16679 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  16683 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  16688 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  16695 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16700 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv2i32),
     /*  16708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16710 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  16712 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  16716 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  16719 */     GIR_RootConstrainSelectedInstOperands,
     /*  16720 */     // GIR_Coverage, 6663,
     /*  16720 */     GIR_EraseRootFromParent_Done,
     /*  16721 */   // Label 329: @16721
     /*  16721 */   GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(16769), // Rule ID 1022 //
     /*  16726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16733 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  16745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  16749 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16754 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16756 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (SADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  16756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i16_v2i32),
     /*  16759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16761 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16767 */     GIR_RootConstrainSelectedInstOperands,
     /*  16768 */     // GIR_Coverage, 1022,
     /*  16768 */     GIR_EraseRootFromParent_Done,
     /*  16769 */   // Label 330: @16769
     /*  16769 */   GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(16817), // Rule ID 1083 //
     /*  16774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16781 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  16789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  16793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  16797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16802 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  16804 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (UADALPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /*  16804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i16_v2i32),
     /*  16807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16809 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  16811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  16815 */     GIR_RootConstrainSelectedInstOperands,
     /*  16816 */     // GIR_Coverage, 1083,
     /*  16816 */     GIR_EraseRootFromParent_Done,
     /*  16817 */   // Label 331: @16817
     /*  16817 */   GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(16844), // Rule ID 1134 //
     /*  16822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16829 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  16837 */     // (add:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  16837 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i32),
     /*  16842 */     GIR_RootConstrainSelectedInstOperands,
     /*  16843 */     // GIR_Coverage, 1134,
     /*  16843 */     GIR_Done,
     /*  16844 */   // Label 332: @16844
     /*  16844 */   GIM_Reject,
     /*  16845 */ // Label 292: @16845
     /*  16845 */ GIM_Reject,
     /*  16846 */ // Label 177: @16846
     /*  16846 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(23123),
     /*  16851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  16854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  16857 */   GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(16975), // Rule ID 14529 //
     /*  16862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  16877 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16881 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  16885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  16889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  16893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16897 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  16901 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  16905 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  16909 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  16913 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16918 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  16922 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  16926 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  16930 */     // MIs[4] Operand 1
     /*  16930 */     // No operand predicates
     /*  16930 */     // MIs[2] Operand 2
     /*  16930 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  16941 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16945 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  16947 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  16954 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  16954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  16957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  16959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  16961 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  16966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  16970 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  16973 */     GIR_RootConstrainSelectedInstOperands,
     /*  16974 */     // GIR_Coverage, 14529,
     /*  16974 */     GIR_EraseRootFromParent_Done,
     /*  16975 */   // Label 334: @16975
     /*  16975 */   GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(17093), // Rule ID 14530 //
     /*  16980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  16983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  16987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  16991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  16995 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  16999 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17003 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17007 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17011 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17015 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17019 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17023 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17027 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17031 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17036 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17040 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17044 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17048 */     // MIs[4] Operand 1
     /*  17048 */     // No operand predicates
     /*  17048 */     // MIs[2] Operand 2
     /*  17048 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17063 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17065 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17072 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  17075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17088 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17091 */     GIR_RootConstrainSelectedInstOperands,
     /*  17092 */     // GIR_Coverage, 14530,
     /*  17092 */     GIR_EraseRootFromParent_Done,
     /*  17093 */   // Label 335: @17093
     /*  17093 */   GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(17211), // Rule ID 14565 //
     /*  17098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17113 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17117 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17129 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17133 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17137 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17141 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17145 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17149 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17154 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17158 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17162 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17166 */     // MIs[4] Operand 1
     /*  17166 */     // No operand predicates
     /*  17166 */     // MIs[2] Operand 2
     /*  17166 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17181 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17183 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17190 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  17193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17195 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17197 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17206 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17209 */     GIR_RootConstrainSelectedInstOperands,
     /*  17210 */     // GIR_Coverage, 14565,
     /*  17210 */     GIR_EraseRootFromParent_Done,
     /*  17211 */   // Label 336: @17211
     /*  17211 */   GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(17329), // Rule ID 14566 //
     /*  17216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17247 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17251 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17255 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17259 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17263 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17267 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17272 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17276 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17280 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17284 */     // MIs[4] Operand 1
     /*  17284 */     // No operand predicates
     /*  17284 */     // MIs[2] Operand 2
     /*  17284 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17299 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17301 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17308 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  17311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17324 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17327 */     GIR_RootConstrainSelectedInstOperands,
     /*  17328 */     // GIR_Coverage, 14566,
     /*  17328 */     GIR_EraseRootFromParent_Done,
     /*  17329 */   // Label 337: @17329
     /*  17329 */   GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(17447), // Rule ID 2073 //
     /*  17334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17341 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17345 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17349 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17353 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17357 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17369 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17373 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17377 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17381 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17385 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17389 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17394 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17398 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17402 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17406 */     // MIs[4] Operand 1
     /*  17406 */     // No operand predicates
     /*  17406 */     // MIs[2] Operand 2
     /*  17406 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17417 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17419 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17426 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  17429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17431 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17442 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17445 */     GIR_RootConstrainSelectedInstOperands,
     /*  17446 */     // GIR_Coverage, 2073,
     /*  17446 */     GIR_EraseRootFromParent_Done,
     /*  17447 */   // Label 338: @17447
     /*  17447 */   GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(17565), // Rule ID 14528 //
     /*  17452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17459 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17463 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17467 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17471 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17475 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17479 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17483 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17487 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17491 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17495 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17499 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17503 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17507 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17512 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17516 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17520 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17524 */     // MIs[4] Operand 1
     /*  17524 */     // No operand predicates
     /*  17524 */     // MIs[2] Operand 2
     /*  17524 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17535 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17537 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17544 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (SMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_indexed),
     /*  17547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17549 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17551 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17556 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17560 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17563 */     GIR_RootConstrainSelectedInstOperands,
     /*  17564 */     // GIR_Coverage, 14528,
     /*  17564 */     GIR_EraseRootFromParent_Done,
     /*  17565 */   // Label 339: @17565
     /*  17565 */   GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(17683), // Rule ID 2125 //
     /*  17570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17577 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17597 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17605 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17609 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17613 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17617 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17621 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17625 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17630 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17634 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17638 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17642 */     // MIs[4] Operand 1
     /*  17642 */     // No operand predicates
     /*  17642 */     // MIs[2] Operand 2
     /*  17642 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17653 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17655 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17662 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  17665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17667 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17674 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17678 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17681 */     GIR_RootConstrainSelectedInstOperands,
     /*  17682 */     // GIR_Coverage, 2125,
     /*  17682 */     GIR_EraseRootFromParent_Done,
     /*  17683 */   // Label 340: @17683
     /*  17683 */   GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(17801), // Rule ID 14564 //
     /*  17688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17695 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17699 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  17703 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  17707 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17711 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17715 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17719 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17723 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17727 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17731 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17735 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17739 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17743 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17748 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17752 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17756 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17760 */     // MIs[4] Operand 1
     /*  17760 */     // No operand predicates
     /*  17760 */     // MIs[2] Operand 2
     /*  17760 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  17771 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17773 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  17780 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (UMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_indexed),
     /*  17783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17785 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  17787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  17792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17796 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17799 */     GIR_RootConstrainSelectedInstOperands,
     /*  17800 */     // GIR_Coverage, 14564,
     /*  17800 */     GIR_EraseRootFromParent_Done,
     /*  17801 */   // Label 341: @17801
     /*  17801 */   GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(17916), // Rule ID 14524 //
     /*  17806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17829 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  17833 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17837 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17841 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17845 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17849 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17853 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17857 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17862 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17866 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17870 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17874 */     // MIs[4] Operand 1
     /*  17874 */     // No operand predicates
     /*  17874 */     // MIs[2] Operand 2
     /*  17874 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  17885 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17894 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  17896 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  17896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  17899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  17901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  17903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  17907 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  17911 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  17914 */     GIR_RootConstrainSelectedInstOperands,
     /*  17915 */     // GIR_Coverage, 14524,
     /*  17915 */     GIR_EraseRootFromParent_Done,
     /*  17916 */   // Label 342: @17916
     /*  17916 */   GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(18031), // Rule ID 14523 //
     /*  17921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  17924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  17932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  17936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  17940 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  17944 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  17949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  17953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  17957 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17961 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  17965 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  17969 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  17973 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  17977 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  17982 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  17986 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  17990 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  17994 */     // MIs[4] Operand 1
     /*  17994 */     // No operand predicates
     /*  17994 */     // MIs[2] Operand 2
     /*  17994 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18009 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18011 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  18014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18016 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  18022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18026 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18029 */     GIR_RootConstrainSelectedInstOperands,
     /*  18030 */     // GIR_Coverage, 14523,
     /*  18030 */     GIR_EraseRootFromParent_Done,
     /*  18031 */   // Label 343: @18031
     /*  18031 */   GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(18146), // Rule ID 14560 //
     /*  18036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18043 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18047 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18051 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18055 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18059 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18063 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18067 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18071 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18075 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18079 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18083 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18087 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18092 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18096 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18100 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18104 */     // MIs[4] Operand 1
     /*  18104 */     // No operand predicates
     /*  18104 */     // MIs[2] Operand 2
     /*  18104 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18115 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18124 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18126 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  18129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18131 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18133 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  18137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18141 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18144 */     GIR_RootConstrainSelectedInstOperands,
     /*  18145 */     // GIR_Coverage, 14560,
     /*  18145 */     GIR_EraseRootFromParent_Done,
     /*  18146 */   // Label 344: @18146
     /*  18146 */   GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(18261), // Rule ID 14559 //
     /*  18151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  18166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18174 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18179 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  18183 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18187 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18191 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18195 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18199 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18203 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18207 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18212 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18216 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18220 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18224 */     // MIs[4] Operand 1
     /*  18224 */     // No operand predicates
     /*  18224 */     // MIs[2] Operand 2
     /*  18224 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18239 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18241 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  18244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  18252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18256 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18259 */     GIR_RootConstrainSelectedInstOperands,
     /*  18260 */     // GIR_Coverage, 14559,
     /*  18260 */     GIR_EraseRootFromParent_Done,
     /*  18261 */   // Label 345: @18261
     /*  18261 */   GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(18330), // Rule ID 1832 //
     /*  18266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  18281 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18285 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  18289 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  18293 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18297 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18299 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18306 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18313 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  18316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  18318 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18328 */     GIR_RootConstrainSelectedInstOperands,
     /*  18329 */     // GIR_Coverage, 1832,
     /*  18329 */     GIR_EraseRootFromParent_Done,
     /*  18330 */   // Label 346: @18330
     /*  18330 */   GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(18399), // Rule ID 1831 //
     /*  18335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  18350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18354 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  18358 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18362 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18366 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18368 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18375 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18382 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  18385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  18387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18397 */     GIR_RootConstrainSelectedInstOperands,
     /*  18398 */     // GIR_Coverage, 1831,
     /*  18398 */     GIR_EraseRootFromParent_Done,
     /*  18399 */   // Label 347: @18399
     /*  18399 */   GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(18468), // Rule ID 1748 //
     /*  18404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18415 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  18419 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18423 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  18427 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  18431 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18435 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18437 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18444 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18451 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i32_v2i64),
     /*  18454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  18456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18461 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18466 */     GIR_RootConstrainSelectedInstOperands,
     /*  18467 */     // GIR_Coverage, 1748,
     /*  18467 */     GIR_EraseRootFromParent_Done,
     /*  18468 */   // Label 348: @18468
     /*  18468 */   GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(18537), // Rule ID 1830 //
     /*  18473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18480 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18484 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18488 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18492 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  18496 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  18500 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18504 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18506 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18513 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18520 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  18523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  18525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18535 */     GIR_RootConstrainSelectedInstOperands,
     /*  18536 */     // GIR_Coverage, 1830,
     /*  18536 */     GIR_EraseRootFromParent_Done,
     /*  18537 */   // Label 349: @18537
     /*  18537 */   GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(18606), // Rule ID 1829 //
     /*  18542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18557 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18561 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  18565 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18569 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18573 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18575 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18582 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18589 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i32_v2i64),
     /*  18592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  18594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18604 */     GIR_RootConstrainSelectedInstOperands,
     /*  18605 */     // GIR_Coverage, 1829,
     /*  18605 */     GIR_EraseRootFromParent_Done,
     /*  18606 */   // Label 350: @18606
     /*  18606 */   GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(18685), // Rule ID 14436 //
     /*  18611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18618 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18622 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18626 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18630 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18634 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  18638 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18642 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18646 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18650 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18652 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18659 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18666 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
     /*  18669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18683 */     GIR_RootConstrainSelectedInstOperands,
     /*  18684 */     // GIR_Coverage, 14436,
     /*  18684 */     GIR_EraseRootFromParent_Done,
     /*  18685 */   // Label 351: @18685
     /*  18685 */   GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(18764), // Rule ID 14458 //
     /*  18690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  18701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  18705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18709 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18713 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  18717 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18721 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18725 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18729 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  18731 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18738 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  18745 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  18745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
     /*  18748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  18752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  18757 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  18762 */     GIR_RootConstrainSelectedInstOperands,
     /*  18763 */     // GIR_Coverage, 14458,
     /*  18763 */     GIR_EraseRootFromParent_Done,
     /*  18764 */   // Label 352: @18764
     /*  18764 */   GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(18879), // Rule ID 14522 //
     /*  18769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18776 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  18788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18792 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  18800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18804 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18808 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18812 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18816 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18820 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18824 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18829 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18833 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18837 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18841 */     // MIs[4] Operand 1
     /*  18841 */     // No operand predicates
     /*  18841 */     // MIs[2] Operand 2
     /*  18841 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18852 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18857 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18859 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  18862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18864 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18866 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  18870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18874 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18877 */     GIR_RootConstrainSelectedInstOperands,
     /*  18878 */     // GIR_Coverage, 14522,
     /*  18878 */     GIR_EraseRootFromParent_Done,
     /*  18879 */   // Label 353: @18879
     /*  18879 */   GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(18994), // Rule ID 2071 //
     /*  18884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  18887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18891 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18895 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  18899 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  18903 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  18907 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  18911 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  18916 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  18920 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  18924 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18928 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  18932 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  18936 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  18940 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  18944 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  18949 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  18953 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  18957 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  18961 */     // MIs[4] Operand 1
     /*  18961 */     // No operand predicates
     /*  18961 */     // MIs[2] Operand 2
     /*  18961 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  18972 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  18974 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  18974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  18977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  18979 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  18981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  18985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  18989 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  18992 */     GIR_RootConstrainSelectedInstOperands,
     /*  18993 */     // GIR_Coverage, 2071,
     /*  18993 */     GIR_EraseRootFromParent_Done,
     /*  18994 */   // Label 354: @18994
     /*  18994 */   GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(19109), // Rule ID 14558 //
     /*  18999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19006 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19022 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19026 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19030 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  19034 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19038 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  19042 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19046 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19050 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  19054 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19059 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  19063 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19067 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19071 */     // MIs[4] Operand 1
     /*  19071 */     // No operand predicates
     /*  19071 */     // MIs[2] Operand 2
     /*  19071 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  19082 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19087 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  19089 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19094 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19096 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19100 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  19104 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  19107 */     GIR_RootConstrainSelectedInstOperands,
     /*  19108 */     // GIR_Coverage, 14558,
     /*  19108 */     GIR_EraseRootFromParent_Done,
     /*  19109 */   // Label 355: @19109
     /*  19109 */   GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(19224), // Rule ID 2123 //
     /*  19114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19121 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19129 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19133 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19137 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19141 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19146 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19150 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  19154 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19158 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  19162 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19166 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19170 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  19174 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19179 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  19183 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19187 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19191 */     // MIs[4] Operand 1
     /*  19191 */     // No operand predicates
     /*  19191 */     // MIs[2] Operand 2
     /*  19191 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  19202 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  19204 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  19219 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  19222 */     GIR_RootConstrainSelectedInstOperands,
     /*  19223 */     // GIR_Coverage, 2123,
     /*  19223 */     GIR_EraseRootFromParent_Done,
     /*  19224 */   // Label 356: @19224
     /*  19224 */   GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(19303), // Rule ID 1736 //
     /*  19229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19240 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19244 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  19248 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19252 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19256 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  19260 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19264 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19268 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  19270 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19277 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19284 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))))  =>  (SABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i32_v2i64),
     /*  19287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19289 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19301 */     GIR_RootConstrainSelectedInstOperands,
     /*  19302 */     // GIR_Coverage, 1736,
     /*  19302 */     GIR_EraseRootFromParent_Done,
     /*  19303 */   // Label 357: @19303
     /*  19303 */   GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(19382), // Rule ID 1802 //
     /*  19308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19315 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19319 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19323 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  19327 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  19339 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19343 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19347 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  19349 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19356 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19363 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))))  =>  (UABALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i32_v2i64),
     /*  19366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19368 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19380 */     GIR_RootConstrainSelectedInstOperands,
     /*  19381 */     // GIR_Coverage, 1802,
     /*  19381 */     GIR_EraseRootFromParent_Done,
     /*  19382 */   // Label 358: @19382
     /*  19382 */   GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(19449), // Rule ID 14448 //
     /*  19387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19406 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19414 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19416 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19423 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19430 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
     /*  19433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19447 */     GIR_RootConstrainSelectedInstOperands,
     /*  19448 */     // GIR_Coverage, 14448,
     /*  19448 */     GIR_EraseRootFromParent_Done,
     /*  19449 */   // Label 359: @19449
     /*  19449 */   GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(19516), // Rule ID 14476 //
     /*  19454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19473 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19477 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19481 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19483 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19490 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19497 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
     /*  19500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19504 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19514 */     GIR_RootConstrainSelectedInstOperands,
     /*  19515 */     // GIR_Coverage, 14476,
     /*  19515 */     GIR_EraseRootFromParent_Done,
     /*  19516 */   // Label 360: @19516
     /*  19516 */   GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(19583), // Rule ID 1760 //
     /*  19521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19528 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19536 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19540 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19544 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19548 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19550 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19557 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19564 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i32_v2i64),
     /*  19567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19569 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19571 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19576 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19581 */     GIR_RootConstrainSelectedInstOperands,
     /*  19582 */     // GIR_Coverage, 1760,
     /*  19582 */     GIR_EraseRootFromParent_Done,
     /*  19583 */   // Label 361: @19583
     /*  19583 */   GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(19650), // Rule ID 1850 //
     /*  19588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19595 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  19603 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19607 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19611 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  19617 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19624 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  19631 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  19631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i32_v2i64),
     /*  19634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19636 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  19638 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  19643 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  19648 */     GIR_RootConstrainSelectedInstOperands,
     /*  19649 */     // GIR_Coverage, 1850,
     /*  19649 */     GIR_EraseRootFromParent_Done,
     /*  19650 */   // Label 362: @19650
     /*  19650 */   GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(19742), // Rule ID 14527 //
     /*  19655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19674 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19678 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19682 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19686 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19690 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19694 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19699 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19703 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19707 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19711 */     // MIs[3] Operand 1
     /*  19711 */     // No operand predicates
     /*  19711 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19716 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19720 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19722 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19737 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19740 */     GIR_RootConstrainSelectedInstOperands,
     /*  19741 */     // GIR_Coverage, 14527,
     /*  19741 */     GIR_EraseRootFromParent_Done,
     /*  19742 */   // Label 363: @19742
     /*  19742 */   GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(19834), // Rule ID 14526 //
     /*  19747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  19762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19766 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19779 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19783 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19787 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19791 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19796 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19800 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19804 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19808 */     // MIs[3] Operand 1
     /*  19808 */     // No operand predicates
     /*  19808 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19812 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19814 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  19817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19819 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  19825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19829 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19832 */     GIR_RootConstrainSelectedInstOperands,
     /*  19833 */     // GIR_Coverage, 14526,
     /*  19833 */     GIR_EraseRootFromParent_Done,
     /*  19834 */   // Label 364: @19834
     /*  19834 */   GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(19926), // Rule ID 14563 //
     /*  19839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19846 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19850 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19854 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19858 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19862 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  19866 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19870 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19874 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19878 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19883 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19887 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19891 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19895 */     // MIs[3] Operand 1
     /*  19895 */     // No operand predicates
     /*  19895 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19904 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19906 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  19909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  19911 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  19913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  19917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  19921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  19924 */     GIR_RootConstrainSelectedInstOperands,
     /*  19925 */     // GIR_Coverage, 14563,
     /*  19925 */     GIR_EraseRootFromParent_Done,
     /*  19926 */   // Label 365: @19926
     /*  19926 */   GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(20018), // Rule ID 14562 //
     /*  19931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  19934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  19942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  19946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  19950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  19954 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  19959 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  19963 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  19967 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  19971 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  19975 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19980 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  19984 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  19988 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  19992 */     // MIs[3] Operand 1
     /*  19992 */     // No operand predicates
     /*  19992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  19996 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  19998 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  19998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  20001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20005 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20013 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  20016 */     GIR_RootConstrainSelectedInstOperands,
     /*  20017 */     // GIR_Coverage, 14562,
     /*  20017 */     GIR_EraseRootFromParent_Done,
     /*  20018 */   // Label 366: @20018
     /*  20018 */   GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(20110), // Rule ID 14525 //
     /*  20023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20030 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20034 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20038 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  20042 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20046 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  20050 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  20054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  20058 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  20062 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  20066 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20071 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  20075 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20079 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  20083 */     // MIs[3] Operand 1
     /*  20083 */     // No operand predicates
     /*  20083 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20088 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  20090 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  20090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  20093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20095 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20097 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20101 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20105 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  20108 */     GIR_RootConstrainSelectedInstOperands,
     /*  20109 */     // GIR_Coverage, 14525,
     /*  20109 */     GIR_EraseRootFromParent_Done,
     /*  20110 */   // Label 367: @20110
     /*  20110 */   GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(20202), // Rule ID 2072 //
     /*  20115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20122 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20126 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20130 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  20134 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20138 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  20142 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  20155 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  20159 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  20163 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20168 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  20172 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20176 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  20180 */     // MIs[3] Operand 1
     /*  20180 */     // No operand predicates
     /*  20180 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  20182 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  20182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_indexed),
     /*  20185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20187 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20193 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  20200 */     GIR_RootConstrainSelectedInstOperands,
     /*  20201 */     // GIR_Coverage, 2072,
     /*  20201 */     GIR_EraseRootFromParent_Done,
     /*  20202 */   // Label 368: @20202
     /*  20202 */   GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(20294), // Rule ID 14561 //
     /*  20207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20214 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  20226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  20234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  20238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  20242 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  20246 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  20250 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20255 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  20259 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20263 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  20267 */     // MIs[3] Operand 1
     /*  20267 */     // No operand predicates
     /*  20267 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20272 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  20274 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  20274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  20277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20279 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20281 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20285 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20289 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  20292 */     GIR_RootConstrainSelectedInstOperands,
     /*  20293 */     // GIR_Coverage, 14561,
     /*  20293 */     GIR_EraseRootFromParent_Done,
     /*  20294 */   // Label 369: @20294
     /*  20294 */   GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(20386), // Rule ID 2124 //
     /*  20299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  20318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20322 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  20326 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  20331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  20335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  20339 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  20343 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  20347 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20352 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  20356 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  20360 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  20364 */     // MIs[3] Operand 1
     /*  20364 */     // No operand predicates
     /*  20364 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  20366 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  20366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_indexed),
     /*  20369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20371 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  20381 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  20384 */     GIR_RootConstrainSelectedInstOperands,
     /*  20385 */     // GIR_Coverage, 2124,
     /*  20385 */     GIR_EraseRootFromParent_Done,
     /*  20386 */   // Label 370: @20386
     /*  20386 */   GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(20437), // Rule ID 14470 //
     /*  20391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20414 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20416 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20423 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  20426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  20430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20435 */     GIR_RootConstrainSelectedInstOperands,
     /*  20436 */     // GIR_Coverage, 14470,
     /*  20436 */     GIR_EraseRootFromParent_Done,
     /*  20437 */   // Label 371: @20437
     /*  20437 */   GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(20488), // Rule ID 14442 //
     /*  20442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20453 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  20457 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20461 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20465 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20467 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20474 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
     /*  20477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  20481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20486 */     GIR_RootConstrainSelectedInstOperands,
     /*  20487 */     // GIR_Coverage, 14442,
     /*  20487 */     GIR_EraseRootFromParent_Done,
     /*  20488 */   // Label 372: @20488
     /*  20488 */   GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(20539), // Rule ID 14469 //
     /*  20493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20500 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20504 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20508 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20516 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20518 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20525 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  20528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20530 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  20532 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20537 */     GIR_RootConstrainSelectedInstOperands,
     /*  20538 */     // GIR_Coverage, 14469,
     /*  20538 */     GIR_EraseRootFromParent_Done,
     /*  20539 */   // Label 373: @20539
     /*  20539 */   GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(20590), // Rule ID 1844 //
     /*  20544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20551 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20555 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20559 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  20563 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20567 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20569 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20576 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  20579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20581 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  20583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20588 */     GIR_RootConstrainSelectedInstOperands,
     /*  20589 */     // GIR_Coverage, 1844,
     /*  20589 */     GIR_EraseRootFromParent_Done,
     /*  20590 */   // Label 374: @20590
     /*  20590 */   GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(20641), // Rule ID 1754 //
     /*  20595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20602 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20606 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20610 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  20614 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20618 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20620 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20627 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i32_v2i64),
     /*  20630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  20634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20639 */     GIR_RootConstrainSelectedInstOperands,
     /*  20640 */     // GIR_Coverage, 1754,
     /*  20640 */     GIR_EraseRootFromParent_Done,
     /*  20641 */   // Label 375: @20641
     /*  20641 */   GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(20692), // Rule ID 1843 //
     /*  20646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20653 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  20665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  20669 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20671 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  20678 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UADDWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  20678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i32_v2i64),
     /*  20681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  20683 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  20685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  20690 */     GIR_RootConstrainSelectedInstOperands,
     /*  20691 */     // GIR_Coverage, 1843,
     /*  20691 */     GIR_EraseRootFromParent_Done,
     /*  20692 */   // Label 376: @20692
     /*  20692 */   GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(20748), // Rule ID 14378 //
     /*  20697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20712 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20715 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  20720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20724 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20729 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20733 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20735 */     // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 685:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  20738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20742 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20746 */     GIR_RootConstrainSelectedInstOperands,
     /*  20747 */     // GIR_Coverage, 14378,
     /*  20747 */     GIR_EraseRootFromParent_Done,
     /*  20748 */   // Label 377: @20748
     /*  20748 */   GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(20804), // Rule ID 14390 //
     /*  20753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20760 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20764 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20768 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20771 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  20776 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20780 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20785 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20789 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20791 */     // (add:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 750:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  20794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20796 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20802 */     GIR_RootConstrainSelectedInstOperands,
     /*  20803 */     // GIR_Coverage, 14390,
     /*  20803 */     GIR_EraseRootFromParent_Done,
     /*  20804 */   // Label 378: @20804
     /*  20804 */   GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(20868), // Rule ID 14604 //
     /*  20809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  20824 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20828 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20833 */     // MIs[1] imm
     /*  20833 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  20836 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20845 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20849 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20851 */     // (add:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  20851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  20854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20858 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20862 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  20866 */     GIR_RootConstrainSelectedInstOperands,
     /*  20867 */     // GIR_Coverage, 14604,
     /*  20867 */     GIR_EraseRootFromParent_Done,
     /*  20868 */   // Label 379: @20868
     /*  20868 */   GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(20932), // Rule ID 14625 //
     /*  20873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  20884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  20888 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  20892 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20897 */     // MIs[1] imm
     /*  20897 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  20900 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  20905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20909 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  20913 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20915 */     // (add:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  20915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  20918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  20922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  20926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  20930 */     GIR_RootConstrainSelectedInstOperands,
     /*  20931 */     // GIR_Coverage, 14625,
     /*  20931 */     GIR_EraseRootFromParent_Done,
     /*  20932 */   // Label 380: @20932
     /*  20932 */   GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(20988), // Rule ID 1029 //
     /*  20937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20944 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  20952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  20956 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  20959 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  20964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  20968 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  20973 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  20975 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 685:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  20975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  20978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  20980 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  20982 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  20986 */     GIR_RootConstrainSelectedInstOperands,
     /*  20987 */     // GIR_Coverage, 1029,
     /*  20987 */     GIR_EraseRootFromParent_Done,
     /*  20988 */   // Label 381: @20988
     /*  20988 */   GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(21044), // Rule ID 1090 //
     /*  20993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  20996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21000 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21004 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21008 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  21012 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  21015 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  21020 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  21024 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21029 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21031 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 750:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  21031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  21034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21038 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  21042 */     GIR_RootConstrainSelectedInstOperands,
     /*  21043 */     // GIR_Coverage, 1090,
     /*  21043 */     GIR_EraseRootFromParent_Done,
     /*  21044 */   // Label 382: @21044
     /*  21044 */   GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(21108), // Rule ID 2273 //
     /*  21049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21056 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21064 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  21068 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21072 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21077 */     // MIs[1] imm
     /*  21077 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21080 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21085 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  21089 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21091 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  21094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21096 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21102 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21106 */     GIR_RootConstrainSelectedInstOperands,
     /*  21107 */     // GIR_Coverage, 2273,
     /*  21107 */     GIR_EraseRootFromParent_Done,
     /*  21108 */   // Label 383: @21108
     /*  21108 */   GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(21172), // Rule ID 2332 //
     /*  21113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21120 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21124 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21128 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  21132 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21136 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21141 */     // MIs[1] imm
     /*  21141 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21144 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21149 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  21153 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21155 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  21158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21160 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21170 */     GIR_RootConstrainSelectedInstOperands,
     /*  21171 */     // GIR_Coverage, 2332,
     /*  21171 */     GIR_EraseRootFromParent_Done,
     /*  21172 */   // Label 384: @21172
     /*  21172 */   GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(21232), // Rule ID 14591 //
     /*  21177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  21192 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21201 */     // MIs[1] imm
     /*  21201 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21204 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21213 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21215 */     // (add:{ *:[v2i64] } (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)  =>  (SRSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv2i64_shift),
     /*  21218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21222 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21226 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21230 */     GIR_RootConstrainSelectedInstOperands,
     /*  21231 */     // GIR_Coverage, 14591,
     /*  21231 */     GIR_EraseRootFromParent_Done,
     /*  21232 */   // Label 385: @21232
     /*  21232 */   GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(21292), // Rule ID 14612 //
     /*  21237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21244 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21248 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  21252 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21256 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21261 */     // MIs[1] imm
     /*  21261 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21264 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21273 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21275 */     // (add:{ *:[v2i64] } (AArch64urshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)  =>  (URSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv2i64_shift),
     /*  21278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21290 */     GIR_RootConstrainSelectedInstOperands,
     /*  21291 */     // GIR_Coverage, 14612,
     /*  21291 */     GIR_EraseRootFromParent_Done,
     /*  21292 */   // Label 386: @21292
     /*  21292 */   GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(21352), // Rule ID 2247 //
     /*  21297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21304 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21312 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  21316 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21320 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21325 */     // MIs[1] imm
     /*  21325 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21328 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21333 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21335 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))  =>  (SRSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv2i64_shift),
     /*  21338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21340 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21346 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21350 */     GIR_RootConstrainSelectedInstOperands,
     /*  21351 */     // GIR_Coverage, 2247,
     /*  21351 */     GIR_EraseRootFromParent_Done,
     /*  21352 */   // Label 387: @21352
     /*  21352 */   GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(21412), // Rule ID 2306 //
     /*  21357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21364 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  21372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  21376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21380 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21385 */     // MIs[1] imm
     /*  21385 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  21388 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  21393 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  21395 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64urshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))  =>  (URSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  21395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv2i64_shift),
     /*  21398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21400 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  21402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  21410 */     GIR_RootConstrainSelectedInstOperands,
     /*  21411 */     // GIR_Coverage, 2306,
     /*  21411 */     GIR_EraseRootFromParent_Done,
     /*  21412 */   // Label 388: @21412
     /*  21412 */   GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(21482), // Rule ID 7575 //
     /*  21417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /*  21429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  21437 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  21451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP2),
     /*  21455 */     // MIs[2] Rn
     /*  21455 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  21460 */     // MIs[2] Rm
     /*  21460 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  21465 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21467 */     // (add:{ *:[v2i64] } (AArch64zip1:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm), (AArch64zip2:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm))  =>  (ADDPv2i64:{ *:[v2i64] } ?:{ *:[v2i64] }:$Rn, ?:{ *:[v2i64] }:$Rm)
     /*  21467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /*  21470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21476 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21480 */     GIR_RootConstrainSelectedInstOperands,
     /*  21481 */     // GIR_Coverage, 7575,
     /*  21481 */     GIR_EraseRootFromParent_Done,
     /*  21482 */   // Label 389: @21482
     /*  21482 */   GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(21552), // Rule ID 15002 //
     /*  21487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21491 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21495 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /*  21499 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  21503 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  21507 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21512 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21517 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  21521 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP1),
     /*  21525 */     // MIs[2] Rn
     /*  21525 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  21530 */     // MIs[2] Rm
     /*  21530 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  21535 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21537 */     // (add:{ *:[v2i64] } (AArch64zip2:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm), (AArch64zip1:{ *:[v2i64] } FPR128:{ *:[v2i64] }:$Rn, FPR128:{ *:[v2i64] }:$Rm))  =>  (ADDPv2i64:{ *:[v2i64] } ?:{ *:[v2i64] }:$Rn, ?:{ *:[v2i64] }:$Rm)
     /*  21537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /*  21540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  21550 */     GIR_RootConstrainSelectedInstOperands,
     /*  21551 */     // GIR_Coverage, 15002,
     /*  21551 */     GIR_EraseRootFromParent_Done,
     /*  21552 */   // Label 390: @21552
     /*  21552 */   GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(21615), // Rule ID 1828 //
     /*  21557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21564 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21568 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21572 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  21585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21589 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21593 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21598 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21600 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  21603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  21613 */     GIR_RootConstrainSelectedInstOperands,
     /*  21614 */     // GIR_Coverage, 1828,
     /*  21614 */     GIR_EraseRootFromParent_Done,
     /*  21615 */   // Label 391: @21615
     /*  21615 */   GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(21678), // Rule ID 1827 //
     /*  21620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21627 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21631 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  21635 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21639 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21644 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  21648 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21652 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21656 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21661 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21663 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  21666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  21676 */     GIR_RootConstrainSelectedInstOperands,
     /*  21677 */     // GIR_Coverage, 1827,
     /*  21677 */     GIR_EraseRootFromParent_Done,
     /*  21678 */   // Label 392: @21678
     /*  21678 */   GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(21741), // Rule ID 1747 //
     /*  21683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  21698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21707 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  21711 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  21715 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21719 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21724 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21726 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv2i32_v2i64),
     /*  21729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  21731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  21735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  21739 */     GIR_RootConstrainSelectedInstOperands,
     /*  21740 */     // GIR_Coverage, 1747,
     /*  21740 */     GIR_EraseRootFromParent_Done,
     /*  21741 */   // Label 393: @21741
     /*  21741 */   GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(21814), // Rule ID 14435 //
     /*  21746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21753 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21757 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21761 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  21769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  21773 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21777 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21781 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21786 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21791 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21795 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21797 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  21800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  21808 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  21812 */     GIR_RootConstrainSelectedInstOperands,
     /*  21813 */     // GIR_Coverage, 14435,
     /*  21813 */     GIR_EraseRootFromParent_Done,
     /*  21814 */   // Label 394: @21814
     /*  21814 */   GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(21887), // Rule ID 14457 //
     /*  21819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  21822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21826 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21830 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21834 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21838 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  21842 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  21846 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21850 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  21854 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21859 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21868 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21870 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  21870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
     /*  21873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21875 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  21877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  21881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  21885 */     GIR_RootConstrainSelectedInstOperands,
     /*  21886 */     // GIR_Coverage, 14457,
     /*  21886 */     GIR_EraseRootFromParent_Done,
     /*  21887 */   // Label 395: @21887
     /*  21887 */   GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(21993), // Rule ID 14976 //
     /*  21892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  21900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  21904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21908 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  21912 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  21916 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  21920 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21929 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  21931 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vm)), V128:{ *:[v2i64] }:$Vn)  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V64:{ *:[v2i32] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  21931 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  21934 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  21938 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  21943 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  21946 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  21948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  21951 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  21955 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  21960 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  21967 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  21972 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  21977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  21980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  21982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  21984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  21988 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  21991 */     GIR_RootConstrainSelectedInstOperands,
     /*  21992 */     // GIR_Coverage, 14976,
     /*  21992 */     GIR_EraseRootFromParent_Done,
     /*  21993 */   // Label 396: @21993
     /*  21993 */   GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(22056), // Rule ID 1826 //
     /*  21998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22005 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22009 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22013 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22017 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  22026 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  22030 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22034 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22039 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22041 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  22044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22050 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  22054 */     GIR_RootConstrainSelectedInstOperands,
     /*  22055 */     // GIR_Coverage, 1826,
     /*  22055 */     GIR_EraseRootFromParent_Done,
     /*  22056 */   // Label 397: @22056
     /*  22056 */   GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(22119), // Rule ID 1825 //
     /*  22061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22068 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22072 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22076 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  22089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22093 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22097 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22102 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22104 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv2i32_v2i64),
     /*  22107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  22117 */     GIR_RootConstrainSelectedInstOperands,
     /*  22118 */     // GIR_Coverage, 1825,
     /*  22118 */     GIR_EraseRootFromParent_Done,
     /*  22119 */   // Label 398: @22119
     /*  22119 */   GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(22192), // Rule ID 1735 //
     /*  22124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22131 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22135 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22139 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22143 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  22155 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22159 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22163 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22168 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22173 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22175 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  22178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22180 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  22182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  22190 */     GIR_RootConstrainSelectedInstOperands,
     /*  22191 */     // GIR_Coverage, 1735,
     /*  22191 */     GIR_EraseRootFromParent_Done,
     /*  22192 */   // Label 399: @22192
     /*  22192 */   GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(22265), // Rule ID 1801 //
     /*  22197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22204 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22208 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22212 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22216 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  22228 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22232 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22236 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22241 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22246 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22248 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)))  =>  (UABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv2i32_v2i64),
     /*  22251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22253 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  22255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  22259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  22263 */     GIR_RootConstrainSelectedInstOperands,
     /*  22264 */     // GIR_Coverage, 1801,
     /*  22264 */     GIR_EraseRootFromParent_Done,
     /*  22265 */   // Label 400: @22265
     /*  22265 */   GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(22371), // Rule ID 6669 //
     /*  22270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22282 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22286 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22290 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  22294 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  22298 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22302 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22307 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  22309 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vm)))  =>  (SABALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V64:{ *:[v2i32] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  22309 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  22312 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  22316 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22321 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  22324 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  22326 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  22329 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  22333 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  22338 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  22345 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22350 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv2i32_v2i64),
     /*  22358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22360 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  22362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  22366 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  22369 */     GIR_RootConstrainSelectedInstOperands,
     /*  22370 */     // GIR_Coverage, 6669,
     /*  22370 */     GIR_EraseRootFromParent_Done,
     /*  22371 */   // Label 401: @22371
     /*  22371 */   GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(22432), // Rule ID 14447 //
     /*  22376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  22391 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22395 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22399 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22404 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22413 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22415 */     // (add:{ *:[v2i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*  22418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22420 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  22422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22426 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  22430 */     GIR_RootConstrainSelectedInstOperands,
     /*  22431 */     // GIR_Coverage, 14447,
     /*  22431 */     GIR_EraseRootFromParent_Done,
     /*  22432 */   // Label 402: @22432
     /*  22432 */   GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(22493), // Rule ID 14475 //
     /*  22437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  22452 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22456 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22465 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22470 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22474 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22476 */     // (add:{ *:[v2i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  22479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22481 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  22483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  22491 */     GIR_RootConstrainSelectedInstOperands,
     /*  22492 */     // GIR_Coverage, 14475,
     /*  22492 */     GIR_EraseRootFromParent_Done,
     /*  22493 */   // Label 403: @22493
     /*  22493 */   GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(22541), // Rule ID 14468 //
     /*  22498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  22513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22526 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22528 */     // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  22531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  22535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  22539 */     GIR_RootConstrainSelectedInstOperands,
     /*  22540 */     // GIR_Coverage, 14468,
     /*  22540 */     GIR_EraseRootFromParent_Done,
     /*  22541 */   // Label 404: @22541
     /*  22541 */   GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(22589), // Rule ID 14377 //
     /*  22546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22553 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22557 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  22561 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  22565 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22576 */     // (add:{ *:[v2i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  22576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  22579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22581 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  22583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22587 */     GIR_RootConstrainSelectedInstOperands,
     /*  22588 */     // GIR_Coverage, 14377,
     /*  22588 */     GIR_EraseRootFromParent_Done,
     /*  22589 */   // Label 405: @22589
     /*  22589 */   GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(22637), // Rule ID 14441 //
     /*  22594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22601 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  22609 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22613 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22622 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22624 */     // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  22627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  22631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  22635 */     GIR_RootConstrainSelectedInstOperands,
     /*  22636 */     // GIR_Coverage, 14441,
     /*  22636 */     GIR_EraseRootFromParent_Done,
     /*  22637 */   // Label 406: @22637
     /*  22637 */   GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(22685), // Rule ID 14389 //
     /*  22642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22649 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22653 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  22657 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  22661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22670 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22672 */     // (add:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn), V128:{ *:[v2i64] }:$Rd)  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  22672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  22675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  22679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22683 */     GIR_RootConstrainSelectedInstOperands,
     /*  22684 */     // GIR_Coverage, 14389,
     /*  22684 */     GIR_EraseRootFromParent_Done,
     /*  22685 */   // Label 407: @22685
     /*  22685 */   GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(22733), // Rule ID 14467 //
     /*  22690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  22701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  22705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22720 */     // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rn)  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  22723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22725 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  22727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  22731 */     GIR_RootConstrainSelectedInstOperands,
     /*  22732 */     // GIR_Coverage, 14467,
     /*  22732 */     GIR_EraseRootFromParent_Done,
     /*  22733 */   // Label 408: @22733
     /*  22733 */   GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(22794), // Rule ID 1759 //
     /*  22738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  22757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22761 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22775 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22777 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv2i32_v2i64),
     /*  22780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22782 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  22784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  22792 */     GIR_RootConstrainSelectedInstOperands,
     /*  22793 */     // GIR_Coverage, 1759,
     /*  22793 */     GIR_EraseRootFromParent_Done,
     /*  22794 */   // Label 409: @22794
     /*  22794 */   GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(22855), // Rule ID 1849 //
     /*  22799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22802 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22806 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  22818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  22826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22831 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22836 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22838 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv2i32_v2i64),
     /*  22841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  22845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  22853 */     GIR_RootConstrainSelectedInstOperands,
     /*  22854 */     // GIR_Coverage, 1849,
     /*  22854 */     GIR_EraseRootFromParent_Done,
     /*  22855 */   // Label 410: @22855
     /*  22855 */   GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(22903), // Rule ID 1842 //
     /*  22860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  22879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22883 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22888 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22890 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  22893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22895 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  22897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  22901 */     GIR_RootConstrainSelectedInstOperands,
     /*  22902 */     // GIR_Coverage, 1842,
     /*  22902 */     GIR_EraseRootFromParent_Done,
     /*  22903 */   // Label 411: @22903
     /*  22903 */   GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(22951), // Rule ID 1028 //
     /*  22908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22915 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22919 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22923 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  22927 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  22931 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22936 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22938 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (SADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  22938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv4i32_v2i64),
     /*  22941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  22943 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  22945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  22949 */     GIR_RootConstrainSelectedInstOperands,
     /*  22950 */     // GIR_Coverage, 1028,
     /*  22950 */     GIR_EraseRootFromParent_Done,
     /*  22951 */   // Label 412: @22951
     /*  22951 */   GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(22999), // Rule ID 1753 //
     /*  22956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  22959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22963 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  22967 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  22971 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  22975 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  22979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  22984 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  22986 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  22986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv2i32_v2i64),
     /*  22989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  22991 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  22993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  22997 */     GIR_RootConstrainSelectedInstOperands,
     /*  22998 */     // GIR_Coverage, 1753,
     /*  22998 */     GIR_EraseRootFromParent_Done,
     /*  22999 */   // Label 413: @22999
     /*  22999 */   GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(23047), // Rule ID 1089 //
     /*  23004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  23007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23011 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23015 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23019 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  23023 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  23027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23032 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  23034 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (UADALPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /*  23034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv4i32_v2i64),
     /*  23037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23039 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  23041 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  23045 */     GIR_RootConstrainSelectedInstOperands,
     /*  23046 */     // GIR_Coverage, 1089,
     /*  23046 */     GIR_EraseRootFromParent_Done,
     /*  23047 */   // Label 414: @23047
     /*  23047 */   GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(23095), // Rule ID 1841 //
     /*  23052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  23055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23059 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  23067 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23071 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  23075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23080 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  23082 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (UADDWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  23082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv2i32_v2i64),
     /*  23085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  23087 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  23089 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  23093 */     GIR_RootConstrainSelectedInstOperands,
     /*  23094 */     // GIR_Coverage, 1841,
     /*  23094 */     GIR_EraseRootFromParent_Done,
     /*  23095 */   // Label 415: @23095
     /*  23095 */   GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(23122), // Rule ID 1136 //
     /*  23100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  23103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23107 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23115 */     // (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  23115 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv2i64),
     /*  23120 */     GIR_RootConstrainSelectedInstOperands,
     /*  23121 */     // GIR_Coverage, 1136,
     /*  23121 */     GIR_Done,
     /*  23122 */   // Label 416: @23122
     /*  23122 */   GIM_Reject,
     /*  23123 */ // Label 333: @23123
     /*  23123 */ GIM_Reject,
     /*  23124 */ // Label 178: @23124
     /*  23124 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(27005),
     /*  23129 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  23132 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  23135 */   GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(23271), // Rule ID 5968 //
     /*  23140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23156 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23160 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23164 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23168 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23173 */     // MIs[1] Operand 2
     /*  23173 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23184 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23188 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23192 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23196 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  23200 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23204 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23208 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23213 */     // MIs[3] Operand 2
     /*  23213 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  23224 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  23226 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23226 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23229 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  23233 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23238 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23242 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  23246 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23253 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23260 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23265 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23270 */     // GIR_Coverage, 5968,
     /*  23270 */     GIR_EraseRootFromParent_Done,
     /*  23271 */   // Label 418: @23271
     /*  23271 */   GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(23407), // Rule ID 5967 //
     /*  23276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23292 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23296 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23300 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23304 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23309 */     // MIs[1] Operand 2
     /*  23309 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23320 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23324 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23328 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23332 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  23336 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23340 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23344 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23349 */     // MIs[3] Operand 2
     /*  23349 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  23360 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  23362 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23362 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23365 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  23369 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23374 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23378 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  23382 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23389 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23396 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23401 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23406 */     // GIR_Coverage, 5967,
     /*  23406 */     GIR_EraseRootFromParent_Done,
     /*  23407 */   // Label 419: @23407
     /*  23407 */   GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(23543), // Rule ID 5983 //
     /*  23412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23416 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23420 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23424 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23432 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  23436 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23440 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23445 */     // MIs[1] Operand 2
     /*  23445 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23456 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23460 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23464 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23468 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  23472 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  23476 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23480 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23485 */     // MIs[3] Operand 2
     /*  23485 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  23496 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  23498 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23498 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23501 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i8_v8i16),
     /*  23505 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23510 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23514 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  23518 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23525 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23532 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23537 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23542 */     // GIR_Coverage, 5983,
     /*  23542 */     GIR_EraseRootFromParent_Done,
     /*  23543 */   // Label 420: @23543
     /*  23543 */   GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(23679), // Rule ID 5966 //
     /*  23548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23552 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23556 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23560 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23564 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23568 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23572 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23576 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23581 */     // MIs[1] Operand 2
     /*  23581 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23592 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23596 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23600 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23604 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  23608 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  23612 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23616 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23621 */     // MIs[3] Operand 2
     /*  23621 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  23632 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  23634 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23634 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23637 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  23641 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23646 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23650 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  23654 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23661 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23668 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23673 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23678 */     // GIR_Coverage, 5966,
     /*  23678 */     GIR_EraseRootFromParent_Done,
     /*  23679 */   // Label 421: @23679
     /*  23679 */   GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(23815), // Rule ID 5965 //
     /*  23684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23700 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23704 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23708 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23712 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23717 */     // MIs[1] Operand 2
     /*  23717 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23728 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23732 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23736 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23740 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  23744 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  23748 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  23752 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23757 */     // MIs[3] Operand 2
     /*  23757 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  23768 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  23770 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  23770 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  23773 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  23777 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23782 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23786 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  23790 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23797 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23804 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23809 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23814 */     // GIR_Coverage, 5965,
     /*  23814 */     GIR_EraseRootFromParent_Done,
     /*  23815 */   // Label 422: @23815
     /*  23815 */   GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(23948), // Rule ID 15007 //
     /*  23820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  23844 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23848 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  23852 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23857 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  23861 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  23865 */     // MIs[1] Operand 2
     /*  23865 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  23876 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  23880 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  23884 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  23888 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  23892 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  23896 */     // MIs[5] Rn
     /*  23896 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  23901 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  23903 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, (undef:{ *:[v8i16] })), 0:{ *:[i64] }), (trunc:{ *:[v4i16] } (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$Rn)))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /*  23903 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  23906 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  23910 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  23915 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23919 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  23923 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  23925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  23928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  23930 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  23937 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23942 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23947 */     // GIR_Coverage, 15007,
     /*  23947 */     GIR_EraseRootFromParent_Done,
     /*  23948 */   // Label 423: @23948
     /*  23948 */   GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(24081), // Rule ID 7580 //
     /*  23953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  23957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  23961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  23965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  23969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  23973 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  23977 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23981 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  23986 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  23990 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  23994 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  23998 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  24002 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_UZP2),
     /*  24006 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  24010 */     // MIs[4] Rn
     /*  24010 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  24015 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  24019 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  24023 */     // MIs[3] Operand 2
     /*  24023 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  24034 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  24036 */     // (add:{ *:[v4i16] } (trunc:{ *:[v4i16] } (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$Rn)), (extract_subvector:{ *:[v4i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, (undef:{ *:[v8i16] })), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /*  24036 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  24039 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  24043 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24048 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  24052 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  24056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24063 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24070 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24075 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24080 */     // GIR_Coverage, 7580,
     /*  24080 */     GIR_EraseRootFromParent_Done,
     /*  24081 */   // Label 424: @24081
     /*  24081 */   GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(24244), // Rule ID 14956 //
     /*  24086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24098 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24102 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24106 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  24110 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24114 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24118 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24123 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24128 */     // MIs[1] Operand 2
     /*  24128 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24143 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24145 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24145 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24148 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24152 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24157 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24159 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24162 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24166 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24171 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24174 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  24178 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24181 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24186 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24191 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  24203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24208 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24211 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  24215 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  24219 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24226 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24233 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24238 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24243 */     // GIR_Coverage, 14956,
     /*  24243 */     GIR_EraseRootFromParent_Done,
     /*  24244 */   // Label 425: @24244
     /*  24244 */   GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(24407), // Rule ID 14953 //
     /*  24249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24253 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24257 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24261 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24265 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24269 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  24273 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24277 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24281 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24286 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24291 */     // MIs[1] Operand 2
     /*  24291 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24306 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24308 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Ra)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24308 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24311 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24315 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24320 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24322 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24325 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24329 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24334 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24337 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Ra
     /*  24341 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24344 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24349 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24354 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24359 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24362 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  24366 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24371 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24374 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  24378 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  24382 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24389 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24396 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24401 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24406 */     // GIR_Coverage, 14953,
     /*  24406 */     GIR_EraseRootFromParent_Done,
     /*  24407 */   // Label 426: @24407
     /*  24407 */   GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(24557), // Rule ID 14960 //
     /*  24412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24416 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24420 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24424 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24432 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  24436 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24440 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24445 */     // MIs[1] Operand 2
     /*  24445 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24460 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24462 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24462 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24465 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24469 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24474 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24476 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24479 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24483 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24488 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24491 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  24495 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24498 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24503 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24508 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24513 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24516 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  24520 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24525 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24528 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  24532 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24539 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24546 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24551 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24556 */     // GIR_Coverage, 14960,
     /*  24556 */     GIR_EraseRootFromParent_Done,
     /*  24557 */   // Label 427: @24557
     /*  24557 */   GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(24707), // Rule ID 14965 //
     /*  24562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24570 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24574 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24578 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24582 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  24586 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24590 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24595 */     // MIs[1] Operand 2
     /*  24595 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24606 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24610 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24612 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24612 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24615 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24619 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24624 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24626 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24629 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24633 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24638 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24641 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  24645 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24648 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24653 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24658 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24663 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24666 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  24670 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24675 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24678 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  24682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24689 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24696 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24701 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24706 */     // GIR_Coverage, 14965,
     /*  24706 */     GIR_EraseRootFromParent_Done,
     /*  24707 */   // Label 428: @24707
     /*  24707 */   GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(24857), // Rule ID 14959 //
     /*  24712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  24720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24728 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24732 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  24736 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24740 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24745 */     // MIs[1] Operand 2
     /*  24745 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24756 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24760 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24762 */     // (add:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24762 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24765 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24769 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24774 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24776 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24779 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24783 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24788 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24791 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /*  24795 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24798 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24803 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24808 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24813 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24816 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  24820 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24825 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24828 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  24832 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  24837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  24839 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  24846 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24851 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24856 */     // GIR_Coverage, 14959,
     /*  24856 */     GIR_EraseRootFromParent_Done,
     /*  24857 */   // Label 429: @24857
     /*  24857 */   GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(25020), // Rule ID 5956 //
     /*  24862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24866 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  24874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  24878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  24882 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  24886 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  24890 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  24894 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  24898 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24903 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24908 */     // MIs[1] Operand 2
     /*  24908 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  24919 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  24921 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  24921 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  24924 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  24928 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24933 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  24935 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  24938 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  24942 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24947 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  24950 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  24954 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  24957 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24962 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  24967 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  24972 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  24975 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  24979 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  24984 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  24987 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  24991 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  24995 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  24997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  25000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25002 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  25009 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25014 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25019 */     // GIR_Coverage, 5956,
     /*  25019 */     GIR_EraseRootFromParent_Done,
     /*  25020 */   // Label 430: @25020
     /*  25020 */   GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(25183), // Rule ID 5953 //
     /*  25025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25029 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25033 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25037 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25041 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  25053 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25057 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  25061 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25066 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25071 */     // MIs[1] Operand 2
     /*  25071 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  25082 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  25084 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLALv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  25084 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  25087 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  25091 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25096 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  25098 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  25101 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  25105 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25110 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  25113 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  25117 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  25120 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25125 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25130 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25135 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  25138 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  25142 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25147 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  25150 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  25154 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  25158 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  25160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  25163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25165 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  25172 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25177 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25182 */     // GIR_Coverage, 5953,
     /*  25182 */     GIR_EraseRootFromParent_Done,
     /*  25183 */   // Label 431: @25183
     /*  25183 */   GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(25333), // Rule ID 5978 //
     /*  25188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25192 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25196 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25200 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25204 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25208 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25212 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  25216 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25220 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25225 */     // MIs[1] Operand 2
     /*  25225 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  25236 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  25238 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  25238 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  25241 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  25245 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25250 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  25252 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  25255 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  25259 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25264 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  25267 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  25271 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  25274 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25279 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25284 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25289 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  25292 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  25296 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25301 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  25304 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  25308 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  25310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  25313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25315 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  25322 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25327 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25332 */     // GIR_Coverage, 5978,
     /*  25332 */     GIR_EraseRootFromParent_Done,
     /*  25333 */   // Label 432: @25333
     /*  25333 */   GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(25483), // Rule ID 5986 //
     /*  25338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25342 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25346 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25350 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25354 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25358 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25362 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  25366 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25370 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25375 */     // MIs[1] Operand 2
     /*  25375 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  25386 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  25388 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  25388 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  25391 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  25395 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25400 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  25402 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  25405 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  25409 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25414 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  25417 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  25421 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  25424 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25429 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25434 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25439 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  25442 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  25446 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25451 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  25454 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  25458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  25460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  25463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25465 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  25472 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25477 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25482 */     // GIR_Coverage, 5986,
     /*  25482 */     GIR_EraseRootFromParent_Done,
     /*  25483 */   // Label 433: @25483
     /*  25483 */   GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(25633), // Rule ID 5977 //
     /*  25488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25492 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25496 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25500 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  25504 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  25508 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  25512 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  25516 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  25520 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25525 */     // MIs[1] Operand 2
     /*  25525 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  25536 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  25538 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UADDWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  25538 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  25541 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  25545 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25550 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  25552 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  25555 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  25559 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25564 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  25567 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  25571 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  25574 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25579 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25584 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25589 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  25592 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  25596 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  25601 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  25604 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  25608 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  25610 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  25613 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25615 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  25622 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25627 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  25632 */     // GIR_Coverage, 5977,
     /*  25632 */     GIR_EraseRootFromParent_Done,
     /*  25633 */   // Label 434: @25633
     /*  25633 */   GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(25689), // Rule ID 14368 //
     /*  25638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25649 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  25653 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  25656 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  25661 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  25665 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25674 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25676 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  25679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  25687 */     GIR_RootConstrainSelectedInstOperands,
     /*  25688 */     // GIR_Coverage, 14368,
     /*  25688 */     GIR_EraseRootFromParent_Done,
     /*  25689 */   // Label 435: @25689
     /*  25689 */   GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(25745), // Rule ID 14380 //
     /*  25694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  25709 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  25712 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  25717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  25721 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25730 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25732 */     // (add:{ *:[v4i16] } (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  25735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  25743 */     GIR_RootConstrainSelectedInstOperands,
     /*  25744 */     // GIR_Coverage, 14380,
     /*  25744 */     GIR_EraseRootFromParent_Done,
     /*  25745 */   // Label 436: @25745
     /*  25745 */   GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(25809), // Rule ID 14596 //
     /*  25750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25757 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25761 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  25765 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25769 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25774 */     // MIs[1] imm
     /*  25774 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  25777 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  25782 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25786 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  25790 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25792 */     // (add:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  25792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  25795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25803 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  25807 */     GIR_RootConstrainSelectedInstOperands,
     /*  25808 */     // GIR_Coverage, 14596,
     /*  25808 */     GIR_EraseRootFromParent_Done,
     /*  25809 */   // Label 437: @25809
     /*  25809 */   GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(25873), // Rule ID 14617 //
     /*  25814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  25825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  25829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  25833 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25838 */     // MIs[1] imm
     /*  25838 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  25841 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  25846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25850 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  25854 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25856 */     // (add:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  25856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  25859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  25863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  25867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  25871 */     GIR_RootConstrainSelectedInstOperands,
     /*  25872 */     // GIR_Coverage, 14617,
     /*  25872 */     GIR_EraseRootFromParent_Done,
     /*  25873 */   // Label 438: @25873
     /*  25873 */   GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(25929), // Rule ID 1019 //
     /*  25878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25885 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  25897 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  25900 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  25905 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  25909 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25914 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25916 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  25919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25921 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  25927 */     GIR_RootConstrainSelectedInstOperands,
     /*  25928 */     // GIR_Coverage, 1019,
     /*  25928 */     GIR_EraseRootFromParent_Done,
     /*  25929 */   // Label 439: @25929
     /*  25929 */   GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(25985), // Rule ID 1080 //
     /*  25934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25941 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  25949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  25953 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  25956 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  25961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  25965 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25970 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  25972 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  25972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  25975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  25977 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  25979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  25983 */     GIR_RootConstrainSelectedInstOperands,
     /*  25984 */     // GIR_Coverage, 1080,
     /*  25984 */     GIR_EraseRootFromParent_Done,
     /*  25985 */   // Label 440: @25985
     /*  25985 */   GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(26049), // Rule ID 2265 //
     /*  25990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  25993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  25997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  26009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26013 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26018 */     // MIs[1] imm
     /*  26018 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26021 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26026 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  26030 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26032 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  26035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26037 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26043 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26047 */     GIR_RootConstrainSelectedInstOperands,
     /*  26048 */     // GIR_Coverage, 2265,
     /*  26048 */     GIR_EraseRootFromParent_Done,
     /*  26049 */   // Label 441: @26049
     /*  26049 */   GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(26113), // Rule ID 2324 //
     /*  26054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26061 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  26073 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26077 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26082 */     // MIs[1] imm
     /*  26082 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26085 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26090 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  26094 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26096 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  26099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26101 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26103 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26111 */     GIR_RootConstrainSelectedInstOperands,
     /*  26112 */     // GIR_Coverage, 2324,
     /*  26112 */     GIR_EraseRootFromParent_Done,
     /*  26113 */   // Label 442: @26113
     /*  26113 */   GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(26173), // Rule ID 14587 //
     /*  26118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26129 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  26133 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26137 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26142 */     // MIs[1] imm
     /*  26142 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26145 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26150 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26154 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26156 */     // (add:{ *:[v4i16] } (AArch64srshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)  =>  (SRSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv4i16_shift),
     /*  26159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26171 */     GIR_RootConstrainSelectedInstOperands,
     /*  26172 */     // GIR_Coverage, 14587,
     /*  26172 */     GIR_EraseRootFromParent_Done,
     /*  26173 */   // Label 443: @26173
     /*  26173 */   GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(26233), // Rule ID 14608 //
     /*  26178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26185 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26189 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  26193 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26197 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26202 */     // MIs[1] imm
     /*  26202 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26205 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26214 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26216 */     // (add:{ *:[v4i16] } (AArch64urshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)  =>  (URSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv4i16_shift),
     /*  26219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26223 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26231 */     GIR_RootConstrainSelectedInstOperands,
     /*  26232 */     // GIR_Coverage, 14608,
     /*  26232 */     GIR_EraseRootFromParent_Done,
     /*  26233 */   // Label 444: @26233
     /*  26233 */   GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(26293), // Rule ID 2243 //
     /*  26238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26245 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  26257 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26261 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26266 */     // MIs[1] imm
     /*  26266 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26269 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26274 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26276 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64srshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))  =>  (SRSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv4i16_shift),
     /*  26279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26281 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26283 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26287 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26291 */     GIR_RootConstrainSelectedInstOperands,
     /*  26292 */     // GIR_Coverage, 2243,
     /*  26292 */     GIR_EraseRootFromParent_Done,
     /*  26293 */   // Label 445: @26293
     /*  26293 */   GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(26353), // Rule ID 2302 //
     /*  26298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26305 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26309 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26313 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  26317 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26321 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26326 */     // MIs[1] imm
     /*  26326 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  26329 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  26334 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26336 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64urshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))  =>  (URSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  26336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv4i16_shift),
     /*  26339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26341 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  26351 */     GIR_RootConstrainSelectedInstOperands,
     /*  26352 */     // GIR_Coverage, 2302,
     /*  26352 */     GIR_EraseRootFromParent_Done,
     /*  26353 */   // Label 446: @26353
     /*  26353 */   GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(26414), // Rule ID 14403 //
     /*  26358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  26373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26391 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26395 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26397 */     // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  26397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  26400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26402 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  26412 */     GIR_RootConstrainSelectedInstOperands,
     /*  26413 */     // GIR_Coverage, 14403,
     /*  26413 */     GIR_EraseRootFromParent_Done,
     /*  26414 */   // Label 447: @26414
     /*  26414 */   GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(26475), // Rule ID 14409 //
     /*  26419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  26434 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26438 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26447 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26456 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26458 */     // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V64:{ *:[v4i16] }:$Rd)  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  26458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
     /*  26461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26469 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  26473 */     GIR_RootConstrainSelectedInstOperands,
     /*  26474 */     // GIR_Coverage, 14409,
     /*  26474 */     GIR_EraseRootFromParent_Done,
     /*  26475 */   // Label 448: @26475
     /*  26475 */   GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(26569), // Rule ID 14969 //
     /*  26480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26488 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  26492 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26496 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26501 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26505 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26507 */     // (add:{ *:[v4i16] } (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vm), V64:{ *:[v4i16] }:$Vn)  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  26507 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  26510 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  26514 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  26519 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  26522 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  26524 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  26527 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  26531 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  26536 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  26543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26548 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  26556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  26560 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  26564 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  26567 */     GIR_RootConstrainSelectedInstOperands,
     /*  26568 */     // GIR_Coverage, 14969,
     /*  26568 */     GIR_EraseRootFromParent_Done,
     /*  26569 */   // Label 449: @26569
     /*  26569 */   GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(26617), // Rule ID 14367 //
     /*  26574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  26589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  26593 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26602 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26604 */     // (add:{ *:[v4i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  26604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  26607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26609 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26615 */     GIR_RootConstrainSelectedInstOperands,
     /*  26616 */     // GIR_Coverage, 14367,
     /*  26616 */     GIR_EraseRootFromParent_Done,
     /*  26617 */   // Label 450: @26617
     /*  26617 */   GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(26665), // Rule ID 14379 //
     /*  26622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  26633 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  26637 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  26641 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26646 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26652 */     // (add:{ *:[v4i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn), V64:{ *:[v4i16] }:$Rd)  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  26652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  26655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  26659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26663 */     GIR_RootConstrainSelectedInstOperands,
     /*  26664 */     // GIR_Coverage, 14379,
     /*  26664 */     GIR_EraseRootFromParent_Done,
     /*  26665 */   // Label 451: @26665
     /*  26665 */   GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(26726), // Rule ID 1388 //
     /*  26670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26677 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  26689 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26693 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26697 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26707 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26709 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  26709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  26712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26714 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26716 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26720 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  26724 */     GIR_RootConstrainSelectedInstOperands,
     /*  26725 */     // GIR_Coverage, 1388,
     /*  26725 */     GIR_EraseRootFromParent_Done,
     /*  26726 */   // Label 452: @26726
     /*  26726 */   GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(26787), // Rule ID 1499 //
     /*  26731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26738 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26746 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  26750 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26754 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  26758 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26763 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26768 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26770 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  26770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i16),
     /*  26773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26775 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26777 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26781 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  26785 */     GIR_RootConstrainSelectedInstOperands,
     /*  26786 */     // GIR_Coverage, 1499,
     /*  26786 */     GIR_EraseRootFromParent_Done,
     /*  26787 */   // Label 453: @26787
     /*  26787 */   GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(26881), // Rule ID 6662 //
     /*  26792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26796 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  26808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  26812 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26817 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26819 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vn, (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vm))  =>  (SABAv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  26819 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  26822 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  26826 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  26831 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  26834 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  26836 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  26839 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  26843 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  26848 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  26855 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26860 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  26865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i16),
     /*  26868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26870 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  26872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  26876 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  26879 */     GIR_RootConstrainSelectedInstOperands,
     /*  26880 */     // GIR_Coverage, 6662,
     /*  26880 */     GIR_EraseRootFromParent_Done,
     /*  26881 */   // Label 454: @26881
     /*  26881 */   GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(26929), // Rule ID 1018 //
     /*  26886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26893 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  26905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  26909 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26914 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26916 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (SADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  26916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i8_v4i16),
     /*  26919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26921 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26927 */     GIR_RootConstrainSelectedInstOperands,
     /*  26928 */     // GIR_Coverage, 1018,
     /*  26928 */     GIR_EraseRootFromParent_Done,
     /*  26929 */   // Label 455: @26929
     /*  26929 */   GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(26977), // Rule ID 1079 //
     /*  26934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26941 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26945 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  26949 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  26953 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  26957 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26962 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  26964 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (UADALPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /*  26964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i8_v4i16),
     /*  26967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  26969 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  26971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  26975 */     GIR_RootConstrainSelectedInstOperands,
     /*  26976 */     // GIR_Coverage, 1079,
     /*  26976 */     GIR_EraseRootFromParent_Done,
     /*  26977 */   // Label 456: @26977
     /*  26977 */   GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(27004), // Rule ID 1132 //
     /*  26982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  26985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26989 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  26997 */     // (add:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  26997 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i16),
     /*  27002 */     GIR_RootConstrainSelectedInstOperands,
     /*  27003 */     // GIR_Coverage, 1132,
     /*  27003 */     GIR_Done,
     /*  27004 */   // Label 457: @27004
     /*  27004 */   GIM_Reject,
     /*  27005 */ // Label 417: @27005
     /*  27005 */ GIM_Reject,
     /*  27006 */ // Label 179: @27006
     /*  27006 */ GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(33657),
     /*  27011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  27014 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  27017 */   GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(27135), // Rule ID 14520 //
     /*  27022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27053 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27057 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27061 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27065 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27069 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27073 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27078 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27082 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27086 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27090 */     // MIs[4] Operand 1
     /*  27090 */     // No operand predicates
     /*  27090 */     // MIs[2] Operand 2
     /*  27090 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27101 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27105 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27107 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27114 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  27117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27121 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27130 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27133 */     GIR_RootConstrainSelectedInstOperands,
     /*  27134 */     // GIR_Coverage, 14520,
     /*  27134 */     GIR_EraseRootFromParent_Done,
     /*  27135 */   // Label 459: @27135
     /*  27135 */   GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(27253), // Rule ID 14521 //
     /*  27140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27155 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27159 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27163 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27167 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27171 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27175 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27179 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27183 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27187 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27191 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27196 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27200 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27204 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27208 */     // MIs[4] Operand 1
     /*  27208 */     // No operand predicates
     /*  27208 */     // MIs[2] Operand 2
     /*  27208 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27223 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27225 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27232 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  27235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27248 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27251 */     GIR_RootConstrainSelectedInstOperands,
     /*  27252 */     // GIR_Coverage, 14521,
     /*  27252 */     GIR_EraseRootFromParent_Done,
     /*  27253 */   // Label 460: @27253
     /*  27253 */   GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(27371), // Rule ID 14556 //
     /*  27258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27277 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27281 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27285 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27289 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27293 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27297 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27301 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27305 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27309 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27314 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27318 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27322 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27326 */     // MIs[4] Operand 1
     /*  27326 */     // No operand predicates
     /*  27326 */     // MIs[2] Operand 2
     /*  27326 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27341 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27343 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27350 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  27353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27366 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27369 */     GIR_RootConstrainSelectedInstOperands,
     /*  27370 */     // GIR_Coverage, 14556,
     /*  27370 */     GIR_EraseRootFromParent_Done,
     /*  27371 */   // Label 461: @27371
     /*  27371 */   GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(27489), // Rule ID 14557 //
     /*  27376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27391 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27395 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27399 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27403 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27407 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27411 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27415 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27419 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27423 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27427 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27432 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27436 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27440 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27444 */     // MIs[4] Operand 1
     /*  27444 */     // No operand predicates
     /*  27444 */     // MIs[2] Operand 2
     /*  27444 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27459 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27461 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27468 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  27471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  27475 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27484 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27487 */     GIR_RootConstrainSelectedInstOperands,
     /*  27488 */     // GIR_Coverage, 14557,
     /*  27488 */     GIR_EraseRootFromParent_Done,
     /*  27489 */   // Label 462: @27489
     /*  27489 */   GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(27607), // Rule ID 2070 //
     /*  27494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27517 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27525 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27529 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27533 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27537 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27541 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27545 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27549 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27554 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27558 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27562 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27566 */     // MIs[4] Operand 1
     /*  27566 */     // No operand predicates
     /*  27566 */     // MIs[2] Operand 2
     /*  27566 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27577 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27579 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27586 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  27589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27591 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27598 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27602 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27605 */     GIR_RootConstrainSelectedInstOperands,
     /*  27606 */     // GIR_Coverage, 2070,
     /*  27606 */     GIR_EraseRootFromParent_Done,
     /*  27607 */   // Label 463: @27607
     /*  27607 */   GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(27725), // Rule ID 14519 //
     /*  27612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27635 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27639 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27643 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27647 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27651 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27655 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27659 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27663 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27667 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27672 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27676 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27680 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27684 */     // MIs[4] Operand 1
     /*  27684 */     // No operand predicates
     /*  27684 */     // MIs[2] Operand 2
     /*  27684 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27695 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27697 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27704 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (SMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_indexed),
     /*  27707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27709 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27716 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27720 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27723 */     GIR_RootConstrainSelectedInstOperands,
     /*  27724 */     // GIR_Coverage, 14519,
     /*  27724 */     GIR_EraseRootFromParent_Done,
     /*  27725 */   // Label 464: @27725
     /*  27725 */   GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(27843), // Rule ID 2122 //
     /*  27730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27737 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27741 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27745 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27749 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27753 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27757 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  27761 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27765 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27769 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27773 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27777 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27781 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27785 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27790 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27794 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27798 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27802 */     // MIs[4] Operand 1
     /*  27802 */     // No operand predicates
     /*  27802 */     // MIs[2] Operand 2
     /*  27802 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27813 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27815 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27822 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  27825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27827 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27829 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27834 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27838 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27841 */     GIR_RootConstrainSelectedInstOperands,
     /*  27842 */     // GIR_Coverage, 2122,
     /*  27842 */     GIR_EraseRootFromParent_Done,
     /*  27843 */   // Label 465: @27843
     /*  27843 */   GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(27961), // Rule ID 14555 //
     /*  27848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27855 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27859 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  27863 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  27867 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27871 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27883 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27887 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  27891 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  27895 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  27899 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  27903 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  27908 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  27912 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  27916 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  27920 */     // MIs[4] Operand 1
     /*  27920 */     // No operand predicates
     /*  27920 */     // MIs[2] Operand 2
     /*  27920 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  27931 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  27933 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  27940 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (UMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  27940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_indexed),
     /*  27943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  27945 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  27947 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  27952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  27956 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  27959 */     GIR_RootConstrainSelectedInstOperands,
     /*  27960 */     // GIR_Coverage, 14555,
     /*  27960 */     GIR_EraseRootFromParent_Done,
     /*  27961 */   // Label 466: @27961
     /*  27961 */   GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(28076), // Rule ID 14515 //
     /*  27966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  27969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  27973 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  27977 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  27981 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  27985 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  27989 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  27993 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  27997 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28001 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  28005 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28009 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28013 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  28017 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28022 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  28026 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28030 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28034 */     // MIs[4] Operand 1
     /*  28034 */     // No operand predicates
     /*  28034 */     // MIs[2] Operand 2
     /*  28034 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  28045 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28054 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  28056 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  28067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  28071 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  28074 */     GIR_RootConstrainSelectedInstOperands,
     /*  28075 */     // GIR_Coverage, 14515,
     /*  28075 */     GIR_EraseRootFromParent_Done,
     /*  28076 */   // Label 467: @28076
     /*  28076 */   GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(28191), // Rule ID 14514 //
     /*  28081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28092 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28096 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28100 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28104 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  28113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  28117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28121 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  28125 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28129 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28133 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  28137 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28142 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  28146 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28150 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28154 */     // MIs[4] Operand 1
     /*  28154 */     // No operand predicates
     /*  28154 */     // MIs[2] Operand 2
     /*  28154 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  28165 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28169 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  28171 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  28174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  28182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  28186 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  28189 */     GIR_RootConstrainSelectedInstOperands,
     /*  28190 */     // GIR_Coverage, 14514,
     /*  28190 */     GIR_EraseRootFromParent_Done,
     /*  28191 */   // Label 468: @28191
     /*  28191 */   GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(28306), // Rule ID 14551 //
     /*  28196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28215 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28223 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  28227 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28231 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  28235 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28239 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28243 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  28247 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28252 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  28256 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28260 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28264 */     // MIs[4] Operand 1
     /*  28264 */     // No operand predicates
     /*  28264 */     // MIs[2] Operand 2
     /*  28264 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  28275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28284 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  28286 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  28289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28291 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28293 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  28297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  28301 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  28304 */     GIR_RootConstrainSelectedInstOperands,
     /*  28305 */     // GIR_Coverage, 14551,
     /*  28305 */     GIR_EraseRootFromParent_Done,
     /*  28306 */   // Label 469: @28306
     /*  28306 */   GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(28421), // Rule ID 14550 //
     /*  28311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  28326 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28330 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28334 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  28339 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  28343 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  28347 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28351 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  28355 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28359 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28363 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  28367 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28372 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  28376 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28380 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  28384 */     // MIs[4] Operand 1
     /*  28384 */     // No operand predicates
     /*  28384 */     // MIs[2] Operand 2
     /*  28384 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  28395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28399 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  28401 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  28401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  28404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  28412 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  28416 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  28419 */     GIR_RootConstrainSelectedInstOperands,
     /*  28420 */     // GIR_Coverage, 14550,
     /*  28420 */     GIR_EraseRootFromParent_Done,
     /*  28421 */   // Label 470: @28421
     /*  28421 */   GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(28490), // Rule ID 1824 //
     /*  28426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28437 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  28441 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  28449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  28453 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28457 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28459 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28466 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28473 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  28476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  28478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28483 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28488 */     GIR_RootConstrainSelectedInstOperands,
     /*  28489 */     // GIR_Coverage, 1824,
     /*  28489 */     GIR_EraseRootFromParent_Done,
     /*  28490 */   // Label 471: @28490
     /*  28490 */   GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(28559), // Rule ID 1823 //
     /*  28495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28502 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28506 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  28510 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28514 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  28518 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28522 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28526 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28528 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28535 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28542 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  28545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  28547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28557 */     GIR_RootConstrainSelectedInstOperands,
     /*  28558 */     // GIR_Coverage, 1823,
     /*  28558 */     GIR_EraseRootFromParent_Done,
     /*  28559 */   // Label 472: @28559
     /*  28559 */   GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(28628), // Rule ID 1746 //
     /*  28564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  28579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28583 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  28587 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  28591 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28595 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28597 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28604 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28611 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i16_v4i32),
     /*  28614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  28616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28621 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28626 */     GIR_RootConstrainSelectedInstOperands,
     /*  28627 */     // GIR_Coverage, 1746,
     /*  28627 */     GIR_EraseRootFromParent_Done,
     /*  28628 */   // Label 473: @28628
     /*  28628 */   GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(28697), // Rule ID 1822 //
     /*  28633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  28656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  28660 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28666 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28673 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28680 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  28683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  28685 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28690 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28695 */     GIR_RootConstrainSelectedInstOperands,
     /*  28696 */     // GIR_Coverage, 1822,
     /*  28696 */     GIR_EraseRootFromParent_Done,
     /*  28697 */   // Label 474: @28697
     /*  28697 */   GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(28766), // Rule ID 1821 //
     /*  28702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  28725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28729 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28733 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28735 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28742 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28749 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i16_v4i32),
     /*  28752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  28754 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28759 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28764 */     GIR_RootConstrainSelectedInstOperands,
     /*  28765 */     // GIR_Coverage, 1821,
     /*  28765 */     GIR_EraseRootFromParent_Done,
     /*  28766 */   // Label 475: @28766
     /*  28766 */   GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(28845), // Rule ID 14434 //
     /*  28771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28778 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28782 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28786 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  28798 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28802 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28806 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28810 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28812 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28819 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28826 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
     /*  28829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28833 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28843 */     GIR_RootConstrainSelectedInstOperands,
     /*  28844 */     // GIR_Coverage, 14434,
     /*  28844 */     GIR_EraseRootFromParent_Done,
     /*  28845 */   // Label 476: @28845
     /*  28845 */   GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(28924), // Rule ID 14456 //
     /*  28850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  28861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  28865 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28869 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28873 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  28877 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28881 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28889 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  28891 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28898 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  28905 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  28905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
     /*  28908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  28910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  28912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  28917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  28922 */     GIR_RootConstrainSelectedInstOperands,
     /*  28923 */     // GIR_Coverage, 14456,
     /*  28923 */     GIR_EraseRootFromParent_Done,
     /*  28924 */   // Label 477: @28924
     /*  28924 */   GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(29039), // Rule ID 14513 //
     /*  28929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  28932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28936 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  28940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  28944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  28948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  28952 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  28956 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  28960 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  28964 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28968 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  28972 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  28976 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  28980 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  28984 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  28989 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  28993 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  28997 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29001 */     // MIs[4] Operand 1
     /*  29001 */     // No operand predicates
     /*  29001 */     // MIs[2] Operand 2
     /*  29001 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  29012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29017 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  29019 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  29022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29024 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  29034 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  29037 */     GIR_RootConstrainSelectedInstOperands,
     /*  29038 */     // GIR_Coverage, 14513,
     /*  29038 */     GIR_EraseRootFromParent_Done,
     /*  29039 */   // Label 478: @29039
     /*  29039 */   GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(29154), // Rule ID 2068 //
     /*  29044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29051 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29055 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29059 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  29063 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29067 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29071 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  29084 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29088 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  29092 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29096 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29100 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  29104 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29109 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  29113 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29117 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29121 */     // MIs[4] Operand 1
     /*  29121 */     // No operand predicates
     /*  29121 */     // MIs[2] Operand 2
     /*  29121 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  29132 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  29134 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  29137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29139 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  29149 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  29152 */     GIR_RootConstrainSelectedInstOperands,
     /*  29153 */     // GIR_Coverage, 2068,
     /*  29153 */     GIR_EraseRootFromParent_Done,
     /*  29154 */   // Label 479: @29154
     /*  29154 */   GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(29269), // Rule ID 14549 //
     /*  29159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29166 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29170 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29174 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  29178 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29182 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  29190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  29194 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29198 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  29202 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29206 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29210 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  29214 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29219 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  29223 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29227 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29231 */     // MIs[4] Operand 1
     /*  29231 */     // No operand predicates
     /*  29231 */     // MIs[2] Operand 2
     /*  29231 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  29242 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29247 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  29249 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  29252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29254 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29260 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  29264 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  29267 */     GIR_RootConstrainSelectedInstOperands,
     /*  29268 */     // GIR_Coverage, 14549,
     /*  29268 */     GIR_EraseRootFromParent_Done,
     /*  29269 */   // Label 480: @29269
     /*  29269 */   GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(29384), // Rule ID 2120 //
     /*  29274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29277 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29281 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  29293 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29297 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29301 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29306 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29310 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  29314 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29318 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  29322 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29326 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29330 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  29334 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29339 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  29343 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29347 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29351 */     // MIs[4] Operand 1
     /*  29351 */     // No operand predicates
     /*  29351 */     // MIs[2] Operand 2
     /*  29351 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  29362 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  29364 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  29367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29369 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29371 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29375 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  29379 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  29382 */     GIR_RootConstrainSelectedInstOperands,
     /*  29383 */     // GIR_Coverage, 2120,
     /*  29383 */     GIR_EraseRootFromParent_Done,
     /*  29384 */   // Label 481: @29384
     /*  29384 */   GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(29463), // Rule ID 1734 //
     /*  29389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29396 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  29408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29412 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  29416 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  29420 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29424 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29428 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  29430 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29437 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29444 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))))  =>  (SABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i16_v4i32),
     /*  29447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29449 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29456 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29461 */     GIR_RootConstrainSelectedInstOperands,
     /*  29462 */     // GIR_Coverage, 1734,
     /*  29462 */     GIR_EraseRootFromParent_Done,
     /*  29463 */   // Label 482: @29463
     /*  29463 */   GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(29542), // Rule ID 1800 //
     /*  29468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29475 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  29487 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29491 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  29495 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  29499 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29503 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29507 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  29509 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29516 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29523 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))))  =>  (UABALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i16_v4i32),
     /*  29526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29528 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29540 */     GIR_RootConstrainSelectedInstOperands,
     /*  29541 */     // GIR_Coverage, 1800,
     /*  29541 */     GIR_EraseRootFromParent_Done,
     /*  29542 */   // Label 483: @29542
     /*  29542 */   GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(29609), // Rule ID 14446 //
     /*  29547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  29562 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29566 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29576 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29583 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29590 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
     /*  29593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29607 */     GIR_RootConstrainSelectedInstOperands,
     /*  29608 */     // GIR_Coverage, 14446,
     /*  29608 */     GIR_EraseRootFromParent_Done,
     /*  29609 */   // Label 484: @29609
     /*  29609 */   GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(29676), // Rule ID 14474 //
     /*  29614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29621 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29625 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  29629 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29633 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29641 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29643 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29650 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29657 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
     /*  29660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29664 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29674 */     GIR_RootConstrainSelectedInstOperands,
     /*  29675 */     // GIR_Coverage, 14474,
     /*  29675 */     GIR_EraseRootFromParent_Done,
     /*  29676 */   // Label 485: @29676
     /*  29676 */   GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(29743), // Rule ID 1758 //
     /*  29681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  29700 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29704 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29708 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29710 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29717 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29724 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i16_v4i32),
     /*  29727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29729 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29741 */     GIR_RootConstrainSelectedInstOperands,
     /*  29742 */     // GIR_Coverage, 1758,
     /*  29742 */     GIR_EraseRootFromParent_Done,
     /*  29743 */   // Label 486: @29743
     /*  29743 */   GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(29810), // Rule ID 1848 //
     /*  29748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29755 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  29763 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  29767 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29771 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29775 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  29777 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29784 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  29791 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  29791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i16_v4i32),
     /*  29794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29796 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  29798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  29803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  29808 */     GIR_RootConstrainSelectedInstOperands,
     /*  29809 */     // GIR_Coverage, 1848,
     /*  29809 */     GIR_EraseRootFromParent_Done,
     /*  29810 */   // Label 487: @29810
     /*  29810 */   GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(29902), // Rule ID 14518 //
     /*  29815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  29830 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29834 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29838 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  29842 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29846 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29850 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  29854 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29859 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  29863 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29867 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29871 */     // MIs[3] Operand 1
     /*  29871 */     // No operand predicates
     /*  29871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29876 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29880 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  29882 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  29885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  29893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  29897 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  29900 */     GIR_RootConstrainSelectedInstOperands,
     /*  29901 */     // GIR_Coverage, 14518,
     /*  29901 */     GIR_EraseRootFromParent_Done,
     /*  29902 */   // Label 488: @29902
     /*  29902 */   GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(29994), // Rule ID 14517 //
     /*  29907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  29910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  29918 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  29922 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  29926 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  29930 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  29935 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  29939 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  29943 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  29947 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  29951 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  29956 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  29960 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  29964 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  29968 */     // MIs[3] Operand 1
     /*  29968 */     // No operand predicates
     /*  29968 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  29972 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  29974 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  29974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  29977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  29979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  29981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  29985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  29989 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  29992 */     GIR_RootConstrainSelectedInstOperands,
     /*  29993 */     // GIR_Coverage, 14517,
     /*  29993 */     GIR_EraseRootFromParent_Done,
     /*  29994 */   // Label 489: @29994
     /*  29994 */   GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(30086), // Rule ID 14554 //
     /*  29999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  30014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  30026 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30030 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30034 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30038 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30043 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30047 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30051 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30055 */     // MIs[3] Operand 1
     /*  30055 */     // No operand predicates
     /*  30055 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30064 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30066 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  30069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30081 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30084 */     GIR_RootConstrainSelectedInstOperands,
     /*  30085 */     // GIR_Coverage, 14554,
     /*  30085 */     GIR_EraseRootFromParent_Done,
     /*  30086 */   // Label 490: @30086
     /*  30086 */   GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(30178), // Rule ID 14553 //
     /*  30091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30102 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  30106 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30110 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30114 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30119 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  30123 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30127 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30131 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30135 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30140 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30144 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30148 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30152 */     // MIs[3] Operand 1
     /*  30152 */     // No operand predicates
     /*  30152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30156 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30158 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  30161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30165 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30169 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30173 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30176 */     GIR_RootConstrainSelectedInstOperands,
     /*  30177 */     // GIR_Coverage, 14553,
     /*  30177 */     GIR_EraseRootFromParent_Done,
     /*  30178 */   // Label 491: @30178
     /*  30178 */   GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(30270), // Rule ID 14516 //
     /*  30183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30194 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30198 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  30202 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30206 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30210 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  30214 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30218 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30222 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30226 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30231 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30235 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30239 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30243 */     // MIs[3] Operand 1
     /*  30243 */     // No operand predicates
     /*  30243 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30248 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30250 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  30253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30255 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30265 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30268 */     GIR_RootConstrainSelectedInstOperands,
     /*  30269 */     // GIR_Coverage, 14516,
     /*  30269 */     GIR_EraseRootFromParent_Done,
     /*  30270 */   // Label 492: @30270
     /*  30270 */   GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(30362), // Rule ID 2069 //
     /*  30275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  30294 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30298 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  30311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30315 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30319 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30323 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30328 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30332 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30336 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30340 */     // MIs[3] Operand 1
     /*  30340 */     // No operand predicates
     /*  30340 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30342 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_indexed),
     /*  30345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30347 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30357 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30360 */     GIR_RootConstrainSelectedInstOperands,
     /*  30361 */     // GIR_Coverage, 2069,
     /*  30361 */     GIR_EraseRootFromParent_Done,
     /*  30362 */   // Label 493: @30362
     /*  30362 */   GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(30454), // Rule ID 14552 //
     /*  30367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30374 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30378 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30382 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  30386 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30390 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30394 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  30398 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30402 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30406 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30410 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30415 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30419 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30423 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30427 */     // MIs[3] Operand 1
     /*  30427 */     // No operand predicates
     /*  30427 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30432 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30434 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  30437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30439 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30441 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30449 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30452 */     GIR_RootConstrainSelectedInstOperands,
     /*  30453 */     // GIR_Coverage, 14552,
     /*  30453 */     GIR_EraseRootFromParent_Done,
     /*  30454 */   // Label 494: @30454
     /*  30454 */   GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(30546), // Rule ID 2121 //
     /*  30459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30466 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30474 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  30478 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30482 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  30486 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  30491 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  30495 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  30499 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  30503 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  30507 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  30512 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  30516 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  30520 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  30524 */     // MIs[3] Operand 1
     /*  30524 */     // No operand predicates
     /*  30524 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  30526 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (UMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  30526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_indexed),
     /*  30529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30531 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  30533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  30537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  30541 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  30544 */     GIR_RootConstrainSelectedInstOperands,
     /*  30545 */     // GIR_Coverage, 2121,
     /*  30545 */     GIR_EraseRootFromParent_Done,
     /*  30546 */   // Label 495: @30546
     /*  30546 */   GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(30597), // Rule ID 14466 //
     /*  30551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30570 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30576 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30583 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  30586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  30590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30595 */     GIR_RootConstrainSelectedInstOperands,
     /*  30596 */     // GIR_Coverage, 14466,
     /*  30596 */     GIR_EraseRootFromParent_Done,
     /*  30597 */   // Label 496: @30597
     /*  30597 */   GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(30648), // Rule ID 14440 //
     /*  30602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  30617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30625 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30627 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30634 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
     /*  30637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30639 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  30641 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30646 */     GIR_RootConstrainSelectedInstOperands,
     /*  30647 */     // GIR_Coverage, 14440,
     /*  30647 */     GIR_EraseRootFromParent_Done,
     /*  30648 */   // Label 497: @30648
     /*  30648 */   GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(30699), // Rule ID 14465 //
     /*  30653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30668 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30672 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30676 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30678 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30685 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  30688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  30692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30697 */     GIR_RootConstrainSelectedInstOperands,
     /*  30698 */     // GIR_Coverage, 14465,
     /*  30698 */     GIR_EraseRootFromParent_Done,
     /*  30699 */   // Label 498: @30699
     /*  30699 */   GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(30750), // Rule ID 1840 //
     /*  30704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30711 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  30723 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30727 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30729 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30736 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  30739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30741 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  30743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30748 */     GIR_RootConstrainSelectedInstOperands,
     /*  30749 */     // GIR_Coverage, 1840,
     /*  30749 */     GIR_EraseRootFromParent_Done,
     /*  30750 */   // Label 499: @30750
     /*  30750 */   GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(30801), // Rule ID 1752 //
     /*  30755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30762 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30766 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30770 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  30774 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30778 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30780 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30787 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i16_v4i32),
     /*  30790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30792 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  30794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30799 */     GIR_RootConstrainSelectedInstOperands,
     /*  30800 */     // GIR_Coverage, 1752,
     /*  30800 */     GIR_EraseRootFromParent_Done,
     /*  30801 */   // Label 500: @30801
     /*  30801 */   GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(30852), // Rule ID 1839 //
     /*  30806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30813 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  30821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  30825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  30829 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30831 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  30838 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UADDWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  30838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i16_v4i32),
     /*  30841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  30843 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  30845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  30850 */     GIR_RootConstrainSelectedInstOperands,
     /*  30851 */     // GIR_Coverage, 1839,
     /*  30851 */     GIR_EraseRootFromParent_Done,
     /*  30852 */   // Label 501: @30852
     /*  30852 */   GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(30908), // Rule ID 14374 //
     /*  30857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  30872 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  30875 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  30880 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  30884 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30893 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30895 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  30898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30902 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30906 */     GIR_RootConstrainSelectedInstOperands,
     /*  30907 */     // GIR_Coverage, 14374,
     /*  30907 */     GIR_EraseRootFromParent_Done,
     /*  30908 */   // Label 502: @30908
     /*  30908 */   GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(30964), // Rule ID 14386 //
     /*  30913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  30928 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  30931 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  30936 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  30940 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30945 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30949 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  30951 */     // (add:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  30951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  30954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  30956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  30958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  30962 */     GIR_RootConstrainSelectedInstOperands,
     /*  30963 */     // GIR_Coverage, 14386,
     /*  30963 */     GIR_EraseRootFromParent_Done,
     /*  30964 */   // Label 503: @30964
     /*  30964 */   GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(31028), // Rule ID 14602 //
     /*  30969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  30972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30976 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  30980 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  30984 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  30988 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  30993 */     // MIs[1] imm
     /*  30993 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  30996 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31001 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31005 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31009 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31011 */     // (add:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  31014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31016 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31026 */     GIR_RootConstrainSelectedInstOperands,
     /*  31027 */     // GIR_Coverage, 14602,
     /*  31027 */     GIR_EraseRootFromParent_Done,
     /*  31028 */   // Label 504: @31028
     /*  31028 */   GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(31092), // Rule ID 14623 //
     /*  31033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  31048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31052 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31057 */     // MIs[1] imm
     /*  31057 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31060 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31069 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31073 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31075 */     // (add:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  31078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31090 */     GIR_RootConstrainSelectedInstOperands,
     /*  31091 */     // GIR_Coverage, 14623,
     /*  31091 */     GIR_EraseRootFromParent_Done,
     /*  31092 */   // Label 505: @31092
     /*  31092 */   GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(31148), // Rule ID 1025 //
     /*  31097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31104 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31108 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31112 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  31116 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  31119 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  31124 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  31128 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31133 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31135 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  31135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  31138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31140 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31142 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  31146 */     GIR_RootConstrainSelectedInstOperands,
     /*  31147 */     // GIR_Coverage, 1025,
     /*  31147 */     GIR_EraseRootFromParent_Done,
     /*  31148 */   // Label 506: @31148
     /*  31148 */   GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(31204), // Rule ID 1086 //
     /*  31153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31160 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  31172 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  31175 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  31180 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  31184 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31189 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31191 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  31191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  31194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31196 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  31202 */     GIR_RootConstrainSelectedInstOperands,
     /*  31203 */     // GIR_Coverage, 1086,
     /*  31203 */     GIR_EraseRootFromParent_Done,
     /*  31204 */   // Label 507: @31204
     /*  31204 */   GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(31268), // Rule ID 2271 //
     /*  31209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31216 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  31228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31232 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31237 */     // MIs[1] imm
     /*  31237 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31240 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31245 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31249 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31251 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  31254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31256 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31266 */     GIR_RootConstrainSelectedInstOperands,
     /*  31267 */     // GIR_Coverage, 2271,
     /*  31267 */     GIR_EraseRootFromParent_Done,
     /*  31268 */   // Label 508: @31268
     /*  31268 */   GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(31332), // Rule ID 2330 //
     /*  31273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31280 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  31292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31301 */     // MIs[1] imm
     /*  31301 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31304 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31309 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  31313 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31315 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  31318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31326 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31330 */     GIR_RootConstrainSelectedInstOperands,
     /*  31331 */     // GIR_Coverage, 2330,
     /*  31331 */     GIR_EraseRootFromParent_Done,
     /*  31332 */   // Label 509: @31332
     /*  31332 */   GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(31392), // Rule ID 14590 //
     /*  31337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31348 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  31352 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31356 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31361 */     // MIs[1] imm
     /*  31361 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31364 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31373 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31375 */     // (add:{ *:[v4i32] } (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)  =>  (SRSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv4i32_shift),
     /*  31378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31380 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31382 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31386 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31390 */     GIR_RootConstrainSelectedInstOperands,
     /*  31391 */     // GIR_Coverage, 14590,
     /*  31391 */     GIR_EraseRootFromParent_Done,
     /*  31392 */   // Label 510: @31392
     /*  31392 */   GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(31452), // Rule ID 14611 //
     /*  31397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31404 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31408 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  31412 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31416 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31421 */     // MIs[1] imm
     /*  31421 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31424 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31433 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31435 */     // (add:{ *:[v4i32] } (AArch64urshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)  =>  (URSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv4i32_shift),
     /*  31438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31450 */     GIR_RootConstrainSelectedInstOperands,
     /*  31451 */     // GIR_Coverage, 14611,
     /*  31451 */     GIR_EraseRootFromParent_Done,
     /*  31452 */   // Label 511: @31452
     /*  31452 */   GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(31512), // Rule ID 2246 //
     /*  31457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31464 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31468 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31472 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  31476 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31480 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31485 */     // MIs[1] imm
     /*  31485 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31488 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31493 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31495 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))  =>  (SRSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv4i32_shift),
     /*  31498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31500 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31502 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31506 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31510 */     GIR_RootConstrainSelectedInstOperands,
     /*  31511 */     // GIR_Coverage, 2246,
     /*  31511 */     GIR_EraseRootFromParent_Done,
     /*  31512 */   // Label 512: @31512
     /*  31512 */   GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(31572), // Rule ID 2305 //
     /*  31517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31524 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31528 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  31532 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  31536 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31540 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31545 */     // MIs[1] imm
     /*  31545 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  31548 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  31553 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  31555 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64urshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))  =>  (URSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  31555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv4i32_shift),
     /*  31558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31560 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  31562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  31570 */     GIR_RootConstrainSelectedInstOperands,
     /*  31571 */     // GIR_Coverage, 2305,
     /*  31571 */     GIR_EraseRootFromParent_Done,
     /*  31572 */   // Label 513: @31572
     /*  31572 */   GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(31642), // Rule ID 7576 //
     /*  31577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  31589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  31597 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31602 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31607 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  31611 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  31615 */     // MIs[2] Rn
     /*  31615 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  31620 */     // MIs[2] Rm
     /*  31620 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  31625 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31627 */     // (add:{ *:[v4i32] } (AArch64uzp1:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm), (AArch64uzp2:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm))  =>  (ADDPv4i32:{ *:[v4i32] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rm)
     /*  31627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  31630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31636 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  31640 */     GIR_RootConstrainSelectedInstOperands,
     /*  31641 */     // GIR_Coverage, 7576,
     /*  31641 */     GIR_EraseRootFromParent_Done,
     /*  31642 */   // Label 514: @31642
     /*  31642 */   GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(31712), // Rule ID 15003 //
     /*  31647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  31659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  31663 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  31667 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31672 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31677 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  31681 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  31685 */     // MIs[2] Rn
     /*  31685 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  31690 */     // MIs[2] Rm
     /*  31690 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  31695 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31697 */     // (add:{ *:[v4i32] } (AArch64uzp2:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm), (AArch64uzp1:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rn, FPR128:{ *:[v4i32] }:$Rm))  =>  (ADDPv4i32:{ *:[v4i32] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rm)
     /*  31697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /*  31700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  31710 */     GIR_RootConstrainSelectedInstOperands,
     /*  31711 */     // GIR_Coverage, 15003,
     /*  31711 */     GIR_EraseRootFromParent_Done,
     /*  31712 */   // Label 515: @31712
     /*  31712 */   GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(31775), // Rule ID 1820 //
     /*  31717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  31732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31736 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31741 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  31745 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  31749 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31753 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31758 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31760 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  31763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31769 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  31773 */     GIR_RootConstrainSelectedInstOperands,
     /*  31774 */     // GIR_Coverage, 1820,
     /*  31774 */     GIR_EraseRootFromParent_Done,
     /*  31775 */   // Label 516: @31775
     /*  31775 */   GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(31838), // Rule ID 1819 //
     /*  31780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  31795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31799 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31804 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  31808 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  31812 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31821 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31823 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  31826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31828 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31832 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  31836 */     GIR_RootConstrainSelectedInstOperands,
     /*  31837 */     // GIR_Coverage, 1819,
     /*  31837 */     GIR_EraseRootFromParent_Done,
     /*  31838 */   // Label 517: @31838
     /*  31838 */   GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(31901), // Rule ID 1745 //
     /*  31843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31846 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31854 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  31858 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31862 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31867 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  31871 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  31875 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31879 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31884 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31886 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv4i16_v4i32),
     /*  31889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  31891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  31895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  31899 */     GIR_RootConstrainSelectedInstOperands,
     /*  31900 */     // GIR_Coverage, 1745,
     /*  31900 */     GIR_EraseRootFromParent_Done,
     /*  31901 */   // Label 518: @31901
     /*  31901 */   GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(31974), // Rule ID 14433 //
     /*  31906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  31921 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31925 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  31929 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  31933 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31937 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  31941 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31946 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  31951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31955 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  31957 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  31957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  31960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  31962 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  31964 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  31968 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  31972 */     GIR_RootConstrainSelectedInstOperands,
     /*  31973 */     // GIR_Coverage, 14433,
     /*  31973 */     GIR_EraseRootFromParent_Done,
     /*  31974 */   // Label 519: @31974
     /*  31974 */   GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(32047), // Rule ID 14455 //
     /*  31979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  31982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  31986 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  31990 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  31994 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  31998 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32002 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  32006 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32010 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  32014 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32019 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32028 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32030 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
     /*  32033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32037 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  32041 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  32045 */     GIR_RootConstrainSelectedInstOperands,
     /*  32046 */     // GIR_Coverage, 14455,
     /*  32046 */     GIR_EraseRootFromParent_Done,
     /*  32047 */   // Label 520: @32047
     /*  32047 */   GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(32153), // Rule ID 14975 //
     /*  32052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32068 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32072 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  32076 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32080 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32085 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32089 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32091 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vm)), V128:{ *:[v4i32] }:$Vn)  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V64:{ *:[v4i16] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  32091 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  32094 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  32098 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  32103 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  32106 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  32108 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  32111 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  32115 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  32120 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  32127 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32132 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  32140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  32144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  32148 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  32151 */     GIR_RootConstrainSelectedInstOperands,
     /*  32152 */     // GIR_Coverage, 14975,
     /*  32152 */     GIR_EraseRootFromParent_Done,
     /*  32153 */   // Label 521: @32153
     /*  32153 */   GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(32216), // Rule ID 1818 //
     /*  32158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32177 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32182 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32186 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32190 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32194 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32199 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32201 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  32204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  32214 */     GIR_RootConstrainSelectedInstOperands,
     /*  32215 */     // GIR_Coverage, 1818,
     /*  32215 */     GIR_EraseRootFromParent_Done,
     /*  32216 */   // Label 522: @32216
     /*  32216 */   GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(32279), // Rule ID 1817 //
     /*  32221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32240 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  32249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32257 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32262 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32264 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv4i16_v4i32),
     /*  32267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32269 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32273 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  32277 */     GIR_RootConstrainSelectedInstOperands,
     /*  32278 */     // GIR_Coverage, 1817,
     /*  32278 */     GIR_EraseRootFromParent_Done,
     /*  32279 */   // Label 523: @32279
     /*  32279 */   GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(32352), // Rule ID 1733 //
     /*  32284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32291 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  32315 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32319 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  32323 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32328 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32333 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32335 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  32338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32340 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  32346 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  32350 */     GIR_RootConstrainSelectedInstOperands,
     /*  32351 */     // GIR_Coverage, 1733,
     /*  32351 */     GIR_EraseRootFromParent_Done,
     /*  32352 */   // Label 524: @32352
     /*  32352 */   GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(32425), // Rule ID 1799 //
     /*  32357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32364 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32380 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32384 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  32388 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32392 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  32396 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32401 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32406 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32408 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)))  =>  (UABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv4i16_v4i32),
     /*  32411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32413 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  32415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  32419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  32423 */     GIR_RootConstrainSelectedInstOperands,
     /*  32424 */     // GIR_Coverage, 1799,
     /*  32424 */     GIR_EraseRootFromParent_Done,
     /*  32425 */   // Label 525: @32425
     /*  32425 */   GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(32531), // Rule ID 6668 //
     /*  32430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32434 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32438 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  32442 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  32446 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32450 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  32454 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  32458 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32462 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32467 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  32469 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vm)))  =>  (SABALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V64:{ *:[v4i16] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  32469 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  32472 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  32476 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  32481 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  32484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  32486 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  32489 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  32493 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  32498 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  32505 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32510 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv4i16_v4i32),
     /*  32518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32520 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  32522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  32526 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  32529 */     GIR_RootConstrainSelectedInstOperands,
     /*  32530 */     // GIR_Coverage, 6668,
     /*  32530 */     GIR_EraseRootFromParent_Done,
     /*  32531 */   // Label 526: @32531
     /*  32531 */   GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(32592), // Rule ID 14406 //
     /*  32536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32547 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  32551 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  32555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  32559 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32564 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32573 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32575 */     // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  32575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  32578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32580 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32582 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  32590 */     GIR_RootConstrainSelectedInstOperands,
     /*  32591 */     // GIR_Coverage, 14406,
     /*  32591 */     GIR_EraseRootFromParent_Done,
     /*  32592 */   // Label 527: @32592
     /*  32592 */   GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(32653), // Rule ID 14412 //
     /*  32597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32608 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  32612 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  32616 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  32620 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32625 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32630 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32634 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32636 */     // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  32636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
     /*  32639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32641 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  32651 */     GIR_RootConstrainSelectedInstOperands,
     /*  32652 */     // GIR_Coverage, 14412,
     /*  32652 */     GIR_EraseRootFromParent_Done,
     /*  32653 */   // Label 528: @32653
     /*  32653 */   GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(32714), // Rule ID 14445 //
     /*  32658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  32673 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32677 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  32681 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32686 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32695 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32697 */     // (add:{ *:[v4i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  32700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  32712 */     GIR_RootConstrainSelectedInstOperands,
     /*  32713 */     // GIR_Coverage, 14445,
     /*  32713 */     GIR_EraseRootFromParent_Done,
     /*  32714 */   // Label 529: @32714
     /*  32714 */   GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(32775), // Rule ID 14473 //
     /*  32719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  32734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  32742 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32747 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32752 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32758 */     // (add:{ *:[v4i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  32761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32769 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  32773 */     GIR_RootConstrainSelectedInstOperands,
     /*  32774 */     // GIR_Coverage, 14473,
     /*  32774 */     GIR_EraseRootFromParent_Done,
     /*  32775 */   // Label 530: @32775
     /*  32775 */   GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(32840), // Rule ID 14973 //
     /*  32780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  32792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  32796 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32801 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32805 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32807 */     // (add:{ *:[v4i32] } (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Vn)  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  32807 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  32810 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  32814 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  32819 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  32822 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  32824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  32827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  32831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  32835 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  32838 */     GIR_RootConstrainSelectedInstOperands,
     /*  32839 */     // GIR_Coverage, 14973,
     /*  32839 */     GIR_EraseRootFromParent_Done,
     /*  32840 */   // Label 531: @32840
     /*  32840 */   GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(32888), // Rule ID 14464 //
     /*  32845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  32860 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32864 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32869 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32873 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32875 */     // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  32878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  32882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  32886 */     GIR_RootConstrainSelectedInstOperands,
     /*  32887 */     // GIR_Coverage, 14464,
     /*  32887 */     GIR_EraseRootFromParent_Done,
     /*  32888 */   // Label 532: @32888
     /*  32888 */   GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(32936), // Rule ID 14373 //
     /*  32893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  32908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  32912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32917 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32921 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32923 */     // (add:{ *:[v4i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  32923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  32926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  32928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  32930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  32934 */     GIR_RootConstrainSelectedInstOperands,
     /*  32935 */     // GIR_Coverage, 14373,
     /*  32935 */     GIR_EraseRootFromParent_Done,
     /*  32936 */   // Label 533: @32936
     /*  32936 */   GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(32984), // Rule ID 14439 //
     /*  32941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  32952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  32956 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  32960 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  32965 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32969 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  32971 */     // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  32971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  32974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  32976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  32978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  32982 */     GIR_RootConstrainSelectedInstOperands,
     /*  32983 */     // GIR_Coverage, 14439,
     /*  32983 */     GIR_EraseRootFromParent_Done,
     /*  32984 */   // Label 534: @32984
     /*  32984 */   GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(33032), // Rule ID 14385 //
     /*  32989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  32992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  32996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  33004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  33008 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33017 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33019 */     // (add:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn), V128:{ *:[v4i32] }:$Rd)  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  33019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  33022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33024 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33030 */     GIR_RootConstrainSelectedInstOperands,
     /*  33031 */     // GIR_Coverage, 14385,
     /*  33031 */     GIR_EraseRootFromParent_Done,
     /*  33032 */   // Label 535: @33032
     /*  33032 */   GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(33080), // Rule ID 14463 //
     /*  33037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33065 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33067 */     // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rn)  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  33070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  33074 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  33078 */     GIR_RootConstrainSelectedInstOperands,
     /*  33079 */     // GIR_Coverage, 14463,
     /*  33079 */     GIR_EraseRootFromParent_Done,
     /*  33080 */   // Label 536: @33080
     /*  33080 */   GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(33141), // Rule ID 1391 //
     /*  33085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33092 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33096 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33100 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  33104 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  33108 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  33112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33117 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33122 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33124 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (abds:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  33124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  33127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33129 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  33139 */     GIR_RootConstrainSelectedInstOperands,
     /*  33140 */     // GIR_Coverage, 1391,
     /*  33140 */     GIR_EraseRootFromParent_Done,
     /*  33141 */   // Label 537: @33141
     /*  33141 */   GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(33202), // Rule ID 1502 //
     /*  33146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33153 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33157 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33161 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  33165 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  33169 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  33173 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33178 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33183 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33185 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (abdu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (UABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  33185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv4i32),
     /*  33188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33190 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33192 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33196 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  33200 */     GIR_RootConstrainSelectedInstOperands,
     /*  33201 */     // GIR_Coverage, 1502,
     /*  33201 */     GIR_EraseRootFromParent_Done,
     /*  33202 */   // Label 538: @33202
     /*  33202 */   GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(33263), // Rule ID 1757 //
     /*  33207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33214 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  33226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  33234 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33239 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33244 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33246 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv4i16_v4i32),
     /*  33249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33251 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  33261 */     GIR_RootConstrainSelectedInstOperands,
     /*  33262 */     // GIR_Coverage, 1757,
     /*  33262 */     GIR_EraseRootFromParent_Done,
     /*  33263 */   // Label 539: @33263
     /*  33263 */   GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(33324), // Rule ID 1847 //
     /*  33268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33275 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  33287 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  33295 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33300 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33305 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33307 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv4i16_v4i32),
     /*  33310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33312 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  33322 */     GIR_RootConstrainSelectedInstOperands,
     /*  33323 */     // GIR_Coverage, 1847,
     /*  33323 */     GIR_EraseRootFromParent_Done,
     /*  33324 */   // Label 540: @33324
     /*  33324 */   GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(33389), // Rule ID 6666 //
     /*  33329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33333 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33337 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33341 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  33345 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  33349 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33354 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33356 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm))  =>  (SABAv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  33356 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  33359 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  33363 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  33368 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  33371 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  33373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv4i32),
     /*  33376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  33380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  33384 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  33387 */     GIR_RootConstrainSelectedInstOperands,
     /*  33388 */     // GIR_Coverage, 6666,
     /*  33388 */     GIR_EraseRootFromParent_Done,
     /*  33389 */   // Label 541: @33389
     /*  33389 */   GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(33437), // Rule ID 1838 //
     /*  33394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  33413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33417 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33422 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33424 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  33427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33429 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33431 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  33435 */     GIR_RootConstrainSelectedInstOperands,
     /*  33436 */     // GIR_Coverage, 1838,
     /*  33436 */     GIR_EraseRootFromParent_Done,
     /*  33437 */   // Label 542: @33437
     /*  33437 */   GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(33485), // Rule ID 1024 //
     /*  33442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33449 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33453 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33457 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  33461 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  33465 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33470 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33472 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (SADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  33472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv8i16_v4i32),
     /*  33475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33477 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33479 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33483 */     GIR_RootConstrainSelectedInstOperands,
     /*  33484 */     // GIR_Coverage, 1024,
     /*  33484 */     GIR_EraseRootFromParent_Done,
     /*  33485 */   // Label 543: @33485
     /*  33485 */   GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(33533), // Rule ID 1751 //
     /*  33490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33497 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  33509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33513 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33518 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33520 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv4i16_v4i32),
     /*  33523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33525 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  33531 */     GIR_RootConstrainSelectedInstOperands,
     /*  33532 */     // GIR_Coverage, 1751,
     /*  33532 */     GIR_EraseRootFromParent_Done,
     /*  33533 */   // Label 544: @33533
     /*  33533 */   GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(33581), // Rule ID 1085 //
     /*  33538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33545 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33549 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33553 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  33557 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  33561 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33566 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33568 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (UADALPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /*  33568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv8i16_v4i32),
     /*  33571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33573 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  33575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33579 */     GIR_RootConstrainSelectedInstOperands,
     /*  33580 */     // GIR_Coverage, 1085,
     /*  33580 */     GIR_EraseRootFromParent_Done,
     /*  33581 */   // Label 545: @33581
     /*  33581 */   GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(33629), // Rule ID 1837 //
     /*  33586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33593 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  33601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  33605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  33609 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33614 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33616 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (UADDWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  33616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv4i16_v4i32),
     /*  33619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  33621 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  33623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  33627 */     GIR_RootConstrainSelectedInstOperands,
     /*  33628 */     // GIR_Coverage, 1837,
     /*  33628 */     GIR_EraseRootFromParent_Done,
     /*  33629 */   // Label 546: @33629
     /*  33629 */   GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(33656), // Rule ID 1135 //
     /*  33634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33641 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33649 */     // (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  33649 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv4i32),
     /*  33654 */     GIR_RootConstrainSelectedInstOperands,
     /*  33655 */     // GIR_Coverage, 1135,
     /*  33655 */     GIR_Done,
     /*  33656 */   // Label 547: @33656
     /*  33656 */   GIM_Reject,
     /*  33657 */ // Label 458: @33657
     /*  33657 */ GIM_Reject,
     /*  33658 */ // Label 180: @33658
     /*  33658 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(34891),
     /*  33663 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33666 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  33669 */   GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(33802), // Rule ID 15008 //
     /*  33674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  33686 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  33690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  33698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  33702 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  33706 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33711 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  33715 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  33719 */     // MIs[1] Operand 2
     /*  33719 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  33730 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  33734 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  33738 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  33742 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  33746 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  33750 */     // MIs[5] Rn
     /*  33750 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  33755 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  33757 */     // (add:{ *:[v8i8] } (extract_subvector:{ *:[v8i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, (undef:{ *:[v16i8] })), 0:{ *:[i64] }), (trunc:{ *:[v8i8] } (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$Rn)))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /*  33757 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  33760 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  33764 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  33769 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  33773 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  33777 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  33779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  33782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33784 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  33791 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33796 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33801 */     // GIR_Coverage, 15008,
     /*  33801 */     GIR_EraseRootFromParent_Done,
     /*  33802 */   // Label 549: @33802
     /*  33802 */   GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(33935), // Rule ID 7581 //
     /*  33807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33811 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33815 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  33819 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  33823 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  33827 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /*  33831 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  33835 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33840 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  33844 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  33848 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  33852 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  33856 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_UZP2),
     /*  33860 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  33864 */     // MIs[4] Rn
     /*  33864 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  33869 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  33873 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /*  33877 */     // MIs[3] Operand 2
     /*  33877 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  33888 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /*  33890 */     // (add:{ *:[v8i8] } (trunc:{ *:[v8i8] } (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$Rn)), (extract_subvector:{ *:[v8i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, (undef:{ *:[v16i8] })), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /*  33890 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  33893 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  33897 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  33902 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  33906 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  33910 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  33912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  33915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33917 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  33924 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33929 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  33934 */     // GIR_Coverage, 7581,
     /*  33934 */     GIR_EraseRootFromParent_Done,
     /*  33935 */   // Label 550: @33935
     /*  33935 */   GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(33999), // Rule ID 14592 //
     /*  33940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  33943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33947 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  33951 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  33955 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  33959 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33964 */     // MIs[1] imm
     /*  33964 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  33967 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  33972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  33976 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  33980 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  33982 */     // (add:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  33982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  33985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  33987 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  33989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  33993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  33997 */     GIR_RootConstrainSelectedInstOperands,
     /*  33998 */     // GIR_Coverage, 14592,
     /*  33998 */     GIR_EraseRootFromParent_Done,
     /*  33999 */   // Label 551: @33999
     /*  33999 */   GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(34063), // Rule ID 14613 //
     /*  34004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  34019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34023 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34028 */     // MIs[1] imm
     /*  34028 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34031 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34036 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34040 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34044 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34046 */     // (add:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  34049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34053 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34061 */     GIR_RootConstrainSelectedInstOperands,
     /*  34062 */     // GIR_Coverage, 14613,
     /*  34062 */     GIR_EraseRootFromParent_Done,
     /*  34063 */   // Label 552: @34063
     /*  34063 */   GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(34127), // Rule ID 2261 //
     /*  34068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  34087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34091 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34096 */     // MIs[1] imm
     /*  34096 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34099 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34104 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34108 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34110 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  34113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34115 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34125 */     GIR_RootConstrainSelectedInstOperands,
     /*  34126 */     // GIR_Coverage, 2261,
     /*  34126 */     GIR_EraseRootFromParent_Done,
     /*  34127 */   // Label 553: @34127
     /*  34127 */   GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(34191), // Rule ID 2320 //
     /*  34132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34139 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  34151 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34155 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34160 */     // MIs[1] imm
     /*  34160 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34163 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34168 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  34172 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34174 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  34177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34179 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34181 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34189 */     GIR_RootConstrainSelectedInstOperands,
     /*  34190 */     // GIR_Coverage, 2320,
     /*  34190 */     GIR_EraseRootFromParent_Done,
     /*  34191 */   // Label 554: @34191
     /*  34191 */   GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(34251), // Rule ID 14585 //
     /*  34196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  34211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34220 */     // MIs[1] imm
     /*  34220 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34223 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34232 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34234 */     // (add:{ *:[v8i8] } (AArch64srshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)  =>  (SRSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv8i8_shift),
     /*  34237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34239 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34245 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34249 */     GIR_RootConstrainSelectedInstOperands,
     /*  34250 */     // GIR_Coverage, 14585,
     /*  34250 */     GIR_EraseRootFromParent_Done,
     /*  34251 */   // Label 555: @34251
     /*  34251 */   GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(34311), // Rule ID 14606 //
     /*  34256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  34271 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34280 */     // MIs[1] imm
     /*  34280 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34283 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34294 */     // (add:{ *:[v8i8] } (AArch64urshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)  =>  (URSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv8i8_shift),
     /*  34297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34299 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34309 */     GIR_RootConstrainSelectedInstOperands,
     /*  34310 */     // GIR_Coverage, 14606,
     /*  34310 */     GIR_EraseRootFromParent_Done,
     /*  34311 */   // Label 556: @34311
     /*  34311 */   GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(34371), // Rule ID 2241 //
     /*  34316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34323 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34327 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34331 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  34335 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34339 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34344 */     // MIs[1] imm
     /*  34344 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34347 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34352 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34354 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64srshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))  =>  (SRSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv8i8_shift),
     /*  34357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34359 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34365 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34369 */     GIR_RootConstrainSelectedInstOperands,
     /*  34370 */     // GIR_Coverage, 2241,
     /*  34370 */     GIR_EraseRootFromParent_Done,
     /*  34371 */   // Label 557: @34371
     /*  34371 */   GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(34431), // Rule ID 2300 //
     /*  34376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34383 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  34395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34399 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34404 */     // MIs[1] imm
     /*  34404 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  34407 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  34412 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34414 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64urshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))  =>  (URSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  34414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv8i8_shift),
     /*  34417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34419 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  34429 */     GIR_RootConstrainSelectedInstOperands,
     /*  34430 */     // GIR_Coverage, 2300,
     /*  34430 */     GIR_EraseRootFromParent_Done,
     /*  34431 */   // Label 558: @34431
     /*  34431 */   GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(34492), // Rule ID 14401 //
     /*  34436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34443 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34447 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  34451 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34455 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  34459 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34464 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34469 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34473 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34475 */     // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  34478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34482 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34486 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34490 */     GIR_RootConstrainSelectedInstOperands,
     /*  34491 */     // GIR_Coverage, 14401,
     /*  34491 */     GIR_EraseRootFromParent_Done,
     /*  34492 */   // Label 559: @34492
     /*  34492 */   GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(34553), // Rule ID 14407 //
     /*  34497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  34512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  34520 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34525 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34534 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34536 */     // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V64:{ *:[v8i8] }:$Rd)  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
     /*  34539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34541 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  34543 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34547 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34551 */     GIR_RootConstrainSelectedInstOperands,
     /*  34552 */     // GIR_Coverage, 14407,
     /*  34552 */     GIR_EraseRootFromParent_Done,
     /*  34553 */   // Label 560: @34553
     /*  34553 */   GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(34647), // Rule ID 14968 //
     /*  34558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  34570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34574 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34579 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34583 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34585 */     // (add:{ *:[v8i8] } (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vm), V64:{ *:[v8i8] }:$Vn)  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  34585 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  34588 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  34592 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  34597 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  34600 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  34602 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  34605 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  34609 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  34614 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  34621 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34626 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  34634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  34638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  34642 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  34645 */     GIR_RootConstrainSelectedInstOperands,
     /*  34646 */     // GIR_Coverage, 14968,
     /*  34646 */     GIR_EraseRootFromParent_Done,
     /*  34647 */   // Label 561: @34647
     /*  34647 */   GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(34708), // Rule ID 1386 //
     /*  34652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34659 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  34671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34675 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  34679 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34689 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34691 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  34694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34696 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34706 */     GIR_RootConstrainSelectedInstOperands,
     /*  34707 */     // GIR_Coverage, 1386,
     /*  34707 */     GIR_EraseRootFromParent_Done,
     /*  34708 */   // Label 562: @34708
     /*  34708 */   GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(34769), // Rule ID 1497 //
     /*  34713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34720 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  34732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34736 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  34740 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34745 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34752 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i8),
     /*  34755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34757 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  34759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  34763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  34767 */     GIR_RootConstrainSelectedInstOperands,
     /*  34768 */     // GIR_Coverage, 1497,
     /*  34768 */     GIR_EraseRootFromParent_Done,
     /*  34769 */   // Label 563: @34769
     /*  34769 */   GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(34863), // Rule ID 6661 //
     /*  34774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34778 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  34786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  34790 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34794 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34799 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  34801 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vn, (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vm))  =>  (SABAv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  34801 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  34804 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  34808 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  34813 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  34816 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  34818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  34821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  34825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  34830 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  34837 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34842 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i8),
     /*  34850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  34852 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  34854 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  34858 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  34861 */     GIR_RootConstrainSelectedInstOperands,
     /*  34862 */     // GIR_Coverage, 6661,
     /*  34862 */     GIR_EraseRootFromParent_Done,
     /*  34863 */   // Label 564: @34863
     /*  34863 */   GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(34890), // Rule ID 1130 //
     /*  34868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  34883 */     // (add:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  34883 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i8),
     /*  34888 */     GIR_RootConstrainSelectedInstOperands,
     /*  34889 */     // GIR_Coverage, 1130,
     /*  34889 */     GIR_Done,
     /*  34890 */   // Label 565: @34890
     /*  34890 */   GIM_Reject,
     /*  34891 */ // Label 548: @34891
     /*  34891 */ GIM_Reject,
     /*  34892 */ // Label 181: @34892
     /*  34892 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(38943),
     /*  34897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  34900 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  34903 */   GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(34972), // Rule ID 1816 //
     /*  34908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34927 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  34931 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34935 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34939 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  34941 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  34948 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  34955 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  34955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  34958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  34960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  34965 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  34970 */     GIR_RootConstrainSelectedInstOperands,
     /*  34971 */     // GIR_Coverage, 1816,
     /*  34971 */     GIR_EraseRootFromParent_Done,
     /*  34972 */   // Label 567: @34972
     /*  34972 */   GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(35041), // Rule ID 1815 //
     /*  34977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  34980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  34984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  34988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  34992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  34996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35004 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35008 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35010 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35017 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35024 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  35027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35039 */     GIR_RootConstrainSelectedInstOperands,
     /*  35040 */     // GIR_Coverage, 1815,
     /*  35040 */     GIR_EraseRootFromParent_Done,
     /*  35041 */   // Label 568: @35041
     /*  35041 */   GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(35110), // Rule ID 1744 //
     /*  35046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  35061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  35073 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35077 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35079 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35086 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35093 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv16i8_v8i16),
     /*  35096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35103 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35108 */     GIR_RootConstrainSelectedInstOperands,
     /*  35109 */     // GIR_Coverage, 1744,
     /*  35109 */     GIR_EraseRootFromParent_Done,
     /*  35110 */   // Label 569: @35110
     /*  35110 */   GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(35179), // Rule ID 1814 //
     /*  35115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35134 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35138 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  35142 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35146 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35148 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35155 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35162 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  35165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35167 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35172 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35177 */     GIR_RootConstrainSelectedInstOperands,
     /*  35178 */     // GIR_Coverage, 1814,
     /*  35178 */     GIR_EraseRootFromParent_Done,
     /*  35179 */   // Label 570: @35179
     /*  35179 */   GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(35248), // Rule ID 1813 //
     /*  35184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35191 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35195 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35199 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35203 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  35207 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35211 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35215 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35217 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35224 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35231 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv16i8_v8i16),
     /*  35234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35246 */     GIR_RootConstrainSelectedInstOperands,
     /*  35247 */     // GIR_Coverage, 1813,
     /*  35247 */     GIR_EraseRootFromParent_Done,
     /*  35248 */   // Label 571: @35248
     /*  35248 */   GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(35327), // Rule ID 14432 //
     /*  35253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35260 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35264 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35268 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35272 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  35276 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  35280 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35284 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35292 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35294 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35301 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35308 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
     /*  35311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35325 */     GIR_RootConstrainSelectedInstOperands,
     /*  35326 */     // GIR_Coverage, 14432,
     /*  35326 */     GIR_EraseRootFromParent_Done,
     /*  35327 */   // Label 572: @35327
     /*  35327 */   GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(35406), // Rule ID 14454 //
     /*  35332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35351 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  35355 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  35359 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35363 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35371 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35373 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35380 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35387 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
     /*  35390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35399 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35404 */     GIR_RootConstrainSelectedInstOperands,
     /*  35405 */     // GIR_Coverage, 14454,
     /*  35405 */     GIR_EraseRootFromParent_Done,
     /*  35406 */   // Label 573: @35406
     /*  35406 */   GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(35485), // Rule ID 1732 //
     /*  35411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35434 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  35438 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  35442 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35446 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35452 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35459 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35466 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))))  =>  (SABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv16i8_v8i16),
     /*  35469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35471 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35473 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35478 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35483 */     GIR_RootConstrainSelectedInstOperands,
     /*  35484 */     // GIR_Coverage, 1732,
     /*  35484 */     GIR_EraseRootFromParent_Done,
     /*  35485 */   // Label 574: @35485
     /*  35485 */   GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(35564), // Rule ID 1798 //
     /*  35490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35497 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35513 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  35517 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  35521 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35525 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35529 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  35531 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35538 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35545 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))))  =>  (UABALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv16i8_v8i16),
     /*  35548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35550 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35562 */     GIR_RootConstrainSelectedInstOperands,
     /*  35563 */     // GIR_Coverage, 1798,
     /*  35563 */     GIR_EraseRootFromParent_Done,
     /*  35564 */   // Label 575: @35564
     /*  35564 */   GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(35631), // Rule ID 14444 //
     /*  35569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35576 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35580 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  35584 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35588 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35592 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35596 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35598 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35605 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35612 */     // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
     /*  35615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35629 */     GIR_RootConstrainSelectedInstOperands,
     /*  35630 */     // GIR_Coverage, 14444,
     /*  35630 */     GIR_EraseRootFromParent_Done,
     /*  35631 */   // Label 576: @35631
     /*  35631 */   GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(35698), // Rule ID 14472 //
     /*  35636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35643 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35647 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  35651 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35655 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35659 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35663 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35665 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35672 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35679 */     // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
     /*  35682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35684 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  35686 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35696 */     GIR_RootConstrainSelectedInstOperands,
     /*  35697 */     // GIR_Coverage, 14472,
     /*  35697 */     GIR_EraseRootFromParent_Done,
     /*  35698 */   // Label 577: @35698
     /*  35698 */   GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(35765), // Rule ID 1756 //
     /*  35703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35710 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35714 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35718 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  35722 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35726 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35730 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35732 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35739 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35746 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv16i8_v8i16),
     /*  35749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35751 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35753 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35763 */     GIR_RootConstrainSelectedInstOperands,
     /*  35764 */     // GIR_Coverage, 1756,
     /*  35764 */     GIR_EraseRootFromParent_Done,
     /*  35765 */   // Label 578: @35765
     /*  35765 */   GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(35832), // Rule ID 1846 //
     /*  35770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35777 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  35785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  35789 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35793 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  35797 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35799 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35806 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35813 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UMLALv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv16i8_v8i16),
     /*  35816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  35818 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  35820 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  35825 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  35830 */     GIR_RootConstrainSelectedInstOperands,
     /*  35831 */     // GIR_Coverage, 1846,
     /*  35831 */     GIR_EraseRootFromParent_Done,
     /*  35832 */   // Label 579: @35832
     /*  35832 */   GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(35883), // Rule ID 14462 //
     /*  35837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  35852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35856 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35860 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35862 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35869 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  35872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35874 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  35881 */     GIR_RootConstrainSelectedInstOperands,
     /*  35882 */     // GIR_Coverage, 14462,
     /*  35882 */     GIR_EraseRootFromParent_Done,
     /*  35883 */   // Label 580: @35883
     /*  35883 */   GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(35934), // Rule ID 14438 //
     /*  35888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35895 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35899 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  35903 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35907 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35911 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35913 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35920 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
     /*  35923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  35932 */     GIR_RootConstrainSelectedInstOperands,
     /*  35933 */     // GIR_Coverage, 14438,
     /*  35933 */     GIR_EraseRootFromParent_Done,
     /*  35934 */   // Label 581: @35934
     /*  35934 */   GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(35985), // Rule ID 14461 //
     /*  35939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35946 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  35950 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  35954 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  35958 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35962 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  35964 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  35971 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  35971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  35974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  35976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  35978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  35983 */     GIR_RootConstrainSelectedInstOperands,
     /*  35984 */     // GIR_Coverage, 14461,
     /*  35984 */     GIR_EraseRootFromParent_Done,
     /*  35985 */   // Label 582: @35985
     /*  35985 */   GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(36036), // Rule ID 1836 //
     /*  35990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  35993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  35997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  36009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  36013 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36015 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  36022 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  36025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36027 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  36029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  36034 */     GIR_RootConstrainSelectedInstOperands,
     /*  36035 */     // GIR_Coverage, 1836,
     /*  36035 */     GIR_EraseRootFromParent_Done,
     /*  36036 */   // Label 583: @36036
     /*  36036 */   GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(36087), // Rule ID 1750 //
     /*  36041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36048 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  36060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  36064 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36066 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  36073 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv16i8_v8i16),
     /*  36076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36078 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  36080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  36085 */     GIR_RootConstrainSelectedInstOperands,
     /*  36086 */     // GIR_Coverage, 1750,
     /*  36086 */     GIR_EraseRootFromParent_Done,
     /*  36087 */   // Label 584: @36087
     /*  36087 */   GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(36138), // Rule ID 1835 //
     /*  36092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36099 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36103 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36107 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  36111 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  36115 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36117 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  36124 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UADDWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  36124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv16i8_v8i16),
     /*  36127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36129 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  36131 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  36136 */     GIR_RootConstrainSelectedInstOperands,
     /*  36137 */     // GIR_Coverage, 1835,
     /*  36137 */     GIR_EraseRootFromParent_Done,
     /*  36138 */   // Label 585: @36138
     /*  36138 */   GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(36194), // Rule ID 14370 //
     /*  36143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36158 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  36161 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  36166 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36170 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36179 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36181 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  36181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  36184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36188 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36192 */     GIR_RootConstrainSelectedInstOperands,
     /*  36193 */     // GIR_Coverage, 14370,
     /*  36193 */     GIR_EraseRootFromParent_Done,
     /*  36194 */   // Label 586: @36194
     /*  36194 */   GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(36250), // Rule ID 14382 //
     /*  36199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36214 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  36217 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  36222 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36237 */     // (add:{ *:[v8i16] } (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  36237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  36240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36248 */     GIR_RootConstrainSelectedInstOperands,
     /*  36249 */     // GIR_Coverage, 14382,
     /*  36249 */     GIR_EraseRootFromParent_Done,
     /*  36250 */   // Label 587: @36250
     /*  36250 */   GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(36314), // Rule ID 14598 //
     /*  36255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  36270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36274 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36279 */     // MIs[1] imm
     /*  36279 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36282 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36287 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36291 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36295 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36297 */     // (add:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  36300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36312 */     GIR_RootConstrainSelectedInstOperands,
     /*  36313 */     // GIR_Coverage, 14598,
     /*  36313 */     GIR_EraseRootFromParent_Done,
     /*  36314 */   // Label 588: @36314
     /*  36314 */   GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(36378), // Rule ID 14619 //
     /*  36319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  36334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36338 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36343 */     // MIs[1] imm
     /*  36343 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36346 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36355 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36359 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36361 */     // (add:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  36364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36368 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36372 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36376 */     GIR_RootConstrainSelectedInstOperands,
     /*  36377 */     // GIR_Coverage, 14619,
     /*  36377 */     GIR_EraseRootFromParent_Done,
     /*  36378 */   // Label 589: @36378
     /*  36378 */   GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(36434), // Rule ID 1021 //
     /*  36383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36390 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36402 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  36405 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /*  36410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36419 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36421 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  36421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  36424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36426 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36432 */     GIR_RootConstrainSelectedInstOperands,
     /*  36433 */     // GIR_Coverage, 1021,
     /*  36433 */     GIR_EraseRootFromParent_Done,
     /*  36434 */   // Label 590: @36434
     /*  36434 */   GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(36490), // Rule ID 1082 //
     /*  36439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  36458 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  36461 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /*  36466 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  36470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36475 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36477 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  36477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  36480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36482 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36484 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  36488 */     GIR_RootConstrainSelectedInstOperands,
     /*  36489 */     // GIR_Coverage, 1082,
     /*  36489 */     GIR_EraseRootFromParent_Done,
     /*  36490 */   // Label 591: @36490
     /*  36490 */   GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(36554), // Rule ID 2267 //
     /*  36495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36502 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36506 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36510 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  36514 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36518 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36523 */     // MIs[1] imm
     /*  36523 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36526 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36531 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36535 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36537 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  36540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36542 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36552 */     GIR_RootConstrainSelectedInstOperands,
     /*  36553 */     // GIR_Coverage, 2267,
     /*  36553 */     GIR_EraseRootFromParent_Done,
     /*  36554 */   // Label 592: @36554
     /*  36554 */   GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(36618), // Rule ID 2326 //
     /*  36559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36566 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36574 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  36578 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36582 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36587 */     // MIs[1] imm
     /*  36587 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36590 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36595 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  36599 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36601 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  36604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36606 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36616 */     GIR_RootConstrainSelectedInstOperands,
     /*  36617 */     // GIR_Coverage, 2326,
     /*  36617 */     GIR_EraseRootFromParent_Done,
     /*  36618 */   // Label 593: @36618
     /*  36618 */   GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(36678), // Rule ID 14588 //
     /*  36623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  36638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36642 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36647 */     // MIs[1] imm
     /*  36647 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36650 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36659 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36661 */     // (add:{ *:[v8i16] } (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)  =>  (SRSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv8i16_shift),
     /*  36664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36676 */     GIR_RootConstrainSelectedInstOperands,
     /*  36677 */     // GIR_Coverage, 14588,
     /*  36677 */     GIR_EraseRootFromParent_Done,
     /*  36678 */   // Label 594: @36678
     /*  36678 */   GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(36738), // Rule ID 14609 //
     /*  36683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  36698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36707 */     // MIs[1] imm
     /*  36707 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36710 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36715 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36719 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36721 */     // (add:{ *:[v8i16] } (AArch64urshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)  =>  (URSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv8i16_shift),
     /*  36724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  36728 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36736 */     GIR_RootConstrainSelectedInstOperands,
     /*  36737 */     // GIR_Coverage, 14609,
     /*  36737 */     GIR_EraseRootFromParent_Done,
     /*  36738 */   // Label 595: @36738
     /*  36738 */   GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(36798), // Rule ID 2244 //
     /*  36743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36750 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  36762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36766 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36771 */     // MIs[1] imm
     /*  36771 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36774 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36779 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36781 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))  =>  (SRSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv8i16_shift),
     /*  36784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36786 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36796 */     GIR_RootConstrainSelectedInstOperands,
     /*  36797 */     // GIR_Coverage, 2244,
     /*  36797 */     GIR_EraseRootFromParent_Done,
     /*  36798 */   // Label 596: @36798
     /*  36798 */   GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(36858), // Rule ID 2303 //
     /*  36803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  36806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  36818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  36822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36831 */     // MIs[1] imm
     /*  36831 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  36834 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  36839 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  36841 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64urshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))  =>  (URSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  36841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv8i16_shift),
     /*  36844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  36846 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  36848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  36856 */     GIR_RootConstrainSelectedInstOperands,
     /*  36857 */     // GIR_Coverage, 2303,
     /*  36857 */     GIR_EraseRootFromParent_Done,
     /*  36858 */   // Label 597: @36858
     /*  36858 */   GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(36928), // Rule ID 7577 //
     /*  36863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  36875 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36879 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  36883 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36888 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36893 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  36897 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  36901 */     // MIs[2] Rn
     /*  36901 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  36906 */     // MIs[2] Rm
     /*  36906 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  36911 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36913 */     // (add:{ *:[v8i16] } (AArch64uzp1:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm), (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm))  =>  (ADDPv8i16:{ *:[v8i16] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rm)
     /*  36913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  36916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  36926 */     GIR_RootConstrainSelectedInstOperands,
     /*  36927 */     // GIR_Coverage, 7577,
     /*  36927 */     GIR_EraseRootFromParent_Done,
     /*  36928 */   // Label 598: @36928
     /*  36928 */   GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(36998), // Rule ID 15004 //
     /*  36933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  36941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  36945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  36949 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  36953 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36958 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  36963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  36967 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  36971 */     // MIs[2] Rn
     /*  36971 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  36976 */     // MIs[2] Rm
     /*  36976 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  36981 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  36983 */     // (add:{ *:[v8i16] } (AArch64uzp2:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm), (AArch64uzp1:{ *:[v8i16] } FPR128:{ *:[v8i16] }:$Rn, FPR128:{ *:[v8i16] }:$Rm))  =>  (ADDPv8i16:{ *:[v8i16] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rm)
     /*  36983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /*  36986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  36988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  36992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  36996 */     GIR_RootConstrainSelectedInstOperands,
     /*  36997 */     // GIR_Coverage, 15004,
     /*  36997 */     GIR_EraseRootFromParent_Done,
     /*  36998 */   // Label 599: @36998
     /*  36998 */   GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(37061), // Rule ID 1812 //
     /*  37003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  37018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  37031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  37035 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37044 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37046 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  37049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  37059 */     GIR_RootConstrainSelectedInstOperands,
     /*  37060 */     // GIR_Coverage, 1812,
     /*  37060 */     GIR_EraseRootFromParent_Done,
     /*  37061 */   // Label 600: @37061
     /*  37061 */   GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(37124), // Rule ID 1811 //
     /*  37066 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37077 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  37081 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37085 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  37094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37098 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37102 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37107 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37109 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  37112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  37122 */     GIR_RootConstrainSelectedInstOperands,
     /*  37123 */     // GIR_Coverage, 1811,
     /*  37123 */     GIR_EraseRootFromParent_Done,
     /*  37124 */   // Label 601: @37124
     /*  37124 */   GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(37187), // Rule ID 1743 //
     /*  37129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37136 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37140 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  37144 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37148 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  37157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  37161 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37165 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37170 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37172 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLv8i8_v8i16),
     /*  37175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37177 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37181 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  37185 */     GIR_RootConstrainSelectedInstOperands,
     /*  37186 */     // GIR_Coverage, 1743,
     /*  37186 */     GIR_EraseRootFromParent_Done,
     /*  37187 */   // Label 602: @37187
     /*  37187 */   GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(37260), // Rule ID 14431 //
     /*  37192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37211 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37215 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  37219 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37223 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  37227 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37232 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37241 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37243 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  37246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  37250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  37254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  37258 */     GIR_RootConstrainSelectedInstOperands,
     /*  37259 */     // GIR_Coverage, 14431,
     /*  37259 */     GIR_EraseRootFromParent_Done,
     /*  37260 */   // Label 603: @37260
     /*  37260 */   GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(37333), // Rule ID 14453 //
     /*  37265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37280 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  37292 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37296 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  37300 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37305 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37310 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37314 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37316 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)), V128:{ *:[v8i16] }:$Rd)  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
     /*  37319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37321 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  37323 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  37327 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  37331 */     GIR_RootConstrainSelectedInstOperands,
     /*  37332 */     // GIR_Coverage, 14453,
     /*  37332 */     GIR_EraseRootFromParent_Done,
     /*  37333 */   // Label 604: @37333
     /*  37333 */   GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(37439), // Rule ID 14974 //
     /*  37338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37354 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37358 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  37362 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37366 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37371 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37375 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37377 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vm)), V128:{ *:[v8i16] }:$Vn)  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V64:{ *:[v8i8] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  37377 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  37380 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  37384 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37389 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  37392 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  37394 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37397 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37401 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37406 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  37413 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37418 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  37426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  37430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  37434 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  37437 */     GIR_RootConstrainSelectedInstOperands,
     /*  37438 */     // GIR_Coverage, 14974,
     /*  37438 */     GIR_EraseRootFromParent_Done,
     /*  37439 */   // Label 605: @37439
     /*  37439 */   GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(37502), // Rule ID 1810 //
     /*  37444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37451 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37455 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37459 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37463 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37468 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  37472 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  37476 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37480 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37485 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37487 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  37490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  37500 */     GIR_RootConstrainSelectedInstOperands,
     /*  37501 */     // GIR_Coverage, 1810,
     /*  37501 */     GIR_EraseRootFromParent_Done,
     /*  37502 */   // Label 606: @37502
     /*  37502 */   GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(37565), // Rule ID 1809 //
     /*  37507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37518 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37522 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37526 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37531 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  37535 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37539 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37543 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37548 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37550 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLv8i8_v8i16),
     /*  37553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  37555 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  37563 */     GIR_RootConstrainSelectedInstOperands,
     /*  37564 */     // GIR_Coverage, 1809,
     /*  37564 */     GIR_EraseRootFromParent_Done,
     /*  37565 */   // Label 607: @37565
     /*  37565 */   GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(37638), // Rule ID 1731 //
     /*  37570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37577 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37593 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37597 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  37601 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37605 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  37609 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37614 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37619 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37621 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  37624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37626 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  37628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  37632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  37636 */     GIR_RootConstrainSelectedInstOperands,
     /*  37637 */     // GIR_Coverage, 1731,
     /*  37637 */     GIR_EraseRootFromParent_Done,
     /*  37638 */   // Label 608: @37638
     /*  37638 */   GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(37711), // Rule ID 1797 //
     /*  37643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37650 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37662 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37666 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37670 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  37674 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37678 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  37682 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37687 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37692 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37694 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)))  =>  (UABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALv8i8_v8i16),
     /*  37697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37699 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  37701 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  37705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  37709 */     GIR_RootConstrainSelectedInstOperands,
     /*  37710 */     // GIR_Coverage, 1797,
     /*  37710 */     GIR_EraseRootFromParent_Done,
     /*  37711 */   // Label 609: @37711
     /*  37711 */   GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(37817), // Rule ID 6667 //
     /*  37716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37720 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  37728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  37732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  37740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  37744 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37748 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37753 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  37755 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vm)))  =>  (SABALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V64:{ *:[v8i8] }:$Vm, (EXTRACT_SUBREG:{ *:[i64] } (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /*  37755 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  37758 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  37762 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37767 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /*  37770 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  37772 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  37775 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  37779 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  37784 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  37791 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37796 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALv8i8_v8i16),
     /*  37804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37806 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  37808 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /*  37812 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  37815 */     GIR_RootConstrainSelectedInstOperands,
     /*  37816 */     // GIR_Coverage, 6667,
     /*  37816 */     GIR_EraseRootFromParent_Done,
     /*  37817 */   // Label 610: @37817
     /*  37817 */   GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(37878), // Rule ID 14404 //
     /*  37822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37829 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37833 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  37837 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  37841 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  37845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37850 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37855 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37859 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  37861 */     // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  37861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  37864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  37868 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  37876 */     GIR_RootConstrainSelectedInstOperands,
     /*  37877 */     // GIR_Coverage, 14404,
     /*  37877 */     GIR_EraseRootFromParent_Done,
     /*  37878 */   // Label 611: @37878
     /*  37878 */   GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(37939), // Rule ID 14410 //
     /*  37883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  37898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  37902 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  37906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37911 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37916 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37920 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  37922 */     // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  37922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
     /*  37925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  37929 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37933 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  37937 */     GIR_RootConstrainSelectedInstOperands,
     /*  37938 */     // GIR_Coverage, 14410,
     /*  37938 */     GIR_EraseRootFromParent_Done,
     /*  37939 */   // Label 612: @37939
     /*  37939 */   GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(38000), // Rule ID 14443 //
     /*  37944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  37947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  37955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  37959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  37963 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  37967 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37972 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  37977 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  37981 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  37983 */     // (add:{ *:[v8i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  37983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  37986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  37988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  37990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  37994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  37998 */     GIR_RootConstrainSelectedInstOperands,
     /*  37999 */     // GIR_Coverage, 14443,
     /*  37999 */     GIR_EraseRootFromParent_Done,
     /*  38000 */   // Label 613: @38000
     /*  38000 */   GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(38061), // Rule ID 14471 //
     /*  38005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38012 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38016 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  38020 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38024 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  38028 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38042 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38044 */     // (add:{ *:[v8i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rd)  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  38047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38049 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  38051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  38059 */     GIR_RootConstrainSelectedInstOperands,
     /*  38060 */     // GIR_Coverage, 14471,
     /*  38060 */     GIR_EraseRootFromParent_Done,
     /*  38061 */   // Label 614: @38061
     /*  38061 */   GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(38126), // Rule ID 14972 //
     /*  38066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38070 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38074 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  38078 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  38082 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38087 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38091 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38093 */     // (add:{ *:[v8i16] } (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Vn)  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  38093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  38096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  38100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38105 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  38108 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  38113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  38117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  38121 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  38124 */     GIR_RootConstrainSelectedInstOperands,
     /*  38125 */     // GIR_Coverage, 14972,
     /*  38125 */     GIR_EraseRootFromParent_Done,
     /*  38126 */   // Label 615: @38126
     /*  38126 */   GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(38174), // Rule ID 14460 //
     /*  38131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  38146 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38150 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38159 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38161 */     // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  38164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38166 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  38168 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38172 */     GIR_RootConstrainSelectedInstOperands,
     /*  38173 */     // GIR_Coverage, 14460,
     /*  38173 */     GIR_EraseRootFromParent_Done,
     /*  38174 */   // Label 616: @38174
     /*  38174 */   GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(38222), // Rule ID 14369 //
     /*  38179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  38194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38209 */     // (add:{ *:[v8i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  38209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  38212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  38216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38220 */     GIR_RootConstrainSelectedInstOperands,
     /*  38221 */     // GIR_Coverage, 14369,
     /*  38221 */     GIR_EraseRootFromParent_Done,
     /*  38222 */   // Label 617: @38222
     /*  38222 */   GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(38270), // Rule ID 14437 //
     /*  38227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  38242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38246 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38251 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38255 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38257 */     // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  38260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  38264 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38268 */     GIR_RootConstrainSelectedInstOperands,
     /*  38269 */     // GIR_Coverage, 14437,
     /*  38269 */     GIR_EraseRootFromParent_Done,
     /*  38270 */   // Label 618: @38270
     /*  38270 */   GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(38318), // Rule ID 14381 //
     /*  38275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  38290 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38294 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38303 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38305 */     // (add:{ *:[v8i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn), V128:{ *:[v8i16] }:$Rd)  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  38305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  38308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  38312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38316 */     GIR_RootConstrainSelectedInstOperands,
     /*  38317 */     // GIR_Coverage, 14381,
     /*  38317 */     GIR_EraseRootFromParent_Done,
     /*  38318 */   // Label 619: @38318
     /*  38318 */   GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(38366), // Rule ID 14459 //
     /*  38323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  38338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38342 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38347 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38351 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38353 */     // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), V128:{ *:[v8i16] }:$Rn)  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  38356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  38360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38364 */     GIR_RootConstrainSelectedInstOperands,
     /*  38365 */     // GIR_Coverage, 14459,
     /*  38365 */     GIR_EraseRootFromParent_Done,
     /*  38366 */   // Label 620: @38366
     /*  38366 */   GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(38427), // Rule ID 1389 //
     /*  38371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38378 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38382 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38386 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  38390 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  38394 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  38398 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38403 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38408 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38410 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (abds:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  38410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  38413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38415 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38417 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  38425 */     GIR_RootConstrainSelectedInstOperands,
     /*  38426 */     // GIR_Coverage, 1389,
     /*  38426 */     GIR_EraseRootFromParent_Done,
     /*  38427 */   // Label 621: @38427
     /*  38427 */   GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(38488), // Rule ID 1500 //
     /*  38432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38439 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38443 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38447 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  38451 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  38455 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  38459 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38464 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38469 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38471 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (abdu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (UABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  38471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv8i16),
     /*  38474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38476 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38482 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  38486 */     GIR_RootConstrainSelectedInstOperands,
     /*  38487 */     // GIR_Coverage, 1500,
     /*  38487 */     GIR_EraseRootFromParent_Done,
     /*  38488 */   // Label 622: @38488
     /*  38488 */   GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(38549), // Rule ID 1755 //
     /*  38493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38500 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  38512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  38520 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38525 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38530 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38532 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALv8i8_v8i16),
     /*  38535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38537 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38543 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  38547 */     GIR_RootConstrainSelectedInstOperands,
     /*  38548 */     // GIR_Coverage, 1755,
     /*  38548 */     GIR_EraseRootFromParent_Done,
     /*  38549 */   // Label 623: @38549
     /*  38549 */   GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(38610), // Rule ID 1845 //
     /*  38554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38561 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  38573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  38581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38586 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38591 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38593 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLALv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALv8i8_v8i16),
     /*  38596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38598 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38600 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  38608 */     GIR_RootConstrainSelectedInstOperands,
     /*  38609 */     // GIR_Coverage, 1845,
     /*  38609 */     GIR_EraseRootFromParent_Done,
     /*  38610 */   // Label 624: @38610
     /*  38610 */   GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(38675), // Rule ID 6665 //
     /*  38615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38619 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  38631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  38635 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38640 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38642 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm))  =>  (SABAv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  38642 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  38645 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  38649 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  38654 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  38657 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  38659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv8i16),
     /*  38662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38664 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  38666 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  38670 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  38673 */     GIR_RootConstrainSelectedInstOperands,
     /*  38674 */     // GIR_Coverage, 6665,
     /*  38674 */     GIR_EraseRootFromParent_Done,
     /*  38675 */   // Label 625: @38675
     /*  38675 */   GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(38723), // Rule ID 1834 //
     /*  38680 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38687 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38691 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38695 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  38699 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38703 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38708 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38710 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  38713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38715 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38717 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38721 */     GIR_RootConstrainSelectedInstOperands,
     /*  38722 */     // GIR_Coverage, 1834,
     /*  38722 */     GIR_EraseRootFromParent_Done,
     /*  38723 */   // Label 626: @38723
     /*  38723 */   GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(38771), // Rule ID 1020 //
     /*  38728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38735 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38739 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38743 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /*  38747 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38751 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38758 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (SADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  38758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALPv16i8_v8i16),
     /*  38761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38763 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38769 */     GIR_RootConstrainSelectedInstOperands,
     /*  38770 */     // GIR_Coverage, 1020,
     /*  38770 */     GIR_EraseRootFromParent_Done,
     /*  38771 */   // Label 627: @38771
     /*  38771 */   GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(38819), // Rule ID 1749 //
     /*  38776 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38783 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  38795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38799 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38804 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38806 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDWv8i8_v8i16),
     /*  38809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38811 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38813 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38817 */     GIR_RootConstrainSelectedInstOperands,
     /*  38818 */     // GIR_Coverage, 1749,
     /*  38818 */     GIR_EraseRootFromParent_Done,
     /*  38819 */   // Label 628: @38819
     /*  38819 */   GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(38867), // Rule ID 1081 //
     /*  38824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38831 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /*  38843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38847 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38852 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38854 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (UADALPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /*  38854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALPv16i8_v8i16),
     /*  38857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  38859 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  38861 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  38865 */     GIR_RootConstrainSelectedInstOperands,
     /*  38866 */     // GIR_Coverage, 1081,
     /*  38866 */     GIR_EraseRootFromParent_Done,
     /*  38867 */   // Label 629: @38867
     /*  38867 */   GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(38915), // Rule ID 1833 //
     /*  38872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38879 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38883 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  38887 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  38891 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  38895 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  38900 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  38902 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (UADDWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  38902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDWv8i8_v8i16),
     /*  38905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  38907 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  38909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  38913 */     GIR_RootConstrainSelectedInstOperands,
     /*  38914 */     // GIR_Coverage, 1833,
     /*  38914 */     GIR_EraseRootFromParent_Done,
     /*  38915 */   // Label 630: @38915
     /*  38915 */   GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(38942), // Rule ID 1133 //
     /*  38920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38927 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38931 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38935 */     // (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  38935 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv8i16),
     /*  38940 */     GIR_RootConstrainSelectedInstOperands,
     /*  38941 */     // GIR_Coverage, 1133,
     /*  38941 */     GIR_Done,
     /*  38942 */   // Label 631: @38942
     /*  38942 */   GIM_Reject,
     /*  38943 */ // Label 566: @38943
     /*  38943 */ GIM_Reject,
     /*  38944 */ // Label 182: @38944
     /*  38944 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(39993),
     /*  38949 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38952 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  38955 */   GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(39019), // Rule ID 14594 //
     /*  38960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  38963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38967 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  38971 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  38975 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  38979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38984 */     // MIs[1] imm
     /*  38984 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  38987 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  38992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  38996 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  39000 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39002 */     // (add:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  39005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39013 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39017 */     GIR_RootConstrainSelectedInstOperands,
     /*  39018 */     // GIR_Coverage, 14594,
     /*  39018 */     GIR_EraseRootFromParent_Done,
     /*  39019 */   // Label 633: @39019
     /*  39019 */   GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(39083), // Rule ID 14615 //
     /*  39024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  39039 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39043 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39048 */     // MIs[1] imm
     /*  39048 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39051 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39056 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39060 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  39064 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39066 */     // (add:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  39069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39081 */     GIR_RootConstrainSelectedInstOperands,
     /*  39082 */     // GIR_Coverage, 14615,
     /*  39082 */     GIR_EraseRootFromParent_Done,
     /*  39083 */   // Label 634: @39083
     /*  39083 */   GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(39147), // Rule ID 2263 //
     /*  39088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39095 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  39107 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39111 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39116 */     // MIs[1] imm
     /*  39116 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39119 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39124 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  39128 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39130 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  39133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39135 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39145 */     GIR_RootConstrainSelectedInstOperands,
     /*  39146 */     // GIR_Coverage, 2263,
     /*  39146 */     GIR_EraseRootFromParent_Done,
     /*  39147 */   // Label 635: @39147
     /*  39147 */   GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(39211), // Rule ID 2322 //
     /*  39152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39163 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39167 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  39171 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39175 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39180 */     // MIs[1] imm
     /*  39180 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39183 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39188 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  39192 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39194 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  39197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39199 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39209 */     GIR_RootConstrainSelectedInstOperands,
     /*  39210 */     // GIR_Coverage, 2322,
     /*  39210 */     GIR_EraseRootFromParent_Done,
     /*  39211 */   // Label 636: @39211
     /*  39211 */   GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(39271), // Rule ID 14586 //
     /*  39216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  39231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39235 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39240 */     // MIs[1] imm
     /*  39240 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39243 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39248 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39252 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39254 */     // (add:{ *:[v16i8] } (AArch64srshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)  =>  (SRSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv16i8_shift),
     /*  39257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39269 */     GIR_RootConstrainSelectedInstOperands,
     /*  39270 */     // GIR_Coverage, 14586,
     /*  39270 */     GIR_EraseRootFromParent_Done,
     /*  39271 */   // Label 637: @39271
     /*  39271 */   GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(39331), // Rule ID 14607 //
     /*  39276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  39291 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39295 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39300 */     // MIs[1] imm
     /*  39300 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39303 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39312 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39314 */     // (add:{ *:[v16i8] } (AArch64urshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)  =>  (URSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv16i8_shift),
     /*  39317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39329 */     GIR_RootConstrainSelectedInstOperands,
     /*  39330 */     // GIR_Coverage, 14607,
     /*  39330 */     GIR_EraseRootFromParent_Done,
     /*  39331 */   // Label 638: @39331
     /*  39331 */   GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(39391), // Rule ID 2242 //
     /*  39336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39343 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39347 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39351 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /*  39355 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39359 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39364 */     // MIs[1] imm
     /*  39364 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39367 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39372 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39374 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64srshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))  =>  (SRSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRAv16i8_shift),
     /*  39377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39379 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39381 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39389 */     GIR_RootConstrainSelectedInstOperands,
     /*  39390 */     // GIR_Coverage, 2242,
     /*  39390 */     GIR_EraseRootFromParent_Done,
     /*  39391 */   // Label 639: @39391
     /*  39391 */   GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(39451), // Rule ID 2301 //
     /*  39396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39403 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39407 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39411 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /*  39415 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39419 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39424 */     // MIs[1] imm
     /*  39424 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  39427 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  39432 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39434 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64urshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))  =>  (URSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  39434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRAv16i8_shift),
     /*  39437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39439 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39441 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  39449 */     GIR_RootConstrainSelectedInstOperands,
     /*  39450 */     // GIR_Coverage, 2301,
     /*  39450 */     GIR_EraseRootFromParent_Done,
     /*  39451 */   // Label 640: @39451
     /*  39451 */   GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(39521), // Rule ID 7578 //
     /*  39456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39464 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /*  39468 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39472 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39476 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39481 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39486 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  39490 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /*  39494 */     // MIs[2] Rn
     /*  39494 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  39499 */     // MIs[2] Rm
     /*  39499 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  39504 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  39506 */     // (add:{ *:[v16i8] } (AArch64uzp1:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm), (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm))  =>  (ADDPv16i8:{ *:[v16i8] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm)
     /*  39506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  39509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39511 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39515 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39519 */     GIR_RootConstrainSelectedInstOperands,
     /*  39520 */     // GIR_Coverage, 7578,
     /*  39520 */     GIR_EraseRootFromParent_Done,
     /*  39521 */   // Label 641: @39521
     /*  39521 */   GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(39591), // Rule ID 15005 //
     /*  39526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /*  39538 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39546 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39551 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  39560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /*  39564 */     // MIs[2] Rn
     /*  39564 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  39569 */     // MIs[2] Rm
     /*  39569 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  39574 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  39576 */     // (add:{ *:[v16i8] } (AArch64uzp2:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm), (AArch64uzp1:{ *:[v16i8] } FPR128:{ *:[v16i8] }:$Rn, FPR128:{ *:[v16i8] }:$Rm))  =>  (ADDPv16i8:{ *:[v16i8] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm)
     /*  39576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /*  39579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  39581 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39589 */     GIR_RootConstrainSelectedInstOperands,
     /*  39590 */     // GIR_Coverage, 15005,
     /*  39590 */     GIR_EraseRootFromParent_Done,
     /*  39591 */   // Label 642: @39591
     /*  39591 */   GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(39652), // Rule ID 14402 //
     /*  39596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  39611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39615 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39619 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39624 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39629 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39633 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39635 */     // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  39635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  39638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39650 */     GIR_RootConstrainSelectedInstOperands,
     /*  39651 */     // GIR_Coverage, 14402,
     /*  39651 */     GIR_EraseRootFromParent_Done,
     /*  39652 */   // Label 643: @39652
     /*  39652 */   GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(39713), // Rule ID 14408 //
     /*  39657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  39672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39676 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39680 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39685 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39694 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39696 */     // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), V128:{ *:[v16i8] }:$Rd)  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  39696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
     /*  39699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  39703 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39707 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39711 */     GIR_RootConstrainSelectedInstOperands,
     /*  39712 */     // GIR_Coverage, 14408,
     /*  39712 */     GIR_EraseRootFromParent_Done,
     /*  39713 */   // Label 644: @39713
     /*  39713 */   GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(39778), // Rule ID 14971 //
     /*  39718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  39726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  39730 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39734 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39739 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39743 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39745 */     // (add:{ *:[v16i8] } (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Vn)  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  39745 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  39748 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  39752 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39757 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  39760 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  39765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  39769 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  39773 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39776 */     GIR_RootConstrainSelectedInstOperands,
     /*  39777 */     // GIR_Coverage, 14971,
     /*  39777 */     GIR_EraseRootFromParent_Done,
     /*  39778 */   // Label 645: @39778
     /*  39778 */   GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(39839), // Rule ID 1387 //
     /*  39783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39790 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /*  39802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39806 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39810 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39815 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39820 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39822 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (abds:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  39822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  39825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39827 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39833 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39837 */     GIR_RootConstrainSelectedInstOperands,
     /*  39838 */     // GIR_Coverage, 1387,
     /*  39838 */     GIR_EraseRootFromParent_Done,
     /*  39839 */   // Label 646: @39839
     /*  39839 */   GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(39900), // Rule ID 1498 //
     /*  39844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39851 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39859 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /*  39863 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39867 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  39871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39876 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39881 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39883 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (abdu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))  =>  (UABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  39883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABAv16i8),
     /*  39886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39888 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  39890 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  39894 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  39898 */     GIR_RootConstrainSelectedInstOperands,
     /*  39899 */     // GIR_Coverage, 1498,
     /*  39899 */     GIR_EraseRootFromParent_Done,
     /*  39900 */   // Label 647: @39900
     /*  39900 */   GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(39965), // Rule ID 6664 //
     /*  39905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39909 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  39917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
     /*  39921 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  39925 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39930 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  39932 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm))  =>  (SABAv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }))
     /*  39932 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  39935 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /*  39939 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  39944 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /*  39947 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  39949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABAv16i8),
     /*  39952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  39954 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  39956 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  39960 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  39963 */     GIR_RootConstrainSelectedInstOperands,
     /*  39964 */     // GIR_Coverage, 6664,
     /*  39964 */     GIR_EraseRootFromParent_Done,
     /*  39965 */   // Label 648: @39965
     /*  39965 */   GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(39992), // Rule ID 1131 //
     /*  39970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  39973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39977 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39981 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  39985 */     // (add:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  39985 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDv16i8),
     /*  39990 */     GIR_RootConstrainSelectedInstOperands,
     /*  39991 */     // GIR_Coverage, 1131,
     /*  39991 */     GIR_Done,
     /*  39992 */   // Label 649: @39992
     /*  39992 */   GIM_Reject,
     /*  39993 */ // Label 632: @39993
     /*  39993 */ GIM_Reject,
     /*  39994 */ // Label 183: @39994
     /*  39994 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(40365),
     /*  39999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40002 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  40005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  40009 */   GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(40071), // Rule ID 16195 //
     /*  40014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  40021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  40025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  40033 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40037 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  40041 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  40045 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  40056 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40058 */     // (add:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  40061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40063 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  40065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  40069 */     GIR_RootConstrainSelectedInstOperands,
     /*  40070 */     // GIR_Coverage, 16195,
     /*  40070 */     GIR_EraseRootFromParent_Done,
     /*  40071 */   // Label 651: @40071
     /*  40071 */   GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(40133), // Rule ID 16194 //
     /*  40076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  40083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  40087 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40091 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  40095 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  40099 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  40103 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  40107 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  40118 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40120 */     // (add:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  40123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  40127 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  40131 */     GIR_RootConstrainSelectedInstOperands,
     /*  40132 */     // GIR_Coverage, 16194,
     /*  40132 */     GIR_EraseRootFromParent_Done,
     /*  40133 */   // Label 652: @40133
     /*  40133 */   GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(40195), // Rule ID 16193 //
     /*  40138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  40149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40153 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  40157 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40161 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  40165 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  40169 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  40180 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40182 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  40185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40187 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  40189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  40193 */     GIR_RootConstrainSelectedInstOperands,
     /*  40194 */     // GIR_Coverage, 16193,
     /*  40194 */     GIR_EraseRootFromParent_Done,
     /*  40195 */   // Label 653: @40195
     /*  40195 */   GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(40257), // Rule ID 9624 //
     /*  40200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  40211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40215 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  40219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  40223 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  40227 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  40231 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/1, GIMT_Encode8(4294967295),
     /*  40242 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40244 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } 4294967295:{ *:[i64] })))  =>  (ADR_UXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_UXTW_ZZZ_D_0),
     /*  40247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40249 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  40251 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  40255 */     GIR_RootConstrainSelectedInstOperands,
     /*  40256 */     // GIR_Coverage, 9624,
     /*  40256 */     GIR_EraseRootFromParent_Done,
     /*  40257 */   // Label 654: @40257
     /*  40257 */   GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(40303), // Rule ID 16196 //
     /*  40262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  40269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  40273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40277 */     // MIs[1] Operand 2
     /*  40277 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  40288 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40290 */     // (add:{ *:[nxv2i64] } (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i32:{ *:[Other] }), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (ADR_SXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_SXTW_ZZZ_D_0),
     /*  40293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  40297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  40301 */     GIR_RootConstrainSelectedInstOperands,
     /*  40302 */     // GIR_Coverage, 16196,
     /*  40302 */     GIR_EraseRootFromParent_Done,
     /*  40303 */   // Label 655: @40303
     /*  40303 */   GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(40349), // Rule ID 9625 //
     /*  40308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /*  40311 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40315 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  40319 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  40323 */     // MIs[1] Operand 2
     /*  40323 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  40334 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  40336 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i32:{ *:[Other] }))  =>  (ADR_SXTW_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_SXTW_ZZZ_D_0),
     /*  40339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  40341 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  40343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  40347 */     GIR_RootConstrainSelectedInstOperands,
     /*  40348 */     // GIR_Coverage, 9625,
     /*  40348 */     GIR_EraseRootFromParent_Done,
     /*  40349 */   // Label 656: @40349
     /*  40349 */   GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(40364), // Rule ID 2825 //
     /*  40354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  40357 */     // (add:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  40357 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_D),
     /*  40362 */     GIR_RootConstrainSelectedInstOperands,
     /*  40363 */     // GIR_Coverage, 2825,
     /*  40363 */     GIR_Done,
     /*  40364 */   // Label 657: @40364
     /*  40364 */   GIM_Reject,
     /*  40365 */ // Label 650: @40365
     /*  40365 */ GIM_Reject,
     /*  40366 */ // Label 184: @40366
     /*  40366 */ GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(40391), // Rule ID 2824 //
     /*  40371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  40374 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  40377 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  40380 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  40384 */   // (add:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  40384 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_S),
     /*  40389 */   GIR_RootConstrainSelectedInstOperands,
     /*  40390 */   // GIR_Coverage, 2824,
     /*  40390 */   GIR_Done,
     /*  40391 */ // Label 658: @40391
     /*  40391 */ GIM_Reject,
     /*  40392 */ // Label 185: @40392
     /*  40392 */ GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(40417), // Rule ID 2823 //
     /*  40397 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  40400 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  40403 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  40406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  40410 */   // (add:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  40410 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_H),
     /*  40415 */   GIR_RootConstrainSelectedInstOperands,
     /*  40416 */   // GIR_Coverage, 2823,
     /*  40416 */   GIR_Done,
     /*  40417 */ // Label 659: @40417
     /*  40417 */ GIM_Reject,
     /*  40418 */ // Label 186: @40418
     /*  40418 */ GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(40443), // Rule ID 2822 //
     /*  40423 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  40426 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  40429 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  40432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  40436 */   // (add:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  40436 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADD_ZZZ_B),
     /*  40441 */   GIR_RootConstrainSelectedInstOperands,
     /*  40442 */   // GIR_Coverage, 2822,
     /*  40442 */   GIR_Done,
     /*  40443 */ // Label 660: @40443
     /*  40443 */ GIM_Reject,
     /*  40444 */ // Label 187: @40444
     /*  40444 */ GIM_Reject,
     /*  40445 */ // Label 1: @40445
     /*  40445 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 674*/ GIMT_Encode4(55429),
     /*  40456 */ /*GILLT_s32*//*Label 661*/ GIMT_Encode4(40544),
     /*  40460 */ /*GILLT_s64*//*Label 662*/ GIMT_Encode4(42159), GIMT_Encode4(0),
     /*  40468 */ /*GILLT_v2s32*//*Label 663*/ GIMT_Encode4(46065),
     /*  40472 */ /*GILLT_v2s64*//*Label 664*/ GIMT_Encode4(47556),
     /*  40476 */ /*GILLT_v4s16*//*Label 665*/ GIMT_Encode4(50016),
     /*  40480 */ /*GILLT_v4s32*//*Label 666*/ GIMT_Encode4(51507),
     /*  40484 */ /*GILLT_v8s8*//*Label 667*/ GIMT_Encode4(53967),
     /*  40488 */ /*GILLT_v8s16*//*Label 668*/ GIMT_Encode4(54042),
     /*  40492 */ /*GILLT_v16s8*//*Label 669*/ GIMT_Encode4(55250), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  40512 */ /*GILLT_nxv2s64*//*Label 670*/ GIMT_Encode4(55325), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  40524 */ /*GILLT_nxv4s32*//*Label 671*/ GIMT_Encode4(55351), GIMT_Encode4(0),
     /*  40532 */ /*GILLT_nxv8s16*//*Label 672*/ GIMT_Encode4(55377), GIMT_Encode4(0),
     /*  40540 */ /*GILLT_nxv16s8*//*Label 673*/ GIMT_Encode4(55403),
     /*  40544 */ // Label 661: @40544
     /*  40544 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(42158),
     /*  40549 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  40552 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  40555 */   GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(40707), // Rule ID 10681 //
     /*  40560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  40579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40583 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40587 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40591 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  40594 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*  40599 */     // MIs[2] pattern
     /*  40599 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  40602 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40607 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40609 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECB_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  40609 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  40612 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  40616 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40621 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  40623 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  40626 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  40630 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40635 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  40638 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  40642 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  40645 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40650 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40655 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40660 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  40663 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
     /*  40667 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40672 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  40675 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  40679 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  40682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  40684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  40689 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  40696 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40701 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40706 */     // GIR_Coverage, 10681,
     /*  40706 */     GIR_EraseRootFromParent_Done,
     /*  40707 */   // Label 676: @40707
     /*  40707 */   GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(40859), // Rule ID 10693 //
     /*  40712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40719 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  40731 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40735 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40739 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40743 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  40746 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*  40751 */     // MIs[2] pattern
     /*  40751 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  40754 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40759 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40761 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECH_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  40761 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  40764 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  40768 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40773 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  40775 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  40778 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  40782 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40787 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  40790 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  40794 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  40797 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40802 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40807 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40812 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  40815 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
     /*  40819 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40824 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  40827 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  40831 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  40834 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  40836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  40841 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  40848 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40853 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  40858 */     // GIR_Coverage, 10693,
     /*  40858 */     GIR_EraseRootFromParent_Done,
     /*  40859 */   // Label 677: @40859
     /*  40859 */   GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(41011), // Rule ID 10705 //
     /*  40864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  40867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40871 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40875 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  40879 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  40883 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  40887 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  40891 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  40895 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  40898 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*  40903 */     // MIs[2] pattern
     /*  40903 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  40906 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  40911 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  40913 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECW_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  40913 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  40916 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  40920 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40925 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  40927 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  40930 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  40934 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40939 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  40942 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  40946 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  40949 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40954 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  40959 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  40964 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  40967 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
     /*  40971 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  40976 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  40979 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  40983 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  40986 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  40988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  40991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  40993 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41000 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41005 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41010 */     // GIR_Coverage, 10705,
     /*  41010 */     GIR_EraseRootFromParent_Done,
     /*  41011 */   // Label 678: @41011
     /*  41011 */   GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(41163), // Rule ID 10717 //
     /*  41016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  41019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41023 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41027 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41035 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41039 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41043 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  41047 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/3,
     /*  41050 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*  41055 */     // MIs[2] pattern
     /*  41055 */     GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /*  41058 */     GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  41063 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41065 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rdn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECD_XPiI:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rdn, sub_32:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] }), sub_32:{ *:[i32] })
     /*  41065 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41068 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41072 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41077 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41079 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41082 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41086 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41091 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41094 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rdn
     /*  41098 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41101 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41106 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41111 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41116 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41119 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
     /*  41123 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41128 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41131 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pattern
     /*  41135 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /*  41138 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41145 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41162 */     // GIR_Coverage, 10717,
     /*  41162 */     GIR_EraseRootFromParent_Done,
     /*  41163 */   // Label 679: @41163
     /*  41163 */   GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(41225), // Rule ID 4049 //
     /*  41168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41172 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  41176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  41184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  41188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  41192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41197 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41202 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  41204 */     // (sub:{ *:[i32] } 0:{ *:[i32] }, (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  41204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  41207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  41209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  41213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  41217 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  41223 */     GIR_RootConstrainSelectedInstOperands,
     /*  41224 */     // GIR_Coverage, 4049,
     /*  41224 */     GIR_EraseRootFromParent_Done,
     /*  41225 */   // Label 680: @41225
     /*  41225 */   GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(41358), // Rule ID 4024 //
     /*  41230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41234 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41238 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41242 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41246 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41250 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_trunc_isWorthFoldingALU),
     /*  41254 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  41256 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  41263 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } arith_shifted_reg64:{ *:[i64] }:$Rm)<<P:Predicate_trunc_isWorthFoldingALU>>)  =>  (EXTRACT_SUBREG:{ *:[i32] } (SUBXrs:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), arith_shifted_reg64:{ *:[i64] }:$Rm), sub_32:{ *:[i32] })
     /*  41263 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41266 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41270 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41275 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41277 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41280 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41284 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41289 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41292 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41296 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41299 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41304 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41309 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41314 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41317 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrs),
     /*  41321 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41326 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41329 */     GIR_ComplexRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), // Rm
     /*  41333 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41340 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41347 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41352 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41357 */     // GIR_Coverage, 4024,
     /*  41357 */     GIR_EraseRootFromParent_Done,
     /*  41358 */   // Label 681: @41358
     /*  41358 */   GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(41515), // Rule ID 10819 //
     /*  41363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  41366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41370 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  41394 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  41397 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  41402 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  41406 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  41408 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  41413 */     // MIs[2] pred
     /*  41413 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  41418 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41420 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  41420 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41423 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41427 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41432 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41434 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41437 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41441 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41446 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41449 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41453 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41456 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41461 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41466 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_B),
     /*  41478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41483 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  41487 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41490 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41497 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41504 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41509 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41514 */     // GIR_Coverage, 10819,
     /*  41514 */     GIR_EraseRootFromParent_Done,
     /*  41515 */   // Label 682: @41515
     /*  41515 */   GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(41672), // Rule ID 10820 //
     /*  41520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  41523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41527 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41531 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41535 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41539 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41543 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41547 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  41551 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  41554 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  41559 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  41563 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  41565 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  41570 */     // MIs[2] pred
     /*  41570 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  41575 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41577 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  41577 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41580 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41584 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41589 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41591 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41594 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41598 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41603 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41606 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41610 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41613 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41618 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41623 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41628 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41631 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_H),
     /*  41635 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41640 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  41644 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41647 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41654 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41661 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41666 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41671 */     // GIR_Coverage, 10820,
     /*  41671 */     GIR_EraseRootFromParent_Done,
     /*  41672 */   // Label 683: @41672
     /*  41672 */   GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(41829), // Rule ID 10821 //
     /*  41677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  41680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41684 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41700 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41704 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  41708 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  41711 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  41716 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  41720 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  41722 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  41727 */     // MIs[2] pred
     /*  41727 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  41732 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41734 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  41734 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41737 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41741 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41746 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41748 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41751 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41755 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41760 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41763 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41767 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41770 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41775 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41780 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41785 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41788 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_S),
     /*  41792 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41797 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  41801 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41804 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41811 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41818 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41823 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41828 */     // GIR_Coverage, 10821,
     /*  41828 */     GIR_EraseRootFromParent_Done,
     /*  41829 */   // Label 684: @41829
     /*  41829 */   GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(41986), // Rule ID 10822 //
     /*  41834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  41837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41841 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41845 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  41849 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /*  41853 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  41857 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  41861 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  41865 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /*  41868 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  41873 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  41877 */     GIM_CheckHasOneUse, /*MI*/2,
     /*  41879 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  41884 */     // MIs[2] pred
     /*  41884 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  41889 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  41891 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (trunc:{ *:[i32] } (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>))  =>  (EXTRACT_SUBREG:{ *:[i32] } (DECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  41891 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /*  41894 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  41898 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41903 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  41905 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /*  41908 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  41912 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41917 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  41920 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  41924 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/20,
     /*  41927 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41932 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  41937 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41942 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /*  41945 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_D),
     /*  41949 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  41954 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // pred
     /*  41958 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  41961 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  41963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  41966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  41968 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::sub_32),
     /*  41975 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41980 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  41985 */     // GIR_Coverage, 10822,
     /*  41985 */     GIR_EraseRootFromParent_Done,
     /*  41986 */   // Label 685: @41986
     /*  41986 */   GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(42022), // Rule ID 4012 //
     /*  41991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  41995 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  41999 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32_i32),
     /*  42006 */     // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3)  =>  (SUBSWrx:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$R2, arith_extended_reg32_i32:{ *:[i32] }:$R3)
     /*  42006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrx),
     /*  42009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42011 */     GIR_RootToRootCopy, /*OpIdx*/1, // R2
     /*  42013 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
     /*  42017 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  42020 */     GIR_RootConstrainSelectedInstOperands,
     /*  42021 */     // GIR_Coverage, 4012,
     /*  42021 */     GIR_EraseRootFromParent_Done,
     /*  42022 */   // Label 686: @42022
     /*  42022 */   GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(42055), // Rule ID 4017 //
     /*  42027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  42031 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42035 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm32),
     /*  42042 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (ADDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, neg_addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*  42042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDWri),
     /*  42045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42047 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42049 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  42053 */     GIR_RootConstrainSelectedInstOperands,
     /*  42054 */     // GIR_Coverage, 4017,
     /*  42054 */     GIR_EraseRootFromParent_Done,
     /*  42055 */   // Label 687: @42055
     /*  42055 */   GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(42091), // Rule ID 4006 //
     /*  42060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42064 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  42068 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm32),
     /*  42075 */     // (sub:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)  =>  (SUBSWri:{ *:[i32] }:{ *:[i32] } GPR32sp:{ *:[i32] }:$Rn, addsub_shifted_imm32:{ *:[i32] }:$imm)
     /*  42075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWri),
     /*  42078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42080 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42082 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  42086 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  42089 */     GIR_RootConstrainSelectedInstOperands,
     /*  42090 */     // GIR_Coverage, 4006,
     /*  42090 */     GIR_EraseRootFromParent_Done,
     /*  42091 */   // Label 688: @42091
     /*  42091 */   GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(42127), // Rule ID 4010 //
     /*  42096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42100 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42104 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg32),
     /*  42111 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm)  =>  (SUBSWrs:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, arith_shifted_reg32:{ *:[i32] }:$Rm)
     /*  42111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrs),
     /*  42114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42116 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  42118 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
     /*  42122 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  42125 */     GIR_RootConstrainSelectedInstOperands,
     /*  42126 */     // GIR_Coverage, 4010,
     /*  42126 */     GIR_EraseRootFromParent_Done,
     /*  42127 */   // Label 689: @42127
     /*  42127 */   GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(42157), // Rule ID 4008 //
     /*  42132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42136 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42144 */     // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SUBSWrr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  42144 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSWrr),
     /*  42149 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
     /*  42155 */     GIR_RootConstrainSelectedInstOperands,
     /*  42156 */     // GIR_Coverage, 4008,
     /*  42156 */     GIR_Done,
     /*  42157 */   // Label 690: @42157
     /*  42157 */   GIM_Reject,
     /*  42158 */ // Label 675: @42158
     /*  42158 */ GIM_Reject,
     /*  42159 */ // Label 662: @42159
     /*  42159 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(46064),
     /*  42164 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  42167 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  42170 */   GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(42306), // Rule ID 6000 //
     /*  42175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42179 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42183 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42187 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42191 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42195 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42199 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42203 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42208 */     // MIs[1] Operand 2
     /*  42208 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42219 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42223 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42227 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42231 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42235 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42239 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42243 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42248 */     // MIs[3] Operand 2
     /*  42248 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42259 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42261 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  42261 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  42264 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  42268 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42273 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42277 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42281 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42288 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42295 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42300 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42305 */     // GIR_Coverage, 6000,
     /*  42305 */     GIR_EraseRootFromParent_Done,
     /*  42306 */   // Label 692: @42306
     /*  42306 */   GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(42442), // Rule ID 5999 //
     /*  42311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42335 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42339 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42344 */     // MIs[1] Operand 2
     /*  42344 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42355 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42359 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42363 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42367 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42371 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42375 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42379 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42384 */     // MIs[3] Operand 2
     /*  42384 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42395 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42397 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  42397 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  42400 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  42404 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42409 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42413 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42417 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42424 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42431 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42436 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42441 */     // GIR_Coverage, 5999,
     /*  42441 */     GIR_EraseRootFromParent_Done,
     /*  42442 */   // Label 693: @42442
     /*  42442 */   GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(42578), // Rule ID 6009 //
     /*  42447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42451 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42455 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42459 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42463 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42467 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  42471 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42475 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42480 */     // MIs[1] Operand 2
     /*  42480 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42491 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42495 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42499 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42503 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42507 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  42511 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42515 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42520 */     // MIs[3] Operand 2
     /*  42520 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42531 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42533 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  42533 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  42536 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv2i32_v2i64),
     /*  42540 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42545 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42549 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42553 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42560 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42567 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42572 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42577 */     // GIR_Coverage, 6009,
     /*  42577 */     GIR_EraseRootFromParent_Done,
     /*  42578 */   // Label 694: @42578
     /*  42578 */   GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(42714), // Rule ID 5998 //
     /*  42583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42587 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42591 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42595 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42607 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42611 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42616 */     // MIs[1] Operand 2
     /*  42616 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42627 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42631 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42635 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42639 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42643 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  42647 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42651 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42656 */     // MIs[3] Operand 2
     /*  42656 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42667 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42669 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  42669 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  42672 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  42676 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42681 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42685 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42689 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42696 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42703 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42708 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42713 */     // GIR_Coverage, 5998,
     /*  42713 */     GIR_EraseRootFromParent_Done,
     /*  42714 */   // Label 695: @42714
     /*  42714 */   GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(42850), // Rule ID 5997 //
     /*  42719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  42727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42731 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42735 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42739 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42743 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42747 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42752 */     // MIs[1] Operand 2
     /*  42752 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  42763 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  42767 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  42771 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  42775 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  42779 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  42783 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  42787 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42792 */     // MIs[3] Operand 2
     /*  42792 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  42803 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  42805 */     // (sub:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  42805 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  42808 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  42812 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42817 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  42821 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  42825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  42827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  42832 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  42839 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  42844 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  42849 */     // GIR_Coverage, 5997,
     /*  42849 */     GIR_EraseRootFromParent_Done,
     /*  42850 */   // Label 696: @42850
     /*  42850 */   GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(42987), // Rule ID 4066 //
     /*  42855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42859 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  42863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  42867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  42871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  42875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  42879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  42883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  42887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  42891 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42896 */     // MIs[2] Operand 2
     /*  42896 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  42907 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  42911 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  42915 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  42919 */     // MIs[3] Operand 1
     /*  42919 */     // No operand predicates
     /*  42919 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  42921 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  42921 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  42924 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  42928 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42933 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  42938 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  42940 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  42943 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  42947 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  42952 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  42958 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  42963 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  42971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  42973 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  42976 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  42979 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  42985 */     GIR_RootConstrainSelectedInstOperands,
     /*  42986 */     // GIR_Coverage, 4066,
     /*  42986 */     GIR_EraseRootFromParent_Done,
     /*  42987 */   // Label 697: @42987
     /*  42987 */   GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(43086), // Rule ID 4064 //
     /*  42992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  42996 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43008 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43012 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43016 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43020 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  43024 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43028 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43033 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43037 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  43041 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  43045 */     // MIs[3] Operand 1
     /*  43045 */     // No operand predicates
     /*  43045 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43047 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  43047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  43054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43059 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  43064 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  43069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43078 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43084 */     GIR_RootConstrainSelectedInstOperands,
     /*  43085 */     // GIR_Coverage, 4064,
     /*  43085 */     GIR_EraseRootFromParent_Done,
     /*  43086 */   // Label 698: @43086
     /*  43086 */   GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(43185), // Rule ID 4065 //
     /*  43091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43095 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43107 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43111 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43115 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43119 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43123 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43127 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43132 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43136 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  43140 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  43144 */     // MIs[3] Operand 1
     /*  43144 */     // No operand predicates
     /*  43144 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43146 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  43146 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43149 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  43153 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43158 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  43163 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43174 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43177 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43183 */     GIR_RootConstrainSelectedInstOperands,
     /*  43184 */     // GIR_Coverage, 4065,
     /*  43184 */     GIR_EraseRootFromParent_Done,
     /*  43185 */   // Label 699: @43185
     /*  43185 */   GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(43271), // Rule ID 4059 //
     /*  43190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43194 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43218 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  43222 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43226 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43231 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43235 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  43239 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  43243 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43248 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43250 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  43250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  43253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  43263 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43269 */     GIR_RootConstrainSelectedInstOperands,
     /*  43270 */     // GIR_Coverage, 4059,
     /*  43270 */     GIR_EraseRootFromParent_Done,
     /*  43271 */   // Label 700: @43271
     /*  43271 */   GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(43357), // Rule ID 4060 //
     /*  43276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43280 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43296 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43300 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43304 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43308 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43312 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43317 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43321 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43325 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  43329 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43334 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43336 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  43336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43341 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43345 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  43349 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43355 */     GIR_RootConstrainSelectedInstOperands,
     /*  43356 */     // GIR_Coverage, 4060,
     /*  43356 */     GIR_EraseRootFromParent_Done,
     /*  43357 */   // Label 701: @43357
     /*  43357 */   GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(43458), // Rule ID 4086 //
     /*  43362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43366 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43386 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  43391 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  43395 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43399 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43403 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43408 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43410 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  43410 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43413 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43417 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43422 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  43428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43433 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43443 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  43450 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43456 */     GIR_RootConstrainSelectedInstOperands,
     /*  43457 */     // GIR_Coverage, 4086,
     /*  43457 */     GIR_EraseRootFromParent_Done,
     /*  43458 */   // Label 702: @43458
     /*  43458 */   GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(43559), // Rule ID 14851 //
     /*  43463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43467 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43471 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43475 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43479 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43483 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43487 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43491 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43495 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43499 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43504 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  43509 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  43511 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  43511 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43514 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43518 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43523 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  43529 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43534 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43544 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43547 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  43551 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43557 */     GIR_RootConstrainSelectedInstOperands,
     /*  43558 */     // GIR_Coverage, 14851,
     /*  43558 */     GIR_EraseRootFromParent_Done,
     /*  43559 */   // Label 703: @43559
     /*  43559 */   GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(43675), // Rule ID 4085 //
     /*  43564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43568 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  43572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43580 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43584 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43588 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  43593 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  43598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  43600 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  43600 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  43603 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43607 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43612 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  43618 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43623 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43628 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43631 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43635 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43640 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  43646 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43651 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43661 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43664 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  43667 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  43673 */     GIR_RootConstrainSelectedInstOperands,
     /*  43674 */     // GIR_Coverage, 4085,
     /*  43674 */     GIR_EraseRootFromParent_Done,
     /*  43675 */   // Label 704: @43675
     /*  43675 */   GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(43808), // Rule ID 4072 //
     /*  43680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43684 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43700 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43704 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43708 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  43712 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  43716 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43721 */     // MIs[2] Operand 2
     /*  43721 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  43732 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43736 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  43740 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  43744 */     // MIs[3] Operand 1
     /*  43744 */     // No operand predicates
     /*  43744 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43746 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  43746 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  43749 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  43753 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43758 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  43763 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  43765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  43772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43777 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  43783 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  43796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43798 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43801 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  43804 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  43806 */     GIR_RootConstrainSelectedInstOperands,
     /*  43807 */     // GIR_Coverage, 4072,
     /*  43807 */     GIR_EraseRootFromParent_Done,
     /*  43808 */   // Label 705: @43808
     /*  43808 */   GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(43903), // Rule ID 4070 //
     /*  43813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43833 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43837 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43841 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  43845 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43849 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43854 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43858 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  43862 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  43866 */     // MIs[3] Operand 1
     /*  43866 */     // No operand predicates
     /*  43866 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43868 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  43868 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43871 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  43875 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43880 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  43885 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  43890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43896 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43899 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  43901 */     GIR_RootConstrainSelectedInstOperands,
     /*  43902 */     // GIR_Coverage, 4070,
     /*  43902 */     GIR_EraseRootFromParent_Done,
     /*  43903 */   // Label 706: @43903
     /*  43903 */   GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(43998), // Rule ID 4071 //
     /*  43908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43912 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  43916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  43920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  43924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  43928 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  43932 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  43936 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  43940 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  43944 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  43949 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  43953 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  43957 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  43961 */     // MIs[3] Operand 1
     /*  43961 */     // No operand predicates
     /*  43961 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  43963 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), GPR64:{ *:[i64] }:$Ra)
     /*  43963 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  43966 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  43970 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  43975 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  43980 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  43982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  43985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  43987 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  43991 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  43994 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  43996 */     GIR_RootConstrainSelectedInstOperands,
     /*  43997 */     // GIR_Coverage, 4071,
     /*  43997 */     GIR_EraseRootFromParent_Done,
     /*  43998 */   // Label 707: @43998
     /*  43998 */   GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(44080), // Rule ID 112 //
     /*  44003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44007 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  44019 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  44023 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  44027 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44031 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  44035 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  44039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44044 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  44048 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  44052 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  44056 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44061 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  44063 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (SMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  44063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMSUBLrrr),
     /*  44066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  44072 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44076 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  44078 */     GIR_RootConstrainSelectedInstOperands,
     /*  44079 */     // GIR_Coverage, 112,
     /*  44079 */     GIR_EraseRootFromParent_Done,
     /*  44080 */   // Label 708: @44080
     /*  44080 */   GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(44162), // Rule ID 114 //
     /*  44085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44089 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  44101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  44105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  44109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  44121 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44126 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  44130 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44134 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /*  44138 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44143 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  44145 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  44145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  44148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  44154 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  44158 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  44160 */     GIR_RootConstrainSelectedInstOperands,
     /*  44161 */     // GIR_Coverage, 114,
     /*  44161 */     GIR_EraseRootFromParent_Done,
     /*  44162 */   // Label 709: @44162
     /*  44162 */   GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(44224), // Rule ID 4050 //
     /*  44167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44171 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  44175 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44179 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  44183 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  44187 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  44191 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44201 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  44203 */     // (sub:{ *:[i64] } 0:{ *:[i64] }, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  44203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  44206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44208 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  44212 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  44216 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  44222 */     GIR_RootConstrainSelectedInstOperands,
     /*  44223 */     // GIR_Coverage, 4050,
     /*  44223 */     GIR_EraseRootFromParent_Done,
     /*  44224 */   // Label 710: @44224
     /*  44224 */   GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(44282), // Rule ID 10678 //
     /*  44229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  44232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44240 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44244 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  44248 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  44251 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /*  44256 */     // MIs[1] pattern
     /*  44256 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  44259 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  44264 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  44266 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECB_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  44266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECB_XPiI),
     /*  44269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  44271 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  44273 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  44277 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  44280 */     GIR_RootConstrainSelectedInstOperands,
     /*  44281 */     // GIR_Coverage, 10678,
     /*  44281 */     GIR_EraseRootFromParent_Done,
     /*  44282 */   // Label 711: @44282
     /*  44282 */   GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(44340), // Rule ID 10690 //
     /*  44287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  44290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44294 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  44306 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  44309 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /*  44314 */     // MIs[1] pattern
     /*  44314 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  44317 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  44322 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  44324 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECH_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  44324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECH_XPiI),
     /*  44327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  44329 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  44331 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  44335 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  44338 */     GIR_RootConstrainSelectedInstOperands,
     /*  44339 */     // GIR_Coverage, 10690,
     /*  44339 */     GIR_EraseRootFromParent_Done,
     /*  44340 */   // Label 712: @44340
     /*  44340 */   GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(44398), // Rule ID 10702 //
     /*  44345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  44348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44352 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44360 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  44364 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  44367 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /*  44372 */     // MIs[1] pattern
     /*  44372 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  44375 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  44380 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  44382 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECW_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  44382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECW_XPiI),
     /*  44385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  44387 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  44389 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  44393 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  44396 */     GIR_RootConstrainSelectedInstOperands,
     /*  44397 */     // GIR_Coverage, 10702,
     /*  44397 */     GIR_EraseRootFromParent_Done,
     /*  44398 */   // Label 713: @44398
     /*  44398 */   GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(44456), // Rule ID 10714 //
     /*  44403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_UseScalarIncVL),
     /*  44406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  44422 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  44425 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /*  44430 */     // MIs[1] pattern
     /*  44430 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  44433 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /*  44438 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  44440 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern))  =>  (DECD_XPiI:{ *:[i64] } GPR64:{ *:[i64] }:$Rdn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /*  44440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECD_XPiI),
     /*  44443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  44445 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rdn
     /*  44447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pattern
     /*  44451 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /*  44454 */     GIR_RootConstrainSelectedInstOperands,
     /*  44455 */     // GIR_Coverage, 10714,
     /*  44455 */     GIR_EraseRootFromParent_Done,
     /*  44456 */   // Label 714: @44456
     /*  44456 */   GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(44553), // Rule ID 4088 //
     /*  44461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44465 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44469 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44473 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  44477 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  44481 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  44485 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  44490 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  44494 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44498 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  44502 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44507 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44509 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm)))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  44509 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  44512 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  44516 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44521 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  44527 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44532 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  44540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44542 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  44545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  44549 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  44551 */     GIR_RootConstrainSelectedInstOperands,
     /*  44552 */     // GIR_Coverage, 4088,
     /*  44552 */     GIR_EraseRootFromParent_Done,
     /*  44553 */   // Label 715: @44553
     /*  44553 */   GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(44650), // Rule ID 14852 //
     /*  44558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44570 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  44574 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  44578 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  44582 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44586 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  44590 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  44594 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44599 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  44604 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44606 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /*  44606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  44609 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  44613 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44618 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  44624 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  44629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  44634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  44637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  44639 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  44642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  44646 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  44648 */     GIR_RootConstrainSelectedInstOperands,
     /*  44649 */     // GIR_Coverage, 14852,
     /*  44649 */     GIR_EraseRootFromParent_Done,
     /*  44650 */   // Label 716: @44650
     /*  44650 */   GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(44813), // Rule ID 5964 //
     /*  44655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44659 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  44675 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44679 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  44683 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44687 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44691 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44696 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44701 */     // MIs[1] Operand 2
     /*  44701 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  44712 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44714 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SMLSLv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  44714 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  44717 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  44721 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44726 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  44728 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  44731 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  44735 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44740 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  44743 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  44747 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  44750 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  44768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_v2i64),
     /*  44772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44777 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  44780 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  44784 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  44788 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  44790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  44793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44795 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  44802 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44807 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44812 */     // GIR_Coverage, 5964,
     /*  44812 */     GIR_EraseRootFromParent_Done,
     /*  44813 */   // Label 717: @44813
     /*  44813 */   GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(44976), // Rule ID 5961 //
     /*  44818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44822 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44826 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44830 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44834 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  44838 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  44842 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  44846 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  44850 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  44854 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44859 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44864 */     // MIs[1] Operand 2
     /*  44864 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  44875 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  44877 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Ra, (extract_subvector:{ *:[v1i64] } (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (UMLSLv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  44877 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  44880 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  44884 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44889 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  44891 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  44894 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  44898 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44903 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  44906 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  44910 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  44913 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44918 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44923 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44928 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  44931 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_v2i64),
     /*  44935 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  44940 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  44943 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  44947 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  44951 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  44953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  44956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  44958 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  44965 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44970 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  44975 */     // GIR_Coverage, 5961,
     /*  44975 */     GIR_EraseRootFromParent_Done,
     /*  44976 */   // Label 718: @44976
     /*  44976 */   GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(45126), // Rule ID 6006 //
     /*  44981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44985 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  44989 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  44993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  44997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  45001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  45009 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45013 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45018 */     // MIs[1] Operand 2
     /*  45018 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  45029 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  45031 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  45031 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  45034 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  45038 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45043 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  45045 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  45048 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  45052 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45057 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  45060 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  45064 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  45067 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45072 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45077 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45082 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  45085 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  45089 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45094 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  45097 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45101 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  45103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  45106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45108 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  45115 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45120 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45125 */     // GIR_Coverage, 6006,
     /*  45125 */     GIR_EraseRootFromParent_Done,
     /*  45126 */   // Label 719: @45126
     /*  45126 */   GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(45276), // Rule ID 6012 //
     /*  45131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45135 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  45147 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  45151 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45155 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  45159 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45163 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45168 */     // MIs[1] Operand 2
     /*  45168 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  45179 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  45181 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (SSUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  45181 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  45184 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  45188 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45193 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  45195 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  45198 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  45202 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45207 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  45210 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  45214 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  45217 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45222 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45227 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45232 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  45235 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv2i32_v2i64),
     /*  45239 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45244 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  45247 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45251 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  45253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  45256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45258 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  45265 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45270 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45275 */     // GIR_Coverage, 6012,
     /*  45275 */     GIR_EraseRootFromParent_Done,
     /*  45276 */   // Label 720: @45276
     /*  45276 */   GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(45426), // Rule ID 6005 //
     /*  45281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45285 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45289 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45293 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  45297 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  45301 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  45305 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  45309 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  45313 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45318 */     // MIs[1] Operand 2
     /*  45318 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  45329 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  45331 */     // (sub:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, (extract_subvector:{ *:[v1i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (USUBWv2i32_v2i64:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v2i32] }:$Rm), dsub:{ *:[i32] })
     /*  45331 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /*  45334 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  45338 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45343 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  45345 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /*  45348 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  45352 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45357 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  45360 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  45364 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  45367 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45372 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45377 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45382 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /*  45385 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  45389 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45394 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  45397 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  45401 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  45403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  45406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  45408 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  45415 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45420 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  45425 */     // GIR_Coverage, 6005,
     /*  45425 */     GIR_EraseRootFromParent_Done,
     /*  45426 */   // Label 721: @45426
     /*  45426 */   GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(45462), // Rule ID 4013 //
     /*  45431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  45439 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_extended_reg32to64_i64),
     /*  45446 */     // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3)  =>  (SUBSXrx:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$R2, arith_extended_reg32to64_i64:{ *:[i64] }:$R3)
     /*  45446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrx),
     /*  45449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45451 */     GIR_RootToRootCopy, /*OpIdx*/1, // R2
     /*  45453 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R3
     /*  45457 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  45460 */     GIR_RootConstrainSelectedInstOperands,
     /*  45461 */     // GIR_Coverage, 4013,
     /*  45461 */     GIR_EraseRootFromParent_Done,
     /*  45462 */   // Label 722: @45462
     /*  45462 */   GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(45495), // Rule ID 4018 //
     /*  45467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  45471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45475 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_neg_addsub_shifted_imm64),
     /*  45482 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (ADDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, neg_addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  45482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDXri),
     /*  45485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45487 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45489 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  45493 */     GIR_RootConstrainSelectedInstOperands,
     /*  45494 */     // GIR_Coverage, 4018,
     /*  45494 */     GIR_EraseRootFromParent_Done,
     /*  45495 */   // Label 723: @45495
     /*  45495 */   GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(45607), // Rule ID 4087 //
     /*  45500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45504 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45508 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45512 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  45516 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  45520 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  45524 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  45529 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  45534 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45536 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm))  =>  (UMSUBLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), GPR64:{ *:[i64] }:$Ra)
     /*  45536 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  45539 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  45543 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45548 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  45554 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  45559 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45564 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  45567 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  45571 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  45576 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  45582 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  45587 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMSUBLrrr),
     /*  45595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  45600 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  45603 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /*  45605 */     GIR_RootConstrainSelectedInstOperands,
     /*  45606 */     // GIR_Coverage, 4087,
     /*  45606 */     GIR_EraseRootFromParent_Done,
     /*  45607 */   // Label 724: @45607
     /*  45607 */   GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(45643), // Rule ID 4007 //
     /*  45612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45616 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  45620 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_addsub_shifted_imm64),
     /*  45627 */     // (sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)  =>  (SUBSXri:{ *:[i64] }:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, addsub_shifted_imm64:{ *:[i64] }:$imm)
     /*  45627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXri),
     /*  45630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45634 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // imm
     /*  45638 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  45641 */     GIR_RootConstrainSelectedInstOperands,
     /*  45642 */     // GIR_Coverage, 4007,
     /*  45642 */     GIR_EraseRootFromParent_Done,
     /*  45643 */   // Label 725: @45643
     /*  45643 */   GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(45679), // Rule ID 4011 //
     /*  45648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45652 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45656 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_arith_shifted_reg64),
     /*  45663 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm)  =>  (SUBSXrs:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, arith_shifted_reg64:{ *:[i64] }:$Rm)
     /*  45663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrs),
     /*  45666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45668 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45670 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm
     /*  45674 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /*  45677 */     GIR_RootConstrainSelectedInstOperands,
     /*  45678 */     // GIR_Coverage, 4011,
     /*  45678 */     GIR_EraseRootFromParent_Done,
     /*  45679 */   // Label 726: @45679
     /*  45679 */   GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(45742), // Rule ID 10811 //
     /*  45684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  45687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45691 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  45703 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  45706 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  45711 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  45715 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  45717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  45722 */     // MIs[1] pred
     /*  45722 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  45727 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45729 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$pred, PPRAny:{ *:[nxv16i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  45729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_B),
     /*  45732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  45734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  45738 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45740 */     GIR_RootConstrainSelectedInstOperands,
     /*  45741 */     // GIR_Coverage, 10811,
     /*  45741 */     GIR_EraseRootFromParent_Done,
     /*  45742 */   // Label 727: @45742
     /*  45742 */   GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(45805), // Rule ID 10812 //
     /*  45747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  45750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45754 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  45766 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  45769 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  45774 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  45778 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  45780 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  45785 */     // MIs[1] pred
     /*  45785 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  45790 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45792 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv8i1] }:$pred, PPRAny:{ *:[nxv8i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  45792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_H),
     /*  45795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  45797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  45801 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45803 */     GIR_RootConstrainSelectedInstOperands,
     /*  45804 */     // GIR_Coverage, 10812,
     /*  45804 */     GIR_EraseRootFromParent_Done,
     /*  45805 */   // Label 728: @45805
     /*  45805 */   GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(45868), // Rule ID 10813 //
     /*  45810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  45813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  45829 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  45832 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  45837 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  45841 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  45843 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  45848 */     // MIs[1] pred
     /*  45848 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  45853 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45855 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv4i1] }:$pred, PPRAny:{ *:[nxv4i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  45855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_S),
     /*  45858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  45860 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  45864 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45866 */     GIR_RootConstrainSelectedInstOperands,
     /*  45867 */     // GIR_Coverage, 10813,
     /*  45867 */     GIR_EraseRootFromParent_Done,
     /*  45868 */   // Label 729: @45868
     /*  45868 */   GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(45931), // Rule ID 10814 //
     /*  45873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  45876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45880 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  45884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  45888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /*  45892 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /*  45895 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /*  45900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  45904 */     GIM_CheckHasOneUse, /*MI*/1,
     /*  45906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  45911 */     // MIs[1] pred
     /*  45911 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  45916 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45918 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, PPRAny:{ *:[nxv2i1] }:$pred, PPRAny:{ *:[nxv2i1] }:$pred)<<P:Predicate_int_aarch64_sve_cntp_oneuse>>)  =>  (DECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$pred, ?:{ *:[i64] }:$Rn)
     /*  45918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DECP_XP_D),
     /*  45921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /*  45923 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // pred
     /*  45927 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  45929 */     GIR_RootConstrainSelectedInstOperands,
     /*  45930 */     // GIR_Coverage, 10814,
     /*  45930 */     GIR_EraseRootFromParent_Done,
     /*  45931 */   // Label 730: @45931
     /*  45931 */   GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(45970), // Rule ID 1697 //
     /*  45936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  45939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  45947 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  45953 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  45955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45959 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45961 */     // (sub:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (NEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /*  45961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
     /*  45964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  45966 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  45968 */     GIR_RootConstrainSelectedInstOperands,
     /*  45969 */     // GIR_Coverage, 1697,
     /*  45969 */     GIR_EraseRootFromParent_Done,
     /*  45970 */   // Label 731: @45970
     /*  45970 */   GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(46006), // Rule ID 5313 //
     /*  45975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45979 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  45983 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  45989 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  45991 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  45995 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  45997 */     // (sub:{ *:[i64] } immAllZerosV:{ *:[i64] }, FPR64:{ *:[i64] }:$Rn)  =>  (NEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /*  45997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv1i64),
     /*  46000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  46002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  46004 */     GIR_RootConstrainSelectedInstOperands,
     /*  46005 */     // GIR_Coverage, 5313,
     /*  46005 */     GIR_EraseRootFromParent_Done,
     /*  46006 */   // Label 732: @46006
     /*  46006 */   GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(46033), // Rule ID 1650 //
     /*  46011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  46014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46022 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46026 */     // (sub:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  46026 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv1i64),
     /*  46031 */     GIR_RootConstrainSelectedInstOperands,
     /*  46032 */     // GIR_Coverage, 1650,
     /*  46032 */     GIR_Done,
     /*  46033 */   // Label 733: @46033
     /*  46033 */   GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(46063), // Rule ID 4009 //
     /*  46038 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  46042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  46046 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  46050 */     // (sub:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SUBSXrr:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  46050 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBSXrr),
     /*  46055 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AArch64::NZCV), GIMT_Encode2(RegState::Dead),
     /*  46061 */     GIR_RootConstrainSelectedInstOperands,
     /*  46062 */     // GIR_Coverage, 4009,
     /*  46062 */     GIR_Done,
     /*  46063 */   // Label 734: @46063
     /*  46063 */   GIM_Reject,
     /*  46064 */ // Label 691: @46064
     /*  46064 */ GIM_Reject,
     /*  46065 */ // Label 663: @46065
     /*  46065 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(47555),
     /*  46070 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  46073 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  46076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46080 */   GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(46212), // Rule ID 5996 //
     /*  46085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46093 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46097 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46101 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46105 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46109 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46114 */     // MIs[1] Operand 2
     /*  46114 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46125 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46129 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46133 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46137 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46141 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46145 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46149 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46154 */     // MIs[3] Operand 2
     /*  46154 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46165 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46167 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46167 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46170 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  46174 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46179 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46183 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46187 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46194 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46201 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46206 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46211 */     // GIR_Coverage, 5996,
     /*  46211 */     GIR_EraseRootFromParent_Done,
     /*  46212 */   // Label 736: @46212
     /*  46212 */   GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(46344), // Rule ID 5995 //
     /*  46217 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46221 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46225 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46229 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46233 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46237 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46241 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46246 */     // MIs[1] Operand 2
     /*  46246 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46257 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46261 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46265 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46269 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46273 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46277 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46281 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46286 */     // MIs[3] Operand 2
     /*  46286 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46297 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46299 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46299 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46302 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  46306 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46311 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46315 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46319 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46326 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46333 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46338 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46343 */     // GIR_Coverage, 5995,
     /*  46343 */     GIR_EraseRootFromParent_Done,
     /*  46344 */   // Label 737: @46344
     /*  46344 */   GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(46476), // Rule ID 6008 //
     /*  46349 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46353 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46357 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46369 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46373 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46378 */     // MIs[1] Operand 2
     /*  46378 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46389 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46393 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46397 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46401 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46405 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  46409 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46413 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46418 */     // MIs[3] Operand 2
     /*  46418 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46429 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46431 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46431 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46434 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i16_v4i32),
     /*  46438 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46443 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46447 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46451 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46458 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46465 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46470 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46475 */     // GIR_Coverage, 6008,
     /*  46475 */     GIR_EraseRootFromParent_Done,
     /*  46476 */   // Label 738: @46476
     /*  46476 */   GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(46608), // Rule ID 5994 //
     /*  46481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46489 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46493 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46497 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46501 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46505 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46510 */     // MIs[1] Operand 2
     /*  46510 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46521 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46525 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46529 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46533 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46537 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  46541 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46545 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46550 */     // MIs[3] Operand 2
     /*  46550 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46561 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46563 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46563 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46566 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  46570 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46575 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46579 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46583 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46590 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46597 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46602 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46607 */     // GIR_Coverage, 5994,
     /*  46607 */     GIR_EraseRootFromParent_Done,
     /*  46608 */   // Label 739: @46608
     /*  46608 */   GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(46740), // Rule ID 5993 //
     /*  46613 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  46617 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46621 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46633 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46637 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46642 */     // MIs[1] Operand 2
     /*  46642 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46653 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  46657 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46661 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46665 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  46669 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  46673 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46677 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46682 */     // MIs[3] Operand 2
     /*  46682 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  46693 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  46695 */     // (sub:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46695 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46698 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  46702 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46707 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46711 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  46715 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46722 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46729 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46734 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46739 */     // GIR_Coverage, 5993,
     /*  46739 */     GIR_EraseRootFromParent_Done,
     /*  46740 */   // Label 740: @46740
     /*  46740 */   GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(46899), // Rule ID 5963 //
     /*  46745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  46769 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46773 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  46777 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46782 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46787 */     // MIs[1] Operand 2
     /*  46787 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46798 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  46800 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SMLSLv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46800 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  46803 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  46807 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46812 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  46814 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  46817 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  46821 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46826 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  46829 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  46833 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  46836 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46841 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46846 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46851 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  46854 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_v4i32),
     /*  46858 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46863 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  46866 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  46870 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  46874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  46876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  46879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  46881 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  46888 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46893 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  46898 */     // GIR_Coverage, 5963,
     /*  46898 */     GIR_EraseRootFromParent_Done,
     /*  46899 */   // Label 741: @46899
     /*  46899 */   GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(47058), // Rule ID 5960 //
     /*  46904 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  46912 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  46916 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  46920 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  46924 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  46928 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  46932 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  46936 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46941 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  46946 */     // MIs[1] Operand 2
     /*  46946 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  46957 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  46959 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Ra, (extract_subvector:{ *:[v2i32] } (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (UMLSLv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  46959 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  46962 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  46966 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46971 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  46973 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  46976 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  46980 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  46985 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  46988 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  46992 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  46995 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47000 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47005 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47010 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  47013 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_v4i32),
     /*  47017 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47022 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47025 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  47029 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  47033 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47040 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47047 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47052 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47057 */     // GIR_Coverage, 5960,
     /*  47057 */     GIR_EraseRootFromParent_Done,
     /*  47058 */   // Label 742: @47058
     /*  47058 */   GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(47204), // Rule ID 6004 //
     /*  47063 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47067 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47071 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47075 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47079 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47083 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  47087 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  47091 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47096 */     // MIs[1] Operand 2
     /*  47096 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47107 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47109 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  47109 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  47112 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47116 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47121 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47123 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  47126 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47130 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47135 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47138 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47142 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47145 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47150 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47155 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47160 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  47163 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  47167 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47172 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47175 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47179 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47186 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47193 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47198 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47203 */     // GIR_Coverage, 6004,
     /*  47203 */     GIR_EraseRootFromParent_Done,
     /*  47204 */   // Label 743: @47204
     /*  47204 */   GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(47350), // Rule ID 6011 //
     /*  47209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47213 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47217 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47221 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47225 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47229 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  47233 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  47237 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47242 */     // MIs[1] Operand 2
     /*  47242 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47253 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47255 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (SSUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  47255 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  47258 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47262 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47267 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47269 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  47272 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47276 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47281 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47284 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47288 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47291 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47296 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47301 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47306 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  47309 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i16_v4i32),
     /*  47313 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47318 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47321 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47325 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47332 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47339 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47344 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47349 */     // GIR_Coverage, 6011,
     /*  47349 */     GIR_EraseRootFromParent_Done,
     /*  47350 */   // Label 744: @47350
     /*  47350 */   GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(47496), // Rule ID 6003 //
     /*  47355 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47359 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47363 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47367 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47371 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47375 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  47379 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  47383 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47388 */     // MIs[1] Operand 2
     /*  47388 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  47399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  47401 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (USUBWv4i16_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v4i16] }:$Rm), dsub:{ *:[i32] })
     /*  47401 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /*  47404 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  47408 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47413 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  47415 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  47418 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  47422 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47427 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  47430 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  47434 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  47437 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47442 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47447 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47452 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  47455 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  47459 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  47464 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  47467 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  47471 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  47473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  47476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47478 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  47485 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47490 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47495 */     // GIR_Coverage, 6003,
     /*  47495 */     GIR_EraseRootFromParent_Done,
     /*  47496 */   // Label 745: @47496
     /*  47496 */   GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(47531), // Rule ID 999 //
     /*  47501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  47508 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  47514 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  47516 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47520 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  47522 */     // (sub:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn)  =>  (NEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /*  47522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i32),
     /*  47525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  47527 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  47529 */     GIR_RootConstrainSelectedInstOperands,
     /*  47530 */     // GIR_Coverage, 999,
     /*  47530 */     GIR_EraseRootFromParent_Done,
     /*  47531 */   // Label 746: @47531
     /*  47531 */   GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(47554), // Rule ID 1494 //
     /*  47536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47539 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  47547 */     // (sub:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  47547 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i32),
     /*  47552 */     GIR_RootConstrainSelectedInstOperands,
     /*  47553 */     // GIR_Coverage, 1494,
     /*  47553 */     GIR_Done,
     /*  47554 */   // Label 747: @47554
     /*  47554 */   GIM_Reject,
     /*  47555 */ // Label 735: @47555
     /*  47555 */ GIM_Reject,
     /*  47556 */ // Label 664: @47556
     /*  47556 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(50015),
     /*  47561 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  47564 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  47567 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47571 */   GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(47685), // Rule ID 2079 //
     /*  47576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47579 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  47591 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  47595 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  47599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  47603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47607 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47611 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  47615 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  47619 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47623 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  47627 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47632 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  47636 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  47640 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  47644 */     // MIs[4] Operand 1
     /*  47644 */     // No operand predicates
     /*  47644 */     // MIs[2] Operand 2
     /*  47644 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  47655 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  47657 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  47664 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  47664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_indexed),
     /*  47667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47669 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  47671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  47676 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  47680 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  47683 */     GIR_RootConstrainSelectedInstOperands,
     /*  47684 */     // GIR_Coverage, 2079,
     /*  47684 */     GIR_EraseRootFromParent_Done,
     /*  47685 */   // Label 749: @47685
     /*  47685 */   GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(47799), // Rule ID 14536 //
     /*  47690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  47705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  47709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  47713 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47717 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47721 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47725 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  47729 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  47733 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47737 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  47741 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47746 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  47750 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  47754 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  47758 */     // MIs[4] Operand 1
     /*  47758 */     // No operand predicates
     /*  47758 */     // MIs[2] Operand 2
     /*  47758 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  47769 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  47771 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  47778 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (SMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  47778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_indexed),
     /*  47781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47783 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  47785 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  47790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  47794 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  47797 */     GIR_RootConstrainSelectedInstOperands,
     /*  47798 */     // GIR_Coverage, 14536,
     /*  47798 */     GIR_EraseRootFromParent_Done,
     /*  47799 */   // Label 750: @47799
     /*  47799 */   GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(47913), // Rule ID 2131 //
     /*  47804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47807 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47811 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47815 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  47819 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  47823 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  47827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  47831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47835 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47839 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  47843 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  47847 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47851 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  47855 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47860 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  47864 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  47868 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  47872 */     // MIs[4] Operand 1
     /*  47872 */     // No operand predicates
     /*  47872 */     // MIs[2] Operand 2
     /*  47872 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  47883 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  47885 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  47892 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (UMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  47892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_indexed),
     /*  47895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  47897 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  47899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  47904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  47908 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  47911 */     GIR_RootConstrainSelectedInstOperands,
     /*  47912 */     // GIR_Coverage, 2131,
     /*  47912 */     GIR_EraseRootFromParent_Done,
     /*  47913 */   // Label 751: @47913
     /*  47913 */   GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(48027), // Rule ID 14572 //
     /*  47918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  47921 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47925 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  47929 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  47933 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  47937 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  47941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  47945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  47949 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47953 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  47957 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  47961 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  47965 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  47969 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  47974 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  47978 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  47982 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  47986 */     // MIs[4] Operand 1
     /*  47986 */     // No operand predicates
     /*  47986 */     // MIs[2] Operand 2
     /*  47986 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /*  47997 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  47999 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48006 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)))  =>  (UMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_indexed),
     /*  48009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48011 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48022 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48025 */     GIR_RootConstrainSelectedInstOperands,
     /*  48026 */     // GIR_Coverage, 14572,
     /*  48026 */     GIR_EraseRootFromParent_Done,
     /*  48027 */   // Label 752: @48027
     /*  48027 */   GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(48092), // Rule ID 1886 //
     /*  48032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48035 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48039 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48043 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48047 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48051 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48055 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48059 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48061 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48068 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48075 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  48078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48080 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48085 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48090 */     GIR_RootConstrainSelectedInstOperands,
     /*  48091 */     // GIR_Coverage, 1886,
     /*  48091 */     GIR_EraseRootFromParent_Done,
     /*  48092 */   // Label 753: @48092
     /*  48092 */   GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(48157), // Rule ID 1885 //
     /*  48097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48112 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48116 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48120 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48124 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48126 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48133 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48140 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  48143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48155 */     GIR_RootConstrainSelectedInstOperands,
     /*  48156 */     // GIR_Coverage, 1885,
     /*  48156 */     GIR_EraseRootFromParent_Done,
     /*  48157 */   // Label 754: @48157
     /*  48157 */   GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(48222), // Rule ID 1790 //
     /*  48162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  48173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  48185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48189 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48191 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48198 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48205 */     // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SSUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i32_v2i64),
     /*  48208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48220 */     GIR_RootConstrainSelectedInstOperands,
     /*  48221 */     // GIR_Coverage, 1790,
     /*  48221 */     GIR_EraseRootFromParent_Done,
     /*  48222 */   // Label 755: @48222
     /*  48222 */   GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(48287), // Rule ID 1884 //
     /*  48227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48230 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48234 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48238 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  48250 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48254 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48256 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48263 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48270 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  48273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48275 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48280 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48285 */     GIR_RootConstrainSelectedInstOperands,
     /*  48286 */     // GIR_Coverage, 1884,
     /*  48286 */     GIR_EraseRootFromParent_Done,
     /*  48287 */   // Label 756: @48287
     /*  48287 */   GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(48352), // Rule ID 1883 //
     /*  48292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  48299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  48311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  48315 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48319 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  48321 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48328 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48335 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn)), (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i32_v2i64),
     /*  48338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  48340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48350 */     GIR_RootConstrainSelectedInstOperands,
     /*  48351 */     // GIR_Coverage, 1883,
     /*  48351 */     GIR_EraseRootFromParent_Done,
     /*  48352 */   // Label 757: @48352
     /*  48352 */   GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(48463), // Rule ID 14534 //
     /*  48357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48360 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48376 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48380 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48384 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48388 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48392 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48396 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  48400 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48404 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48408 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48413 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48417 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48421 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  48425 */     // MIs[4] Operand 1
     /*  48425 */     // No operand predicates
     /*  48425 */     // MIs[2] Operand 2
     /*  48425 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48436 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48441 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48443 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  48446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48448 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  48454 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48458 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48461 */     GIR_RootConstrainSelectedInstOperands,
     /*  48462 */     // GIR_Coverage, 14534,
     /*  48462 */     GIR_EraseRootFromParent_Done,
     /*  48463 */   // Label 758: @48463
     /*  48463 */   GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(48574), // Rule ID 2077 //
     /*  48468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48475 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48479 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48483 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48487 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48491 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48496 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  48500 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48504 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48508 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48512 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  48516 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48520 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48524 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48529 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48533 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48537 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  48541 */     // MIs[4] Operand 1
     /*  48541 */     // No operand predicates
     /*  48541 */     // MIs[2] Operand 2
     /*  48541 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48552 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48554 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  48557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48559 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48561 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  48565 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48569 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48572 */     GIR_RootConstrainSelectedInstOperands,
     /*  48573 */     // GIR_Coverage, 2077,
     /*  48573 */     GIR_EraseRootFromParent_Done,
     /*  48574 */   // Label 759: @48574
     /*  48574 */   GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(48685), // Rule ID 14570 //
     /*  48579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48582 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48586 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48590 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  48594 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48598 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48602 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48606 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48610 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48614 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48618 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  48622 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48626 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48630 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48635 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48639 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48643 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  48647 */     // MIs[4] Operand 1
     /*  48647 */     // No operand predicates
     /*  48647 */     // MIs[2] Operand 2
     /*  48647 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48658 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48663 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48665 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  48668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48670 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  48676 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48680 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48683 */     GIR_RootConstrainSelectedInstOperands,
     /*  48684 */     // GIR_Coverage, 14570,
     /*  48684 */     GIR_EraseRootFromParent_Done,
     /*  48685 */   // Label 760: @48685
     /*  48685 */   GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(48796), // Rule ID 2129 //
     /*  48690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  48705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48713 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48718 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  48722 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  48726 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48730 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  48734 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  48738 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48742 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  48746 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48751 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  48755 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48759 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  48763 */     // MIs[4] Operand 1
     /*  48763 */     // No operand predicates
     /*  48763 */     // MIs[2] Operand 2
     /*  48763 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  48774 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  48776 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  48779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48783 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  48787 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  48791 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  48794 */     GIR_RootConstrainSelectedInstOperands,
     /*  48795 */     // GIR_Coverage, 2129,
     /*  48795 */     GIR_EraseRootFromParent_Done,
     /*  48796 */   // Label 761: @48796
     /*  48796 */   GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(48859), // Rule ID 1766 //
     /*  48801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48804 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48816 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48820 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48824 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  48826 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48833 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48840 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i32_v2i64),
     /*  48843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48845 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48847 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48852 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48857 */     GIR_RootConstrainSelectedInstOperands,
     /*  48858 */     // GIR_Coverage, 1766,
     /*  48858 */     GIR_EraseRootFromParent_Done,
     /*  48859 */   // Label 762: @48859
     /*  48859 */   GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(48922), // Rule ID 1856 //
     /*  48864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  48879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48883 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48887 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  48889 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48896 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  48903 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  48903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i32_v2i64),
     /*  48906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48908 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  48915 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  48920 */     GIR_RootConstrainSelectedInstOperands,
     /*  48921 */     // GIR_Coverage, 1856,
     /*  48921 */     GIR_EraseRootFromParent_Done,
     /*  48922 */   // Label 763: @48922
     /*  48922 */   GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(49010), // Rule ID 14535 //
     /*  48927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  48930 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  48938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  48942 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  48946 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  48950 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  48954 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  48958 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  48962 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  48966 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  48971 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  48975 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  48979 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  48983 */     // MIs[3] Operand 1
     /*  48983 */     // No operand predicates
     /*  48983 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  48988 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  48990 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  48990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  48993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  48995 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  48997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  49001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49005 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49008 */     GIR_RootConstrainSelectedInstOperands,
     /*  49009 */     // GIR_Coverage, 14535,
     /*  49009 */     GIR_EraseRootFromParent_Done,
     /*  49010 */   // Label 764: @49010
     /*  49010 */   GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(49098), // Rule ID 2078 //
     /*  49015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49022 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49026 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  49030 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49034 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  49038 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49043 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  49047 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  49051 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  49055 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49059 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49064 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49068 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49072 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  49076 */     // MIs[3] Operand 1
     /*  49076 */     // No operand predicates
     /*  49076 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49078 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_indexed),
     /*  49081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49089 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49093 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49096 */     GIR_RootConstrainSelectedInstOperands,
     /*  49097 */     // GIR_Coverage, 2078,
     /*  49097 */     GIR_EraseRootFromParent_Done,
     /*  49098 */   // Label 765: @49098
     /*  49098 */   GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(49186), // Rule ID 14571 //
     /*  49103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49106 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49122 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  49126 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  49130 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  49134 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  49138 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49142 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49147 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49151 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49155 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  49159 */     // MIs[3] Operand 1
     /*  49159 */     // No operand predicates
     /*  49159 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49164 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49166 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  49169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49171 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49173 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  49177 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49181 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49184 */     GIR_RootConstrainSelectedInstOperands,
     /*  49185 */     // GIR_Coverage, 14571,
     /*  49185 */     GIR_EraseRootFromParent_Done,
     /*  49186 */   // Label 766: @49186
     /*  49186 */   GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(49274), // Rule ID 2130 //
     /*  49191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49194 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  49214 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  49223 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  49227 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  49231 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  49235 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49240 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  49244 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  49248 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  49252 */     // MIs[3] Operand 1
     /*  49252 */     // No operand predicates
     /*  49252 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  49254 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  49254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_indexed),
     /*  49257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49259 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49261 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49265 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49269 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  49272 */     GIR_RootConstrainSelectedInstOperands,
     /*  49273 */     // GIR_Coverage, 2130,
     /*  49273 */     GIR_EraseRootFromParent_Done,
     /*  49274 */   // Label 767: @49274
     /*  49274 */   GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(49321), // Rule ID 1898 //
     /*  49279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49294 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49298 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49300 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  49307 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  49307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
     /*  49310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49312 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49319 */     GIR_RootConstrainSelectedInstOperands,
     /*  49320 */     // GIR_Coverage, 1898,
     /*  49320 */     GIR_EraseRootFromParent_Done,
     /*  49321 */   // Label 768: @49321
     /*  49321 */   GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(49368), // Rule ID 1796 //
     /*  49326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49329 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49333 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49337 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49341 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49345 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49347 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  49354 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SSUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  49354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i32_v2i64),
     /*  49357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49359 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49361 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49366 */     GIR_RootConstrainSelectedInstOperands,
     /*  49367 */     // GIR_Coverage, 1796,
     /*  49367 */     GIR_EraseRootFromParent_Done,
     /*  49368 */   // Label 769: @49368
     /*  49368 */   GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(49415), // Rule ID 1897 //
     /*  49373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49392 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49394 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /*  49401 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (USUBWv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  49401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i32_v2i64),
     /*  49404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49406 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  49413 */     GIR_RootConstrainSelectedInstOperands,
     /*  49414 */     // GIR_Coverage, 1897,
     /*  49414 */     GIR_EraseRootFromParent_Done,
     /*  49415 */   // Label 770: @49415
     /*  49415 */   GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(49474), // Rule ID 1882 //
     /*  49420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49423 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49427 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49431 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49435 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49440 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49444 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49448 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49452 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49457 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49459 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  49462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49472 */     GIR_RootConstrainSelectedInstOperands,
     /*  49473 */     // GIR_Coverage, 1882,
     /*  49473 */     GIR_EraseRootFromParent_Done,
     /*  49474 */   // Label 771: @49474
     /*  49474 */   GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(49533), // Rule ID 1881 //
     /*  49479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49482 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49486 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49490 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49494 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49499 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49503 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49507 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49511 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49516 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49518 */     // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  49521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49531 */     GIR_RootConstrainSelectedInstOperands,
     /*  49532 */     // GIR_Coverage, 1881,
     /*  49532 */     GIR_EraseRootFromParent_Done,
     /*  49533 */   // Label 772: @49533
     /*  49533 */   GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(49592), // Rule ID 1789 //
     /*  49538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49549 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49553 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49562 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49566 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49570 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49575 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49577 */     // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv2i32_v2i64),
     /*  49580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49582 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49590 */     GIR_RootConstrainSelectedInstOperands,
     /*  49591 */     // GIR_Coverage, 1789,
     /*  49591 */     GIR_EraseRootFromParent_Done,
     /*  49592 */   // Label 773: @49592
     /*  49592 */   GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(49651), // Rule ID 1880 //
     /*  49597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49612 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49617 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49621 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49625 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49629 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49634 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49636 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  49639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49641 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49645 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49649 */     GIR_RootConstrainSelectedInstOperands,
     /*  49650 */     // GIR_Coverage, 1880,
     /*  49650 */     GIR_EraseRootFromParent_Done,
     /*  49651 */   // Label 774: @49651
     /*  49651 */   GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(49710), // Rule ID 1879 //
     /*  49656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49659 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49663 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49667 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49671 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  49680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49684 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49688 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49693 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  49695 */     // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn), (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv2i32_v2i64),
     /*  49698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  49708 */     GIR_RootConstrainSelectedInstOperands,
     /*  49709 */     // GIR_Coverage, 1879,
     /*  49709 */     GIR_EraseRootFromParent_Done,
     /*  49710 */   // Label 775: @49710
     /*  49710 */   GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(49745), // Rule ID 1001 //
     /*  49715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  49722 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  49728 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  49730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49736 */     // (sub:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn)  =>  (NEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /*  49736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv2i64),
     /*  49739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  49743 */     GIR_RootConstrainSelectedInstOperands,
     /*  49744 */     // GIR_Coverage, 1001,
     /*  49744 */     GIR_EraseRootFromParent_Done,
     /*  49745 */   // Label 776: @49745
     /*  49745 */   GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(49802), // Rule ID 1765 //
     /*  49750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49753 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49757 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49761 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  49765 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49769 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  49773 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49778 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49783 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49785 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv2i32_v2i64),
     /*  49788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49790 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  49800 */     GIR_RootConstrainSelectedInstOperands,
     /*  49801 */     // GIR_Coverage, 1765,
     /*  49801 */     GIR_EraseRootFromParent_Done,
     /*  49802 */   // Label 777: @49802
     /*  49802 */   GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(49859), // Rule ID 1855 //
     /*  49807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  49822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49826 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  49830 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49840 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49842 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv2i32_v2i64),
     /*  49845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  49847 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  49849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  49853 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  49857 */     GIR_RootConstrainSelectedInstOperands,
     /*  49858 */     // GIR_Coverage, 1855,
     /*  49858 */     GIR_EraseRootFromParent_Done,
     /*  49859 */   // Label 778: @49859
     /*  49859 */   GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(49903), // Rule ID 1896 //
     /*  49864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  49879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49883 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49888 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49890 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  49893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49895 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49897 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  49901 */     GIR_RootConstrainSelectedInstOperands,
     /*  49902 */     // GIR_Coverage, 1896,
     /*  49902 */     GIR_EraseRootFromParent_Done,
     /*  49903 */   // Label 779: @49903
     /*  49903 */   GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(49947), // Rule ID 1795 //
     /*  49908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49911 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  49923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49927 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49932 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49934 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (SSUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv2i32_v2i64),
     /*  49937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49939 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  49945 */     GIR_RootConstrainSelectedInstOperands,
     /*  49946 */     // GIR_Coverage, 1795,
     /*  49946 */     GIR_EraseRootFromParent_Done,
     /*  49947 */   // Label 780: @49947
     /*  49947 */   GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(49991), // Rule ID 1895 //
     /*  49952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49955 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  49959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  49963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  49967 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  49971 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  49976 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  49978 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm))  =>  (USUBWv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  49978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv2i32_v2i64),
     /*  49981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  49983 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  49985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  49989 */     GIR_RootConstrainSelectedInstOperands,
     /*  49990 */     // GIR_Coverage, 1895,
     /*  49990 */     GIR_EraseRootFromParent_Done,
     /*  49991 */   // Label 781: @49991
     /*  49991 */   GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(50014), // Rule ID 1496 //
     /*  49996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  49999 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50003 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50007 */     // (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  50007 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv2i64),
     /*  50012 */     GIR_RootConstrainSelectedInstOperands,
     /*  50013 */     // GIR_Coverage, 1496,
     /*  50013 */     GIR_Done,
     /*  50014 */   // Label 782: @50014
     /*  50014 */   GIM_Reject,
     /*  50015 */ // Label 748: @50015
     /*  50015 */ GIM_Reject,
     /*  50016 */ // Label 665: @50016
     /*  50016 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(51506),
     /*  50021 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  50024 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  50027 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50031 */   GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(50163), // Rule ID 5992 //
     /*  50036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50048 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50052 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50056 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50060 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50065 */     // MIs[1] Operand 2
     /*  50065 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50076 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  50080 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50084 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50088 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  50092 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50096 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50100 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50105 */     // MIs[3] Operand 2
     /*  50105 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  50116 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  50118 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50118 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50121 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  50125 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50130 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50134 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  50138 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50145 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50162 */     // GIR_Coverage, 5992,
     /*  50162 */     GIR_EraseRootFromParent_Done,
     /*  50163 */   // Label 784: @50163
     /*  50163 */   GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(50295), // Rule ID 5991 //
     /*  50168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50188 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50192 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50197 */     // MIs[1] Operand 2
     /*  50197 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50208 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  50212 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50216 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50220 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  50224 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50228 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50232 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50237 */     // MIs[3] Operand 2
     /*  50237 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  50248 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  50250 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50250 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50253 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  50257 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50262 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50266 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  50270 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50277 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50284 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50289 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50294 */     // GIR_Coverage, 5991,
     /*  50294 */     GIR_EraseRootFromParent_Done,
     /*  50295 */   // Label 785: @50295
     /*  50295 */   GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(50427), // Rule ID 6007 //
     /*  50300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50308 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50312 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50316 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  50320 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50324 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50329 */     // MIs[1] Operand 2
     /*  50329 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50340 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  50344 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50348 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50352 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  50356 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  50360 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50364 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50369 */     // MIs[3] Operand 2
     /*  50369 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  50380 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  50382 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50382 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50385 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i8_v8i16),
     /*  50389 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50394 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50398 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  50402 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50409 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50416 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50421 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50426 */     // GIR_Coverage, 6007,
     /*  50426 */     GIR_EraseRootFromParent_Done,
     /*  50427 */   // Label 786: @50427
     /*  50427 */   GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(50559), // Rule ID 5990 //
     /*  50432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50440 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50444 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50448 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50452 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50456 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50461 */     // MIs[1] Operand 2
     /*  50461 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50472 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  50476 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50480 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50484 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  50488 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  50492 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50496 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50501 */     // MIs[3] Operand 2
     /*  50501 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  50512 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  50514 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50514 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50517 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  50521 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50526 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50530 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  50534 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50541 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50548 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50553 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50558 */     // GIR_Coverage, 5990,
     /*  50558 */     GIR_EraseRootFromParent_Done,
     /*  50559 */   // Label 787: @50559
     /*  50559 */   GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(50691), // Rule ID 5989 //
     /*  50564 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  50568 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50572 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50576 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50580 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50584 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50588 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50593 */     // MIs[1] Operand 2
     /*  50593 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50604 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  50608 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50612 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50616 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  50620 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  50624 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50628 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50633 */     // MIs[3] Operand 2
     /*  50633 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /*  50644 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  50646 */     // (sub:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50646 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50649 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  50653 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50658 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50662 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /*  50666 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50673 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50680 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50685 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50690 */     // GIR_Coverage, 5989,
     /*  50690 */     GIR_EraseRootFromParent_Done,
     /*  50691 */   // Label 788: @50691
     /*  50691 */   GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(50850), // Rule ID 5962 //
     /*  50696 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50712 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50716 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SMULL),
     /*  50720 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50724 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  50728 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50733 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50738 */     // MIs[1] Operand 2
     /*  50738 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50749 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50751 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SMLSLv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50751 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  50754 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  50758 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50763 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  50765 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  50768 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  50772 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50777 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  50780 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  50784 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  50787 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50792 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50797 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50802 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50805 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i8_v8i16),
     /*  50809 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50814 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  50817 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50821 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  50825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50832 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50839 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50844 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50849 */     // GIR_Coverage, 5962,
     /*  50849 */     GIR_EraseRootFromParent_Done,
     /*  50850 */   // Label 789: @50850
     /*  50850 */   GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(51009), // Rule ID 5959 //
     /*  50855 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50859 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  50863 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  50867 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  50871 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  50875 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UMULL),
     /*  50879 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  50883 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  50887 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50892 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50897 */     // MIs[1] Operand 2
     /*  50897 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  50908 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  50910 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Ra, (extract_subvector:{ *:[v4i16] } (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (UMLSLv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Ra, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  50910 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  50913 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  50917 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50922 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  50924 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  50927 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  50931 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50936 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  50939 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ra
     /*  50943 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  50946 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50951 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  50956 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  50961 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  50964 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i8_v8i16),
     /*  50968 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  50973 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  50976 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  50980 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  50984 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  50986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  50989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  50991 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  50998 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51003 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51008 */     // GIR_Coverage, 5959,
     /*  51008 */     GIR_EraseRootFromParent_Done,
     /*  51009 */   // Label 790: @51009
     /*  51009 */   GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(51155), // Rule ID 6002 //
     /*  51014 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51030 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  51034 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51038 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51042 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51047 */     // MIs[1] Operand 2
     /*  51047 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  51058 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51060 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  51060 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  51063 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  51067 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51072 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  51074 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  51077 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  51081 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51086 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  51089 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  51093 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  51096 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51101 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51106 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51111 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  51114 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  51118 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51123 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  51126 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51130 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  51132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  51135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51137 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  51144 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51149 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51154 */     // GIR_Coverage, 6002,
     /*  51154 */     GIR_EraseRootFromParent_Done,
     /*  51155 */   // Label 791: @51155
     /*  51155 */   GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(51301), // Rule ID 6010 //
     /*  51160 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  51180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  51184 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51188 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51193 */     // MIs[1] Operand 2
     /*  51193 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  51204 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51206 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (SSUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  51206 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  51209 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  51213 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51218 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  51220 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  51223 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  51227 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51232 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  51235 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  51239 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  51242 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51247 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51252 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  51260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i8_v8i16),
     /*  51264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51269 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  51272 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51276 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  51278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  51281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51283 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  51290 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51295 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51300 */     // GIR_Coverage, 6010,
     /*  51300 */     GIR_EraseRootFromParent_Done,
     /*  51301 */   // Label 792: @51301
     /*  51301 */   GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(51447), // Rule ID 6001 //
     /*  51306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  51326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  51330 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  51334 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51339 */     // MIs[1] Operand 2
     /*  51339 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  51350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  51352 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (USUBWv8i8_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V64:{ *:[v8i8] }:$Rm), dsub:{ *:[i32] })
     /*  51352 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /*  51355 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  51359 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51364 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  51366 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  51369 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  51373 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51378 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  51381 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /*  51385 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  51388 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51393 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51398 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51403 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  51406 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  51410 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  51415 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  51418 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  51422 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  51424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  51427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51429 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  51436 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51441 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51446 */     // GIR_Coverage, 6001,
     /*  51446 */     GIR_EraseRootFromParent_Done,
     /*  51447 */   // Label 793: @51447
     /*  51447 */   GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(51482), // Rule ID 997 //
     /*  51452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51455 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51459 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  51465 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  51467 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51471 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  51473 */     // (sub:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn)  =>  (NEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /*  51473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i16),
     /*  51476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  51478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  51480 */     GIR_RootConstrainSelectedInstOperands,
     /*  51481 */     // GIR_Coverage, 997,
     /*  51481 */     GIR_EraseRootFromParent_Done,
     /*  51482 */   // Label 794: @51482
     /*  51482 */   GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(51505), // Rule ID 1492 //
     /*  51487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51494 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  51498 */     // (sub:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  51498 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i16),
     /*  51503 */     GIR_RootConstrainSelectedInstOperands,
     /*  51504 */     // GIR_Coverage, 1492,
     /*  51504 */     GIR_Done,
     /*  51505 */   // Label 795: @51505
     /*  51505 */   GIM_Reject,
     /*  51506 */ // Label 783: @51506
     /*  51506 */ GIM_Reject,
     /*  51507 */ // Label 666: @51507
     /*  51507 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(53966),
     /*  51512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  51515 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  51518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51522 */   GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(51636), // Rule ID 2076 //
     /*  51527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51530 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  51542 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  51546 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  51550 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  51554 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51558 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51562 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  51566 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  51570 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51574 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  51578 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  51583 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  51587 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  51591 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  51595 */     // MIs[4] Operand 1
     /*  51595 */     // No operand predicates
     /*  51595 */     // MIs[2] Operand 2
     /*  51595 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  51606 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  51608 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  51615 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  51615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_indexed),
     /*  51618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51620 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51622 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  51627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  51631 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  51634 */     GIR_RootConstrainSelectedInstOperands,
     /*  51635 */     // GIR_Coverage, 2076,
     /*  51635 */     GIR_EraseRootFromParent_Done,
     /*  51636 */   // Label 797: @51636
     /*  51636 */   GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(51750), // Rule ID 14533 //
     /*  51641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51644 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  51656 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  51660 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  51664 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  51668 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51672 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51676 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  51680 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  51684 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51688 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  51692 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  51697 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  51701 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  51705 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  51709 */     // MIs[4] Operand 1
     /*  51709 */     // No operand predicates
     /*  51709 */     // MIs[2] Operand 2
     /*  51709 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  51720 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  51722 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  51729 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (SMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  51729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_indexed),
     /*  51732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51734 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  51741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  51745 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  51748 */     GIR_RootConstrainSelectedInstOperands,
     /*  51749 */     // GIR_Coverage, 14533,
     /*  51749 */     GIR_EraseRootFromParent_Done,
     /*  51750 */   // Label 798: @51750
     /*  51750 */   GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(51864), // Rule ID 2128 //
     /*  51755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51758 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51762 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51766 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  51770 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  51774 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  51778 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  51782 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51786 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51790 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  51794 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  51798 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51802 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  51806 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  51811 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  51815 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  51819 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  51823 */     // MIs[4] Operand 1
     /*  51823 */     // No operand predicates
     /*  51823 */     // MIs[2] Operand 2
     /*  51823 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  51834 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  51836 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  51843 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (UMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  51843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_indexed),
     /*  51846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51848 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  51855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  51859 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  51862 */     GIR_RootConstrainSelectedInstOperands,
     /*  51863 */     // GIR_Coverage, 2128,
     /*  51863 */     GIR_EraseRootFromParent_Done,
     /*  51864 */   // Label 799: @51864
     /*  51864 */   GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(51978), // Rule ID 14569 //
     /*  51869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51872 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  51876 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  51880 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  51884 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  51888 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  51892 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  51896 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  51900 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51904 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  51908 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  51912 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  51916 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  51920 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  51925 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  51929 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  51933 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  51937 */     // MIs[4] Operand 1
     /*  51937 */     // No operand predicates
     /*  51937 */     // MIs[2] Operand 2
     /*  51937 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /*  51948 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  51950 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  51957 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)))  =>  (UMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  51957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_indexed),
     /*  51960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  51962 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  51964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  51969 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  51973 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  51976 */     GIR_RootConstrainSelectedInstOperands,
     /*  51977 */     // GIR_Coverage, 14569,
     /*  51977 */     GIR_EraseRootFromParent_Done,
     /*  51978 */   // Label 800: @51978
     /*  51978 */   GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(52043), // Rule ID 1878 //
     /*  51983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  51986 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  51990 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  51994 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  51998 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52002 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  52006 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52010 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52012 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52019 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52026 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  52029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52041 */     GIR_RootConstrainSelectedInstOperands,
     /*  52042 */     // GIR_Coverage, 1878,
     /*  52042 */     GIR_EraseRootFromParent_Done,
     /*  52043 */   // Label 801: @52043
     /*  52043 */   GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(52108), // Rule ID 1877 //
     /*  52048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52051 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52055 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  52059 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52063 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52067 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52071 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52075 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52077 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52084 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52091 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  52094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52101 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52106 */     GIR_RootConstrainSelectedInstOperands,
     /*  52107 */     // GIR_Coverage, 1877,
     /*  52107 */     GIR_EraseRootFromParent_Done,
     /*  52108 */   // Label 802: @52108
     /*  52108 */   GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(52173), // Rule ID 1788 //
     /*  52113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  52124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52128 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52132 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  52136 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52140 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52142 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52149 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52156 */     // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SSUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i16_v4i32),
     /*  52159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52161 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52171 */     GIR_RootConstrainSelectedInstOperands,
     /*  52172 */     // GIR_Coverage, 1788,
     /*  52172 */     GIR_EraseRootFromParent_Done,
     /*  52173 */   // Label 803: @52173
     /*  52173 */   GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(52238), // Rule ID 1876 //
     /*  52178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52193 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52197 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  52201 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52205 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52207 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52214 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52221 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  52224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52226 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52231 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52236 */     GIR_RootConstrainSelectedInstOperands,
     /*  52237 */     // GIR_Coverage, 1876,
     /*  52237 */     GIR_EraseRootFromParent_Done,
     /*  52238 */   // Label 804: @52238
     /*  52238 */   GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(52303), // Rule ID 1875 //
     /*  52243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  52250 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52254 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  52262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  52266 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52270 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  52272 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52279 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52286 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn)), (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i16_v4i32),
     /*  52289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  52291 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52296 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52301 */     GIR_RootConstrainSelectedInstOperands,
     /*  52302 */     // GIR_Coverage, 1875,
     /*  52302 */     GIR_EraseRootFromParent_Done,
     /*  52303 */   // Label 805: @52303
     /*  52303 */   GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(52414), // Rule ID 14531 //
     /*  52308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52311 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  52323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52327 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  52335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  52339 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52343 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  52347 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  52351 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52355 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  52359 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  52364 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  52368 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52372 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  52376 */     // MIs[4] Operand 1
     /*  52376 */     // No operand predicates
     /*  52376 */     // MIs[2] Operand 2
     /*  52376 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  52387 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52392 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  52394 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  52394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  52397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52399 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52401 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52405 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  52409 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  52412 */     GIR_RootConstrainSelectedInstOperands,
     /*  52413 */     // GIR_Coverage, 14531,
     /*  52413 */     GIR_EraseRootFromParent_Done,
     /*  52414 */   // Label 806: @52414
     /*  52414 */   GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(52525), // Rule ID 2074 //
     /*  52419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52422 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  52434 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52438 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  52451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  52455 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52459 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  52463 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  52467 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52471 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  52475 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  52480 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  52484 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52488 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  52492 */     // MIs[4] Operand 1
     /*  52492 */     // No operand predicates
     /*  52492 */     // MIs[2] Operand 2
     /*  52492 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  52503 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  52505 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  52505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  52508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52510 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  52516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  52520 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  52523 */     GIR_RootConstrainSelectedInstOperands,
     /*  52524 */     // GIR_Coverage, 2074,
     /*  52524 */     GIR_EraseRootFromParent_Done,
     /*  52525 */   // Label 807: @52525
     /*  52525 */   GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(52636), // Rule ID 14567 //
     /*  52530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52533 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  52545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  52557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  52561 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52565 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  52569 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  52573 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52577 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  52581 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  52586 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  52590 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52594 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  52598 */     // MIs[4] Operand 1
     /*  52598 */     // No operand predicates
     /*  52598 */     // MIs[2] Operand 2
     /*  52598 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  52609 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52614 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  52616 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  52616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  52619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52621 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52627 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  52631 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  52634 */     GIR_RootConstrainSelectedInstOperands,
     /*  52635 */     // GIR_Coverage, 14567,
     /*  52635 */     GIR_EraseRootFromParent_Done,
     /*  52636 */   // Label 808: @52636
     /*  52636 */   GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(52747), // Rule ID 2126 //
     /*  52641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52644 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  52656 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52660 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52664 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52669 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  52673 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  52677 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52681 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  52685 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  52689 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52693 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  52697 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  52702 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  52706 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52710 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  52714 */     // MIs[4] Operand 1
     /*  52714 */     // No operand predicates
     /*  52714 */     // MIs[2] Operand 2
     /*  52714 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /*  52725 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  52727 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  52727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  52730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52732 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  52738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /*  52742 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /*  52745 */     GIR_RootConstrainSelectedInstOperands,
     /*  52746 */     // GIR_Coverage, 2126,
     /*  52746 */     GIR_EraseRootFromParent_Done,
     /*  52747 */   // Label 809: @52747
     /*  52747 */   GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(52810), // Rule ID 1764 //
     /*  52752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52755 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52763 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  52767 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52771 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52775 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  52777 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52784 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52791 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i16_v4i32),
     /*  52794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52796 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52808 */     GIR_RootConstrainSelectedInstOperands,
     /*  52809 */     // GIR_Coverage, 1764,
     /*  52809 */     GIR_EraseRootFromParent_Done,
     /*  52810 */   // Label 810: @52810
     /*  52810 */   GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(52873), // Rule ID 1854 //
     /*  52815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52818 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  52830 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52834 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52838 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  52840 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52847 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  52854 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  52854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i16_v4i32),
     /*  52857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52859 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  52866 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  52871 */     GIR_RootConstrainSelectedInstOperands,
     /*  52872 */     // GIR_Coverage, 1854,
     /*  52872 */     GIR_EraseRootFromParent_Done,
     /*  52873 */   // Label 811: @52873
     /*  52873 */   GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(52961), // Rule ID 14532 //
     /*  52878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52881 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52885 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52889 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  52893 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52897 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52901 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  52905 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  52909 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  52913 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  52917 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  52922 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  52926 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  52930 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  52934 */     // MIs[3] Operand 1
     /*  52934 */     // No operand predicates
     /*  52934 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52939 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  52941 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  52941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  52944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  52946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  52948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  52952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  52956 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  52959 */     GIR_RootConstrainSelectedInstOperands,
     /*  52960 */     // GIR_Coverage, 14532,
     /*  52960 */     GIR_EraseRootFromParent_Done,
     /*  52961 */   // Label 812: @52961
     /*  52961 */   GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(53049), // Rule ID 2075 //
     /*  52966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  52969 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  52973 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  52977 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  52981 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  52985 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  52989 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  52994 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  52998 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  53002 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  53006 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53010 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  53015 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53019 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53023 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  53027 */     // MIs[3] Operand 1
     /*  53027 */     // No operand predicates
     /*  53027 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  53029 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_indexed),
     /*  53032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  53034 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  53036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53044 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  53047 */     GIR_RootConstrainSelectedInstOperands,
     /*  53048 */     // GIR_Coverage, 2075,
     /*  53048 */     GIR_EraseRootFromParent_Done,
     /*  53049 */   // Label 813: @53049
     /*  53049 */   GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(53137), // Rule ID 14568 //
     /*  53054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53057 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53061 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53065 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  53069 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53073 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  53077 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  53081 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  53085 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  53089 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53093 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  53098 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53102 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53106 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  53110 */     // MIs[3] Operand 1
     /*  53110 */     // No operand predicates
     /*  53110 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53115 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  53117 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  53120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  53122 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  53124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  53128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53132 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  53135 */     GIR_RootConstrainSelectedInstOperands,
     /*  53136 */     // GIR_Coverage, 14568,
     /*  53136 */     GIR_EraseRootFromParent_Done,
     /*  53137 */   // Label 814: @53137
     /*  53137 */   GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(53225), // Rule ID 2127 //
     /*  53142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53145 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  53157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  53165 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53170 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  53174 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  53178 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  53182 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  53186 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  53191 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  53195 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  53199 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  53203 */     // MIs[3] Operand 1
     /*  53203 */     // No operand predicates
     /*  53203 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  53205 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (UMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  53205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_indexed),
     /*  53208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  53210 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  53212 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53220 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  53223 */     GIR_RootConstrainSelectedInstOperands,
     /*  53224 */     // GIR_Coverage, 2127,
     /*  53224 */     GIR_EraseRootFromParent_Done,
     /*  53225 */   // Label 815: @53225
     /*  53225 */   GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(53272), // Rule ID 1894 //
     /*  53230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53249 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53251 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  53258 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  53258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
     /*  53261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53263 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53265 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  53270 */     GIR_RootConstrainSelectedInstOperands,
     /*  53271 */     // GIR_Coverage, 1894,
     /*  53271 */     GIR_EraseRootFromParent_Done,
     /*  53272 */   // Label 816: @53272
     /*  53272 */   GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(53319), // Rule ID 1794 //
     /*  53277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53280 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53298 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  53305 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SSUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  53305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i16_v4i32),
     /*  53308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53310 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  53317 */     GIR_RootConstrainSelectedInstOperands,
     /*  53318 */     // GIR_Coverage, 1794,
     /*  53318 */     GIR_EraseRootFromParent_Done,
     /*  53319 */   // Label 817: @53319
     /*  53319 */   GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(53366), // Rule ID 1893 //
     /*  53324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53327 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53343 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53345 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /*  53352 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (USUBWv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  53352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i16_v4i32),
     /*  53355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53357 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  53364 */     GIR_RootConstrainSelectedInstOperands,
     /*  53365 */     // GIR_Coverage, 1893,
     /*  53365 */     GIR_EraseRootFromParent_Done,
     /*  53366 */   // Label 818: @53366
     /*  53366 */   GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(53425), // Rule ID 1874 //
     /*  53371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53391 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53395 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53399 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53403 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53408 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53410 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  53413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53423 */     GIR_RootConstrainSelectedInstOperands,
     /*  53424 */     // GIR_Coverage, 1874,
     /*  53424 */     GIR_EraseRootFromParent_Done,
     /*  53425 */   // Label 819: @53425
     /*  53425 */   GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(53484), // Rule ID 1873 //
     /*  53430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53437 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53441 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53445 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53450 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53454 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53458 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53462 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53467 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53469 */     // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  53472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53474 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53482 */     GIR_RootConstrainSelectedInstOperands,
     /*  53483 */     // GIR_Coverage, 1873,
     /*  53483 */     GIR_EraseRootFromParent_Done,
     /*  53484 */   // Label 820: @53484
     /*  53484 */   GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(53543), // Rule ID 1787 //
     /*  53489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53492 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53496 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53500 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53504 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53509 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53513 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53517 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53521 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53526 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53528 */     // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv4i16_v4i32),
     /*  53531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53541 */     GIR_RootConstrainSelectedInstOperands,
     /*  53542 */     // GIR_Coverage, 1787,
     /*  53542 */     GIR_EraseRootFromParent_Done,
     /*  53543 */   // Label 821: @53543
     /*  53543 */   GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(53602), // Rule ID 1872 //
     /*  53548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53580 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53587 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  53590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53596 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53600 */     GIR_RootConstrainSelectedInstOperands,
     /*  53601 */     // GIR_Coverage, 1872,
     /*  53601 */     GIR_EraseRootFromParent_Done,
     /*  53602 */   // Label 822: @53602
     /*  53602 */   GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(53661), // Rule ID 1871 //
     /*  53607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53610 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53614 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53618 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53622 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53627 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  53631 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53635 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53639 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53644 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  53646 */     // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn), (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv4i16_v4i32),
     /*  53649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53651 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53655 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  53659 */     GIR_RootConstrainSelectedInstOperands,
     /*  53660 */     // GIR_Coverage, 1871,
     /*  53660 */     GIR_EraseRootFromParent_Done,
     /*  53661 */   // Label 823: @53661
     /*  53661 */   GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(53696), // Rule ID 1000 //
     /*  53666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53673 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  53679 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  53681 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53685 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53687 */     // (sub:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn)  =>  (NEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /*  53687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv4i32),
     /*  53690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  53694 */     GIR_RootConstrainSelectedInstOperands,
     /*  53695 */     // GIR_Coverage, 1000,
     /*  53695 */     GIR_EraseRootFromParent_Done,
     /*  53696 */   // Label 824: @53696
     /*  53696 */   GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(53753), // Rule ID 1763 //
     /*  53701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53704 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53712 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  53716 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  53724 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53729 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53736 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv4i16_v4i32),
     /*  53739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  53741 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  53743 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  53751 */     GIR_RootConstrainSelectedInstOperands,
     /*  53752 */     // GIR_Coverage, 1763,
     /*  53752 */     GIR_EraseRootFromParent_Done,
     /*  53753 */   // Label 825: @53753
     /*  53753 */   GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(53810), // Rule ID 1853 //
     /*  53758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53761 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53765 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53769 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  53773 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53777 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  53781 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53786 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53791 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53793 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv4i16_v4i32),
     /*  53796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  53798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  53800 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  53804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  53808 */     GIR_RootConstrainSelectedInstOperands,
     /*  53809 */     // GIR_Coverage, 1853,
     /*  53809 */     GIR_EraseRootFromParent_Done,
     /*  53810 */   // Label 826: @53810
     /*  53810 */   GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(53854), // Rule ID 1892 //
     /*  53815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53818 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  53830 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53834 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53839 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53841 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  53844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53846 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53852 */     GIR_RootConstrainSelectedInstOperands,
     /*  53853 */     // GIR_Coverage, 1892,
     /*  53853 */     GIR_EraseRootFromParent_Done,
     /*  53854 */   // Label 827: @53854
     /*  53854 */   GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(53898), // Rule ID 1793 //
     /*  53859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53862 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  53874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53878 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53883 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53885 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (SSUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv4i16_v4i32),
     /*  53888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53890 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53896 */     GIR_RootConstrainSelectedInstOperands,
     /*  53897 */     // GIR_Coverage, 1793,
     /*  53897 */     GIR_EraseRootFromParent_Done,
     /*  53898 */   // Label 828: @53898
     /*  53898 */   GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(53942), // Rule ID 1891 //
     /*  53903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53906 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  53914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  53918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  53922 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53927 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  53929 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm))  =>  (USUBWv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  53929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv4i16_v4i32),
     /*  53932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  53934 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  53936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  53940 */     GIR_RootConstrainSelectedInstOperands,
     /*  53941 */     // GIR_Coverage, 1891,
     /*  53941 */     GIR_EraseRootFromParent_Done,
     /*  53942 */   // Label 829: @53942
     /*  53942 */   GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(53965), // Rule ID 1495 //
     /*  53947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53950 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53954 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  53958 */     // (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  53958 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv4i32),
     /*  53963 */     GIR_RootConstrainSelectedInstOperands,
     /*  53964 */     // GIR_Coverage, 1495,
     /*  53964 */     GIR_Done,
     /*  53965 */   // Label 830: @53965
     /*  53965 */   GIM_Reject,
     /*  53966 */ // Label 796: @53966
     /*  53966 */ GIM_Reject,
     /*  53967 */ // Label 667: @53967
     /*  53967 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(54041),
     /*  53972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  53975 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  53978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  53982 */   GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(54017), // Rule ID 995 //
     /*  53987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  53990 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  53994 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  54000 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  54002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54006 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54008 */     // (sub:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn)  =>  (NEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /*  54008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i8),
     /*  54011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54015 */     GIR_RootConstrainSelectedInstOperands,
     /*  54016 */     // GIR_Coverage, 995,
     /*  54016 */     GIR_EraseRootFromParent_Done,
     /*  54017 */   // Label 832: @54017
     /*  54017 */   GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(54040), // Rule ID 1490 //
     /*  54022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54025 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54029 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54033 */     // (sub:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54033 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i8),
     /*  54038 */     GIR_RootConstrainSelectedInstOperands,
     /*  54039 */     // GIR_Coverage, 1490,
     /*  54039 */     GIR_Done,
     /*  54040 */   // Label 833: @54040
     /*  54040 */   GIM_Reject,
     /*  54041 */ // Label 831: @54041
     /*  54041 */ GIM_Reject,
     /*  54042 */ // Label 668: @54042
     /*  54042 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(55249),
     /*  54047 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  54050 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  54053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54057 */   GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(54122), // Rule ID 1870 //
     /*  54062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54073 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54077 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54081 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54085 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54089 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54091 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54098 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54105 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  54108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54120 */     GIR_RootConstrainSelectedInstOperands,
     /*  54121 */     // GIR_Coverage, 1870,
     /*  54121 */     GIR_EraseRootFromParent_Done,
     /*  54122 */   // Label 835: @54122
     /*  54122 */   GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(54187), // Rule ID 1869 //
     /*  54127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54134 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54138 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54150 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54154 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54156 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54163 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54170 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  54173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54185 */     GIR_RootConstrainSelectedInstOperands,
     /*  54186 */     // GIR_Coverage, 1869,
     /*  54186 */     GIR_EraseRootFromParent_Done,
     /*  54187 */   // Label 836: @54187
     /*  54187 */   GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(54252), // Rule ID 1786 //
     /*  54192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54199 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  54203 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54207 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54211 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  54215 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54219 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54221 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54228 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54235 */     // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SSUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv16i8_v8i16),
     /*  54238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54245 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54250 */     GIR_RootConstrainSelectedInstOperands,
     /*  54251 */     // GIR_Coverage, 1786,
     /*  54251 */     GIR_EraseRootFromParent_Done,
     /*  54252 */   // Label 837: @54252
     /*  54252 */   GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(54317), // Rule ID 1868 //
     /*  54257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54260 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54264 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54268 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54272 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54276 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54280 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54284 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54286 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54293 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54300 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  54303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54305 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54310 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54315 */     GIR_RootConstrainSelectedInstOperands,
     /*  54316 */     // GIR_Coverage, 1868,
     /*  54316 */     GIR_EraseRootFromParent_Done,
     /*  54317 */   // Label 838: @54317
     /*  54317 */   GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(54382), // Rule ID 1867 //
     /*  54322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54345 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54349 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54351 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54358 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54365 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn)), (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv16i8_v8i16),
     /*  54368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54370 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54380 */     GIR_RootConstrainSelectedInstOperands,
     /*  54381 */     // GIR_Coverage, 1867,
     /*  54381 */     GIR_EraseRootFromParent_Done,
     /*  54382 */   // Label 839: @54382
     /*  54382 */   GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(54445), // Rule ID 1762 //
     /*  54387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54390 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  54402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54406 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  54410 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54412 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54419 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54426 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv16i8_v8i16),
     /*  54429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  54431 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  54433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54443 */     GIR_RootConstrainSelectedInstOperands,
     /*  54444 */     // GIR_Coverage, 1762,
     /*  54444 */     GIR_EraseRootFromParent_Done,
     /*  54445 */   // Label 840: @54445
     /*  54445 */   GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(54508), // Rule ID 1852 //
     /*  54450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54453 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54457 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54461 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  54465 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54469 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  54473 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54475 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54482 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54489 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UMLSLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv16i8_v8i16),
     /*  54492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  54494 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  54496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /*  54501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /*  54506 */     GIR_RootConstrainSelectedInstOperands,
     /*  54507 */     // GIR_Coverage, 1852,
     /*  54507 */     GIR_EraseRootFromParent_Done,
     /*  54508 */   // Label 841: @54508
     /*  54508 */   GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(54555), // Rule ID 1890 //
     /*  54513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54516 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54528 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54532 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54534 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54541 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
     /*  54544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54546 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  54553 */     GIR_RootConstrainSelectedInstOperands,
     /*  54554 */     // GIR_Coverage, 1890,
     /*  54554 */     GIR_EraseRootFromParent_Done,
     /*  54555 */   // Label 842: @54555
     /*  54555 */   GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(54602), // Rule ID 1792 //
     /*  54560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54563 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  54575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54579 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54581 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54588 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SSUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv16i8_v8i16),
     /*  54591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54593 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  54600 */     GIR_RootConstrainSelectedInstOperands,
     /*  54601 */     // GIR_Coverage, 1792,
     /*  54601 */     GIR_EraseRootFromParent_Done,
     /*  54602 */   // Label 843: @54602
     /*  54602 */   GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(54649), // Rule ID 1889 //
     /*  54607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54610 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54614 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54618 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54622 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54626 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54628 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /*  54635 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (USUBWv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  54635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv16i8_v8i16),
     /*  54638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54640 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  54642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rm
     /*  54647 */     GIR_RootConstrainSelectedInstOperands,
     /*  54648 */     // GIR_Coverage, 1889,
     /*  54648 */     GIR_EraseRootFromParent_Done,
     /*  54649 */   // Label 844: @54649
     /*  54649 */   GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(54708), // Rule ID 1866 //
     /*  54654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54669 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54674 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54678 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54682 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54686 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54691 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54693 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  54696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  54702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54706 */     GIR_RootConstrainSelectedInstOperands,
     /*  54707 */     // GIR_Coverage, 1866,
     /*  54707 */     GIR_EraseRootFromParent_Done,
     /*  54708 */   // Label 845: @54708
     /*  54708 */   GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(54767), // Rule ID 1865 //
     /*  54713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54728 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54733 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54737 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54741 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54745 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54750 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54752 */     // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  54755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  54761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54765 */     GIR_RootConstrainSelectedInstOperands,
     /*  54766 */     // GIR_Coverage, 1865,
     /*  54766 */     GIR_EraseRootFromParent_Done,
     /*  54767 */   // Label 846: @54767
     /*  54767 */   GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(54826), // Rule ID 1785 //
     /*  54772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  54783 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54787 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  54800 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54804 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54809 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54811 */     // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLv8i8_v8i16),
     /*  54814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54816 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  54820 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54824 */     GIR_RootConstrainSelectedInstOperands,
     /*  54825 */     // GIR_Coverage, 1785,
     /*  54825 */     GIR_EraseRootFromParent_Done,
     /*  54826 */   // Label 847: @54826
     /*  54826 */   GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(54885), // Rule ID 1864 //
     /*  54831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54842 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54846 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54851 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54855 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  54859 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54863 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54868 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54870 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  54873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  54879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54883 */     GIR_RootConstrainSelectedInstOperands,
     /*  54884 */     // GIR_Coverage, 1864,
     /*  54884 */     GIR_EraseRootFromParent_Done,
     /*  54885 */   // Label 848: @54885
     /*  54885 */   GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(54944), // Rule ID 1863 //
     /*  54890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54893 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54897 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54901 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54905 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54910 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  54914 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  54918 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  54922 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  54927 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  54929 */     // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn), (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  54929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLv8i8_v8i16),
     /*  54932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  54938 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  54942 */     GIR_RootConstrainSelectedInstOperands,
     /*  54943 */     // GIR_Coverage, 1863,
     /*  54943 */     GIR_EraseRootFromParent_Done,
     /*  54944 */   // Label 849: @54944
     /*  54944 */   GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(54979), // Rule ID 998 //
     /*  54949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  54956 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  54962 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  54964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54968 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  54970 */     // (sub:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn)  =>  (NEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /*  54970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv8i16),
     /*  54973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  54975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  54977 */     GIR_RootConstrainSelectedInstOperands,
     /*  54978 */     // GIR_Coverage, 998,
     /*  54978 */     GIR_EraseRootFromParent_Done,
     /*  54979 */   // Label 850: @54979
     /*  54979 */   GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(55036), // Rule ID 1761 //
     /*  54984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  54987 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  54991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  54995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SMULL),
     /*  54999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  55003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  55007 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55017 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55019 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  55019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLv8i8_v8i16),
     /*  55022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55024 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  55026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  55030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  55034 */     GIR_RootConstrainSelectedInstOperands,
     /*  55035 */     // GIR_Coverage, 1761,
     /*  55035 */     GIR_EraseRootFromParent_Done,
     /*  55036 */   // Label 851: @55036
     /*  55036 */   GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(55093), // Rule ID 1851 //
     /*  55041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55044 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55048 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55052 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UMULL),
     /*  55056 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  55060 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  55064 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55069 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55074 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55076 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UMLSLv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  55076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLv8i8_v8i16),
     /*  55079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  55081 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  55083 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  55087 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  55091 */     GIR_RootConstrainSelectedInstOperands,
     /*  55092 */     // GIR_Coverage, 1851,
     /*  55092 */     GIR_EraseRootFromParent_Done,
     /*  55093 */   // Label 852: @55093
     /*  55093 */   GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(55137), // Rule ID 1888 //
     /*  55098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55101 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  55113 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  55117 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55122 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55124 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  55124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  55127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55129 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55135 */     GIR_RootConstrainSelectedInstOperands,
     /*  55136 */     // GIR_Coverage, 1888,
     /*  55136 */     GIR_EraseRootFromParent_Done,
     /*  55137 */   // Label 853: @55137
     /*  55137 */   GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(55181), // Rule ID 1791 //
     /*  55142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55145 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  55157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  55161 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55166 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55168 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (SSUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  55168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWv8i8_v8i16),
     /*  55171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55173 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55179 */     GIR_RootConstrainSelectedInstOperands,
     /*  55180 */     // GIR_Coverage, 1791,
     /*  55180 */     GIR_EraseRootFromParent_Done,
     /*  55181 */   // Label 854: @55181
     /*  55181 */   GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(55225), // Rule ID 1887 //
     /*  55186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55189 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  55201 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  55205 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  55210 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55212 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm))  =>  (USUBWv8i8_v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  55212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWv8i8_v8i16),
     /*  55215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55217 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55223 */     GIR_RootConstrainSelectedInstOperands,
     /*  55224 */     // GIR_Coverage, 1887,
     /*  55224 */     GIR_EraseRootFromParent_Done,
     /*  55225 */   // Label 855: @55225
     /*  55225 */   GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(55248), // Rule ID 1493 //
     /*  55230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55241 */     // (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  55241 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv8i16),
     /*  55246 */     GIR_RootConstrainSelectedInstOperands,
     /*  55247 */     // GIR_Coverage, 1493,
     /*  55247 */     GIR_Done,
     /*  55248 */   // Label 856: @55248
     /*  55248 */   GIM_Reject,
     /*  55249 */ // Label 834: @55249
     /*  55249 */ GIM_Reject,
     /*  55250 */ // Label 669: @55250
     /*  55250 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(55324),
     /*  55255 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  55258 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  55261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55265 */   GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(55300), // Rule ID 996 //
     /*  55270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55277 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  55283 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /*  55285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55289 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55291 */     // (sub:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn)  =>  (NEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /*  55291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NEGv16i8),
     /*  55294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  55298 */     GIR_RootConstrainSelectedInstOperands,
     /*  55299 */     // GIR_Coverage, 996,
     /*  55299 */     GIR_EraseRootFromParent_Done,
     /*  55300 */   // Label 858: @55300
     /*  55300 */   GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(55323), // Rule ID 1491 //
     /*  55305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  55308 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55312 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  55316 */     // (sub:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  55316 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUBv16i8),
     /*  55321 */     GIR_RootConstrainSelectedInstOperands,
     /*  55322 */     // GIR_Coverage, 1491,
     /*  55322 */     GIR_Done,
     /*  55323 */   // Label 859: @55323
     /*  55323 */   GIM_Reject,
     /*  55324 */ // Label 857: @55324
     /*  55324 */ GIM_Reject,
     /*  55325 */ // Label 670: @55325
     /*  55325 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(55350), // Rule ID 8109 //
     /*  55330 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  55333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  55336 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  55339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  55343 */   // (sub:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  55343 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_D),
     /*  55348 */   GIR_RootConstrainSelectedInstOperands,
     /*  55349 */   // GIR_Coverage, 8109,
     /*  55349 */   GIR_Done,
     /*  55350 */ // Label 860: @55350
     /*  55350 */ GIM_Reject,
     /*  55351 */ // Label 671: @55351
     /*  55351 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(55376), // Rule ID 8108 //
     /*  55356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  55359 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  55362 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  55365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  55369 */   // (sub:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  55369 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_S),
     /*  55374 */   GIR_RootConstrainSelectedInstOperands,
     /*  55375 */   // GIR_Coverage, 8108,
     /*  55375 */   GIR_Done,
     /*  55376 */ // Label 861: @55376
     /*  55376 */ GIM_Reject,
     /*  55377 */ // Label 672: @55377
     /*  55377 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(55402), // Rule ID 8107 //
     /*  55382 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  55385 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  55388 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  55391 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  55395 */   // (sub:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  55395 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_H),
     /*  55400 */   GIR_RootConstrainSelectedInstOperands,
     /*  55401 */   // GIR_Coverage, 8107,
     /*  55401 */   GIR_Done,
     /*  55402 */ // Label 862: @55402
     /*  55402 */ GIM_Reject,
     /*  55403 */ // Label 673: @55403
     /*  55403 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(55428), // Rule ID 8106 //
     /*  55408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  55411 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  55414 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  55417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  55421 */   // (sub:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  55421 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SUB_ZZZ_B),
     /*  55426 */   GIR_RootConstrainSelectedInstOperands,
     /*  55427 */   // GIR_Coverage, 8106,
     /*  55427 */   GIR_Done,
     /*  55428 */ // Label 863: @55428
     /*  55428 */ GIM_Reject,
     /*  55429 */ // Label 674: @55429
     /*  55429 */ GIM_Reject,
     /*  55430 */ // Label 2: @55430
     /*  55430 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 872*/ GIMT_Encode4(58194),
     /*  55441 */ /*GILLT_s32*//*Label 864*/ GIMT_Encode4(55481),
     /*  55445 */ /*GILLT_s64*//*Label 865*/ GIMT_Encode4(55638), GIMT_Encode4(0),
     /*  55453 */ /*GILLT_v2s32*//*Label 866*/ GIMT_Encode4(57118), GIMT_Encode4(0),
     /*  55461 */ /*GILLT_v4s16*//*Label 867*/ GIMT_Encode4(57456),
     /*  55465 */ /*GILLT_v4s32*//*Label 868*/ GIMT_Encode4(57794),
     /*  55469 */ /*GILLT_v8s8*//*Label 869*/ GIMT_Encode4(57960),
     /*  55473 */ /*GILLT_v8s16*//*Label 870*/ GIMT_Encode4(57994),
     /*  55477 */ /*GILLT_v16s8*//*Label 871*/ GIMT_Encode4(58160),
     /*  55481 */ // Label 864: @55481
     /*  55481 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(55637),
     /*  55486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  55489 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  55492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55496 */   GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(55551), // Rule ID 4051 //
     /*  55501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  55509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55513 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  55517 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  55521 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55526 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55530 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55532 */     // (mul:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn), GPR32:{ *:[i32] }:$Rm)  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  55532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  55535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  55541 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  55543 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  55549 */     GIR_RootConstrainSelectedInstOperands,
     /*  55550 */     // GIR_Coverage, 4051,
     /*  55550 */     GIR_EraseRootFromParent_Done,
     /*  55551 */   // Label 874: @55551
     /*  55551 */   GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(55606), // Rule ID 14832 //
     /*  55556 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  55564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  55568 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55572 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  55576 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  55580 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55585 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  55587 */     // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (sub:{ *:[i32] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rn))  =>  (MSUBWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  55587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBWrrr),
     /*  55590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  55596 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  55598 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  55604 */     GIR_RootConstrainSelectedInstOperands,
     /*  55605 */     // GIR_Coverage, 14832,
     /*  55605 */     GIR_EraseRootFromParent_Done,
     /*  55606 */   // Label 875: @55606
     /*  55606 */   GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(55636), // Rule ID 4047 //
     /*  55611 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55619 */     // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (MADDWrrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, WZR:{ *:[i32] })
     /*  55619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDWrrr),
     /*  55622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55624 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  55626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  55628 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  55634 */     GIR_RootConstrainSelectedInstOperands,
     /*  55635 */     // GIR_Coverage, 4047,
     /*  55635 */     GIR_EraseRootFromParent_Done,
     /*  55636 */   // Label 876: @55636
     /*  55636 */   GIM_Reject,
     /*  55637 */ // Label 873: @55637
     /*  55637 */ GIM_Reject,
     /*  55638 */ // Label 865: @55638
     /*  55638 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(57117),
     /*  55643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  55646 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  55649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55653 */   GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(55799), // Rule ID 4056 //
     /*  55658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  55666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  55670 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55674 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55679 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /*  55690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  55694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  55698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  55702 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  55706 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55711 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295),
     /*  55722 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  55724 */     // (mul:{ *:[i64] } (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }), (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, 4294967295:{ *:[i64] }))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  55724 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  55727 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  55731 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55736 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  55742 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55747 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55752 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55755 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  55759 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55764 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  55770 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55775 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  55783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55785 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55788 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  55791 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  55797 */     GIR_RootConstrainSelectedInstOperands,
     /*  55798 */     // GIR_Coverage, 4056,
     /*  55798 */     GIR_EraseRootFromParent_Done,
     /*  55799 */   // Label 878: @55799
     /*  55799 */   GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(55903), // Rule ID 4057 //
     /*  55804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55808 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  55812 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  55816 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  55820 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55825 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /*  55836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  55840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  55844 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  55848 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55853 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  55855 */     // (mul:{ *:[i64] } (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  55855 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55858 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  55862 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55867 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  55873 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55878 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  55886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55888 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  55895 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  55901 */     GIR_RootConstrainSelectedInstOperands,
     /*  55902 */     // GIR_Coverage, 4057,
     /*  55902 */     GIR_EraseRootFromParent_Done,
     /*  55903 */   // Label 879: @55903
     /*  55903 */   GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(56007), // Rule ID 14835 //
     /*  55908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  55912 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  55916 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  55920 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55925 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  55929 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  55933 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  55937 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  55941 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55946 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294967295),
     /*  55957 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  55959 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] }))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  55959 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  55962 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  55966 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  55971 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  55977 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  55982 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  55987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  55990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  55992 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  55995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  55999 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56005 */     GIR_RootConstrainSelectedInstOperands,
     /*  56006 */     // GIR_Coverage, 14835,
     /*  56006 */     GIR_EraseRootFromParent_Done,
     /*  56007 */   // Label 880: @56007
     /*  56007 */   GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(56062), // Rule ID 4052 //
     /*  56012 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56016 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  56020 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56024 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56028 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  56032 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56037 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56041 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56043 */     // (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn), GPR64:{ *:[i64] }:$Rm)  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  56043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  56046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  56052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  56054 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56060 */     GIR_RootConstrainSelectedInstOperands,
     /*  56061 */     // GIR_Coverage, 4052,
     /*  56061 */     GIR_EraseRootFromParent_Done,
     /*  56062 */   // Label 881: @56062
     /*  56062 */   GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(56117), // Rule ID 14833 //
     /*  56067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56071 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56075 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /*  56079 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56083 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  56087 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /*  56091 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56096 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56098 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rn))  =>  (MSUBXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  56098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBXrrr),
     /*  56101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56103 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  56107 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  56109 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56115 */     GIR_RootConstrainSelectedInstOperands,
     /*  56116 */     // GIR_Coverage, 14833,
     /*  56116 */     GIR_EraseRootFromParent_Done,
     /*  56117 */   // Label 882: @56117
     /*  56117 */   GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(56230), // Rule ID 4063 //
     /*  56122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  56130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56134 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56139 */     // MIs[1] Operand 2
     /*  56139 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  56150 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56154 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  56158 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  56162 */     // MIs[2] Operand 1
     /*  56162 */     // No operand predicates
     /*  56162 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56164 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  56164 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  56167 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  56171 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56176 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  56181 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /*  56183 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56186 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56190 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56195 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56201 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56206 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56216 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56219 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  56222 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56228 */     GIR_RootConstrainSelectedInstOperands,
     /*  56229 */     // GIR_Coverage, 4063,
     /*  56229 */     GIR_EraseRootFromParent_Done,
     /*  56230 */   // Label 883: @56230
     /*  56230 */   GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(56305), // Rule ID 4061 //
     /*  56235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  56243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56247 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56252 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56256 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  56260 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_s64imm_32bit),
     /*  56264 */     // MIs[2] Operand 1
     /*  56264 */     // No operand predicates
     /*  56264 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56266 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_s64imm_32bit>>:$C)  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  56266 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56269 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  56273 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56278 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  56283 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  56294 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56297 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56303 */     GIR_RootConstrainSelectedInstOperands,
     /*  56304 */     // GIR_Coverage, 4061,
     /*  56304 */     GIR_EraseRootFromParent_Done,
     /*  56305 */   // Label 884: @56305
     /*  56305 */   GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(56380), // Rule ID 4062 //
     /*  56310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  56318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56322 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  56335 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /*  56339 */     // MIs[2] Operand 1
     /*  56339 */     // No operand predicates
     /*  56339 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56341 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$C)  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$C)), XZR:{ *:[i64] })
     /*  56341 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56344 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /*  56348 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56353 */     GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // C
     /*  56358 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  56360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  56363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56365 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  56369 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56372 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56378 */     GIR_RootConstrainSelectedInstOperands,
     /*  56379 */     // GIR_Coverage, 4062,
     /*  56379 */     GIR_EraseRootFromParent_Done,
     /*  56380 */   // Label 885: @56380
     /*  56380 */   GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(56518), // Rule ID 4053 //
     /*  56385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  56393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56397 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56402 */     // MIs[1] Operand 2
     /*  56402 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  56413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  56421 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  56425 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56430 */     // MIs[2] Operand 2
     /*  56430 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  56441 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56443 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, i32:{ *:[Other] }))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  56443 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  56446 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56450 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56455 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  56461 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56466 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56483 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56489 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56494 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56504 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56507 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  56510 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56516 */     GIR_RootConstrainSelectedInstOperands,
     /*  56517 */     // GIR_Coverage, 4053,
     /*  56517 */     GIR_EraseRootFromParent_Done,
     /*  56518 */   // Label 886: @56518
     /*  56518 */   GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(56618), // Rule ID 4054 //
     /*  56523 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56527 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  56531 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  56535 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56540 */     // MIs[1] Operand 2
     /*  56540 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /*  56551 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56555 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  56559 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  56563 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56568 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56570 */     // (mul:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56570 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56573 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56577 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56582 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56588 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56593 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56603 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  56610 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56616 */     GIR_RootConstrainSelectedInstOperands,
     /*  56617 */     // GIR_Coverage, 4054,
     /*  56617 */     GIR_EraseRootFromParent_Done,
     /*  56618 */   // Label 887: @56618
     /*  56618 */   GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(56718), // Rule ID 14834 //
     /*  56623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  56631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56635 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56640 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56644 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /*  56648 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  56652 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56657 */     // MIs[2] Operand 2
     /*  56657 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /*  56668 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56670 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i32:{ *:[Other] }))  =>  (SMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56670 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56673 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56677 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56682 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56688 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56693 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56703 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  56710 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56716 */     GIR_RootConstrainSelectedInstOperands,
     /*  56717 */     // GIR_Coverage, 14834,
     /*  56717 */     GIR_EraseRootFromParent_Done,
     /*  56718 */   // Label 888: @56718
     /*  56718 */   GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(56780), // Rule ID 4055 //
     /*  56723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  56731 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56735 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56740 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56744 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /*  56748 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  56752 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56757 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56759 */     // (mul:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (SMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMADDLrrr),
     /*  56762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  56768 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  56772 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56778 */     GIR_RootConstrainSelectedInstOperands,
     /*  56779 */     // GIR_Coverage, 4055,
     /*  56779 */     GIR_EraseRootFromParent_Done,
     /*  56780 */   // Label 889: @56780
     /*  56780 */   GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(56842), // Rule ID 4058 //
     /*  56785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  56793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  56806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  56810 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  56814 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  56821 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  56824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  56830 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  56834 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56840 */     GIR_RootConstrainSelectedInstOperands,
     /*  56841 */     // GIR_Coverage, 4058,
     /*  56841 */     GIR_EraseRootFromParent_Done,
     /*  56842 */   // Label 890: @56842
     /*  56842 */   GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(56919), // Rule ID 4082 //
     /*  56847 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  56852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  56856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  56860 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56864 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56869 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56871 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56871 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56874 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56878 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56883 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56889 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56894 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  56902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56904 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56907 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  56911 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56917 */     GIR_RootConstrainSelectedInstOperands,
     /*  56918 */     // GIR_Coverage, 4082,
     /*  56918 */     GIR_EraseRootFromParent_Done,
     /*  56919 */   // Label 891: @56919
     /*  56919 */   GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(56996), // Rule ID 14846 //
     /*  56924 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  56928 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /*  56932 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  56936 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56941 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  56946 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  56948 */     // (mul:{ *:[i64] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm), GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), ?:{ *:[i32] }:$Rm, XZR:{ *:[i64] })
     /*  56948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  56951 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  56955 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  56960 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  56966 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  56971 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  56976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  56979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  56981 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  56984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  56988 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  56994 */     GIR_RootConstrainSelectedInstOperands,
     /*  56995 */     // GIR_Coverage, 14846,
     /*  56995 */     GIR_EraseRootFromParent_Done,
     /*  56996 */   // Label 892: @56996
     /*  56996 */   GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(57086), // Rule ID 4081 //
     /*  57001 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  57006 */     GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /*  57011 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn, GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rm)  =>  (UMADDLrrr:{ *:[i64] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }), XZR:{ *:[i64] })
     /*  57011 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  57014 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  57018 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  57023 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /*  57029 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  57034 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  57039 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  57042 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  57046 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  57051 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  57057 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  57062 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  57067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMADDLrrr),
     /*  57070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57072 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  57075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /*  57078 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  57084 */     GIR_RootConstrainSelectedInstOperands,
     /*  57085 */     // GIR_Coverage, 4081,
     /*  57085 */     GIR_EraseRootFromParent_Done,
     /*  57086 */   // Label 893: @57086
     /*  57086 */   GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(57116), // Rule ID 4048 //
     /*  57091 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  57095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  57099 */     // (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (MADDXrrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, XZR:{ *:[i64] })
     /*  57099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDXrrr),
     /*  57102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57104 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  57108 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  57114 */     GIR_RootConstrainSelectedInstOperands,
     /*  57115 */     // GIR_Coverage, 4048,
     /*  57115 */     GIR_EraseRootFromParent_Done,
     /*  57116 */   // Label 894: @57116
     /*  57116 */   GIM_Reject,
     /*  57117 */ // Label 877: @57117
     /*  57117 */ GIM_Reject,
     /*  57118 */ // Label 866: @57118
     /*  57118 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(57455),
     /*  57123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  57126 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  57129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57133 */   GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(57219), // Rule ID 14510 //
     /*  57138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  57149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  57157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57161 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57165 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  57169 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57174 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  57178 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57182 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57186 */     // MIs[3] Operand 1
     /*  57186 */     // No operand predicates
     /*  57186 */     // MIs[1] Operand 2
     /*  57186 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  57197 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57201 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  57203 */     // (mul:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  57206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  57214 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  57217 */     GIR_RootConstrainSelectedInstOperands,
     /*  57218 */     // GIR_Coverage, 14510,
     /*  57218 */     GIR_EraseRootFromParent_Done,
     /*  57219 */   // Label 896: @57219
     /*  57219 */   GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(57305), // Rule ID 2065 //
     /*  57224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57227 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57231 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57235 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  57239 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57243 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  57247 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57251 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57255 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  57259 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57264 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  57268 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57272 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57276 */     // MIs[3] Operand 1
     /*  57276 */     // No operand predicates
     /*  57276 */     // MIs[1] Operand 2
     /*  57276 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  57287 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  57289 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  57292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57294 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  57300 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  57303 */     GIR_RootConstrainSelectedInstOperands,
     /*  57304 */     // GIR_Coverage, 2065,
     /*  57304 */     GIR_EraseRootFromParent_Done,
     /*  57305 */   // Label 897: @57305
     /*  57305 */   GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(57368), // Rule ID 14511 //
     /*  57310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57329 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57342 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57346 */     // MIs[2] Operand 1
     /*  57346 */     // No operand predicates
     /*  57346 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57350 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57352 */     // (mul:{ *:[v2i32] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  57355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57359 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57363 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57366 */     GIR_RootConstrainSelectedInstOperands,
     /*  57367 */     // GIR_Coverage, 14511,
     /*  57367 */     GIR_EraseRootFromParent_Done,
     /*  57368 */   // Label 898: @57368
     /*  57368 */   GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(57431), // Rule ID 2066 //
     /*  57373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57392 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57396 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57401 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57405 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57409 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57413 */     // MIs[2] Operand 1
     /*  57413 */     // No operand predicates
     /*  57413 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57415 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (MULv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32_indexed),
     /*  57418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57420 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57426 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57429 */     GIR_RootConstrainSelectedInstOperands,
     /*  57430 */     // GIR_Coverage, 2066,
     /*  57430 */     GIR_EraseRootFromParent_Done,
     /*  57431 */   // Label 899: @57431
     /*  57431 */   GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(57454), // Rule ID 1382 //
     /*  57436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57439 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57447 */     // (mul:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (MULv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  57447 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv2i32),
     /*  57452 */     GIR_RootConstrainSelectedInstOperands,
     /*  57453 */     // GIR_Coverage, 1382,
     /*  57453 */     GIR_Done,
     /*  57454 */   // Label 900: @57454
     /*  57454 */   GIM_Reject,
     /*  57455 */ // Label 895: @57455
     /*  57455 */ GIM_Reject,
     /*  57456 */ // Label 867: @57456
     /*  57456 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(57793),
     /*  57461 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  57464 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  57467 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57471 */   GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(57557), // Rule ID 14507 //
     /*  57476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  57487 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57491 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  57495 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  57499 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57503 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  57507 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  57512 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  57516 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57520 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  57524 */     // MIs[3] Operand 1
     /*  57524 */     // No operand predicates
     /*  57524 */     // MIs[1] Operand 2
     /*  57524 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  57535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57539 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  57541 */     // (mul:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  57544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57546 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  57552 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  57555 */     GIR_RootConstrainSelectedInstOperands,
     /*  57556 */     // GIR_Coverage, 14507,
     /*  57556 */     GIR_EraseRootFromParent_Done,
     /*  57557 */   // Label 902: @57557
     /*  57557 */   GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(57643), // Rule ID 2062 //
     /*  57562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57565 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /*  57577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  57585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  57589 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57593 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  57597 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  57602 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  57606 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57610 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  57614 */     // MIs[3] Operand 1
     /*  57614 */     // No operand predicates
     /*  57614 */     // MIs[1] Operand 2
     /*  57614 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /*  57625 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  57627 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  57630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  57638 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /*  57641 */     GIR_RootConstrainSelectedInstOperands,
     /*  57642 */     // GIR_Coverage, 2062,
     /*  57642 */     GIR_EraseRootFromParent_Done,
     /*  57643 */   // Label 903: @57643
     /*  57643 */   GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(57706), // Rule ID 14508 //
     /*  57648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  57659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57663 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57667 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  57672 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57676 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57680 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  57684 */     // MIs[2] Operand 1
     /*  57684 */     // No operand predicates
     /*  57684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57688 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57690 */     // (mul:{ *:[v4i16] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  57693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57697 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57701 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57704 */     GIR_RootConstrainSelectedInstOperands,
     /*  57705 */     // GIR_Coverage, 14508,
     /*  57705 */     GIR_EraseRootFromParent_Done,
     /*  57706 */   // Label 904: @57706
     /*  57706 */   GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(57769), // Rule ID 2063 //
     /*  57711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57714 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57722 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  57726 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  57730 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57734 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  57739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57747 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  57751 */     // MIs[2] Operand 1
     /*  57751 */     // No operand predicates
     /*  57751 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57753 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (MULv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16_indexed),
     /*  57756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57758 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57764 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57767 */     GIR_RootConstrainSelectedInstOperands,
     /*  57768 */     // GIR_Coverage, 2063,
     /*  57768 */     GIR_EraseRootFromParent_Done,
     /*  57769 */   // Label 905: @57769
     /*  57769 */   GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(57792), // Rule ID 1380 //
     /*  57774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57777 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57781 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57785 */     // (mul:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (MULv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  57785 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i16),
     /*  57790 */     GIR_RootConstrainSelectedInstOperands,
     /*  57791 */     // GIR_Coverage, 1380,
     /*  57791 */     GIR_Done,
     /*  57792 */   // Label 906: @57792
     /*  57792 */   GIM_Reject,
     /*  57793 */ // Label 901: @57793
     /*  57793 */ GIM_Reject,
     /*  57794 */ // Label 868: @57794
     /*  57794 */ GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(57959),
     /*  57799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57802 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  57805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57809 */   GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(57872), // Rule ID 14512 //
     /*  57814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  57821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57829 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57833 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57838 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57842 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57846 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57850 */     // MIs[2] Operand 1
     /*  57850 */     // No operand predicates
     /*  57850 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57856 */     // (mul:{ *:[v4i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4i32] }:$Rn)  =>  (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
     /*  57859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  57863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57867 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57870 */     GIR_RootConstrainSelectedInstOperands,
     /*  57871 */     // GIR_Coverage, 14512,
     /*  57871 */     GIR_EraseRootFromParent_Done,
     /*  57872 */   // Label 908: @57872
     /*  57872 */   GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(57935), // Rule ID 2067 //
     /*  57877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57880 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  57888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /*  57892 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  57896 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  57900 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57905 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  57909 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  57913 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /*  57917 */     // MIs[2] Operand 1
     /*  57917 */     // No operand predicates
     /*  57917 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  57919 */     // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (MULv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  57919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32_indexed),
     /*  57922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  57924 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  57926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  57930 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  57933 */     GIR_RootConstrainSelectedInstOperands,
     /*  57934 */     // GIR_Coverage, 2067,
     /*  57934 */     GIR_EraseRootFromParent_Done,
     /*  57935 */   // Label 909: @57935
     /*  57935 */   GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(57958), // Rule ID 1383 //
     /*  57940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57943 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57947 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  57951 */     // (mul:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (MULv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  57951 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv4i32),
     /*  57956 */     GIR_RootConstrainSelectedInstOperands,
     /*  57957 */     // GIR_Coverage, 1383,
     /*  57957 */     GIR_Done,
     /*  57958 */   // Label 910: @57958
     /*  57958 */   GIM_Reject,
     /*  57959 */ // Label 907: @57959
     /*  57959 */ GIM_Reject,
     /*  57960 */ // Label 869: @57960
     /*  57960 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(57993), // Rule ID 1378 //
     /*  57965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  57968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  57971 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  57974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57982 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  57986 */   // (mul:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (MULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  57986 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i8),
     /*  57991 */   GIR_RootConstrainSelectedInstOperands,
     /*  57992 */   // GIR_Coverage, 1378,
     /*  57992 */   GIR_Done,
     /*  57993 */ // Label 911: @57993
     /*  57993 */ GIM_Reject,
     /*  57994 */ // Label 870: @57994
     /*  57994 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(58159),
     /*  57999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  58002 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  58005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58009 */   GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(58072), // Rule ID 14509 //
     /*  58014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  58025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  58029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  58038 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58042 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58046 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  58050 */     // MIs[2] Operand 1
     /*  58050 */     // No operand predicates
     /*  58050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58054 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58056 */     // (mul:{ *:[v8i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8i16] }:$Rn)  =>  (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  58056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
     /*  58059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  58063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  58067 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  58070 */     GIR_RootConstrainSelectedInstOperands,
     /*  58071 */     // GIR_Coverage, 14509,
     /*  58071 */     GIR_EraseRootFromParent_Done,
     /*  58072 */   // Label 913: @58072
     /*  58072 */   GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(58135), // Rule ID 2064 //
     /*  58077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58080 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58084 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58088 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /*  58092 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  58096 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58100 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /*  58105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58109 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58113 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  58117 */     // MIs[2] Operand 1
     /*  58117 */     // No operand predicates
     /*  58117 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58119 */     // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (MULv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /*  58119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16_indexed),
     /*  58122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58124 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  58126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  58130 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  58133 */     GIR_RootConstrainSelectedInstOperands,
     /*  58134 */     // GIR_Coverage, 2064,
     /*  58134 */     GIR_EraseRootFromParent_Done,
     /*  58135 */   // Label 914: @58135
     /*  58135 */   GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(58158), // Rule ID 1381 //
     /*  58140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58151 */     // (mul:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (MULv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  58151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv8i16),
     /*  58156 */     GIR_RootConstrainSelectedInstOperands,
     /*  58157 */     // GIR_Coverage, 1381,
     /*  58157 */     GIR_Done,
     /*  58158 */   // Label 915: @58158
     /*  58158 */   GIM_Reject,
     /*  58159 */ // Label 912: @58159
     /*  58159 */ GIM_Reject,
     /*  58160 */ // Label 871: @58160
     /*  58160 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(58193), // Rule ID 1379 //
     /*  58165 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  58171 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  58174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58178 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58182 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58186 */   // (mul:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (MULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  58186 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::MULv16i8),
     /*  58191 */   GIR_RootConstrainSelectedInstOperands,
     /*  58192 */   // GIR_Coverage, 1379,
     /*  58192 */   GIR_Done,
     /*  58193 */ // Label 916: @58193
     /*  58193 */ GIM_Reject,
     /*  58194 */ // Label 872: @58194
     /*  58194 */ GIM_Reject,
     /*  58195 */ // Label 3: @58195
     /*  58195 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 919*/ GIMT_Encode4(58276),
     /*  58206 */ /*GILLT_s32*//*Label 917*/ GIMT_Encode4(58214),
     /*  58210 */ /*GILLT_s64*//*Label 918*/ GIMT_Encode4(58245),
     /*  58214 */ // Label 917: @58214
     /*  58214 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(58244), // Rule ID 105 //
     /*  58219 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  58222 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  58225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58229 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58233 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58237 */   // (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  58237 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
     /*  58242 */   GIR_RootConstrainSelectedInstOperands,
     /*  58243 */   // GIR_Coverage, 105,
     /*  58243 */   GIR_Done,
     /*  58244 */ // Label 920: @58244
     /*  58244 */ GIM_Reject,
     /*  58245 */ // Label 918: @58245
     /*  58245 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(58275), // Rule ID 106 //
     /*  58250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  58253 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  58256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58260 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58264 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58268 */   // (sdiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  58268 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
     /*  58273 */   GIR_RootConstrainSelectedInstOperands,
     /*  58274 */   // GIR_Coverage, 106,
     /*  58274 */   GIR_Done,
     /*  58275 */ // Label 921: @58275
     /*  58275 */ GIM_Reject,
     /*  58276 */ // Label 919: @58276
     /*  58276 */ GIM_Reject,
     /*  58277 */ // Label 4: @58277
     /*  58277 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 924*/ GIMT_Encode4(58358),
     /*  58288 */ /*GILLT_s32*//*Label 922*/ GIMT_Encode4(58296),
     /*  58292 */ /*GILLT_s64*//*Label 923*/ GIMT_Encode4(58327),
     /*  58296 */ // Label 922: @58296
     /*  58296 */ GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(58326), // Rule ID 103 //
     /*  58301 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  58304 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  58307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58311 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58315 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58319 */   // (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  58319 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
     /*  58324 */   GIR_RootConstrainSelectedInstOperands,
     /*  58325 */   // GIR_Coverage, 103,
     /*  58325 */   GIR_Done,
     /*  58326 */ // Label 925: @58326
     /*  58326 */ GIM_Reject,
     /*  58327 */ // Label 923: @58327
     /*  58327 */ GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(58357), // Rule ID 104 //
     /*  58332 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  58335 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  58338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58342 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58346 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  58350 */   // (udiv:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  58350 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
     /*  58355 */   GIR_RootConstrainSelectedInstOperands,
     /*  58356 */   // GIR_Coverage, 104,
     /*  58356 */   GIR_Done,
     /*  58357 */ // Label 926: @58357
     /*  58357 */ GIM_Reject,
     /*  58358 */ // Label 924: @58358
     /*  58358 */ GIM_Reject,
     /*  58359 */ // Label 5: @58359
     /*  58359 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 945*/ GIMT_Encode4(66568),
     /*  58370 */ /*GILLT_s32*//*Label 927*/ GIMT_Encode4(58458),
     /*  58374 */ /*GILLT_s64*//*Label 928*/ GIMT_Encode4(59144), GIMT_Encode4(0),
     /*  58382 */ /*GILLT_v2s32*//*Label 929*/ GIMT_Encode4(60855),
     /*  58386 */ /*GILLT_v2s64*//*Label 930*/ GIMT_Encode4(61015),
     /*  58390 */ /*GILLT_v4s16*//*Label 931*/ GIMT_Encode4(61175),
     /*  58394 */ /*GILLT_v4s32*//*Label 932*/ GIMT_Encode4(61335),
     /*  58398 */ /*GILLT_v8s8*//*Label 933*/ GIMT_Encode4(61495),
     /*  58402 */ /*GILLT_v8s16*//*Label 934*/ GIMT_Encode4(61655),
     /*  58406 */ /*GILLT_v16s8*//*Label 935*/ GIMT_Encode4(61815),
     /*  58410 */ /*GILLT_nxv1s1*//*Label 936*/ GIMT_Encode4(61975),
     /*  58414 */ /*GILLT_nxv2s1*//*Label 937*/ GIMT_Encode4(62516), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  58426 */ /*GILLT_nxv2s64*//*Label 938*/ GIMT_Encode4(63057),
     /*  58430 */ /*GILLT_nxv4s1*//*Label 939*/ GIMT_Encode4(63529), GIMT_Encode4(0),
     /*  58438 */ /*GILLT_nxv4s32*//*Label 940*/ GIMT_Encode4(64070),
     /*  58442 */ /*GILLT_nxv8s1*//*Label 941*/ GIMT_Encode4(64542),
     /*  58446 */ /*GILLT_nxv8s16*//*Label 942*/ GIMT_Encode4(65083),
     /*  58450 */ /*GILLT_nxv16s1*//*Label 943*/ GIMT_Encode4(65555),
     /*  58454 */ /*GILLT_nxv16s8*//*Label 944*/ GIMT_Encode4(66096),
     /*  58458 */ // Label 927: @58458
     /*  58458 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(59143),
     /*  58463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  58466 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  58469 */   GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(58524), // Rule ID 14287 //
     /*  58474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58482 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58486 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  58490 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  58494 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  58498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58502 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  58504 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  58511 */     // (and:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  58511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
     /*  58514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  58518 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  58522 */     GIR_RootConstrainSelectedInstOperands,
     /*  58523 */     // GIR_Coverage, 14287,
     /*  58523 */     GIR_EraseRootFromParent_Done,
     /*  58524 */   // Label 947: @58524
     /*  58524 */   GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(58579), // Rule ID 150 //
     /*  58529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58533 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  58549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  58553 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  58557 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  58559 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  58566 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (BICWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  58566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrs),
     /*  58569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58571 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  58573 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  58577 */     GIR_RootConstrainSelectedInstOperands,
     /*  58578 */     // GIR_Coverage, 150,
     /*  58578 */     GIR_EraseRootFromParent_Done,
     /*  58579 */   // Label 948: @58579
     /*  58579 */   GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(58648), // Rule ID 6261 //
     /*  58584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  58596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  58600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58604 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58617 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  58621 */     // MIs[2] Operand 1
     /*  58621 */     // No operand predicates
     /*  58621 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  58632 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58634 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), 255:{ *:[i32] })  =>  (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /*  58634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  58637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  58643 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  58646 */     GIR_RootConstrainSelectedInstOperands,
     /*  58647 */     // GIR_Coverage, 6261,
     /*  58647 */     GIR_EraseRootFromParent_Done,
     /*  58648 */   // Label 949: @58648
     /*  58648 */   GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(58717), // Rule ID 6262 //
     /*  58653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  58665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  58669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58678 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58682 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58686 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  58690 */     // MIs[2] Operand 1
     /*  58690 */     // No operand predicates
     /*  58690 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  58701 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58703 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 65535:{ *:[i32] })  =>  (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /*  58703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  58706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  58712 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /*  58715 */     GIR_RootConstrainSelectedInstOperands,
     /*  58716 */     // GIR_Coverage, 6262,
     /*  58716 */     GIR_EraseRootFromParent_Done,
     /*  58717 */   // Label 950: @58717
     /*  58717 */   GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(58811), // Rule ID 12019 //
     /*  58722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58729 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58733 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  58737 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  58741 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58745 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58749 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58753 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  58757 */     // MIs[2] Operand 1
     /*  58757 */     // No operand predicates
     /*  58757 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  58768 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58770 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index), 255:{ *:[i32] })  =>  (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /*  58770 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /*  58773 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  58777 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  58782 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /*  58788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58793 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  58798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  58801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58803 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  58806 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /*  58809 */     GIR_RootConstrainSelectedInstOperands,
     /*  58810 */     // GIR_Coverage, 12019,
     /*  58810 */     GIR_EraseRootFromParent_Done,
     /*  58811 */   // Label 951: @58811
     /*  58811 */   GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(58905), // Rule ID 12020 //
     /*  58816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  58819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  58831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  58835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  58839 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  58843 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  58847 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  58851 */     // MIs[2] Operand 1
     /*  58851 */     // No operand predicates
     /*  58851 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  58862 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  58864 */     // (and:{ *:[i32] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index), 65535:{ *:[i32] })  =>  (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /*  58864 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  58867 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  58871 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  58876 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /*  58882 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  58887 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  58892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  58895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58897 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  58900 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /*  58903 */     GIR_RootConstrainSelectedInstOperands,
     /*  58904 */     // GIR_Coverage, 12020,
     /*  58904 */     GIR_EraseRootFromParent_Done,
     /*  58905 */   // Label 952: @58905
     /*  58905 */   GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(58958), // Rule ID 14285 //
     /*  58910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  58918 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58922 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  58926 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  58930 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58935 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  58939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58943 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  58945 */     // (and:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  58945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
     /*  58948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  58950 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  58952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  58956 */     GIR_RootConstrainSelectedInstOperands,
     /*  58957 */     // GIR_Coverage, 14285,
     /*  58957 */     GIR_EraseRootFromParent_Done,
     /*  58958 */   // Label 953: @58958
     /*  58958 */   GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(59011), // Rule ID 148 //
     /*  58963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58967 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  58975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  58979 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  58983 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  58987 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  58992 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  58996 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  58998 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (BICWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  58998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICWrr),
     /*  59001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59003 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  59005 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  59009 */     GIR_RootConstrainSelectedInstOperands,
     /*  59010 */     // GIR_Coverage, 148,
     /*  59010 */     GIR_EraseRootFromParent_Done,
     /*  59011 */   // Label 954: @59011
     /*  59011 */   GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(59052), // Rule ID 130 //
     /*  59016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  59020 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  59032 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  59036 */     // MIs[1] Operand 1
     /*  59036 */     // No operand predicates
     /*  59036 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  59038 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (ANDWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  59038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
     /*  59041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  59045 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  59050 */     GIR_RootConstrainSelectedInstOperands,
     /*  59051 */     // GIR_Coverage, 130,
     /*  59051 */     GIR_EraseRootFromParent_Done,
     /*  59052 */   // Label 955: @59052
     /*  59052 */   GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(59085), // Rule ID 14283 //
     /*  59057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59065 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  59072 */     // (and:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  59072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
     /*  59075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  59079 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  59083 */     GIR_RootConstrainSelectedInstOperands,
     /*  59084 */     // GIR_Coverage, 14283,
     /*  59084 */     GIR_EraseRootFromParent_Done,
     /*  59085 */   // Label 956: @59085
     /*  59085 */   GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(59118), // Rule ID 146 //
     /*  59090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  59105 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ANDWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  59105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDWrs),
     /*  59108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59110 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  59112 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  59116 */     GIR_RootConstrainSelectedInstOperands,
     /*  59117 */     // GIR_Coverage, 146,
     /*  59117 */     GIR_EraseRootFromParent_Done,
     /*  59118 */   // Label 957: @59118
     /*  59118 */   GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(59142), // Rule ID 144 //
     /*  59123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59135 */     // (and:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ANDWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  59135 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDWrr),
     /*  59140 */     GIR_RootConstrainSelectedInstOperands,
     /*  59141 */     // GIR_Coverage, 144,
     /*  59141 */     GIR_Done,
     /*  59142 */   // Label 958: @59142
     /*  59142 */   GIM_Reject,
     /*  59143 */ // Label 946: @59143
     /*  59143 */ GIM_Reject,
     /*  59144 */ // Label 928: @59144
     /*  59144 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(60854),
     /*  59149 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  59152 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  59155 */   GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(59210), // Rule ID 14288 //
     /*  59160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  59164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  59176 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  59180 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  59184 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  59188 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  59190 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  59197 */     // (and:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  59197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
     /*  59200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59202 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  59204 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  59208 */     GIR_RootConstrainSelectedInstOperands,
     /*  59209 */     // GIR_Coverage, 14288,
     /*  59209 */     GIR_EraseRootFromParent_Done,
     /*  59210 */   // Label 960: @59210
     /*  59210 */   GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(59265), // Rule ID 151 //
     /*  59215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  59219 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  59223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  59227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  59231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  59235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  59239 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  59243 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  59245 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  59252 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (BICXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  59252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrs),
     /*  59255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  59257 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  59259 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  59263 */     GIR_RootConstrainSelectedInstOperands,
     /*  59264 */     // GIR_Coverage, 151,
     /*  59264 */     GIR_EraseRootFromParent_Done,
     /*  59265 */   // Label 961: @59265
     /*  59265 */   GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(59378), // Rule ID 6263 //
     /*  59270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59274 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59278 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  59282 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  59286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  59294 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  59298 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  59302 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  59307 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  59311 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  59315 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  59319 */     // MIs[3] Operand 1
     /*  59319 */     // No operand predicates
     /*  59319 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  59330 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  59332 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)), 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), sub_32:{ *:[i32] })
     /*  59332 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59335 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  59339 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59344 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  59348 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
     /*  59351 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59361 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59367 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59372 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59377 */     // GIR_Coverage, 6263,
     /*  59377 */     GIR_EraseRootFromParent_Done,
     /*  59378 */   // Label 962: @59378
     /*  59378 */   GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(59491), // Rule ID 6264 //
     /*  59383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  59395 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  59399 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59403 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  59407 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  59411 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  59415 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  59420 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  59424 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  59428 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  59432 */     // MIs[3] Operand 1
     /*  59432 */     // No operand predicates
     /*  59432 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  59443 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  59445 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), sub_32:{ *:[i32] })
     /*  59445 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59448 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  59452 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59457 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  59461 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // idx
     /*  59464 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59474 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59480 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59485 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59490 */     // GIR_Coverage, 6264,
     /*  59490 */     GIR_EraseRootFromParent_Done,
     /*  59491 */   // Label 963: @59491
     /*  59491 */   GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(59629), // Rule ID 12021 //
     /*  59496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  59499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59507 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  59511 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  59515 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59519 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  59523 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  59527 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  59531 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  59535 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  59539 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /*  59543 */     // MIs[3] Operand 1
     /*  59543 */     // No operand predicates
     /*  59543 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  59554 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  59556 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)), 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index), sub_32:{ *:[i32] })
     /*  59556 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /*  59559 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  59563 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59568 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /*  59574 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  59579 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  59584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /*  59591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59596 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  59599 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // index
     /*  59602 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59612 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59618 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59628 */     // GIR_Coverage, 12021,
     /*  59628 */     GIR_EraseRootFromParent_Done,
     /*  59629 */   // Label 964: @59629
     /*  59629 */   GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(59767), // Rule ID 12022 //
     /*  59634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  59637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /*  59649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  59653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  59657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /*  59661 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  59665 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  59669 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  59673 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  59677 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /*  59681 */     // MIs[3] Operand 1
     /*  59681 */     // No operand predicates
     /*  59681 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  59692 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  59694 */     // (and:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)), 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index), sub_32:{ *:[i32] })
     /*  59694 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  59697 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  59701 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59706 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /*  59712 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  59717 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  59722 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59725 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /*  59729 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59734 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  59737 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // index
     /*  59740 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59750 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59756 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59761 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59766 */     // GIR_Coverage, 12022,
     /*  59766 */     GIR_EraseRootFromParent_Done,
     /*  59767 */   // Label 965: @59767
     /*  59767 */   GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(59866), // Rule ID 7758 //
     /*  59772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  59784 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  59787 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  59792 */     // MIs[1] addr
     /*  59792 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  59796 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  59801 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
     /*  59805 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  59816 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  59818 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>, 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  59818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
     /*  59825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59830 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  59834 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  59839 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59846 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59849 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59852 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59855 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59860 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59865 */     // GIR_Coverage, 7758,
     /*  59865 */     GIR_EraseRootFromParent_Done,
     /*  59866 */   // Label 966: @59866
     /*  59866 */   GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(59965), // Rule ID 7759 //
     /*  59871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59875 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59879 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  59883 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  59886 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  59891 */     // MIs[1] addr
     /*  59891 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  59895 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  59900 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
     /*  59904 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  59915 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  59917 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>, 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  59917 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  59920 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
     /*  59924 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  59929 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  59933 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  59938 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  59940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  59943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  59945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  59948 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  59951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  59954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59959 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  59964 */     // GIR_Coverage, 7759,
     /*  59964 */     GIR_EraseRootFromParent_Done,
     /*  59965 */   // Label 967: @59965
     /*  59965 */   GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(60064), // Rule ID 7760 //
     /*  59970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  59974 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  59978 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  59982 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  59985 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /*  59990 */     // MIs[1] addr
     /*  59990 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  59994 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  59999 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
     /*  60003 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  60014 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60016 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  60016 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  60019 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
     /*  60023 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60028 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  60032 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  60037 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  60042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  60044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  60047 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  60053 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60058 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60063 */     // GIR_Coverage, 7760,
     /*  60063 */     GIR_EraseRootFromParent_Done,
     /*  60064 */   // Label 968: @60064
     /*  60064 */   GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(60163), // Rule ID 7765 //
     /*  60069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60077 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  60081 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  60084 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  60089 */     // MIs[1] addr
     /*  60089 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  60093 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  60098 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
     /*  60102 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  60113 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60115 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>, 255:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  60115 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  60118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
     /*  60122 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60127 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  60131 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  60136 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  60141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  60143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  60146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  60152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60162 */     // GIR_Coverage, 7765,
     /*  60162 */     GIR_EraseRootFromParent_Done,
     /*  60163 */   // Label 969: @60163
     /*  60163 */   GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(60262), // Rule ID 7766 //
     /*  60168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60172 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60176 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  60180 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  60183 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  60188 */     // MIs[1] addr
     /*  60188 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  60192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  60197 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
     /*  60201 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
     /*  60212 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60214 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>, 65535:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  60214 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  60217 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
     /*  60221 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60226 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  60230 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  60235 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  60240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  60242 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  60245 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  60251 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60256 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60261 */     // GIR_Coverage, 7766,
     /*  60261 */     GIR_EraseRootFromParent_Done,
     /*  60262 */   // Label 970: @60262
     /*  60262 */   GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(60361), // Rule ID 7767 //
     /*  60267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS),
     /*  60279 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /*  60282 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /*  60287 */     // MIs[1] addr
     /*  60287 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/2, /*SizeInBits*/64,
     /*  60291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  60296 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
     /*  60300 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  60311 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60313 */     // (and:{ *:[i64] } (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /*  60313 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  60316 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
     /*  60320 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60325 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // addr
     /*  60329 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /*  60334 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  60339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  60341 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  60344 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  60350 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60355 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60360 */     // GIR_Coverage, 7767,
     /*  60360 */     GIR_EraseRootFromParent_Done,
     /*  60361 */   // Label 971: @60361
     /*  60361 */   GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(60414), // Rule ID 14286 //
     /*  60366 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  60382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  60386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60391 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  60395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60399 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60401 */     // (and:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  60401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
     /*  60404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  60408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  60412 */     GIR_RootConstrainSelectedInstOperands,
     /*  60413 */     // GIR_Coverage, 14286,
     /*  60413 */     GIR_EraseRootFromParent_Done,
     /*  60414 */   // Label 972: @60414
     /*  60414 */   GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(60467), // Rule ID 149 //
     /*  60419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60423 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60427 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60431 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60435 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  60439 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  60443 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60448 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  60452 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60454 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }))  =>  (BICXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  60454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICXrr),
     /*  60457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60459 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  60461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  60465 */     GIR_RootConstrainSelectedInstOperands,
     /*  60466 */     // GIR_Coverage, 149,
     /*  60466 */     GIR_EraseRootFromParent_Done,
     /*  60467 */   // Label 973: @60467
     /*  60467 */   GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(60567), // Rule ID 4102 //
     /*  60472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60476 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60480 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294967295),
     /*  60491 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 4294967295:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (ORRWrr:{ *:[i32] } WZR:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rn, sub_32:{ *:[i32] })), sub_32:{ *:[i32] })
     /*  60491 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /*  60494 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  60498 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60503 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // Rn
     /*  60509 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60514 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60519 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /*  60522 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
     /*  60526 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  60531 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  60537 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  60540 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  60542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /*  60545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  60547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /*  60550 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  60553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /*  60556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /*  60561 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  60566 */     // GIR_Coverage, 4102,
     /*  60566 */     GIR_EraseRootFromParent_Done,
     /*  60567 */   // Label 974: @60567
     /*  60567 */   GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(60608), // Rule ID 131 //
     /*  60572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  60576 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60580 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60584 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  60588 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  60592 */     // MIs[1] Operand 1
     /*  60592 */     // No operand predicates
     /*  60592 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  60594 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (ANDXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  60594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXri),
     /*  60597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60599 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  60601 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  60606 */     GIR_RootConstrainSelectedInstOperands,
     /*  60607 */     // GIR_Coverage, 131,
     /*  60607 */     GIR_EraseRootFromParent_Done,
     /*  60608 */   // Label 975: @60608
     /*  60608 */   GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(60641), // Rule ID 14284 //
     /*  60613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60617 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60621 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  60628 */     // (and:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  60628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
     /*  60631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60633 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  60635 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  60639 */     GIR_RootConstrainSelectedInstOperands,
     /*  60640 */     // GIR_Coverage, 14284,
     /*  60640 */     GIR_EraseRootFromParent_Done,
     /*  60641 */   // Label 976: @60641
     /*  60641 */   GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(60674), // Rule ID 147 //
     /*  60646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60650 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60654 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  60661 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ANDXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  60661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDXrs),
     /*  60664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60666 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  60668 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  60672 */     GIR_RootConstrainSelectedInstOperands,
     /*  60673 */     // GIR_Coverage, 147,
     /*  60673 */     GIR_EraseRootFromParent_Done,
     /*  60674 */   // Label 977: @60674
     /*  60674 */   GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(60738), // Rule ID 14904 //
     /*  60679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60686 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60690 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60694 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  60698 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  60702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60707 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60711 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  60717 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  60719 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60723 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60725 */     // (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS)  =>  (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  60725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  60728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60730 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  60732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  60736 */     GIR_RootConstrainSelectedInstOperands,
     /*  60737 */     // GIR_Coverage, 14904,
     /*  60737 */     GIR_EraseRootFromParent_Done,
     /*  60738 */   // Label 978: @60738
     /*  60738 */   GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(60802), // Rule ID 5094 //
     /*  60743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60750 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60762 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  60766 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  60770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60779 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  60785 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  60787 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60789 */     // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }))  =>  (BICv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  60789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  60792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60794 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  60796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  60800 */     GIR_RootConstrainSelectedInstOperands,
     /*  60801 */     // GIR_Coverage, 5094,
     /*  60801 */     GIR_EraseRootFromParent_Done,
     /*  60802 */   // Label 979: @60802
     /*  60802 */   GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(60826), // Rule ID 145 //
     /*  60807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60811 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  60819 */     // (and:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ANDXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  60819 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDXrr),
     /*  60824 */     GIR_RootConstrainSelectedInstOperands,
     /*  60825 */     // GIR_Coverage, 145,
     /*  60825 */     GIR_Done,
     /*  60826 */   // Label 980: @60826
     /*  60826 */   GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(60853), // Rule ID 2514 //
     /*  60831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60838 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60842 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60846 */     // (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (ANDv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  60846 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  60851 */     GIR_RootConstrainSelectedInstOperands,
     /*  60852 */     // GIR_Coverage, 2514,
     /*  60852 */     GIR_Done,
     /*  60853 */   // Label 981: @60853
     /*  60853 */   GIM_Reject,
     /*  60854 */ // Label 959: @60854
     /*  60854 */ GIM_Reject,
     /*  60855 */ // Label 929: @60855
     /*  60855 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(61014),
     /*  60860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  60863 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  60866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60870 */   GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(60930), // Rule ID 14903 //
     /*  60875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60878 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  60882 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60886 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  60890 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  60894 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60899 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60903 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  60909 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  60911 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60915 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60917 */     // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS)  =>  (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  60917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  60920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60922 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  60924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  60928 */     GIR_RootConstrainSelectedInstOperands,
     /*  60929 */     // GIR_Coverage, 14903,
     /*  60929 */     GIR_EraseRootFromParent_Done,
     /*  60930 */   // Label 983: @60930
     /*  60930 */   GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(60990), // Rule ID 5093 //
     /*  60935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60938 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60942 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  60946 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  60950 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  60954 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  60958 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  60963 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  60967 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  60973 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  60975 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  60977 */     // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }))  =>  (BICv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  60977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  60980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  60982 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  60984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  60988 */     GIR_RootConstrainSelectedInstOperands,
     /*  60989 */     // GIR_Coverage, 5093,
     /*  60989 */     GIR_EraseRootFromParent_Done,
     /*  60990 */   // Label 984: @60990
     /*  60990 */   GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(61013), // Rule ID 2513 //
     /*  60995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  60998 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61006 */     // (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (ANDv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  61006 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  61011 */     GIR_RootConstrainSelectedInstOperands,
     /*  61012 */     // GIR_Coverage, 2513,
     /*  61012 */     GIR_Done,
     /*  61013 */   // Label 985: @61013
     /*  61013 */   GIM_Reject,
     /*  61014 */ // Label 982: @61014
     /*  61014 */ GIM_Reject,
     /*  61015 */ // Label 930: @61015
     /*  61015 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(61174),
     /*  61020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  61023 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  61026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61030 */   GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(61090), // Rule ID 14907 //
     /*  61035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61042 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61046 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  61050 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  61054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61059 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61063 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61069 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61075 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61077 */     // (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS)  =>  (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  61077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61082 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  61084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61088 */     GIR_RootConstrainSelectedInstOperands,
     /*  61089 */     // GIR_Coverage, 14907,
     /*  61089 */     GIR_EraseRootFromParent_Done,
     /*  61090 */   // Label 987: @61090
     /*  61090 */   GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(61150), // Rule ID 5097 //
     /*  61095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61098 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61102 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61110 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  61114 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  61118 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61123 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61127 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61133 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61135 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61137 */     // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }))  =>  (BICv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  61137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61142 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  61144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61148 */     GIR_RootConstrainSelectedInstOperands,
     /*  61149 */     // GIR_Coverage, 5097,
     /*  61149 */     GIR_EraseRootFromParent_Done,
     /*  61150 */   // Label 988: @61150
     /*  61150 */   GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(61173), // Rule ID 2517 //
     /*  61155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61158 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61166 */     // (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (ANDv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  61166 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  61171 */     GIR_RootConstrainSelectedInstOperands,
     /*  61172 */     // GIR_Coverage, 2517,
     /*  61172 */     GIR_Done,
     /*  61173 */   // Label 989: @61173
     /*  61173 */   GIM_Reject,
     /*  61174 */ // Label 986: @61174
     /*  61174 */ GIM_Reject,
     /*  61175 */ // Label 931: @61175
     /*  61175 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(61334),
     /*  61180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  61183 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  61186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61190 */   GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(61250), // Rule ID 14902 //
     /*  61195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  61210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  61214 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61223 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61229 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61235 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61237 */     // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS)  =>  (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  61237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  61240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61242 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  61244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61248 */     GIR_RootConstrainSelectedInstOperands,
     /*  61249 */     // GIR_Coverage, 14902,
     /*  61249 */     GIR_EraseRootFromParent_Done,
     /*  61250 */   // Label 991: @61250
     /*  61250 */   GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(61310), // Rule ID 5092 //
     /*  61255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  61274 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  61278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61283 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61287 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61293 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61295 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61297 */     // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }))  =>  (BICv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  61297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  61300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61302 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  61304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61308 */     GIR_RootConstrainSelectedInstOperands,
     /*  61309 */     // GIR_Coverage, 5092,
     /*  61309 */     GIR_EraseRootFromParent_Done,
     /*  61310 */   // Label 992: @61310
     /*  61310 */   GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(61333), // Rule ID 2512 //
     /*  61315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61318 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61322 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61326 */     // (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (ANDv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  61326 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  61331 */     GIR_RootConstrainSelectedInstOperands,
     /*  61332 */     // GIR_Coverage, 2512,
     /*  61332 */     GIR_Done,
     /*  61333 */   // Label 993: @61333
     /*  61333 */   GIM_Reject,
     /*  61334 */ // Label 990: @61334
     /*  61334 */ GIM_Reject,
     /*  61335 */ // Label 932: @61335
     /*  61335 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(61494),
     /*  61340 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  61343 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  61346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61350 */   GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(61410), // Rule ID 14906 //
     /*  61355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61358 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61362 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61366 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  61370 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  61374 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61379 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61383 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61389 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61391 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61395 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61397 */     // (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS)  =>  (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  61397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61402 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  61404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61408 */     GIR_RootConstrainSelectedInstOperands,
     /*  61409 */     // GIR_Coverage, 14906,
     /*  61409 */     GIR_EraseRootFromParent_Done,
     /*  61410 */   // Label 995: @61410
     /*  61410 */   GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(61470), // Rule ID 5096 //
     /*  61415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  61434 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  61438 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61443 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61447 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61453 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61455 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61457 */     // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }))  =>  (BICv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  61457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61462 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  61464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61468 */     GIR_RootConstrainSelectedInstOperands,
     /*  61469 */     // GIR_Coverage, 5096,
     /*  61469 */     GIR_EraseRootFromParent_Done,
     /*  61470 */   // Label 996: @61470
     /*  61470 */   GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(61493), // Rule ID 2516 //
     /*  61475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61486 */     // (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (ANDv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  61486 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  61491 */     GIR_RootConstrainSelectedInstOperands,
     /*  61492 */     // GIR_Coverage, 2516,
     /*  61492 */     GIR_Done,
     /*  61493 */   // Label 997: @61493
     /*  61493 */   GIM_Reject,
     /*  61494 */ // Label 994: @61494
     /*  61494 */ GIM_Reject,
     /*  61495 */ // Label 933: @61495
     /*  61495 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(61654),
     /*  61500 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  61503 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  61506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61510 */   GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(61570), // Rule ID 14413 //
     /*  61515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61518 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61522 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61526 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  61530 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  61534 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61539 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61543 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61549 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61555 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61557 */     // (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn)  =>  (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  61557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  61560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61562 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  61564 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  61568 */     GIR_RootConstrainSelectedInstOperands,
     /*  61569 */     // GIR_Coverage, 14413,
     /*  61569 */     GIR_EraseRootFromParent_Done,
     /*  61570 */   // Label 999: @61570
     /*  61570 */   GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(61630), // Rule ID 1603 //
     /*  61575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61578 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61582 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61586 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61590 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  61594 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  61598 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61603 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61607 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61613 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61615 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61617 */     // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }))  =>  (BICv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  61617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i8),
     /*  61620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61622 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  61624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  61628 */     GIR_RootConstrainSelectedInstOperands,
     /*  61629 */     // GIR_Coverage, 1603,
     /*  61629 */     GIR_EraseRootFromParent_Done,
     /*  61630 */   // Label 1000: @61630
     /*  61630 */   GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(61653), // Rule ID 1601 //
     /*  61635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61638 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61642 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  61646 */     // (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ANDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  61646 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv8i8),
     /*  61651 */     GIR_RootConstrainSelectedInstOperands,
     /*  61652 */     // GIR_Coverage, 1601,
     /*  61652 */     GIR_Done,
     /*  61653 */   // Label 1001: @61653
     /*  61653 */   GIM_Reject,
     /*  61654 */ // Label 998: @61654
     /*  61654 */ GIM_Reject,
     /*  61655 */ // Label 934: @61655
     /*  61655 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(61814),
     /*  61660 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  61663 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  61666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61670 */   GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(61730), // Rule ID 14905 //
     /*  61675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61686 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  61690 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  61694 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61703 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61709 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61711 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61715 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61717 */     // (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS)  =>  (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  61717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61722 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  61724 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61728 */     GIR_RootConstrainSelectedInstOperands,
     /*  61729 */     // GIR_Coverage, 14905,
     /*  61729 */     GIR_EraseRootFromParent_Done,
     /*  61730 */   // Label 1003: @61730
     /*  61730 */   GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(61790), // Rule ID 5095 //
     /*  61735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61738 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61746 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61750 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  61754 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  61758 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61763 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61767 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61773 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61775 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61777 */     // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }))  =>  (BICv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  61777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61782 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  61784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  61788 */     GIR_RootConstrainSelectedInstOperands,
     /*  61789 */     // GIR_Coverage, 5095,
     /*  61789 */     GIR_EraseRootFromParent_Done,
     /*  61790 */   // Label 1004: @61790
     /*  61790 */   GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(61813), // Rule ID 2515 //
     /*  61795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61798 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61802 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61806 */     // (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (ANDv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  61806 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  61811 */     GIR_RootConstrainSelectedInstOperands,
     /*  61812 */     // GIR_Coverage, 2515,
     /*  61812 */     GIR_Done,
     /*  61813 */   // Label 1005: @61813
     /*  61813 */   GIM_Reject,
     /*  61814 */ // Label 1002: @61814
     /*  61814 */ GIM_Reject,
     /*  61815 */ // Label 935: @61815
     /*  61815 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(61974),
     /*  61820 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  61823 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  61826 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61830 */   GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(61890), // Rule ID 14414 //
     /*  61835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  61842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61846 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  61850 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  61854 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61859 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61863 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61869 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61875 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61877 */     // (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn)  =>  (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  61877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61882 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  61884 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  61888 */     GIR_RootConstrainSelectedInstOperands,
     /*  61889 */     // GIR_Coverage, 14414,
     /*  61889 */     GIR_EraseRootFromParent_Done,
     /*  61890 */   // Label 1007: @61890
     /*  61890 */   GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(61950), // Rule ID 1604 //
     /*  61895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  61906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  61910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  61914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  61918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  61927 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  61933 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  61935 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  61937 */     // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }))  =>  (BICv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  61937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv16i8),
     /*  61940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  61942 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  61944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  61948 */     GIR_RootConstrainSelectedInstOperands,
     /*  61949 */     // GIR_Coverage, 1604,
     /*  61949 */     GIR_EraseRootFromParent_Done,
     /*  61950 */   // Label 1008: @61950
     /*  61950 */   GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(61973), // Rule ID 1602 //
     /*  61955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  61958 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61962 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  61966 */     // (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ANDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  61966 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ANDv16i8),
     /*  61971 */     GIR_RootConstrainSelectedInstOperands,
     /*  61972 */     // GIR_Coverage, 1602,
     /*  61972 */     GIR_Done,
     /*  61973 */   // Label 1009: @61973
     /*  61973 */   GIM_Reject,
     /*  61974 */ // Label 1006: @61974
     /*  61974 */ GIM_Reject,
     /*  61975 */ // Label 936: @61975
     /*  61975 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(62515),
     /*  61980 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  61983 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  61986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  61990 */   GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(62047), // Rule ID 16150 //
     /*  61995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  61998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62010 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62014 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62018 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62022 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62026 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62030 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62032 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] }), nxv1i1:{ *:[nxv1i1] }:$Op2), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62041 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62045 */     GIR_RootConstrainSelectedInstOperands,
     /*  62046 */     // GIR_Coverage, 16150,
     /*  62046 */     GIR_EraseRootFromParent_Done,
     /*  62047 */   // Label 1011: @62047
     /*  62047 */   GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(62104), // Rule ID 16153 //
     /*  62052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62055 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62059 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62063 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62067 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62071 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62075 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62079 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62083 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62087 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62089 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] }), nxv1i1:{ *:[nxv1i1] }:$Op2), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62102 */     GIR_RootConstrainSelectedInstOperands,
     /*  62103 */     // GIR_Coverage, 16153,
     /*  62103 */     GIR_EraseRootFromParent_Done,
     /*  62104 */   // Label 1012: @62104
     /*  62104 */   GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(62161), // Rule ID 16149 //
     /*  62109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62112 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62116 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62120 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62124 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62128 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62132 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62136 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62140 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62144 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62146 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] })), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62151 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62159 */     GIR_RootConstrainSelectedInstOperands,
     /*  62160 */     // GIR_Coverage, 16149,
     /*  62160 */     GIR_EraseRootFromParent_Done,
     /*  62161 */   // Label 1013: @62161
     /*  62161 */   GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(62218), // Rule ID 16152 //
     /*  62166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62177 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62181 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62185 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62189 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62193 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62197 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62201 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62203 */     // (and:{ *:[nxv1i1] } (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] })), nxv1i1:{ *:[nxv1i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62210 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62212 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62216 */     GIR_RootConstrainSelectedInstOperands,
     /*  62217 */     // GIR_Coverage, 16152,
     /*  62217 */     GIR_EraseRootFromParent_Done,
     /*  62218 */   // Label 1014: @62218
     /*  62218 */   GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(62275), // Rule ID 16148 //
     /*  62223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62226 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62230 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62234 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62238 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62242 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62246 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62250 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62254 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62258 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62260 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] }), nxv1i1:{ *:[nxv1i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62265 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62267 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62269 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62273 */     GIR_RootConstrainSelectedInstOperands,
     /*  62274 */     // GIR_Coverage, 16148,
     /*  62274 */     GIR_EraseRootFromParent_Done,
     /*  62275 */   // Label 1015: @62275
     /*  62275 */   GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(62332), // Rule ID 16151 //
     /*  62280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62291 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62295 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62299 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62303 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62307 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62311 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62315 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62317 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] }), nxv1i1:{ *:[nxv1i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62322 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62324 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62326 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62330 */     GIR_RootConstrainSelectedInstOperands,
     /*  62331 */     // GIR_Coverage, 16151,
     /*  62331 */     GIR_EraseRootFromParent_Done,
     /*  62332 */   // Label 1016: @62332
     /*  62332 */   GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(62389), // Rule ID 9163 //
     /*  62337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62348 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62352 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62356 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62360 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62364 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62368 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62372 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62374 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62379 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62381 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62387 */     GIR_RootConstrainSelectedInstOperands,
     /*  62388 */     // GIR_Coverage, 9163,
     /*  62388 */     GIR_EraseRootFromParent_Done,
     /*  62389 */   // Label 1017: @62389
     /*  62389 */   GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(62446), // Rule ID 9164 //
     /*  62394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  62409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  62413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62421 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62425 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62429 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62431 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op2, (splat_vector:{ *:[nxv1i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62436 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62438 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62440 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62444 */     GIR_RootConstrainSelectedInstOperands,
     /*  62445 */     // GIR_Coverage, 9164,
     /*  62445 */     GIR_EraseRootFromParent_Done,
     /*  62446 */   // Label 1018: @62446
     /*  62446 */   GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(62493), // Rule ID 11439 //
     /*  62451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62454 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  62458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  62462 */     // (and:{ *:[nxv1i1] } PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv1i1] }:$Ps1, PPR:{ *:[nxv1i1] }:$Ps2)
     /*  62462 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  62465 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  62469 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  62474 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  62477 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  62479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  62482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62484 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  62487 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  62489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  62491 */     GIR_RootConstrainSelectedInstOperands,
     /*  62492 */     // GIR_Coverage, 11439,
     /*  62492 */     GIR_EraseRootFromParent_Done,
     /*  62493 */   // Label 1019: @62493
     /*  62493 */   GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(62514), // Rule ID 2792 //
     /*  62498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62501 */     // (and:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  62501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  62504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62506 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62508 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  62512 */     GIR_RootConstrainSelectedInstOperands,
     /*  62513 */     // GIR_Coverage, 2792,
     /*  62513 */     GIR_EraseRootFromParent_Done,
     /*  62514 */   // Label 1020: @62514
     /*  62514 */   GIM_Reject,
     /*  62515 */ // Label 1010: @62515
     /*  62515 */ GIM_Reject,
     /*  62516 */ // Label 937: @62516
     /*  62516 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(63056),
     /*  62521 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62524 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  62531 */   GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(62588), // Rule ID 16141 //
     /*  62536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62551 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62555 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62559 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62563 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62567 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62571 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62573 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] }), nxv2i1:{ *:[nxv2i1] }:$Op2), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62580 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62582 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62586 */     GIR_RootConstrainSelectedInstOperands,
     /*  62587 */     // GIR_Coverage, 16141,
     /*  62587 */     GIR_EraseRootFromParent_Done,
     /*  62588 */   // Label 1022: @62588
     /*  62588 */   GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(62645), // Rule ID 16144 //
     /*  62593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62600 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62604 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62608 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62612 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62616 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62620 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62624 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62628 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62630 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] }), nxv2i1:{ *:[nxv2i1] }:$Op2), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62643 */     GIR_RootConstrainSelectedInstOperands,
     /*  62644 */     // GIR_Coverage, 16144,
     /*  62644 */     GIR_EraseRootFromParent_Done,
     /*  62645 */   // Label 1023: @62645
     /*  62645 */   GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(62702), // Rule ID 16140 //
     /*  62650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62653 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62657 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62661 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62665 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62669 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62673 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62677 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62681 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62685 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62687 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] })), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62700 */     GIR_RootConstrainSelectedInstOperands,
     /*  62701 */     // GIR_Coverage, 16140,
     /*  62701 */     GIR_EraseRootFromParent_Done,
     /*  62702 */   // Label 1024: @62702
     /*  62702 */   GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(62759), // Rule ID 16143 //
     /*  62707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  62714 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62718 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62722 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62726 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62730 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62734 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62738 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62742 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62744 */     // (and:{ *:[nxv2i1] } (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] })), nxv2i1:{ *:[nxv2i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  62753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62757 */     GIR_RootConstrainSelectedInstOperands,
     /*  62758 */     // GIR_Coverage, 16143,
     /*  62758 */     GIR_EraseRootFromParent_Done,
     /*  62759 */   // Label 1025: @62759
     /*  62759 */   GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(62816), // Rule ID 16139 //
     /*  62764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62767 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62771 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62775 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62779 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62783 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62787 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62791 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62795 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62799 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62801 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] }), nxv2i1:{ *:[nxv2i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62806 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62808 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62810 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62814 */     GIR_RootConstrainSelectedInstOperands,
     /*  62815 */     // GIR_Coverage, 16139,
     /*  62815 */     GIR_EraseRootFromParent_Done,
     /*  62816 */   // Label 1026: @62816
     /*  62816 */   GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(62873), // Rule ID 16142 //
     /*  62821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62836 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  62844 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62848 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62852 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62856 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62858 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] }), nxv2i1:{ *:[nxv2i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62863 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62865 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  62871 */     GIR_RootConstrainSelectedInstOperands,
     /*  62872 */     // GIR_Coverage, 16142,
     /*  62872 */     GIR_EraseRootFromParent_Done,
     /*  62873 */   // Label 1027: @62873
     /*  62873 */   GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(62930), // Rule ID 9159 //
     /*  62878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62881 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62885 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62889 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62893 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62897 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62901 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62905 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  62909 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62913 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62915 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62920 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62922 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62928 */     GIR_RootConstrainSelectedInstOperands,
     /*  62929 */     // GIR_Coverage, 9159,
     /*  62929 */     GIR_EraseRootFromParent_Done,
     /*  62930 */   // Label 1028: @62930
     /*  62930 */   GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(62987), // Rule ID 9160 //
     /*  62935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  62942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  62946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  62950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  62954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  62958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  62962 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  62966 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  62970 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  62972 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op2, (splat_vector:{ *:[nxv2i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  62972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  62975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  62977 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62979 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  62981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  62985 */     GIR_RootConstrainSelectedInstOperands,
     /*  62986 */     // GIR_Coverage, 9160,
     /*  62986 */     GIR_EraseRootFromParent_Done,
     /*  62987 */   // Label 1029: @62987
     /*  62987 */   GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(63034), // Rule ID 11438 //
     /*  62992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  62995 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  62999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  63003 */     // (and:{ *:[nxv2i1] } PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv2i1] }:$Ps1, PPR:{ *:[nxv2i1] }:$Ps2)
     /*  63003 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  63006 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  63010 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  63015 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  63018 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  63020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  63023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63025 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  63028 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  63030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  63032 */     GIR_RootConstrainSelectedInstOperands,
     /*  63033 */     // GIR_Coverage, 11438,
     /*  63033 */     GIR_EraseRootFromParent_Done,
     /*  63034 */   // Label 1030: @63034
     /*  63034 */   GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(63055), // Rule ID 2791 //
     /*  63039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63042 */     // (and:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  63042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  63045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63047 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63049 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  63053 */     GIR_RootConstrainSelectedInstOperands,
     /*  63054 */     // GIR_Coverage, 2791,
     /*  63054 */     GIR_EraseRootFromParent_Done,
     /*  63055 */   // Label 1031: @63055
     /*  63055 */   GIM_Reject,
     /*  63056 */ // Label 1021: @63056
     /*  63056 */ GIM_Reject,
     /*  63057 */ // Label 938: @63057
     /*  63057 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(63528),
     /*  63062 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63065 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  63072 */   GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(63127), // Rule ID 16076 //
     /*  63077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63088 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63092 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63096 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63100 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63104 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63108 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63112 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63114 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63121 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63125 */     GIR_RootConstrainSelectedInstOperands,
     /*  63126 */     // GIR_Coverage, 16076,
     /*  63126 */     GIR_EraseRootFromParent_Done,
     /*  63127 */   // Label 1033: @63127
     /*  63127 */   GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(63182), // Rule ID 16079 //
     /*  63132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63135 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63139 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63143 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63147 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63151 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63155 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63159 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63163 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63167 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63169 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63180 */     GIR_RootConstrainSelectedInstOperands,
     /*  63181 */     // GIR_Coverage, 16079,
     /*  63181 */     GIR_EraseRootFromParent_Done,
     /*  63182 */   // Label 1034: @63182
     /*  63182 */   GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(63237), // Rule ID 16075 //
     /*  63187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63198 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63202 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63206 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63210 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63214 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63218 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63222 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63224 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63235 */     GIR_RootConstrainSelectedInstOperands,
     /*  63236 */     // GIR_Coverage, 16075,
     /*  63236 */     GIR_EraseRootFromParent_Done,
     /*  63237 */   // Label 1035: @63237
     /*  63237 */   GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(63292), // Rule ID 16078 //
     /*  63242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63245 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63249 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63253 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63257 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63261 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63265 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63269 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63273 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63277 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63279 */     // (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63290 */     GIR_RootConstrainSelectedInstOperands,
     /*  63291 */     // GIR_Coverage, 16078,
     /*  63291 */     GIR_EraseRootFromParent_Done,
     /*  63292 */   // Label 1036: @63292
     /*  63292 */   GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(63347), // Rule ID 16074 //
     /*  63297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63300 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63304 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63308 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63312 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63316 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63320 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63324 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63328 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63334 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63339 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63341 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63345 */     GIR_RootConstrainSelectedInstOperands,
     /*  63346 */     // GIR_Coverage, 16074,
     /*  63346 */     GIR_EraseRootFromParent_Done,
     /*  63347 */   // Label 1037: @63347
     /*  63347 */   GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(63402), // Rule ID 16077 //
     /*  63352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63363 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63367 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63371 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63375 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63379 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63383 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63387 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63389 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63394 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63400 */     GIR_RootConstrainSelectedInstOperands,
     /*  63401 */     // GIR_Coverage, 16077,
     /*  63401 */     GIR_EraseRootFromParent_Done,
     /*  63402 */   // Label 1038: @63402
     /*  63402 */   GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(63457), // Rule ID 8146 //
     /*  63407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63422 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63426 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63430 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63434 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63438 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63442 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63444 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63449 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63455 */     GIR_RootConstrainSelectedInstOperands,
     /*  63456 */     // GIR_Coverage, 8146,
     /*  63456 */     GIR_EraseRootFromParent_Done,
     /*  63457 */   // Label 1039: @63457
     /*  63457 */   GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(63512), // Rule ID 8147 //
     /*  63462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63465 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63469 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63473 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  63477 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  63481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63489 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63493 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63497 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63499 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (splat_vector:{ *:[nxv2i64] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  63502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  63504 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63506 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63510 */     GIR_RootConstrainSelectedInstOperands,
     /*  63511 */     // GIR_Coverage, 8147,
     /*  63511 */     GIR_EraseRootFromParent_Done,
     /*  63512 */   // Label 1040: @63512
     /*  63512 */   GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(63527), // Rule ID 3212 //
     /*  63517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63520 */     // (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  63520 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  63525 */     GIR_RootConstrainSelectedInstOperands,
     /*  63526 */     // GIR_Coverage, 3212,
     /*  63526 */     GIR_Done,
     /*  63527 */   // Label 1041: @63527
     /*  63527 */   GIM_Reject,
     /*  63528 */ // Label 1032: @63528
     /*  63528 */ GIM_Reject,
     /*  63529 */ // Label 939: @63529
     /*  63529 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(64069),
     /*  63534 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63537 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  63544 */   GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(63601), // Rule ID 16132 //
     /*  63549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63552 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63556 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63560 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63564 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63580 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63584 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63586 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] }), nxv4i1:{ *:[nxv4i1] }:$Op2), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63595 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63599 */     GIR_RootConstrainSelectedInstOperands,
     /*  63600 */     // GIR_Coverage, 16132,
     /*  63600 */     GIR_EraseRootFromParent_Done,
     /*  63601 */   // Label 1043: @63601
     /*  63601 */   GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(63658), // Rule ID 16135 //
     /*  63606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63621 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63633 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63637 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63641 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63643 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] }), nxv4i1:{ *:[nxv4i1] }:$Op2), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63650 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63656 */     GIR_RootConstrainSelectedInstOperands,
     /*  63657 */     // GIR_Coverage, 16135,
     /*  63657 */     GIR_EraseRootFromParent_Done,
     /*  63658 */   // Label 1044: @63658
     /*  63658 */   GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(63715), // Rule ID 16131 //
     /*  63663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63666 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63670 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63674 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63678 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63682 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63686 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63690 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63694 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63698 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63700 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] })), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63713 */     GIR_RootConstrainSelectedInstOperands,
     /*  63714 */     // GIR_Coverage, 16131,
     /*  63714 */     GIR_EraseRootFromParent_Done,
     /*  63715 */   // Label 1045: @63715
     /*  63715 */   GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(63772), // Rule ID 16134 //
     /*  63720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63723 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  63727 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63731 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63735 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63747 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63751 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63755 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63757 */     // (and:{ *:[nxv4i1] } (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] })), nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63762 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  63766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63770 */     GIR_RootConstrainSelectedInstOperands,
     /*  63771 */     // GIR_Coverage, 16134,
     /*  63771 */     GIR_EraseRootFromParent_Done,
     /*  63772 */   // Label 1046: @63772
     /*  63772 */   GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(63829), // Rule ID 16130 //
     /*  63777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63792 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63804 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63808 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63812 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63814 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] }), nxv4i1:{ *:[nxv4i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63819 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63821 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63827 */     GIR_RootConstrainSelectedInstOperands,
     /*  63828 */     // GIR_Coverage, 16130,
     /*  63828 */     GIR_EraseRootFromParent_Done,
     /*  63829 */   // Label 1047: @63829
     /*  63829 */   GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(63886), // Rule ID 16133 //
     /*  63834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63837 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63841 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63845 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63849 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63853 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  63857 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63861 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63865 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63869 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63871 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] }), nxv4i1:{ *:[nxv4i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63876 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63878 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63880 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  63884 */     GIR_RootConstrainSelectedInstOperands,
     /*  63885 */     // GIR_Coverage, 16133,
     /*  63885 */     GIR_EraseRootFromParent_Done,
     /*  63886 */   // Label 1048: @63886
     /*  63886 */   GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(63943), // Rule ID 9155 //
     /*  63891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63910 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63914 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63918 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  63922 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63926 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63928 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63933 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63935 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63941 */     GIR_RootConstrainSelectedInstOperands,
     /*  63942 */     // GIR_Coverage, 9155,
     /*  63942 */     GIR_EraseRootFromParent_Done,
     /*  63943 */   // Label 1049: @63943
     /*  63943 */   GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(64000), // Rule ID 9156 //
     /*  63948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  63951 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  63955 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  63959 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  63963 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  63967 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  63971 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  63975 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  63979 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  63983 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  63985 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op2, (splat_vector:{ *:[nxv4i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  63985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  63988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  63990 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63992 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  63994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  63998 */     GIR_RootConstrainSelectedInstOperands,
     /*  63999 */     // GIR_Coverage, 9156,
     /*  63999 */     GIR_EraseRootFromParent_Done,
     /*  64000 */   // Label 1050: @64000
     /*  64000 */   GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(64047), // Rule ID 11437 //
     /*  64005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64008 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  64012 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  64016 */     // (and:{ *:[nxv4i1] } PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv4i1] }:$Ps1, PPR:{ *:[nxv4i1] }:$Ps2)
     /*  64016 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  64019 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /*  64023 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  64028 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  64031 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  64033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  64036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64038 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  64041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  64043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  64045 */     GIR_RootConstrainSelectedInstOperands,
     /*  64046 */     // GIR_Coverage, 11437,
     /*  64046 */     GIR_EraseRootFromParent_Done,
     /*  64047 */   // Label 1051: @64047
     /*  64047 */   GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(64068), // Rule ID 2790 //
     /*  64052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64055 */     // (and:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  64055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  64058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64060 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64062 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  64066 */     GIR_RootConstrainSelectedInstOperands,
     /*  64067 */     // GIR_Coverage, 2790,
     /*  64067 */     GIR_EraseRootFromParent_Done,
     /*  64068 */   // Label 1052: @64068
     /*  64068 */   GIM_Reject,
     /*  64069 */ // Label 1042: @64069
     /*  64069 */ GIM_Reject,
     /*  64070 */ // Label 940: @64070
     /*  64070 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(64541),
     /*  64075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64078 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  64085 */   GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(64140), // Rule ID 16067 //
     /*  64090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64121 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64125 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64127 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64134 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64138 */     GIR_RootConstrainSelectedInstOperands,
     /*  64139 */     // GIR_Coverage, 16067,
     /*  64139 */     GIR_EraseRootFromParent_Done,
     /*  64140 */   // Label 1054: @64140
     /*  64140 */   GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(64195), // Rule ID 16070 //
     /*  64145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64160 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64164 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64168 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64172 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64176 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64180 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64182 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64193 */     GIR_RootConstrainSelectedInstOperands,
     /*  64194 */     // GIR_Coverage, 16070,
     /*  64194 */     GIR_EraseRootFromParent_Done,
     /*  64195 */   // Label 1055: @64195
     /*  64195 */   GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(64250), // Rule ID 16066 //
     /*  64200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64215 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64223 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64227 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64231 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64235 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64237 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64248 */     GIR_RootConstrainSelectedInstOperands,
     /*  64249 */     // GIR_Coverage, 16066,
     /*  64249 */     GIR_EraseRootFromParent_Done,
     /*  64250 */   // Label 1056: @64250
     /*  64250 */   GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(64305), // Rule ID 16069 //
     /*  64255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64270 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64274 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64278 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64282 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64286 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64290 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64292 */     // (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64303 */     GIR_RootConstrainSelectedInstOperands,
     /*  64304 */     // GIR_Coverage, 16069,
     /*  64304 */     GIR_EraseRootFromParent_Done,
     /*  64305 */   // Label 1057: @64305
     /*  64305 */   GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(64360), // Rule ID 16065 //
     /*  64310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64329 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64333 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64337 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64341 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64345 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64347 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64352 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64358 */     GIR_RootConstrainSelectedInstOperands,
     /*  64359 */     // GIR_Coverage, 16065,
     /*  64359 */     GIR_EraseRootFromParent_Done,
     /*  64360 */   // Label 1058: @64360
     /*  64360 */   GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(64415), // Rule ID 16068 //
     /*  64365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64384 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64388 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64392 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64396 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64400 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64402 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64407 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64409 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64413 */     GIR_RootConstrainSelectedInstOperands,
     /*  64414 */     // GIR_Coverage, 16068,
     /*  64414 */     GIR_EraseRootFromParent_Done,
     /*  64415 */   // Label 1059: @64415
     /*  64415 */   GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(64470), // Rule ID 8142 //
     /*  64420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64423 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64427 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64431 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64435 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64439 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64443 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64447 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64451 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64455 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64457 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64462 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64468 */     GIR_RootConstrainSelectedInstOperands,
     /*  64469 */     // GIR_Coverage, 8142,
     /*  64469 */     GIR_EraseRootFromParent_Done,
     /*  64470 */   // Label 1060: @64470
     /*  64470 */   GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(64525), // Rule ID 8143 //
     /*  64475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64482 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64486 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  64490 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  64494 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64498 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64502 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64506 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64510 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64512 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (splat_vector:{ *:[nxv4i32] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  64515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  64517 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64519 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64523 */     GIR_RootConstrainSelectedInstOperands,
     /*  64524 */     // GIR_Coverage, 8143,
     /*  64524 */     GIR_EraseRootFromParent_Done,
     /*  64525 */   // Label 1061: @64525
     /*  64525 */   GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(64540), // Rule ID 3211 //
     /*  64530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64533 */     // (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  64533 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  64538 */     GIR_RootConstrainSelectedInstOperands,
     /*  64539 */     // GIR_Coverage, 3211,
     /*  64539 */     GIR_Done,
     /*  64540 */   // Label 1062: @64540
     /*  64540 */   GIM_Reject,
     /*  64541 */ // Label 1053: @64541
     /*  64541 */ GIM_Reject,
     /*  64542 */ // Label 941: @64542
     /*  64542 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(65082),
     /*  64547 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64550 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  64557 */   GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(64614), // Rule ID 16123 //
     /*  64562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64573 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64577 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64589 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64593 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64597 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64599 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] }), nxv8i1:{ *:[nxv8i1] }:$Op2), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64612 */     GIR_RootConstrainSelectedInstOperands,
     /*  64613 */     // GIR_Coverage, 16123,
     /*  64613 */     GIR_EraseRootFromParent_Done,
     /*  64614 */   // Label 1064: @64614
     /*  64614 */   GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(64671), // Rule ID 16126 //
     /*  64619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64622 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64626 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64630 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64634 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64638 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64642 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64646 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64650 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64654 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64656 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] }), nxv8i1:{ *:[nxv8i1] }:$Op2), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64669 */     GIR_RootConstrainSelectedInstOperands,
     /*  64670 */     // GIR_Coverage, 16126,
     /*  64670 */     GIR_EraseRootFromParent_Done,
     /*  64671 */   // Label 1065: @64671
     /*  64671 */   GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(64728), // Rule ID 16122 //
     /*  64676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64679 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64683 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64687 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64691 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64695 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64699 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64703 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64707 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64711 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64713 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] })), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64720 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64726 */     GIR_RootConstrainSelectedInstOperands,
     /*  64727 */     // GIR_Coverage, 16122,
     /*  64727 */     GIR_EraseRootFromParent_Done,
     /*  64728 */   // Label 1066: @64728
     /*  64728 */   GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(64785), // Rule ID 16125 //
     /*  64733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64736 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  64740 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64744 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64748 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64752 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64756 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64760 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64764 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64768 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64770 */     // (and:{ *:[nxv8i1] } (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] })), nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  64779 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64783 */     GIR_RootConstrainSelectedInstOperands,
     /*  64784 */     // GIR_Coverage, 16125,
     /*  64784 */     GIR_EraseRootFromParent_Done,
     /*  64785 */   // Label 1067: @64785
     /*  64785 */   GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(64842), // Rule ID 16121 //
     /*  64790 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64805 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64809 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64813 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64817 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64821 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64825 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64827 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] }), nxv8i1:{ *:[nxv8i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64832 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64834 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64840 */     GIR_RootConstrainSelectedInstOperands,
     /*  64841 */     // GIR_Coverage, 16121,
     /*  64841 */     GIR_EraseRootFromParent_Done,
     /*  64842 */   // Label 1068: @64842
     /*  64842 */   GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(64899), // Rule ID 16124 //
     /*  64847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64854 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64858 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64862 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64866 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  64870 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64874 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64878 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64882 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64884 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] }), nxv8i1:{ *:[nxv8i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64889 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64891 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64893 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  64897 */     GIR_RootConstrainSelectedInstOperands,
     /*  64898 */     // GIR_Coverage, 16124,
     /*  64898 */     GIR_EraseRootFromParent_Done,
     /*  64899 */   // Label 1069: @64899
     /*  64899 */   GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(64956), // Rule ID 9151 //
     /*  64904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64911 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64915 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64919 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64931 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  64935 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64939 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64941 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  64944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  64946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64948 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  64950 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  64954 */     GIR_RootConstrainSelectedInstOperands,
     /*  64955 */     // GIR_Coverage, 9151,
     /*  64955 */     GIR_EraseRootFromParent_Done,
     /*  64956 */   // Label 1070: @64956
     /*  64956 */   GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(65013), // Rule ID 9152 //
     /*  64961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  64964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  64968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  64972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  64976 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  64980 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  64984 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  64988 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  64992 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  64996 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  64998 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op2, (splat_vector:{ *:[nxv8i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  64998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65003 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65005 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65007 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65011 */     GIR_RootConstrainSelectedInstOperands,
     /*  65012 */     // GIR_Coverage, 9152,
     /*  65012 */     GIR_EraseRootFromParent_Done,
     /*  65013 */   // Label 1071: @65013
     /*  65013 */   GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(65060), // Rule ID 11436 //
     /*  65018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65021 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  65025 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  65029 */     // (and:{ *:[nxv8i1] } PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv8i1] }:$Ps1, PPR:{ *:[nxv8i1] }:$Ps2)
     /*  65029 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  65032 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /*  65036 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  65041 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  65044 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  65046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  65049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65051 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  65054 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  65056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  65058 */     GIR_RootConstrainSelectedInstOperands,
     /*  65059 */     // GIR_Coverage, 11436,
     /*  65059 */     GIR_EraseRootFromParent_Done,
     /*  65060 */   // Label 1072: @65060
     /*  65060 */   GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(65081), // Rule ID 2789 //
     /*  65065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65068 */     // (and:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  65068 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  65071 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65073 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65075 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  65079 */     GIR_RootConstrainSelectedInstOperands,
     /*  65080 */     // GIR_Coverage, 2789,
     /*  65080 */     GIR_EraseRootFromParent_Done,
     /*  65081 */   // Label 1073: @65081
     /*  65081 */   GIM_Reject,
     /*  65082 */ // Label 1063: @65082
     /*  65082 */ GIM_Reject,
     /*  65083 */ // Label 942: @65083
     /*  65083 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(65554),
     /*  65088 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65091 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  65098 */   GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(65153), // Rule ID 16058 //
     /*  65103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65122 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65126 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65130 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65134 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65138 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65140 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65147 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65151 */     GIR_RootConstrainSelectedInstOperands,
     /*  65152 */     // GIR_Coverage, 16058,
     /*  65152 */     GIR_EraseRootFromParent_Done,
     /*  65153 */   // Label 1075: @65153
     /*  65153 */   GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(65208), // Rule ID 16061 //
     /*  65158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65169 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65173 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65189 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65193 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65195 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65206 */     GIR_RootConstrainSelectedInstOperands,
     /*  65207 */     // GIR_Coverage, 16061,
     /*  65207 */     GIR_EraseRootFromParent_Done,
     /*  65208 */   // Label 1076: @65208
     /*  65208 */   GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(65263), // Rule ID 16057 //
     /*  65213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65216 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65220 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65224 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65228 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65232 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65236 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65240 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65244 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65248 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65250 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65261 */     GIR_RootConstrainSelectedInstOperands,
     /*  65262 */     // GIR_Coverage, 16057,
     /*  65262 */     GIR_EraseRootFromParent_Done,
     /*  65263 */   // Label 1077: @65263
     /*  65263 */   GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(65318), // Rule ID 16060 //
     /*  65268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65279 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65283 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65287 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65291 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65295 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65299 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65303 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65305 */     // (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65316 */     GIR_RootConstrainSelectedInstOperands,
     /*  65317 */     // GIR_Coverage, 16060,
     /*  65317 */     GIR_EraseRootFromParent_Done,
     /*  65318 */   // Label 1078: @65318
     /*  65318 */   GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(65373), // Rule ID 16056 //
     /*  65323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65338 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65342 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65346 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65350 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65354 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65358 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65360 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65365 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65367 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65371 */     GIR_RootConstrainSelectedInstOperands,
     /*  65372 */     // GIR_Coverage, 16056,
     /*  65372 */     GIR_EraseRootFromParent_Done,
     /*  65373 */   // Label 1079: @65373
     /*  65373 */   GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(65428), // Rule ID 16059 //
     /*  65378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65385 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65389 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65393 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65405 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65409 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65413 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65415 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65420 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65426 */     GIR_RootConstrainSelectedInstOperands,
     /*  65427 */     // GIR_Coverage, 16059,
     /*  65427 */     GIR_EraseRootFromParent_Done,
     /*  65428 */   // Label 1080: @65428
     /*  65428 */   GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(65483), // Rule ID 8138 //
     /*  65433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65448 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65452 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65456 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65460 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65464 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65468 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65470 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65475 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65477 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65481 */     GIR_RootConstrainSelectedInstOperands,
     /*  65482 */     // GIR_Coverage, 8138,
     /*  65482 */     GIR_EraseRootFromParent_Done,
     /*  65483 */   // Label 1081: @65483
     /*  65483 */   GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(65538), // Rule ID 8139 //
     /*  65488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65491 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65495 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65499 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  65503 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  65507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65519 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65523 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65525 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (splat_vector:{ *:[nxv8i16] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  65528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  65530 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65536 */     GIR_RootConstrainSelectedInstOperands,
     /*  65537 */     // GIR_Coverage, 8139,
     /*  65537 */     GIR_EraseRootFromParent_Done,
     /*  65538 */   // Label 1082: @65538
     /*  65538 */   GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(65553), // Rule ID 3210 //
     /*  65543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65546 */     // (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  65546 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  65551 */     GIR_RootConstrainSelectedInstOperands,
     /*  65552 */     // GIR_Coverage, 3210,
     /*  65552 */     GIR_Done,
     /*  65553 */   // Label 1083: @65553
     /*  65553 */   GIM_Reject,
     /*  65554 */ // Label 1074: @65554
     /*  65554 */ GIM_Reject,
     /*  65555 */ // Label 943: @65555
     /*  65555 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(66095),
     /*  65560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65563 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  65570 */   GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(65627), // Rule ID 16114 //
     /*  65575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65594 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65598 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65602 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65606 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65610 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65612 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] }), nxv16i1:{ *:[nxv16i1] }:$Op2), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65619 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65621 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65625 */     GIR_RootConstrainSelectedInstOperands,
     /*  65626 */     // GIR_Coverage, 16114,
     /*  65626 */     GIR_EraseRootFromParent_Done,
     /*  65627 */   // Label 1085: @65627
     /*  65627 */   GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(65684), // Rule ID 16117 //
     /*  65632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65659 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65663 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65667 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65669 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] }), nxv16i1:{ *:[nxv16i1] }:$Op2), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65682 */     GIR_RootConstrainSelectedInstOperands,
     /*  65683 */     // GIR_Coverage, 16117,
     /*  65683 */     GIR_EraseRootFromParent_Done,
     /*  65684 */   // Label 1086: @65684
     /*  65684 */   GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(65741), // Rule ID 16113 //
     /*  65689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65700 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65704 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65708 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65712 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65716 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65720 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65724 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65726 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] })), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65731 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65733 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65739 */     GIR_RootConstrainSelectedInstOperands,
     /*  65740 */     // GIR_Coverage, 16113,
     /*  65740 */     GIR_EraseRootFromParent_Done,
     /*  65741 */   // Label 1087: @65741
     /*  65741 */   GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(65798), // Rule ID 16116 //
     /*  65746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  65753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65761 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65773 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65777 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65781 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65783 */     // (and:{ *:[nxv16i1] } (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] })), nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65790 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  65792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65796 */     GIR_RootConstrainSelectedInstOperands,
     /*  65797 */     // GIR_Coverage, 16116,
     /*  65797 */     GIR_EraseRootFromParent_Done,
     /*  65798 */   // Label 1088: @65798
     /*  65798 */   GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(65855), // Rule ID 16112 //
     /*  65803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65818 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65822 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65826 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65830 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65834 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65838 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65840 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] }), nxv16i1:{ *:[nxv16i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65845 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65847 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65853 */     GIR_RootConstrainSelectedInstOperands,
     /*  65854 */     // GIR_Coverage, 16112,
     /*  65854 */     GIR_EraseRootFromParent_Done,
     /*  65855 */   // Label 1089: @65855
     /*  65855 */   GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(65912), // Rule ID 16115 //
     /*  65860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  65883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  65891 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65895 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65897 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] }), nxv16i1:{ *:[nxv16i1] }:$Op2))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65902 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65904 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65906 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  65910 */     GIR_RootConstrainSelectedInstOperands,
     /*  65911 */     // GIR_Coverage, 16115,
     /*  65911 */     GIR_EraseRootFromParent_Done,
     /*  65912 */   // Label 1090: @65912
     /*  65912 */   GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(65969), // Rule ID 9147 //
     /*  65917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65928 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65932 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65936 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65940 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  65944 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  65948 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  65952 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  65954 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i32] })))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  65954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  65957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  65959 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65961 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  65963 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  65967 */     GIR_RootConstrainSelectedInstOperands,
     /*  65968 */     // GIR_Coverage, 9147,
     /*  65968 */     GIR_EraseRootFromParent_Done,
     /*  65969 */   // Label 1091: @65969
     /*  65969 */   GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(66026), // Rule ID 9148 //
     /*  65974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  65977 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  65981 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  65985 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  65989 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  65993 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  65997 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66001 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  66005 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66009 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66011 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op2, (splat_vector:{ *:[nxv16i1] } -1:{ *:[i64] })))  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  66011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /*  66014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  66016 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66018 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66020 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  66024 */     GIR_RootConstrainSelectedInstOperands,
     /*  66025 */     // GIR_Coverage, 9148,
     /*  66025 */     GIR_EraseRootFromParent_Done,
     /*  66026 */   // Label 1092: @66026
     /*  66026 */   GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(66073), // Rule ID 11435 //
     /*  66031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66034 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  66038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /*  66042 */     // (and:{ *:[nxv16i1] } PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2)  =>  (AND_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), PPR:{ *:[nxv16i1] }:$Ps1, PPR:{ *:[nxv16i1] }:$Ps2)
     /*  66042 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  66045 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /*  66049 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  66054 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  66057 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  66059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  66062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  66064 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  66067 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps1
     /*  66069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ps2
     /*  66071 */     GIR_RootConstrainSelectedInstOperands,
     /*  66072 */     // GIR_Coverage, 11435,
     /*  66072 */     GIR_EraseRootFromParent_Done,
     /*  66073 */   // Label 1093: @66073
     /*  66073 */   GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(66094), // Rule ID 2788 //
     /*  66078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66081 */     // (and:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  66081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /*  66084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  66086 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66088 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66090 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  66092 */     GIR_RootConstrainSelectedInstOperands,
     /*  66093 */     // GIR_Coverage, 2788,
     /*  66093 */     GIR_EraseRootFromParent_Done,
     /*  66094 */   // Label 1094: @66094
     /*  66094 */   GIM_Reject,
     /*  66095 */ // Label 1084: @66095
     /*  66095 */ GIM_Reject,
     /*  66096 */ // Label 944: @66096
     /*  66096 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(66567),
     /*  66101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66104 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  66111 */   GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(66166), // Rule ID 16049 //
     /*  66116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66131 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66135 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66139 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66143 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  66147 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66151 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66153 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  66160 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  66164 */     GIR_RootConstrainSelectedInstOperands,
     /*  66165 */     // GIR_Coverage, 16049,
     /*  66165 */     GIR_EraseRootFromParent_Done,
     /*  66166 */   // Label 1096: @66166
     /*  66166 */   GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(66221), // Rule ID 16052 //
     /*  66171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66186 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66190 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66194 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66198 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  66202 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66206 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66208 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  66215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  66219 */     GIR_RootConstrainSelectedInstOperands,
     /*  66220 */     // GIR_Coverage, 16052,
     /*  66220 */     GIR_EraseRootFromParent_Done,
     /*  66221 */   // Label 1097: @66221
     /*  66221 */   GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(66276), // Rule ID 16048 //
     /*  66226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66229 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66233 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66237 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66241 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  66257 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66261 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66263 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  66270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  66274 */     GIR_RootConstrainSelectedInstOperands,
     /*  66275 */     // GIR_Coverage, 16048,
     /*  66275 */     GIR_EraseRootFromParent_Done,
     /*  66276 */   // Label 1098: @66276
     /*  66276 */   GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(66331), // Rule ID 16051 //
     /*  66281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66296 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66300 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66304 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66308 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  66312 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66316 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66318 */     // (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /*  66325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  66329 */     GIR_RootConstrainSelectedInstOperands,
     /*  66330 */     // GIR_Coverage, 16051,
     /*  66330 */     GIR_EraseRootFromParent_Done,
     /*  66331 */   // Label 1099: @66331
     /*  66331 */   GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(66386), // Rule ID 16047 //
     /*  66336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66351 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66355 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66359 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66363 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  66367 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66371 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66373 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  66384 */     GIR_RootConstrainSelectedInstOperands,
     /*  66385 */     // GIR_Coverage, 16047,
     /*  66385 */     GIR_EraseRootFromParent_Done,
     /*  66386 */   // Label 1100: @66386
     /*  66386 */   GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(66441), // Rule ID 16050 //
     /*  66391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66406 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66410 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  66414 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66418 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  66422 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66426 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66428 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66433 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66435 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  66439 */     GIR_RootConstrainSelectedInstOperands,
     /*  66440 */     // GIR_Coverage, 16050,
     /*  66440 */     GIR_EraseRootFromParent_Done,
     /*  66441 */   // Label 1101: @66441
     /*  66441 */   GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(66496), // Rule ID 8134 //
     /*  66446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66453 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66457 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66461 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66465 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66469 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66473 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /*  66477 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66481 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66483 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i32] })))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66488 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  66494 */     GIR_RootConstrainSelectedInstOperands,
     /*  66495 */     // GIR_Coverage, 8134,
     /*  66495 */     GIR_EraseRootFromParent_Done,
     /*  66496 */   // Label 1102: @66496
     /*  66496 */   GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(66551), // Rule ID 8135 //
     /*  66501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  66516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  66520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  66524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /*  66528 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  66532 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 255,
     /*  66536 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  66538 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (splat_vector:{ *:[nxv16i8] } -1:{ *:[i64] })))  =>  (BIC_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZZZ),
     /*  66541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /*  66543 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  66545 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  66549 */     GIR_RootConstrainSelectedInstOperands,
     /*  66550 */     // GIR_Coverage, 8135,
     /*  66550 */     GIR_EraseRootFromParent_Done,
     /*  66551 */   // Label 1103: @66551
     /*  66551 */   GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(66566), // Rule ID 3209 //
     /*  66556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  66559 */     // (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (AND_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  66559 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::AND_ZZZ),
     /*  66564 */     GIR_RootConstrainSelectedInstOperands,
     /*  66565 */     // GIR_Coverage, 3209,
     /*  66565 */     GIR_Done,
     /*  66566 */   // Label 1104: @66566
     /*  66566 */   GIM_Reject,
     /*  66567 */ // Label 1095: @66567
     /*  66567 */ GIM_Reject,
     /*  66568 */ // Label 945: @66568
     /*  66568 */ GIM_Reject,
     /*  66569 */ // Label 6: @66569
     /*  66569 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1123*/ GIMT_Encode4(92011),
     /*  66580 */ /*GILLT_s32*//*Label 1105*/ GIMT_Encode4(66668),
     /*  66584 */ /*GILLT_s64*//*Label 1106*/ GIMT_Encode4(67028), GIMT_Encode4(0),
     /*  66592 */ /*GILLT_v2s32*//*Label 1107*/ GIMT_Encode4(68915),
     /*  66596 */ /*GILLT_v2s64*//*Label 1108*/ GIMT_Encode4(70211),
     /*  66600 */ /*GILLT_v4s16*//*Label 1109*/ GIMT_Encode4(71507),
     /*  66604 */ /*GILLT_v4s32*//*Label 1110*/ GIMT_Encode4(72803),
     /*  66608 */ /*GILLT_v8s8*//*Label 1111*/ GIMT_Encode4(74099),
     /*  66612 */ /*GILLT_v8s16*//*Label 1112*/ GIMT_Encode4(75395),
     /*  66616 */ /*GILLT_v16s8*//*Label 1113*/ GIMT_Encode4(76691),
     /*  66620 */ /*GILLT_nxv1s1*//*Label 1114*/ GIMT_Encode4(77987),
     /*  66624 */ /*GILLT_nxv2s1*//*Label 1115*/ GIMT_Encode4(78019), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  66636 */ /*GILLT_nxv2s64*//*Label 1116*/ GIMT_Encode4(78051),
     /*  66640 */ /*GILLT_nxv4s1*//*Label 1117*/ GIMT_Encode4(81517), GIMT_Encode4(0),
     /*  66648 */ /*GILLT_nxv4s32*//*Label 1118*/ GIMT_Encode4(81549),
     /*  66652 */ /*GILLT_nxv8s1*//*Label 1119*/ GIMT_Encode4(85015),
     /*  66656 */ /*GILLT_nxv8s16*//*Label 1120*/ GIMT_Encode4(85047),
     /*  66660 */ /*GILLT_nxv16s1*//*Label 1121*/ GIMT_Encode4(88513),
     /*  66664 */ /*GILLT_nxv16s8*//*Label 1122*/ GIMT_Encode4(88545),
     /*  66668 */ // Label 1105: @66668
     /*  66668 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(67027),
     /*  66673 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  66676 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  66679 */   GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(66734), // Rule ID 14309 //
     /*  66684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66688 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66692 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66696 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  66700 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  66704 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  66708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66712 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  66714 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  66721 */     // (or:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  66721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
     /*  66724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  66728 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  66732 */     GIR_RootConstrainSelectedInstOperands,
     /*  66733 */     // GIR_Coverage, 14309,
     /*  66733 */     GIR_EraseRootFromParent_Done,
     /*  66734 */   // Label 1125: @66734
     /*  66734 */   GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(66789), // Rule ID 166 //
     /*  66739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66743 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66751 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66755 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  66759 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  66763 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  66767 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  66769 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  66776 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (ORNWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  66776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
     /*  66779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  66783 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  66787 */     GIR_RootConstrainSelectedInstOperands,
     /*  66788 */     // GIR_Coverage, 166,
     /*  66788 */     GIR_EraseRootFromParent_Done,
     /*  66789 */   // Label 1126: @66789
     /*  66789 */   GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(66830), // Rule ID 134 //
     /*  66794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  66798 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66802 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66806 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  66810 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  66814 */     // MIs[1] Operand 1
     /*  66814 */     // No operand predicates
     /*  66814 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  66816 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (ORRWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  66816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWri),
     /*  66819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66821 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  66823 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  66828 */     GIR_RootConstrainSelectedInstOperands,
     /*  66829 */     // GIR_Coverage, 134,
     /*  66829 */     GIR_EraseRootFromParent_Done,
     /*  66830 */   // Label 1127: @66830
     /*  66830 */   GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(66863), // Rule ID 14311 //
     /*  66835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66843 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  66850 */     // (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  66850 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
     /*  66853 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  66857 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  66861 */     GIR_RootConstrainSelectedInstOperands,
     /*  66862 */     // GIR_Coverage, 14311,
     /*  66862 */     GIR_EraseRootFromParent_Done,
     /*  66863 */   // Label 1128: @66863
     /*  66863 */   GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(66896), // Rule ID 170 //
     /*  66868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66872 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66876 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  66883 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (ORRWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  66883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRWrs),
     /*  66886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66888 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  66890 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  66894 */     GIR_RootConstrainSelectedInstOperands,
     /*  66895 */     // GIR_Coverage, 170,
     /*  66895 */     GIR_EraseRootFromParent_Done,
     /*  66896 */   // Label 1129: @66896
     /*  66896 */   GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(66949), // Rule ID 14307 //
     /*  66901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66905 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  66909 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66913 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  66917 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  66921 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66926 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  66930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66934 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  66936 */     // (or:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  66936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  66939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  66943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  66947 */     GIR_RootConstrainSelectedInstOperands,
     /*  66948 */     // GIR_Coverage, 14307,
     /*  66948 */     GIR_EraseRootFromParent_Done,
     /*  66949 */   // Label 1130: @66949
     /*  66949 */   GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(67002), // Rule ID 164 //
     /*  66954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66958 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  66966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  66970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  66974 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  66978 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  66983 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  66987 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  66989 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, -1:{ *:[i32] }))  =>  (ORNWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  66989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  66992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  66994 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  66996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  67000 */     GIR_RootConstrainSelectedInstOperands,
     /*  67001 */     // GIR_Coverage, 164,
     /*  67001 */     GIR_EraseRootFromParent_Done,
     /*  67002 */   // Label 1131: @67002
     /*  67002 */   GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(67026), // Rule ID 168 //
     /*  67007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  67011 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  67015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  67019 */     // (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (ORRWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  67019 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRWrr),
     /*  67024 */     GIR_RootConstrainSelectedInstOperands,
     /*  67025 */     // GIR_Coverage, 168,
     /*  67025 */     GIR_Done,
     /*  67026 */   // Label 1132: @67026
     /*  67026 */   GIM_Reject,
     /*  67027 */ // Label 1124: @67027
     /*  67027 */ GIM_Reject,
     /*  67028 */ // Label 1106: @67028
     /*  67028 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(68914),
     /*  67033 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  67036 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  67039 */   GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(67161), // Rule ID 4113 //
     /*  67044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67048 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67052 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67056 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67060 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67064 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67068 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  67072 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67076 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67080 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67085 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
     /*  67089 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(71777214294589695),
     /*  67100 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  67104 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67108 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*  67112 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  67116 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  67120 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  67124 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  67128 */     // MIs[4] Rn
     /*  67128 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67133 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
     /*  67137 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(18374966859414961920u),
     /*  67148 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67150 */     // (or:{ *:[i64] } (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }), (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }))  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /*  67150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /*  67153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  67159 */     GIR_RootConstrainSelectedInstOperands,
     /*  67160 */     // GIR_Coverage, 4113,
     /*  67160 */     GIR_EraseRootFromParent_Done,
     /*  67161 */   // Label 1134: @67161
     /*  67161 */   GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(67283), // Rule ID 14855 //
     /*  67166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67170 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67174 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67178 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67182 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  67194 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67198 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67202 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67207 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
     /*  67211 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(18374966859414961920u),
     /*  67222 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  67226 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67230 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /*  67234 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  67238 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /*  67242 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
     /*  67246 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  67250 */     // MIs[4] Rn
     /*  67250 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67255 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
     /*  67259 */     GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(71777214294589695),
     /*  67270 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67272 */     // (or:{ *:[i64] } (and:{ *:[i64] } (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), -71777214294589696:{ *:[i64] }), (and:{ *:[i64] } (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 8:{ *:[i64] }), 71777214294589695:{ *:[i64] }))  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /*  67272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /*  67275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67277 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  67281 */     GIR_RootConstrainSelectedInstOperands,
     /*  67282 */     // GIR_Coverage, 14855,
     /*  67282 */     GIR_EraseRootFromParent_Done,
     /*  67283 */   // Label 1135: @67283
     /*  67283 */   GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(67338), // Rule ID 14310 //
     /*  67288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67300 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67304 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67308 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  67312 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67316 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  67318 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  67325 */     // (or:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  67325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
     /*  67328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  67332 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  67336 */     GIR_RootConstrainSelectedInstOperands,
     /*  67337 */     // GIR_Coverage, 14310,
     /*  67337 */     GIR_EraseRootFromParent_Done,
     /*  67338 */   // Label 1136: @67338
     /*  67338 */   GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(67393), // Rule ID 167 //
     /*  67343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  67351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  67355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67363 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67367 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  67371 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  67373 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  67380 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (ORNXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  67380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
     /*  67383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  67385 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  67387 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  67391 */     GIR_RootConstrainSelectedInstOperands,
     /*  67392 */     // GIR_Coverage, 167,
     /*  67392 */     GIR_EraseRootFromParent_Done,
     /*  67393 */   // Label 1137: @67393
     /*  67393 */   GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(67502), // Rule ID 14645 //
     /*  67398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67429 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67433 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67437 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67442 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67446 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67452 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67454 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67459 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67463 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67467 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /*  67471 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67476 */     // MIs[4] LHS
     /*  67476 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67481 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67483 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  67483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  67496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  67500 */     GIR_RootConstrainSelectedInstOperands,
     /*  67501 */     // GIR_Coverage, 14645,
     /*  67501 */     GIR_EraseRootFromParent_Done,
     /*  67502 */   // Label 1138: @67502
     /*  67502 */   GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(67611), // Rule ID 14644 //
     /*  67507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67518 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67522 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67526 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67530 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  67534 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67538 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67542 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67546 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67551 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67555 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67561 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67568 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67572 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67576 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  67580 */     // MIs[4] LHS
     /*  67580 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67585 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67590 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67592 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  67592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67597 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67601 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  67605 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  67609 */     GIR_RootConstrainSelectedInstOperands,
     /*  67610 */     // GIR_Coverage, 14644,
     /*  67610 */     GIR_EraseRootFromParent_Done,
     /*  67611 */   // Label 1139: @67611
     /*  67611 */   GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(67720), // Rule ID 14647 //
     /*  67616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67631 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67635 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67639 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67644 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67648 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67652 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67656 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67660 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67665 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67669 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67675 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67677 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67681 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67685 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /*  67689 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67694 */     // MIs[4] LHS
     /*  67694 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67699 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67701 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  67701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  67714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67718 */     GIR_RootConstrainSelectedInstOperands,
     /*  67719 */     // GIR_Coverage, 14647,
     /*  67719 */     GIR_EraseRootFromParent_Done,
     /*  67720 */   // Label 1140: @67720
     /*  67720 */   GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(67829), // Rule ID 14646 //
     /*  67725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67740 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67744 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67748 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67753 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  67757 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67761 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67765 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67769 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67774 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  67778 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67784 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  67786 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  67790 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67794 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /*  67798 */     // MIs[4] LHS
     /*  67798 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  67803 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67808 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67810 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  67810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67815 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  67819 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  67823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  67827 */     GIR_RootConstrainSelectedInstOperands,
     /*  67828 */     // GIR_Coverage, 14646,
     /*  67828 */     GIR_EraseRootFromParent_Done,
     /*  67829 */   // Label 1141: @67829
     /*  67829 */   GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(67938), // Rule ID 2508 //
     /*  67834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67841 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67845 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67849 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67853 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67857 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67862 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67867 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  67871 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67875 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67879 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67883 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  67887 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  67891 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  67895 */     // MIs[3] LHS
     /*  67895 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  67900 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  67904 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  67910 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  67912 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67917 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  67919 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  67919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  67922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  67924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  67928 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  67932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  67936 */     GIR_RootConstrainSelectedInstOperands,
     /*  67937 */     // GIR_Coverage, 2508,
     /*  67937 */     GIR_EraseRootFromParent_Done,
     /*  67938 */   // Label 1142: @67938
     /*  67938 */   GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(68047), // Rule ID 14642 //
     /*  67943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  67946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  67954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67958 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  67962 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  67966 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67971 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  67976 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  67980 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  67984 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  67988 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  67992 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  67996 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68000 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  68004 */     // MIs[3] LHS
     /*  68004 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  68009 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68013 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68019 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68021 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68026 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68028 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$RHS))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  68028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68033 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  68037 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  68041 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  68045 */     GIR_RootConstrainSelectedInstOperands,
     /*  68046 */     // GIR_Coverage, 14642,
     /*  68046 */     GIR_EraseRootFromParent_Done,
     /*  68047 */   // Label 1143: @68047
     /*  68047 */   GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(68156), // Rule ID 14641 //
     /*  68052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68059 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68063 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68067 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68071 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68093 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  68097 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  68101 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68106 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68110 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68114 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  68118 */     // MIs[3] LHS
     /*  68118 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  68123 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68127 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68133 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68135 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68137 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  68137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68142 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  68146 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  68150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  68154 */     GIR_RootConstrainSelectedInstOperands,
     /*  68155 */     // GIR_Coverage, 14641,
     /*  68155 */     GIR_EraseRootFromParent_Done,
     /*  68156 */   // Label 1144: @68156
     /*  68156 */   GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(68265), // Rule ID 14643 //
     /*  68161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68180 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68184 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68189 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68194 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  68198 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68202 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  68206 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  68210 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68215 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68219 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68223 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /*  68227 */     // MIs[3] LHS
     /*  68227 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  68232 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  68236 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68242 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  68244 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  68246 */     // (or:{ *:[v1i64] } (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$LHS), (and:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, immAllOnesV:{ *:[v1i64] })))  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$MHS, V64:{ *:[v1i64] }:$RHS)
     /*  68246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  68249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68251 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  68255 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  68259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  68263 */     GIR_RootConstrainSelectedInstOperands,
     /*  68264 */     // GIR_Coverage, 14643,
     /*  68264 */     GIR_EraseRootFromParent_Done,
     /*  68265 */   // Label 1145: @68265
     /*  68265 */   GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(68306), // Rule ID 135 //
     /*  68270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  68274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68282 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  68286 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  68290 */     // MIs[1] Operand 1
     /*  68290 */     // No operand predicates
     /*  68290 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68292 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (ORRXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  68292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXri),
     /*  68295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68297 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  68299 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  68304 */     GIR_RootConstrainSelectedInstOperands,
     /*  68305 */     // GIR_Coverage, 135,
     /*  68305 */     GIR_EraseRootFromParent_Done,
     /*  68306 */   // Label 1146: @68306
     /*  68306 */   GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(68339), // Rule ID 14312 //
     /*  68311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68319 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  68326 */     // (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  68326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
     /*  68329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  68333 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  68337 */     GIR_RootConstrainSelectedInstOperands,
     /*  68338 */     // GIR_Coverage, 14312,
     /*  68338 */     GIR_EraseRootFromParent_Done,
     /*  68339 */   // Label 1147: @68339
     /*  68339 */   GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(68372), // Rule ID 171 //
     /*  68344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68348 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  68359 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (ORRXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  68359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORRXrs),
     /*  68362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68364 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  68366 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  68370 */     GIR_RootConstrainSelectedInstOperands,
     /*  68371 */     // GIR_Coverage, 171,
     /*  68371 */     GIR_EraseRootFromParent_Done,
     /*  68372 */   // Label 1148: @68372
     /*  68372 */   GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(68436), // Rule ID 14581 //
     /*  68377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  68392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68396 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68401 */     // MIs[1] imm
     /*  68401 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  68404 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  68409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68413 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68417 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68419 */     // (or:{ *:[v1i64] } (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  68419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  68422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  68426 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  68434 */     GIR_RootConstrainSelectedInstOperands,
     /*  68435 */     // GIR_Coverage, 14581,
     /*  68435 */     GIR_EraseRootFromParent_Done,
     /*  68436 */   // Label 1149: @68436
     /*  68436 */   GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(68500), // Rule ID 14584 //
     /*  68441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  68456 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68465 */     // MIs[1] imm
     /*  68465 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  68468 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  68473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68477 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68481 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68483 */     // (or:{ *:[v1i64] } (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), FPR64:{ *:[v1i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  68483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  68486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  68490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  68498 */     GIR_RootConstrainSelectedInstOperands,
     /*  68499 */     // GIR_Coverage, 14584,
     /*  68499 */     GIR_EraseRootFromParent_Done,
     /*  68500 */   // Label 1150: @68500
     /*  68500 */   GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(68553), // Rule ID 14308 //
     /*  68505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68513 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68517 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68521 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68525 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68530 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  68534 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68538 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68540 */     // (or:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  68540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  68543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  68547 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  68551 */     GIR_RootConstrainSelectedInstOperands,
     /*  68552 */     // GIR_Coverage, 14308,
     /*  68552 */     GIR_EraseRootFromParent_Done,
     /*  68553 */   // Label 1151: @68553
     /*  68553 */   GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(68617), // Rule ID 2153 //
     /*  68558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68565 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  68577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68581 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68586 */     // MIs[1] imm
     /*  68586 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  68589 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  68594 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68600 */     // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  68600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAd),
     /*  68603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68605 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  68607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  68615 */     GIR_RootConstrainSelectedInstOperands,
     /*  68616 */     // GIR_Coverage, 2153,
     /*  68616 */     GIR_EraseRootFromParent_Done,
     /*  68617 */   // Label 1152: @68617
     /*  68617 */   GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(68681), // Rule ID 2162 //
     /*  68622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68629 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68633 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68637 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  68641 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68645 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68650 */     // MIs[1] imm
     /*  68650 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  68653 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  68658 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  68662 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68664 */     // (or:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  68664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAd),
     /*  68667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  68669 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  68671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  68675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  68679 */     GIR_RootConstrainSelectedInstOperands,
     /*  68680 */     // GIR_Coverage, 2162,
     /*  68680 */     GIR_EraseRootFromParent_Done,
     /*  68681 */   // Label 1153: @68681
     /*  68681 */   GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(68734), // Rule ID 165 //
     /*  68686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68690 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68706 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68710 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68715 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  68719 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  68721 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, -1:{ *:[i64] }))  =>  (ORNXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  68721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  68724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68726 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  68728 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  68732 */     GIR_RootConstrainSelectedInstOperands,
     /*  68733 */     // GIR_Coverage, 165,
     /*  68733 */     GIR_EraseRootFromParent_Done,
     /*  68734 */   // Label 1154: @68734
     /*  68734 */   GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(68798), // Rule ID 14910 //
     /*  68739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68746 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68750 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68754 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68758 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68762 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68767 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68771 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68777 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  68779 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68783 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68785 */     // (or:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }), V64:{ *:[v1i64] }:$LHS)  =>  (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  68785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  68788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68790 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  68792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  68796 */     GIR_RootConstrainSelectedInstOperands,
     /*  68797 */     // GIR_Coverage, 14910,
     /*  68797 */     GIR_EraseRootFromParent_Done,
     /*  68798 */   // Label 1155: @68798
     /*  68798 */   GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(68862), // Rule ID 5106 //
     /*  68803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  68818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  68826 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  68830 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68835 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  68839 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68845 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  68847 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  68849 */     // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$RHS, immAllOnesV:{ *:[v1i64] }))  =>  (ORNv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  68849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  68852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  68854 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  68856 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  68860 */     GIR_RootConstrainSelectedInstOperands,
     /*  68861 */     // GIR_Coverage, 5106,
     /*  68861 */     GIR_EraseRootFromParent_Done,
     /*  68862 */   // Label 1156: @68862
     /*  68862 */   GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(68886), // Rule ID 169 //
     /*  68867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68871 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  68879 */     // (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ORRXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  68879 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRXrr),
     /*  68884 */     GIR_RootConstrainSelectedInstOperands,
     /*  68885 */     // GIR_Coverage, 169,
     /*  68885 */     GIR_Done,
     /*  68886 */   // Label 1157: @68886
     /*  68886 */   GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(68913), // Rule ID 5112 //
     /*  68891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68906 */     // (or:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (ORRv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  68906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  68911 */     GIR_RootConstrainSelectedInstOperands,
     /*  68912 */     // GIR_Coverage, 5112,
     /*  68912 */     GIR_Done,
     /*  68913 */   // Label 1158: @68913
     /*  68913 */   GIM_Reject,
     /*  68914 */ // Label 1133: @68914
     /*  68914 */ GIM_Reject,
     /*  68915 */ // Label 1107: @68915
     /*  68915 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(70210),
     /*  68920 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  68923 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  68926 */   GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(69035), // Rule ID 14638 //
     /*  68931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  68934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68938 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  68942 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  68946 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  68950 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  68954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  68958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  68962 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  68966 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  68970 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68975 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  68979 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  68985 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  68987 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  68992 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  68996 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69000 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69004 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69009 */     // MIs[4] LHS
     /*  69009 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69014 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69016 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69021 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  69029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  69033 */     GIR_RootConstrainSelectedInstOperands,
     /*  69034 */     // GIR_Coverage, 14638,
     /*  69034 */     GIR_EraseRootFromParent_Done,
     /*  69035 */   // Label 1160: @69035
     /*  69035 */   GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(69144), // Rule ID 14637 //
     /*  69040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69047 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69051 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69055 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69059 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69063 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  69067 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69071 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69075 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69079 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69084 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69088 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69094 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69096 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69101 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69105 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69109 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69113 */     // MIs[4] LHS
     /*  69113 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69118 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69123 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69125 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69134 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  69138 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  69142 */     GIR_RootConstrainSelectedInstOperands,
     /*  69143 */     // GIR_Coverage, 14637,
     /*  69143 */     GIR_EraseRootFromParent_Done,
     /*  69144 */   // Label 1161: @69144
     /*  69144 */   GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(69253), // Rule ID 14640 //
     /*  69149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69172 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69189 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69193 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69198 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69202 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69208 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69210 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69214 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69218 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69222 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69227 */     // MIs[4] LHS
     /*  69227 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69232 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69234 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69239 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69243 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  69247 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  69251 */     GIR_RootConstrainSelectedInstOperands,
     /*  69252 */     // GIR_Coverage, 14640,
     /*  69252 */     GIR_EraseRootFromParent_Done,
     /*  69253 */   // Label 1162: @69253
     /*  69253 */   GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(69362), // Rule ID 14639 //
     /*  69258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69277 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69281 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  69290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69294 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69298 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69302 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69307 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69311 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69317 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  69319 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  69323 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69327 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69331 */     // MIs[4] LHS
     /*  69331 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  69336 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69341 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69343 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69348 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  69352 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  69356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  69360 */     GIR_RootConstrainSelectedInstOperands,
     /*  69361 */     // GIR_Coverage, 14639,
     /*  69361 */     GIR_EraseRootFromParent_Done,
     /*  69362 */   // Label 1163: @69362
     /*  69362 */   GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(69471), // Rule ID 2507 //
     /*  69367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69386 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69390 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69395 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69400 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69404 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69408 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69412 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69416 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  69420 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69424 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69428 */     // MIs[3] LHS
     /*  69428 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  69433 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69437 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69443 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69445 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69450 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69452 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69457 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  69461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  69465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  69469 */     GIR_RootConstrainSelectedInstOperands,
     /*  69470 */     // GIR_Coverage, 2507,
     /*  69470 */     GIR_EraseRootFromParent_Done,
     /*  69471 */   // Label 1164: @69471
     /*  69471 */   GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(69580), // Rule ID 14635 //
     /*  69476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69483 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69487 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69491 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69495 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69499 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69504 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69509 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69513 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69517 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69521 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69525 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  69529 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69533 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69537 */     // MIs[3] LHS
     /*  69537 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  69542 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69546 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69552 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69554 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69559 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69561 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$RHS))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  69570 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  69574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  69578 */     GIR_RootConstrainSelectedInstOperands,
     /*  69579 */     // GIR_Coverage, 14635,
     /*  69579 */     GIR_EraseRootFromParent_Done,
     /*  69580 */   // Label 1165: @69580
     /*  69580 */   GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(69689), // Rule ID 14634 //
     /*  69585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69604 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69613 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69618 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69622 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69626 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69630 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69634 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69639 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69643 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69647 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69651 */     // MIs[3] LHS
     /*  69651 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  69656 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69660 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69666 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69668 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69670 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  69679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  69683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  69687 */     GIR_RootConstrainSelectedInstOperands,
     /*  69688 */     // GIR_Coverage, 14634,
     /*  69688 */     GIR_EraseRootFromParent_Done,
     /*  69689 */   // Label 1166: @69689
     /*  69689 */   GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(69798), // Rule ID 14636 //
     /*  69694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69713 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69722 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69727 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  69731 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  69735 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69739 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69743 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69748 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  69752 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  69756 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  69760 */     // MIs[3] LHS
     /*  69760 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  69765 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  69769 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  69775 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  69777 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  69779 */     // (or:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$LHS), (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, immAllOnesV:{ *:[v2i32] })))  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$MHS, V64:{ *:[v2i32] }:$RHS)
     /*  69779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  69782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  69788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  69792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  69796 */     GIR_RootConstrainSelectedInstOperands,
     /*  69797 */     // GIR_Coverage, 14636,
     /*  69797 */     GIR_EraseRootFromParent_Done,
     /*  69798 */   // Label 1167: @69798
     /*  69798 */   GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(69862), // Rule ID 14601 //
     /*  69803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  69818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69822 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69827 */     // MIs[1] imm
     /*  69827 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  69830 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69835 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69839 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69843 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  69845 */     // (or:{ *:[v2i32] } (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  69845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  69848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  69852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69856 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  69860 */     GIR_RootConstrainSelectedInstOperands,
     /*  69861 */     // GIR_Coverage, 14601,
     /*  69861 */     GIR_EraseRootFromParent_Done,
     /*  69862 */   // Label 1168: @69862
     /*  69862 */   GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(69926), // Rule ID 14622 //
     /*  69867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69874 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  69878 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  69882 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69886 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69891 */     // MIs[1] imm
     /*  69891 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  69894 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69903 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69907 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  69909 */     // (or:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V64:{ *:[v2i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  69909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  69912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  69916 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69920 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  69924 */     GIR_RootConstrainSelectedInstOperands,
     /*  69925 */     // GIR_Coverage, 14622,
     /*  69925 */     GIR_EraseRootFromParent_Done,
     /*  69926 */   // Label 1169: @69926
     /*  69926 */   GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(69990), // Rule ID 2270 //
     /*  69931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69938 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69942 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  69946 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  69950 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  69954 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  69959 */     // MIs[1] imm
     /*  69959 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  69962 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  69967 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  69971 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  69973 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  69973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i32_shift),
     /*  69976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  69978 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  69980 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  69984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  69988 */     GIR_RootConstrainSelectedInstOperands,
     /*  69989 */     // GIR_Coverage, 2270,
     /*  69989 */     GIR_EraseRootFromParent_Done,
     /*  69990 */   // Label 1170: @69990
     /*  69990 */   GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(70054), // Rule ID 2329 //
     /*  69995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  69998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70002 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  70010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  70014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  70018 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70023 */     // MIs[1] imm
     /*  70023 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  70026 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  70031 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  70035 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  70037 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  70037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i32_shift),
     /*  70040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70042 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  70044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  70048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  70052 */     GIR_RootConstrainSelectedInstOperands,
     /*  70053 */     // GIR_Coverage, 2329,
     /*  70053 */     GIR_EraseRootFromParent_Done,
     /*  70054 */   // Label 1171: @70054
     /*  70054 */   GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(70118), // Rule ID 14909 //
     /*  70059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70074 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  70078 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  70082 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70087 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70091 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70097 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  70099 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70103 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  70105 */     // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }), V64:{ *:[v2i32] }:$LHS)  =>  (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  70105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  70108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  70110 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  70112 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70116 */     GIR_RootConstrainSelectedInstOperands,
     /*  70117 */     // GIR_Coverage, 14909,
     /*  70117 */     GIR_EraseRootFromParent_Done,
     /*  70118 */   // Label 1172: @70118
     /*  70118 */   GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(70182), // Rule ID 5105 //
     /*  70123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70130 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70134 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  70138 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70142 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  70146 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  70150 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70155 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70159 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70165 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  70167 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  70169 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$RHS, immAllOnesV:{ *:[v2i32] }))  =>  (ORNv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  70169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  70172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  70174 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  70176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70180 */     GIR_RootConstrainSelectedInstOperands,
     /*  70181 */     // GIR_Coverage, 5105,
     /*  70181 */     GIR_EraseRootFromParent_Done,
     /*  70182 */   // Label 1173: @70182
     /*  70182 */   GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(70209), // Rule ID 5111 //
     /*  70187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70194 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  70202 */     // (or:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (ORRv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  70202 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  70207 */     GIR_RootConstrainSelectedInstOperands,
     /*  70208 */     // GIR_Coverage, 5111,
     /*  70208 */     GIR_Done,
     /*  70209 */   // Label 1174: @70209
     /*  70209 */   GIM_Reject,
     /*  70210 */ // Label 1159: @70210
     /*  70210 */ GIM_Reject,
     /*  70211 */ // Label 1108: @70211
     /*  70211 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(71506),
     /*  70216 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70219 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70222 */   GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(70331), // Rule ID 14666 //
     /*  70227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70246 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  70254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70258 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70262 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70266 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70271 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70275 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70281 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70288 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70292 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70296 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70300 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70305 */     // MIs[4] LHS
     /*  70305 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70310 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70312 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70317 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  70321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  70325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  70329 */     GIR_RootConstrainSelectedInstOperands,
     /*  70330 */     // GIR_Coverage, 14666,
     /*  70330 */     GIR_EraseRootFromParent_Done,
     /*  70331 */   // Label 1176: @70331
     /*  70331 */   GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(70440), // Rule ID 14665 //
     /*  70336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70343 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70347 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70351 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70355 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70359 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  70363 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70367 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70371 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70375 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70380 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70384 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70390 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70397 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70401 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70405 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70409 */     // MIs[4] LHS
     /*  70409 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70414 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70419 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70421 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70426 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  70430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  70434 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  70438 */     GIR_RootConstrainSelectedInstOperands,
     /*  70439 */     // GIR_Coverage, 14665,
     /*  70439 */     GIR_EraseRootFromParent_Done,
     /*  70440 */   // Label 1177: @70440
     /*  70440 */   GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(70549), // Rule ID 14668 //
     /*  70445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70464 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70468 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70473 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70477 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70481 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70485 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70489 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70494 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70498 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70504 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70506 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70510 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70514 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70518 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70523 */     // MIs[4] LHS
     /*  70523 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70528 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70530 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  70539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  70543 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70547 */     GIR_RootConstrainSelectedInstOperands,
     /*  70548 */     // GIR_Coverage, 14668,
     /*  70548 */     GIR_EraseRootFromParent_Done,
     /*  70549 */   // Label 1178: @70549
     /*  70549 */   GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(70658), // Rule ID 14667 //
     /*  70554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70569 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70573 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70577 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70582 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  70586 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70590 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70594 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70598 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70603 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70607 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70613 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  70615 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  70619 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70623 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70627 */     // MIs[4] LHS
     /*  70627 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  70632 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70637 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70639 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  70648 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  70652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  70656 */     GIR_RootConstrainSelectedInstOperands,
     /*  70657 */     // GIR_Coverage, 14667,
     /*  70657 */     GIR_EraseRootFromParent_Done,
     /*  70658 */   // Label 1179: @70658
     /*  70658 */   GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(70767), // Rule ID 2511 //
     /*  70663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70686 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70691 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70696 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70700 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70704 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70708 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70712 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  70716 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70720 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70724 */     // MIs[3] LHS
     /*  70724 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  70729 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70733 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70739 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70741 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70746 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70748 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  70757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  70761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  70765 */     GIR_RootConstrainSelectedInstOperands,
     /*  70766 */     // GIR_Coverage, 2511,
     /*  70766 */     GIR_EraseRootFromParent_Done,
     /*  70767 */   // Label 1180: @70767
     /*  70767 */   GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(70876), // Rule ID 14663 //
     /*  70772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70787 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70791 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70795 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70800 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70805 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70809 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70813 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70817 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70821 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  70825 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70829 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70833 */     // MIs[3] LHS
     /*  70833 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  70838 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70842 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70848 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70850 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70855 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70857 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$RHS))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70862 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  70866 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  70870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  70874 */     GIR_RootConstrainSelectedInstOperands,
     /*  70875 */     // GIR_Coverage, 14663,
     /*  70875 */     GIR_EraseRootFromParent_Done,
     /*  70876 */   // Label 1181: @70876
     /*  70876 */   GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(70985), // Rule ID 14662 //
     /*  70881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  70892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70904 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70909 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70914 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  70918 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  70922 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  70926 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70930 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70935 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  70939 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  70943 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  70947 */     // MIs[3] LHS
     /*  70947 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  70952 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  70956 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  70962 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  70964 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  70966 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  70966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  70969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  70971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  70975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  70979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  70983 */     GIR_RootConstrainSelectedInstOperands,
     /*  70984 */     // GIR_Coverage, 14662,
     /*  70984 */     GIR_EraseRootFromParent_Done,
     /*  70985 */   // Label 1182: @70985
     /*  70985 */   GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(71094), // Rule ID 14664 //
     /*  70990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  70993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  70997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71005 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71009 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  71013 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71018 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  71027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71031 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71035 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  71039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71044 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71048 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71052 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  71056 */     // MIs[3] LHS
     /*  71056 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  71061 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  71065 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71071 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  71073 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71075 */     // (or:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$LHS), (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, immAllOnesV:{ *:[v2i64] })))  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$MHS, V128:{ *:[v2i64] }:$RHS)
     /*  71075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  71078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71080 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  71084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  71088 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  71092 */     GIR_RootConstrainSelectedInstOperands,
     /*  71093 */     // GIR_Coverage, 14664,
     /*  71093 */     GIR_EraseRootFromParent_Done,
     /*  71094 */   // Label 1183: @71094
     /*  71094 */   GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(71158), // Rule ID 14605 //
     /*  71099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  71114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71118 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71123 */     // MIs[1] imm
     /*  71123 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  71126 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  71131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71135 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71139 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  71141 */     // (or:{ *:[v2i64] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  71141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  71144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  71148 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71152 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  71156 */     GIR_RootConstrainSelectedInstOperands,
     /*  71157 */     // GIR_Coverage, 14605,
     /*  71157 */     GIR_EraseRootFromParent_Done,
     /*  71158 */   // Label 1184: @71158
     /*  71158 */   GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(71222), // Rule ID 14626 //
     /*  71163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71170 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71174 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  71178 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71182 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71187 */     // MIs[1] imm
     /*  71187 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  71190 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  71195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71199 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71203 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  71205 */     // (or:{ *:[v2i64] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), V128:{ *:[v2i64] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  71205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  71208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71210 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  71212 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71216 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  71220 */     GIR_RootConstrainSelectedInstOperands,
     /*  71221 */     // GIR_Coverage, 14626,
     /*  71221 */     GIR_EraseRootFromParent_Done,
     /*  71222 */   // Label 1185: @71222
     /*  71222 */   GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(71286), // Rule ID 2274 //
     /*  71227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71234 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71238 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71242 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  71246 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71250 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71255 */     // MIs[1] imm
     /*  71255 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  71258 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  71263 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71267 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  71269 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  71269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv2i64_shift),
     /*  71272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71274 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  71276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  71284 */     GIR_RootConstrainSelectedInstOperands,
     /*  71285 */     // GIR_Coverage, 2274,
     /*  71285 */     GIR_EraseRootFromParent_Done,
     /*  71286 */   // Label 1186: @71286
     /*  71286 */   GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(71350), // Rule ID 2333 //
     /*  71291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71298 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71302 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71306 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  71310 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71314 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71319 */     // MIs[1] imm
     /*  71319 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  71322 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /*  71327 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  71331 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  71333 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  71333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv2i64_shift),
     /*  71336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71338 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  71340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  71344 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  71348 */     GIR_RootConstrainSelectedInstOperands,
     /*  71349 */     // GIR_Coverage, 2333,
     /*  71349 */     GIR_EraseRootFromParent_Done,
     /*  71350 */   // Label 1187: @71350
     /*  71350 */   GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(71414), // Rule ID 14913 //
     /*  71355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  71378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71387 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71393 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  71395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71401 */     // (or:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$LHS)  =>  (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  71401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  71404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  71406 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  71408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71412 */     GIR_RootConstrainSelectedInstOperands,
     /*  71413 */     // GIR_Coverage, 14913,
     /*  71413 */     GIR_EraseRootFromParent_Done,
     /*  71414 */   // Label 1188: @71414
     /*  71414 */   GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(71478), // Rule ID 5109 //
     /*  71419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71430 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  71434 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71438 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  71442 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  71446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71451 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71455 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71461 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  71463 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  71465 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$RHS, immAllOnesV:{ *:[v2i64] }))  =>  (ORNv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  71465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  71468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  71470 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  71472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71476 */     GIR_RootConstrainSelectedInstOperands,
     /*  71477 */     // GIR_Coverage, 5109,
     /*  71477 */     GIR_EraseRootFromParent_Done,
     /*  71478 */   // Label 1189: @71478
     /*  71478 */   GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(71505), // Rule ID 5115 //
     /*  71483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71494 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  71498 */     // (or:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (ORRv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  71498 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  71503 */     GIR_RootConstrainSelectedInstOperands,
     /*  71504 */     // GIR_Coverage, 5115,
     /*  71504 */     GIR_Done,
     /*  71505 */   // Label 1190: @71505
     /*  71505 */   GIM_Reject,
     /*  71506 */ // Label 1175: @71506
     /*  71506 */ GIM_Reject,
     /*  71507 */ // Label 1109: @71507
     /*  71507 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(72802),
     /*  71512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71515 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71518 */   GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(71627), // Rule ID 14631 //
     /*  71523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71538 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  71550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71554 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71558 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71562 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71567 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71571 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71577 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71584 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71588 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71592 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71596 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71601 */     // MIs[4] LHS
     /*  71601 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71606 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71608 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  71608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  71611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  71621 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  71625 */     GIR_RootConstrainSelectedInstOperands,
     /*  71626 */     // GIR_Coverage, 14631,
     /*  71626 */     GIR_EraseRootFromParent_Done,
     /*  71627 */   // Label 1192: @71627
     /*  71627 */   GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(71736), // Rule ID 14630 //
     /*  71632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71643 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71647 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71651 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71655 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  71659 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71663 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71667 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71671 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71676 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71680 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71686 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71688 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71693 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71697 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71701 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71705 */     // MIs[4] LHS
     /*  71705 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71710 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71715 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71717 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  71717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  71720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  71730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  71734 */     GIR_RootConstrainSelectedInstOperands,
     /*  71735 */     // GIR_Coverage, 14630,
     /*  71735 */     GIR_EraseRootFromParent_Done,
     /*  71736 */   // Label 1193: @71736
     /*  71736 */   GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(71845), // Rule ID 14633 //
     /*  71741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71760 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71764 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71769 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71773 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71777 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71781 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71785 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71790 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71794 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71800 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71802 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71806 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71810 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71814 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71819 */     // MIs[4] LHS
     /*  71819 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71824 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71826 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  71826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  71829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  71839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71843 */     GIR_RootConstrainSelectedInstOperands,
     /*  71844 */     // GIR_Coverage, 14633,
     /*  71844 */     GIR_EraseRootFromParent_Done,
     /*  71845 */   // Label 1194: @71845
     /*  71845 */   GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(71954), // Rule ID 14632 //
     /*  71850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71865 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71869 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71878 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  71882 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  71886 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71890 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71894 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71899 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  71903 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  71909 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  71911 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  71915 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71919 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71923 */     // MIs[4] LHS
     /*  71923 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  71928 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71933 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  71935 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  71935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  71938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  71940 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  71944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  71948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  71952 */     GIR_RootConstrainSelectedInstOperands,
     /*  71953 */     // GIR_Coverage, 14632,
     /*  71953 */     GIR_EraseRootFromParent_Done,
     /*  71954 */   // Label 1195: @71954
     /*  71954 */   GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(72063), // Rule ID 2506 //
     /*  71959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  71962 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  71970 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  71974 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  71978 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  71982 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71987 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  71992 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  71996 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72000 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72004 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72008 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  72012 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72016 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72020 */     // MIs[3] LHS
     /*  72020 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  72025 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72029 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72035 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72037 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72042 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72044 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  72044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  72047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72049 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  72053 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  72057 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  72061 */     GIR_RootConstrainSelectedInstOperands,
     /*  72062 */     // GIR_Coverage, 2506,
     /*  72062 */     GIR_EraseRootFromParent_Done,
     /*  72063 */   // Label 1196: @72063
     /*  72063 */   GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(72172), // Rule ID 14628 //
     /*  72068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72083 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72087 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72091 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72096 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72109 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72113 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72117 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  72121 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72125 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72129 */     // MIs[3] LHS
     /*  72129 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  72134 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72138 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72144 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72146 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72151 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72153 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$RHS))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  72153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  72156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  72162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  72166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  72170 */     GIR_RootConstrainSelectedInstOperands,
     /*  72171 */     // GIR_Coverage, 14628,
     /*  72171 */     GIR_EraseRootFromParent_Done,
     /*  72172 */   // Label 1197: @72172
     /*  72172 */   GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(72281), // Rule ID 14627 //
     /*  72177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72192 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72196 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72200 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72205 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72210 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72214 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72218 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72222 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72226 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72231 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72235 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72239 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72243 */     // MIs[3] LHS
     /*  72243 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  72248 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72252 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72258 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72260 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72262 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  72262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  72265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72267 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  72271 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  72275 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  72279 */     GIR_RootConstrainSelectedInstOperands,
     /*  72280 */     // GIR_Coverage, 14627,
     /*  72280 */     GIR_EraseRootFromParent_Done,
     /*  72281 */   // Label 1198: @72281
     /*  72281 */   GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(72390), // Rule ID 14629 //
     /*  72286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72293 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72297 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72301 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72305 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72309 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72314 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72319 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  72323 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72327 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72331 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72335 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72340 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72344 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72348 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72352 */     // MIs[3] LHS
     /*  72352 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  72357 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  72361 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72367 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  72369 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72371 */     // (or:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$LHS), (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, immAllOnesV:{ *:[v4i16] })))  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$MHS, V64:{ *:[v4i16] }:$RHS)
     /*  72371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  72374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  72380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  72384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  72388 */     GIR_RootConstrainSelectedInstOperands,
     /*  72389 */     // GIR_Coverage, 14629,
     /*  72389 */     GIR_EraseRootFromParent_Done,
     /*  72390 */   // Label 1199: @72390
     /*  72390 */   GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(72454), // Rule ID 14597 //
     /*  72395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72398 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  72410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72419 */     // MIs[1] imm
     /*  72419 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  72422 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72427 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72431 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72435 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  72437 */     // (or:{ *:[v4i16] } (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  72437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  72440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  72444 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72448 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  72452 */     GIR_RootConstrainSelectedInstOperands,
     /*  72453 */     // GIR_Coverage, 14597,
     /*  72453 */     GIR_EraseRootFromParent_Done,
     /*  72454 */   // Label 1200: @72454
     /*  72454 */   GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(72518), // Rule ID 14618 //
     /*  72459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72466 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72470 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  72474 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72478 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72483 */     // MIs[1] imm
     /*  72483 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  72486 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72495 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72499 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  72501 */     // (or:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V64:{ *:[v4i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  72501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  72504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  72508 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  72516 */     GIR_RootConstrainSelectedInstOperands,
     /*  72517 */     // GIR_Coverage, 14618,
     /*  72517 */     GIR_EraseRootFromParent_Done,
     /*  72518 */   // Label 1201: @72518
     /*  72518 */   GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(72582), // Rule ID 2266 //
     /*  72523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72530 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  72542 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72546 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72551 */     // MIs[1] imm
     /*  72551 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  72554 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72559 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72563 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  72565 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  72565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i16_shift),
     /*  72568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72570 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  72572 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72576 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  72580 */     GIR_RootConstrainSelectedInstOperands,
     /*  72581 */     // GIR_Coverage, 2266,
     /*  72581 */     GIR_EraseRootFromParent_Done,
     /*  72582 */   // Label 1202: @72582
     /*  72582 */   GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(72646), // Rule ID 2325 //
     /*  72587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  72606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72615 */     // MIs[1] imm
     /*  72615 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  72618 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  72623 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  72627 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  72629 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  72629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i16_shift),
     /*  72632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72634 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  72636 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  72640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  72644 */     GIR_RootConstrainSelectedInstOperands,
     /*  72645 */     // GIR_Coverage, 2325,
     /*  72645 */     GIR_EraseRootFromParent_Done,
     /*  72646 */   // Label 1203: @72646
     /*  72646 */   GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(72710), // Rule ID 14908 //
     /*  72651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72670 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72674 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72683 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72689 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  72691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72695 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72697 */     // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }), V64:{ *:[v4i16] }:$LHS)  =>  (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  72697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  72700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  72702 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  72704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  72708 */     GIR_RootConstrainSelectedInstOperands,
     /*  72709 */     // GIR_Coverage, 14908,
     /*  72709 */     GIR_EraseRootFromParent_Done,
     /*  72710 */   // Label 1204: @72710
     /*  72710 */   GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(72774), // Rule ID 5104 //
     /*  72715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72722 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  72730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  72738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  72742 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72747 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  72751 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72757 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  72759 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  72761 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$RHS, immAllOnesV:{ *:[v4i16] }))  =>  (ORNv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  72761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  72764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  72766 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  72768 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  72772 */     GIR_RootConstrainSelectedInstOperands,
     /*  72773 */     // GIR_Coverage, 5104,
     /*  72773 */     GIR_EraseRootFromParent_Done,
     /*  72774 */   // Label 1205: @72774
     /*  72774 */   GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(72801), // Rule ID 5110 //
     /*  72779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72790 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  72794 */     // (or:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (ORRv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  72794 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  72799 */     GIR_RootConstrainSelectedInstOperands,
     /*  72800 */     // GIR_Coverage, 5110,
     /*  72800 */     GIR_Done,
     /*  72801 */   // Label 1206: @72801
     /*  72801 */   GIM_Reject,
     /*  72802 */ // Label 1191: @72802
     /*  72802 */ GIM_Reject,
     /*  72803 */ // Label 1110: @72803
     /*  72803 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(74098),
     /*  72808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72811 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  72814 */   GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(72923), // Rule ID 14659 //
     /*  72819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72826 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72830 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72834 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72838 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  72842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  72846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72850 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72854 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  72858 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72863 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72867 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72873 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  72875 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72880 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  72884 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72888 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72892 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72897 */     // MIs[4] LHS
     /*  72897 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  72902 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  72904 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  72904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  72907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  72909 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  72913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  72917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  72921 */     GIR_RootConstrainSelectedInstOperands,
     /*  72922 */     // GIR_Coverage, 14659,
     /*  72922 */     GIR_EraseRootFromParent_Done,
     /*  72923 */   // Label 1208: @72923
     /*  72923 */   GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(73032), // Rule ID 14658 //
     /*  72928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  72931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72935 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  72939 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72943 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72947 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  72951 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  72955 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  72959 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  72963 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  72967 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72972 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  72976 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  72982 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  72984 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  72989 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  72993 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  72997 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73001 */     // MIs[4] LHS
     /*  73001 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  73006 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73011 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73013 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  73022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  73026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  73030 */     GIR_RootConstrainSelectedInstOperands,
     /*  73031 */     // GIR_Coverage, 14658,
     /*  73031 */     GIR_EraseRootFromParent_Done,
     /*  73032 */   // Label 1209: @73032
     /*  73032 */   GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(73141), // Rule ID 14661 //
     /*  73037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73056 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73060 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73073 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73077 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73081 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73086 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73090 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73096 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  73098 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  73102 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73106 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73110 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73115 */     // MIs[4] LHS
     /*  73115 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  73120 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73122 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73127 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  73131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  73135 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  73139 */     GIR_RootConstrainSelectedInstOperands,
     /*  73140 */     // GIR_Coverage, 14661,
     /*  73140 */     GIR_EraseRootFromParent_Done,
     /*  73141 */   // Label 1210: @73141
     /*  73141 */   GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(73250), // Rule ID 14660 //
     /*  73146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73153 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73157 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73161 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73165 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73169 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73174 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73178 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73182 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73186 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73190 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73195 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73199 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73205 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  73207 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  73211 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73215 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73219 */     // MIs[4] LHS
     /*  73219 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  73224 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73229 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73231 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73236 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  73240 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  73244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  73248 */     GIR_RootConstrainSelectedInstOperands,
     /*  73249 */     // GIR_Coverage, 14660,
     /*  73249 */     GIR_EraseRootFromParent_Done,
     /*  73250 */   // Label 1211: @73250
     /*  73250 */   GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(73359), // Rule ID 2510 //
     /*  73255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73274 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73288 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73292 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73296 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73300 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73304 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  73308 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73312 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73316 */     // MIs[3] LHS
     /*  73316 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  73321 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73325 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73331 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73333 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73338 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73340 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73345 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  73349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  73353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  73357 */     GIR_RootConstrainSelectedInstOperands,
     /*  73358 */     // GIR_Coverage, 2510,
     /*  73358 */     GIR_EraseRootFromParent_Done,
     /*  73359 */   // Label 1212: @73359
     /*  73359 */   GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(73468), // Rule ID 14656 //
     /*  73364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73371 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73375 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73379 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73383 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73387 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73405 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73409 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73413 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  73417 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73421 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73425 */     // MIs[3] LHS
     /*  73425 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  73430 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73434 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73440 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73442 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73447 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73449 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$RHS))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73454 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  73458 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  73462 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  73466 */     GIR_RootConstrainSelectedInstOperands,
     /*  73467 */     // GIR_Coverage, 14656,
     /*  73467 */     GIR_EraseRootFromParent_Done,
     /*  73468 */   // Label 1213: @73468
     /*  73468 */   GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(73577), // Rule ID 14655 //
     /*  73473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73480 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73484 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73488 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73492 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73496 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73501 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73514 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73518 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73522 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73527 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73531 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73535 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73539 */     // MIs[3] LHS
     /*  73539 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  73544 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73548 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73554 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73556 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73558 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  73567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  73571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  73575 */     GIR_RootConstrainSelectedInstOperands,
     /*  73576 */     // GIR_Coverage, 14655,
     /*  73576 */     GIR_EraseRootFromParent_Done,
     /*  73577 */   // Label 1214: @73577
     /*  73577 */   GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(73686), // Rule ID 14657 //
     /*  73582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73597 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73601 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73605 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73615 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  73619 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  73623 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73627 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73631 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73636 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  73640 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73644 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73648 */     // MIs[3] LHS
     /*  73648 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  73653 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  73657 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73663 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  73665 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  73667 */     // (or:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$LHS), (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, immAllOnesV:{ *:[v4i32] })))  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$MHS, V128:{ *:[v4i32] }:$RHS)
     /*  73667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  73670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  73676 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  73680 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  73684 */     GIR_RootConstrainSelectedInstOperands,
     /*  73685 */     // GIR_Coverage, 14657,
     /*  73685 */     GIR_EraseRootFromParent_Done,
     /*  73686 */   // Label 1215: @73686
     /*  73686 */   GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(73750), // Rule ID 14603 //
     /*  73691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73698 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73702 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  73706 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73710 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73715 */     // MIs[1] imm
     /*  73715 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  73718 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  73723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73727 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73731 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  73733 */     // (or:{ *:[v4i32] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  73733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  73736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  73740 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73744 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  73748 */     GIR_RootConstrainSelectedInstOperands,
     /*  73749 */     // GIR_Coverage, 14603,
     /*  73749 */     GIR_EraseRootFromParent_Done,
     /*  73750 */   // Label 1216: @73750
     /*  73750 */   GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(73814), // Rule ID 14624 //
     /*  73755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73762 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73766 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  73770 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73774 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73779 */     // MIs[1] imm
     /*  73779 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  73782 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  73787 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73791 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73795 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  73797 */     // (or:{ *:[v4i32] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), V128:{ *:[v4i32] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  73797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  73800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  73804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73808 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  73812 */     GIR_RootConstrainSelectedInstOperands,
     /*  73813 */     // GIR_Coverage, 14624,
     /*  73813 */     GIR_EraseRootFromParent_Done,
     /*  73814 */   // Label 1217: @73814
     /*  73814 */   GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(73878), // Rule ID 2272 //
     /*  73819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73826 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73830 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  73834 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  73838 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73842 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73847 */     // MIs[1] imm
     /*  73847 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  73850 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  73855 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73859 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  73861 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  73861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv4i32_shift),
     /*  73864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73866 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  73868 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  73876 */     GIR_RootConstrainSelectedInstOperands,
     /*  73877 */     // GIR_Coverage, 2272,
     /*  73877 */     GIR_EraseRootFromParent_Done,
     /*  73878 */   // Label 1218: @73878
     /*  73878 */   GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(73942), // Rule ID 2331 //
     /*  73883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73890 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  73898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  73902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73911 */     // MIs[1] imm
     /*  73911 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  73914 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /*  73919 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  73923 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  73925 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  73925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv4i32_shift),
     /*  73928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  73930 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  73932 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  73936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  73940 */     GIR_RootConstrainSelectedInstOperands,
     /*  73941 */     // GIR_Coverage, 2331,
     /*  73941 */     GIR_EraseRootFromParent_Done,
     /*  73942 */   // Label 1219: @73942
     /*  73942 */   GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(74006), // Rule ID 14912 //
     /*  73947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  73950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73954 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  73958 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  73962 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  73966 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  73970 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73975 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  73979 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  73985 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  73987 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  73991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  73993 */     // (or:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$LHS)  =>  (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  73993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  73996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  73998 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  74000 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  74004 */     GIR_RootConstrainSelectedInstOperands,
     /*  74005 */     // GIR_Coverage, 14912,
     /*  74005 */     GIR_EraseRootFromParent_Done,
     /*  74006 */   // Label 1220: @74006
     /*  74006 */   GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(74070), // Rule ID 5108 //
     /*  74011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74022 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  74026 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74030 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  74034 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  74038 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74043 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  74047 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74053 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  74055 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  74057 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$RHS, immAllOnesV:{ *:[v4i32] }))  =>  (ORNv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  74057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  74060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  74062 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  74064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  74068 */     GIR_RootConstrainSelectedInstOperands,
     /*  74069 */     // GIR_Coverage, 5108,
     /*  74069 */     GIR_EraseRootFromParent_Done,
     /*  74070 */   // Label 1221: @74070
     /*  74070 */   GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(74097), // Rule ID 5114 //
     /*  74075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74086 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  74090 */     // (or:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (ORRv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  74090 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  74095 */     GIR_RootConstrainSelectedInstOperands,
     /*  74096 */     // GIR_Coverage, 5114,
     /*  74096 */     GIR_Done,
     /*  74097 */   // Label 1222: @74097
     /*  74097 */   GIM_Reject,
     /*  74098 */ // Label 1207: @74098
     /*  74098 */ GIM_Reject,
     /*  74099 */ // Label 1111: @74099
     /*  74099 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(75394),
     /*  74104 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74107 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74110 */   GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(74219), // Rule ID 14421 //
     /*  74115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74134 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74138 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74142 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74146 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74150 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74154 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74159 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74163 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74169 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74171 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74176 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74180 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74184 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74188 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74193 */     // MIs[4] Rd
     /*  74193 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74198 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74200 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  74209 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  74213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  74217 */     GIR_RootConstrainSelectedInstOperands,
     /*  74218 */     // GIR_Coverage, 14421,
     /*  74218 */     GIR_EraseRootFromParent_Done,
     /*  74219 */   // Label 1224: @74219
     /*  74219 */   GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(74328), // Rule ID 14420 //
     /*  74224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74231 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74235 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74239 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74243 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74247 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  74251 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74255 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74259 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74263 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74268 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74272 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74278 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74280 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74285 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74289 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74293 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74297 */     // MIs[4] Rd
     /*  74297 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74302 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74307 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74309 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74314 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  74318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  74322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  74326 */     GIR_RootConstrainSelectedInstOperands,
     /*  74327 */     // GIR_Coverage, 14420,
     /*  74327 */     GIR_EraseRootFromParent_Done,
     /*  74328 */   // Label 1225: @74328
     /*  74328 */   GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(74437), // Rule ID 14423 //
     /*  74333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74348 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74352 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74356 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  74365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74369 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74373 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74377 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74382 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74386 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74392 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74394 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74398 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74402 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74406 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74411 */     // MIs[4] Rd
     /*  74411 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74416 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74418 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74423 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  74427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  74431 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  74435 */     GIR_RootConstrainSelectedInstOperands,
     /*  74436 */     // GIR_Coverage, 14423,
     /*  74436 */     GIR_EraseRootFromParent_Done,
     /*  74437 */   // Label 1226: @74437
     /*  74437 */   GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(74546), // Rule ID 14422 //
     /*  74442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74453 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74457 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74461 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74465 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74470 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  74474 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74478 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74482 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74486 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74491 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74495 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74501 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  74503 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  74507 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74511 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74515 */     // MIs[4] Rd
     /*  74515 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  74520 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74525 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74527 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  74536 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  74540 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  74544 */     GIR_RootConstrainSelectedInstOperands,
     /*  74545 */     // GIR_Coverage, 14422,
     /*  74545 */     GIR_EraseRootFromParent_Done,
     /*  74546 */   // Label 1227: @74546
     /*  74546 */   GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(74655), // Rule ID 1611 //
     /*  74551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74570 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74574 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  74588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74592 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74596 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74600 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  74604 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74608 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74612 */     // MIs[3] Rd
     /*  74612 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  74617 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  74621 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74627 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  74629 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74634 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74636 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74641 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  74645 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  74649 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  74653 */     GIR_RootConstrainSelectedInstOperands,
     /*  74654 */     // GIR_Coverage, 1611,
     /*  74654 */     GIR_EraseRootFromParent_Done,
     /*  74655 */   // Label 1228: @74655
     /*  74655 */   GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(74764), // Rule ID 14418 //
     /*  74660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74675 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74679 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74683 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74688 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74693 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  74697 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74701 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74705 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74709 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  74713 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74717 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74721 */     // MIs[3] Rd
     /*  74721 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  74726 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  74730 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74736 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  74738 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74743 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74745 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rm))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  74754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  74758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  74762 */     GIR_RootConstrainSelectedInstOperands,
     /*  74763 */     // GIR_Coverage, 14418,
     /*  74763 */     GIR_EraseRootFromParent_Done,
     /*  74764 */   // Label 1229: @74764
     /*  74764 */   GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(74873), // Rule ID 14417 //
     /*  74769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74784 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74788 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74792 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  74806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74810 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74814 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74823 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74827 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74831 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74835 */     // MIs[3] Rd
     /*  74835 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  74840 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  74844 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74850 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  74852 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74854 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74859 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  74863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  74867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  74871 */     GIR_RootConstrainSelectedInstOperands,
     /*  74872 */     // GIR_Coverage, 14417,
     /*  74872 */     GIR_EraseRootFromParent_Done,
     /*  74873 */   // Label 1230: @74873
     /*  74873 */   GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(74982), // Rule ID 14419 //
     /*  74878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74885 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74889 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74893 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74897 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74901 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74911 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  74915 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  74919 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  74923 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74927 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74932 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  74936 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  74940 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  74944 */     // MIs[3] Rd
     /*  74944 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  74949 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  74953 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  74959 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  74961 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  74963 */     // (or:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rd), (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, immAllOnesV:{ *:[v8i8] })))  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  74963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /*  74966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  74968 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  74972 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  74976 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  74980 */     GIR_RootConstrainSelectedInstOperands,
     /*  74981 */     // GIR_Coverage, 14419,
     /*  74981 */     GIR_EraseRootFromParent_Done,
     /*  74982 */   // Label 1231: @74982
     /*  74982 */   GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(75046), // Rule ID 14593 //
     /*  74987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  74990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  74994 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  74998 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  75002 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75006 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75011 */     // MIs[1] imm
     /*  75011 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  75014 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  75019 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75023 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  75027 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  75029 */     // (or:{ *:[v8i8] } (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  75029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  75032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  75036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  75040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  75044 */     GIR_RootConstrainSelectedInstOperands,
     /*  75045 */     // GIR_Coverage, 14593,
     /*  75045 */     GIR_EraseRootFromParent_Done,
     /*  75046 */   // Label 1232: @75046
     /*  75046 */   GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(75110), // Rule ID 14614 //
     /*  75051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  75066 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75070 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75075 */     // MIs[1] imm
     /*  75075 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  75078 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  75083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75087 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  75091 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  75093 */     // (or:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V64:{ *:[v8i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  75093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  75096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75098 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  75100 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  75104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  75108 */     GIR_RootConstrainSelectedInstOperands,
     /*  75109 */     // GIR_Coverage, 14614,
     /*  75109 */     GIR_EraseRootFromParent_Done,
     /*  75110 */   // Label 1233: @75110
     /*  75110 */   GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(75174), // Rule ID 2262 //
     /*  75115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75122 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75126 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  75130 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  75134 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75138 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75143 */     // MIs[1] imm
     /*  75143 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  75146 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  75151 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  75155 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  75157 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  75157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i8_shift),
     /*  75160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75162 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  75164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  75168 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  75172 */     GIR_RootConstrainSelectedInstOperands,
     /*  75173 */     // GIR_Coverage, 2262,
     /*  75173 */     GIR_EraseRootFromParent_Done,
     /*  75174 */   // Label 1234: @75174
     /*  75174 */   GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(75238), // Rule ID 2321 //
     /*  75179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75186 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  75194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  75198 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75202 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75207 */     // MIs[1] imm
     /*  75207 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  75210 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  75215 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  75219 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  75221 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  75221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i8_shift),
     /*  75224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75226 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  75228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  75232 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  75236 */     GIR_RootConstrainSelectedInstOperands,
     /*  75237 */     // GIR_Coverage, 2321,
     /*  75237 */     GIR_EraseRootFromParent_Done,
     /*  75238 */   // Label 1235: @75238
     /*  75238 */   GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(75302), // Rule ID 14415 //
     /*  75243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75250 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75254 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75258 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75262 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  75266 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75271 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75275 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75281 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  75283 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75287 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  75289 */     // (or:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }), V64:{ *:[v8i8] }:$Rn)  =>  (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  75289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  75292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  75294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  75296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  75300 */     GIR_RootConstrainSelectedInstOperands,
     /*  75301 */     // GIR_Coverage, 14415,
     /*  75301 */     GIR_EraseRootFromParent_Done,
     /*  75302 */   // Label 1236: @75302
     /*  75302 */   GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(75366), // Rule ID 1607 //
     /*  75307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75314 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  75322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75326 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  75330 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  75334 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75339 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75343 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75349 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  75351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  75353 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, immAllOnesV:{ *:[v8i8] }))  =>  (ORNv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  75353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv8i8),
     /*  75356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  75358 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  75360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  75364 */     GIR_RootConstrainSelectedInstOperands,
     /*  75365 */     // GIR_Coverage, 1607,
     /*  75365 */     GIR_EraseRootFromParent_Done,
     /*  75366 */   // Label 1237: @75366
     /*  75366 */   GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(75393), // Rule ID 1609 //
     /*  75371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75378 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75382 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  75386 */     // (or:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ORRv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  75386 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv8i8),
     /*  75391 */     GIR_RootConstrainSelectedInstOperands,
     /*  75392 */     // GIR_Coverage, 1609,
     /*  75392 */     GIR_Done,
     /*  75393 */   // Label 1238: @75393
     /*  75393 */   GIM_Reject,
     /*  75394 */ // Label 1223: @75394
     /*  75394 */ GIM_Reject,
     /*  75395 */ // Label 1112: @75395
     /*  75395 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(76690),
     /*  75400 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75403 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75406 */   GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(75515), // Rule ID 14652 //
     /*  75411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75430 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75434 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  75438 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75442 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75446 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75450 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75455 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75459 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75465 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75467 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75472 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75476 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75480 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75484 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75489 */     // MIs[4] LHS
     /*  75489 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75494 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  75496 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  75496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  75499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75501 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  75505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  75509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  75513 */     GIR_RootConstrainSelectedInstOperands,
     /*  75514 */     // GIR_Coverage, 14652,
     /*  75514 */     GIR_EraseRootFromParent_Done,
     /*  75515 */   // Label 1240: @75515
     /*  75515 */   GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(75624), // Rule ID 14651 //
     /*  75520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75543 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  75547 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75551 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75555 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75559 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75564 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75568 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75574 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75581 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75585 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75589 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75593 */     // MIs[4] LHS
     /*  75593 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75598 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75603 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  75605 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  75605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  75608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  75614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  75618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // RHS
     /*  75622 */     GIR_RootConstrainSelectedInstOperands,
     /*  75623 */     // GIR_Coverage, 14651,
     /*  75623 */     GIR_EraseRootFromParent_Done,
     /*  75624 */   // Label 1241: @75624
     /*  75624 */   GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(75733), // Rule ID 14654 //
     /*  75629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75657 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75661 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75665 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75669 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75673 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75678 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75682 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75688 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75690 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75694 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75698 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75702 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75707 */     // MIs[4] LHS
     /*  75707 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75712 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  75714 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  75714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  75717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75719 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  75723 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // MHS
     /*  75727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  75731 */     GIR_RootConstrainSelectedInstOperands,
     /*  75732 */     // GIR_Coverage, 14654,
     /*  75732 */     GIR_EraseRootFromParent_Done,
     /*  75733 */   // Label 1242: @75733
     /*  75733 */   GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(75842), // Rule ID 14653 //
     /*  75738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75745 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75749 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75753 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75757 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75761 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75766 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  75770 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75774 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75778 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75782 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75787 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  75791 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75797 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  75799 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  75803 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75807 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75811 */     // MIs[4] LHS
     /*  75811 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  75816 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75821 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  75823 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  75823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  75826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75828 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // LHS
     /*  75832 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // MHS
     /*  75836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  75840 */     GIR_RootConstrainSelectedInstOperands,
     /*  75841 */     // GIR_Coverage, 14653,
     /*  75841 */     GIR_EraseRootFromParent_Done,
     /*  75842 */   // Label 1243: @75842
     /*  75842 */   GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(75951), // Rule ID 2509 //
     /*  75847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75866 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75870 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75875 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75880 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75884 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75888 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75892 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75896 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  75900 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  75904 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75908 */     // MIs[3] LHS
     /*  75908 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  75913 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  75917 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  75923 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  75925 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75930 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  75932 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  75932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  75935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  75937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  75941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  75945 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  75949 */     GIR_RootConstrainSelectedInstOperands,
     /*  75950 */     // GIR_Coverage, 2509,
     /*  75950 */     GIR_EraseRootFromParent_Done,
     /*  75951 */   // Label 1244: @75951
     /*  75951 */   GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(76060), // Rule ID 14649 //
     /*  75956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  75959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75963 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  75967 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75971 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  75975 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  75979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75984 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  75989 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  75993 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  75997 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76001 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76005 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  76009 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76013 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76017 */     // MIs[3] LHS
     /*  76017 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  76022 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76026 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76032 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76034 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76039 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76041 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$RHS))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  76041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  76044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  76050 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  76054 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // RHS
     /*  76058 */     GIR_RootConstrainSelectedInstOperands,
     /*  76059 */     // GIR_Coverage, 14649,
     /*  76059 */     GIR_EraseRootFromParent_Done,
     /*  76060 */   // Label 1245: @76060
     /*  76060 */   GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(76169), // Rule ID 14648 //
     /*  76065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76072 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76076 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76080 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76084 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76088 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76093 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76098 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76102 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76106 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76110 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76114 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76119 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76123 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76127 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76131 */     // MIs[3] LHS
     /*  76131 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  76136 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76140 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76146 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76148 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76150 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  76150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  76153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // LHS
     /*  76159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // MHS
     /*  76163 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  76167 */     GIR_RootConstrainSelectedInstOperands,
     /*  76168 */     // GIR_Coverage, 14648,
     /*  76168 */     GIR_EraseRootFromParent_Done,
     /*  76169 */   // Label 1246: @76169
     /*  76169 */   GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(76278), // Rule ID 14650 //
     /*  76174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76193 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76197 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76202 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76207 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  76211 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76215 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76219 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76223 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76228 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76232 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76236 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76240 */     // MIs[3] LHS
     /*  76240 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  76245 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  76249 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76255 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  76257 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76259 */     // (or:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$LHS), (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, immAllOnesV:{ *:[v8i16] })))  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$MHS, V128:{ *:[v8i16] }:$RHS)
     /*  76259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  76262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76264 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // LHS
     /*  76268 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // MHS
     /*  76272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // RHS
     /*  76276 */     GIR_RootConstrainSelectedInstOperands,
     /*  76277 */     // GIR_Coverage, 14650,
     /*  76277 */     GIR_EraseRootFromParent_Done,
     /*  76278 */   // Label 1247: @76278
     /*  76278 */   GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(76342), // Rule ID 14599 //
     /*  76283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  76298 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76307 */     // MIs[1] imm
     /*  76307 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  76310 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  76315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76319 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  76323 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  76325 */     // (or:{ *:[v8i16] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  76325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  76328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  76332 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  76336 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  76340 */     GIR_RootConstrainSelectedInstOperands,
     /*  76341 */     // GIR_Coverage, 14599,
     /*  76341 */     GIR_EraseRootFromParent_Done,
     /*  76342 */   // Label 1248: @76342
     /*  76342 */   GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(76406), // Rule ID 14620 //
     /*  76347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76354 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76358 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  76362 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76366 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76371 */     // MIs[1] imm
     /*  76371 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  76374 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  76379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76383 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  76387 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  76389 */     // (or:{ *:[v8i16] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm), V128:{ *:[v8i16] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  76389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  76392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76394 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  76396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  76400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  76404 */     GIR_RootConstrainSelectedInstOperands,
     /*  76405 */     // GIR_Coverage, 14620,
     /*  76405 */     GIR_EraseRootFromParent_Done,
     /*  76406 */   // Label 1249: @76406
     /*  76406 */   GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(76470), // Rule ID 2268 //
     /*  76411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76422 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  76426 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  76430 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76434 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76439 */     // MIs[1] imm
     /*  76439 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  76442 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  76447 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  76451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  76453 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  76453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv8i16_shift),
     /*  76456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76458 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  76460 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  76464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  76468 */     GIR_RootConstrainSelectedInstOperands,
     /*  76469 */     // GIR_Coverage, 2268,
     /*  76469 */     GIR_EraseRootFromParent_Done,
     /*  76470 */   // Label 1250: @76470
     /*  76470 */   GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(76534), // Rule ID 2327 //
     /*  76475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76482 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  76490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  76494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76498 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76503 */     // MIs[1] imm
     /*  76503 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  76506 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /*  76511 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  76515 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  76517 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  76517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv8i16_shift),
     /*  76520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76522 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  76524 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  76528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  76532 */     GIR_RootConstrainSelectedInstOperands,
     /*  76533 */     // GIR_Coverage, 2327,
     /*  76533 */     GIR_EraseRootFromParent_Done,
     /*  76534 */   // Label 1251: @76534
     /*  76534 */   GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(76598), // Rule ID 14911 //
     /*  76539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76562 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  76571 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76577 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  76579 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76583 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  76585 */     // (or:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$LHS)  =>  (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  76585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  76588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  76590 */     GIR_RootToRootCopy, /*OpIdx*/2, // LHS
     /*  76592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  76596 */     GIR_RootConstrainSelectedInstOperands,
     /*  76597 */     // GIR_Coverage, 14911,
     /*  76597 */     GIR_EraseRootFromParent_Done,
     /*  76598 */   // Label 1252: @76598
     /*  76598 */   GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(76662), // Rule ID 5107 //
     /*  76603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76610 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76614 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  76618 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76622 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  76626 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  76630 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76635 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  76639 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76645 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  76647 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  76649 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$RHS, immAllOnesV:{ *:[v8i16] }))  =>  (ORNv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  76649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  76652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  76654 */     GIR_RootToRootCopy, /*OpIdx*/1, // LHS
     /*  76656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // RHS
     /*  76660 */     GIR_RootConstrainSelectedInstOperands,
     /*  76661 */     // GIR_Coverage, 5107,
     /*  76661 */     GIR_EraseRootFromParent_Done,
     /*  76662 */   // Label 1253: @76662
     /*  76662 */   GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(76689), // Rule ID 5113 //
     /*  76667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76678 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76682 */     // (or:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (ORRv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  76682 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  76687 */     GIR_RootConstrainSelectedInstOperands,
     /*  76688 */     // GIR_Coverage, 5113,
     /*  76688 */     GIR_Done,
     /*  76689 */   // Label 1254: @76689
     /*  76689 */   GIM_Reject,
     /*  76690 */ // Label 1239: @76690
     /*  76690 */ GIM_Reject,
     /*  76691 */ // Label 1113: @76691
     /*  76691 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(77986),
     /*  76696 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76699 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76702 */   GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(76811), // Rule ID 14428 //
     /*  76707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76714 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76718 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76722 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76726 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76730 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  76734 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76738 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76742 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76746 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76751 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76755 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76761 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76763 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76768 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76772 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76776 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76780 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76785 */     // MIs[4] Rd
     /*  76785 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76790 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76792 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  76792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  76795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  76801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  76805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  76809 */     GIR_RootConstrainSelectedInstOperands,
     /*  76810 */     // GIR_Coverage, 14428,
     /*  76810 */     GIR_EraseRootFromParent_Done,
     /*  76811 */   // Label 1256: @76811
     /*  76811 */   GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(76920), // Rule ID 14427 //
     /*  76816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76839 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  76843 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76847 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76851 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76855 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76860 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76864 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76870 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76872 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76877 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76881 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76885 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76889 */     // MIs[4] Rd
     /*  76889 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  76894 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76899 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  76901 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  76901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  76904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  76906 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  76910 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  76914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  76918 */     GIR_RootConstrainSelectedInstOperands,
     /*  76919 */     // GIR_Coverage, 14427,
     /*  76919 */     GIR_EraseRootFromParent_Done,
     /*  76920 */   // Label 1257: @76920
     /*  76920 */   GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(77029), // Rule ID 14430 //
     /*  76925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  76928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  76936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76944 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76948 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76953 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  76957 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  76961 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76965 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  76969 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  76974 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  76978 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  76984 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  76986 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  76990 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  76994 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  76998 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77003 */     // MIs[4] Rd
     /*  77003 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  77008 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77010 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  77019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /*  77023 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  77027 */     GIR_RootConstrainSelectedInstOperands,
     /*  77028 */     // GIR_Coverage, 14430,
     /*  77028 */     GIR_EraseRootFromParent_Done,
     /*  77029 */   // Label 1258: @77029
     /*  77029 */   GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(77138), // Rule ID 14429 //
     /*  77034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77041 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77045 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77049 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77053 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77057 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77062 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  77066 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77070 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77074 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77078 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77083 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77087 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77093 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  77095 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  77099 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77103 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77107 */     // MIs[4] Rd
     /*  77107 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  77112 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77117 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77119 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rd
     /*  77128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Rn
     /*  77132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  77136 */     GIR_RootConstrainSelectedInstOperands,
     /*  77137 */     // GIR_Coverage, 14429,
     /*  77137 */     GIR_EraseRootFromParent_Done,
     /*  77138 */   // Label 1259: @77138
     /*  77138 */   GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(77247), // Rule ID 1612 //
     /*  77143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77158 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77162 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77166 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77171 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  77180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77184 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77188 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77192 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  77196 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77200 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77204 */     // MIs[3] Rd
     /*  77204 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  77209 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  77213 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77219 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77221 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77226 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77228 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77233 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  77237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  77241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  77245 */     GIR_RootConstrainSelectedInstOperands,
     /*  77246 */     // GIR_Coverage, 1612,
     /*  77246 */     GIR_EraseRootFromParent_Done,
     /*  77247 */   // Label 1260: @77247
     /*  77247 */   GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(77356), // Rule ID 14425 //
     /*  77252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77275 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77280 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77285 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  77289 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77293 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77297 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77301 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  77305 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77309 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77313 */     // MIs[3] Rd
     /*  77313 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  77318 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  77322 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77328 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77330 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77335 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77337 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rm))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  77346 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  77354 */     GIR_RootConstrainSelectedInstOperands,
     /*  77355 */     // GIR_Coverage, 14425,
     /*  77355 */     GIR_EraseRootFromParent_Done,
     /*  77356 */   // Label 1261: @77356
     /*  77356 */   GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(77465), // Rule ID 14424 //
     /*  77361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77384 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77389 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77394 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  77398 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77402 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77406 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77410 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77415 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77419 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77423 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77427 */     // MIs[3] Rd
     /*  77427 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  77432 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  77436 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77442 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77444 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77446 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rd
     /*  77455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  77459 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  77463 */     GIR_RootConstrainSelectedInstOperands,
     /*  77464 */     // GIR_Coverage, 14424,
     /*  77464 */     GIR_EraseRootFromParent_Done,
     /*  77465 */   // Label 1262: @77465
     /*  77465 */   GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(77574), // Rule ID 14426 //
     /*  77470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77485 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77489 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77498 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77503 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  77507 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  77511 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77515 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77519 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77524 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  77528 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77532 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77536 */     // MIs[3] Rd
     /*  77536 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  77541 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  77545 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77551 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  77553 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  77555 */     // (or:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rd), (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, immAllOnesV:{ *:[v16i8] })))  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /*  77558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77560 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rd
     /*  77564 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77568 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /*  77572 */     GIR_RootConstrainSelectedInstOperands,
     /*  77573 */     // GIR_Coverage, 14426,
     /*  77573 */     GIR_EraseRootFromParent_Done,
     /*  77574 */   // Label 1263: @77574
     /*  77574 */   GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(77638), // Rule ID 14595 //
     /*  77579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77586 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77590 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  77594 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77598 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77603 */     // MIs[1] imm
     /*  77603 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  77606 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  77611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77615 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  77619 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  77621 */     // (or:{ *:[v16i8] } (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  77621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  77624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  77628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  77636 */     GIR_RootConstrainSelectedInstOperands,
     /*  77637 */     // GIR_Coverage, 14595,
     /*  77637 */     GIR_EraseRootFromParent_Done,
     /*  77638 */   // Label 1264: @77638
     /*  77638 */   GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(77702), // Rule ID 14616 //
     /*  77643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  77658 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77662 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77667 */     // MIs[1] imm
     /*  77667 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  77670 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  77675 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77679 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  77683 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  77685 */     // (or:{ *:[v16i8] } (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm), V128:{ *:[v16i8] }:$Rd)<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  77685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  77688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /*  77692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77696 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  77700 */     GIR_RootConstrainSelectedInstOperands,
     /*  77701 */     // GIR_Coverage, 14616,
     /*  77701 */     GIR_EraseRootFromParent_Done,
     /*  77702 */   // Label 1265: @77702
     /*  77702 */   GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(77766), // Rule ID 2264 //
     /*  77707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77714 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  77722 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /*  77726 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77730 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77735 */     // MIs[1] imm
     /*  77735 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  77738 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  77743 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  77747 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  77749 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (SSRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  77749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRAv16i8_shift),
     /*  77752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77754 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  77756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  77764 */     GIR_RootConstrainSelectedInstOperands,
     /*  77765 */     // GIR_Coverage, 2264,
     /*  77765 */     GIR_EraseRootFromParent_Done,
     /*  77766 */   // Label 1266: @77766
     /*  77766 */   GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(77830), // Rule ID 2323 //
     /*  77771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77778 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  77786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /*  77790 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77794 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77799 */     // MIs[1] imm
     /*  77799 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /*  77802 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /*  77807 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_add_and_or_is_add),
     /*  77811 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  77813 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm))<<P:Predicate_add_and_or_is_add>>  =>  (USRAv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /*  77813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRAv16i8_shift),
     /*  77816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  77818 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /*  77820 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  77824 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /*  77828 */     GIR_RootConstrainSelectedInstOperands,
     /*  77829 */     // GIR_Coverage, 2323,
     /*  77829 */     GIR_EraseRootFromParent_Done,
     /*  77830 */   // Label 1267: @77830
     /*  77830 */   GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(77894), // Rule ID 14416 //
     /*  77835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77842 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  77846 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77850 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77854 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77858 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77863 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  77867 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77873 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  77875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77879 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  77881 */     // (or:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Rn)  =>  (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  77884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  77886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  77888 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  77892 */     GIR_RootConstrainSelectedInstOperands,
     /*  77893 */     // GIR_Coverage, 14416,
     /*  77893 */     GIR_EraseRootFromParent_Done,
     /*  77894 */   // Label 1268: @77894
     /*  77894 */   GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(77958), // Rule ID 1608 //
     /*  77899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77906 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  77914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  77918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  77922 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  77926 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77931 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  77935 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  77941 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  77943 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  77945 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, immAllOnesV:{ *:[v16i8] }))  =>  (ORNv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNv16i8),
     /*  77948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  77950 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  77952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /*  77956 */     GIR_RootConstrainSelectedInstOperands,
     /*  77957 */     // GIR_Coverage, 1608,
     /*  77957 */     GIR_EraseRootFromParent_Done,
     /*  77958 */   // Label 1269: @77958
     /*  77958 */   GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(77985), // Rule ID 1610 //
     /*  77963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  77966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77970 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77974 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  77978 */     // (or:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ORRv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  77978 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORRv16i8),
     /*  77983 */     GIR_RootConstrainSelectedInstOperands,
     /*  77984 */     // GIR_Coverage, 1610,
     /*  77984 */     GIR_Done,
     /*  77985 */   // Label 1270: @77985
     /*  77985 */   GIM_Reject,
     /*  77986 */ // Label 1255: @77986
     /*  77986 */ GIM_Reject,
     /*  77987 */ // Label 1114: @77987
     /*  77987 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(78018), // Rule ID 9186 //
     /*  77992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  77995 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  77998 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  78001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  78005 */   // (or:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  78005 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  78008 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  78010 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  78012 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  78014 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  78016 */   GIR_RootConstrainSelectedInstOperands,
     /*  78017 */   // GIR_Coverage, 9186,
     /*  78017 */   GIR_EraseRootFromParent_Done,
     /*  78018 */ // Label 1271: @78018
     /*  78018 */ GIM_Reject,
     /*  78019 */ // Label 1115: @78019
     /*  78019 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(78050), // Rule ID 9185 //
     /*  78024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  78027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  78030 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  78033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  78037 */   // (or:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  78037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  78040 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  78042 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  78044 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  78046 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  78048 */   GIR_RootConstrainSelectedInstOperands,
     /*  78049 */   // GIR_Coverage, 9185,
     /*  78049 */   GIR_EraseRootFromParent_Done,
     /*  78050 */ // Label 1272: @78050
     /*  78050 */ GIM_Reject,
     /*  78051 */ // Label 1116: @78051
     /*  78051 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(81516),
     /*  78056 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78059 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  78066 */   GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(78184), // Rule ID 16936 //
     /*  78071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78074 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78078 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78082 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78086 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78098 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78102 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78106 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78110 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78116 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78118 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  78122 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78126 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78130 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78134 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78138 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78144 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  78146 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  78150 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78154 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78158 */     // MIs[6] Op3
     /*  78158 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  78163 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78165 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  78168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  78174 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  78178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  78182 */     GIR_RootConstrainSelectedInstOperands,
     /*  78183 */     // GIR_Coverage, 16936,
     /*  78183 */     GIR_EraseRootFromParent_Done,
     /*  78184 */   // Label 1274: @78184
     /*  78184 */   GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(78302), // Rule ID 16938 //
     /*  78189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78192 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78196 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78200 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78204 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78208 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78212 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78216 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78220 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78224 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78228 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78234 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78236 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  78240 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78244 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78248 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78252 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78256 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78262 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  78264 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  78268 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78272 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78276 */     // MIs[6] Op3
     /*  78276 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78281 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78283 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  78286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78288 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  78292 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  78296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78300 */     GIR_RootConstrainSelectedInstOperands,
     /*  78301 */     // GIR_Coverage, 16938,
     /*  78301 */     GIR_EraseRootFromParent_Done,
     /*  78302 */   // Label 1275: @78302
     /*  78302 */   GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(78420), // Rule ID 16935 //
     /*  78307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78322 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78326 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78330 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78334 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78338 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78342 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78346 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78352 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78354 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  78358 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78362 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78366 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78370 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78374 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78380 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  78382 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  78386 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78390 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78394 */     // MIs[6] Op3
     /*  78394 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  78399 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78401 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  78404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  78410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  78414 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  78418 */     GIR_RootConstrainSelectedInstOperands,
     /*  78419 */     // GIR_Coverage, 16935,
     /*  78419 */     GIR_EraseRootFromParent_Done,
     /*  78420 */   // Label 1276: @78420
     /*  78420 */   GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(78538), // Rule ID 16937 //
     /*  78425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78428 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78432 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78436 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78440 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78444 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78448 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78452 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78456 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78460 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78464 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78470 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78472 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  78476 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78480 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78484 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78488 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78492 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78498 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  78500 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  78504 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78508 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78512 */     // MIs[6] Op3
     /*  78512 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78517 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78519 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  78522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78524 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  78528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  78532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78536 */     GIR_RootConstrainSelectedInstOperands,
     /*  78537 */     // GIR_Coverage, 16937,
     /*  78537 */     GIR_EraseRootFromParent_Done,
     /*  78538 */   // Label 1277: @78538
     /*  78538 */   GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(78656), // Rule ID 16827 //
     /*  78543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78570 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78574 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78578 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78582 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78588 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78590 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78594 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78598 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78602 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78606 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78610 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78614 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78618 */     // MIs[5] Op3
     /*  78618 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  78623 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78627 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78633 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78635 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78637 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  78646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  78650 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  78654 */     GIR_RootConstrainSelectedInstOperands,
     /*  78655 */     // GIR_Coverage, 16827,
     /*  78655 */     GIR_EraseRootFromParent_Done,
     /*  78656 */   // Label 1278: @78656
     /*  78656 */   GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(78774), // Rule ID 16832 //
     /*  78661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78676 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78692 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78696 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78700 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78706 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78708 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78712 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78716 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78720 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  78724 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78728 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78732 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78736 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78740 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78746 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78748 */     // MIs[4] Op3
     /*  78748 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78753 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78755 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  78768 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78772 */     GIR_RootConstrainSelectedInstOperands,
     /*  78773 */     // GIR_Coverage, 16832,
     /*  78773 */     GIR_EraseRootFromParent_Done,
     /*  78774 */   // Label 1279: @78774
     /*  78774 */   GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(78892), // Rule ID 16833 //
     /*  78779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78790 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78794 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78798 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78802 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78806 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78810 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78814 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78818 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78824 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78826 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78830 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78834 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78838 */     // MIs[4] Op3
     /*  78838 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  78843 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78847 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78851 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78855 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78859 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78863 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78869 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78871 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78873 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  78882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  78886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  78890 */     GIR_RootConstrainSelectedInstOperands,
     /*  78891 */     // GIR_Coverage, 16833,
     /*  78891 */     GIR_EraseRootFromParent_Done,
     /*  78892 */   // Label 1280: @78892
     /*  78892 */   GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(79010), // Rule ID 12758 //
     /*  78897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  78900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  78904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78912 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78916 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  78920 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78924 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78928 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78932 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  78936 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78942 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  78944 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  78948 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  78952 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  78956 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78960 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  78964 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  78968 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  78972 */     // MIs[5] Op3
     /*  78972 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  78977 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  78981 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  78987 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  78989 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  78991 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  78991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  78994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  78996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  79000 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  79004 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79008 */     GIR_RootConstrainSelectedInstOperands,
     /*  79009 */     // GIR_Coverage, 12758,
     /*  79009 */     GIR_EraseRootFromParent_Done,
     /*  79010 */   // Label 1281: @79010
     /*  79010 */   GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(79128), // Rule ID 16829 //
     /*  79015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79030 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79034 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79038 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79042 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79046 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79050 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79054 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79060 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79062 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79066 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79070 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79074 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79078 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  79082 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79086 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79090 */     // MIs[5] Op3
     /*  79090 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79095 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79099 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79105 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79107 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79109 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  79112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  79118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  79122 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79126 */     GIR_RootConstrainSelectedInstOperands,
     /*  79127 */     // GIR_Coverage, 16829,
     /*  79127 */     GIR_EraseRootFromParent_Done,
     /*  79128 */   // Label 1282: @79128
     /*  79128 */   GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(79246), // Rule ID 16830 //
     /*  79133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79136 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79140 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79144 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79148 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79152 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79156 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79160 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79164 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79168 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79172 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79178 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79180 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79184 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79188 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79192 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  79196 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79200 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79204 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79208 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79212 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79218 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79220 */     // MIs[4] Op3
     /*  79220 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79225 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79227 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  79230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79232 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  79236 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  79240 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79244 */     GIR_RootConstrainSelectedInstOperands,
     /*  79245 */     // GIR_Coverage, 16830,
     /*  79245 */     GIR_EraseRootFromParent_Done,
     /*  79246 */   // Label 1283: @79246
     /*  79246 */   GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(79364), // Rule ID 16831 //
     /*  79251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79262 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79266 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79270 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79274 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79278 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79282 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79286 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79290 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79296 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79298 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79302 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79306 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79310 */     // MIs[4] Op3
     /*  79310 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  79315 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  79319 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79323 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79327 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79331 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79335 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79341 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79343 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79345 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  79348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  79354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  79358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  79362 */     GIR_RootConstrainSelectedInstOperands,
     /*  79363 */     // GIR_Coverage, 16831,
     /*  79363 */     GIR_EraseRootFromParent_Done,
     /*  79364 */   // Label 1284: @79364
     /*  79364 */   GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(79482), // Rule ID 16828 //
     /*  79369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79384 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79388 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  79392 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79396 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79400 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79404 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79408 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79414 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  79416 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  79420 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79424 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79428 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79432 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  79436 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79440 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79444 */     // MIs[5] Op3
     /*  79444 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79449 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79453 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79459 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79461 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79463 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  79466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  79472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  79476 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79480 */     GIR_RootConstrainSelectedInstOperands,
     /*  79481 */     // GIR_Coverage, 16828,
     /*  79481 */     GIR_EraseRootFromParent_Done,
     /*  79482 */   // Label 1285: @79482
     /*  79482 */   GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(79600), // Rule ID 16932 //
     /*  79487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79502 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79514 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79518 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79522 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79526 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79530 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79534 */     // MIs[3] Op3
     /*  79534 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  79539 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79543 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79549 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79551 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79555 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79559 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79563 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79567 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79571 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79577 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79579 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79581 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  79590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  79594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79598 */     GIR_RootConstrainSelectedInstOperands,
     /*  79599 */     // GIR_Coverage, 16932,
     /*  79599 */     GIR_EraseRootFromParent_Done,
     /*  79600 */   // Label 1286: @79600
     /*  79600 */   GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(79718), // Rule ID 16934 //
     /*  79605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79616 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79620 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79624 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79628 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79632 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79636 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79640 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79644 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79648 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79652 */     // MIs[3] Op3
     /*  79652 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79657 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79661 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79667 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79669 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79673 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79677 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79681 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79685 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79689 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79695 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79697 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79699 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  79708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  79712 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79716 */     GIR_RootConstrainSelectedInstOperands,
     /*  79717 */     // GIR_Coverage, 16934,
     /*  79717 */     GIR_EraseRootFromParent_Done,
     /*  79718 */   // Label 1287: @79718
     /*  79718 */   GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(79836), // Rule ID 12785 //
     /*  79723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79742 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79746 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79750 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79754 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79758 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79762 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79766 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79770 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79774 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79778 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79784 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79786 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79790 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79794 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79798 */     // MIs[5] Op3
     /*  79798 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  79803 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79807 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79813 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79815 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79817 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79822 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  79826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  79830 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  79834 */     GIR_RootConstrainSelectedInstOperands,
     /*  79835 */     // GIR_Coverage, 12785,
     /*  79835 */     GIR_EraseRootFromParent_Done,
     /*  79836 */   // Label 1288: @79836
     /*  79836 */   GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(79954), // Rule ID 16933 //
     /*  79841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79856 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79860 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  79864 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79868 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79872 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79876 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  79880 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79884 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79888 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79892 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  79896 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79902 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  79904 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  79908 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79912 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79916 */     // MIs[5] Op3
     /*  79916 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  79921 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  79925 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  79931 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  79933 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  79935 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }), (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  79935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  79938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  79940 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  79944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  79948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  79952 */     GIR_RootConstrainSelectedInstOperands,
     /*  79953 */     // GIR_Coverage, 16933,
     /*  79953 */     GIR_EraseRootFromParent_Done,
     /*  79954 */   // Label 1289: @79954
     /*  79954 */   GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(80044), // Rule ID 16749 //
     /*  79959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  79962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  79966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  79970 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79974 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79978 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  79982 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  79986 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  79990 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  79994 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  79998 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80004 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80006 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80010 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80014 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80018 */     // MIs[4] Op3
     /*  80018 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80023 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80025 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  80034 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  80038 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80042 */     GIR_RootConstrainSelectedInstOperands,
     /*  80043 */     // GIR_Coverage, 16749,
     /*  80043 */     GIR_EraseRootFromParent_Done,
     /*  80044 */   // Label 1290: @80044
     /*  80044 */   GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(80134), // Rule ID 16748 //
     /*  80049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80052 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80056 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80060 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80064 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80068 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  80072 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80076 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80080 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80084 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80088 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80094 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80096 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80100 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80104 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80108 */     // MIs[4] Op3
     /*  80108 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80113 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80115 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80120 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  80124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  80128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80132 */     GIR_RootConstrainSelectedInstOperands,
     /*  80133 */     // GIR_Coverage, 16748,
     /*  80133 */     GIR_EraseRootFromParent_Done,
     /*  80134 */   // Label 1291: @80134
     /*  80134 */   GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(80224), // Rule ID 16747 //
     /*  80139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80142 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80146 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80150 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80154 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80158 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  80162 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80166 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80170 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80174 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80178 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80184 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80186 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80190 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80194 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80198 */     // MIs[4] Op3
     /*  80198 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80203 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80205 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  80214 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  80218 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80222 */     GIR_RootConstrainSelectedInstOperands,
     /*  80223 */     // GIR_Coverage, 16747,
     /*  80223 */     GIR_EraseRootFromParent_Done,
     /*  80224 */   // Label 1292: @80224
     /*  80224 */   GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(80314), // Rule ID 16746 //
     /*  80229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80236 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80240 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80244 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80248 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  80252 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80256 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80260 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80264 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80268 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80274 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  80276 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  80280 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80284 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80288 */     // MIs[4] Op3
     /*  80288 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  80293 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80295 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  80304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  80308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  80312 */     GIR_RootConstrainSelectedInstOperands,
     /*  80313 */     // GIR_Coverage, 16746,
     /*  80313 */     GIR_EraseRootFromParent_Done,
     /*  80314 */   // Label 1293: @80314
     /*  80314 */   GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(80404), // Rule ID 16743 //
     /*  80319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80334 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80338 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80342 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80346 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80350 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80354 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80358 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80362 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80366 */     // MIs[3] Op3
     /*  80366 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80371 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80375 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80381 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80383 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80385 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  80398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80402 */     GIR_RootConstrainSelectedInstOperands,
     /*  80403 */     // GIR_Coverage, 16743,
     /*  80403 */     GIR_EraseRootFromParent_Done,
     /*  80404 */   // Label 1294: @80404
     /*  80404 */   GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(80494), // Rule ID 16745 //
     /*  80409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80412 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80416 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80420 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80424 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80432 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80436 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80440 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80444 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80448 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80452 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80456 */     // MIs[3] Op3
     /*  80456 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80461 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80465 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80471 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80473 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80475 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80484 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  80488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80492 */     GIR_RootConstrainSelectedInstOperands,
     /*  80493 */     // GIR_Coverage, 16745,
     /*  80493 */     GIR_EraseRootFromParent_Done,
     /*  80494 */   // Label 1295: @80494
     /*  80494 */   GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(80584), // Rule ID 12734 //
     /*  80499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80502 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80506 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80510 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80514 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80518 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80522 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80526 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80530 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80534 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80538 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80542 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80546 */     // MIs[3] Op3
     /*  80546 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80551 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80555 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80561 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80563 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80565 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80570 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80578 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80582 */     GIR_RootConstrainSelectedInstOperands,
     /*  80583 */     // GIR_Coverage, 12734,
     /*  80583 */     GIR_EraseRootFromParent_Done,
     /*  80584 */   // Label 1296: @80584
     /*  80584 */   GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(80674), // Rule ID 16744 //
     /*  80589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80604 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80608 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80612 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80616 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80620 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80624 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  80628 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80632 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80636 */     // MIs[3] Op3
     /*  80636 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80641 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  80645 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80651 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80653 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80655 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  80658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80664 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  80668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80672 */     GIR_RootConstrainSelectedInstOperands,
     /*  80673 */     // GIR_Coverage, 16744,
     /*  80673 */     GIR_EraseRootFromParent_Done,
     /*  80674 */   // Label 1297: @80674
     /*  80674 */   GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(80764), // Rule ID 16939 //
     /*  80679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80682 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80686 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80690 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80694 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80698 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80702 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80706 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80710 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80714 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80718 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80722 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80726 */     // MIs[3] Op3
     /*  80726 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80731 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80735 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80741 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80743 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80745 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  80758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80762 */     GIR_RootConstrainSelectedInstOperands,
     /*  80763 */     // GIR_Coverage, 16939,
     /*  80763 */     GIR_EraseRootFromParent_Done,
     /*  80764 */   // Label 1298: @80764
     /*  80764 */   GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(80854), // Rule ID 16941 //
     /*  80769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80776 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80780 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80784 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80788 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80792 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80796 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80800 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80804 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80808 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80812 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80816 */     // MIs[3] Op3
     /*  80816 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  80821 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80825 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80831 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80833 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80835 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80840 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  80844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  80848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  80852 */     GIR_RootConstrainSelectedInstOperands,
     /*  80853 */     // GIR_Coverage, 16941,
     /*  80853 */     GIR_EraseRootFromParent_Done,
     /*  80854 */   // Label 1299: @80854
     /*  80854 */   GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(80944), // Rule ID 12786 //
     /*  80859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80862 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80866 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80870 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80874 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80878 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80882 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80886 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80890 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80894 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80898 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80902 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80906 */     // MIs[3] Op3
     /*  80906 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  80911 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  80915 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  80921 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  80923 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  80925 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  80925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  80928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  80930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  80934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  80938 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  80942 */     GIR_RootConstrainSelectedInstOperands,
     /*  80943 */     // GIR_Coverage, 12786,
     /*  80943 */     GIR_EraseRootFromParent_Done,
     /*  80944 */   // Label 1300: @80944
     /*  80944 */   GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(81034), // Rule ID 16940 //
     /*  80949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  80952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  80956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  80960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80968 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  80972 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  80976 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80980 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  80984 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  80988 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  80992 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  80996 */     // MIs[3] Op3
     /*  80996 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  81001 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  81005 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81011 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  81013 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  81015 */     // (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  81015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81020 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  81024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  81028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  81032 */     GIR_RootConstrainSelectedInstOperands,
     /*  81033 */     // GIR_Coverage, 16940,
     /*  81033 */     GIR_EraseRootFromParent_Done,
     /*  81034 */   // Label 1301: @81034
     /*  81034 */   GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(81124), // Rule ID 16943 //
     /*  81039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81058 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  81066 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81070 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81074 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  81078 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81084 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81086 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81090 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81094 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81098 */     // MIs[4] Op3
     /*  81098 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  81103 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  81105 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  81105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81110 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  81114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  81122 */     GIR_RootConstrainSelectedInstOperands,
     /*  81123 */     // GIR_Coverage, 16943,
     /*  81123 */     GIR_EraseRootFromParent_Done,
     /*  81124 */   // Label 1302: @81124
     /*  81124 */   GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(81214), // Rule ID 16945 //
     /*  81129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81144 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81148 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81152 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  81156 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81160 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81164 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  81168 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81174 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81176 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81180 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81184 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81188 */     // MIs[4] Op3
     /*  81188 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81193 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  81195 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  81195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81200 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  81204 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  81208 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81212 */     GIR_RootConstrainSelectedInstOperands,
     /*  81213 */     // GIR_Coverage, 16945,
     /*  81213 */     GIR_EraseRootFromParent_Done,
     /*  81214 */   // Label 1303: @81214
     /*  81214 */   GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(81304), // Rule ID 16942 //
     /*  81219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81222 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81226 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81230 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81234 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81238 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81242 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  81246 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81250 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81254 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  81258 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81264 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81266 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81270 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81274 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81278 */     // MIs[4] Op3
     /*  81278 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  81283 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  81285 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  81285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  81294 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81298 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  81302 */     GIR_RootConstrainSelectedInstOperands,
     /*  81303 */     // GIR_Coverage, 16942,
     /*  81303 */     GIR_EraseRootFromParent_Done,
     /*  81304 */   // Label 1304: @81304
     /*  81304 */   GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(81394), // Rule ID 16944 //
     /*  81309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81312 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81316 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81320 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81324 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81328 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81332 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  81336 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81340 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81344 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  81348 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81354 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81356 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  81360 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81364 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81368 */     // MIs[4] Op3
     /*  81368 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81373 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  81375 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] }), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  81375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  81384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  81388 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81392 */     GIR_RootConstrainSelectedInstOperands,
     /*  81393 */     // GIR_Coverage, 16944,
     /*  81393 */     GIR_EraseRootFromParent_Done,
     /*  81394 */   // Label 1305: @81394
     /*  81394 */   GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(81447), // Rule ID 17175 //
     /*  81399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81414 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81418 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  81422 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81428 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  81430 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  81432 */     // (or:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1)
     /*  81432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81437 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  81439 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  81443 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  81445 */     GIR_RootConstrainSelectedInstOperands,
     /*  81446 */     // GIR_Coverage, 17175,
     /*  81446 */     GIR_EraseRootFromParent_Done,
     /*  81447 */   // Label 1306: @81447
     /*  81447 */   GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(81500), // Rule ID 12880 //
     /*  81452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81455 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  81459 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81463 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  81467 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  81471 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  81475 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81481 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  81483 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  81485 */     // (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1)
     /*  81485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81490 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  81492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  81496 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  81498 */     GIR_RootConstrainSelectedInstOperands,
     /*  81499 */     // GIR_Coverage, 12880,
     /*  81499 */     GIR_EraseRootFromParent_Done,
     /*  81500 */   // Label 1307: @81500
     /*  81500 */   GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(81515), // Rule ID 8129 //
     /*  81505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  81508 */     // (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /*  81508 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  81513 */     GIR_RootConstrainSelectedInstOperands,
     /*  81514 */     // GIR_Coverage, 8129,
     /*  81514 */     GIR_Done,
     /*  81515 */   // Label 1308: @81515
     /*  81515 */   GIM_Reject,
     /*  81516 */ // Label 1273: @81516
     /*  81516 */ GIM_Reject,
     /*  81517 */ // Label 1117: @81517
     /*  81517 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(81548), // Rule ID 9184 //
     /*  81522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  81525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /*  81528 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /*  81531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  81535 */   // (or:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /*  81535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  81538 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  81540 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  81542 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  81544 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  81546 */   GIR_RootConstrainSelectedInstOperands,
     /*  81547 */   // GIR_Coverage, 9184,
     /*  81547 */   GIR_EraseRootFromParent_Done,
     /*  81548 */ // Label 1309: @81548
     /*  81548 */ GIM_Reject,
     /*  81549 */ // Label 1118: @81549
     /*  81549 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(85014),
     /*  81554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81557 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  81564 */   GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(81682), // Rule ID 16922 //
     /*  81569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81580 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81584 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81596 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81600 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81604 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81608 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81614 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81616 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81620 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81624 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81628 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81632 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81636 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81642 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81644 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81648 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81652 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81656 */     // MIs[6] Op3
     /*  81656 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  81661 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81663 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  81663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  81672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81676 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  81680 */     GIR_RootConstrainSelectedInstOperands,
     /*  81681 */     // GIR_Coverage, 16922,
     /*  81681 */     GIR_EraseRootFromParent_Done,
     /*  81682 */   // Label 1311: @81682
     /*  81682 */   GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(81800), // Rule ID 16924 //
     /*  81687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81694 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81698 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81702 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81706 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81710 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81714 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81718 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81722 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81726 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81732 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81734 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81738 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81742 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81746 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81750 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81754 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81760 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81762 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81766 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81770 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81774 */     // MIs[6] Op3
     /*  81774 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  81779 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81781 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  81781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81786 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  81790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  81794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  81798 */     GIR_RootConstrainSelectedInstOperands,
     /*  81799 */     // GIR_Coverage, 16924,
     /*  81799 */     GIR_EraseRootFromParent_Done,
     /*  81800 */   // Label 1312: @81800
     /*  81800 */   GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(81918), // Rule ID 16921 //
     /*  81805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81816 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81820 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81824 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81828 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81832 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81836 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81840 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81844 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81850 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81852 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81856 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81860 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81864 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81868 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81872 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81878 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81880 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  81884 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81888 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81892 */     // MIs[6] Op3
     /*  81892 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  81897 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  81899 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  81899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  81902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  81904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  81908 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  81912 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  81916 */     GIR_RootConstrainSelectedInstOperands,
     /*  81917 */     // GIR_Coverage, 16921,
     /*  81917 */     GIR_EraseRootFromParent_Done,
     /*  81918 */   // Label 1313: @81918
     /*  81918 */   GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(82036), // Rule ID 16923 //
     /*  81923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  81926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  81930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  81934 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81938 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81942 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  81946 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81950 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81954 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81958 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  81962 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81968 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  81970 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  81974 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  81978 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  81982 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  81986 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  81990 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  81996 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  81998 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  82002 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82006 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82010 */     // MIs[6] Op3
     /*  82010 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82015 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82017 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  82020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  82026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  82030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82034 */     GIR_RootConstrainSelectedInstOperands,
     /*  82035 */     // GIR_Coverage, 16923,
     /*  82035 */     GIR_EraseRootFromParent_Done,
     /*  82036 */   // Label 1314: @82036
     /*  82036 */   GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(82154), // Rule ID 16820 //
     /*  82041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82056 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82060 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  82064 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82068 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82072 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82076 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82080 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82086 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82088 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82092 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82096 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82100 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82104 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82108 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82112 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82116 */     // MIs[5] Op3
     /*  82116 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  82121 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82125 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82131 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82133 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82135 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  82148 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  82152 */     GIR_RootConstrainSelectedInstOperands,
     /*  82153 */     // GIR_Coverage, 16820,
     /*  82153 */     GIR_EraseRootFromParent_Done,
     /*  82154 */   // Label 1315: @82154
     /*  82154 */   GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(82272), // Rule ID 16825 //
     /*  82159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82162 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82166 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82170 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82174 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82178 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  82182 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82186 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82190 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82194 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82198 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82204 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82206 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82210 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82214 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82218 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82222 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82226 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82230 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82234 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82238 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82244 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82246 */     // MIs[4] Op3
     /*  82246 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82251 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82253 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  82266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82270 */     GIR_RootConstrainSelectedInstOperands,
     /*  82271 */     // GIR_Coverage, 16825,
     /*  82271 */     GIR_EraseRootFromParent_Done,
     /*  82272 */   // Label 1316: @82272
     /*  82272 */   GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(82390), // Rule ID 16826 //
     /*  82277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82292 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82296 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  82300 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82304 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82308 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82312 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82316 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82322 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82324 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82328 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82332 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82336 */     // MIs[4] Op3
     /*  82336 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82341 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82345 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82349 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82353 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82357 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82361 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82367 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82369 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82371 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  82384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82388 */     GIR_RootConstrainSelectedInstOperands,
     /*  82389 */     // GIR_Coverage, 16826,
     /*  82389 */     GIR_EraseRootFromParent_Done,
     /*  82390 */   // Label 1317: @82390
     /*  82390 */   GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(82508), // Rule ID 12756 //
     /*  82395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  82418 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82422 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82426 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82430 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82434 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82440 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82442 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82446 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82450 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82454 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82458 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82462 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82466 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82470 */     // MIs[5] Op3
     /*  82470 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  82475 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82479 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82485 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82487 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82489 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82498 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  82502 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  82506 */     GIR_RootConstrainSelectedInstOperands,
     /*  82507 */     // GIR_Coverage, 12756,
     /*  82507 */     GIR_EraseRootFromParent_Done,
     /*  82508 */   // Label 1318: @82508
     /*  82508 */   GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(82626), // Rule ID 16822 //
     /*  82513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82524 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82528 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82532 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82536 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82540 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82544 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82548 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82552 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82558 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82560 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82564 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82568 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82572 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82576 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82580 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82584 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82588 */     // MIs[5] Op3
     /*  82588 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  82593 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82597 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82603 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82605 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82607 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  82620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  82624 */     GIR_RootConstrainSelectedInstOperands,
     /*  82625 */     // GIR_Coverage, 16822,
     /*  82625 */     GIR_EraseRootFromParent_Done,
     /*  82626 */   // Label 1319: @82626
     /*  82626 */   GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(82744), // Rule ID 16823 //
     /*  82631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82634 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82638 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82642 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82646 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82650 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82654 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82658 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82662 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82666 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82670 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82676 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82678 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82682 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82686 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82690 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  82694 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82698 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82702 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82706 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82710 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82716 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82718 */     // MIs[4] Op3
     /*  82718 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82723 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82725 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  82738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82742 */     GIR_RootConstrainSelectedInstOperands,
     /*  82743 */     // GIR_Coverage, 16823,
     /*  82743 */     GIR_EraseRootFromParent_Done,
     /*  82744 */   // Label 1320: @82744
     /*  82744 */   GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(82862), // Rule ID 16824 //
     /*  82749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82764 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82768 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82772 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82776 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82780 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82784 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82788 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82794 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82796 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82800 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82804 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82808 */     // MIs[4] Op3
     /*  82808 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  82813 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82817 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82821 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82825 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82829 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82833 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82839 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82841 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82843 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  82852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  82856 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  82860 */     GIR_RootConstrainSelectedInstOperands,
     /*  82861 */     // GIR_Coverage, 16824,
     /*  82861 */     GIR_EraseRootFromParent_Done,
     /*  82862 */   // Label 1321: @82862
     /*  82862 */   GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(82980), // Rule ID 16821 //
     /*  82867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82882 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82886 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  82890 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82894 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82898 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82902 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  82906 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82912 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  82914 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  82918 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82922 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  82926 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82930 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  82934 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  82938 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  82942 */     // MIs[5] Op3
     /*  82942 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  82947 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  82951 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  82957 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  82959 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  82961 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  82961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  82964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  82966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  82970 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  82974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  82978 */     GIR_RootConstrainSelectedInstOperands,
     /*  82979 */     // GIR_Coverage, 16821,
     /*  82979 */     GIR_EraseRootFromParent_Done,
     /*  82980 */   // Label 1322: @82980
     /*  82980 */   GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(83098), // Rule ID 16918 //
     /*  82985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  82988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  82992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  82996 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83000 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83004 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83008 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83012 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83016 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83020 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83024 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83028 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83032 */     // MIs[3] Op3
     /*  83032 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83037 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83041 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83047 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83049 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  83053 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83057 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83061 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83065 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  83069 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83075 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  83077 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  83079 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83088 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  83092 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83096 */     GIR_RootConstrainSelectedInstOperands,
     /*  83097 */     // GIR_Coverage, 16918,
     /*  83097 */     GIR_EraseRootFromParent_Done,
     /*  83098 */   // Label 1323: @83098
     /*  83098 */   GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(83216), // Rule ID 16920 //
     /*  83103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83122 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83126 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83130 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83134 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83138 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83142 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83146 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83150 */     // MIs[3] Op3
     /*  83150 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83155 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83159 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83165 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83167 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  83171 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83175 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83179 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83183 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  83187 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83193 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  83195 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  83197 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  83210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83214 */     GIR_RootConstrainSelectedInstOperands,
     /*  83215 */     // GIR_Coverage, 16920,
     /*  83215 */     GIR_EraseRootFromParent_Done,
     /*  83216 */   // Label 1324: @83216
     /*  83216 */   GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(83334), // Rule ID 12782 //
     /*  83221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83240 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83244 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83248 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83252 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83256 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83260 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83264 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83268 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83272 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83276 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83282 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83284 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  83288 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83292 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83296 */     // MIs[5] Op3
     /*  83296 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83301 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  83305 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83311 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  83313 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  83315 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83324 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  83328 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83332 */     GIR_RootConstrainSelectedInstOperands,
     /*  83333 */     // GIR_Coverage, 12782,
     /*  83333 */     GIR_EraseRootFromParent_Done,
     /*  83334 */   // Label 1325: @83334
     /*  83334 */   GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(83452), // Rule ID 16919 //
     /*  83339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83354 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83358 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83362 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83366 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83370 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83374 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83378 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83382 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83386 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83390 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83394 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83400 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83402 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  83406 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83410 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83414 */     // MIs[5] Op3
     /*  83414 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83419 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  83423 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83429 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  83431 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  83433 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }), (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  83436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  83446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83450 */     GIR_RootConstrainSelectedInstOperands,
     /*  83451 */     // GIR_Coverage, 16919,
     /*  83451 */     GIR_EraseRootFromParent_Done,
     /*  83452 */   // Label 1326: @83452
     /*  83452 */   GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(83542), // Rule ID 16742 //
     /*  83457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83464 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83468 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83472 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  83480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83484 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83488 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83492 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83496 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83502 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83504 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83508 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83512 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83516 */     // MIs[4] Op3
     /*  83516 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83521 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83523 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  83532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  83536 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83540 */     GIR_RootConstrainSelectedInstOperands,
     /*  83541 */     // GIR_Coverage, 16742,
     /*  83541 */     GIR_EraseRootFromParent_Done,
     /*  83542 */   // Label 1327: @83542
     /*  83542 */   GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(83632), // Rule ID 16741 //
     /*  83547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83554 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83558 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83562 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83566 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  83570 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83574 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83578 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83582 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83586 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83592 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83594 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83598 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83602 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83606 */     // MIs[4] Op3
     /*  83606 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83611 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83613 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  83622 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  83626 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83630 */     GIR_RootConstrainSelectedInstOperands,
     /*  83631 */     // GIR_Coverage, 16741,
     /*  83631 */     GIR_EraseRootFromParent_Done,
     /*  83632 */   // Label 1328: @83632
     /*  83632 */   GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(83722), // Rule ID 16740 //
     /*  83637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83652 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83656 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  83660 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83664 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83668 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83672 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83676 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83682 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83684 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83688 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83692 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83696 */     // MIs[4] Op3
     /*  83696 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83701 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83703 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  83712 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  83716 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83720 */     GIR_RootConstrainSelectedInstOperands,
     /*  83721 */     // GIR_Coverage, 16740,
     /*  83721 */     GIR_EraseRootFromParent_Done,
     /*  83722 */   // Label 1329: @83722
     /*  83722 */   GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(83812), // Rule ID 16739 //
     /*  83727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83742 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83746 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  83750 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83754 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83758 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83762 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  83766 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83772 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  83774 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  83778 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83782 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83786 */     // MIs[4] Op3
     /*  83786 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  83791 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83793 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  83802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  83806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  83810 */     GIR_RootConstrainSelectedInstOperands,
     /*  83811 */     // GIR_Coverage, 16739,
     /*  83811 */     GIR_EraseRootFromParent_Done,
     /*  83812 */   // Label 1330: @83812
     /*  83812 */   GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(83902), // Rule ID 16736 //
     /*  83817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83828 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83832 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83836 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83840 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83844 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83848 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83852 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83856 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83860 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83864 */     // MIs[3] Op3
     /*  83864 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  83869 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83873 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83879 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83881 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83883 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83888 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  83892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  83896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  83900 */     GIR_RootConstrainSelectedInstOperands,
     /*  83901 */     // GIR_Coverage, 16736,
     /*  83901 */     GIR_EraseRootFromParent_Done,
     /*  83902 */   // Label 1331: @83902
     /*  83902 */   GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(83992), // Rule ID 16738 //
     /*  83907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  83910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  83914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83922 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83926 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  83930 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  83934 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  83938 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83942 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  83946 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  83950 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  83954 */     // MIs[3] Op3
     /*  83954 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  83959 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  83963 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  83969 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  83971 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  83973 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  83973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  83976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  83978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  83982 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  83986 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  83990 */     GIR_RootConstrainSelectedInstOperands,
     /*  83991 */     // GIR_Coverage, 16738,
     /*  83991 */     GIR_EraseRootFromParent_Done,
     /*  83992 */   // Label 1332: @83992
     /*  83992 */   GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(84082), // Rule ID 12732 //
     /*  83997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84008 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84012 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84016 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84020 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84024 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84028 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84032 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  84036 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84040 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84044 */     // MIs[3] Op3
     /*  84044 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  84049 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  84053 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84059 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84061 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84063 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  84066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  84072 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84076 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  84080 */     GIR_RootConstrainSelectedInstOperands,
     /*  84081 */     // GIR_Coverage, 12732,
     /*  84081 */     GIR_EraseRootFromParent_Done,
     /*  84082 */   // Label 1333: @84082
     /*  84082 */   GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(84172), // Rule ID 16737 //
     /*  84087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84098 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84102 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84106 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84110 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84114 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84118 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84122 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  84126 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84130 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84134 */     // MIs[3] Op3
     /*  84134 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  84139 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  84143 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84149 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84151 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84153 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  84156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  84162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  84170 */     GIR_RootConstrainSelectedInstOperands,
     /*  84171 */     // GIR_Coverage, 16737,
     /*  84171 */     GIR_EraseRootFromParent_Done,
     /*  84172 */   // Label 1334: @84172
     /*  84172 */   GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(84262), // Rule ID 16925 //
     /*  84177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84192 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84196 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84200 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84204 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84208 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84212 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  84216 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84220 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84224 */     // MIs[3] Op3
     /*  84224 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  84229 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84233 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84239 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84241 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84243 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  84252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  84256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  84260 */     GIR_RootConstrainSelectedInstOperands,
     /*  84261 */     // GIR_Coverage, 16925,
     /*  84261 */     GIR_EraseRootFromParent_Done,
     /*  84262 */   // Label 1335: @84262
     /*  84262 */   GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(84352), // Rule ID 16927 //
     /*  84267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84270 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84274 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84278 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84282 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84294 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84298 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84302 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  84306 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84310 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84314 */     // MIs[3] Op3
     /*  84314 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  84319 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84323 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84329 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84331 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84333 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84338 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  84342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  84346 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  84350 */     GIR_RootConstrainSelectedInstOperands,
     /*  84351 */     // GIR_Coverage, 16927,
     /*  84351 */     GIR_EraseRootFromParent_Done,
     /*  84352 */   // Label 1336: @84352
     /*  84352 */   GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(84442), // Rule ID 12783 //
     /*  84357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84360 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84364 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84368 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84372 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84380 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84384 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84388 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84392 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  84396 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84400 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84404 */     // MIs[3] Op3
     /*  84404 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  84409 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84413 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84419 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84421 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84423 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  84432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  84436 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  84440 */     GIR_RootConstrainSelectedInstOperands,
     /*  84441 */     // GIR_Coverage, 12783,
     /*  84441 */     GIR_EraseRootFromParent_Done,
     /*  84442 */   // Label 1337: @84442
     /*  84442 */   GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(84532), // Rule ID 16926 //
     /*  84447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84462 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84466 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  84470 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84474 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84478 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84482 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  84486 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84490 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84494 */     // MIs[3] Op3
     /*  84494 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  84499 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  84503 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84509 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  84511 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84513 */     // (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  84522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  84526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  84530 */     GIR_RootConstrainSelectedInstOperands,
     /*  84531 */     // GIR_Coverage, 16926,
     /*  84531 */     GIR_EraseRootFromParent_Done,
     /*  84532 */   // Label 1338: @84532
     /*  84532 */   GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(84622), // Rule ID 16929 //
     /*  84537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84540 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84544 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84548 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84552 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84564 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84568 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84572 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84576 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84582 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84584 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84588 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84592 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84596 */     // MIs[4] Op3
     /*  84596 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  84601 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84603 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  84612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  84620 */     GIR_RootConstrainSelectedInstOperands,
     /*  84621 */     // GIR_Coverage, 16929,
     /*  84621 */     GIR_EraseRootFromParent_Done,
     /*  84622 */   // Label 1339: @84622
     /*  84622 */   GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(84712), // Rule ID 16931 //
     /*  84627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84646 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84650 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84654 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84658 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84662 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84666 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84672 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84674 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84678 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84682 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84686 */     // MIs[4] Op3
     /*  84686 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  84691 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84693 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  84702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  84706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  84710 */     GIR_RootConstrainSelectedInstOperands,
     /*  84711 */     // GIR_Coverage, 16931,
     /*  84711 */     GIR_EraseRootFromParent_Done,
     /*  84712 */   // Label 1340: @84712
     /*  84712 */   GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(84802), // Rule ID 16928 //
     /*  84717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84744 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84748 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84752 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84756 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84762 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84764 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84768 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84772 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84776 */     // MIs[4] Op3
     /*  84776 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  84781 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84783 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  84792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  84796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  84800 */     GIR_RootConstrainSelectedInstOperands,
     /*  84801 */     // GIR_Coverage, 16928,
     /*  84801 */     GIR_EraseRootFromParent_Done,
     /*  84802 */   // Label 1341: @84802
     /*  84802 */   GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(84892), // Rule ID 16930 //
     /*  84807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84826 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  84830 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  84834 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84838 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84842 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  84846 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84852 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  84854 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  84858 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  84862 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84866 */     // MIs[4] Op3
     /*  84866 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  84871 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  84873 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] }), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /*  84873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  84882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  84886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  84890 */     GIR_RootConstrainSelectedInstOperands,
     /*  84891 */     // GIR_Coverage, 16930,
     /*  84891 */     GIR_EraseRootFromParent_Done,
     /*  84892 */   // Label 1342: @84892
     /*  84892 */   GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(84945), // Rule ID 17166 //
     /*  84897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  84904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84912 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84916 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  84920 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84926 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  84928 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  84930 */     // (or:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1)
     /*  84930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84935 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  84937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  84941 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  84943 */     GIR_RootConstrainSelectedInstOperands,
     /*  84944 */     // GIR_Coverage, 17166,
     /*  84944 */     GIR_EraseRootFromParent_Done,
     /*  84945 */   // Label 1343: @84945
     /*  84945 */   GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(84998), // Rule ID 12868 //
     /*  84950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  84953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  84957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  84961 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /*  84965 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /*  84969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  84973 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  84979 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  84981 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  84983 */     // (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1)
     /*  84983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  84986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  84988 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  84990 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  84994 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  84996 */     GIR_RootConstrainSelectedInstOperands,
     /*  84997 */     // GIR_Coverage, 12868,
     /*  84997 */     GIR_EraseRootFromParent_Done,
     /*  84998 */   // Label 1344: @84998
     /*  84998 */   GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(85013), // Rule ID 8128 //
     /*  85003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  85006 */     // (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /*  85006 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  85011 */     GIR_RootConstrainSelectedInstOperands,
     /*  85012 */     // GIR_Coverage, 8128,
     /*  85012 */     GIR_Done,
     /*  85013 */   // Label 1345: @85013
     /*  85013 */   GIM_Reject,
     /*  85014 */ // Label 1310: @85014
     /*  85014 */ GIM_Reject,
     /*  85015 */ // Label 1119: @85015
     /*  85015 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(85046), // Rule ID 9183 //
     /*  85020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  85023 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /*  85026 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /*  85029 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  85033 */   // (or:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /*  85033 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  85036 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  85038 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  85040 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  85042 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  85044 */   GIR_RootConstrainSelectedInstOperands,
     /*  85045 */   // GIR_Coverage, 9183,
     /*  85045 */   GIR_EraseRootFromParent_Done,
     /*  85046 */ // Label 1346: @85046
     /*  85046 */ GIM_Reject,
     /*  85047 */ // Label 1120: @85047
     /*  85047 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(88512),
     /*  85052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85055 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85058 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  85062 */   GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(85180), // Rule ID 16908 //
     /*  85067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85070 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85074 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85078 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85082 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85086 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85090 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85094 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85098 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85102 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85106 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85112 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85114 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  85118 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85122 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85126 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85130 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85134 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85140 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  85142 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  85146 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85150 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85154 */     // MIs[6] Op3
     /*  85154 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  85159 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85161 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  85164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  85170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  85174 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  85178 */     GIR_RootConstrainSelectedInstOperands,
     /*  85179 */     // GIR_Coverage, 16908,
     /*  85179 */     GIR_EraseRootFromParent_Done,
     /*  85180 */   // Label 1348: @85180
     /*  85180 */   GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(85298), // Rule ID 16910 //
     /*  85185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85196 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85200 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85204 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85208 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85212 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85216 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85220 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85224 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85230 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85232 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  85236 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85240 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85244 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85248 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85252 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85258 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  85260 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  85264 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85268 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85272 */     // MIs[6] Op3
     /*  85272 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85277 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85279 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  85282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85284 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  85288 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  85292 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85296 */     GIR_RootConstrainSelectedInstOperands,
     /*  85297 */     // GIR_Coverage, 16910,
     /*  85297 */     GIR_EraseRootFromParent_Done,
     /*  85298 */   // Label 1349: @85298
     /*  85298 */   GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(85416), // Rule ID 16907 //
     /*  85303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85314 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85318 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85330 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85334 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85338 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85342 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85348 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85350 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  85354 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85358 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85362 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85366 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85370 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85376 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  85378 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  85382 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85386 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85390 */     // MIs[6] Op3
     /*  85390 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  85395 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85397 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  85400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  85406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  85410 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  85414 */     GIR_RootConstrainSelectedInstOperands,
     /*  85415 */     // GIR_Coverage, 16907,
     /*  85415 */     GIR_EraseRootFromParent_Done,
     /*  85416 */   // Label 1350: @85416
     /*  85416 */   GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(85534), // Rule ID 16909 //
     /*  85421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85428 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85432 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85436 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85440 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85444 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85448 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85452 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85456 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85460 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85466 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85468 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  85472 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85476 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85480 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85484 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85488 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85494 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  85496 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  85500 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85504 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85508 */     // MIs[6] Op3
     /*  85508 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85513 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85515 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  85518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85520 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  85524 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  85528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85532 */     GIR_RootConstrainSelectedInstOperands,
     /*  85533 */     // GIR_Coverage, 16909,
     /*  85533 */     GIR_EraseRootFromParent_Done,
     /*  85534 */   // Label 1351: @85534
     /*  85534 */   GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(85652), // Rule ID 16813 //
     /*  85539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85542 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85546 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85550 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85554 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85558 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85562 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85566 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85570 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85574 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85578 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85584 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85586 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85590 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85594 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85598 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85602 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85606 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85610 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85614 */     // MIs[5] Op3
     /*  85614 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  85619 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85623 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85629 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85631 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85633 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  85642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  85646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  85650 */     GIR_RootConstrainSelectedInstOperands,
     /*  85651 */     // GIR_Coverage, 16813,
     /*  85651 */     GIR_EraseRootFromParent_Done,
     /*  85652 */   // Label 1352: @85652
     /*  85652 */   GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(85770), // Rule ID 16818 //
     /*  85657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85668 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85672 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85684 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85688 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85692 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85696 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85702 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85704 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85708 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85712 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85716 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  85720 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85724 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85728 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85732 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85736 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85742 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85744 */     // MIs[4] Op3
     /*  85744 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85749 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85751 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85760 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  85764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85768 */     GIR_RootConstrainSelectedInstOperands,
     /*  85769 */     // GIR_Coverage, 16818,
     /*  85769 */     GIR_EraseRootFromParent_Done,
     /*  85770 */   // Label 1353: @85770
     /*  85770 */   GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(85888), // Rule ID 16819 //
     /*  85775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85778 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85782 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85786 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85790 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85794 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85798 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85802 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85806 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85810 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85814 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85820 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85822 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85826 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85830 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85834 */     // MIs[4] Op3
     /*  85834 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  85839 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85843 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85847 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85851 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85855 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85859 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85865 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85867 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85869 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  85878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  85882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  85886 */     GIR_RootConstrainSelectedInstOperands,
     /*  85887 */     // GIR_Coverage, 16819,
     /*  85887 */     GIR_EraseRootFromParent_Done,
     /*  85888 */   // Label 1354: @85888
     /*  85888 */   GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(86006), // Rule ID 12754 //
     /*  85893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  85896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  85900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85908 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85912 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  85916 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85920 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85924 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85928 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  85932 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85938 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  85940 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  85944 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  85948 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  85952 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85956 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  85960 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  85964 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  85968 */     // MIs[5] Op3
     /*  85968 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  85973 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  85977 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  85983 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  85985 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  85987 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  85987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  85990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  85992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  85996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  86000 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86004 */     GIR_RootConstrainSelectedInstOperands,
     /*  86005 */     // GIR_Coverage, 12754,
     /*  86005 */     GIR_EraseRootFromParent_Done,
     /*  86006 */   // Label 1355: @86006
     /*  86006 */   GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(86124), // Rule ID 16815 //
     /*  86011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86014 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86018 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86022 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86026 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86030 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86034 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86038 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86042 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86046 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86050 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86056 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86058 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86062 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86066 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86070 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86074 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  86078 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86082 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86086 */     // MIs[5] Op3
     /*  86086 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86091 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86095 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86101 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86103 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86105 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  86108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86110 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  86114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  86118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86122 */     GIR_RootConstrainSelectedInstOperands,
     /*  86123 */     // GIR_Coverage, 16815,
     /*  86123 */     GIR_EraseRootFromParent_Done,
     /*  86124 */   // Label 1356: @86124
     /*  86124 */   GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(86242), // Rule ID 16816 //
     /*  86129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86144 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86148 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86152 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86156 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86160 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86164 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86168 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86174 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86176 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86180 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86184 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86188 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  86192 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86196 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86200 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86204 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86208 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86214 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86216 */     // MIs[4] Op3
     /*  86216 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86221 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86223 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  86226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  86232 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  86236 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86240 */     GIR_RootConstrainSelectedInstOperands,
     /*  86241 */     // GIR_Coverage, 16816,
     /*  86241 */     GIR_EraseRootFromParent_Done,
     /*  86242 */   // Label 1357: @86242
     /*  86242 */   GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(86360), // Rule ID 16817 //
     /*  86247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86250 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86254 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86258 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86262 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86266 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86270 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86274 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86278 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86282 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86286 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86292 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86294 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86298 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86302 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86306 */     // MIs[4] Op3
     /*  86306 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  86311 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  86315 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86319 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86323 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86327 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86331 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86337 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86339 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86341 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  86344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86346 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  86350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  86354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  86358 */     GIR_RootConstrainSelectedInstOperands,
     /*  86359 */     // GIR_Coverage, 16817,
     /*  86359 */     GIR_EraseRootFromParent_Done,
     /*  86360 */   // Label 1358: @86360
     /*  86360 */   GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(86478), // Rule ID 16814 //
     /*  86365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86384 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  86388 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86392 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86396 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86400 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86404 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86410 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  86412 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  86416 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86420 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86424 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86428 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  86432 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86436 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86440 */     // MIs[5] Op3
     /*  86440 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86445 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86449 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86455 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86457 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86459 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  86462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  86468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  86472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86476 */     GIR_RootConstrainSelectedInstOperands,
     /*  86477 */     // GIR_Coverage, 16814,
     /*  86477 */     GIR_EraseRootFromParent_Done,
     /*  86478 */   // Label 1359: @86478
     /*  86478 */   GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(86596), // Rule ID 16904 //
     /*  86483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86498 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86510 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86514 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86518 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86522 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86526 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86530 */     // MIs[3] Op3
     /*  86530 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  86535 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86539 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86545 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86547 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86551 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86555 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86559 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86563 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86567 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86573 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86575 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86577 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86582 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  86586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  86590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86594 */     GIR_RootConstrainSelectedInstOperands,
     /*  86595 */     // GIR_Coverage, 16904,
     /*  86595 */     GIR_EraseRootFromParent_Done,
     /*  86596 */   // Label 1360: @86596
     /*  86596 */   GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(86714), // Rule ID 16906 //
     /*  86601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86608 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86612 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86616 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86620 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86624 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86628 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86632 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86636 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86640 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86644 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86648 */     // MIs[3] Op3
     /*  86648 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86653 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86657 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86663 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86665 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86669 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86673 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86677 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86681 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86685 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86691 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86693 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86695 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  86704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  86708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86712 */     GIR_RootConstrainSelectedInstOperands,
     /*  86713 */     // GIR_Coverage, 16906,
     /*  86713 */     GIR_EraseRootFromParent_Done,
     /*  86714 */   // Label 1361: @86714
     /*  86714 */   GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(86832), // Rule ID 12779 //
     /*  86719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86730 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86734 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86738 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86742 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86746 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86750 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86754 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86758 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86762 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86766 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86770 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86774 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86780 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86782 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86786 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86790 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86794 */     // MIs[5] Op3
     /*  86794 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  86799 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86803 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86809 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86811 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86813 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86818 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  86822 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  86826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  86830 */     GIR_RootConstrainSelectedInstOperands,
     /*  86831 */     // GIR_Coverage, 12779,
     /*  86831 */     GIR_EraseRootFromParent_Done,
     /*  86832 */   // Label 1362: @86832
     /*  86832 */   GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(86950), // Rule ID 16905 //
     /*  86837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86840 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86844 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86848 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86852 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86856 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  86860 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86864 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86868 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86872 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  86876 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86880 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86884 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86888 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  86892 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86898 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  86900 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  86904 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86908 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86912 */     // MIs[5] Op3
     /*  86912 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  86917 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  86921 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  86927 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  86929 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  86931 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }), (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  86931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  86934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  86936 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  86940 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  86944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  86948 */     GIR_RootConstrainSelectedInstOperands,
     /*  86949 */     // GIR_Coverage, 16905,
     /*  86949 */     GIR_EraseRootFromParent_Done,
     /*  86950 */   // Label 1363: @86950
     /*  86950 */   GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(87040), // Rule ID 16735 //
     /*  86955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  86958 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  86962 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  86966 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86970 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86974 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  86978 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  86982 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  86986 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  86990 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  86994 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87000 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87002 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87006 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87010 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87014 */     // MIs[4] Op3
     /*  87014 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87019 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87021 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  87030 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  87034 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87038 */     GIR_RootConstrainSelectedInstOperands,
     /*  87039 */     // GIR_Coverage, 16735,
     /*  87039 */     GIR_EraseRootFromParent_Done,
     /*  87040 */   // Label 1364: @87040
     /*  87040 */   GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(87130), // Rule ID 16734 //
     /*  87045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87048 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87052 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87056 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87060 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87064 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  87068 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87072 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87076 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87080 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87084 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87090 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87092 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87096 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87100 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87104 */     // MIs[4] Op3
     /*  87104 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87109 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87111 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87116 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  87120 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  87124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87128 */     GIR_RootConstrainSelectedInstOperands,
     /*  87129 */     // GIR_Coverage, 16734,
     /*  87129 */     GIR_EraseRootFromParent_Done,
     /*  87130 */   // Label 1365: @87130
     /*  87130 */   GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(87220), // Rule ID 16733 //
     /*  87135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87146 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87150 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  87158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87162 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87166 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87170 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87174 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87180 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87182 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87186 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87190 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87194 */     // MIs[4] Op3
     /*  87194 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87199 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87201 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  87210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  87214 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87218 */     GIR_RootConstrainSelectedInstOperands,
     /*  87219 */     // GIR_Coverage, 16733,
     /*  87219 */     GIR_EraseRootFromParent_Done,
     /*  87220 */   // Label 1366: @87220
     /*  87220 */   GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(87310), // Rule ID 16732 //
     /*  87225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87244 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  87248 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87252 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87256 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87260 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87264 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87270 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  87272 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  87276 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87280 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87284 */     // MIs[4] Op3
     /*  87284 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  87289 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87291 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  87300 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  87304 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  87308 */     GIR_RootConstrainSelectedInstOperands,
     /*  87309 */     // GIR_Coverage, 16732,
     /*  87309 */     GIR_EraseRootFromParent_Done,
     /*  87310 */   // Label 1367: @87310
     /*  87310 */   GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(87400), // Rule ID 16729 //
     /*  87315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87326 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87330 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87334 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87338 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87342 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87346 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87350 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87354 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87358 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87362 */     // MIs[3] Op3
     /*  87362 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87367 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87371 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87377 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87379 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87381 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87386 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  87394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87398 */     GIR_RootConstrainSelectedInstOperands,
     /*  87399 */     // GIR_Coverage, 16729,
     /*  87399 */     GIR_EraseRootFromParent_Done,
     /*  87400 */   // Label 1368: @87400
     /*  87400 */   GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(87490), // Rule ID 16731 //
     /*  87405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87408 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87412 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87416 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87420 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87424 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87428 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87432 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87436 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87440 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87444 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87448 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87452 */     // MIs[3] Op3
     /*  87452 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87457 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87461 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87467 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87469 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87471 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87476 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  87484 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87488 */     GIR_RootConstrainSelectedInstOperands,
     /*  87489 */     // GIR_Coverage, 16731,
     /*  87489 */     GIR_EraseRootFromParent_Done,
     /*  87490 */   // Label 1369: @87490
     /*  87490 */   GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(87580), // Rule ID 12730 //
     /*  87495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87498 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87502 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87506 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87510 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87514 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87518 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87522 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87526 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87530 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87534 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87538 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87542 */     // MIs[3] Op3
     /*  87542 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87547 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87551 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87557 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87559 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87561 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87570 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87578 */     GIR_RootConstrainSelectedInstOperands,
     /*  87579 */     // GIR_Coverage, 12730,
     /*  87579 */     GIR_EraseRootFromParent_Done,
     /*  87580 */   // Label 1370: @87580
     /*  87580 */   GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(87670), // Rule ID 16730 //
     /*  87585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87604 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87608 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87612 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87616 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87620 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  87624 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87628 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87632 */     // MIs[3] Op3
     /*  87632 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87637 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  87641 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87647 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87649 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87651 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  87654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  87664 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87668 */     GIR_RootConstrainSelectedInstOperands,
     /*  87669 */     // GIR_Coverage, 16730,
     /*  87669 */     GIR_EraseRootFromParent_Done,
     /*  87670 */   // Label 1371: @87670
     /*  87670 */   GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(87760), // Rule ID 16911 //
     /*  87675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87686 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87690 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87702 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87706 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87710 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87714 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87718 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87722 */     // MIs[3] Op3
     /*  87722 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87727 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87731 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87737 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87739 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87741 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  87754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87758 */     GIR_RootConstrainSelectedInstOperands,
     /*  87759 */     // GIR_Coverage, 16911,
     /*  87759 */     GIR_EraseRootFromParent_Done,
     /*  87760 */   // Label 1372: @87760
     /*  87760 */   GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(87850), // Rule ID 16913 //
     /*  87765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87776 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87780 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87784 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87788 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87792 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87796 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87800 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87804 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87808 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87812 */     // MIs[3] Op3
     /*  87812 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87817 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87821 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87827 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87829 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87831 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  87840 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  87844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  87848 */     GIR_RootConstrainSelectedInstOperands,
     /*  87849 */     // GIR_Coverage, 16913,
     /*  87849 */     GIR_EraseRootFromParent_Done,
     /*  87850 */   // Label 1373: @87850
     /*  87850 */   GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(87940), // Rule ID 12780 //
     /*  87855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87866 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87870 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87874 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87878 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87882 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87886 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87890 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87894 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87898 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87902 */     // MIs[3] Op3
     /*  87902 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  87907 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  87911 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  87917 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  87919 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  87921 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  87921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  87924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  87926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  87930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  87934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  87938 */     GIR_RootConstrainSelectedInstOperands,
     /*  87939 */     // GIR_Coverage, 12780,
     /*  87939 */     GIR_EraseRootFromParent_Done,
     /*  87940 */   // Label 1374: @87940
     /*  87940 */   GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(88030), // Rule ID 16912 //
     /*  87945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  87948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  87952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  87956 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87960 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87964 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  87968 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  87972 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87976 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  87980 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  87984 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  87988 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  87992 */     // MIs[3] Op3
     /*  87992 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  87997 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  88001 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88007 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  88009 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  88011 */     // (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  88011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88016 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  88020 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  88024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  88028 */     GIR_RootConstrainSelectedInstOperands,
     /*  88029 */     // GIR_Coverage, 16912,
     /*  88029 */     GIR_EraseRootFromParent_Done,
     /*  88030 */   // Label 1375: @88030
     /*  88030 */   GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(88120), // Rule ID 16915 //
     /*  88035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88042 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88046 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88050 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88054 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88058 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88062 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88066 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88070 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  88074 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88080 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88082 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  88086 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88090 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88094 */     // MIs[4] Op3
     /*  88094 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  88099 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  88101 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  88101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88106 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  88110 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  88114 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  88118 */     GIR_RootConstrainSelectedInstOperands,
     /*  88119 */     // GIR_Coverage, 16915,
     /*  88119 */     GIR_EraseRootFromParent_Done,
     /*  88120 */   // Label 1376: @88120
     /*  88120 */   GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(88210), // Rule ID 16917 //
     /*  88125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88128 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88132 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88136 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88140 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88144 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88148 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88152 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88156 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88160 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  88164 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88170 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88172 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  88176 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88180 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88184 */     // MIs[4] Op3
     /*  88184 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  88189 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  88191 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  88191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88196 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  88200 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  88204 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  88208 */     GIR_RootConstrainSelectedInstOperands,
     /*  88209 */     // GIR_Coverage, 16917,
     /*  88209 */     GIR_EraseRootFromParent_Done,
     /*  88210 */   // Label 1377: @88210
     /*  88210 */   GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(88300), // Rule ID 16914 //
     /*  88215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88234 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88238 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88242 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88246 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88250 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  88254 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88260 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88262 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  88266 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88270 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88274 */     // MIs[4] Op3
     /*  88274 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  88279 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  88281 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  88281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  88290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  88294 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  88298 */     GIR_RootConstrainSelectedInstOperands,
     /*  88299 */     // GIR_Coverage, 16914,
     /*  88299 */     GIR_EraseRootFromParent_Done,
     /*  88300 */   // Label 1378: @88300
     /*  88300 */   GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(88390), // Rule ID 16916 //
     /*  88305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88308 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88312 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88316 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88320 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88324 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88328 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  88332 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88336 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88340 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  88344 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88350 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88352 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  88356 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88360 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88364 */     // MIs[4] Op3
     /*  88364 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  88369 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  88371 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] }), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /*  88371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  88380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  88384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  88388 */     GIR_RootConstrainSelectedInstOperands,
     /*  88389 */     // GIR_Coverage, 16916,
     /*  88389 */     GIR_EraseRootFromParent_Done,
     /*  88390 */   // Label 1379: @88390
     /*  88390 */   GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(88443), // Rule ID 17157 //
     /*  88395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88410 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88414 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  88418 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88424 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  88426 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  88428 */     // (or:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1)
     /*  88428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88433 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  88435 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  88439 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  88441 */     GIR_RootConstrainSelectedInstOperands,
     /*  88442 */     // GIR_Coverage, 17157,
     /*  88442 */     GIR_EraseRootFromParent_Done,
     /*  88443 */   // Label 1380: @88443
     /*  88443 */   GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(88496), // Rule ID 12856 //
     /*  88448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88451 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  88455 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88459 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /*  88463 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /*  88467 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  88471 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88477 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  88479 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  88481 */     // (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1)
     /*  88481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88486 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  88488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  88492 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  88494 */     GIR_RootConstrainSelectedInstOperands,
     /*  88495 */     // GIR_Coverage, 12856,
     /*  88495 */     GIR_EraseRootFromParent_Done,
     /*  88496 */   // Label 1381: @88496
     /*  88496 */   GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(88511), // Rule ID 8127 //
     /*  88501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  88504 */     // (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /*  88504 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  88509 */     GIR_RootConstrainSelectedInstOperands,
     /*  88510 */     // GIR_Coverage, 8127,
     /*  88510 */     GIR_Done,
     /*  88511 */   // Label 1382: @88511
     /*  88511 */   GIM_Reject,
     /*  88512 */ // Label 1347: @88512
     /*  88512 */ GIM_Reject,
     /*  88513 */ // Label 1121: @88513
     /*  88513 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(88544), // Rule ID 9182 //
     /*  88518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  88521 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /*  88524 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /*  88527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  88531 */   // (or:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /*  88531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /*  88534 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  88536 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  88538 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  88540 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  88542 */   GIR_RootConstrainSelectedInstOperands,
     /*  88543 */   // GIR_Coverage, 9182,
     /*  88543 */   GIR_EraseRootFromParent_Done,
     /*  88544 */ // Label 1383: @88544
     /*  88544 */ GIM_Reject,
     /*  88545 */ // Label 1122: @88545
     /*  88545 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(92010),
     /*  88550 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88553 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  88560 */   GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(88678), // Rule ID 16894 //
     /*  88565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88568 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88572 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88576 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88580 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88592 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88596 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88600 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  88604 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88610 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88612 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  88616 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88620 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88624 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88628 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  88632 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88638 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  88640 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  88644 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88648 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88652 */     // MIs[6] Op3
     /*  88652 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  88657 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  88659 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  88659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88664 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  88668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  88672 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  88676 */     GIR_RootConstrainSelectedInstOperands,
     /*  88677 */     // GIR_Coverage, 16894,
     /*  88677 */     GIR_EraseRootFromParent_Done,
     /*  88678 */   // Label 1385: @88678
     /*  88678 */   GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(88796), // Rule ID 16896 //
     /*  88683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88686 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88690 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88694 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88698 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88710 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88714 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88718 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  88722 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88728 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88730 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  88734 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88738 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88742 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88746 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  88750 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88756 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  88758 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  88762 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88766 */     GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88770 */     // MIs[6] Op3
     /*  88770 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  88775 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  88777 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  88777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/2, // Op1
     /*  88786 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  88790 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  88794 */     GIR_RootConstrainSelectedInstOperands,
     /*  88795 */     // GIR_Coverage, 16896,
     /*  88795 */     GIR_EraseRootFromParent_Done,
     /*  88796 */   // Label 1386: @88796
     /*  88796 */   GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(88914), // Rule ID 16893 //
     /*  88801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88808 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88812 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88816 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88820 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88824 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88828 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88832 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88836 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  88840 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88846 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88848 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  88852 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88856 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88860 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88864 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  88868 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88874 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  88876 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  88880 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88884 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88888 */     // MIs[6] Op3
     /*  88888 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /*  88893 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  88895 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  88895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  88898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  88900 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  88904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  88908 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op3
     /*  88912 */     GIR_RootConstrainSelectedInstOperands,
     /*  88913 */     // GIR_Coverage, 16893,
     /*  88913 */     GIR_EraseRootFromParent_Done,
     /*  88914 */   // Label 1387: @88914
     /*  88914 */   GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(89032), // Rule ID 16895 //
     /*  88919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  88922 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  88926 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  88930 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88934 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88938 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  88942 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88946 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88950 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88954 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  88958 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88964 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  88966 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
     /*  88970 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  88974 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  88978 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  88982 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  88986 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  88992 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /*  88994 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  88998 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89002 */     GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89006 */     // MIs[6] Op3
     /*  89006 */     GIM_CheckIsSameOperand, /*MI*/6, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  89011 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89013 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  89016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // Op1
     /*  89022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  89026 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  89030 */     GIR_RootConstrainSelectedInstOperands,
     /*  89031 */     // GIR_Coverage, 16895,
     /*  89031 */     GIR_EraseRootFromParent_Done,
     /*  89032 */   // Label 1388: @89032
     /*  89032 */   GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(89150), // Rule ID 16806 //
     /*  89037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89052 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89056 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  89060 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89064 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89068 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89072 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89076 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89082 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89084 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89088 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89092 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89096 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89100 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  89104 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89108 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89112 */     // MIs[5] Op3
     /*  89112 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  89117 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89121 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89127 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89129 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89131 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  89140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  89144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  89148 */     GIR_RootConstrainSelectedInstOperands,
     /*  89149 */     // GIR_Coverage, 16806,
     /*  89149 */     GIR_EraseRootFromParent_Done,
     /*  89150 */   // Label 1389: @89150
     /*  89150 */   GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(89268), // Rule ID 16811 //
     /*  89155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89166 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89170 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89174 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  89178 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89182 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89186 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89190 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89194 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89200 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89202 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89206 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89210 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89214 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  89218 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89222 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89226 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89230 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89234 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89240 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89242 */     // MIs[4] Op3
     /*  89242 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  89247 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89249 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  89258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  89262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  89266 */     GIR_RootConstrainSelectedInstOperands,
     /*  89267 */     // GIR_Coverage, 16811,
     /*  89267 */     GIR_EraseRootFromParent_Done,
     /*  89268 */   // Label 1390: @89268
     /*  89268 */   GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(89386), // Rule ID 16812 //
     /*  89273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89280 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89284 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89288 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89292 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  89296 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89300 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89304 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89308 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89312 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89318 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89320 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89324 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89328 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89332 */     // MIs[4] Op3
     /*  89332 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  89337 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  89341 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89345 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89349 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89353 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89357 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89363 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89365 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89367 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89372 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  89376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  89380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  89384 */     GIR_RootConstrainSelectedInstOperands,
     /*  89385 */     // GIR_Coverage, 16812,
     /*  89385 */     GIR_EraseRootFromParent_Done,
     /*  89386 */   // Label 1391: @89386
     /*  89386 */   GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(89504), // Rule ID 12752 //
     /*  89391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89394 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89398 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89402 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89406 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89410 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  89414 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89418 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89422 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89426 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89430 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89436 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89438 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89442 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89446 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89450 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89454 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  89458 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89462 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89466 */     // MIs[5] Op3
     /*  89466 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  89471 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89475 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89481 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89483 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89485 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  89494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  89498 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  89502 */     GIR_RootConstrainSelectedInstOperands,
     /*  89503 */     // GIR_Coverage, 12752,
     /*  89503 */     GIR_EraseRootFromParent_Done,
     /*  89504 */   // Label 1392: @89504
     /*  89504 */   GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(89622), // Rule ID 16808 //
     /*  89509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89512 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89516 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89520 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89524 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89528 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  89532 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89536 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89540 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89544 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89548 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89554 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89556 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89560 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89564 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89568 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89572 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  89576 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89580 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89584 */     // MIs[5] Op3
     /*  89584 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  89589 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89593 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89599 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89601 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89603 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  89612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op2
     /*  89616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  89620 */     GIR_RootConstrainSelectedInstOperands,
     /*  89621 */     // GIR_Coverage, 16808,
     /*  89621 */     GIR_EraseRootFromParent_Done,
     /*  89622 */   // Label 1393: @89622
     /*  89622 */   GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(89740), // Rule ID 16809 //
     /*  89627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89646 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  89650 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89654 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89658 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89662 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89666 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89672 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89674 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89678 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89682 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89686 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
     /*  89690 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89694 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89698 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89702 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89706 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89712 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89714 */     // MIs[4] Op3
     /*  89714 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  89719 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89721 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  89730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  89734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  89738 */     GIR_RootConstrainSelectedInstOperands,
     /*  89739 */     // GIR_Coverage, 16809,
     /*  89739 */     GIR_EraseRootFromParent_Done,
     /*  89740 */   // Label 1394: @89740
     /*  89740 */   GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(89858), // Rule ID 16810 //
     /*  89745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89760 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89764 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  89768 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89772 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89776 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89780 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89784 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89790 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89792 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89796 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89800 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89804 */     // MIs[4] Op3
     /*  89804 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  89809 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  89813 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89817 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89821 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89825 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89829 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89835 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89837 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89839 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  89848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  89852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  89856 */     GIR_RootConstrainSelectedInstOperands,
     /*  89857 */     // GIR_Coverage, 16810,
     /*  89857 */     GIR_EraseRootFromParent_Done,
     /*  89858 */   // Label 1395: @89858
     /*  89858 */   GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(89976), // Rule ID 16807 //
     /*  89863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89878 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89882 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  89886 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89890 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89894 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89898 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  89902 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89908 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  89910 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  89914 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89918 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89922 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89926 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /*  89930 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  89934 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  89938 */     // MIs[5] Op3
     /*  89938 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  89943 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  89947 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  89953 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  89955 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  89957 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  89957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /*  89960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  89962 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /*  89966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op2
     /*  89970 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  89974 */     GIR_RootConstrainSelectedInstOperands,
     /*  89975 */     // GIR_Coverage, 16807,
     /*  89975 */     GIR_EraseRootFromParent_Done,
     /*  89976 */   // Label 1396: @89976
     /*  89976 */   GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(90094), // Rule ID 16890 //
     /*  89981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  89984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  89988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  89992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  89996 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90000 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90004 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90008 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90012 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90016 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90020 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90024 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90028 */     // MIs[3] Op3
     /*  90028 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  90033 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90037 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90043 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90045 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  90049 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90053 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90057 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90061 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  90065 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90071 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  90073 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  90075 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  90078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90080 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  90084 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  90088 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  90092 */     GIR_RootConstrainSelectedInstOperands,
     /*  90093 */     // GIR_Coverage, 16890,
     /*  90093 */     GIR_EraseRootFromParent_Done,
     /*  90094 */   // Label 1397: @90094
     /*  90094 */   GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(90212), // Rule ID 16892 //
     /*  90099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90102 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90106 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90110 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90114 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90118 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90122 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90126 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90130 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90134 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90138 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90142 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90146 */     // MIs[3] Op3
     /*  90146 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  90151 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90155 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90161 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90163 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  90167 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90171 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90175 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90179 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  90183 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90189 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  90191 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  90193 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  90196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  90202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op2
     /*  90206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  90210 */     GIR_RootConstrainSelectedInstOperands,
     /*  90211 */     // GIR_Coverage, 16892,
     /*  90211 */     GIR_EraseRootFromParent_Done,
     /*  90212 */   // Label 1398: @90212
     /*  90212 */   GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(90330), // Rule ID 12776 //
     /*  90217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90232 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90236 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90240 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90244 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90248 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90252 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90256 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90260 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90264 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90268 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90272 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90278 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90280 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  90284 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90288 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90292 */     // MIs[5] Op3
     /*  90292 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  90297 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  90301 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90307 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  90309 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  90311 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  90314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  90320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  90324 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  90328 */     GIR_RootConstrainSelectedInstOperands,
     /*  90329 */     // GIR_Coverage, 12776,
     /*  90329 */     GIR_EraseRootFromParent_Done,
     /*  90330 */   // Label 1399: @90330
     /*  90330 */   GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(90448), // Rule ID 16891 //
     /*  90335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90346 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90350 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90354 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90358 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90362 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90366 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90370 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90374 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90378 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90382 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90386 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90390 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90396 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90398 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/2, // MIs[5]
     /*  90402 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90406 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90410 */     // MIs[5] Op3
     /*  90410 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  90415 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/2, // MIs[6]
     /*  90419 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90425 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  90427 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  90429 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }), (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  90432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90434 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  90438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  90442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  90446 */     GIR_RootConstrainSelectedInstOperands,
     /*  90447 */     // GIR_Coverage, 16891,
     /*  90447 */     GIR_EraseRootFromParent_Done,
     /*  90448 */   // Label 1400: @90448
     /*  90448 */   GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(90538), // Rule ID 16728 //
     /*  90453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90460 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90464 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90468 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90472 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  90476 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90480 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90484 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90488 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90492 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90498 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90500 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90504 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90508 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90512 */     // MIs[4] Op3
     /*  90512 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  90517 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90519 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90524 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  90528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  90532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  90536 */     GIR_RootConstrainSelectedInstOperands,
     /*  90537 */     // GIR_Coverage, 16728,
     /*  90537 */     GIR_EraseRootFromParent_Done,
     /*  90538 */   // Label 1401: @90538
     /*  90538 */   GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(90628), // Rule ID 16727 //
     /*  90543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  90566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90570 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90574 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90578 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90582 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90588 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90590 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90594 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90598 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90602 */     // MIs[4] Op3
     /*  90602 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  90607 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90609 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  90618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /*  90622 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  90626 */     GIR_RootConstrainSelectedInstOperands,
     /*  90627 */     // GIR_Coverage, 16727,
     /*  90627 */     GIR_EraseRootFromParent_Done,
     /*  90628 */   // Label 1402: @90628
     /*  90628 */   GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(90718), // Rule ID 16726 //
     /*  90633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90660 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90664 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90668 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90672 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90678 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90680 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90684 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90688 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90692 */     // MIs[4] Op3
     /*  90692 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  90697 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90699 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  90708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  90712 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  90716 */     GIR_RootConstrainSelectedInstOperands,
     /*  90717 */     // GIR_Coverage, 16726,
     /*  90717 */     GIR_EraseRootFromParent_Done,
     /*  90718 */   // Label 1403: @90718
     /*  90718 */   GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(90808), // Rule ID 16725 //
     /*  90723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90726 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90730 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90734 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90738 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90742 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  90746 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90750 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90754 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90758 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  90762 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90768 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  90770 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  90774 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90778 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90782 */     // MIs[4] Op3
     /*  90782 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  90787 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90789 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  90798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /*  90802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  90806 */     GIR_RootConstrainSelectedInstOperands,
     /*  90807 */     // GIR_Coverage, 16725,
     /*  90807 */     GIR_EraseRootFromParent_Done,
     /*  90808 */   // Label 1404: @90808
     /*  90808 */   GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(90898), // Rule ID 16722 //
     /*  90813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90816 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90820 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90824 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90828 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90840 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90844 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90848 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90852 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90856 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90860 */     // MIs[3] Op3
     /*  90860 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  90865 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90869 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90875 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90877 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90879 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90884 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  90888 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  90892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  90896 */     GIR_RootConstrainSelectedInstOperands,
     /*  90897 */     // GIR_Coverage, 16722,
     /*  90897 */     GIR_EraseRootFromParent_Done,
     /*  90898 */   // Label 1405: @90898
     /*  90898 */   GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(90988), // Rule ID 16724 //
     /*  90903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90906 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  90910 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90914 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90918 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90922 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  90926 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  90930 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  90934 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90938 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  90942 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  90946 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  90950 */     // MIs[3] Op3
     /*  90950 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  90955 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  90959 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  90965 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  90967 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  90969 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  90969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  90972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  90974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  90978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  90982 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  90986 */     GIR_RootConstrainSelectedInstOperands,
     /*  90987 */     // GIR_Coverage, 16724,
     /*  90987 */     GIR_EraseRootFromParent_Done,
     /*  90988 */   // Label 1406: @90988
     /*  90988 */   GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(91078), // Rule ID 12728 //
     /*  90993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  90996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91020 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91024 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91028 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91032 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91036 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91040 */     // MIs[3] Op3
     /*  91040 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  91045 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  91049 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91055 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91057 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91059 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  91062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  91068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  91072 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  91076 */     GIR_RootConstrainSelectedInstOperands,
     /*  91077 */     // GIR_Coverage, 12728,
     /*  91077 */     GIR_EraseRootFromParent_Done,
     /*  91078 */   // Label 1407: @91078
     /*  91078 */   GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(91168), // Rule ID 16723 //
     /*  91083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91090 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91094 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91098 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91102 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91106 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91110 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91114 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91118 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  91122 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91126 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91130 */     // MIs[3] Op3
     /*  91130 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  91135 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  91139 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91145 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91147 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91149 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /*  91152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91154 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  91158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  91162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  91166 */     GIR_RootConstrainSelectedInstOperands,
     /*  91167 */     // GIR_Coverage, 16723,
     /*  91167 */     GIR_EraseRootFromParent_Done,
     /*  91168 */   // Label 1408: @91168
     /*  91168 */   GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(91258), // Rule ID 16897 //
     /*  91173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91200 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91204 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91208 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  91212 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91216 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91220 */     // MIs[3] Op3
     /*  91220 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  91225 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  91229 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91235 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91237 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91239 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  91248 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  91252 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  91256 */     GIR_RootConstrainSelectedInstOperands,
     /*  91257 */     // GIR_Coverage, 16897,
     /*  91257 */     GIR_EraseRootFromParent_Done,
     /*  91258 */   // Label 1409: @91258
     /*  91258 */   GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(91348), // Rule ID 16899 //
     /*  91263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91278 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91286 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91290 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91294 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91298 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  91302 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91306 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91310 */     // MIs[3] Op3
     /*  91310 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  91315 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  91319 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91325 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91327 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91329 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91334 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  91338 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /*  91342 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  91346 */     GIR_RootConstrainSelectedInstOperands,
     /*  91347 */     // GIR_Coverage, 16899,
     /*  91347 */     GIR_EraseRootFromParent_Done,
     /*  91348 */   // Label 1410: @91348
     /*  91348 */   GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(91438), // Rule ID 12777 //
     /*  91353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91360 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91364 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91368 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91372 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91376 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91380 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91384 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91388 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  91392 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91396 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91400 */     // MIs[3] Op3
     /*  91400 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /*  91405 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  91409 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91415 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91417 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91419 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /*  91428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  91432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /*  91436 */     GIR_RootConstrainSelectedInstOperands,
     /*  91437 */     // GIR_Coverage, 12777,
     /*  91437 */     GIR_EraseRootFromParent_Done,
     /*  91438 */   // Label 1411: @91438
     /*  91438 */   GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(91528), // Rule ID 16898 //
     /*  91443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91454 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91458 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /*  91466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91470 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91474 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91478 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  91482 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91486 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91490 */     // MIs[3] Op3
     /*  91490 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /*  91495 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /*  91499 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91505 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  91507 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91509 */     // (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91514 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /*  91518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /*  91522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /*  91526 */     GIR_RootConstrainSelectedInstOperands,
     /*  91527 */     // GIR_Coverage, 16898,
     /*  91527 */     GIR_EraseRootFromParent_Done,
     /*  91528 */   // Label 1412: @91528
     /*  91528 */   GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(91618), // Rule ID 16901 //
     /*  91533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91536 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91540 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91544 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91548 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91552 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91556 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91560 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91564 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91568 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  91572 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91578 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91580 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91584 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91588 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91592 */     // MIs[4] Op3
     /*  91592 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  91597 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91599 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  91608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  91612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  91616 */     GIR_RootConstrainSelectedInstOperands,
     /*  91617 */     // GIR_Coverage, 16901,
     /*  91617 */     GIR_EraseRootFromParent_Done,
     /*  91618 */   // Label 1413: @91618
     /*  91618 */   GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(91708), // Rule ID 16903 //
     /*  91623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91638 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91642 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91646 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91650 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91654 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  91662 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91668 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91670 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91674 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91678 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91682 */     // MIs[4] Op3
     /*  91682 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  91687 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91689 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91694 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/2, // Op1
     /*  91698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  91702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  91706 */     GIR_RootConstrainSelectedInstOperands,
     /*  91707 */     // GIR_Coverage, 16903,
     /*  91707 */     GIR_EraseRootFromParent_Done,
     /*  91708 */   // Label 1414: @91708
     /*  91708 */   GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(91798), // Rule ID 16900 //
     /*  91713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91728 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91732 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91736 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91740 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91744 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91748 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  91752 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91758 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91760 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91764 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91768 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91772 */     // MIs[4] Op3
     /*  91772 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
     /*  91777 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91779 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  91788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  91792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /*  91796 */     GIR_RootConstrainSelectedInstOperands,
     /*  91797 */     // GIR_Coverage, 16900,
     /*  91797 */     GIR_EraseRootFromParent_Done,
     /*  91798 */   // Label 1415: @91798
     /*  91798 */   GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(91888), // Rule ID 16902 //
     /*  91803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91818 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91822 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  91826 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
     /*  91830 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91834 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91838 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /*  91842 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91848 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  91850 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  91854 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
     /*  91858 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91862 */     // MIs[4] Op3
     /*  91862 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
     /*  91867 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  91869 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] }), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /*  91869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Op1
     /*  91878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  91882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /*  91886 */     GIR_RootConstrainSelectedInstOperands,
     /*  91887 */     // GIR_Coverage, 16902,
     /*  91887 */     GIR_EraseRootFromParent_Done,
     /*  91888 */   // Label 1416: @91888
     /*  91888 */   GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(91941), // Rule ID 17148 //
     /*  91893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  91900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91908 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91912 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91916 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91922 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  91924 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  91926 */     // (or:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$op1)  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1)
     /*  91926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91931 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  91933 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  91937 */     GIR_RootToRootCopy, /*OpIdx*/2, // op1
     /*  91939 */     GIR_RootConstrainSelectedInstOperands,
     /*  91940 */     // GIR_Coverage, 17148,
     /*  91940 */     GIR_EraseRootFromParent_Done,
     /*  91941 */   // Label 1417: @91941
     /*  91941 */   GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(91994), // Rule ID 12844 //
     /*  91946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  91949 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  91953 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  91957 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /*  91961 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /*  91965 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  91969 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  91975 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /*  91977 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  91979 */     // (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1)
     /*  91979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /*  91982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  91984 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  91986 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op2
     /*  91990 */     GIR_RootToRootCopy, /*OpIdx*/1, // op1
     /*  91992 */     GIR_RootConstrainSelectedInstOperands,
     /*  91993 */     // GIR_Coverage, 12844,
     /*  91993 */     GIR_EraseRootFromParent_Done,
     /*  91994 */   // Label 1418: @91994
     /*  91994 */   GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(92009), // Rule ID 8126 //
     /*  91999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  92002 */     // (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ORR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /*  92002 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ORR_ZZZ),
     /*  92007 */     GIR_RootConstrainSelectedInstOperands,
     /*  92008 */     // GIR_Coverage, 8126,
     /*  92008 */     GIR_Done,
     /*  92009 */   // Label 1419: @92009
     /*  92009 */   GIM_Reject,
     /*  92010 */ // Label 1384: @92010
     /*  92010 */ GIM_Reject,
     /*  92011 */ // Label 1123: @92011
     /*  92011 */ GIM_Reject,
     /*  92012 */ // Label 7: @92012
     /*  92012 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1438*/ GIMT_Encode4(106465),
     /*  92023 */ /*GILLT_s32*//*Label 1420*/ GIMT_Encode4(92111),
     /*  92027 */ /*GILLT_s64*//*Label 1421*/ GIMT_Encode4(93012), GIMT_Encode4(0),
     /*  92035 */ /*GILLT_v2s32*//*Label 1422*/ GIMT_Encode4(94562),
     /*  92039 */ /*GILLT_v2s64*//*Label 1423*/ GIMT_Encode4(95275),
     /*  92043 */ /*GILLT_v4s16*//*Label 1424*/ GIMT_Encode4(95964),
     /*  92047 */ /*GILLT_v4s32*//*Label 1425*/ GIMT_Encode4(96677),
     /*  92051 */ /*GILLT_v8s8*//*Label 1426*/ GIMT_Encode4(97366),
     /*  92055 */ /*GILLT_v8s16*//*Label 1427*/ GIMT_Encode4(98082),
     /*  92059 */ /*GILLT_v16s8*//*Label 1428*/ GIMT_Encode4(98771),
     /*  92063 */ /*GILLT_nxv1s1*//*Label 1429*/ GIMT_Encode4(99463),
     /*  92067 */ /*GILLT_nxv2s1*//*Label 1430*/ GIMT_Encode4(99513), GIMT_Encode4(0), GIMT_Encode4(0),
     /*  92079 */ /*GILLT_nxv2s64*//*Label 1431*/ GIMT_Encode4(99563),
     /*  92083 */ /*GILLT_nxv4s1*//*Label 1432*/ GIMT_Encode4(101251), GIMT_Encode4(0),
     /*  92091 */ /*GILLT_nxv4s32*//*Label 1433*/ GIMT_Encode4(101301),
     /*  92095 */ /*GILLT_nxv8s1*//*Label 1434*/ GIMT_Encode4(102989),
     /*  92099 */ /*GILLT_nxv8s16*//*Label 1435*/ GIMT_Encode4(103039),
     /*  92103 */ /*GILLT_nxv16s1*//*Label 1436*/ GIMT_Encode4(104727),
     /*  92107 */ /*GILLT_nxv16s8*//*Label 1437*/ GIMT_Encode4(104777),
     /*  92111 */ // Label 1420: @92111
     /*  92111 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(93011),
     /*  92116 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  92119 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  92122 */   GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(92184), // Rule ID 14298 //
     /*  92127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  92139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92143 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92147 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92152 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  92156 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92160 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92162 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92169 */     // (xor:{ *:[i32] } (or:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92174 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92178 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92182 */     GIR_RootConstrainSelectedInstOperands,
     /*  92183 */     // GIR_Coverage, 14298,
     /*  92183 */     GIR_EraseRootFromParent_Done,
     /*  92184 */   // Label 1440: @92184
     /*  92184 */   GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(92246), // Rule ID 157 //
     /*  92189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  92201 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92205 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92209 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92214 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  92218 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92222 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92224 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92231 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92236 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92240 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92244 */     GIR_RootConstrainSelectedInstOperands,
     /*  92245 */     // GIR_Coverage, 157,
     /*  92245 */     GIR_EraseRootFromParent_Done,
     /*  92246 */   // Label 1441: @92246
     /*  92246 */   GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(92304), // Rule ID 14296 //
     /*  92251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92255 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92259 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92263 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92267 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92271 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92276 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92280 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92282 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92289 */     // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }))  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92294 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92298 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92302 */     GIR_RootConstrainSelectedInstOperands,
     /*  92303 */     // GIR_Coverage, 14296,
     /*  92303 */     GIR_EraseRootFromParent_Done,
     /*  92304 */   // Label 1442: @92304
     /*  92304 */   GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(92359), // Rule ID 14295 //
     /*  92309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92329 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92333 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92337 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92339 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92346 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rn)  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92351 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  92353 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92357 */     GIR_RootConstrainSelectedInstOperands,
     /*  92358 */     // GIR_Coverage, 14295,
     /*  92358 */     GIR_EraseRootFromParent_Done,
     /*  92359 */   // Label 1443: @92359
     /*  92359 */   GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(92417), // Rule ID 14293 //
     /*  92364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92384 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92389 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92393 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92395 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92402 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn), -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  92411 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92415 */     GIR_RootConstrainSelectedInstOperands,
     /*  92416 */     // GIR_Coverage, 14293,
     /*  92416 */     GIR_EraseRootFromParent_Done,
     /*  92417 */   // Label 1444: @92417
     /*  92417 */   GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(92475), // Rule ID 156 //
     /*  92422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92434 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92438 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92447 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92453 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92460 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift), -1:{ *:[i32] })  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92469 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92473 */     GIR_RootConstrainSelectedInstOperands,
     /*  92474 */     // GIR_Coverage, 156,
     /*  92474 */     GIR_EraseRootFromParent_Done,
     /*  92475 */   // Label 1445: @92475
     /*  92475 */   GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(92533), // Rule ID 14294 //
     /*  92480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92488 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92492 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92496 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92500 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92505 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92509 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92511 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92518 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92527 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92531 */     GIR_RootConstrainSelectedInstOperands,
     /*  92532 */     // GIR_Coverage, 14294,
     /*  92532 */     GIR_EraseRootFromParent_Done,
     /*  92533 */   // Label 1446: @92533
     /*  92533 */   GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(92588), // Rule ID 14297 //
     /*  92538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92542 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92562 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92566 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92568 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92575 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] }))  =>  (EONWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92575 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrs),
     /*  92578 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92580 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  92582 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92586 */     GIR_RootConstrainSelectedInstOperands,
     /*  92587 */     // GIR_Coverage, 14297,
     /*  92587 */     GIR_EraseRootFromParent_Done,
     /*  92588 */   // Label 1447: @92588
     /*  92588 */   GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(92625), // Rule ID 4100 //
     /*  92593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92597 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92601 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92608 */     // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, -1:{ *:[i32] })  =>  (ORNWrs:{ *:[i32] } WZR:{ *:[i32] }, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrs),
     /*  92611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92613 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  92619 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92623 */     GIR_RootConstrainSelectedInstOperands,
     /*  92624 */     // GIR_Coverage, 4100,
     /*  92624 */     GIR_EraseRootFromParent_Done,
     /*  92625 */   // Label 1448: @92625
     /*  92625 */   GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(92666), // Rule ID 132 //
     /*  92630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /*  92634 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92638 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92642 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  92646 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm32),
     /*  92650 */     // MIs[1] Operand 1
     /*  92650 */     // No operand predicates
     /*  92650 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92652 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_logical_imm32>><<X:logical_imm32_XFORM>>:$imm)  =>  (EORWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (logical_imm32_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
     /*  92652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
     /*  92655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92657 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  92659 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // imm
     /*  92664 */     GIR_RootConstrainSelectedInstOperands,
     /*  92665 */     // GIR_Coverage, 132,
     /*  92665 */     GIR_EraseRootFromParent_Done,
     /*  92666 */   // Label 1449: @92666
     /*  92666 */   GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(92699), // Rule ID 14305 //
     /*  92671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92675 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92686 */     // (xor:{ *:[i32] } logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift, GPR32:{ *:[i32] }:$Rn)  =>  (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
     /*  92689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92691 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  92693 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92697 */     GIR_RootConstrainSelectedInstOperands,
     /*  92698 */     // GIR_Coverage, 14305,
     /*  92698 */     GIR_EraseRootFromParent_Done,
     /*  92699 */   // Label 1450: @92699
     /*  92699 */   GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(92759), // Rule ID 153 //
     /*  92704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92712 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  92716 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92724 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92729 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92734 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  92738 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92742 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92744 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_or_disjoint>>, -1:{ *:[i32] })  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  92744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  92747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  92757 */     GIR_RootConstrainSelectedInstOperands,
     /*  92758 */     // GIR_Coverage, 153,
     /*  92758 */     GIR_EraseRootFromParent_Done,
     /*  92759 */   // Label 1451: @92759
     /*  92759 */   GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(92792), // Rule ID 162 //
     /*  92764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92768 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg32),
     /*  92779 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)  =>  (EORWrs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, logical_shifted_reg32:{ *:[i32] }:$Rm_and_shift)
     /*  92779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORWrs),
     /*  92782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92784 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  92786 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  92790 */     GIR_RootConstrainSelectedInstOperands,
     /*  92791 */     // GIR_Coverage, 162,
     /*  92791 */     GIR_EraseRootFromParent_Done,
     /*  92792 */   // Label 1452: @92792
     /*  92792 */   GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(92845), // Rule ID 14289 //
     /*  92797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92809 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92813 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92817 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92822 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92826 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92830 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92832 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }), GPR32:{ *:[i32] }:$Rm)  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  92832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  92835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92837 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  92843 */     GIR_RootConstrainSelectedInstOperands,
     /*  92844 */     // GIR_Coverage, 14289,
     /*  92844 */     GIR_EraseRootFromParent_Done,
     /*  92845 */   // Label 1453: @92845
     /*  92845 */   GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(92901), // Rule ID 152 //
     /*  92850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  92858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92866 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92870 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92875 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92880 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92884 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92886 */     // (xor:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm), -1:{ *:[i32] })  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  92886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  92889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  92899 */     GIR_RootConstrainSelectedInstOperands,
     /*  92900 */     // GIR_Coverage, 152,
     /*  92900 */     GIR_EraseRootFromParent_Done,
     /*  92901 */   // Label 1454: @92901
     /*  92901 */   GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(92954), // Rule ID 14290 //
     /*  92906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92910 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  92918 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  92922 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  92926 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  92930 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92935 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  92939 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  92941 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, -1:{ *:[i32] }))  =>  (EONWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  92941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONWrr),
     /*  92944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92946 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  92950 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  92952 */     GIR_RootConstrainSelectedInstOperands,
     /*  92953 */     // GIR_Coverage, 14290,
     /*  92953 */     GIR_EraseRootFromParent_Done,
     /*  92954 */   // Label 1455: @92954
     /*  92954 */   GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(92986), // Rule ID 4098 //
     /*  92959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92963 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92967 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  92971 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] })  =>  (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm)
     /*  92971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /*  92974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  92976 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  92982 */     GIR_RootToRootCopy, /*OpIdx*/1, // Wm
     /*  92984 */     GIR_RootConstrainSelectedInstOperands,
     /*  92985 */     // GIR_Coverage, 4098,
     /*  92985 */     GIR_EraseRootFromParent_Done,
     /*  92986 */   // Label 1456: @92986
     /*  92986 */   GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(93010), // Rule ID 160 //
     /*  92991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92995 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  92999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /*  93003 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (EORWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /*  93003 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORWrr),
     /*  93008 */     GIR_RootConstrainSelectedInstOperands,
     /*  93009 */     // GIR_Coverage, 160,
     /*  93009 */     GIR_Done,
     /*  93010 */   // Label 1457: @93010
     /*  93010 */   GIM_Reject,
     /*  93011 */ // Label 1439: @93011
     /*  93011 */ GIM_Reject,
     /*  93012 */ // Label 1421: @93012
     /*  93012 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(94561),
     /*  93017 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  93020 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  93023 */   GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(93085), // Rule ID 14304 //
     /*  93028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93032 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93036 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93040 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93044 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93048 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93053 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  93057 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93061 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93063 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93070 */     // (xor:{ *:[i64] } (or:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  93079 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93083 */     GIR_RootConstrainSelectedInstOperands,
     /*  93084 */     // GIR_Coverage, 14304,
     /*  93084 */     GIR_EraseRootFromParent_Done,
     /*  93085 */   // Label 1459: @93085
     /*  93085 */   GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(93147), // Rule ID 159 //
     /*  93090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93094 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93098 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93102 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93106 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93110 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93115 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  93119 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93123 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93125 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93132 */     // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93141 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93145 */     GIR_RootConstrainSelectedInstOperands,
     /*  93146 */     // GIR_Coverage, 159,
     /*  93146 */     GIR_EraseRootFromParent_Done,
     /*  93147 */   // Label 1460: @93147
     /*  93147 */   GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(93205), // Rule ID 14302 //
     /*  93152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93172 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93177 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93181 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93183 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93190 */     // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }))  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93199 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93203 */     GIR_RootConstrainSelectedInstOperands,
     /*  93204 */     // GIR_Coverage, 14302,
     /*  93204 */     GIR_EraseRootFromParent_Done,
     /*  93205 */   // Label 1461: @93205
     /*  93205 */   GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(93260), // Rule ID 14301 //
     /*  93210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93214 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93218 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93222 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93226 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93230 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93234 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93238 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93240 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93247 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn)  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  93254 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93258 */     GIR_RootConstrainSelectedInstOperands,
     /*  93259 */     // GIR_Coverage, 14301,
     /*  93259 */     GIR_EraseRootFromParent_Done,
     /*  93260 */   // Label 1462: @93260
     /*  93260 */   GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(93318), // Rule ID 14299 //
     /*  93265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93273 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93277 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93281 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93285 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93290 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93294 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93296 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93303 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn), -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  93312 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93316 */     GIR_RootConstrainSelectedInstOperands,
     /*  93317 */     // GIR_Coverage, 14299,
     /*  93317 */     GIR_EraseRootFromParent_Done,
     /*  93318 */   // Label 1463: @93318
     /*  93318 */   GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(93376), // Rule ID 158 //
     /*  93323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93327 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93331 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93335 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93339 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93343 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93348 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93352 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93354 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93361 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift), -1:{ *:[i64] })  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93370 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93374 */     GIR_RootConstrainSelectedInstOperands,
     /*  93375 */     // GIR_Coverage, 158,
     /*  93375 */     GIR_EraseRootFromParent_Done,
     /*  93376 */   // Label 1464: @93376
     /*  93376 */   GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(93434), // Rule ID 14300 //
     /*  93381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93385 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93389 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93393 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93397 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93406 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93410 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93412 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93419 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93428 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93432 */     GIR_RootConstrainSelectedInstOperands,
     /*  93433 */     // GIR_Coverage, 14300,
     /*  93433 */     GIR_EraseRootFromParent_Done,
     /*  93434 */   // Label 1465: @93434
     /*  93434 */   GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(93489), // Rule ID 14303 //
     /*  93439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93443 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93447 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93451 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93455 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93459 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93463 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93467 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93469 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93476 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] }))  =>  (EONXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrs),
     /*  93479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93481 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  93483 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93487 */     GIR_RootConstrainSelectedInstOperands,
     /*  93488 */     // GIR_Coverage, 14303,
     /*  93488 */     GIR_EraseRootFromParent_Done,
     /*  93489 */   // Label 1466: @93489
     /*  93489 */   GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(93526), // Rule ID 4101 //
     /*  93494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93498 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93502 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93509 */     // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, -1:{ *:[i64] })  =>  (ORNXrs:{ *:[i64] } XZR:{ *:[i64] }, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrs),
     /*  93512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93514 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  93520 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93524 */     GIR_RootConstrainSelectedInstOperands,
     /*  93525 */     // GIR_Coverage, 4101,
     /*  93525 */     GIR_EraseRootFromParent_Done,
     /*  93526 */   // Label 1467: @93526
     /*  93526 */   GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(93626), // Rule ID 1619 //
     /*  93531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  93534 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  93538 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93542 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  93546 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93550 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /*  93554 */     // MIs[1] Operand 1
     /*  93554 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  93559 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  93563 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  93567 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /*  93571 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /*  93575 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  93580 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  93585 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  93589 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93595 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  93597 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  93601 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  93607 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  93609 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  93611 */     // (xor:{ *:[v1i64] } (setcc:{ *:[v1i64] } (and:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm), immAllZerosV:{ *:[v1i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v1i64] })  =>  (CMTSTv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /*  93611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv1i64),
     /*  93614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  93620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  93624 */     GIR_RootConstrainSelectedInstOperands,
     /*  93625 */     // GIR_Coverage, 1619,
     /*  93625 */     GIR_EraseRootFromParent_Done,
     /*  93626 */   // Label 1468: @93626
     /*  93626 */   GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(93667), // Rule ID 133 //
     /*  93631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /*  93635 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93643 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  93647 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_logical_imm64),
     /*  93651 */     // MIs[1] Operand 1
     /*  93651 */     // No operand predicates
     /*  93651 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93653 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_logical_imm64>><<X:logical_imm64_XFORM>>:$imm)  =>  (EORXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (logical_imm64_XFORM:{ *:[i64] } (imm:{ *:[i64] }):$imm))
     /*  93653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXri),
     /*  93656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93658 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  93660 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm64), // imm
     /*  93665 */     GIR_RootConstrainSelectedInstOperands,
     /*  93666 */     // GIR_Coverage, 133,
     /*  93666 */     GIR_EraseRootFromParent_Done,
     /*  93667 */   // Label 1469: @93667
     /*  93667 */   GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(93700), // Rule ID 14306 //
     /*  93672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93676 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93687 */     // (xor:{ *:[i64] } logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift, GPR64:{ *:[i64] }:$Rn)  =>  (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
     /*  93690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /*  93694 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93698 */     GIR_RootConstrainSelectedInstOperands,
     /*  93699 */     // GIR_Coverage, 14306,
     /*  93699 */     GIR_EraseRootFromParent_Done,
     /*  93700 */   // Label 1470: @93700
     /*  93700 */   GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(93760), // Rule ID 155 //
     /*  93705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  93717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93721 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93725 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93730 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93735 */     GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_disjoint),
     /*  93739 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93743 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93745 */     // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_or_disjoint>>, -1:{ *:[i64] })  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  93745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  93748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  93758 */     GIR_RootConstrainSelectedInstOperands,
     /*  93759 */     // GIR_Coverage, 155,
     /*  93759 */     GIR_EraseRootFromParent_Done,
     /*  93760 */   // Label 1471: @93760
     /*  93760 */   GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(93793), // Rule ID 163 //
     /*  93765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93773 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_logical_shifted_reg64),
     /*  93780 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)  =>  (EORXrs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, logical_shifted_reg64:{ *:[i64] }:$Rm_and_shift)
     /*  93780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORXrs),
     /*  93783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93785 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  93787 */     GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // Rm_and_shift
     /*  93791 */     GIR_RootConstrainSelectedInstOperands,
     /*  93792 */     // GIR_Coverage, 163,
     /*  93792 */     GIR_EraseRootFromParent_Done,
     /*  93793 */   // Label 1472: @93793
     /*  93793 */   GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(93846), // Rule ID 14291 //
     /*  93798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93802 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93806 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93810 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93814 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93818 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93823 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93827 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93831 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93833 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }), GPR64:{ *:[i64] }:$Rm)  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  93833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  93836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93838 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /*  93844 */     GIR_RootConstrainSelectedInstOperands,
     /*  93845 */     // GIR_Coverage, 14291,
     /*  93845 */     GIR_EraseRootFromParent_Done,
     /*  93846 */   // Label 1473: @93846
     /*  93846 */   GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(93902), // Rule ID 154 //
     /*  93851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  93859 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93863 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93867 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93876 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93881 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93885 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93887 */     // (xor:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm), -1:{ *:[i64] })  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  93887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  93890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /*  93900 */     GIR_RootConstrainSelectedInstOperands,
     /*  93901 */     // GIR_Coverage, 154,
     /*  93901 */     GIR_EraseRootFromParent_Done,
     /*  93902 */   // Label 1474: @93902
     /*  93902 */   GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(93955), // Rule ID 14292 //
     /*  93907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93911 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93915 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  93919 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  93923 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  93927 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  93931 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93936 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /*  93940 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  93942 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, -1:{ *:[i64] }))  =>  (EONXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  93942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EONXrr),
     /*  93945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /*  93951 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /*  93953 */     GIR_RootConstrainSelectedInstOperands,
     /*  93954 */     // GIR_Coverage, 14292,
     /*  93954 */     GIR_EraseRootFromParent_Done,
     /*  93955 */   // Label 1475: @93955
     /*  93955 */   GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(93987), // Rule ID 4099 //
     /*  93960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93964 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  93968 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  93972 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Xm, -1:{ *:[i64] })  =>  (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Xm)
     /*  93972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /*  93975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  93977 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  93983 */     GIR_RootToRootCopy, /*OpIdx*/1, // Xm
     /*  93985 */     GIR_RootConstrainSelectedInstOperands,
     /*  93986 */     // GIR_Coverage, 4099,
     /*  93986 */     GIR_EraseRootFromParent_Done,
     /*  93987 */   // Label 1476: @93987
     /*  93987 */   GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(94023), // Rule ID 5022 //
     /*  93992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  93996 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  94004 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94010 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  94012 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  94014 */     // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] })  =>  (NOTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
     /*  94014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  94017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  94019 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  94021 */     GIR_RootConstrainSelectedInstOperands,
     /*  94022 */     // GIR_Coverage, 5022,
     /*  94022 */     GIR_EraseRootFromParent_Done,
     /*  94023 */   // Label 1477: @94023
     /*  94023 */   GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(94266), // Rule ID 3919 //
     /*  94028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  94031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94035 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94039 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94043 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  94047 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  94051 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94061 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94065 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  94067 */     // (xor:{ *:[v1i64] } (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Vn, V64:{ *:[v1i64] }:$Vm), V64:{ *:[v1i64] }:$Va)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  94067 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  94070 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94074 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94079 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  94081 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  94084 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94088 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94093 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  94096 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // Va
     /*  94100 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  94103 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94108 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94113 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94118 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  94121 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94125 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94130 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  94132 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  94135 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94139 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94144 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  94147 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  94151 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  94154 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94159 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94164 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94169 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  94172 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94176 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94181 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  94183 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  94186 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94190 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94195 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  94198 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  94202 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  94205 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94210 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94215 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94220 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  94223 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  94227 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94232 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  94235 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  94238 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  94241 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  94243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  94246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  94248 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  94255 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94260 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94265 */     // GIR_Coverage, 3919,
     /*  94265 */     GIR_EraseRootFromParent_Done,
     /*  94266 */   // Label 1478: @94266
     /*  94266 */   GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(94509), // Rule ID 14811 //
     /*  94271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  94274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94278 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  94286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94290 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  94294 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  94298 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94303 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94308 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  94310 */     // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Va, (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$Vn, V64:{ *:[v1i64] }:$Vm))  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  94310 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  94313 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94317 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94322 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  94324 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  94327 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94331 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94336 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  94339 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Va
     /*  94343 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  94346 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94351 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94356 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94361 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  94364 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94368 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94373 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  94375 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  94378 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94382 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94387 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  94390 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  94394 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  94397 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94402 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94407 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94412 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  94415 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94419 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94424 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  94426 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  94429 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94433 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94438 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  94441 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  94445 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  94448 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94453 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94458 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94463 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  94466 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  94470 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94475 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  94478 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  94481 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  94484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  94486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  94489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  94491 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  94498 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94503 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94508 */     // GIR_Coverage, 14811,
     /*  94508 */     GIR_EraseRootFromParent_Done,
     /*  94509 */   // Label 1479: @94509
     /*  94509 */   GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(94533), // Rule ID 161 //
     /*  94514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  94518 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  94522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /*  94526 */     // (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (EORXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /*  94526 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORXrr),
     /*  94531 */     GIR_RootConstrainSelectedInstOperands,
     /*  94532 */     // GIR_Coverage, 161,
     /*  94532 */     GIR_Done,
     /*  94533 */   // Label 1480: @94533
     /*  94533 */   GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(94560), // Rule ID 5100 //
     /*  94538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  94541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94545 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94553 */     // (xor:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)  =>  (EORv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$LHS, V64:{ *:[v1i64] }:$RHS)
     /*  94553 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  94558 */     GIR_RootConstrainSelectedInstOperands,
     /*  94559 */     // GIR_Coverage, 5100,
     /*  94559 */     GIR_Done,
     /*  94560 */   // Label 1481: @94560
     /*  94560 */   GIM_Reject,
     /*  94561 */ // Label 1458: @94561
     /*  94561 */ GIM_Reject,
     /*  94562 */ // Label 1422: @94562
     /*  94562 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(95274),
     /*  94567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  94570 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  94573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94577 */   GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(94673), // Rule ID 1190 //
     /*  94582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  94585 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94589 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  94593 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  94597 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  94601 */     // MIs[1] Operand 1
     /*  94601 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  94606 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  94610 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  94614 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  94618 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  94622 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94627 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94632 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  94636 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94642 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  94644 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  94648 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94654 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  94656 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  94658 */     // (xor:{ *:[v2i32] } (setcc:{ *:[v2i32] } (and:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i32] })  =>  (CMTSTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /*  94658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i32),
     /*  94661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  94663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  94667 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  94671 */     GIR_RootConstrainSelectedInstOperands,
     /*  94672 */     // GIR_Coverage, 1190,
     /*  94672 */     GIR_EraseRootFromParent_Done,
     /*  94673 */   // Label 1483: @94673
     /*  94673 */   GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(94740), // Rule ID 5069 //
     /*  94678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  94686 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  94690 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /*  94694 */     // MIs[1] Operand 1
     /*  94694 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  94699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  94703 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94709 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  94711 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  94715 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94721 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  94723 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  94725 */     // (xor:{ *:[v2i32] } (setcc:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i32] })  =>  (CMTSTv2i32:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$Rn, v2i32:{ *:[v2i32] }:$Rn)
     /*  94725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i32),
     /*  94728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  94730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  94734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  94738 */     GIR_RootConstrainSelectedInstOperands,
     /*  94739 */     // GIR_Coverage, 5069,
     /*  94739 */     GIR_EraseRootFromParent_Done,
     /*  94740 */   // Label 1484: @94740
     /*  94740 */   GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(94772), // Rule ID 5020 //
     /*  94745 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  94753 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  94759 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  94761 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  94763 */     // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] })  =>  (NOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /*  94763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  94766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  94768 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  94770 */     GIR_RootConstrainSelectedInstOperands,
     /*  94771 */     // GIR_Coverage, 5020,
     /*  94771 */     GIR_EraseRootFromParent_Done,
     /*  94772 */   // Label 1485: @94772
     /*  94772 */   GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(95011), // Rule ID 3917 //
     /*  94777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  94780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  94784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  94788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  94792 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  94796 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94801 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94806 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94810 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  94812 */     // (xor:{ *:[v2i32] } (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm), V64:{ *:[v2i32] }:$Va)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  94812 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  94815 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94819 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94824 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  94826 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  94829 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94833 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94838 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  94841 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // Va
     /*  94845 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  94848 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94853 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94858 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94863 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  94866 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94870 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94875 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  94877 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  94880 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94884 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94889 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  94892 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  94896 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  94899 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94904 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94909 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94914 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  94917 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  94921 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94926 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  94928 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  94931 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  94935 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94940 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  94943 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  94947 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  94950 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94955 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  94960 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  94965 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  94968 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  94972 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  94977 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  94980 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  94983 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  94986 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  94988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  94991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  94993 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  95000 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95005 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95010 */     // GIR_Coverage, 3917,
     /*  95010 */     GIR_EraseRootFromParent_Done,
     /*  95011 */   // Label 1486: @95011
     /*  95011 */   GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(95250), // Rule ID 14809 //
     /*  95016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95019 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95031 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /*  95035 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /*  95039 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95044 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95049 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95051 */     // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Va, (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  95051 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  95054 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  95058 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95063 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  95065 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  95068 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  95072 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95077 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  95080 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Va
     /*  95084 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  95087 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95092 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95097 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95102 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  95105 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  95109 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95114 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  95116 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  95119 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  95123 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95128 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  95131 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  95135 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  95138 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95143 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95148 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95153 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  95156 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  95160 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95165 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  95167 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  95170 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  95174 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95179 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  95182 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  95186 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  95189 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95194 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95199 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95204 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  95207 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  95211 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  95216 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  95219 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  95222 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  95225 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  95227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  95230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  95232 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  95239 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95244 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95249 */     // GIR_Coverage, 14809,
     /*  95249 */     GIR_EraseRootFromParent_Done,
     /*  95250 */   // Label 1487: @95250
     /*  95250 */   GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(95273), // Rule ID 5099 //
     /*  95255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  95258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95266 */     // (xor:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)  =>  (EORv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$LHS, V64:{ *:[v2i32] }:$RHS)
     /*  95266 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  95271 */     GIR_RootConstrainSelectedInstOperands,
     /*  95272 */     // GIR_Coverage, 5099,
     /*  95272 */     GIR_Done,
     /*  95273 */   // Label 1488: @95273
     /*  95273 */   GIM_Reject,
     /*  95274 */ // Label 1482: @95274
     /*  95274 */ GIM_Reject,
     /*  95275 */ // Label 1423: @95275
     /*  95275 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(95963),
     /*  95280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95283 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95290 */   GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(95386), // Rule ID 1192 //
     /*  95295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  95298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  95306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95310 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /*  95314 */     // MIs[1] Operand 1
     /*  95314 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  95319 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  95323 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95327 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95331 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95335 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95340 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95345 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  95349 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95355 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  95357 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  95361 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95367 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  95369 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  95371 */     // (xor:{ *:[v2i64] } (setcc:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i64] })  =>  (CMTSTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /*  95371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i64),
     /*  95374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  95376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  95380 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  95384 */     GIR_RootConstrainSelectedInstOperands,
     /*  95385 */     // GIR_Coverage, 1192,
     /*  95385 */     GIR_EraseRootFromParent_Done,
     /*  95386 */   // Label 1490: @95386
     /*  95386 */   GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(95453), // Rule ID 5071 //
     /*  95391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  95399 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95403 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /*  95407 */     // MIs[1] Operand 1
     /*  95407 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  95412 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  95416 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95422 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  95424 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  95428 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95434 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  95436 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  95438 */     // (xor:{ *:[v2i64] } (setcc:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v2i64] })  =>  (CMTSTv2i64:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, v2i64:{ *:[v2i64] }:$Rn)
     /*  95438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv2i64),
     /*  95441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  95443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  95447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  95451 */     GIR_RootConstrainSelectedInstOperands,
     /*  95452 */     // GIR_Coverage, 5071,
     /*  95452 */     GIR_EraseRootFromParent_Done,
     /*  95453 */   // Label 1491: @95453
     /*  95453 */   GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(95538), // Rule ID 14823 //
     /*  95458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95473 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95477 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95481 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95485 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95489 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95493 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95498 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95502 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95508 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  95510 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95515 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95519 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  95521 */     // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Vn)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  95524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  95528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  95532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  95536 */     GIR_RootConstrainSelectedInstOperands,
     /*  95537 */     // GIR_Coverage, 14823,
     /*  95537 */     GIR_EraseRootFromParent_Done,
     /*  95538 */   // Label 1492: @95538
     /*  95538 */   GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(95623), // Rule ID 14822 //
     /*  95543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95558 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95562 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  95571 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95575 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95579 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95583 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95588 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95592 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95598 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  95600 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95604 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  95606 */     // (xor:{ *:[v2i64] } (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })), V128:{ *:[v2i64] }:$Vn)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  95609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  95613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  95617 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  95621 */     GIR_RootConstrainSelectedInstOperands,
     /*  95622 */     // GIR_Coverage, 14822,
     /*  95622 */     GIR_EraseRootFromParent_Done,
     /*  95623 */   // Label 1493: @95623
     /*  95623 */   GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(95708), // Rule ID 14821 //
     /*  95628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95631 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  95655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95659 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95663 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95667 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95672 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95676 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95682 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  95684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95689 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  95691 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] }), V128:{ *:[v2i64] }:$Vm))  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  95694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95696 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  95698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  95702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  95706 */     GIR_RootConstrainSelectedInstOperands,
     /*  95707 */     // GIR_Coverage, 14821,
     /*  95707 */     GIR_EraseRootFromParent_Done,
     /*  95708 */   // Label 1494: @95708
     /*  95708 */   GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(95793), // Rule ID 3923 //
     /*  95713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95716 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  95728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95732 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95736 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95741 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  95745 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95749 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95753 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95757 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95762 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  95766 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95772 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  95774 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  95776 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, (and:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, immAllOnesV:{ *:[v2i64] })))  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  95779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  95783 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  95787 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  95791 */     GIR_RootConstrainSelectedInstOperands,
     /*  95792 */     // GIR_Coverage, 3923,
     /*  95792 */     GIR_EraseRootFromParent_Done,
     /*  95793 */   // Label 1495: @95793
     /*  95793 */   GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(95825), // Rule ID 5023 //
     /*  95798 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95802 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95806 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  95812 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  95814 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95816 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] })  =>  (NOTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /*  95816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  95819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  95821 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  95823 */     GIR_RootConstrainSelectedInstOperands,
     /*  95824 */     // GIR_Coverage, 5023,
     /*  95824 */     GIR_EraseRootFromParent_Done,
     /*  95825 */   // Label 1496: @95825
     /*  95825 */   GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(95882), // Rule ID 3918 //
     /*  95830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95845 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95849 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95854 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95863 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95865 */     // (xor:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm), V128:{ *:[v2i64] }:$Va)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  95868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  95874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  95878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  95880 */     GIR_RootConstrainSelectedInstOperands,
     /*  95881 */     // GIR_Coverage, 3918,
     /*  95881 */     GIR_EraseRootFromParent_Done,
     /*  95882 */   // Label 1497: @95882
     /*  95882 */   GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(95939), // Rule ID 14810 //
     /*  95887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  95890 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  95898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  95902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  95906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  95910 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95915 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95920 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  95922 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Va, (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm))  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, V128:{ *:[v2i64] }:$Va)
     /*  95922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  95925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  95927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  95931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  95935 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  95937 */     GIR_RootConstrainSelectedInstOperands,
     /*  95938 */     // GIR_Coverage, 14810,
     /*  95938 */     GIR_EraseRootFromParent_Done,
     /*  95939 */   // Label 1498: @95939
     /*  95939 */   GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(95962), // Rule ID 5103 //
     /*  95944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  95947 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  95955 */     // (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)  =>  (EORv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$LHS, V128:{ *:[v2i64] }:$RHS)
     /*  95955 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  95960 */     GIR_RootConstrainSelectedInstOperands,
     /*  95961 */     // GIR_Coverage, 5103,
     /*  95961 */     GIR_Done,
     /*  95962 */   // Label 1499: @95962
     /*  95962 */   GIM_Reject,
     /*  95963 */ // Label 1489: @95963
     /*  95963 */ GIM_Reject,
     /*  95964 */ // Label 1424: @95964
     /*  95964 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(96676),
     /*  95969 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  95972 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  95975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  95979 */   GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(96075), // Rule ID 1188 //
     /*  95984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  95987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  95991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  95995 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  95999 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  96003 */     // MIs[1] Operand 1
     /*  96003 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  96008 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96012 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96016 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  96020 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  96024 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96029 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96034 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  96038 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96044 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  96046 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  96050 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96056 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  96058 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  96060 */     // (xor:{ *:[v4i16] } (setcc:{ *:[v4i16] } (and:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i16] })  =>  (CMTSTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /*  96060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i16),
     /*  96063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  96065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  96069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  96073 */     GIR_RootConstrainSelectedInstOperands,
     /*  96074 */     // GIR_Coverage, 1188,
     /*  96074 */     GIR_EraseRootFromParent_Done,
     /*  96075 */   // Label 1501: @96075
     /*  96075 */   GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(96142), // Rule ID 5067 //
     /*  96080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  96088 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  96092 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /*  96096 */     // MIs[1] Operand 1
     /*  96096 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  96101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  96105 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96111 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  96113 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  96117 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96123 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96125 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96127 */     // (xor:{ *:[v4i16] } (setcc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i16] })  =>  (CMTSTv4i16:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$Rn, v4i16:{ *:[v4i16] }:$Rn)
     /*  96127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i16),
     /*  96130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  96132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  96136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  96140 */     GIR_RootConstrainSelectedInstOperands,
     /*  96141 */     // GIR_Coverage, 5067,
     /*  96141 */     GIR_EraseRootFromParent_Done,
     /*  96142 */   // Label 1502: @96142
     /*  96142 */   GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(96174), // Rule ID 5018 //
     /*  96147 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96151 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  96155 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96161 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  96163 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  96165 */     // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] })  =>  (NOTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /*  96165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  96168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  96170 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  96172 */     GIR_RootConstrainSelectedInstOperands,
     /*  96173 */     // GIR_Coverage, 5018,
     /*  96173 */     GIR_EraseRootFromParent_Done,
     /*  96174 */   // Label 1503: @96174
     /*  96174 */   GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(96413), // Rule ID 3915 //
     /*  96179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  96182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  96194 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  96198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96203 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96212 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  96214 */     // (xor:{ *:[v4i16] } (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm), V64:{ *:[v4i16] }:$Va)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  96214 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  96217 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96221 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96226 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  96228 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  96231 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96235 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96240 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  96243 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // Va
     /*  96247 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  96250 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96255 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96260 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96265 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  96268 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96272 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96277 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  96279 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  96282 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96286 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96291 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  96294 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  96298 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  96301 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96306 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96311 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96316 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  96319 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96323 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96328 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  96330 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  96333 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96337 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96342 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  96345 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  96349 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  96352 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96357 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96362 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96367 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  96370 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  96374 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96379 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  96382 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  96385 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  96388 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  96390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  96393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  96395 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  96402 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96407 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96412 */     // GIR_Coverage, 3915,
     /*  96412 */     GIR_EraseRootFromParent_Done,
     /*  96413 */   // Label 1504: @96413
     /*  96413 */   GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(96652), // Rule ID 14807 //
     /*  96418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  96421 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96425 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  96429 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96433 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /*  96437 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /*  96441 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  96453 */     // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Va, (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  96453 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  96456 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96460 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96465 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  96467 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  96470 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96474 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96479 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  96482 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Va
     /*  96486 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  96489 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96494 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96499 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96504 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  96507 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96511 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96516 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  96518 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  96521 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96525 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96530 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  96533 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  96537 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  96540 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96545 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96550 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96555 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  96558 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  96562 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96567 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  96569 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  96572 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  96576 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96581 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  96584 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  96588 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  96591 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96596 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96601 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  96609 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  96613 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  96618 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  96621 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  96624 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  96627 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  96629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  96632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  96634 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  96641 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96646 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96651 */     // GIR_Coverage, 14807,
     /*  96651 */     GIR_EraseRootFromParent_Done,
     /*  96652 */   // Label 1505: @96652
     /*  96652 */   GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(96675), // Rule ID 5098 //
     /*  96657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  96660 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  96668 */     // (xor:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)  =>  (EORv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$LHS, V64:{ *:[v4i16] }:$RHS)
     /*  96668 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  96673 */     GIR_RootConstrainSelectedInstOperands,
     /*  96674 */     // GIR_Coverage, 5098,
     /*  96674 */     GIR_Done,
     /*  96675 */   // Label 1506: @96675
     /*  96675 */   GIM_Reject,
     /*  96676 */ // Label 1500: @96676
     /*  96676 */ GIM_Reject,
     /*  96677 */ // Label 1425: @96677
     /*  96677 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(97365),
     /*  96682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96685 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96692 */   GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(96788), // Rule ID 1191 //
     /*  96697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  96700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  96708 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96712 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  96716 */     // MIs[1] Operand 1
     /*  96716 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  96721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96729 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96733 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96737 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96742 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96747 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  96751 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96757 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  96759 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  96763 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96769 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  96771 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  96773 */     // (xor:{ *:[v4i32] } (setcc:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i32] })  =>  (CMTSTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /*  96773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i32),
     /*  96776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  96778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  96782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  96786 */     GIR_RootConstrainSelectedInstOperands,
     /*  96787 */     // GIR_Coverage, 1191,
     /*  96787 */     GIR_EraseRootFromParent_Done,
     /*  96788 */   // Label 1508: @96788
     /*  96788 */   GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(96855), // Rule ID 5070 //
     /*  96793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  96801 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96805 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /*  96809 */     // MIs[1] Operand 1
     /*  96809 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  96814 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  96818 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96824 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  96826 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  96830 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96836 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96838 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96840 */     // (xor:{ *:[v4i32] } (setcc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v4i32] })  =>  (CMTSTv4i32:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, v4i32:{ *:[v4i32] }:$Rn)
     /*  96840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv4i32),
     /*  96843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  96845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  96849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  96853 */     GIR_RootConstrainSelectedInstOperands,
     /*  96854 */     // GIR_Coverage, 5070,
     /*  96854 */     GIR_EraseRootFromParent_Done,
     /*  96855 */   // Label 1509: @96855
     /*  96855 */   GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(96940), // Rule ID 14820 //
     /*  96860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  96863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96879 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  96883 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96887 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96891 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96895 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96900 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96904 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  96910 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  96912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96917 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96921 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  96923 */     // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Vn)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  96923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  96926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  96928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  96930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  96934 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  96938 */     GIR_RootConstrainSelectedInstOperands,
     /*  96939 */     // GIR_Coverage, 14820,
     /*  96939 */     GIR_EraseRootFromParent_Done,
     /*  96940 */   // Label 1510: @96940
     /*  96940 */   GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(97025), // Rule ID 14819 //
     /*  96945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  96948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  96952 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  96956 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96960 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96964 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  96973 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  96977 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  96981 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  96985 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  96990 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  96994 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97000 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  97002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97006 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  97008 */     // (xor:{ *:[v4i32] } (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })), V128:{ *:[v4i32] }:$Vn)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  97008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  97011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  97013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  97015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  97019 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  97023 */     GIR_RootConstrainSelectedInstOperands,
     /*  97024 */     // GIR_Coverage, 14819,
     /*  97024 */     GIR_EraseRootFromParent_Done,
     /*  97025 */   // Label 1511: @97025
     /*  97025 */   GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(97110), // Rule ID 14818 //
     /*  97030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97033 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97037 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97041 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97045 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97049 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97053 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  97057 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97061 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97065 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97069 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97074 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  97078 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97084 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  97086 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97091 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  97093 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] }), V128:{ *:[v4i32] }:$Vm))  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  97093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  97096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  97098 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  97100 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  97104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  97108 */     GIR_RootConstrainSelectedInstOperands,
     /*  97109 */     // GIR_Coverage, 14818,
     /*  97109 */     GIR_EraseRootFromParent_Done,
     /*  97110 */   // Label 1512: @97110
     /*  97110 */   GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(97195), // Rule ID 3922 //
     /*  97115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97134 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97138 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97143 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  97147 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97151 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97155 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97159 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97164 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  97168 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97174 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  97176 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  97178 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, (and:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, immAllOnesV:{ *:[v4i32] })))  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  97178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  97181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  97183 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  97185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  97189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  97193 */     GIR_RootConstrainSelectedInstOperands,
     /*  97194 */     // GIR_Coverage, 3922,
     /*  97194 */     GIR_EraseRootFromParent_Done,
     /*  97195 */   // Label 1513: @97195
     /*  97195 */   GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(97227), // Rule ID 5021 //
     /*  97200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97208 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97214 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  97216 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97218 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] })  =>  (NOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /*  97218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  97221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  97223 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  97225 */     GIR_RootConstrainSelectedInstOperands,
     /*  97226 */     // GIR_Coverage, 5021,
     /*  97226 */     GIR_EraseRootFromParent_Done,
     /*  97227 */   // Label 1514: @97227
     /*  97227 */   GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(97284), // Rule ID 3916 //
     /*  97232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97247 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97251 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97256 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97265 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97267 */     // (xor:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm), V128:{ *:[v4i32] }:$Va)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  97267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  97270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  97272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  97276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  97280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  97282 */     GIR_RootConstrainSelectedInstOperands,
     /*  97283 */     // GIR_Coverage, 3916,
     /*  97283 */     GIR_EraseRootFromParent_Done,
     /*  97284 */   // Label 1515: @97284
     /*  97284 */   GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(97341), // Rule ID 14808 //
     /*  97289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97292 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97304 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  97308 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  97312 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97317 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97322 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97324 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Va, (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm))  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /*  97324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  97327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  97329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  97333 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  97337 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  97339 */     GIR_RootConstrainSelectedInstOperands,
     /*  97340 */     // GIR_Coverage, 14808,
     /*  97340 */     GIR_EraseRootFromParent_Done,
     /*  97341 */   // Label 1516: @97341
     /*  97341 */   GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(97364), // Rule ID 5102 //
     /*  97346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  97349 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97353 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97357 */     // (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)  =>  (EORv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$LHS, V128:{ *:[v4i32] }:$RHS)
     /*  97357 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  97362 */     GIR_RootConstrainSelectedInstOperands,
     /*  97363 */     // GIR_Coverage, 5102,
     /*  97363 */     GIR_Done,
     /*  97364 */   // Label 1517: @97364
     /*  97364 */   GIM_Reject,
     /*  97365 */ // Label 1507: @97365
     /*  97365 */ GIM_Reject,
     /*  97366 */ // Label 1426: @97366
     /*  97366 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(98081),
     /*  97371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  97374 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97377 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97381 */   GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(97477), // Rule ID 1186 //
     /*  97386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  97389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  97397 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97401 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  97405 */     // MIs[1] Operand 1
     /*  97405 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  97410 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  97414 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  97418 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  97422 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97426 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97431 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97436 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  97440 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97446 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  97448 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  97452 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97458 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  97460 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  97462 */     // (xor:{ *:[v8i8] } (setcc:{ *:[v8i8] } (and:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm), immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i8] })  =>  (CMTSTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  97462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i8),
     /*  97465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  97467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  97471 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  97475 */     GIR_RootConstrainSelectedInstOperands,
     /*  97476 */     // GIR_Coverage, 1186,
     /*  97476 */     GIR_EraseRootFromParent_Done,
     /*  97477 */   // Label 1519: @97477
     /*  97477 */   GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(97544), // Rule ID 5065 //
     /*  97482 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97486 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  97490 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97494 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s8,
     /*  97498 */     // MIs[1] Operand 1
     /*  97498 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  97503 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  97507 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97513 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  97515 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  97519 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97525 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  97527 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  97529 */     // (xor:{ *:[v8i8] } (setcc:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i8] })  =>  (CMTSTv8i8:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rn)
     /*  97529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i8),
     /*  97532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  97534 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  97538 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  97542 */     GIR_RootConstrainSelectedInstOperands,
     /*  97543 */     // GIR_Coverage, 5065,
     /*  97543 */     GIR_EraseRootFromParent_Done,
     /*  97544 */   // Label 1520: @97544
     /*  97544 */   GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(97579), // Rule ID 1002 //
     /*  97549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  97552 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97560 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  97566 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  97568 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97570 */     // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] })  =>  (NOTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /*  97570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv8i8),
     /*  97573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  97575 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  97577 */     GIR_RootConstrainSelectedInstOperands,
     /*  97578 */     // GIR_Coverage, 1002,
     /*  97578 */     GIR_EraseRootFromParent_Done,
     /*  97579 */   // Label 1521: @97579
     /*  97579 */   GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(97818), // Rule ID 3913 //
     /*  97584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97587 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  97591 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97595 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  97599 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97603 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97617 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97619 */     // (xor:{ *:[v8i8] } (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vm), V64:{ *:[v8i8] }:$Va)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  97619 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  97622 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97626 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97631 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  97633 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  97636 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97640 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97645 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  97648 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // Va
     /*  97652 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  97655 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97660 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97665 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97670 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  97673 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97677 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  97684 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  97687 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97691 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97696 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  97699 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  97703 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  97706 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97711 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97716 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97721 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  97724 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97728 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97733 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  97735 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  97738 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97742 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97747 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  97750 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  97754 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  97757 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97762 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97767 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97772 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  97775 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  97779 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97784 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  97787 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  97790 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  97793 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  97795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  97798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  97800 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  97807 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97812 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97817 */     // GIR_Coverage, 3913,
     /*  97817 */     GIR_EraseRootFromParent_Done,
     /*  97818 */   // Label 1522: @97818
     /*  97818 */   GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(98057), // Rule ID 14805 //
     /*  97823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  97826 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97830 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  97834 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  97838 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /*  97842 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /*  97846 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97851 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97856 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  97858 */     // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Va, (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vm))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EOR3:{ *:[f128] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vm, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Va, dsub:{ *:[i32] })), dsub:{ *:[i32] })
     /*  97858 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s128,
     /*  97861 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97865 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97870 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /*  97872 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s128,
     /*  97875 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97879 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97884 */     GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
     /*  97887 */     GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, // Va
     /*  97891 */     GIR_AddImm8, /*InsnID*/6, /*Imm*/3,
     /*  97894 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97899 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97904 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97909 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /*  97912 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97916 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97921 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /*  97923 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /*  97926 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97930 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97935 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /*  97938 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  97942 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/3,
     /*  97945 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97950 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  97955 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  97960 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /*  97963 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /*  97967 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97972 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  97974 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /*  97977 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /*  97981 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  97986 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  97989 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  97993 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /*  97996 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98001 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98006 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  98011 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /*  98014 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  98018 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  98023 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  98026 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /*  98029 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
     /*  98032 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  98034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  98037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  98039 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /*  98046 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  98051 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98056 */     // GIR_Coverage, 14805,
     /*  98056 */     GIR_EraseRootFromParent_Done,
     /*  98057 */   // Label 1523: @98057
     /*  98057 */   GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(98080), // Rule ID 1605 //
     /*  98062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  98065 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  98069 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /*  98073 */     // (xor:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (EORv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /*  98073 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /*  98078 */     GIR_RootConstrainSelectedInstOperands,
     /*  98079 */     // GIR_Coverage, 1605,
     /*  98079 */     GIR_Done,
     /*  98080 */   // Label 1524: @98080
     /*  98080 */   GIM_Reject,
     /*  98081 */ // Label 1518: @98081
     /*  98081 */ GIM_Reject,
     /*  98082 */ // Label 1427: @98082
     /*  98082 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(98770),
     /*  98087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98090 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98097 */   GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(98193), // Rule ID 1189 //
     /*  98102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  98105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  98113 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98117 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  98121 */     // MIs[1] Operand 1
     /*  98121 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  98126 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98130 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98134 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98138 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98142 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98147 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98152 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  98156 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98162 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  98164 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  98168 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98174 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  98176 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  98178 */     // (xor:{ *:[v8i16] } (setcc:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i16] })  =>  (CMTSTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /*  98178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i16),
     /*  98181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  98183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  98187 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  98191 */     GIR_RootConstrainSelectedInstOperands,
     /*  98192 */     // GIR_Coverage, 1189,
     /*  98192 */     GIR_EraseRootFromParent_Done,
     /*  98193 */   // Label 1526: @98193
     /*  98193 */   GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(98260), // Rule ID 5068 //
     /*  98198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  98206 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98210 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /*  98214 */     // MIs[1] Operand 1
     /*  98214 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  98219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  98223 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98229 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  98231 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  98235 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98241 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98243 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98245 */     // (xor:{ *:[v8i16] } (setcc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v8i16] })  =>  (CMTSTv8i16:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, v8i16:{ *:[v8i16] }:$Rn)
     /*  98245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv8i16),
     /*  98248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  98250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  98254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  98258 */     GIR_RootConstrainSelectedInstOperands,
     /*  98259 */     // GIR_Coverage, 5068,
     /*  98259 */     GIR_EraseRootFromParent_Done,
     /*  98260 */   // Label 1527: @98260
     /*  98260 */   GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(98345), // Rule ID 14817 //
     /*  98265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98292 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98296 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98300 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98305 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98309 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98315 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98317 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98322 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98326 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98328 */     // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Vn)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  98331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  98335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  98339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  98343 */     GIR_RootConstrainSelectedInstOperands,
     /*  98344 */     // GIR_Coverage, 14817,
     /*  98344 */     GIR_EraseRootFromParent_Done,
     /*  98345 */   // Label 1528: @98345
     /*  98345 */   GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(98430), // Rule ID 14816 //
     /*  98350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98353 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98357 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98361 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98365 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98369 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98374 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98378 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98382 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98386 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98390 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98395 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98399 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98405 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98411 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98413 */     // (xor:{ *:[v8i16] } (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })), V128:{ *:[v8i16] }:$Vn)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  98416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  98420 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  98424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  98428 */     GIR_RootConstrainSelectedInstOperands,
     /*  98429 */     // GIR_Coverage, 14816,
     /*  98429 */     GIR_EraseRootFromParent_Done,
     /*  98430 */   // Label 1529: @98430
     /*  98430 */   GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(98515), // Rule ID 14815 //
     /*  98435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98438 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98442 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98446 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98450 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98454 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98458 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98462 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98466 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98470 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98474 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98479 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98483 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98489 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98491 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98496 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98498 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] }), V128:{ *:[v8i16] }:$Vm))  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  98501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98503 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  98505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  98509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  98513 */     GIR_RootConstrainSelectedInstOperands,
     /*  98514 */     // GIR_Coverage, 14815,
     /*  98514 */     GIR_EraseRootFromParent_Done,
     /*  98515 */   // Label 1530: @98515
     /*  98515 */   GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(98600), // Rule ID 3921 //
     /*  98520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98543 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98548 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98552 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98556 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98560 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98564 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98569 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98573 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98579 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98581 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98583 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, (and:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, immAllOnesV:{ *:[v8i16] })))  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  98586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98588 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  98590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  98594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  98598 */     GIR_RootConstrainSelectedInstOperands,
     /*  98599 */     // GIR_Coverage, 3921,
     /*  98599 */     GIR_EraseRootFromParent_Done,
     /*  98600 */   // Label 1531: @98600
     /*  98600 */   GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(98632), // Rule ID 5019 //
     /*  98605 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98613 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98619 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  98621 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  98623 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] })  =>  (NOTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /*  98623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  98626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  98628 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  98630 */     GIR_RootConstrainSelectedInstOperands,
     /*  98631 */     // GIR_Coverage, 5019,
     /*  98631 */     GIR_EraseRootFromParent_Done,
     /*  98632 */   // Label 1532: @98632
     /*  98632 */   GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(98689), // Rule ID 3914 //
     /*  98637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98652 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98656 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98670 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  98672 */     // (xor:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm), V128:{ *:[v8i16] }:$Va)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  98675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  98681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  98685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  98687 */     GIR_RootConstrainSelectedInstOperands,
     /*  98688 */     // GIR_Coverage, 3914,
     /*  98688 */     GIR_EraseRootFromParent_Done,
     /*  98689 */   // Label 1533: @98689
     /*  98689 */   GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(98746), // Rule ID 14806 //
     /*  98694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  98705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  98713 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  98717 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98722 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98727 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  98729 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Va, (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm))  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm, V128:{ *:[v8i16] }:$Va)
     /*  98729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  98732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  98734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  98738 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  98742 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  98744 */     GIR_RootConstrainSelectedInstOperands,
     /*  98745 */     // GIR_Coverage, 14806,
     /*  98745 */     GIR_EraseRootFromParent_Done,
     /*  98746 */   // Label 1534: @98746
     /*  98746 */   GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(98769), // Rule ID 5101 //
     /*  98751 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  98754 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98758 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98762 */     // (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)  =>  (EORv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$LHS, V128:{ *:[v8i16] }:$RHS)
     /*  98762 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  98767 */     GIR_RootConstrainSelectedInstOperands,
     /*  98768 */     // GIR_Coverage, 5101,
     /*  98768 */     GIR_Done,
     /*  98769 */   // Label 1535: @98769
     /*  98769 */   GIM_Reject,
     /*  98770 */ // Label 1525: @98770
     /*  98770 */ GIM_Reject,
     /*  98771 */ // Label 1428: @98771
     /*  98771 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(99462),
     /*  98776 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  98779 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98782 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98786 */   GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(98882), // Rule ID 1187 //
     /*  98791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  98794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  98802 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98806 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  98810 */     // MIs[1] Operand 1
     /*  98810 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  98815 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  98819 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98823 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  98827 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98831 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98836 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98841 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/3, // MIs[3]
     /*  98845 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98851 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/3,
     /*  98853 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /*  98857 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98863 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  98865 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /*  98867 */     // (xor:{ *:[v16i8] } (setcc:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm), immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v16i8] })  =>  (CMTSTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  98867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv16i8),
     /*  98870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  98872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /*  98876 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /*  98880 */     GIR_RootConstrainSelectedInstOperands,
     /*  98881 */     // GIR_Coverage, 1187,
     /*  98881 */     GIR_EraseRootFromParent_Done,
     /*  98882 */   // Label 1537: @98882
     /*  98882 */   GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(98949), // Rule ID 5066 //
     /*  98887 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98891 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /*  98895 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98899 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /*  98903 */     // MIs[1] Operand 1
     /*  98903 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /*  98908 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /*  98912 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98918 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/2,
     /*  98920 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /*  98924 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  98930 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  98932 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  98934 */     // (xor:{ *:[v16i8] } (setcc:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] }), immAllOnesV:{ *:[v16i8] })  =>  (CMTSTv16i8:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rn)
     /*  98934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMTSTv16i8),
     /*  98937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  98939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  98943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /*  98947 */     GIR_RootConstrainSelectedInstOperands,
     /*  98948 */     // GIR_Coverage, 5066,
     /*  98948 */     GIR_EraseRootFromParent_Done,
     /*  98949 */   // Label 1538: @98949
     /*  98949 */   GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(99034), // Rule ID 14814 //
     /*  98954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  98957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  98961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  98965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  98969 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98973 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  98977 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  98981 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  98985 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  98989 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  98994 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  98998 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99004 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99006 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99011 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99015 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99017 */     // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Vn)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  99020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  99024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  99028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  99032 */     GIR_RootConstrainSelectedInstOperands,
     /*  99033 */     // GIR_Coverage, 14814,
     /*  99033 */     GIR_EraseRootFromParent_Done,
     /*  99034 */   // Label 1539: @99034
     /*  99034 */   GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(99119), // Rule ID 14813 //
     /*  99039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  99042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99058 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99063 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  99067 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99071 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99075 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99079 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99084 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99088 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99094 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99096 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99100 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99102 */     // (xor:{ *:[v16i8] } (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })), V128:{ *:[v16i8] }:$Vn)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  99105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /*  99109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  99113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  99117 */     GIR_RootConstrainSelectedInstOperands,
     /*  99118 */     // GIR_Coverage, 14813,
     /*  99118 */     GIR_EraseRootFromParent_Done,
     /*  99119 */   // Label 1540: @99119
     /*  99119 */   GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(99204), // Rule ID 14812 //
     /*  99124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  99127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  99135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99143 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99155 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99159 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99163 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99168 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99172 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99178 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99180 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99185 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99187 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] }), V128:{ *:[v16i8] }:$Vm))  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  99190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99192 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  99194 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  99198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  99202 */     GIR_RootConstrainSelectedInstOperands,
     /*  99203 */     // GIR_Coverage, 14812,
     /*  99203 */     GIR_EraseRootFromParent_Done,
     /*  99204 */   // Label 1541: @99204
     /*  99204 */   GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(99289), // Rule ID 3920 //
     /*  99209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  99212 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99216 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  99220 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99224 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99228 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99232 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99237 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  99241 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99245 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99249 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99253 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99258 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99262 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99268 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /*  99270 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /*  99272 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, (and:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vm, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, immAllOnesV:{ *:[v16i8] })))  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /*  99275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99277 */     GIR_RootToRootCopy, /*OpIdx*/1, // Vn
     /*  99279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /*  99283 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Va
     /*  99287 */     GIR_RootConstrainSelectedInstOperands,
     /*  99288 */     // GIR_Coverage, 3920,
     /*  99288 */     GIR_EraseRootFromParent_Done,
     /*  99289 */   // Label 1542: @99289
     /*  99289 */   GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(99324), // Rule ID 1003 //
     /*  99294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  99297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99301 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  99305 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99311 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /*  99313 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  99315 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] })  =>  (NOTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /*  99315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOTv16i8),
     /*  99318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /*  99320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /*  99322 */     GIR_RootConstrainSelectedInstOperands,
     /*  99323 */     // GIR_Coverage, 1003,
     /*  99323 */     GIR_EraseRootFromParent_Done,
     /*  99324 */   // Label 1543: @99324
     /*  99324 */   GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(99381), // Rule ID 3912 //
     /*  99329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  99332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99344 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99348 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99353 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99362 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  99364 */     // (xor:{ *:[v16i8] } (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm), V128:{ *:[v16i8] }:$Va)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  99367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  99373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  99377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Va
     /*  99379 */     GIR_RootConstrainSelectedInstOperands,
     /*  99380 */     // GIR_Coverage, 3912,
     /*  99380 */     GIR_EraseRootFromParent_Done,
     /*  99381 */   // Label 1544: @99381
     /*  99381 */   GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(99438), // Rule ID 14804 //
     /*  99386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /*  99389 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99393 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  99397 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99401 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  99405 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  99409 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99414 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99419 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  99421 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Va, (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm))  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm, V128:{ *:[v16i8] }:$Va)
     /*  99421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /*  99424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /*  99426 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /*  99430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /*  99434 */     GIR_RootToRootCopy, /*OpIdx*/1, // Va
     /*  99436 */     GIR_RootConstrainSelectedInstOperands,
     /*  99437 */     // GIR_Coverage, 14804,
     /*  99437 */     GIR_EraseRootFromParent_Done,
     /*  99438 */   // Label 1545: @99438
     /*  99438 */   GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(99461), // Rule ID 1606 //
     /*  99443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /*  99446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /*  99454 */     // (xor:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (EORv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /*  99454 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /*  99459 */     GIR_RootConstrainSelectedInstOperands,
     /*  99460 */     // GIR_Coverage, 1606,
     /*  99460 */     GIR_Done,
     /*  99461 */   // Label 1546: @99461
     /*  99461 */   GIM_Reject,
     /*  99462 */ // Label 1536: @99462
     /*  99462 */ GIM_Reject,
     /*  99463 */ // Label 1429: @99463
     /*  99463 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(99512), // Rule ID 9176 //
     /*  99468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  99471 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /*  99474 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /*  99477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  99481 */   // (xor:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv1i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2)
     /*  99481 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  99484 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  99488 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  99493 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  99496 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  99498 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  99501 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  99503 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  99506 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  99508 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  99510 */   GIR_RootConstrainSelectedInstOperands,
     /*  99511 */   // GIR_Coverage, 9176,
     /*  99511 */   GIR_EraseRootFromParent_Done,
     /*  99512 */ // Label 1547: @99512
     /*  99512 */ GIM_Reject,
     /*  99513 */ // Label 1430: @99513
     /*  99513 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(99562), // Rule ID 9175 //
     /*  99518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /*  99521 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /*  99524 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /*  99527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /*  99531 */   // (xor:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv2i1] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /*  99531 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /*  99534 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /*  99538 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  99543 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /*  99546 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  99548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /*  99551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /*  99553 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  99556 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /*  99558 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /*  99560 */   GIR_RootConstrainSelectedInstOperands,
     /*  99561 */   // GIR_Coverage, 9175,
     /*  99561 */   GIR_EraseRootFromParent_Done,
     /*  99562 */ // Label 1548: @99562
     /*  99562 */ GIM_Reject,
     /*  99563 */ // Label 1431: @99563
     /*  99563 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(101250),
     /*  99568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99571 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /*  99578 */   GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(99696), // Rule ID 17085 //
     /*  99583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99586 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99590 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99594 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99598 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99602 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99606 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99610 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99614 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99618 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  99622 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99626 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99630 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99634 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99638 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99644 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99646 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99650 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99654 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99658 */     // MIs[5] Op3
     /*  99658 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99663 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99667 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99673 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99675 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99677 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  99677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99682 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  99686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  99690 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99694 */     GIR_RootConstrainSelectedInstOperands,
     /*  99695 */     // GIR_Coverage, 17085,
     /*  99695 */     GIR_EraseRootFromParent_Done,
     /*  99696 */   // Label 1550: @99696
     /*  99696 */   GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(99814), // Rule ID 17084 //
     /*  99701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99716 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99720 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99724 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99728 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99732 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99736 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /*  99740 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99744 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99748 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99752 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99756 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99762 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99764 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99768 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99772 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99776 */     // MIs[5] Op3
     /*  99776 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99781 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99785 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99791 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99793 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99795 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  99795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99800 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /*  99804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /*  99808 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99812 */     GIR_RootConstrainSelectedInstOperands,
     /*  99813 */     // GIR_Coverage, 17084,
     /*  99813 */     GIR_EraseRootFromParent_Done,
     /*  99814 */   // Label 1551: @99814
     /*  99814 */   GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(99932), // Rule ID 17083 //
     /*  99819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99830 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99834 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99838 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99842 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99846 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99850 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99854 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99858 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99862 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99866 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99870 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99874 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99880 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /*  99882 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /*  99886 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99890 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99894 */     // MIs[5] Op3
     /*  99894 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /*  99899 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /*  99903 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99909 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /*  99911 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /*  99913 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /*  99913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /*  99916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /*  99918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /*  99922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /*  99926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /*  99930 */     GIR_RootConstrainSelectedInstOperands,
     /*  99931 */     // GIR_Coverage, 17083,
     /*  99931 */     GIR_EraseRootFromParent_Done,
     /*  99932 */   // Label 1552: @99932
     /*  99932 */   GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(100050), // Rule ID 17082 //
     /*  99937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /*  99940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  99944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  99948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99952 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99956 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /*  99960 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /*  99964 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99968 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99972 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /*  99976 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /*  99980 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /*  99984 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /*  99988 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /*  99992 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /*  99998 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 100000 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 100004 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100008 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100012 */     // MIs[5] Op3
     /* 100012 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 100017 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 100021 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100027 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 100029 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 100031 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 100040 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 100044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 100048 */     GIR_RootConstrainSelectedInstOperands,
     /* 100049 */     // GIR_Coverage, 17082,
     /* 100049 */     GIR_EraseRootFromParent_Done,
     /* 100050 */   // Label 1553: @100050
     /* 100050 */   GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(100168), // Rule ID 17079 //
     /* 100055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100066 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100070 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100074 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100078 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100082 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100086 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100090 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 100094 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100098 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100102 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100106 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 100110 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100114 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100118 */     // MIs[4] Op3
     /* 100118 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 100123 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 100127 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100133 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 100135 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 100139 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100145 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 100147 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 100149 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100154 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 100158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 100162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 100166 */     GIR_RootConstrainSelectedInstOperands,
     /* 100167 */     // GIR_Coverage, 17079,
     /* 100167 */     GIR_EraseRootFromParent_Done,
     /* 100168 */   // Label 1554: @100168
     /* 100168 */   GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(100286), // Rule ID 17081 //
     /* 100173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100200 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100204 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100208 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 100212 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100216 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100220 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100224 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 100228 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100232 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100236 */     // MIs[4] Op3
     /* 100236 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 100241 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 100245 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100251 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 100253 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 100257 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100263 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 100265 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 100267 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 100276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 100280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100284 */     GIR_RootConstrainSelectedInstOperands,
     /* 100285 */     // GIR_Coverage, 17081,
     /* 100285 */     GIR_EraseRootFromParent_Done,
     /* 100286 */   // Label 1555: @100286
     /* 100286 */   GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(100404), // Rule ID 12818 //
     /* 100291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100294 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100302 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100310 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100314 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100318 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100322 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100326 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 100330 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100334 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100338 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100342 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 100346 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100350 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100354 */     // MIs[4] Op3
     /* 100354 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 100359 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 100363 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100369 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 100371 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 100375 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100381 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 100383 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 100385 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op3), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }))), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 100394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 100398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 100402 */     GIR_RootConstrainSelectedInstOperands,
     /* 100403 */     // GIR_Coverage, 12818,
     /* 100403 */     GIR_EraseRootFromParent_Done,
     /* 100404 */   // Label 1556: @100404
     /* 100404 */   GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(100522), // Rule ID 17080 //
     /* 100409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100412 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100416 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100420 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100424 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100428 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100432 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100436 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100440 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100444 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 100448 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100452 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100456 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100460 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 100464 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100468 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100472 */     // MIs[4] Op3
     /* 100472 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 100477 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 100481 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100487 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 100489 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 100493 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100499 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 100501 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 100503 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1), (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }))), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100508 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 100512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 100516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100520 */     GIR_RootConstrainSelectedInstOperands,
     /* 100521 */     // GIR_Coverage, 17080,
     /* 100521 */     GIR_EraseRootFromParent_Done,
     /* 100522 */   // Label 1557: @100522
     /* 100522 */   GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(100593), // Rule ID 16697 //
     /* 100527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100538 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100554 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100558 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100562 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100566 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100572 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100574 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100576 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100581 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 100583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 100587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100591 */     GIR_RootConstrainSelectedInstOperands,
     /* 100592 */     // GIR_Coverage, 16697,
     /* 100592 */     GIR_EraseRootFromParent_Done,
     /* 100593 */   // Label 1558: @100593
     /* 100593 */   GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(100664), // Rule ID 16696 //
     /* 100598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100601 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100605 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100609 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100613 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100617 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 100621 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100625 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100629 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100633 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100637 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100643 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100645 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100647 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })), nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 100654 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 100658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100662 */     GIR_RootConstrainSelectedInstOperands,
     /* 100663 */     // GIR_Coverage, 16696,
     /* 100663 */     GIR_EraseRootFromParent_Done,
     /* 100664 */   // Label 1559: @100664
     /* 100664 */   GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(100735), // Rule ID 16695 //
     /* 100669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100672 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100676 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100680 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100684 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100688 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 100692 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100696 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100700 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100704 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100708 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100714 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100716 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100718 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100723 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 100725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 100729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100733 */     GIR_RootConstrainSelectedInstOperands,
     /* 100734 */     // GIR_Coverage, 16695,
     /* 100734 */     GIR_EraseRootFromParent_Done,
     /* 100735 */   // Label 1560: @100735
     /* 100735 */   GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(100806), // Rule ID 12710 //
     /* 100740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 100747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100755 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100759 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 100763 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100767 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100771 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100775 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 100779 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100785 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 100787 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 100789 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, immAllOnesV:{ *:[nxv2i64] })))  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 100792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100794 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 100796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 100800 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 100804 */     GIR_RootConstrainSelectedInstOperands,
     /* 100805 */     // GIR_Coverage, 12710,
     /* 100805 */     GIR_EraseRootFromParent_Done,
     /* 100806 */   // Label 1561: @100806
     /* 100806 */   GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(100867), // Rule ID 12817 //
     /* 100811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /* 100822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100826 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100830 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 100834 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100838 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100844 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100846 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100848 */     // (xor:{ *:[nxv2i64] } (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 100848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100853 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /* 100857 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /* 100861 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 100865 */     GIR_RootConstrainSelectedInstOperands,
     /* 100866 */     // GIR_Coverage, 12817,
     /* 100866 */     GIR_EraseRootFromParent_Done,
     /* 100867 */   // Label 1562: @100867
     /* 100867 */   GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(100924), // Rule ID 12874 //
     /* 100872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100875 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100879 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 100883 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100887 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100891 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100895 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100901 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100903 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100905 */     // (xor:{ *:[nxv2i64] } (and:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1)
     /* 100905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100910 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100922 */     GIR_RootConstrainSelectedInstOperands,
     /* 100923 */     // GIR_Coverage, 12874,
     /* 100923 */     GIR_EraseRootFromParent_Done,
     /* 100924 */   // Label 1563: @100924
     /* 100924 */   GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(100981), // Rule ID 12877 //
     /* 100929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 100940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 100944 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 100948 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 100952 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 100958 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 100960 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 100962 */     // (xor:{ *:[nxv2i64] } (or:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (NBSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op2, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /* 100962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 100965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 100967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 100975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 100979 */     GIR_RootConstrainSelectedInstOperands,
     /* 100980 */     // GIR_Coverage, 12877,
     /* 100980 */     GIR_EraseRootFromParent_Done,
     /* 100981 */   // Label 1564: @100981
     /* 100981 */   GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(101036), // Rule ID 17169 //
     /* 100986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 100989 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 100993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 100997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 101001 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 101005 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 101009 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101015 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 101017 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 101019 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /* 101019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 101022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101032 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /* 101034 */     GIR_RootConstrainSelectedInstOperands,
     /* 101035 */     // GIR_Coverage, 17169,
     /* 101035 */     GIR_EraseRootFromParent_Done,
     /* 101036 */   // Label 1565: @101036
     /* 101036 */   GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(101093), // Rule ID 12871 //
     /* 101041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 101056 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 101060 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 101064 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101070 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 101072 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 101074 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, nxv2i64:{ *:[nxv2i64] }:$op2), immAllOnesV:{ *:[nxv2i64] })  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /* 101074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 101077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101079 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101083 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101087 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 101091 */     GIR_RootConstrainSelectedInstOperands,
     /* 101092 */     // GIR_Coverage, 12871,
     /* 101092 */     GIR_EraseRootFromParent_Done,
     /* 101093 */   // Label 1566: @101093
     /* 101093 */   GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(101148), // Rule ID 17170 //
     /* 101098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101101 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101105 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101109 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 101113 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 101117 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 101121 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101127 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 101129 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 101131 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op2, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$op1, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op1, ?:{ *:[nxv2i64] }:$op2)
     /* 101131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 101134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 101144 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /* 101146 */     GIR_RootConstrainSelectedInstOperands,
     /* 101147 */     // GIR_Coverage, 17170,
     /* 101147 */     GIR_EraseRootFromParent_Done,
     /* 101148 */   // Label 1567: @101148
     /* 101148 */   GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(101191), // Rule ID 14769 //
     /* 101153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101156 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101160 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101164 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 101168 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 101172 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 101174 */     // (xor:{ *:[nxv2i64] } (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 101174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 101177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 101183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 101187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 101189 */     GIR_RootConstrainSelectedInstOperands,
     /* 101190 */     // GIR_Coverage, 14769,
     /* 101190 */     GIR_EraseRootFromParent_Done,
     /* 101191 */   // Label 1568: @101191
     /* 101191 */   GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(101234), // Rule ID 3220 //
     /* 101196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 101203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101207 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 101211 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 101215 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 101217 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 101217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 101220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101222 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 101224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 101228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /* 101232 */     GIR_RootConstrainSelectedInstOperands,
     /* 101233 */     // GIR_Coverage, 3220,
     /* 101233 */     GIR_EraseRootFromParent_Done,
     /* 101234 */   // Label 1569: @101234
     /* 101234 */   GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(101249), // Rule ID 8133 //
     /* 101239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 101242 */     // (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 101242 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /* 101247 */     GIR_RootConstrainSelectedInstOperands,
     /* 101248 */     // GIR_Coverage, 8133,
     /* 101248 */     GIR_Done,
     /* 101249 */   // Label 1570: @101249
     /* 101249 */   GIM_Reject,
     /* 101250 */ // Label 1549: @101250
     /* 101250 */ GIM_Reject,
     /* 101251 */ // Label 1432: @101251
     /* 101251 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(101300), // Rule ID 9174 //
     /* 101256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 101259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 101262 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 101265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 101269 */   // (xor:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv4i1] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 101269 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 101272 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 101276 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 101281 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 101284 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 101286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 101289 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 101291 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 101294 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 101296 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /* 101298 */   GIR_RootConstrainSelectedInstOperands,
     /* 101299 */   // GIR_Coverage, 9174,
     /* 101299 */   GIR_EraseRootFromParent_Done,
     /* 101300 */ // Label 1571: @101300
     /* 101300 */ GIM_Reject,
     /* 101301 */ // Label 1433: @101301
     /* 101301 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(102988),
     /* 101306 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101309 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101312 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 101316 */   GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(101434), // Rule ID 17078 //
     /* 101321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101328 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101332 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101336 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101340 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101344 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101348 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101352 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101356 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 101360 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101364 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101368 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101372 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 101376 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101382 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 101384 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 101388 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101392 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101396 */     // MIs[5] Op3
     /* 101396 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 101401 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101405 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101411 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 101413 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 101415 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 101415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 101418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101420 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 101424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 101428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 101432 */     GIR_RootConstrainSelectedInstOperands,
     /* 101433 */     // GIR_Coverage, 17078,
     /* 101433 */     GIR_EraseRootFromParent_Done,
     /* 101434 */   // Label 1573: @101434
     /* 101434 */   GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(101552), // Rule ID 17077 //
     /* 101439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101442 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101446 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101450 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101454 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101458 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101462 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101466 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101470 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101474 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 101478 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101482 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101486 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101490 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 101494 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101500 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 101502 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 101506 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101510 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101514 */     // MIs[5] Op3
     /* 101514 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 101519 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101523 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101529 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 101531 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 101533 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 101533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 101536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101538 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 101542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 101546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 101550 */     GIR_RootConstrainSelectedInstOperands,
     /* 101551 */     // GIR_Coverage, 17077,
     /* 101551 */     GIR_EraseRootFromParent_Done,
     /* 101552 */   // Label 1574: @101552
     /* 101552 */   GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(101670), // Rule ID 17076 //
     /* 101557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101568 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101572 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101576 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101580 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101584 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101588 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101592 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 101596 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101600 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101604 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101608 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 101612 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101618 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 101620 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 101624 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101628 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101632 */     // MIs[5] Op3
     /* 101632 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 101637 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101641 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101647 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 101649 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 101651 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 101651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 101654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 101660 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 101664 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 101668 */     GIR_RootConstrainSelectedInstOperands,
     /* 101669 */     // GIR_Coverage, 17076,
     /* 101669 */     GIR_EraseRootFromParent_Done,
     /* 101670 */   // Label 1575: @101670
     /* 101670 */   GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(101788), // Rule ID 17075 //
     /* 101675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101686 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101690 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101702 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101706 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101710 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 101714 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101718 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101722 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101726 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 101730 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101736 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 101738 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 101742 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101746 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101750 */     // MIs[5] Op3
     /* 101750 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 101755 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101759 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101765 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 101767 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 101769 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 101769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 101772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 101778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 101782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 101786 */     GIR_RootConstrainSelectedInstOperands,
     /* 101787 */     // GIR_Coverage, 17075,
     /* 101787 */     GIR_EraseRootFromParent_Done,
     /* 101788 */   // Label 1576: @101788
     /* 101788 */   GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(101906), // Rule ID 17072 //
     /* 101793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101796 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101800 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101804 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101808 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101812 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101816 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101820 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101824 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101828 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 101832 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101836 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101840 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101844 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 101848 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101852 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101856 */     // MIs[4] Op3
     /* 101856 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 101861 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 101865 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101871 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 101873 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101877 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101883 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 101885 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 101887 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 101887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 101890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 101892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 101896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 101900 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 101904 */     GIR_RootConstrainSelectedInstOperands,
     /* 101905 */     // GIR_Coverage, 17072,
     /* 101905 */     GIR_EraseRootFromParent_Done,
     /* 101906 */   // Label 1577: @101906
     /* 101906 */   GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(102024), // Rule ID 17074 //
     /* 101911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 101914 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 101918 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 101922 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101926 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101930 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 101934 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101938 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101942 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101946 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 101950 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 101954 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 101958 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101962 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 101966 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 101970 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 101974 */     // MIs[4] Op3
     /* 101974 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 101979 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 101983 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 101989 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 101991 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 101995 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102001 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 102003 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 102005 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 102014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 102018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102022 */     GIR_RootConstrainSelectedInstOperands,
     /* 102023 */     // GIR_Coverage, 17074,
     /* 102023 */     GIR_EraseRootFromParent_Done,
     /* 102024 */   // Label 1578: @102024
     /* 102024 */   GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(102142), // Rule ID 12816 //
     /* 102029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102032 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102036 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 102040 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102044 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102048 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102052 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102056 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102060 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102064 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 102068 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102072 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102076 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102080 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 102084 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102088 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102092 */     // MIs[4] Op3
     /* 102092 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 102097 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 102101 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102107 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 102109 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 102113 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102119 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 102121 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 102123 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op3), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }))), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 102132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 102136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 102140 */     GIR_RootConstrainSelectedInstOperands,
     /* 102141 */     // GIR_Coverage, 12816,
     /* 102141 */     GIR_EraseRootFromParent_Done,
     /* 102142 */   // Label 1579: @102142
     /* 102142 */   GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(102260), // Rule ID 17073 //
     /* 102147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102150 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102154 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 102158 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102162 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102166 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102170 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102174 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102178 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102182 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 102186 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102190 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102194 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102198 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 102202 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102206 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102210 */     // MIs[4] Op3
     /* 102210 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 102215 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 102219 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102225 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 102227 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 102231 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102237 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 102239 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 102241 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1), (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }))), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 102250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 102254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102258 */     GIR_RootConstrainSelectedInstOperands,
     /* 102259 */     // GIR_Coverage, 17073,
     /* 102259 */     GIR_EraseRootFromParent_Done,
     /* 102260 */   // Label 1580: @102260
     /* 102260 */   GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(102331), // Rule ID 16694 //
     /* 102265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102292 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102296 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102300 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102304 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102310 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 102312 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102314 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 102317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 102321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 102325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102329 */     GIR_RootConstrainSelectedInstOperands,
     /* 102330 */     // GIR_Coverage, 16694,
     /* 102330 */     GIR_EraseRootFromParent_Done,
     /* 102331 */   // Label 1581: @102331
     /* 102331 */   GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(102402), // Rule ID 16693 //
     /* 102336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102339 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102343 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102347 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102351 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102355 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 102359 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102363 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102367 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102371 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102375 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102381 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 102383 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102385 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })), nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 102388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 102392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 102396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102400 */     GIR_RootConstrainSelectedInstOperands,
     /* 102401 */     // GIR_Coverage, 16693,
     /* 102401 */     GIR_EraseRootFromParent_Done,
     /* 102402 */   // Label 1582: @102402
     /* 102402 */   GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(102473), // Rule ID 16692 //
     /* 102407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102422 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102426 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 102430 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102434 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102438 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102442 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102446 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102452 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 102454 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102456 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (and:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 102459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102461 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 102463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 102467 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102471 */     GIR_RootConstrainSelectedInstOperands,
     /* 102472 */     // GIR_Coverage, 16692,
     /* 102472 */     GIR_EraseRootFromParent_Done,
     /* 102473 */   // Label 1583: @102473
     /* 102473 */   GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(102544), // Rule ID 12708 //
     /* 102478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102489 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102493 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102497 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 102501 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102505 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102509 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102513 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 102517 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102523 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 102525 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 102527 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, immAllOnesV:{ *:[nxv4i32] })))  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 102530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102532 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 102534 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 102538 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 102542 */     GIR_RootConstrainSelectedInstOperands,
     /* 102543 */     // GIR_Coverage, 12708,
     /* 102543 */     GIR_EraseRootFromParent_Done,
     /* 102544 */   // Label 1584: @102544
     /* 102544 */   GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(102605), // Rule ID 12815 //
     /* 102549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102552 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102556 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /* 102560 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102564 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102568 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 102572 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 102576 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102582 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102584 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102586 */     // (xor:{ *:[nxv4i32] } (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102591 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /* 102595 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /* 102599 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 102603 */     GIR_RootConstrainSelectedInstOperands,
     /* 102604 */     // GIR_Coverage, 12815,
     /* 102604 */     GIR_EraseRootFromParent_Done,
     /* 102605 */   // Label 1585: @102605
     /* 102605 */   GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(102662), // Rule ID 12862 //
     /* 102610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102613 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102617 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 102621 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102625 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102629 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 102633 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102639 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102641 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102643 */     // (xor:{ *:[nxv4i32] } (and:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1)
     /* 102643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102648 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 102652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102660 */     GIR_RootConstrainSelectedInstOperands,
     /* 102661 */     // GIR_Coverage, 12862,
     /* 102661 */     GIR_EraseRootFromParent_Done,
     /* 102662 */   // Label 1586: @102662
     /* 102662 */   GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(102719), // Rule ID 12865 //
     /* 102667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 102678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102686 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 102690 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102696 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102698 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102700 */     // (xor:{ *:[nxv4i32] } (or:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (NBSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op2, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /* 102700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 102703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 102709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102713 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 102717 */     GIR_RootConstrainSelectedInstOperands,
     /* 102718 */     // GIR_Coverage, 12865,
     /* 102718 */     GIR_EraseRootFromParent_Done,
     /* 102719 */   // Label 1587: @102719
     /* 102719 */   GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(102774), // Rule ID 17160 //
     /* 102724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102739 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102743 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 102747 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102753 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102755 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102757 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /* 102757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 102760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102762 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102770 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /* 102772 */     GIR_RootConstrainSelectedInstOperands,
     /* 102773 */     // GIR_Coverage, 17160,
     /* 102773 */     GIR_EraseRootFromParent_Done,
     /* 102774 */   // Label 1588: @102774
     /* 102774 */   GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(102831), // Rule ID 12859 //
     /* 102779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102790 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102794 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102798 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 102802 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102808 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102810 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102812 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, nxv4i32:{ *:[nxv4i32] }:$op2), immAllOnesV:{ *:[nxv4i32] })  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /* 102812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 102815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102817 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102821 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102825 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 102829 */     GIR_RootConstrainSelectedInstOperands,
     /* 102830 */     // GIR_Coverage, 12859,
     /* 102830 */     GIR_EraseRootFromParent_Done,
     /* 102831 */   // Label 1589: @102831
     /* 102831 */   GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(102886), // Rule ID 17161 //
     /* 102836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102839 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102843 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102847 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102851 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102855 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 102859 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 102865 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 102867 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 102869 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op2, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$op1, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op1, ?:{ *:[nxv4i32] }:$op2)
     /* 102869 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 102872 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 102882 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /* 102884 */     GIR_RootConstrainSelectedInstOperands,
     /* 102885 */     // GIR_Coverage, 17161,
     /* 102885 */     GIR_EraseRootFromParent_Done,
     /* 102886 */   // Label 1590: @102886
     /* 102886 */   GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(102929), // Rule ID 14768 //
     /* 102891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 102898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102910 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102912 */     // (xor:{ *:[nxv4i32] } (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 102915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 102921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 102925 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 102927 */     GIR_RootConstrainSelectedInstOperands,
     /* 102928 */     // GIR_Coverage, 14768,
     /* 102928 */     GIR_EraseRootFromParent_Done,
     /* 102929 */   // Label 1591: @102929
     /* 102929 */   GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(102972), // Rule ID 3218 //
     /* 102934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 102937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 102941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 102945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 102949 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 102953 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 102955 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 102955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 102958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 102960 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 102962 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 102966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /* 102970 */     GIR_RootConstrainSelectedInstOperands,
     /* 102971 */     // GIR_Coverage, 3218,
     /* 102971 */     GIR_EraseRootFromParent_Done,
     /* 102972 */   // Label 1592: @102972
     /* 102972 */   GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(102987), // Rule ID 8132 //
     /* 102977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 102980 */     // (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 102980 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /* 102985 */     GIR_RootConstrainSelectedInstOperands,
     /* 102986 */     // GIR_Coverage, 8132,
     /* 102986 */     GIR_Done,
     /* 102987 */   // Label 1593: @102987
     /* 102987 */   GIM_Reject,
     /* 102988 */ // Label 1572: @102988
     /* 102988 */ GIM_Reject,
     /* 102989 */ // Label 1434: @102989
     /* 102989 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(103038), // Rule ID 9173 //
     /* 102994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 102997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 103000 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 103003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 103007 */   // (xor:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv8i1] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 103007 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 103010 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 103014 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 103019 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 103022 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 103024 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 103027 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 103029 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 103032 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 103034 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /* 103036 */   GIR_RootConstrainSelectedInstOperands,
     /* 103037 */   // GIR_Coverage, 9173,
     /* 103037 */   GIR_EraseRootFromParent_Done,
     /* 103038 */ // Label 1594: @103038
     /* 103038 */ GIM_Reject,
     /* 103039 */ // Label 1435: @103039
     /* 103039 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(104726),
     /* 103044 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103047 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 103054 */   GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(103172), // Rule ID 17071 //
     /* 103059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103070 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103074 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103086 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103090 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103094 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 103098 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103102 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103106 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103110 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103114 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103120 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 103122 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 103126 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103130 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103134 */     // MIs[5] Op3
     /* 103134 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 103139 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103143 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103149 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103151 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103153 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 103162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 103166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 103170 */     GIR_RootConstrainSelectedInstOperands,
     /* 103171 */     // GIR_Coverage, 17071,
     /* 103171 */     GIR_EraseRootFromParent_Done,
     /* 103172 */   // Label 1596: @103172
     /* 103172 */   GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(103290), // Rule ID 17070 //
     /* 103177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103192 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103196 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103200 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103204 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103208 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103212 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 103216 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103220 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103224 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103228 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103232 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103238 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 103240 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 103244 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103248 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103252 */     // MIs[5] Op3
     /* 103252 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 103257 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103261 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103267 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103269 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103271 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 103280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 103284 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 103288 */     GIR_RootConstrainSelectedInstOperands,
     /* 103289 */     // GIR_Coverage, 17070,
     /* 103289 */     GIR_EraseRootFromParent_Done,
     /* 103290 */   // Label 1597: @103290
     /* 103290 */   GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(103408), // Rule ID 17069 //
     /* 103295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103306 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103310 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103314 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103318 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103322 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103326 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103330 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 103334 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103338 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103342 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103346 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103350 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103356 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 103358 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 103362 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103366 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103370 */     // MIs[5] Op3
     /* 103370 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 103375 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103379 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103385 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103387 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103389 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 103398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 103402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 103406 */     GIR_RootConstrainSelectedInstOperands,
     /* 103407 */     // GIR_Coverage, 17069,
     /* 103407 */     GIR_EraseRootFromParent_Done,
     /* 103408 */   // Label 1598: @103408
     /* 103408 */   GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(103526), // Rule ID 17068 //
     /* 103413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103416 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103420 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103424 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103428 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103432 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103436 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103440 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103444 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103448 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 103452 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103456 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103460 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103464 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103468 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103474 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 103476 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 103480 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103484 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103488 */     // MIs[5] Op3
     /* 103488 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 103493 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103497 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103503 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103505 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103507 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 103516 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 103520 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 103524 */     GIR_RootConstrainSelectedInstOperands,
     /* 103525 */     // GIR_Coverage, 17068,
     /* 103525 */     GIR_EraseRootFromParent_Done,
     /* 103526 */   // Label 1599: @103526
     /* 103526 */   GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(103644), // Rule ID 17065 //
     /* 103531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103538 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103542 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103546 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103550 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103554 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103558 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103562 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103566 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 103570 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103574 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103578 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103582 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 103586 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103590 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103594 */     // MIs[4] Op3
     /* 103594 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 103599 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 103603 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103609 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 103611 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103615 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103621 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103623 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103625 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103630 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 103634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 103638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 103642 */     GIR_RootConstrainSelectedInstOperands,
     /* 103643 */     // GIR_Coverage, 17065,
     /* 103643 */     GIR_EraseRootFromParent_Done,
     /* 103644 */   // Label 1600: @103644
     /* 103644 */   GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(103762), // Rule ID 17067 //
     /* 103649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103664 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103668 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103672 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103676 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103680 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103684 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 103688 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103692 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103696 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103700 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 103704 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103708 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103712 */     // MIs[4] Op3
     /* 103712 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 103717 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 103721 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103727 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 103729 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103733 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103739 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103741 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103743 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 103752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 103756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 103760 */     GIR_RootConstrainSelectedInstOperands,
     /* 103761 */     // GIR_Coverage, 17067,
     /* 103761 */     GIR_EraseRootFromParent_Done,
     /* 103762 */   // Label 1601: @103762
     /* 103762 */   GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(103880), // Rule ID 12814 //
     /* 103767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103778 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103782 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103794 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103798 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103802 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 103806 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103810 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103814 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103818 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103822 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103826 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103830 */     // MIs[4] Op3
     /* 103830 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 103835 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 103839 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103845 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 103847 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103851 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103857 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103859 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103861 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op3), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }))), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103866 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 103870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 103874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 103878 */     GIR_RootConstrainSelectedInstOperands,
     /* 103879 */     // GIR_Coverage, 12814,
     /* 103879 */     GIR_EraseRootFromParent_Done,
     /* 103880 */   // Label 1602: @103880
     /* 103880 */   GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(103998), // Rule ID 17066 //
     /* 103885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 103888 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 103892 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 103896 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103904 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 103908 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103912 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103916 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103920 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 103924 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 103928 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 103932 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103936 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 103940 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 103944 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 103948 */     // MIs[4] Op3
     /* 103948 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 103953 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 103957 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103963 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 103965 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 103969 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 103975 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 103977 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 103979 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1), (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }))), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 103979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 103982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 103984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 103988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 103992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 103996 */     GIR_RootConstrainSelectedInstOperands,
     /* 103997 */     // GIR_Coverage, 17066,
     /* 103997 */     GIR_EraseRootFromParent_Done,
     /* 103998 */   // Label 1603: @103998
     /* 103998 */   GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(104069), // Rule ID 16691 //
     /* 104003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104026 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104030 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104034 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104038 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104042 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104048 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 104050 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104052 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 104055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 104059 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 104063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 104067 */     GIR_RootConstrainSelectedInstOperands,
     /* 104068 */     // GIR_Coverage, 16691,
     /* 104068 */     GIR_EraseRootFromParent_Done,
     /* 104069 */   // Label 1604: @104069
     /* 104069 */   GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(104140), // Rule ID 16690 //
     /* 104074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104085 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104089 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104093 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 104097 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104101 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104105 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104109 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104113 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104119 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 104121 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104123 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })), nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 104126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 104130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 104134 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 104138 */     GIR_RootConstrainSelectedInstOperands,
     /* 104139 */     // GIR_Coverage, 16690,
     /* 104139 */     GIR_EraseRootFromParent_Done,
     /* 104140 */   // Label 1605: @104140
     /* 104140 */   GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(104211), // Rule ID 16689 //
     /* 104145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104160 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104164 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104168 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104172 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104176 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104180 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104184 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104190 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 104192 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104194 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (and:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 104197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104199 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 104201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 104205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 104209 */     GIR_RootConstrainSelectedInstOperands,
     /* 104210 */     // GIR_Coverage, 16689,
     /* 104210 */     GIR_EraseRootFromParent_Done,
     /* 104211 */   // Label 1606: @104211
     /* 104211 */   GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(104282), // Rule ID 12706 //
     /* 104216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104227 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104231 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 104239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104243 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104247 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104251 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 104255 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104261 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 104263 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 104265 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, immAllOnesV:{ *:[nxv8i16] })))  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 104268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104270 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 104272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 104276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 104280 */     GIR_RootConstrainSelectedInstOperands,
     /* 104281 */     // GIR_Coverage, 12706,
     /* 104281 */     GIR_EraseRootFromParent_Done,
     /* 104282 */   // Label 1607: @104282
     /* 104282 */   GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(104343), // Rule ID 12813 //
     /* 104287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /* 104298 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104302 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104306 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 104310 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 104314 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104320 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104322 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104324 */     // (xor:{ *:[nxv8i16] } (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 104327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104329 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /* 104333 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /* 104337 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 104341 */     GIR_RootConstrainSelectedInstOperands,
     /* 104342 */     // GIR_Coverage, 12813,
     /* 104342 */     GIR_EraseRootFromParent_Done,
     /* 104343 */   // Label 1608: @104343
     /* 104343 */   GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(104400), // Rule ID 12850 //
     /* 104348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104363 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104367 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 104371 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104377 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104379 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104381 */     // (xor:{ *:[nxv8i16] } (and:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1)
     /* 104381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 104384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104386 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 104390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104398 */     GIR_RootConstrainSelectedInstOperands,
     /* 104399 */     // GIR_Coverage, 12850,
     /* 104399 */     GIR_EraseRootFromParent_Done,
     /* 104400 */   // Label 1609: @104400
     /* 104400 */   GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(104457), // Rule ID 12853 //
     /* 104405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104408 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104412 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 104416 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104420 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104424 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 104428 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104434 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104436 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104438 */     // (xor:{ *:[nxv8i16] } (or:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (NBSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op2, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /* 104438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 104441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 104447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 104455 */     GIR_RootConstrainSelectedInstOperands,
     /* 104456 */     // GIR_Coverage, 12853,
     /* 104456 */     GIR_EraseRootFromParent_Done,
     /* 104457 */   // Label 1610: @104457
     /* 104457 */   GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(104512), // Rule ID 17151 //
     /* 104462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104465 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104469 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104473 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104477 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 104485 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104491 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104493 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104495 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /* 104495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 104498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104500 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104504 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104508 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /* 104510 */     GIR_RootConstrainSelectedInstOperands,
     /* 104511 */     // GIR_Coverage, 17151,
     /* 104511 */     GIR_EraseRootFromParent_Done,
     /* 104512 */   // Label 1611: @104512
     /* 104512 */   GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(104569), // Rule ID 12847 //
     /* 104517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104528 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104532 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104536 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 104540 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104546 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104548 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104550 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, nxv8i16:{ *:[nxv8i16] }:$op2), immAllOnesV:{ *:[nxv8i16] })  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /* 104550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 104553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104555 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104559 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 104567 */     GIR_RootConstrainSelectedInstOperands,
     /* 104568 */     // GIR_Coverage, 12847,
     /* 104568 */     GIR_EraseRootFromParent_Done,
     /* 104569 */   // Label 1612: @104569
     /* 104569 */   GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(104624), // Rule ID 17152 //
     /* 104574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104589 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104593 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 104597 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104603 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 104605 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 104607 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op2, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$op1, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op1, ?:{ *:[nxv8i16] }:$op2)
     /* 104607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 104610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 104620 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /* 104622 */     GIR_RootConstrainSelectedInstOperands,
     /* 104623 */     // GIR_Coverage, 17152,
     /* 104623 */     GIR_EraseRootFromParent_Done,
     /* 104624 */   // Label 1613: @104624
     /* 104624 */   GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(104667), // Rule ID 14767 //
     /* 104629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104640 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104644 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104648 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104650 */     // (xor:{ *:[nxv8i16] } (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 104653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104655 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 104659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 104663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 104665 */     GIR_RootConstrainSelectedInstOperands,
     /* 104666 */     // GIR_Coverage, 14767,
     /* 104666 */     GIR_EraseRootFromParent_Done,
     /* 104667 */   // Label 1614: @104667
     /* 104667 */   GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(104710), // Rule ID 3216 //
     /* 104672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 104679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104683 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 104687 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 104691 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 104693 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 104693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 104696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104698 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 104700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 104704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /* 104708 */     GIR_RootConstrainSelectedInstOperands,
     /* 104709 */     // GIR_Coverage, 3216,
     /* 104709 */     GIR_EraseRootFromParent_Done,
     /* 104710 */   // Label 1615: @104710
     /* 104710 */   GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(104725), // Rule ID 8131 //
     /* 104715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 104718 */     // (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 104718 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /* 104723 */     GIR_RootConstrainSelectedInstOperands,
     /* 104724 */     // GIR_Coverage, 8131,
     /* 104724 */     GIR_Done,
     /* 104725 */   // Label 1616: @104725
     /* 104725 */   GIM_Reject,
     /* 104726 */ // Label 1595: @104726
     /* 104726 */ GIM_Reject,
     /* 104727 */ // Label 1436: @104727
     /* 104727 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(104776), // Rule ID 9172 //
     /* 104732 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 104735 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 104738 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 104741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 104745 */   // (xor:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (EOR_PPzPP:{ *:[nxv16i1] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 104745 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 104748 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 104752 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 104757 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 104760 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 104762 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 104765 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 104767 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 104770 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 104772 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /* 104774 */   GIR_RootConstrainSelectedInstOperands,
     /* 104775 */   // GIR_Coverage, 9172,
     /* 104775 */   GIR_EraseRootFromParent_Done,
     /* 104776 */ // Label 1617: @104776
     /* 104776 */ GIM_Reject,
     /* 104777 */ // Label 1437: @104777
     /* 104777 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(106464),
     /* 104782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104785 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 104792 */   GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(104910), // Rule ID 17064 //
     /* 104797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 104808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104812 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104816 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104820 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104824 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104828 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104832 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 104836 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104840 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104844 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104848 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 104852 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104858 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 104860 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 104864 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104868 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104872 */     // MIs[5] Op3
     /* 104872 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 104877 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 104881 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104887 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 104889 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 104891 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 104891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 104894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 104896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 104900 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 104904 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 104908 */     GIR_RootConstrainSelectedInstOperands,
     /* 104909 */     // GIR_Coverage, 17064,
     /* 104909 */     GIR_EraseRootFromParent_Done,
     /* 104910 */   // Label 1619: @104910
     /* 104910 */   GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(105028), // Rule ID 17063 //
     /* 104915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 104918 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 104922 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 104926 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104930 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104934 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 104938 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104942 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104946 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104950 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 104954 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 104958 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104962 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 104966 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 104970 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 104976 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 104978 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 104982 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 104986 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 104990 */     // MIs[5] Op3
     /* 104990 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 104995 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 104999 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105005 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105007 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105009 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 105018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op2
     /* 105022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 105026 */     GIR_RootConstrainSelectedInstOperands,
     /* 105027 */     // GIR_Coverage, 17063,
     /* 105027 */     GIR_EraseRootFromParent_Done,
     /* 105028 */   // Label 1620: @105028
     /* 105028 */   GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(105146), // Rule ID 17062 //
     /* 105033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105052 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105056 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105060 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105064 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105068 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105072 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105076 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105080 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105084 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 105088 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105094 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 105096 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 105100 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105104 */     GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105108 */     // MIs[5] Op3
     /* 105108 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 105113 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105117 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105123 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105125 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105127 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/2, // Op1
     /* 105136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 105140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 105144 */     GIR_RootConstrainSelectedInstOperands,
     /* 105145 */     // GIR_Coverage, 17062,
     /* 105145 */     GIR_EraseRootFromParent_Done,
     /* 105146 */   // Label 1621: @105146
     /* 105146 */   GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(105264), // Rule ID 17061 //
     /* 105151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105154 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105158 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105162 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105166 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105170 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105174 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105178 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105182 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105186 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105190 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105194 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105198 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105202 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 105206 */     GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105212 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 105214 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/1, /*OpIdx*/2, // MIs[5]
     /* 105218 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105222 */     GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105226 */     // MIs[5] Op3
     /* 105226 */     GIM_CheckIsSameOperand, /*MI*/5, /*OpIdx*/2, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 105231 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105235 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105241 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105243 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105245 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/5, /*OpIdx*/1, // Op1
     /* 105254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op2
     /* 105258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op3
     /* 105262 */     GIR_RootConstrainSelectedInstOperands,
     /* 105263 */     // GIR_Coverage, 17061,
     /* 105263 */     GIR_EraseRootFromParent_Done,
     /* 105264 */   // Label 1622: @105264
     /* 105264 */   GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(105382), // Rule ID 17058 //
     /* 105269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105280 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105284 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105288 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105292 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105296 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105300 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105304 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 105308 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105312 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105316 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105320 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 105324 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105328 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105332 */     // MIs[4] Op3
     /* 105332 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 105337 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 105341 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105347 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 105349 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105353 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105359 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105361 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105363 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105368 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 105372 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 105376 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 105380 */     GIR_RootConstrainSelectedInstOperands,
     /* 105381 */     // GIR_Coverage, 17058,
     /* 105381 */     GIR_EraseRootFromParent_Done,
     /* 105382 */   // Label 1623: @105382
     /* 105382 */   GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(105500), // Rule ID 17060 //
     /* 105387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105398 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105402 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105406 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105410 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105414 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105418 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105422 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 105426 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105430 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105434 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105438 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 105442 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105446 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105450 */     // MIs[4] Op3
     /* 105450 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 105455 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 105459 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105465 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 105467 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105471 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105477 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105479 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105481 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105486 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 105490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Op2
     /* 105494 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 105498 */     GIR_RootConstrainSelectedInstOperands,
     /* 105499 */     // GIR_Coverage, 17060,
     /* 105499 */     GIR_EraseRootFromParent_Done,
     /* 105500 */   // Label 1624: @105500
     /* 105500 */   GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(105618), // Rule ID 12812 //
     /* 105505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105508 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105512 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105516 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105520 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105524 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105528 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105532 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105536 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105540 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 105544 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105548 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105552 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105556 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 105560 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105564 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105568 */     // MIs[4] Op3
     /* 105568 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
     /* 105573 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 105577 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105583 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 105585 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105589 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105595 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105597 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105599 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op3), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }))), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op1
     /* 105608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 105612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op3
     /* 105616 */     GIR_RootConstrainSelectedInstOperands,
     /* 105617 */     // GIR_Coverage, 12812,
     /* 105617 */     GIR_EraseRootFromParent_Done,
     /* 105618 */   // Label 1625: @105618
     /* 105618 */   GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(105736), // Rule ID 17059 //
     /* 105623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 105634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105638 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105642 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105646 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105650 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105654 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 105662 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105666 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105670 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105674 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 105678 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105682 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105686 */     // MIs[4] Op3
     /* 105686 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
     /* 105691 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 105695 */     GIM_CheckOpcodeIsEither, /*MI*/5, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105701 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/5,
     /* 105703 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/0, /*OpIdx*/2, // MIs[6]
     /* 105707 */     GIM_CheckOpcodeIsEither, /*MI*/6, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105713 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/6,
     /* 105715 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 105717 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1), (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }))), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 105720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Op1
     /* 105726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Op2
     /* 105730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 105734 */     GIR_RootConstrainSelectedInstOperands,
     /* 105735 */     // GIR_Coverage, 17059,
     /* 105735 */     GIR_EraseRootFromParent_Done,
     /* 105736 */   // Label 1626: @105736
     /* 105736 */   GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(105807), // Rule ID 16688 //
     /* 105741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105756 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105768 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105772 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105776 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105780 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105786 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 105788 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 105790 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 105793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 105797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 105801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 105805 */     GIR_RootConstrainSelectedInstOperands,
     /* 105806 */     // GIR_Coverage, 16688,
     /* 105806 */     GIR_EraseRootFromParent_Done,
     /* 105807 */   // Label 1627: @105807
     /* 105807 */   GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(105878), // Rule ID 16687 //
     /* 105812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 105819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105827 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105831 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 105835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105839 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105843 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105847 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105851 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105857 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 105859 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 105861 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })), nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 105864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 105868 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 105872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 105876 */     GIR_RootConstrainSelectedInstOperands,
     /* 105877 */     // GIR_Coverage, 16687,
     /* 105877 */     GIR_EraseRootFromParent_Done,
     /* 105878 */   // Label 1628: @105878
     /* 105878 */   GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(105949), // Rule ID 16686 //
     /* 105883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105886 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105890 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105894 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105898 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105902 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 105906 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105910 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105914 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105918 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105922 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105928 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 105930 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 105932 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (and:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2))  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 105932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 105935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 105937 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 105939 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 105943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 105947 */     GIR_RootConstrainSelectedInstOperands,
     /* 105948 */     // GIR_Coverage, 16686,
     /* 105948 */     GIR_EraseRootFromParent_Done,
     /* 105949 */   // Label 1629: @105949
     /* 105949 */   GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(106020), // Rule ID 12704 //
     /* 105954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 105957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 105961 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 105965 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105969 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105973 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 105977 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 105981 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 105985 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 105989 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 105993 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 105999 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 106001 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 106003 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, immAllOnesV:{ *:[nxv16i8] })))  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 106003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 106006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 106010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 106014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Op3
     /* 106018 */     GIR_RootConstrainSelectedInstOperands,
     /* 106019 */     // GIR_Coverage, 12704,
     /* 106019 */     GIR_EraseRootFromParent_Done,
     /* 106020 */   // Label 1630: @106020
     /* 106020 */   GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(106081), // Rule ID 12811 //
     /* 106025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_BSP),
     /* 106036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106040 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106044 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 106048 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 106052 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106058 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106060 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106062 */     // (xor:{ *:[nxv16i8] } (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 106062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 106065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op1
     /* 106071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Op2
     /* 106075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 106079 */     GIR_RootConstrainSelectedInstOperands,
     /* 106080 */     // GIR_Coverage, 12811,
     /* 106080 */     GIR_EraseRootFromParent_Done,
     /* 106081 */   // Label 1631: @106081
     /* 106081 */   GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(106138), // Rule ID 12838 //
     /* 106086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106093 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 106097 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106101 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 106109 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106115 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106117 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106119 */     // (xor:{ *:[nxv16i8] } (and:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1)
     /* 106119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 106122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106124 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 106128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106136 */     GIR_RootConstrainSelectedInstOperands,
     /* 106137 */     // GIR_Coverage, 12838,
     /* 106137 */     GIR_EraseRootFromParent_Done,
     /* 106138 */   // Label 1632: @106138
     /* 106138 */   GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(106195), // Rule ID 12841 //
     /* 106143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 106154 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106158 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106162 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 106166 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106172 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106174 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106176 */     // (xor:{ *:[nxv16i8] } (or:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (NBSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op2, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 106176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NBSL_ZZZZ),
     /* 106179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106181 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 106185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 106193 */     GIR_RootConstrainSelectedInstOperands,
     /* 106194 */     // GIR_Coverage, 12841,
     /* 106194 */     GIR_EraseRootFromParent_Done,
     /* 106195 */   // Label 1633: @106195
     /* 106195 */   GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(106250), // Rule ID 17142 //
     /* 106200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106215 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 106223 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106229 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106231 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106233 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$op2)  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 106233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 106236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106246 */     GIR_RootToRootCopy, /*OpIdx*/2, // op2
     /* 106248 */     GIR_RootConstrainSelectedInstOperands,
     /* 106249 */     // GIR_Coverage, 17142,
     /* 106249 */     GIR_EraseRootFromParent_Done,
     /* 106250 */   // Label 1634: @106250
     /* 106250 */   GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(106307), // Rule ID 12835 //
     /* 106255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106270 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106274 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 106278 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106284 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106286 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106288 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, nxv16i8:{ *:[nxv16i8] }:$op2), immAllOnesV:{ *:[nxv16i8] })  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 106288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 106291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106293 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // op2
     /* 106305 */     GIR_RootConstrainSelectedInstOperands,
     /* 106306 */     // GIR_Coverage, 12835,
     /* 106306 */     GIR_EraseRootFromParent_Done,
     /* 106307 */   // Label 1635: @106307
     /* 106307 */   GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(106362), // Rule ID 17143 //
     /* 106312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106327 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 106335 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 106341 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 106343 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 106345 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op2, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$op1, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op1, ?:{ *:[nxv16i8] }:$op2)
     /* 106345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 106348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // op1
     /* 106358 */     GIR_RootToRootCopy, /*OpIdx*/1, // op2
     /* 106360 */     GIR_RootConstrainSelectedInstOperands,
     /* 106361 */     // GIR_Coverage, 17143,
     /* 106361 */     GIR_EraseRootFromParent_Done,
     /* 106362 */   // Label 1636: @106362
     /* 106362 */   GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(106405), // Rule ID 14766 //
     /* 106367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 106374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106386 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 106388 */     // (xor:{ *:[nxv16i8] } (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 106388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 106391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106393 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 106397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 106401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 106403 */     GIR_RootConstrainSelectedInstOperands,
     /* 106404 */     // GIR_Coverage, 14766,
     /* 106404 */     GIR_EraseRootFromParent_Done,
     /* 106405 */   // Label 1637: @106405
     /* 106405 */   GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(106448), // Rule ID 3214 //
     /* 106410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 106413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 106417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 106421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 106425 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 106429 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 106431 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3))  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 106431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 106434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 106436 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 106438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 106442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op3
     /* 106446 */     GIR_RootConstrainSelectedInstOperands,
     /* 106447 */     // GIR_Coverage, 3214,
     /* 106447 */     GIR_EraseRootFromParent_Done,
     /* 106448 */   // Label 1638: @106448
     /* 106448 */   GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(106463), // Rule ID 8130 //
     /* 106453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 106456 */     // (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (EOR_ZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 106456 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::EOR_ZZZ),
     /* 106461 */     GIR_RootConstrainSelectedInstOperands,
     /* 106462 */     // GIR_Coverage, 8130,
     /* 106462 */     GIR_Done,
     /* 106463 */   // Label 1639: @106463
     /* 106463 */   GIM_Reject,
     /* 106464 */ // Label 1618: @106464
     /* 106464 */ GIM_Reject,
     /* 106465 */ // Label 1438: @106465
     /* 106465 */ GIM_Reject,
     /* 106466 */ // Label 8: @106466
     /* 106466 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1646*/ GIMT_Encode4(106709),
     /* 106477 */ /*GILLT_v2s32*//*Label 1640*/ GIMT_Encode4(106505), GIMT_Encode4(0),
     /* 106485 */ /*GILLT_v4s16*//*Label 1641*/ GIMT_Encode4(106539),
     /* 106489 */ /*GILLT_v4s32*//*Label 1642*/ GIMT_Encode4(106573),
     /* 106493 */ /*GILLT_v8s8*//*Label 1643*/ GIMT_Encode4(106607),
     /* 106497 */ /*GILLT_v8s16*//*Label 1644*/ GIMT_Encode4(106641),
     /* 106501 */ /*GILLT_v16s8*//*Label 1645*/ GIMT_Encode4(106675),
     /* 106505 */ // Label 1640: @106505
     /* 106505 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(106538), // Rule ID 1396 //
     /* 106510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 106516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 106519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106523 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106527 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106531 */   // (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 106531 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv2i32),
     /* 106536 */   GIR_RootConstrainSelectedInstOperands,
     /* 106537 */   // GIR_Coverage, 1396,
     /* 106537 */   GIR_Done,
     /* 106538 */ // Label 1647: @106538
     /* 106538 */ GIM_Reject,
     /* 106539 */ // Label 1641: @106539
     /* 106539 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(106572), // Rule ID 1394 //
     /* 106544 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106547 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 106550 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 106553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106557 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106561 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106565 */   // (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 106565 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i16),
     /* 106570 */   GIR_RootConstrainSelectedInstOperands,
     /* 106571 */   // GIR_Coverage, 1394,
     /* 106571 */   GIR_Done,
     /* 106572 */ // Label 1648: @106572
     /* 106572 */ GIM_Reject,
     /* 106573 */ // Label 1642: @106573
     /* 106573 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(106606), // Rule ID 1397 //
     /* 106578 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106581 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 106584 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 106587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106591 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106595 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106599 */   // (abds:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 106599 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv4i32),
     /* 106604 */   GIR_RootConstrainSelectedInstOperands,
     /* 106605 */   // GIR_Coverage, 1397,
     /* 106605 */   GIR_Done,
     /* 106606 */ // Label 1649: @106606
     /* 106606 */ GIM_Reject,
     /* 106607 */ // Label 1643: @106607
     /* 106607 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(106640), // Rule ID 1392 //
     /* 106612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106615 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 106618 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 106621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106625 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106629 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106633 */   // (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 106633 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i8),
     /* 106638 */   GIR_RootConstrainSelectedInstOperands,
     /* 106639 */   // GIR_Coverage, 1392,
     /* 106639 */   GIR_Done,
     /* 106640 */ // Label 1650: @106640
     /* 106640 */ GIM_Reject,
     /* 106641 */ // Label 1644: @106641
     /* 106641 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(106674), // Rule ID 1395 //
     /* 106646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106649 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106652 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106659 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106663 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106667 */   // (abds:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 106667 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv8i16),
     /* 106672 */   GIR_RootConstrainSelectedInstOperands,
     /* 106673 */   // GIR_Coverage, 1395,
     /* 106673 */   GIR_Done,
     /* 106674 */ // Label 1651: @106674
     /* 106674 */ GIM_Reject,
     /* 106675 */ // Label 1645: @106675
     /* 106675 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(106708), // Rule ID 1393 //
     /* 106680 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106683 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 106686 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 106689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106693 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106697 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106701 */   // (abds:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 106701 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SABDv16i8),
     /* 106706 */   GIR_RootConstrainSelectedInstOperands,
     /* 106707 */   // GIR_Coverage, 1393,
     /* 106707 */   GIR_Done,
     /* 106708 */ // Label 1652: @106708
     /* 106708 */ GIM_Reject,
     /* 106709 */ // Label 1646: @106709
     /* 106709 */ GIM_Reject,
     /* 106710 */ // Label 9: @106710
     /* 106710 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1659*/ GIMT_Encode4(106953),
     /* 106721 */ /*GILLT_v2s32*//*Label 1653*/ GIMT_Encode4(106749), GIMT_Encode4(0),
     /* 106729 */ /*GILLT_v4s16*//*Label 1654*/ GIMT_Encode4(106783),
     /* 106733 */ /*GILLT_v4s32*//*Label 1655*/ GIMT_Encode4(106817),
     /* 106737 */ /*GILLT_v8s8*//*Label 1656*/ GIMT_Encode4(106851),
     /* 106741 */ /*GILLT_v8s16*//*Label 1657*/ GIMT_Encode4(106885),
     /* 106745 */ /*GILLT_v16s8*//*Label 1658*/ GIMT_Encode4(106919),
     /* 106749 */ // Label 1653: @106749
     /* 106749 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(106782), // Rule ID 1507 //
     /* 106754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106757 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 106760 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 106763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106767 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106771 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106775 */   // (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UABDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 106775 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv2i32),
     /* 106780 */   GIR_RootConstrainSelectedInstOperands,
     /* 106781 */   // GIR_Coverage, 1507,
     /* 106781 */   GIR_Done,
     /* 106782 */ // Label 1660: @106782
     /* 106782 */ GIM_Reject,
     /* 106783 */ // Label 1654: @106783
     /* 106783 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(106816), // Rule ID 1505 //
     /* 106788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106791 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 106794 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 106797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106801 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106805 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106809 */   // (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UABDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 106809 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i16),
     /* 106814 */   GIR_RootConstrainSelectedInstOperands,
     /* 106815 */   // GIR_Coverage, 1505,
     /* 106815 */   GIR_Done,
     /* 106816 */ // Label 1661: @106816
     /* 106816 */ GIM_Reject,
     /* 106817 */ // Label 1655: @106817
     /* 106817 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(106850), // Rule ID 1508 //
     /* 106822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 106828 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 106831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106835 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106839 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106843 */   // (abdu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UABDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 106843 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv4i32),
     /* 106848 */   GIR_RootConstrainSelectedInstOperands,
     /* 106849 */   // GIR_Coverage, 1508,
     /* 106849 */   GIR_Done,
     /* 106850 */ // Label 1662: @106850
     /* 106850 */ GIM_Reject,
     /* 106851 */ // Label 1656: @106851
     /* 106851 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(106884), // Rule ID 1503 //
     /* 106856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 106862 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 106865 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106869 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106873 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 106877 */   // (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UABDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 106877 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i8),
     /* 106882 */   GIR_RootConstrainSelectedInstOperands,
     /* 106883 */   // GIR_Coverage, 1503,
     /* 106883 */   GIR_Done,
     /* 106884 */ // Label 1663: @106884
     /* 106884 */ GIM_Reject,
     /* 106885 */ // Label 1657: @106885
     /* 106885 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(106918), // Rule ID 1506 //
     /* 106890 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106893 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 106896 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 106899 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106903 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106907 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106911 */   // (abdu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UABDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 106911 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv8i16),
     /* 106916 */   GIR_RootConstrainSelectedInstOperands,
     /* 106917 */   // GIR_Coverage, 1506,
     /* 106917 */   GIR_Done,
     /* 106918 */ // Label 1664: @106918
     /* 106918 */ GIM_Reject,
     /* 106919 */ // Label 1658: @106919
     /* 106919 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(106952), // Rule ID 1504 //
     /* 106924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 106927 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 106930 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 106933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106937 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106941 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 106945 */   // (abdu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UABDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 106945 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UABDv16i8),
     /* 106950 */   GIR_RootConstrainSelectedInstOperands,
     /* 106951 */   // GIR_Coverage, 1504,
     /* 106951 */   GIR_Done,
     /* 106952 */ // Label 1665: @106952
     /* 106952 */ GIM_Reject,
     /* 106953 */ // Label 1659: @106953
     /* 106953 */ GIM_Reject,
     /* 106954 */ // Label 10: @106954
     /* 106954 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1672*/ GIMT_Encode4(107197),
     /* 106965 */ /*GILLT_v2s32*//*Label 1666*/ GIMT_Encode4(106993), GIMT_Encode4(0),
     /* 106973 */ /*GILLT_v4s16*//*Label 1667*/ GIMT_Encode4(107027),
     /* 106977 */ /*GILLT_v4s32*//*Label 1668*/ GIMT_Encode4(107061),
     /* 106981 */ /*GILLT_v8s8*//*Label 1669*/ GIMT_Encode4(107095),
     /* 106985 */ /*GILLT_v8s16*//*Label 1670*/ GIMT_Encode4(107129),
     /* 106989 */ /*GILLT_v16s8*//*Label 1671*/ GIMT_Encode4(107163),
     /* 106993 */ // Label 1666: @106993
     /* 106993 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(107026), // Rule ID 1513 //
     /* 106998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107001 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 107004 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 107007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107011 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107015 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107019 */   // (avgflooru:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 107019 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv2i32),
     /* 107024 */   GIR_RootConstrainSelectedInstOperands,
     /* 107025 */   // GIR_Coverage, 1513,
     /* 107025 */   GIR_Done,
     /* 107026 */ // Label 1673: @107026
     /* 107026 */ GIM_Reject,
     /* 107027 */ // Label 1667: @107027
     /* 107027 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(107060), // Rule ID 1511 //
     /* 107032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 107038 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 107041 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107045 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107049 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107053 */   // (avgflooru:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 107053 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv4i16),
     /* 107058 */   GIR_RootConstrainSelectedInstOperands,
     /* 107059 */   // GIR_Coverage, 1511,
     /* 107059 */   GIR_Done,
     /* 107060 */ // Label 1674: @107060
     /* 107060 */ GIM_Reject,
     /* 107061 */ // Label 1668: @107061
     /* 107061 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(107094), // Rule ID 1514 //
     /* 107066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 107072 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 107075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107079 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107083 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107087 */   // (avgflooru:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 107087 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv4i32),
     /* 107092 */   GIR_RootConstrainSelectedInstOperands,
     /* 107093 */   // GIR_Coverage, 1514,
     /* 107093 */   GIR_Done,
     /* 107094 */ // Label 1675: @107094
     /* 107094 */ GIM_Reject,
     /* 107095 */ // Label 1669: @107095
     /* 107095 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(107128), // Rule ID 1509 //
     /* 107100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107103 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 107106 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 107109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107113 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107117 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107121 */   // (avgflooru:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 107121 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv8i8),
     /* 107126 */   GIR_RootConstrainSelectedInstOperands,
     /* 107127 */   // GIR_Coverage, 1509,
     /* 107127 */   GIR_Done,
     /* 107128 */ // Label 1676: @107128
     /* 107128 */ GIM_Reject,
     /* 107129 */ // Label 1670: @107129
     /* 107129 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(107162), // Rule ID 1512 //
     /* 107134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107137 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107140 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107147 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107151 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107155 */   // (avgflooru:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107155 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv8i16),
     /* 107160 */   GIR_RootConstrainSelectedInstOperands,
     /* 107161 */   // GIR_Coverage, 1512,
     /* 107161 */   GIR_Done,
     /* 107162 */ // Label 1677: @107162
     /* 107162 */ GIM_Reject,
     /* 107163 */ // Label 1671: @107163
     /* 107163 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(107196), // Rule ID 1510 //
     /* 107168 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107171 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 107174 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 107177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107181 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107185 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107189 */   // (avgflooru:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 107189 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UHADDv16i8),
     /* 107194 */   GIR_RootConstrainSelectedInstOperands,
     /* 107195 */   // GIR_Coverage, 1510,
     /* 107195 */   GIR_Done,
     /* 107196 */ // Label 1678: @107196
     /* 107196 */ GIM_Reject,
     /* 107197 */ // Label 1672: @107197
     /* 107197 */ GIM_Reject,
     /* 107198 */ // Label 11: @107198
     /* 107198 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(107441),
     /* 107209 */ /*GILLT_v2s32*//*Label 1679*/ GIMT_Encode4(107237), GIMT_Encode4(0),
     /* 107217 */ /*GILLT_v4s16*//*Label 1680*/ GIMT_Encode4(107271),
     /* 107221 */ /*GILLT_v4s32*//*Label 1681*/ GIMT_Encode4(107305),
     /* 107225 */ /*GILLT_v8s8*//*Label 1682*/ GIMT_Encode4(107339),
     /* 107229 */ /*GILLT_v8s16*//*Label 1683*/ GIMT_Encode4(107373),
     /* 107233 */ /*GILLT_v16s8*//*Label 1684*/ GIMT_Encode4(107407),
     /* 107237 */ // Label 1679: @107237
     /* 107237 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(107270), // Rule ID 1577 //
     /* 107242 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107245 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 107248 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 107251 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107255 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107259 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107263 */   // (avgceilu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (URHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 107263 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv2i32),
     /* 107268 */   GIR_RootConstrainSelectedInstOperands,
     /* 107269 */   // GIR_Coverage, 1577,
     /* 107269 */   GIR_Done,
     /* 107270 */ // Label 1686: @107270
     /* 107270 */ GIM_Reject,
     /* 107271 */ // Label 1680: @107271
     /* 107271 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(107304), // Rule ID 1575 //
     /* 107276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107279 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 107282 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 107285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107289 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107293 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107297 */   // (avgceilu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (URHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 107297 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv4i16),
     /* 107302 */   GIR_RootConstrainSelectedInstOperands,
     /* 107303 */   // GIR_Coverage, 1575,
     /* 107303 */   GIR_Done,
     /* 107304 */ // Label 1687: @107304
     /* 107304 */ GIM_Reject,
     /* 107305 */ // Label 1681: @107305
     /* 107305 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(107338), // Rule ID 1578 //
     /* 107310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 107316 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 107319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107323 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107327 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107331 */   // (avgceilu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (URHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 107331 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv4i32),
     /* 107336 */   GIR_RootConstrainSelectedInstOperands,
     /* 107337 */   // GIR_Coverage, 1578,
     /* 107337 */   GIR_Done,
     /* 107338 */ // Label 1688: @107338
     /* 107338 */ GIM_Reject,
     /* 107339 */ // Label 1682: @107339
     /* 107339 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(107372), // Rule ID 1573 //
     /* 107344 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107347 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 107350 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 107353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107357 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107361 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107365 */   // (avgceilu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (URHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 107365 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv8i8),
     /* 107370 */   GIR_RootConstrainSelectedInstOperands,
     /* 107371 */   // GIR_Coverage, 1573,
     /* 107371 */   GIR_Done,
     /* 107372 */ // Label 1689: @107372
     /* 107372 */ GIM_Reject,
     /* 107373 */ // Label 1683: @107373
     /* 107373 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(107406), // Rule ID 1576 //
     /* 107378 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107381 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107384 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107391 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107395 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107399 */   // (avgceilu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (URHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107399 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv8i16),
     /* 107404 */   GIR_RootConstrainSelectedInstOperands,
     /* 107405 */   // GIR_Coverage, 1576,
     /* 107405 */   GIR_Done,
     /* 107406 */ // Label 1690: @107406
     /* 107406 */ GIM_Reject,
     /* 107407 */ // Label 1684: @107407
     /* 107407 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(107440), // Rule ID 1574 //
     /* 107412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107415 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 107418 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 107421 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107425 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107429 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107433 */   // (avgceilu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (URHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 107433 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URHADDv16i8),
     /* 107438 */   GIR_RootConstrainSelectedInstOperands,
     /* 107439 */   // GIR_Coverage, 1574,
     /* 107439 */   GIR_Done,
     /* 107440 */ // Label 1691: @107440
     /* 107440 */ GIM_Reject,
     /* 107441 */ // Label 1685: @107441
     /* 107441 */ GIM_Reject,
     /* 107442 */ // Label 12: @107442
     /* 107442 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1698*/ GIMT_Encode4(107685),
     /* 107453 */ /*GILLT_v2s32*//*Label 1692*/ GIMT_Encode4(107481), GIMT_Encode4(0),
     /* 107461 */ /*GILLT_v4s16*//*Label 1693*/ GIMT_Encode4(107515),
     /* 107465 */ /*GILLT_v4s32*//*Label 1694*/ GIMT_Encode4(107549),
     /* 107469 */ /*GILLT_v8s8*//*Label 1695*/ GIMT_Encode4(107583),
     /* 107473 */ /*GILLT_v8s16*//*Label 1696*/ GIMT_Encode4(107617),
     /* 107477 */ /*GILLT_v16s8*//*Label 1697*/ GIMT_Encode4(107651),
     /* 107481 */ // Label 1692: @107481
     /* 107481 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(107514), // Rule ID 1402 //
     /* 107486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107489 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 107492 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 107495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107499 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107503 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107507 */   // (avgfloors:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 107507 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv2i32),
     /* 107512 */   GIR_RootConstrainSelectedInstOperands,
     /* 107513 */   // GIR_Coverage, 1402,
     /* 107513 */   GIR_Done,
     /* 107514 */ // Label 1699: @107514
     /* 107514 */ GIM_Reject,
     /* 107515 */ // Label 1693: @107515
     /* 107515 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(107548), // Rule ID 1400 //
     /* 107520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 107526 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 107529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107533 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107537 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107541 */   // (avgfloors:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 107541 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv4i16),
     /* 107546 */   GIR_RootConstrainSelectedInstOperands,
     /* 107547 */   // GIR_Coverage, 1400,
     /* 107547 */   GIR_Done,
     /* 107548 */ // Label 1700: @107548
     /* 107548 */ GIM_Reject,
     /* 107549 */ // Label 1694: @107549
     /* 107549 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(107582), // Rule ID 1403 //
     /* 107554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107557 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 107560 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 107563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107567 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107571 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107575 */   // (avgfloors:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 107575 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv4i32),
     /* 107580 */   GIR_RootConstrainSelectedInstOperands,
     /* 107581 */   // GIR_Coverage, 1403,
     /* 107581 */   GIR_Done,
     /* 107582 */ // Label 1701: @107582
     /* 107582 */ GIM_Reject,
     /* 107583 */ // Label 1695: @107583
     /* 107583 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(107616), // Rule ID 1398 //
     /* 107588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107591 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 107594 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 107597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107601 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107605 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107609 */   // (avgfloors:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 107609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv8i8),
     /* 107614 */   GIR_RootConstrainSelectedInstOperands,
     /* 107615 */   // GIR_Coverage, 1398,
     /* 107615 */   GIR_Done,
     /* 107616 */ // Label 1702: @107616
     /* 107616 */ GIM_Reject,
     /* 107617 */ // Label 1696: @107617
     /* 107617 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(107650), // Rule ID 1401 //
     /* 107622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107625 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107628 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107639 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107643 */   // (avgfloors:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107643 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv8i16),
     /* 107648 */   GIR_RootConstrainSelectedInstOperands,
     /* 107649 */   // GIR_Coverage, 1401,
     /* 107649 */   GIR_Done,
     /* 107650 */ // Label 1703: @107650
     /* 107650 */ GIM_Reject,
     /* 107651 */ // Label 1697: @107651
     /* 107651 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(107684), // Rule ID 1399 //
     /* 107656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 107662 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 107665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107669 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107673 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107677 */   // (avgfloors:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 107677 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SHADDv16i8),
     /* 107682 */   GIR_RootConstrainSelectedInstOperands,
     /* 107683 */   // GIR_Coverage, 1399,
     /* 107683 */   GIR_Done,
     /* 107684 */ // Label 1704: @107684
     /* 107684 */ GIM_Reject,
     /* 107685 */ // Label 1698: @107685
     /* 107685 */ GIM_Reject,
     /* 107686 */ // Label 13: @107686
     /* 107686 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 1711*/ GIMT_Encode4(107929),
     /* 107697 */ /*GILLT_v2s32*//*Label 1705*/ GIMT_Encode4(107725), GIMT_Encode4(0),
     /* 107705 */ /*GILLT_v4s16*//*Label 1706*/ GIMT_Encode4(107759),
     /* 107709 */ /*GILLT_v4s32*//*Label 1707*/ GIMT_Encode4(107793),
     /* 107713 */ /*GILLT_v8s8*//*Label 1708*/ GIMT_Encode4(107827),
     /* 107717 */ /*GILLT_v8s16*//*Label 1709*/ GIMT_Encode4(107861),
     /* 107721 */ /*GILLT_v16s8*//*Label 1710*/ GIMT_Encode4(107895),
     /* 107725 */ // Label 1705: @107725
     /* 107725 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(107758), // Rule ID 1474 //
     /* 107730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107733 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 107736 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 107739 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107743 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107747 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107751 */   // (avgceils:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SRHADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 107751 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv2i32),
     /* 107756 */   GIR_RootConstrainSelectedInstOperands,
     /* 107757 */   // GIR_Coverage, 1474,
     /* 107757 */   GIR_Done,
     /* 107758 */ // Label 1712: @107758
     /* 107758 */ GIM_Reject,
     /* 107759 */ // Label 1706: @107759
     /* 107759 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(107792), // Rule ID 1472 //
     /* 107764 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107767 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 107770 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 107773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107777 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107781 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107785 */   // (avgceils:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SRHADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 107785 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv4i16),
     /* 107790 */   GIR_RootConstrainSelectedInstOperands,
     /* 107791 */   // GIR_Coverage, 1472,
     /* 107791 */   GIR_Done,
     /* 107792 */ // Label 1713: @107792
     /* 107792 */ GIM_Reject,
     /* 107793 */ // Label 1707: @107793
     /* 107793 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(107826), // Rule ID 1475 //
     /* 107798 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107801 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 107804 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 107807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107811 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107815 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107819 */   // (avgceils:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SRHADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 107819 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv4i32),
     /* 107824 */   GIR_RootConstrainSelectedInstOperands,
     /* 107825 */   // GIR_Coverage, 1475,
     /* 107825 */   GIR_Done,
     /* 107826 */ // Label 1714: @107826
     /* 107826 */ GIM_Reject,
     /* 107827 */ // Label 1708: @107827
     /* 107827 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(107860), // Rule ID 1470 //
     /* 107832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 107838 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 107841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107845 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107849 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 107853 */   // (avgceils:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SRHADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 107853 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv8i8),
     /* 107858 */   GIR_RootConstrainSelectedInstOperands,
     /* 107859 */   // GIR_Coverage, 1470,
     /* 107859 */   GIR_Done,
     /* 107860 */ // Label 1715: @107860
     /* 107860 */ GIM_Reject,
     /* 107861 */ // Label 1709: @107861
     /* 107861 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(107894), // Rule ID 1473 //
     /* 107866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107869 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 107872 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 107875 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107879 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107883 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107887 */   // (avgceils:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SRHADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 107887 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv8i16),
     /* 107892 */   GIR_RootConstrainSelectedInstOperands,
     /* 107893 */   // GIR_Coverage, 1473,
     /* 107893 */   GIR_Done,
     /* 107894 */ // Label 1716: @107894
     /* 107894 */ GIM_Reject,
     /* 107895 */ // Label 1710: @107895
     /* 107895 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(107928), // Rule ID 1471 //
     /* 107900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 107903 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 107906 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 107909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107913 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107917 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 107921 */   // (avgceils:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SRHADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 107921 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRHADDv16i8),
     /* 107926 */   GIR_RootConstrainSelectedInstOperands,
     /* 107927 */   // GIR_Coverage, 1471,
     /* 107927 */   GIR_Done,
     /* 107928 */ // Label 1717: @107928
     /* 107928 */ GIM_Reject,
     /* 107929 */ // Label 1711: @107929
     /* 107929 */ GIM_Reject,
     /* 107930 */ // Label 14: @107930
     /* 107930 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(118543),
     /* 107935 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 107938 */   GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(23), /*)*//*default:*//*Label 1730*/ GIMT_Encode4(118542),
     /* 107949 */   /*GILLT_v2s64*//*Label 1719*/ GIMT_Encode4(108017), GIMT_Encode4(0),
     /* 107957 */   /*GILLT_v4s32*//*Label 1720*/ GIMT_Encode4(108538), GIMT_Encode4(0),
     /* 107965 */   /*GILLT_v8s16*//*Label 1721*/ GIMT_Encode4(112044),
     /* 107969 */   /*GILLT_v16s8*//*Label 1722*/ GIMT_Encode4(115451), GIMT_Encode4(0),
     /* 107977 */   /*GILLT_nxv2s1*//*Label 1723*/ GIMT_Encode4(118360), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 107993 */   /*GILLT_nxv4s1*//*Label 1724*/ GIMT_Encode4(118386),
     /* 107997 */   /*GILLT_nxv4s16*//*Label 1725*/ GIMT_Encode4(118412),
     /* 108001 */   /*GILLT_nxv4s32*//*Label 1726*/ GIMT_Encode4(118438),
     /* 108005 */   /*GILLT_nxv8s1*//*Label 1727*/ GIMT_Encode4(118464),
     /* 108009 */   /*GILLT_nxv8s16*//*Label 1728*/ GIMT_Encode4(118490),
     /* 108013 */   /*GILLT_nxv16s1*//*Label 1729*/ GIMT_Encode4(118516),
     /* 108017 */   // Label 1719: @108017
     /* 108017 */   GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(108537),
     /* 108022 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 108025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 108028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108032 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108036 */     GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(108098), // Rule ID 6407 //
     /* 108041 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108045 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 108051 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 108053 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108055 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1i64] }:$Rn), dsub:{ *:[i32] })
     /* 108055 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 108058 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 108062 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108067 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 108071 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 108073 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 108076 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108078 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 108081 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108084 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 108087 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108092 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108097 */       // GIR_Coverage, 6407,
     /* 108097 */       GIR_EraseRootFromParent_Done,
     /* 108098 */     // Label 1732: @108098
     /* 108098 */     GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(108160), // Rule ID 6411 //
     /* 108103 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108107 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 108113 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 108115 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108117 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v1f64] }:$Rn), dsub:{ *:[i32] })
     /* 108117 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 108120 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 108124 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108129 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 108133 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 108135 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 108138 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108140 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 108143 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108146 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 108149 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108154 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108159 */       // GIR_Coverage, 6411,
     /* 108159 */       GIR_EraseRootFromParent_Done,
     /* 108160 */     // Label 1733: @108160
     /* 108160 */     GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(108218), // Rule ID 6408 //
     /* 108165 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108169 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 108173 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108175 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rn, (undef:{ *:[v1i64] }))  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] })
     /* 108175 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 108178 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108182 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108187 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 108189 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108192 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108194 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108197 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 108199 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 108202 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108207 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108212 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108217 */       // GIR_Coverage, 6408,
     /* 108217 */       GIR_EraseRootFromParent_Done,
     /* 108218 */     // Label 1734: @108218
     /* 108218 */     GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(108276), // Rule ID 6412 //
     /* 108223 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108227 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 108231 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 108233 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rn, (undef:{ *:[v1f64] }))  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] })
     /* 108233 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 108236 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108240 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108245 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 108247 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108250 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108252 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108255 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 108257 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 108260 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108265 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108270 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108275 */       // GIR_Coverage, 6412,
     /* 108275 */       GIR_EraseRootFromParent_Done,
     /* 108276 */     // Label 1735: @108276
     /* 108276 */     GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(108406), // Rule ID 6406 //
     /* 108281 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108285 */       // (concat_vectors:{ *:[v2i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn)  =>  (INSvi64lane:{ *:[v2i64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 108285 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 108288 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108292 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108297 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 108299 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 108302 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108306 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108311 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 108314 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 108318 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 108321 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108326 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108331 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108336 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 108339 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108343 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108348 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 108350 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 108353 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108357 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108362 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 108365 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 108369 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 108372 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108377 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108382 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108387 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 108390 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108392 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108395 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 108398 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 108401 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 108404 */       GIR_RootConstrainSelectedInstOperands,
     /* 108405 */       // GIR_Coverage, 6406,
     /* 108405 */       GIR_EraseRootFromParent_Done,
     /* 108406 */     // Label 1736: @108406
     /* 108406 */     GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(108536), // Rule ID 6410 //
     /* 108411 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108415 */       // (concat_vectors:{ *:[v2f64] } V64:{ *:[v1f64] }:$Rd, V64:{ *:[v1f64] }:$Rn)  =>  (INSvi64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 108415 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 108418 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108422 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108427 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 108429 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 108432 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108436 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108441 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 108444 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 108448 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 108451 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108456 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108461 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108466 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 108469 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 108473 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108478 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 108480 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 108483 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 108487 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108492 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 108495 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 108499 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 108502 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108507 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108512 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108517 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 108520 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108522 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108525 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 108528 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 108531 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 108534 */       GIR_RootConstrainSelectedInstOperands,
     /* 108535 */       // GIR_Coverage, 6410,
     /* 108535 */       GIR_EraseRootFromParent_Done,
     /* 108536 */     // Label 1737: @108536
     /* 108536 */     GIM_Reject,
     /* 108537 */   // Label 1731: @108537
     /* 108537 */   GIM_Reject,
     /* 108538 */   // Label 1720: @108538
     /* 108538 */   GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(112043),
     /* 108543 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 108546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 108549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108553 */     GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(108682), // Rule ID 6030 //
     /* 108558 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108562 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108566 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 108570 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108574 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 108578 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 108582 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108586 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 108590 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 108594 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108598 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 108602 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108607 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 108611 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 108617 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 108619 */       // MIs[2] Operand 2
     /* 108619 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 108630 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 108632 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 108632 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 108635 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 108639 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108644 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 108647 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 108651 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 108654 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108659 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108664 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 108667 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108669 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108672 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 108676 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 108680 */       GIR_RootConstrainSelectedInstOperands,
     /* 108681 */       // GIR_Coverage, 6030,
     /* 108681 */       GIR_EraseRootFromParent_Done,
     /* 108682 */     // Label 1739: @108682
     /* 108682 */     GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(108804), // Rule ID 6026 //
     /* 108687 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108691 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108695 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 108699 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108703 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 108707 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 108711 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108715 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 108719 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 108723 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108727 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 108731 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108736 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108741 */       // MIs[2] Operand 2
     /* 108741 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 108752 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 108754 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (ADDHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 108754 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 108757 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 108761 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108766 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 108769 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 108773 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 108776 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108781 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108786 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
     /* 108789 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108791 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108794 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 108798 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 108802 */       GIR_RootConstrainSelectedInstOperands,
     /* 108803 */       // GIR_Coverage, 6026,
     /* 108803 */       GIR_EraseRootFromParent_Done,
     /* 108804 */     // Label 1740: @108804
     /* 108804 */     GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(108926), // Rule ID 6028 //
     /* 108809 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108813 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 108817 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 108821 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108825 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 108829 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 108833 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108837 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 108841 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 108845 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108849 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 108853 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108858 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108863 */       // MIs[2] Operand 2
     /* 108863 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 108874 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 108876 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] })))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 108876 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 108879 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 108883 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 108888 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 108891 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 108895 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 108898 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108903 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 108908 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 108911 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 108913 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 108916 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 108920 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 108924 */       GIR_RootConstrainSelectedInstOperands,
     /* 108925 */       // GIR_Coverage, 6028,
     /* 108925 */       GIR_EraseRootFromParent_Done,
     /* 108926 */     // Label 1741: @108926
     /* 108926 */     GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(109028), // Rule ID 6176 //
     /* 108931 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 108935 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 108939 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108943 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 108947 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 108951 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108955 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 108960 */       // MIs[2] Operand 2
     /* 108960 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(32),
     /* 108971 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 108975 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 108979 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108983 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 108987 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 108991 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 108995 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109000 */       // MIs[4] Operand 2
     /* 109000 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(32),
     /* 109011 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 109013 */       // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })), (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vm, 32:{ *:[i32] })))  =>  (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 109013 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 109016 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 109018 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 109022 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 109026 */       GIR_RootConstrainSelectedInstOperands,
     /* 109027 */       // GIR_Coverage, 6176,
     /* 109027 */       GIR_EraseRootFromParent_Done,
     /* 109028 */     // Label 1742: @109028
     /* 109028 */     GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(109160), // Rule ID 6976 //
     /* 109033 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109037 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109041 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 109045 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 109048 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 109053 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 109057 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109062 */       // MIs[1] Operand 3
     /* 109062 */       GIM_CheckLiteralInt, /*MI*/1, /*Op*/3, GIMT_Encode8(32),
     /* 109073 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 109075 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vd, (intrinsic_wo_chain:{ *:[v2i32] } 682:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] }))  =>  (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
     /* 109075 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s64,
     /* 109078 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 109082 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109087 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 109090 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 109092 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109095 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109099 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109104 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109106 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109109 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109113 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109118 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109121 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 109125 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109128 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109133 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109138 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109143 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
     /* 109146 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109148 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109151 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 109155 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 109158 */       GIR_RootConstrainSelectedInstOperands,
     /* 109159 */       // GIR_Coverage, 6976,
     /* 109159 */       GIR_EraseRootFromParent_Done,
     /* 109160 */     // Label 1743: @109160
     /* 109160 */     GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(109202), // Rule ID 6417 //
     /* 109165 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 109172 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 109179 */       // (concat_vectors:{ *:[v4i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (INSvi64lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] })
     /* 109179 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 109182 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109184 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 109189 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 109192 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 109197 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 109200 */       GIR_RootConstrainSelectedInstOperands,
     /* 109201 */       // GIR_Coverage, 6417,
     /* 109201 */       GIR_EraseRootFromParent_Done,
     /* 109202 */     // Label 1744: @109202
     /* 109202 */     GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(109244), // Rule ID 6421 //
     /* 109207 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 109214 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 109221 */       // (concat_vectors:{ *:[v4f32] } (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn), (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm))  =>  (INSvi64lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] })
     /* 109221 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 109224 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109226 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 109231 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 109234 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 109239 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 109242 */       GIR_RootConstrainSelectedInstOperands,
     /* 109243 */       // GIR_Coverage, 6421,
     /* 109243 */       GIR_EraseRootFromParent_Done,
     /* 109244 */     // Label 1745: @109244
     /* 109244 */     GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(109360), // Rule ID 2616 //
     /* 109249 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109252 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109256 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109260 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 109264 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 109267 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 109272 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 109276 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109281 */       // MIs[1] imm
     /* 109281 */       GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 109284 */       GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109289 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 109291 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 682:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (RSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 109291 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109294 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109298 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109303 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109305 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109308 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109312 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109317 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109320 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109324 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109327 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109332 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109337 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109342 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i32_shift),
     /* 109345 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109347 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109350 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 109354 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // imm
     /* 109358 */       GIR_RootConstrainSelectedInstOperands,
     /* 109359 */       // GIR_Coverage, 2616,
     /* 109359 */       GIR_EraseRootFromParent_Done,
     /* 109360 */     // Label 1746: @109360
     /* 109360 */     GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(109480), // Rule ID 6946 //
     /* 109365 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109368 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109372 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109376 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 109380 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109384 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109388 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 109392 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109396 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109401 */       // MIs[2] imm
     /* 109401 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 109404 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109409 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 109411 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 109411 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109414 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109418 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109423 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109425 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109428 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109432 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109437 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109440 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109444 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109447 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109452 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109457 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109462 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
     /* 109465 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109467 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109470 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 109474 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 109478 */       GIR_RootConstrainSelectedInstOperands,
     /* 109479 */       // GIR_Coverage, 6946,
     /* 109479 */       GIR_EraseRootFromParent_Done,
     /* 109480 */     // Label 1747: @109480
     /* 109480 */     GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(109597), // Rule ID 6982 //
     /* 109485 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109489 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109493 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 109497 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109501 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109505 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 109509 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109513 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109518 */       // MIs[2] imm
     /* 109518 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 109521 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109526 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 109528 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 109528 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109531 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109535 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109540 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109542 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109545 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109549 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109554 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109557 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109561 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109564 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109569 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109574 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109579 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i32_shift),
     /* 109582 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109584 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109587 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 109591 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 109595 */       GIR_RootConstrainSelectedInstOperands,
     /* 109596 */       // GIR_Coverage, 6982,
     /* 109596 */       GIR_EraseRootFromParent_Done,
     /* 109597 */     // Label 1748: @109597
     /* 109597 */     GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(109717), // Rule ID 6949 //
     /* 109602 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109605 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109609 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109613 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 109617 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109621 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109625 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 109629 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109633 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109638 */       // MIs[2] imm
     /* 109638 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 109641 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109646 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 109648 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_s:{ *:[v2i32] } (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 109648 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109651 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109655 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109660 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109662 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109665 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109669 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109674 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109677 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109681 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109684 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109689 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109694 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109699 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv4i32_shift),
     /* 109702 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109704 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109707 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 109711 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 109715 */       GIR_RootConstrainSelectedInstOperands,
     /* 109716 */       // GIR_Coverage, 6949,
     /* 109716 */       GIR_EraseRootFromParent_Done,
     /* 109717 */     // Label 1749: @109717
     /* 109717 */     GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(109837), // Rule ID 6955 //
     /* 109722 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109725 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109729 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109733 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 109737 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109741 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109745 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 109749 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109753 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109758 */       // MIs[2] imm
     /* 109758 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 109761 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109766 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 109768 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_s:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 109768 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109771 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109775 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109780 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109782 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109785 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109789 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109794 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109797 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109801 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109804 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109809 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109814 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109819 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv4i32_shift),
     /* 109822 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109824 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109827 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 109831 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 109835 */       GIR_RootConstrainSelectedInstOperands,
     /* 109836 */       // GIR_Coverage, 6955,
     /* 109836 */       GIR_EraseRootFromParent_Done,
     /* 109837 */     // Label 1750: @109837
     /* 109837 */     GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(109957), // Rule ID 6952 //
     /* 109842 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109845 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109849 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109853 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 109857 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109861 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109865 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 109869 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109873 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109878 */       // MIs[2] imm
     /* 109878 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 109881 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 109886 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 109888 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_u:{ *:[v2i32] } (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SQRSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 109888 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 109891 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 109895 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109900 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 109902 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 109905 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 109909 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 109914 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 109917 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 109921 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 109924 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109929 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109934 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109939 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv4i32_shift),
     /* 109942 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 109944 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 109947 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 109951 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 109955 */       GIR_RootConstrainSelectedInstOperands,
     /* 109956 */       // GIR_Coverage, 6952,
     /* 109956 */       GIR_EraseRootFromParent_Done,
     /* 109957 */     // Label 1751: @109957
     /* 109957 */     GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(110077), // Rule ID 6958 //
     /* 109962 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 109965 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 109969 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 109973 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 109977 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109981 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 109985 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 109989 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 109993 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 109998 */       // MIs[2] imm
     /* 109998 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 110001 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 110006 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 110008 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_u:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (SQSHRUNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 110008 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110011 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110015 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110020 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110022 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110025 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110029 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110034 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110037 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110041 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110044 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110049 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110054 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110059 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv4i32_shift),
     /* 110062 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110064 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110067 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 110071 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 110075 */       GIR_RootConstrainSelectedInstOperands,
     /* 110076 */       // GIR_Coverage, 6958,
     /* 110076 */       GIR_EraseRootFromParent_Done,
     /* 110077 */     // Label 1752: @110077
     /* 110077 */     GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(110197), // Rule ID 6961 //
     /* 110082 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110085 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110089 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110093 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 110097 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110101 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 110105 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 110109 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110113 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110118 */       // MIs[2] imm
     /* 110118 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 110121 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 110126 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 110128 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncusat_u:{ *:[v2i32] } (AArch64urshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (UQRSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 110128 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110131 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110135 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110140 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110142 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110145 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110149 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110154 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110157 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110161 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110164 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110169 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110174 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110179 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv4i32_shift),
     /* 110182 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110184 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110187 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 110191 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 110195 */       GIR_RootConstrainSelectedInstOperands,
     /* 110196 */       // GIR_Coverage, 6961,
     /* 110196 */       GIR_EraseRootFromParent_Done,
     /* 110197 */     // Label 1753: @110197
     /* 110197 */     GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(110317), // Rule ID 6964 //
     /* 110202 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110205 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110209 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110213 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 110217 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110221 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 110225 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 110229 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110233 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110238 */       // MIs[2] imm
     /* 110238 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 110241 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 110246 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 110248 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncusat_u:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)))  =>  (UQSHRNv4i32_shift:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 110248 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110251 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110255 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110260 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110262 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110265 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110269 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110274 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110277 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110281 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110284 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110289 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110294 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110299 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv4i32_shift),
     /* 110302 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110304 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110307 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 110311 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 110315 */       GIR_RootConstrainSelectedInstOperands,
     /* 110316 */       // GIR_Coverage, 6964,
     /* 110316 */       GIR_EraseRootFromParent_Done,
     /* 110317 */     // Label 1754: @110317
     /* 110317 */     GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(110434), // Rule ID 2531 //
     /* 110322 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110325 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110329 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110333 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 110337 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 110340 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 110345 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 110349 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 110353 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110358 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110363 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110365 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 593:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (ADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 110365 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110368 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110372 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110377 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110379 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110382 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110386 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110391 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110394 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110398 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110401 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110406 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110411 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110416 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v4i32),
     /* 110419 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110421 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110424 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 110428 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 110432 */       GIR_RootConstrainSelectedInstOperands,
     /* 110433 */       // GIR_Coverage, 2531,
     /* 110433 */       GIR_EraseRootFromParent_Done,
     /* 110434 */     // Label 1755: @110434
     /* 110434 */     GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(110551), // Rule ID 5946 //
     /* 110439 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110442 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110446 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110450 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 110454 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 110457 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 110462 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 110466 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 110470 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110475 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110480 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110482 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 739:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (SUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 110482 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110485 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110489 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110494 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110496 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110499 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110503 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110508 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110511 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110515 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110518 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110523 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110528 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110533 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v4i32),
     /* 110536 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110538 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110541 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 110545 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 110549 */       GIR_RootConstrainSelectedInstOperands,
     /* 110550 */       // GIR_Coverage, 5946,
     /* 110550 */       GIR_EraseRootFromParent_Done,
     /* 110551 */     // Label 1756: @110551
     /* 110551 */     GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(110668), // Rule ID 5949 //
     /* 110556 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110559 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110563 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110567 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 110571 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 110574 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 110579 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 110583 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 110587 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110592 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110597 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110599 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 681:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (RADDHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 110599 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110602 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110606 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110611 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110613 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110616 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110620 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110625 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110628 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110632 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110635 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110640 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110645 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110650 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v4i32),
     /* 110653 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110655 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110658 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 110662 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 110666 */       GIR_RootConstrainSelectedInstOperands,
     /* 110667 */       // GIR_Coverage, 5949,
     /* 110667 */       GIR_EraseRootFromParent_Done,
     /* 110668 */     // Label 1757: @110668
     /* 110668 */     GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(110785), // Rule ID 5952 //
     /* 110673 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110676 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110680 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110684 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 110688 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 110691 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 110696 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 110700 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 110704 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110709 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110714 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110716 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (intrinsic_wo_chain:{ *:[v2i32] } 683:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm))  =>  (RSUBHNv2i64_v4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 110716 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110719 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110723 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110728 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110730 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110733 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110737 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110742 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110745 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110749 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110752 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110757 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110762 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110767 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v4i32),
     /* 110770 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110772 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110775 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 110779 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 110783 */       GIR_RootConstrainSelectedInstOperands,
     /* 110784 */       // GIR_Coverage, 5952,
     /* 110784 */       GIR_EraseRootFromParent_Done,
     /* 110785 */     // Label 1758: @110785
     /* 110785 */     GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(110889), // Rule ID 2527 //
     /* 110790 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 110793 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110797 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110801 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 110805 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 110808 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
     /* 110813 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 110817 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110822 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110824 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (intrinsic_wo_chain:{ *:[v2f32] } 615:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn))  =>  (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
     /* 110824 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 110827 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 110831 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110836 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 110838 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 110841 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 110845 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110850 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 110853 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 110857 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 110860 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110865 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110870 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110875 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv4f32),
     /* 110878 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110880 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110883 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 110887 */       GIR_RootConstrainSelectedInstOperands,
     /* 110888 */       // GIR_Coverage, 2527,
     /* 110888 */       GIR_EraseRootFromParent_Done,
     /* 110889 */     // Label 1759: @110889
     /* 110889 */     GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(110945), // Rule ID 6109 //
     /* 110894 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 110898 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 110902 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110906 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110911 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 110915 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 110919 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 110923 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 110928 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 110930 */       // (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm))  =>  (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 110930 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 110933 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 110935 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 110939 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 110943 */       GIR_RootConstrainSelectedInstOperands,
     /* 110944 */       // GIR_Coverage, 6109,
     /* 110944 */       GIR_EraseRootFromParent_Done,
     /* 110945 */     // Label 1760: @110945
     /* 110945 */     GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(111011), // Rule ID 6415 //
     /* 110950 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 110954 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 110958 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 110964 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 110966 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 110968 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 110968 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 110971 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 110975 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 110980 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 110984 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 110986 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 110989 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 110991 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 110994 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 110997 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 111000 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111005 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111010 */       // GIR_Coverage, 6415,
     /* 111010 */       GIR_EraseRootFromParent_Done,
     /* 111011 */     // Label 1761: @111011
     /* 111011 */     GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(111077), // Rule ID 6419 //
     /* 111016 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111020 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111024 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 111030 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 111032 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111034 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v2f32] }:$Rn), dsub:{ *:[i32] })
     /* 111034 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 111037 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 111041 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111046 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 111050 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111052 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 111055 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111057 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 111060 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111063 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 111066 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111071 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111076 */       // GIR_Coverage, 6419,
     /* 111076 */       GIR_EraseRootFromParent_Done,
     /* 111077 */     // Label 1762: @111077
     /* 111077 */     GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(111170), // Rule ID 4985 //
     /* 111082 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111086 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111090 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /* 111094 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111098 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111103 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111105 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn))  =>  (FCVTNv4i32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
     /* 111105 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111108 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111112 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111117 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111119 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111122 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111126 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111131 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111134 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111138 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111141 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111146 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111151 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111156 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i32),
     /* 111159 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111161 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111164 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111168 */       GIR_RootConstrainSelectedInstOperands,
     /* 111169 */       // GIR_Coverage, 4985,
     /* 111169 */       GIR_EraseRootFromParent_Done,
     /* 111170 */     // Label 1763: @111170
     /* 111170 */     GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(111266), // Rule ID 2528 //
     /* 111175 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 111178 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111182 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111186 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_FPTRUNC_ODD),
     /* 111190 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111194 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111199 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111201 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, (AArch64fcvtxn_n:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn))  =>  (FCVTXNv4f32:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rn)
     /* 111201 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111204 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111208 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111213 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111215 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111218 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111222 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111227 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111230 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111234 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111237 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111242 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111247 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111252 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv4f32),
     /* 111255 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111257 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111260 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111264 */       GIR_RootConstrainSelectedInstOperands,
     /* 111265 */       // GIR_Coverage, 2528,
     /* 111265 */       GIR_EraseRootFromParent_Done,
     /* 111266 */     // Label 1764: @111266
     /* 111266 */     GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(111362), // Rule ID 5032 //
     /* 111271 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 111274 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111278 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111282 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 111286 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111290 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111295 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111297 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn))  =>  (XTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
     /* 111297 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111300 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111304 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111309 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111311 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111314 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111318 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111323 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111326 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111330 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111333 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111338 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111343 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111348 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i32),
     /* 111351 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111353 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111356 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111360 */       GIR_RootConstrainSelectedInstOperands,
     /* 111361 */       // GIR_Coverage, 5032,
     /* 111361 */       GIR_EraseRootFromParent_Done,
     /* 111362 */     // Label 1765: @111362
     /* 111362 */     GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(111458), // Rule ID 2524 //
     /* 111367 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 111370 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111374 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111378 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 111382 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111386 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111391 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111393 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_s:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn))  =>  (SQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
     /* 111393 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111396 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111400 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111405 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111407 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111410 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111414 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111419 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111422 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111426 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111429 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111434 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111439 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111444 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv4i32),
     /* 111447 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111449 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111452 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111456 */       GIR_RootConstrainSelectedInstOperands,
     /* 111457 */       // GIR_Coverage, 2524,
     /* 111457 */       GIR_EraseRootFromParent_Done,
     /* 111458 */     // Label 1766: @111458
     /* 111458 */     GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(111554), // Rule ID 5026 //
     /* 111463 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 111466 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111470 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111474 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 111478 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111482 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111487 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111489 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncssat_u:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn))  =>  (SQXTUNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
     /* 111489 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111492 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111496 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111501 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111503 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111506 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111510 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111515 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111518 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111522 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111525 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111530 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111535 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111540 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv4i32),
     /* 111543 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111545 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111548 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111552 */       GIR_RootConstrainSelectedInstOperands,
     /* 111553 */       // GIR_Coverage, 5026,
     /* 111553 */       GIR_EraseRootFromParent_Done,
     /* 111554 */     // Label 1767: @111554
     /* 111554 */     GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(111650), // Rule ID 5029 //
     /* 111559 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 111562 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111566 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111570 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 111574 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 111578 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111583 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111585 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, (truncusat_u:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn))  =>  (UQXTNv4i32:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v2i64] }:$Rn)
     /* 111585 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111588 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111592 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111597 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111599 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111602 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111606 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111611 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111614 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111618 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111621 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111626 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111631 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111636 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv4i32),
     /* 111639 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111641 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111644 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 111648 */       GIR_RootConstrainSelectedInstOperands,
     /* 111649 */       // GIR_Coverage, 5029,
     /* 111649 */       GIR_EraseRootFromParent_Done,
     /* 111650 */     // Label 1768: @111650
     /* 111650 */     GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(111712), // Rule ID 6416 //
     /* 111655 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111659 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111663 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 111667 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111669 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rn, (undef:{ *:[v2i32] }))  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] })
     /* 111669 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 111672 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111676 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111681 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111683 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111686 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111688 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111691 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 111693 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 111696 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111701 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111706 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111711 */       // GIR_Coverage, 6416,
     /* 111711 */       GIR_EraseRootFromParent_Done,
     /* 111712 */     // Label 1769: @111712
     /* 111712 */     GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(111774), // Rule ID 6420 //
     /* 111717 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111721 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 111725 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 111729 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 111731 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rn, (undef:{ *:[v2f32] }))  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] })
     /* 111731 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 111734 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111738 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111743 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 111745 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111748 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111750 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111753 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 111755 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 111758 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111763 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111768 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111773 */       // GIR_Coverage, 6420,
     /* 111773 */       GIR_EraseRootFromParent_Done,
     /* 111774 */     // Label 1770: @111774
     /* 111774 */     GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(111908), // Rule ID 6414 //
     /* 111779 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111783 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111787 */       // (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (INSvi64lane:{ *:[v4i32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 111787 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 111790 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111794 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111799 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 111801 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 111804 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111808 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111813 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 111816 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 111820 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 111823 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111828 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111833 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111838 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111841 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111845 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111850 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111852 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111855 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111859 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111864 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 111867 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 111871 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 111874 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111879 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111884 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111889 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 111892 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 111894 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 111897 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 111900 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 111903 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 111906 */       GIR_RootConstrainSelectedInstOperands,
     /* 111907 */       // GIR_Coverage, 6414,
     /* 111907 */       GIR_EraseRootFromParent_Done,
     /* 111908 */     // Label 1771: @111908
     /* 111908 */     GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(112042), // Rule ID 6418 //
     /* 111913 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111917 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111921 */       // (concat_vectors:{ *:[v4f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn)  =>  (INSvi64lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 111921 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 111924 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111928 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111933 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 111935 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 111938 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111942 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111947 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 111950 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 111954 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 111957 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111962 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 111967 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 111972 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 111975 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 111979 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111984 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 111986 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 111989 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 111993 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 111998 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 112001 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112005 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112008 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112013 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112018 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112023 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 112026 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112028 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112031 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 112034 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 112037 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 112040 */       GIR_RootConstrainSelectedInstOperands,
     /* 112041 */       // GIR_Coverage, 6418,
     /* 112041 */       GIR_EraseRootFromParent_Done,
     /* 112042 */     // Label 1772: @112042
     /* 112042 */     GIM_Reject,
     /* 112043 */   // Label 1738: @112043
     /* 112043 */   GIM_Reject,
     /* 112044 */   // Label 1721: @112044
     /* 112044 */   GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(115450),
     /* 112049 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 112052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 112055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112059 */     GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(112188), // Rule ID 6024 //
     /* 112064 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112068 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112072 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112076 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112080 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 112084 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 112088 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112092 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 112096 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 112100 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112104 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 112108 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112113 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 112117 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 112123 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 112125 */       // MIs[2] Operand 2
     /* 112125 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 112136 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 112138 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 112138 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112141 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 112145 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112150 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 112153 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112157 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112160 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112165 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112170 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 112173 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112175 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112178 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 112182 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 112186 */       GIR_RootConstrainSelectedInstOperands,
     /* 112187 */       // GIR_Coverage, 6024,
     /* 112187 */       GIR_EraseRootFromParent_Done,
     /* 112188 */     // Label 1774: @112188
     /* 112188 */     GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(112310), // Rule ID 6020 //
     /* 112193 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112197 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112201 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112205 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112209 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 112213 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 112217 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112221 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 112225 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 112229 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112233 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 112237 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112242 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112247 */       // MIs[2] Operand 2
     /* 112247 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 112258 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 112260 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (ADDHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 112260 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112263 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 112267 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112272 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 112275 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112279 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112282 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112287 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112292 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
     /* 112295 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112297 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112300 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 112304 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 112308 */       GIR_RootConstrainSelectedInstOperands,
     /* 112309 */       // GIR_Coverage, 6020,
     /* 112309 */       GIR_EraseRootFromParent_Done,
     /* 112310 */     // Label 1775: @112310
     /* 112310 */     GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(112432), // Rule ID 6022 //
     /* 112315 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112319 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112323 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112327 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112331 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 112335 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 112339 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112343 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 112347 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 112351 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112355 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 112359 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112364 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112369 */       // MIs[2] Operand 2
     /* 112369 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 112380 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 112382 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] })))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 112382 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112385 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 112389 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112394 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 112397 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112401 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112404 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112409 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112414 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 112417 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112419 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112422 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 112426 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 112430 */       GIR_RootConstrainSelectedInstOperands,
     /* 112431 */       // GIR_Coverage, 6022,
     /* 112431 */       GIR_EraseRootFromParent_Done,
     /* 112432 */     // Label 1776: @112432
     /* 112432 */     GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(112534), // Rule ID 6175 //
     /* 112437 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 112441 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112445 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112449 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 112453 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 112457 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112461 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112466 */       // MIs[2] Operand 2
     /* 112466 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
     /* 112477 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 112481 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112485 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112489 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 112493 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 112497 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112501 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112506 */       // MIs[4] Operand 2
     /* 112506 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(16),
     /* 112517 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 112519 */       // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })), (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vm, 16:{ *:[i32] })))  =>  (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 112519 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 112522 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 112524 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 112528 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 112532 */       GIR_RootConstrainSelectedInstOperands,
     /* 112533 */       // GIR_Coverage, 6175,
     /* 112533 */       GIR_EraseRootFromParent_Done,
     /* 112534 */     // Label 1777: @112534
     /* 112534 */     GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(112666), // Rule ID 6975 //
     /* 112539 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112543 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112547 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 112551 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 112554 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 112559 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 112563 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112568 */       // MIs[1] Operand 3
     /* 112568 */       GIM_CheckLiteralInt, /*MI*/1, /*Op*/3, GIMT_Encode8(16),
     /* 112579 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 112581 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vd, (intrinsic_wo_chain:{ *:[v4i16] } 682:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] }))  =>  (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
     /* 112581 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 112584 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 112588 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112593 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 112596 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 112598 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 112601 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 112605 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112610 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 112612 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112615 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 112619 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112624 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 112627 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 112631 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112634 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112639 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112644 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112649 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
     /* 112652 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112654 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112657 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 112661 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 112664 */       GIR_RootConstrainSelectedInstOperands,
     /* 112665 */       // GIR_Coverage, 6975,
     /* 112665 */       GIR_EraseRootFromParent_Done,
     /* 112666 */     // Label 1778: @112666
     /* 112666 */     GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(112708), // Rule ID 6425 //
     /* 112671 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 112678 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 112685 */       // (concat_vectors:{ *:[v8i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (INSvi64lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] })
     /* 112685 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 112688 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112690 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 112695 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 112698 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 112703 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 112706 */       GIR_RootConstrainSelectedInstOperands,
     /* 112707 */       // GIR_Coverage, 6425,
     /* 112707 */       GIR_EraseRootFromParent_Done,
     /* 112708 */     // Label 1779: @112708
     /* 112708 */     GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(112750), // Rule ID 6429 //
     /* 112713 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 112720 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 112727 */       // (concat_vectors:{ *:[v8f16] } (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn), (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rm))  =>  (INSvi64lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] })
     /* 112727 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 112730 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112732 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 112737 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 112740 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 112745 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 112748 */       GIR_RootConstrainSelectedInstOperands,
     /* 112749 */       // GIR_Coverage, 6429,
     /* 112749 */       GIR_EraseRootFromParent_Done,
     /* 112750 */     // Label 1780: @112750
     /* 112750 */     GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(112866), // Rule ID 2614 //
     /* 112755 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 112758 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112762 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112766 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 112770 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 112773 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 112778 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 112782 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112787 */       // MIs[1] imm
     /* 112787 */       GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 112790 */       GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 112795 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 112797 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 682:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (RSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 112797 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 112800 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 112804 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112809 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 112811 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112814 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 112818 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112823 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 112826 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112830 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112833 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112838 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112843 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112848 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i16_shift),
     /* 112851 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112853 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112856 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 112860 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // imm
     /* 112864 */       GIR_RootConstrainSelectedInstOperands,
     /* 112865 */       // GIR_Coverage, 2614,
     /* 112865 */       GIR_EraseRootFromParent_Done,
     /* 112866 */     // Label 1781: @112866
     /* 112866 */     GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(112986), // Rule ID 6945 //
     /* 112871 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 112874 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112878 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112882 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 112886 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112890 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 112894 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 112898 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 112902 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112907 */       // MIs[2] imm
     /* 112907 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 112910 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 112915 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 112917 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 112917 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 112920 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 112924 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112929 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 112931 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 112934 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 112938 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 112943 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 112946 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 112950 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 112953 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112958 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 112963 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112968 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
     /* 112971 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 112973 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 112976 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 112980 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 112984 */       GIR_RootConstrainSelectedInstOperands,
     /* 112985 */       // GIR_Coverage, 6945,
     /* 112985 */       GIR_EraseRootFromParent_Done,
     /* 112986 */     // Label 1782: @112986
     /* 112986 */     GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(113103), // Rule ID 6981 //
     /* 112991 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 112995 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 112999 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 113003 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113007 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113011 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 113015 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113019 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113024 */       // MIs[2] imm
     /* 113024 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113027 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113032 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113034 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113034 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113037 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113041 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113046 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113048 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113051 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113055 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113060 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113063 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113067 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113070 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113075 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113080 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113085 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i16_shift),
     /* 113088 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113090 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113093 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113097 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113101 */       GIR_RootConstrainSelectedInstOperands,
     /* 113102 */       // GIR_Coverage, 6981,
     /* 113102 */       GIR_EraseRootFromParent_Done,
     /* 113103 */     // Label 1783: @113103
     /* 113103 */     GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(113223), // Rule ID 6948 //
     /* 113108 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113111 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113115 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113119 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 113123 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113127 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113131 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 113135 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113139 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113144 */       // MIs[2] imm
     /* 113144 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113147 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113152 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113154 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_s:{ *:[v4i16] } (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113154 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113157 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113161 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113166 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113168 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113171 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113175 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113180 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113183 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113187 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113190 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113195 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113200 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113205 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv8i16_shift),
     /* 113208 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113210 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113213 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113217 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113221 */       GIR_RootConstrainSelectedInstOperands,
     /* 113222 */       // GIR_Coverage, 6948,
     /* 113222 */       GIR_EraseRootFromParent_Done,
     /* 113223 */     // Label 1784: @113223
     /* 113223 */     GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(113343), // Rule ID 6954 //
     /* 113228 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113231 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113235 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113239 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 113243 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113247 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113251 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 113255 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113259 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113264 */       // MIs[2] imm
     /* 113264 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113267 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113272 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113274 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_s:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113274 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113277 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113281 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113286 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113288 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113291 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113295 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113300 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113303 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113307 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113310 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113315 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113320 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113325 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv8i16_shift),
     /* 113328 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113330 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113333 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113337 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113341 */       GIR_RootConstrainSelectedInstOperands,
     /* 113342 */       // GIR_Coverage, 6954,
     /* 113342 */       GIR_EraseRootFromParent_Done,
     /* 113343 */     // Label 1785: @113343
     /* 113343 */     GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(113463), // Rule ID 6951 //
     /* 113348 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113351 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113355 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113359 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 113363 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113367 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113371 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 113375 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113379 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113384 */       // MIs[2] imm
     /* 113384 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113387 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113392 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113394 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_u:{ *:[v4i16] } (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SQRSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113394 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113397 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113401 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113406 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113408 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113411 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113415 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113420 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113423 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113427 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113430 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113435 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113440 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113445 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv8i16_shift),
     /* 113448 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113450 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113453 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113457 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113461 */       GIR_RootConstrainSelectedInstOperands,
     /* 113462 */       // GIR_Coverage, 6951,
     /* 113462 */       GIR_EraseRootFromParent_Done,
     /* 113463 */     // Label 1786: @113463
     /* 113463 */     GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(113583), // Rule ID 6957 //
     /* 113468 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113471 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113475 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113479 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 113483 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113487 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113491 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 113495 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113499 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113504 */       // MIs[2] imm
     /* 113504 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113507 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113512 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113514 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_u:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (SQSHRUNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113514 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113517 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113521 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113526 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113528 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113531 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113535 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113540 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113543 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113547 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113550 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113555 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113560 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113565 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv8i16_shift),
     /* 113568 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113570 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113573 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113577 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113581 */       GIR_RootConstrainSelectedInstOperands,
     /* 113582 */       // GIR_Coverage, 6957,
     /* 113582 */       GIR_EraseRootFromParent_Done,
     /* 113583 */     // Label 1787: @113583
     /* 113583 */     GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(113703), // Rule ID 6960 //
     /* 113588 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113591 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113595 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113599 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 113603 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113607 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113611 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 113615 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113619 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113624 */       // MIs[2] imm
     /* 113624 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113627 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113632 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113634 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncusat_u:{ *:[v4i16] } (AArch64urshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (UQRSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113634 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113637 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113641 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113646 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113648 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113651 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113655 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113660 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113663 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113667 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113670 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113675 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113680 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113685 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv8i16_shift),
     /* 113688 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113690 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113693 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113697 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113701 */       GIR_RootConstrainSelectedInstOperands,
     /* 113702 */       // GIR_Coverage, 6960,
     /* 113702 */       GIR_EraseRootFromParent_Done,
     /* 113703 */     // Label 1788: @113703
     /* 113703 */     GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(113823), // Rule ID 6963 //
     /* 113708 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113711 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113715 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113719 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 113723 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113727 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 113731 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 113735 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 113739 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113744 */       // MIs[2] imm
     /* 113744 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 113747 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 113752 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 113754 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncusat_u:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)))  =>  (UQSHRNv8i16_shift:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 113754 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113757 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113761 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113766 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113768 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113771 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113775 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113780 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113783 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113787 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113790 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113795 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113800 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113805 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv8i16_shift),
     /* 113808 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113810 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113813 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 113817 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 113821 */       GIR_RootConstrainSelectedInstOperands,
     /* 113822 */       // GIR_Coverage, 6963,
     /* 113822 */       GIR_EraseRootFromParent_Done,
     /* 113823 */     // Label 1789: @113823
     /* 113823 */     GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(113940), // Rule ID 2530 //
     /* 113828 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113831 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113835 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113839 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 113843 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 113846 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 113851 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 113855 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 113859 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113864 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113869 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 113871 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 593:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (ADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 113871 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113874 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113878 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113883 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 113885 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 113888 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 113892 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 113897 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 113900 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 113904 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 113907 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113912 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113917 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113922 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v8i16),
     /* 113925 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 113927 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 113930 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 113934 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 113938 */       GIR_RootConstrainSelectedInstOperands,
     /* 113939 */       // GIR_Coverage, 2530,
     /* 113939 */       GIR_EraseRootFromParent_Done,
     /* 113940 */     // Label 1790: @113940
     /* 113940 */     GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(114057), // Rule ID 5945 //
     /* 113945 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 113948 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 113952 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 113956 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 113960 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 113963 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 113968 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 113972 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 113976 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113981 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 113986 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 113988 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 739:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (SUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 113988 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 113991 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 113995 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114000 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114002 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114005 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114009 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114014 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114017 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114021 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114024 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114029 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114034 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114039 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v8i16),
     /* 114042 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114044 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114047 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 114051 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 114055 */       GIR_RootConstrainSelectedInstOperands,
     /* 114056 */       // GIR_Coverage, 5945,
     /* 114056 */       GIR_EraseRootFromParent_Done,
     /* 114057 */     // Label 1791: @114057
     /* 114057 */     GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(114174), // Rule ID 5948 //
     /* 114062 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114065 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114069 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114073 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 114077 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 114080 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 114085 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 114089 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 114093 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114098 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114103 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114105 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 681:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (RADDHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 114105 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114108 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114112 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114117 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114119 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114122 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114126 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114131 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114134 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114138 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114141 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114146 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114151 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114156 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v8i16),
     /* 114159 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114161 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114164 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 114168 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 114172 */       GIR_RootConstrainSelectedInstOperands,
     /* 114173 */       // GIR_Coverage, 5948,
     /* 114173 */       GIR_EraseRootFromParent_Done,
     /* 114174 */     // Label 1792: @114174
     /* 114174 */     GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(114291), // Rule ID 5951 //
     /* 114179 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114182 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114186 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114190 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 114194 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 114197 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 114202 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 114206 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 114210 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114215 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114220 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114222 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 683:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))  =>  (RSUBHNv4i32_v8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 114222 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114225 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114229 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114234 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114236 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114239 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114243 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114248 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114251 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114255 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114258 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114263 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114268 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114273 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v8i16),
     /* 114276 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114278 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114281 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 114285 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 114289 */       GIR_RootConstrainSelectedInstOperands,
     /* 114290 */       // GIR_Coverage, 5951,
     /* 114290 */       GIR_EraseRootFromParent_Done,
     /* 114291 */     // Label 1793: @114291
     /* 114291 */     GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(114392), // Rule ID 4979 //
     /* 114296 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114300 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114304 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 114308 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 114311 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
     /* 114316 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 114320 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114325 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114327 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (intrinsic_wo_chain:{ *:[v4i16] } 789:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn))  =>  (FCVTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
     /* 114327 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114330 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114334 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114339 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114341 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114344 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114348 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114353 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114356 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114360 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114363 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114368 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114373 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114378 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 114381 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114383 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114386 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 114390 */       GIR_RootConstrainSelectedInstOperands,
     /* 114391 */       // GIR_Coverage, 4979,
     /* 114391 */       GIR_EraseRootFromParent_Done,
     /* 114392 */     // Label 1794: @114392
     /* 114392 */     GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(114448), // Rule ID 6100 //
     /* 114397 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 114401 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 114405 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114409 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114414 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 114418 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 114422 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114426 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114431 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 114433 */       // (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm))  =>  (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 114433 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 114436 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 114438 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 114442 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 114446 */       GIR_RootConstrainSelectedInstOperands,
     /* 114447 */       // GIR_Coverage, 6100,
     /* 114447 */       GIR_EraseRootFromParent_Done,
     /* 114448 */     // Label 1795: @114448
     /* 114448 */     GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(114514), // Rule ID 6423 //
     /* 114453 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114457 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114461 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 114467 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 114469 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114471 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4i16] }:$Rn), dsub:{ *:[i32] })
     /* 114471 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 114474 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 114478 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114483 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 114487 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 114489 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 114492 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114494 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 114497 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114500 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 114503 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114508 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114513 */       // GIR_Coverage, 6423,
     /* 114513 */       GIR_EraseRootFromParent_Done,
     /* 114514 */     // Label 1796: @114514
     /* 114514 */     GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(114580), // Rule ID 6427 //
     /* 114519 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114523 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114527 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 114533 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 114535 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114537 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v4f16] }:$Rn), dsub:{ *:[i32] })
     /* 114537 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 114540 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 114544 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114549 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 114553 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 114555 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 114558 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114560 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 114563 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114566 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 114569 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114574 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114579 */       // GIR_Coverage, 6427,
     /* 114579 */       GIR_EraseRootFromParent_Done,
     /* 114580 */     // Label 1797: @114580
     /* 114580 */     GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(114673), // Rule ID 4987 //
     /* 114585 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114589 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114593 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
     /* 114597 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114601 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114606 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114608 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn))  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rn)
     /* 114608 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114611 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114615 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114620 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114622 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114625 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114629 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114634 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114637 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114641 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114644 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114649 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114654 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114659 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 114662 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114664 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114667 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 114671 */       GIR_RootConstrainSelectedInstOperands,
     /* 114672 */       // GIR_Coverage, 4987,
     /* 114672 */       GIR_EraseRootFromParent_Done,
     /* 114673 */     // Label 1798: @114673
     /* 114673 */     GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(114769), // Rule ID 5031 //
     /* 114678 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114681 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114685 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114689 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 114693 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114697 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114702 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114704 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn))  =>  (XTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
     /* 114704 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114707 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114711 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114716 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114718 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114721 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114725 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114730 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114733 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114737 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114740 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114745 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114750 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114755 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i16),
     /* 114758 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114760 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114763 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 114767 */       GIR_RootConstrainSelectedInstOperands,
     /* 114768 */       // GIR_Coverage, 5031,
     /* 114768 */       GIR_EraseRootFromParent_Done,
     /* 114769 */     // Label 1799: @114769
     /* 114769 */     GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(114865), // Rule ID 2523 //
     /* 114774 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114777 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114781 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114785 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 114789 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114793 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114798 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114800 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_s:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn))  =>  (SQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
     /* 114800 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114803 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114807 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114812 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114814 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114817 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114821 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114826 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114829 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114833 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114836 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114841 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114846 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114851 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv8i16),
     /* 114854 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114856 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114859 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 114863 */       GIR_RootConstrainSelectedInstOperands,
     /* 114864 */       // GIR_Coverage, 2523,
     /* 114864 */       GIR_EraseRootFromParent_Done,
     /* 114865 */     // Label 1800: @114865
     /* 114865 */     GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(114961), // Rule ID 5025 //
     /* 114870 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114873 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114877 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114881 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 114885 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114889 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114894 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114896 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncssat_u:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn))  =>  (SQXTUNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
     /* 114896 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114899 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114903 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114908 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 114910 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 114913 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 114917 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 114922 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 114925 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 114929 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 114932 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114937 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114942 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114947 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv8i16),
     /* 114950 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 114952 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 114955 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 114959 */       GIR_RootConstrainSelectedInstOperands,
     /* 114960 */       // GIR_Coverage, 5025,
     /* 114960 */       GIR_EraseRootFromParent_Done,
     /* 114961 */     // Label 1801: @114961
     /* 114961 */     GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(115057), // Rule ID 5028 //
     /* 114966 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 114969 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 114973 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 114977 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 114981 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 114985 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 114990 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 114992 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, (truncusat_u:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn))  =>  (UQXTNv8i16:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v4i32] }:$Rn)
     /* 114992 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 114995 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 114999 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115004 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 115006 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115009 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115013 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115018 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 115021 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115025 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115028 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115033 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115038 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115043 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv8i16),
     /* 115046 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115048 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115051 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 115055 */       GIR_RootConstrainSelectedInstOperands,
     /* 115056 */       // GIR_Coverage, 5028,
     /* 115056 */       GIR_EraseRootFromParent_Done,
     /* 115057 */     // Label 1802: @115057
     /* 115057 */     GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(115119), // Rule ID 6424 //
     /* 115062 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115066 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115070 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 115074 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 115076 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rn, (undef:{ *:[v4i16] }))  =>  (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] })
     /* 115076 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 115079 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115083 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115088 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 115090 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115093 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115095 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115098 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 115100 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 115103 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115108 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115113 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115118 */       // GIR_Coverage, 6424,
     /* 115118 */       GIR_EraseRootFromParent_Done,
     /* 115119 */     // Label 1803: @115119
     /* 115119 */     GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(115181), // Rule ID 6428 //
     /* 115124 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115128 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115132 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 115136 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 115138 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rn, (undef:{ *:[v4f16] }))  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] })
     /* 115138 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 115141 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115145 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115150 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 115152 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115155 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115157 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115160 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 115162 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 115165 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115170 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115175 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115180 */       // GIR_Coverage, 6428,
     /* 115180 */       GIR_EraseRootFromParent_Done,
     /* 115181 */     // Label 1804: @115181
     /* 115181 */     GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(115315), // Rule ID 6422 //
     /* 115186 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115190 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115194 */       // (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (INSvi64lane:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 115194 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 115197 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115201 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115206 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 115208 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 115211 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115215 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115220 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 115223 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 115227 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 115230 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115235 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115240 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115245 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 115248 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115252 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115257 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 115259 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115262 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115266 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115271 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 115274 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115278 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115281 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115286 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115291 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115296 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 115299 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115301 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115304 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 115307 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 115310 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 115313 */       GIR_RootConstrainSelectedInstOperands,
     /* 115314 */       // GIR_Coverage, 6422,
     /* 115314 */       GIR_EraseRootFromParent_Done,
     /* 115315 */     // Label 1805: @115315
     /* 115315 */     GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(115449), // Rule ID 6426 //
     /* 115320 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115324 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115328 */       // (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn)  =>  (INSvi64lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 115328 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 115331 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115335 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115340 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 115342 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 115345 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115349 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115354 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 115357 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 115361 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 115364 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115369 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115374 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115379 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 115382 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 115386 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115391 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 115393 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115396 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 115400 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115405 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 115408 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115412 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115415 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115420 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115425 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115430 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 115433 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115435 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115438 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 115441 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 115444 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 115447 */       GIR_RootConstrainSelectedInstOperands,
     /* 115448 */       // GIR_Coverage, 6426,
     /* 115448 */       GIR_EraseRootFromParent_Done,
     /* 115449 */     // Label 1806: @115449
     /* 115449 */     GIM_Reject,
     /* 115450 */   // Label 1773: @115450
     /* 115450 */   GIM_Reject,
     /* 115451 */   // Label 1722: @115451
     /* 115451 */   GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(118359),
     /* 115456 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 115459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 115462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115466 */     GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(115595), // Rule ID 6018 //
     /* 115471 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115475 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115479 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 115483 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115487 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 115491 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 115495 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115499 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 115503 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 115507 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115511 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 115515 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115520 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 115524 */       GIM_CheckOpcodeIsEither, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 115530 */       GIM_CheckIsBuildVectorAllOnes, /*MI*/4,
     /* 115532 */       // MIs[2] Operand 2
     /* 115532 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 115543 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 115545 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 115545 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115548 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 115552 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115557 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 115560 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115564 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115567 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115572 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115577 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 115580 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115582 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115585 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 115589 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 115593 */       GIR_RootConstrainSelectedInstOperands,
     /* 115594 */       // GIR_Coverage, 6018,
     /* 115594 */       GIR_EraseRootFromParent_Done,
     /* 115595 */     // Label 1808: @115595
     /* 115595 */     GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(115717), // Rule ID 6014 //
     /* 115600 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115604 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115608 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 115612 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115616 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 115620 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 115624 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115628 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 115632 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 115636 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115640 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 115644 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115649 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115654 */       // MIs[2] Operand 2
     /* 115654 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 115665 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 115667 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (ADDHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 115667 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115670 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 115674 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115679 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 115682 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115686 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115689 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115694 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115699 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
     /* 115702 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115704 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115707 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 115711 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 115715 */       GIR_RootConstrainSelectedInstOperands,
     /* 115716 */       // GIR_Coverage, 6014,
     /* 115716 */       GIR_EraseRootFromParent_Done,
     /* 115717 */     // Label 1809: @115717
     /* 115717 */     GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(115839), // Rule ID 6016 //
     /* 115722 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115726 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115730 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 115734 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115738 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 115742 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 115746 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115750 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 115754 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 115758 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115762 */       GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 115766 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115771 */       GIM_CheckRegBankForClass, /*MI*/3, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115776 */       // MIs[2] Operand 2
     /* 115776 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 115787 */       GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 115789 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] })))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 115789 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 115792 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 115796 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 115801 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 115804 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 115808 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 115811 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115816 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115821 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 115824 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 115826 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 115829 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 115833 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/2, // Rm
     /* 115837 */       GIR_RootConstrainSelectedInstOperands,
     /* 115838 */       // GIR_Coverage, 6016,
     /* 115838 */       GIR_EraseRootFromParent_Done,
     /* 115839 */     // Label 1810: @115839
     /* 115839 */     GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(115941), // Rule ID 6174 //
     /* 115844 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 115848 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 115852 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115856 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 115860 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 115864 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115868 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115873 */       // MIs[2] Operand 2
     /* 115873 */       GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 115884 */       GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 115888 */       GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 115892 */       GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115896 */       GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 115900 */       GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_VLSHR),
     /* 115904 */       GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 115908 */       GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115913 */       // MIs[4] Operand 2
     /* 115913 */       GIM_CheckLiteralInt, /*MI*/4, /*Op*/2, GIMT_Encode8(8),
     /* 115924 */       GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 115926 */       // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })), (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vm, 8:{ *:[i32] })))  =>  (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 115926 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 115929 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 115931 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 115935 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Vm
     /* 115939 */       GIR_RootConstrainSelectedInstOperands,
     /* 115940 */       // GIR_Coverage, 6174,
     /* 115940 */       GIR_EraseRootFromParent_Done,
     /* 115941 */     // Label 1811: @115941
     /* 115941 */     GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(116073), // Rule ID 6974 //
     /* 115946 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 115950 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 115954 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 115958 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 115961 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 115966 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 115970 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 115975 */       // MIs[1] Operand 3
     /* 115975 */       GIM_CheckLiteralInt, /*MI*/1, /*Op*/3, GIMT_Encode8(8),
     /* 115986 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 115988 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Vd, (intrinsic_wo_chain:{ *:[v8i8] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] }))  =>  (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Vd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
     /* 115988 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 115991 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 115995 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116000 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 116003 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 116005 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116008 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116012 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116017 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116019 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116022 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116026 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116031 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116034 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vd
     /* 116038 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116041 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116046 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116051 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116056 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
     /* 116059 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116061 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116064 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
     /* 116068 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 116071 */       GIR_RootConstrainSelectedInstOperands,
     /* 116072 */       // GIR_Coverage, 6974,
     /* 116072 */       GIR_EraseRootFromParent_Done,
     /* 116073 */     // Label 1812: @116073
     /* 116073 */     GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(116115), // Rule ID 6433 //
     /* 116078 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 116085 */       GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 116092 */       // (concat_vectors:{ *:[v16i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (INSvi64lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, 0:{ *:[i64] }, V128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] })
     /* 116092 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 116095 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116097 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 116102 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 116105 */       GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 116110 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 116113 */       GIR_RootConstrainSelectedInstOperands,
     /* 116114 */       // GIR_Coverage, 6433,
     /* 116114 */       GIR_EraseRootFromParent_Done,
     /* 116115 */     // Label 1813: @116115
     /* 116115 */     GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(116231), // Rule ID 2612 //
     /* 116120 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116123 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116127 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116131 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 116135 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 116138 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 116143 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 116147 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116152 */       // MIs[1] imm
     /* 116152 */       GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 116155 */       GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116160 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 116162 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (RSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116162 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116165 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116169 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116174 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116176 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116179 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116183 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116188 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116191 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116195 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116198 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116203 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116208 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116213 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv16i8_shift),
     /* 116216 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116218 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116221 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 116225 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // imm
     /* 116229 */       GIR_RootConstrainSelectedInstOperands,
     /* 116230 */       // GIR_Coverage, 2612,
     /* 116230 */       GIR_EraseRootFromParent_Done,
     /* 116231 */     // Label 1814: @116231
     /* 116231 */     GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(116351), // Rule ID 6944 //
     /* 116236 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116239 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116243 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116247 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 116251 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116255 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116259 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 116263 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116267 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116272 */       // MIs[2] imm
     /* 116272 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116275 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116280 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116282 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116282 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116285 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116289 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116294 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116296 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116299 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116303 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116308 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116311 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116315 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116318 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116323 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116328 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116333 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
     /* 116336 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116338 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116341 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116345 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116349 */       GIR_RootConstrainSelectedInstOperands,
     /* 116350 */       // GIR_Coverage, 6944,
     /* 116350 */       GIR_EraseRootFromParent_Done,
     /* 116351 */     // Label 1815: @116351
     /* 116351 */     GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(116468), // Rule ID 6980 //
     /* 116356 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116360 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116364 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 116368 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116372 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116376 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 116380 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116384 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116389 */       // MIs[2] imm
     /* 116389 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116392 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116397 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116399 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116399 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116402 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116406 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116411 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116413 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116416 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116420 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116425 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116428 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116432 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116435 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116440 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116445 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116450 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv16i8_shift),
     /* 116453 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116455 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116458 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116462 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116466 */       GIR_RootConstrainSelectedInstOperands,
     /* 116467 */       // GIR_Coverage, 6980,
     /* 116467 */       GIR_EraseRootFromParent_Done,
     /* 116468 */     // Label 1816: @116468
     /* 116468 */     GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(116588), // Rule ID 6947 //
     /* 116473 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116476 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116480 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116484 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 116488 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116492 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116496 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 116500 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116504 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116509 */       // MIs[2] imm
     /* 116509 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116512 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116517 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116519 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_s:{ *:[v8i8] } (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116519 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116522 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116526 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116531 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116533 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116536 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116540 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116545 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116548 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116552 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116555 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116560 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116565 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116570 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv16i8_shift),
     /* 116573 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116575 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116578 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116582 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116586 */       GIR_RootConstrainSelectedInstOperands,
     /* 116587 */       // GIR_Coverage, 6947,
     /* 116587 */       GIR_EraseRootFromParent_Done,
     /* 116588 */     // Label 1817: @116588
     /* 116588 */     GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(116708), // Rule ID 6953 //
     /* 116593 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116596 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116600 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116604 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 116608 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116612 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116616 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 116620 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116624 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116629 */       // MIs[2] imm
     /* 116629 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116632 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116637 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116639 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_s:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116639 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116642 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116646 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116651 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116653 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116656 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116660 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116665 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116668 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116672 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116675 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116680 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116685 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116690 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv16i8_shift),
     /* 116693 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116695 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116698 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116702 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116706 */       GIR_RootConstrainSelectedInstOperands,
     /* 116707 */       // GIR_Coverage, 6953,
     /* 116707 */       GIR_EraseRootFromParent_Done,
     /* 116708 */     // Label 1818: @116708
     /* 116708 */     GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(116828), // Rule ID 6950 //
     /* 116713 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116716 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116720 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116724 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 116728 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116732 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116736 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 116740 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116744 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116749 */       // MIs[2] imm
     /* 116749 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116752 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116757 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116759 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_u:{ *:[v8i8] } (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SQRSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116759 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116762 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116766 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116771 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116773 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116776 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116780 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116785 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116788 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116792 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116795 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116800 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116805 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116810 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv16i8_shift),
     /* 116813 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116815 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116818 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116822 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116826 */       GIR_RootConstrainSelectedInstOperands,
     /* 116827 */       // GIR_Coverage, 6950,
     /* 116827 */       GIR_EraseRootFromParent_Done,
     /* 116828 */     // Label 1819: @116828
     /* 116828 */     GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(116948), // Rule ID 6956 //
     /* 116833 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116836 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116840 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116844 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 116848 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116852 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116856 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VASHR),
     /* 116860 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116864 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116869 */       // MIs[2] imm
     /* 116869 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116872 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116877 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116879 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_u:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (SQSHRUNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116879 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 116882 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 116886 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116891 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 116893 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 116896 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 116900 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 116905 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 116908 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 116912 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 116915 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116920 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116925 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116930 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv16i8_shift),
     /* 116933 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 116935 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 116938 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 116942 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 116946 */       GIR_RootConstrainSelectedInstOperands,
     /* 116947 */       // GIR_Coverage, 6956,
     /* 116947 */       GIR_EraseRootFromParent_Done,
     /* 116948 */     // Label 1820: @116948
     /* 116948 */     GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(117068), // Rule ID 6959 //
     /* 116953 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 116956 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 116960 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 116964 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 116968 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116972 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 116976 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 116980 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 116984 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 116989 */       // MIs[2] imm
     /* 116989 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 116992 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 116997 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 116999 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncusat_u:{ *:[v8i8] } (AArch64urshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (UQRSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 116999 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117002 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117006 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117011 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117013 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117016 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117020 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117025 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117028 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117032 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117035 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117040 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117045 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117050 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv16i8_shift),
     /* 117053 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117055 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117058 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 117062 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 117066 */       GIR_RootConstrainSelectedInstOperands,
     /* 117067 */       // GIR_Coverage, 6959,
     /* 117067 */       GIR_EraseRootFromParent_Done,
     /* 117068 */     // Label 1821: @117068
     /* 117068 */     GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(117188), // Rule ID 6962 //
     /* 117073 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117076 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117080 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117084 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 117088 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117092 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 117096 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_VLSHR),
     /* 117100 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117104 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117109 */       // MIs[2] imm
     /* 117109 */       GIM_CheckIsImm, /*MI*/2, /*Op*/2,
     /* 117112 */       GIM_CheckImmOperandPredicate, /*MI*/2, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 117117 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 117119 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncusat_u:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)))  =>  (UQSHRNv16i8_shift:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 117119 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117122 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117126 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117131 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117133 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117136 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117140 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117145 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117148 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117152 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117155 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117160 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117165 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117170 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv16i8_shift),
     /* 117173 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117175 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117178 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 117182 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // imm
     /* 117186 */       GIR_RootConstrainSelectedInstOperands,
     /* 117187 */       // GIR_Coverage, 6962,
     /* 117187 */       GIR_EraseRootFromParent_Done,
     /* 117188 */     // Label 1822: @117188
     /* 117188 */     GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(117305), // Rule ID 2529 //
     /* 117193 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117196 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117200 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117204 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 117208 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 117211 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 117216 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 117220 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 117224 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117229 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117234 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117236 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 593:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (ADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 117236 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117239 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117243 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117248 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117250 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117253 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117257 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117262 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117265 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117269 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117272 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117277 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117282 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117287 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v16i8),
     /* 117290 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117292 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117295 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 117299 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 117303 */       GIR_RootConstrainSelectedInstOperands,
     /* 117304 */       // GIR_Coverage, 2529,
     /* 117304 */       GIR_EraseRootFromParent_Done,
     /* 117305 */     // Label 1823: @117305
     /* 117305 */     GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(117422), // Rule ID 5944 //
     /* 117310 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117313 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117317 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117321 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 117325 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 117328 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 117333 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 117337 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 117341 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117346 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117351 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117353 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 739:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (SUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 117353 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117356 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117360 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117365 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117367 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117370 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117374 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117379 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117382 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117386 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117389 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117394 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117399 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117404 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v16i8),
     /* 117407 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117409 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117412 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 117416 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 117420 */       GIR_RootConstrainSelectedInstOperands,
     /* 117421 */       // GIR_Coverage, 5944,
     /* 117421 */       GIR_EraseRootFromParent_Done,
     /* 117422 */     // Label 1824: @117422
     /* 117422 */     GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(117539), // Rule ID 5947 //
     /* 117427 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117430 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117434 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117438 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 117442 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 117445 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 117450 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 117454 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 117458 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117463 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117468 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117470 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 681:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (RADDHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 117470 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117473 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117477 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117482 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117484 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117487 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117491 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117496 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117499 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117503 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117506 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117511 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117516 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117521 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v16i8),
     /* 117524 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117526 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117529 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 117533 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 117537 */       GIR_RootConstrainSelectedInstOperands,
     /* 117538 */       // GIR_Coverage, 5947,
     /* 117538 */       GIR_EraseRootFromParent_Done,
     /* 117539 */     // Label 1825: @117539
     /* 117539 */     GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(117656), // Rule ID 5950 //
     /* 117544 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117547 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117551 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117555 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 117559 */       GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 117562 */       GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 117567 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 117571 */       GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 117575 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117580 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117585 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117587 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (intrinsic_wo_chain:{ *:[v8i8] } 683:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))  =>  (RSUBHNv8i16_v16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 117587 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117590 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117594 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117599 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117601 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117604 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117608 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117613 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117616 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117620 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117623 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117628 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117633 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117638 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v16i8),
     /* 117641 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117643 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117646 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 117650 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 117654 */       GIR_RootConstrainSelectedInstOperands,
     /* 117655 */       // GIR_Coverage, 5950,
     /* 117655 */       GIR_EraseRootFromParent_Done,
     /* 117656 */     // Label 1826: @117656
     /* 117656 */     GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(117712), // Rule ID 6091 //
     /* 117661 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 117665 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 117669 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117673 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117678 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 117682 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 117686 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117690 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117695 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 117697 */       // (concat_vectors:{ *:[v16i8] } (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn), (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vm))  =>  (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 117697 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
     /* 117700 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 117702 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 117706 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
     /* 117710 */       GIR_RootConstrainSelectedInstOperands,
     /* 117711 */       // GIR_Coverage, 6091,
     /* 117711 */       GIR_EraseRootFromParent_Done,
     /* 117712 */     // Label 1827: @117712
     /* 117712 */     GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(117778), // Rule ID 6431 //
     /* 117717 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117721 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117725 */       GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 117731 */       GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 117733 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117735 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (FMOVDr:{ *:[i64] } V64:{ *:[v8i8] }:$Rn), dsub:{ *:[i32] })
     /* 117735 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 117738 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVDr),
     /* 117742 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117747 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 117751 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 117753 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 117756 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117758 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 117761 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117764 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 117767 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117772 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117777 */       // GIR_Coverage, 6431,
     /* 117777 */       GIR_EraseRootFromParent_Done,
     /* 117778 */     // Label 1828: @117778
     /* 117778 */     GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(117874), // Rule ID 5030 //
     /* 117783 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117786 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117790 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117794 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 117798 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117802 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117807 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117809 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn))  =>  (XTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
     /* 117809 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117812 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117816 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117821 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117823 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117826 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117830 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117835 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117838 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117842 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117845 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117850 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117855 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117860 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv16i8),
     /* 117863 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117865 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117868 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 117872 */       GIR_RootConstrainSelectedInstOperands,
     /* 117873 */       // GIR_Coverage, 5030,
     /* 117873 */       GIR_EraseRootFromParent_Done,
     /* 117874 */     // Label 1829: @117874
     /* 117874 */     GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(117970), // Rule ID 2522 //
     /* 117879 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117882 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117886 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117890 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_S),
     /* 117894 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117898 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117903 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 117905 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_s:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn))  =>  (SQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
     /* 117905 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 117908 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 117912 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117917 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 117919 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 117922 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 117926 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 117931 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 117934 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 117938 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 117941 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117946 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117951 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117956 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv16i8),
     /* 117959 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 117961 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 117964 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 117968 */       GIR_RootConstrainSelectedInstOperands,
     /* 117969 */       // GIR_Coverage, 2522,
     /* 117969 */       GIR_EraseRootFromParent_Done,
     /* 117970 */     // Label 1830: @117970
     /* 117970 */     GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(118066), // Rule ID 5024 //
     /* 117975 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 117978 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 117982 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 117986 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_SSAT_U),
     /* 117990 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 117994 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 117999 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118001 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncssat_u:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn))  =>  (SQXTUNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
     /* 118001 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 118004 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118008 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118013 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 118015 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 118018 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118022 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118027 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 118030 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 118034 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 118037 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118042 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118047 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118052 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv16i8),
     /* 118055 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118057 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118060 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 118064 */       GIR_RootConstrainSelectedInstOperands,
     /* 118065 */       // GIR_Coverage, 5024,
     /* 118065 */       GIR_EraseRootFromParent_Done,
     /* 118066 */     // Label 1831: @118066
     /* 118066 */     GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(118162), // Rule ID 5027 //
     /* 118071 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 118074 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118078 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 118082 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC_USAT_U),
     /* 118086 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 118090 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118095 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118097 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, (truncusat_u:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn))  =>  (UQXTNv16i8:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), V128:{ *:[v8i16] }:$Rn)
     /* 118097 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 118100 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118104 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118109 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 118111 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 118114 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118118 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118123 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 118126 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 118130 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 118133 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118138 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118143 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118148 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv16i8),
     /* 118151 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118153 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118156 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 118160 */       GIR_RootConstrainSelectedInstOperands,
     /* 118161 */       // GIR_Coverage, 5027,
     /* 118161 */       GIR_EraseRootFromParent_Done,
     /* 118162 */     // Label 1832: @118162
     /* 118162 */     GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(118224), // Rule ID 6432 //
     /* 118167 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118171 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 118175 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 118179 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118181 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rn, (undef:{ *:[v8i8] }))  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] })
     /* 118181 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 118184 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118188 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118193 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 118195 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118198 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118200 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118203 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 118205 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 118208 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118213 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118218 */       GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118223 */       // GIR_Coverage, 6432,
     /* 118223 */       GIR_EraseRootFromParent_Done,
     /* 118224 */     // Label 1833: @118224
     /* 118224 */     GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(118358), // Rule ID 6430 //
     /* 118229 */       GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118233 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118237 */       // (concat_vectors:{ *:[v16i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (INSvi64lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), 1:{ *:[i64] }, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 118237 */       GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 118240 */       GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118244 */       GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118249 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 118251 */       GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 118254 */       GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118258 */       GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118263 */       GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 118266 */       GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 118270 */       GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 118273 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118278 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118283 */       GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118288 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 118291 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 118295 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118300 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 118302 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 118305 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 118309 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118314 */       GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 118317 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 118321 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 118324 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118329 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 118334 */       GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 118339 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 118342 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118344 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118347 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 118350 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 118353 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 118356 */       GIR_RootConstrainSelectedInstOperands,
     /* 118357 */       // GIR_Coverage, 6430,
     /* 118357 */       GIR_EraseRootFromParent_Done,
     /* 118358 */     // Label 1834: @118358
     /* 118358 */     GIM_Reject,
     /* 118359 */   // Label 1807: @118359
     /* 118359 */   GIM_Reject,
     /* 118360 */   // Label 1723: @118360
     /* 118360 */   GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(118385), // Rule ID 9803 //
     /* 118365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118368 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /* 118371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 118374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 118378 */     // (concat_vectors:{ *:[nxv2i1] } nxv1i1:{ *:[nxv1i1] }:$p1, nxv1i1:{ *:[nxv1i1] }:$p2)  =>  (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv1i1] }:$p1, ?:{ *:[nxv1i1] }:$p2)
     /* 118378 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 118383 */     GIR_RootConstrainSelectedInstOperands,
     /* 118384 */     // GIR_Coverage, 9803,
     /* 118384 */     GIR_Done,
     /* 118385 */   // Label 1835: @118385
     /* 118385 */   GIM_Reject,
     /* 118386 */   // Label 1724: @118386
     /* 118386 */   GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(118411), // Rule ID 9804 //
     /* 118391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118394 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 118397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 118400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 118404 */     // (concat_vectors:{ *:[nxv4i1] } nxv2i1:{ *:[nxv2i1] }:$p1, nxv2i1:{ *:[nxv2i1] }:$p2)  =>  (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv2i1] }:$p1, ?:{ *:[nxv2i1] }:$p2)
     /* 118404 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 118409 */     GIR_RootConstrainSelectedInstOperands,
     /* 118410 */     // GIR_Coverage, 9804,
     /* 118410 */     GIR_Done,
     /* 118411 */   // Label 1836: @118411
     /* 118411 */   GIM_Reject,
     /* 118412 */   // Label 1725: @118412
     /* 118412 */   GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(118437), // Rule ID 9807 //
     /* 118417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118420 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 118423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 118426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118430 */     // (concat_vectors:{ *:[nxv4f16] } nxv2f16:{ *:[nxv2f16] }:$v1, nxv2f16:{ *:[nxv2f16] }:$v2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv2f16] }:$v1, ?:{ *:[nxv2f16] }:$v2)
     /* 118430 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 118435 */     GIR_RootConstrainSelectedInstOperands,
     /* 118436 */     // GIR_Coverage, 9807,
     /* 118436 */     GIR_Done,
     /* 118437 */   // Label 1837: @118437
     /* 118437 */   GIM_Reject,
     /* 118438 */   // Label 1726: @118438
     /* 118438 */   GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(118463), // Rule ID 9809 //
     /* 118443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118446 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 118449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 118452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118456 */     // (concat_vectors:{ *:[nxv4f32] } nxv2f32:{ *:[nxv2f32] }:$v1, nxv2f32:{ *:[nxv2f32] }:$v2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv2f32] }:$v1, ?:{ *:[nxv2f32] }:$v2)
     /* 118456 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 118461 */     GIR_RootConstrainSelectedInstOperands,
     /* 118462 */     // GIR_Coverage, 9809,
     /* 118462 */     GIR_Done,
     /* 118463 */   // Label 1838: @118463
     /* 118463 */   GIM_Reject,
     /* 118464 */   // Label 1727: @118464
     /* 118464 */   GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(118489), // Rule ID 9805 //
     /* 118469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118472 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 118475 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 118478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 118482 */     // (concat_vectors:{ *:[nxv8i1] } nxv4i1:{ *:[nxv4i1] }:$p1, nxv4i1:{ *:[nxv4i1] }:$p2)  =>  (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv4i1] }:$p1, ?:{ *:[nxv4i1] }:$p2)
     /* 118482 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 118487 */     GIR_RootConstrainSelectedInstOperands,
     /* 118488 */     // GIR_Coverage, 9805,
     /* 118488 */     GIR_Done,
     /* 118489 */   // Label 1839: @118489
     /* 118489 */   GIM_Reject,
     /* 118490 */   // Label 1728: @118490
     /* 118490 */   GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(118515), // Rule ID 9808 //
     /* 118495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118498 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 118501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 118504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 118508 */     // (concat_vectors:{ *:[nxv8f16] } nxv4f16:{ *:[nxv4f16] }:$v1, nxv4f16:{ *:[nxv4f16] }:$v2)  =>  (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv4f16] }:$v1, ?:{ *:[nxv4f16] }:$v2)
     /* 118508 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 118513 */     GIR_RootConstrainSelectedInstOperands,
     /* 118514 */     // GIR_Coverage, 9808,
     /* 118514 */     GIR_Done,
     /* 118515 */   // Label 1840: @118515
     /* 118515 */   GIM_Reject,
     /* 118516 */   // Label 1729: @118516
     /* 118516 */   GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(118541), // Rule ID 9806 //
     /* 118521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 118524 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 118527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 118530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 118534 */     // (concat_vectors:{ *:[nxv16i1] } nxv8i1:{ *:[nxv8i1] }:$p1, nxv8i1:{ *:[nxv8i1] }:$p2)  =>  (UZP1_PPP_B:{ *:[nxv16i1] } ?:{ *:[nxv8i1] }:$p1, ?:{ *:[nxv8i1] }:$p2)
     /* 118534 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
     /* 118539 */     GIR_RootConstrainSelectedInstOperands,
     /* 118540 */     // GIR_Coverage, 9806,
     /* 118540 */     GIR_Done,
     /* 118541 */   // Label 1841: @118541
     /* 118541 */   GIM_Reject,
     /* 118542 */   // Label 1730: @118542
     /* 118542 */   GIM_Reject,
     /* 118543 */ // Label 1718: @118543
     /* 118543 */ GIM_Reject,
     /* 118544 */ // Label 15: @118544
     /* 118544 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(24), /*)*//*default:*//*Label 1856*/ GIMT_Encode4(136476),
     /* 118555 */ /*GILLT_s32*//*Label 1842*/ GIMT_Encode4(118643),
     /* 118559 */ /*GILLT_s64*//*Label 1843*/ GIMT_Encode4(122631),
     /* 118563 */ /*GILLT_s128*//*Label 1844*/ GIMT_Encode4(128988),
     /* 118567 */ /*GILLT_v2s32*//*Label 1845*/ GIMT_Encode4(129634),
     /* 118571 */ /*GILLT_v2s64*//*Label 1846*/ GIMT_Encode4(130549),
     /* 118575 */ /*GILLT_v4s16*//*Label 1847*/ GIMT_Encode4(131318),
     /* 118579 */ /*GILLT_v4s32*//*Label 1848*/ GIMT_Encode4(132233),
     /* 118583 */ /*GILLT_v8s8*//*Label 1849*/ GIMT_Encode4(133078),
     /* 118587 */ /*GILLT_v8s16*//*Label 1850*/ GIMT_Encode4(133639),
     /* 118591 */ /*GILLT_v16s8*//*Label 1851*/ GIMT_Encode4(134484), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 118611 */ /*GILLT_nxv2s64*//*Label 1852*/ GIMT_Encode4(134936), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 118623 */ /*GILLT_nxv4s32*//*Label 1853*/ GIMT_Encode4(135385), GIMT_Encode4(0),
     /* 118631 */ /*GILLT_nxv8s16*//*Label 1854*/ GIMT_Encode4(135834), GIMT_Encode4(0),
     /* 118639 */ /*GILLT_nxv16s8*//*Label 1855*/ GIMT_Encode4(136283),
     /* 118643 */ // Label 1842: @118643
     /* 118643 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(122630),
     /* 118648 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 118651 */   GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(118725), // Rule ID 7718 //
     /* 118656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 118664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 118668 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 118671 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 118675 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 118682 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 118685 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 118689 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118691 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 118698 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>)  =>  (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 118698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 118701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 118703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 118708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 118713 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 118718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 118723 */     GIR_RootConstrainSelectedInstOperands,
     /* 118724 */     // GIR_Coverage, 7718,
     /* 118724 */     GIR_EraseRootFromParent_Done,
     /* 118725 */   // Label 1858: @118725
     /* 118725 */   GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(118799), // Rule ID 7719 //
     /* 118730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118734 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 118738 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 118742 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 118745 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 118749 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 118756 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 118759 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 118763 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118765 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 118772 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>)  =>  (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 118772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 118775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 118777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 118782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 118787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 118792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 118797 */     GIR_RootConstrainSelectedInstOperands,
     /* 118798 */     // GIR_Coverage, 7719,
     /* 118798 */     GIR_EraseRootFromParent_Done,
     /* 118799 */   // Label 1859: @118799
     /* 118799 */   GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(118898), // Rule ID 4574 //
     /* 118804 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 118812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 118816 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 118819 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 118826 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 118830 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118832 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 118839 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 118839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 118842 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 118846 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 118856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 118861 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 118866 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 118871 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 118873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 118876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118878 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 118881 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118884 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 118887 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118892 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 118897 */     // GIR_Coverage, 4574,
     /* 118897 */     GIR_EraseRootFromParent_Done,
     /* 118898 */   // Label 1860: @118898
     /* 118898 */   GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(118997), // Rule ID 4575 //
     /* 118903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 118911 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 118915 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 118918 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 118925 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 118929 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 118931 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 118938 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 118938 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 118941 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 118945 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 118950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 118955 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 118960 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 118965 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 118970 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 118972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 118975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 118977 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 118980 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 118983 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 118986 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 118991 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 118996 */     // GIR_Coverage, 4575,
     /* 118996 */     GIR_EraseRootFromParent_Done,
     /* 118997 */   // Label 1861: @118997
     /* 118997 */   GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(119096), // Rule ID 4578 //
     /* 119002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119014 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119017 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 119024 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119028 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119030 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 119037 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 119037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119040 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 119044 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 119059 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 119064 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119069 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119076 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119079 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119082 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 119085 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119090 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119095 */     // GIR_Coverage, 4578,
     /* 119095 */     GIR_EraseRootFromParent_Done,
     /* 119096 */   // Label 1862: @119096
     /* 119096 */   GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(119195), // Rule ID 4579 //
     /* 119101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119113 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119116 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 119123 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119127 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119129 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 119136 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 119136 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119139 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 119143 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119148 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119153 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 119158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 119163 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119168 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119175 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119178 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 119184 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119189 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119194 */     // GIR_Coverage, 4579,
     /* 119194 */     GIR_EraseRootFromParent_Done,
     /* 119195 */   // Label 1863: @119195
     /* 119195 */   GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(119264), // Rule ID 7720 //
     /* 119200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 119212 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 119215 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 119219 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 119226 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 119229 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119233 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119235 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 119242 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>)  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 119242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 119245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 119247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119257 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119262 */     GIR_RootConstrainSelectedInstOperands,
     /* 119263 */     // GIR_Coverage, 7720,
     /* 119263 */     GIR_EraseRootFromParent_Done,
     /* 119264 */   // Label 1864: @119264
     /* 119264 */   GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(119333), // Rule ID 7721 //
     /* 119269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 119281 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 119284 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 119288 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 119295 */     GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 119298 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119302 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119304 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 119311 */     // (bitconvert:{ *:[f32] } (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>)  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 119311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 119314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 119316 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119321 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119331 */     GIR_RootConstrainSelectedInstOperands,
     /* 119332 */     // GIR_Coverage, 7721,
     /* 119332 */     GIR_EraseRootFromParent_Done,
     /* 119333 */   // Label 1865: @119333
     /* 119333 */   GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(119427), // Rule ID 4572 //
     /* 119338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119350 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119353 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 119360 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119364 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119366 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 119373 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 119373 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 119376 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 119380 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119390 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119395 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119400 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119410 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119413 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 119416 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119421 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 119426 */     // GIR_Coverage, 4572,
     /* 119426 */     GIR_EraseRootFromParent_Done,
     /* 119427 */   // Label 1866: @119427
     /* 119427 */   GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(119521), // Rule ID 4573 //
     /* 119432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119444 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119447 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 119454 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119458 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119460 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 119467 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 119467 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 119470 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 119474 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119489 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119494 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119504 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119507 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 119510 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119515 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 119520 */     // GIR_Coverage, 4573,
     /* 119520 */     GIR_EraseRootFromParent_Done,
     /* 119521 */   // Label 1867: @119521
     /* 119521 */   GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(119615), // Rule ID 4576 //
     /* 119526 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119534 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119538 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119541 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 119548 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119554 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 119561 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 119561 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119564 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 119568 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119583 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119588 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119595 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119598 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119601 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 119604 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119609 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119614 */     // GIR_Coverage, 4576,
     /* 119614 */     GIR_EraseRootFromParent_Done,
     /* 119615 */   // Label 1868: @119615
     /* 119615 */   GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(119709), // Rule ID 4577 //
     /* 119620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 119632 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 119635 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 119642 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 119646 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119648 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 119655 */     // (bitconvert:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f32] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 119655 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 119658 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 119662 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 119667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 119672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 119677 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 119682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 119684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 119687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119689 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 119692 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 119695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 119698 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119703 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119708 */     // GIR_Coverage, 4577,
     /* 119708 */     GIR_EraseRootFromParent_Done,
     /* 119709 */   // Label 1869: @119709
     /* 119709 */   GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(119762), // Rule ID 6392 //
     /* 119714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 119718 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119722 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 119726 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 119730 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 119734 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 119738 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119740 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v16i8:{ *:[v16i8] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v16i8] }:$src, bsub:{ *:[i32] })
     /* 119740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 119743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119745 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
     /* 119751 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 119756 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119761 */     // GIR_Coverage, 6392,
     /* 119761 */     GIR_EraseRootFromParent_Done,
     /* 119762 */   // Label 1870: @119762
     /* 119762 */   GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(119815), // Rule ID 6393 //
     /* 119767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119771 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119775 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 119779 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 119783 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 119787 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 119791 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119793 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v8i16:{ *:[v8i16] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v8i16] }:$src, hsub:{ *:[i32] })
     /* 119793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 119796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119798 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // src
     /* 119804 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119809 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119814 */     // GIR_Coverage, 6393,
     /* 119814 */     GIR_EraseRootFromParent_Done,
     /* 119815 */   // Label 1871: @119815
     /* 119815 */   GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(119868), // Rule ID 6394 //
     /* 119820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 119832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 119836 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 119840 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 119844 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119846 */     // (bitconvert:{ *:[f32] } (vector_extract:{ *:[i32] } v4i32:{ *:[v4i32] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4i32] }:$src, ssub:{ *:[i32] })
     /* 119846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 119849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 119851 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // src
     /* 119857 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119862 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 119867 */     // GIR_Coverage, 6394,
     /* 119867 */     GIR_EraseRootFromParent_Done,
     /* 119868 */   // Label 1872: @119868
     /* 119868 */   GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(119918), // Rule ID 5340 //
     /* 119873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 119876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 119888 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 119891 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 119896 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 119900 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 119905 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119907 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTASSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 119907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 119910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119912 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 119916 */     GIR_RootConstrainSelectedInstOperands,
     /* 119917 */     // GIR_Coverage, 5340,
     /* 119917 */     GIR_EraseRootFromParent_Done,
     /* 119918 */   // Label 1873: @119918
     /* 119918 */   GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(119968), // Rule ID 5341 //
     /* 119923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 119926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119930 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119934 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 119938 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 119941 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 119946 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 119950 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 119955 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 119957 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTASSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 119957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSHr),
     /* 119960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 119962 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 119966 */     GIR_RootConstrainSelectedInstOperands,
     /* 119967 */     // GIR_Coverage, 5341,
     /* 119967 */     GIR_EraseRootFromParent_Done,
     /* 119968 */   // Label 1874: @119968
     /* 119968 */   GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(120015), // Rule ID 5344 //
     /* 119973 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 119977 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 119981 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 119985 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 119988 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 119993 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 119997 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120002 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120004 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTASv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 120007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120009 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120013 */     GIR_RootConstrainSelectedInstOperands,
     /* 120014 */     // GIR_Coverage, 5344,
     /* 120014 */     GIR_EraseRootFromParent_Done,
     /* 120015 */   // Label 1875: @120015
     /* 120015 */   GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(120065), // Rule ID 5346 //
     /* 120020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120027 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120031 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120035 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120038 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 120043 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120047 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120052 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120054 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTAUSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSDr),
     /* 120057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120059 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120063 */     GIR_RootConstrainSelectedInstOperands,
     /* 120064 */     // GIR_Coverage, 5346,
     /* 120064 */     GIR_EraseRootFromParent_Done,
     /* 120065 */   // Label 1876: @120065
     /* 120065 */   GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(120115), // Rule ID 5347 //
     /* 120070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120085 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120088 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 120093 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120097 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120102 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120104 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTAUSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSHr),
     /* 120107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120113 */     GIR_RootConstrainSelectedInstOperands,
     /* 120114 */     // GIR_Coverage, 5347,
     /* 120114 */     GIR_EraseRootFromParent_Done,
     /* 120115 */   // Label 1877: @120115
     /* 120115 */   GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(120162), // Rule ID 5350 //
     /* 120120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120124 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120128 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120132 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120135 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 120140 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120144 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120149 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120151 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTAUv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i32),
     /* 120154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120160 */     GIR_RootConstrainSelectedInstOperands,
     /* 120161 */     // GIR_Coverage, 5350,
     /* 120161 */     GIR_EraseRootFromParent_Done,
     /* 120162 */   // Label 1878: @120162
     /* 120162 */   GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(120212), // Rule ID 5352 //
     /* 120167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120182 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120185 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 120190 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120194 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120199 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120201 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTMSSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSDr),
     /* 120204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120210 */     GIR_RootConstrainSelectedInstOperands,
     /* 120211 */     // GIR_Coverage, 5352,
     /* 120211 */     GIR_EraseRootFromParent_Done,
     /* 120212 */   // Label 1879: @120212
     /* 120212 */   GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(120262), // Rule ID 5353 //
     /* 120217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120232 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120235 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 120240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120244 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120249 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120251 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTMSSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSHr),
     /* 120254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120260 */     GIR_RootConstrainSelectedInstOperands,
     /* 120261 */     // GIR_Coverage, 5353,
     /* 120261 */     GIR_EraseRootFromParent_Done,
     /* 120262 */   // Label 1880: @120262
     /* 120262 */   GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(120309), // Rule ID 5356 //
     /* 120267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120271 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120275 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120279 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120282 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 120287 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120298 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTMSv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i32),
     /* 120301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120307 */     GIR_RootConstrainSelectedInstOperands,
     /* 120308 */     // GIR_Coverage, 5356,
     /* 120308 */     GIR_EraseRootFromParent_Done,
     /* 120309 */   // Label 1881: @120309
     /* 120309 */   GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(120359), // Rule ID 5358 //
     /* 120314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120329 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120332 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 120337 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120346 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120348 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTMUSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSDr),
     /* 120351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120357 */     GIR_RootConstrainSelectedInstOperands,
     /* 120358 */     // GIR_Coverage, 5358,
     /* 120358 */     GIR_EraseRootFromParent_Done,
     /* 120359 */   // Label 1882: @120359
     /* 120359 */   GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(120409), // Rule ID 5359 //
     /* 120364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120371 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120375 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120379 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120382 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 120387 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120391 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120396 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120398 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTMUSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSHr),
     /* 120401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120403 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120407 */     GIR_RootConstrainSelectedInstOperands,
     /* 120408 */     // GIR_Coverage, 5359,
     /* 120408 */     GIR_EraseRootFromParent_Done,
     /* 120409 */   // Label 1883: @120409
     /* 120409 */   GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(120456), // Rule ID 5362 //
     /* 120414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120426 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120429 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 120434 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120438 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120443 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120445 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTMUv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i32),
     /* 120448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120454 */     GIR_RootConstrainSelectedInstOperands,
     /* 120455 */     // GIR_Coverage, 5362,
     /* 120455 */     GIR_EraseRootFromParent_Done,
     /* 120456 */   // Label 1884: @120456
     /* 120456 */   GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(120506), // Rule ID 5364 //
     /* 120461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120468 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120472 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120476 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120479 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 120484 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120488 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120493 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120495 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTNSSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSSDr),
     /* 120498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120500 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120504 */     GIR_RootConstrainSelectedInstOperands,
     /* 120505 */     // GIR_Coverage, 5364,
     /* 120505 */     GIR_EraseRootFromParent_Done,
     /* 120506 */   // Label 1885: @120506
     /* 120506 */   GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(120556), // Rule ID 5365 //
     /* 120511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120518 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120522 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120526 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120529 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 120534 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120538 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120543 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120545 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTNSSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSSHr),
     /* 120548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120550 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120554 */     GIR_RootConstrainSelectedInstOperands,
     /* 120555 */     // GIR_Coverage, 5365,
     /* 120555 */     GIR_EraseRootFromParent_Done,
     /* 120556 */   // Label 1886: @120556
     /* 120556 */   GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(120603), // Rule ID 5368 //
     /* 120561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120565 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120569 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120573 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120576 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 120581 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120585 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120590 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120592 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTNSv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i32),
     /* 120595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120597 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120601 */     GIR_RootConstrainSelectedInstOperands,
     /* 120602 */     // GIR_Coverage, 5368,
     /* 120602 */     GIR_EraseRootFromParent_Done,
     /* 120603 */   // Label 1887: @120603
     /* 120603 */   GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(120653), // Rule ID 5370 //
     /* 120608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120615 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120619 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120623 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120626 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 120631 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120635 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120640 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120642 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTNUSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUSDr),
     /* 120645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120651 */     GIR_RootConstrainSelectedInstOperands,
     /* 120652 */     // GIR_Coverage, 5370,
     /* 120652 */     GIR_EraseRootFromParent_Done,
     /* 120653 */   // Label 1888: @120653
     /* 120653 */   GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(120703), // Rule ID 5371 //
     /* 120658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120673 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120676 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 120681 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120685 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120690 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120692 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTNUSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUSHr),
     /* 120695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120697 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120701 */     GIR_RootConstrainSelectedInstOperands,
     /* 120702 */     // GIR_Coverage, 5371,
     /* 120702 */     GIR_EraseRootFromParent_Done,
     /* 120703 */   // Label 1889: @120703
     /* 120703 */   GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(120750), // Rule ID 5374 //
     /* 120708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120712 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120716 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120720 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120723 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 120728 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120737 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120739 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTNUv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i32),
     /* 120742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120744 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120748 */     GIR_RootConstrainSelectedInstOperands,
     /* 120749 */     // GIR_Coverage, 5374,
     /* 120749 */     GIR_EraseRootFromParent_Done,
     /* 120750 */   // Label 1890: @120750
     /* 120750 */   GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(120800), // Rule ID 5376 //
     /* 120755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120762 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120766 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120770 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120773 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 120778 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120782 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120787 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120789 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTPSSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSDr),
     /* 120792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120798 */     GIR_RootConstrainSelectedInstOperands,
     /* 120799 */     // GIR_Coverage, 5376,
     /* 120799 */     GIR_EraseRootFromParent_Done,
     /* 120800 */   // Label 1891: @120800
     /* 120800 */   GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(120850), // Rule ID 5377 //
     /* 120805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120812 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120816 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120820 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120823 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 120828 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120832 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120837 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120839 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTPSSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSHr),
     /* 120842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120844 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120848 */     GIR_RootConstrainSelectedInstOperands,
     /* 120849 */     // GIR_Coverage, 5377,
     /* 120849 */     GIR_EraseRootFromParent_Done,
     /* 120850 */   // Label 1892: @120850
     /* 120850 */   GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(120897), // Rule ID 5380 //
     /* 120855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120859 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120863 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120867 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120870 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 120875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 120879 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120884 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120886 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTPSv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 120886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i32),
     /* 120889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120895 */     GIR_RootConstrainSelectedInstOperands,
     /* 120896 */     // GIR_Coverage, 5380,
     /* 120896 */     GIR_EraseRootFromParent_Done,
     /* 120897 */   // Label 1893: @120897
     /* 120897 */   GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(120947), // Rule ID 5382 //
     /* 120902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120917 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120920 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 120925 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 120929 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 120934 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120936 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTPUSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 120936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSDr),
     /* 120939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120945 */     GIR_RootConstrainSelectedInstOperands,
     /* 120946 */     // GIR_Coverage, 5382,
     /* 120946 */     GIR_EraseRootFromParent_Done,
     /* 120947 */   // Label 1894: @120947
     /* 120947 */   GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(120997), // Rule ID 5383 //
     /* 120952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 120955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 120959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 120963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 120967 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 120970 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 120975 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 120979 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 120984 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 120986 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTPUSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 120986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSHr),
     /* 120989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 120991 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 120995 */     GIR_RootConstrainSelectedInstOperands,
     /* 120996 */     // GIR_Coverage, 5383,
     /* 120996 */     GIR_EraseRootFromParent_Done,
     /* 120997 */   // Label 1895: @120997
     /* 120997 */   GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(121044), // Rule ID 5386 //
     /* 121002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121014 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121017 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 121022 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 121026 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121031 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121033 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTPUv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 121033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i32),
     /* 121036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121038 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121042 */     GIR_RootConstrainSelectedInstOperands,
     /* 121043 */     // GIR_Coverage, 5386,
     /* 121043 */     GIR_EraseRootFromParent_Done,
     /* 121044 */   // Label 1896: @121044
     /* 121044 */   GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(121089), // Rule ID 5424 //
     /* 121049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121064 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121067 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 121072 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 121076 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121078 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn))  =>  (FCVTZSSHr:{ *:[f32] } ?:{ *:[f16] }:$Rn)
     /* 121078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 121081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121083 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121087 */     GIR_RootConstrainSelectedInstOperands,
     /* 121088 */     // GIR_Coverage, 5424,
     /* 121088 */     GIR_EraseRootFromParent_Done,
     /* 121089 */   // Label 1897: @121089
     /* 121089 */   GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(121134), // Rule ID 5427 //
     /* 121094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121101 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121105 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121109 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121112 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 121117 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 121121 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121123 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn))  =>  (FCVTZSSDr:{ *:[f32] } ?:{ *:[f64] }:$Rn)
     /* 121123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 121126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121132 */     GIR_RootConstrainSelectedInstOperands,
     /* 121133 */     // GIR_Coverage, 5427,
     /* 121133 */     GIR_EraseRootFromParent_Done,
     /* 121134 */   // Label 1898: @121134
     /* 121134 */   GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(121176), // Rule ID 5428 //
     /* 121139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121151 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121154 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 121159 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 121163 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121165 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn))  =>  (FCVTZSv1i32:{ *:[f32] } ?:{ *:[f32] }:$Rn)
     /* 121165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 121168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121174 */     GIR_RootConstrainSelectedInstOperands,
     /* 121175 */     // GIR_Coverage, 5428,
     /* 121175 */     GIR_EraseRootFromParent_Done,
     /* 121176 */   // Label 1899: @121176
     /* 121176 */   GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(121221), // Rule ID 5448 //
     /* 121181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121188 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121192 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121196 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121199 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 121204 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 121208 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121210 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn))  =>  (FCVTZUSHr:{ *:[f32] } ?:{ *:[f16] }:$Rn)
     /* 121210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 121213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121219 */     GIR_RootConstrainSelectedInstOperands,
     /* 121220 */     // GIR_Coverage, 5448,
     /* 121220 */     GIR_EraseRootFromParent_Done,
     /* 121221 */   // Label 1900: @121221
     /* 121221 */   GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(121266), // Rule ID 5451 //
     /* 121226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121241 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121244 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 121249 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 121253 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121255 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn))  =>  (FCVTZUSDr:{ *:[f32] } ?:{ *:[f64] }:$Rn)
     /* 121255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 121258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121260 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121264 */     GIR_RootConstrainSelectedInstOperands,
     /* 121265 */     // GIR_Coverage, 5451,
     /* 121265 */     GIR_EraseRootFromParent_Done,
     /* 121266 */   // Label 1901: @121266
     /* 121266 */   GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(121308), // Rule ID 5452 //
     /* 121271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121275 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121279 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 121283 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 121286 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 121291 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 121295 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 121297 */     // (bitconvert:{ *:[f32] } (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn))  =>  (FCVTZUv1i32:{ *:[f32] } ?:{ *:[f32] }:$Rn)
     /* 121297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 121300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121302 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 121306 */     GIR_RootConstrainSelectedInstOperands,
     /* 121307 */     // GIR_Coverage, 5452,
     /* 121307 */     GIR_EraseRootFromParent_Done,
     /* 121308 */   // Label 1902: @121308
     /* 121308 */   GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(121357), // Rule ID 5541 //
     /* 121313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121328 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121332 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121336 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 121340 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121344 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121346 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTPSSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSDr),
     /* 121349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121355 */     GIR_RootConstrainSelectedInstOperands,
     /* 121356 */     // GIR_Coverage, 5541,
     /* 121356 */     GIR_EraseRootFromParent_Done,
     /* 121357 */   // Label 1903: @121357
     /* 121357 */   GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(121403), // Rule ID 5542 //
     /* 121362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121366 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121370 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121374 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121378 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121382 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 121386 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121390 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121392 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTPSv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i32),
     /* 121395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121401 */     GIR_RootConstrainSelectedInstOperands,
     /* 121402 */     // GIR_Coverage, 5542,
     /* 121402 */     GIR_EraseRootFromParent_Done,
     /* 121403 */   // Label 1904: @121403
     /* 121403 */   GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(121452), // Rule ID 5601 //
     /* 121408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121415 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121419 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121423 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121427 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121431 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 121435 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121439 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121441 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTMSSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSDr),
     /* 121444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121450 */     GIR_RootConstrainSelectedInstOperands,
     /* 121451 */     // GIR_Coverage, 5601,
     /* 121451 */     GIR_EraseRootFromParent_Done,
     /* 121452 */   // Label 1905: @121452
     /* 121452 */   GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(121498), // Rule ID 5602 //
     /* 121457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121461 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121465 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121469 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121473 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121477 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 121481 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121485 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121487 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTMSv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i32),
     /* 121490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121496 */     GIR_RootConstrainSelectedInstOperands,
     /* 121497 */     // GIR_Coverage, 5602,
     /* 121497 */     GIR_EraseRootFromParent_Done,
     /* 121498 */   // Label 1906: @121498
     /* 121498 */   GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(121547), // Rule ID 5721 //
     /* 121503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 121530 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121534 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121536 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTASSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 121539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121541 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121545 */     GIR_RootConstrainSelectedInstOperands,
     /* 121546 */     // GIR_Coverage, 5721,
     /* 121546 */     GIR_EraseRootFromParent_Done,
     /* 121547 */   // Label 1907: @121547
     /* 121547 */   GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(121593), // Rule ID 5722 //
     /* 121552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121564 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 121576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121580 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121582 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTASv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 121585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121591 */     GIR_RootConstrainSelectedInstOperands,
     /* 121592 */     // GIR_Coverage, 5722,
     /* 121592 */     GIR_EraseRootFromParent_Done,
     /* 121593 */   // Label 1908: @121593
     /* 121593 */   GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(121642), // Rule ID 5661 //
     /* 121598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121617 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121621 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 121625 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121629 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121631 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTZSSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 121634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121636 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121640 */     GIR_RootConstrainSelectedInstOperands,
     /* 121641 */     // GIR_Coverage, 5661,
     /* 121641 */     GIR_EraseRootFromParent_Done,
     /* 121642 */   // Label 1909: @121642
     /* 121642 */   GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(121688), // Rule ID 5662 //
     /* 121647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 121659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121663 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121667 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 121671 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121675 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121677 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTZSv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 121680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121682 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121686 */     GIR_RootConstrainSelectedInstOperands,
     /* 121687 */     // GIR_Coverage, 5662,
     /* 121687 */     GIR_EraseRootFromParent_Done,
     /* 121688 */   // Label 1910: @121688
     /* 121688 */   GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(121737), // Rule ID 5571 //
     /* 121693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121712 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121716 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 121720 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121724 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121726 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTPUSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSDr),
     /* 121729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121735 */     GIR_RootConstrainSelectedInstOperands,
     /* 121736 */     // GIR_Coverage, 5571,
     /* 121736 */     GIR_EraseRootFromParent_Done,
     /* 121737 */   // Label 1911: @121737
     /* 121737 */   GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(121783), // Rule ID 5572 //
     /* 121742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121746 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121750 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121754 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121758 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121762 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 121766 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121770 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121772 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTPUv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i32),
     /* 121775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121777 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121781 */     GIR_RootConstrainSelectedInstOperands,
     /* 121782 */     // GIR_Coverage, 5572,
     /* 121782 */     GIR_EraseRootFromParent_Done,
     /* 121783 */   // Label 1912: @121783
     /* 121783 */   GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(121832), // Rule ID 5631 //
     /* 121788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121807 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121811 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 121815 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121821 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTMUSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSDr),
     /* 121824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121830 */     GIR_RootConstrainSelectedInstOperands,
     /* 121831 */     // GIR_Coverage, 5631,
     /* 121831 */     GIR_EraseRootFromParent_Done,
     /* 121832 */   // Label 1913: @121832
     /* 121832 */   GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(121878), // Rule ID 5632 //
     /* 121837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121841 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121845 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121849 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121853 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121857 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 121861 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121865 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121867 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTMUv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i32),
     /* 121870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121876 */     GIR_RootConstrainSelectedInstOperands,
     /* 121877 */     // GIR_Coverage, 5632,
     /* 121877 */     GIR_EraseRootFromParent_Done,
     /* 121878 */   // Label 1914: @121878
     /* 121878 */   GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(121927), // Rule ID 5751 //
     /* 121883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121902 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121906 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 121910 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 121914 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121916 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTAUSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 121916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSDr),
     /* 121919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121921 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121925 */     GIR_RootConstrainSelectedInstOperands,
     /* 121926 */     // GIR_Coverage, 5751,
     /* 121926 */     GIR_EraseRootFromParent_Done,
     /* 121927 */   // Label 1915: @121927
     /* 121927 */   GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(121973), // Rule ID 5752 //
     /* 121932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121936 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121940 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121944 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 121948 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 121952 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 121956 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 121960 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 121962 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTAUv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 121962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i32),
     /* 121965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 121967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 121971 */     GIR_RootConstrainSelectedInstOperands,
     /* 121972 */     // GIR_Coverage, 5752,
     /* 121972 */     GIR_EraseRootFromParent_Done,
     /* 121973 */   // Label 1916: @121973
     /* 121973 */   GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(122022), // Rule ID 5691 //
     /* 121978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 121981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 121985 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 121989 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 121993 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 121997 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 122001 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 122005 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 122009 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 122011 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTZUSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 122011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 122014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122016 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 122020 */     GIR_RootConstrainSelectedInstOperands,
     /* 122021 */     // GIR_Coverage, 5691,
     /* 122021 */     GIR_EraseRootFromParent_Done,
     /* 122022 */   // Label 1917: @122022
     /* 122022 */   GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(122068), // Rule ID 5692 //
     /* 122027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 122039 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 122043 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 122047 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 122051 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 122055 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 122057 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTZUv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 122057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 122060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122062 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 122066 */     GIR_RootConstrainSelectedInstOperands,
     /* 122067 */     // GIR_Coverage, 5692,
     /* 122067 */     GIR_EraseRootFromParent_Done,
     /* 122068 */   // Label 1918: @122068
     /* 122068 */   GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(122110), // Rule ID 5389 //
     /* 122073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 122088 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 122092 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122097 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122099 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn))  =>  (FCVTZSSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 122099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 122102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122108 */     GIR_RootConstrainSelectedInstOperands,
     /* 122109 */     // GIR_Coverage, 5389,
     /* 122109 */     GIR_EraseRootFromParent_Done,
     /* 122110 */   // Label 1919: @122110
     /* 122110 */   GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(122152), // Rule ID 5391 //
     /* 122115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 122130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 122134 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 122139 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122141 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn))  =>  (FCVTZSSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 122141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 122144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122146 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122150 */     GIR_RootConstrainSelectedInstOperands,
     /* 122151 */     // GIR_Coverage, 5391,
     /* 122151 */     GIR_EraseRootFromParent_Done,
     /* 122152 */   // Label 1920: @122152
     /* 122152 */   GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(122191), // Rule ID 5397 //
     /* 122157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 122169 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 122173 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122178 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122180 */     // (bitconvert:{ *:[f32] } (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (FCVTZSv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 122180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 122183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122185 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122189 */     GIR_RootConstrainSelectedInstOperands,
     /* 122190 */     // GIR_Coverage, 5397,
     /* 122190 */     GIR_EraseRootFromParent_Done,
     /* 122191 */   // Label 1921: @122191
     /* 122191 */   GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(122233), // Rule ID 5401 //
     /* 122196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 122211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 122215 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122220 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122222 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn))  =>  (FCVTZUSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 122222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 122225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122227 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122231 */     GIR_RootConstrainSelectedInstOperands,
     /* 122232 */     // GIR_Coverage, 5401,
     /* 122232 */     GIR_EraseRootFromParent_Done,
     /* 122233 */   // Label 1922: @122233
     /* 122233 */   GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(122275), // Rule ID 5403 //
     /* 122238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122245 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122249 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 122253 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 122257 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 122262 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122264 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn))  =>  (FCVTZUSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 122264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 122267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122269 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122273 */     GIR_RootConstrainSelectedInstOperands,
     /* 122274 */     // GIR_Coverage, 5403,
     /* 122274 */     GIR_EraseRootFromParent_Done,
     /* 122275 */   // Label 1923: @122275
     /* 122275 */   GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(122314), // Rule ID 5409 //
     /* 122280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 122292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 122296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122301 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122303 */     // (bitconvert:{ *:[f32] } (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (FCVTZUv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 122303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 122306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122312 */     GIR_RootConstrainSelectedInstOperands,
     /* 122313 */     // GIR_Coverage, 5409,
     /* 122313 */     GIR_EraseRootFromParent_Done,
     /* 122314 */   // Label 1924: @122314
     /* 122314 */   GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(122368), // Rule ID 5809 //
     /* 122319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 122334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 122338 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122340 */     // (bitconvert:{ *:[f32] } (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZSSHr:{ *:[f32] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 122340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 122343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 122347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 122352 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122356 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 122358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 122361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122363 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 122366 */     GIR_RootConstrainSelectedInstOperands,
     /* 122367 */     // GIR_Coverage, 5809,
     /* 122367 */     GIR_EraseRootFromParent_Done,
     /* 122368 */   // Label 1925: @122368
     /* 122368 */   GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(122422), // Rule ID 5817 //
     /* 122373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 122388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 122392 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122394 */     // (bitconvert:{ *:[f32] } (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSSDr:{ *:[f32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 122394 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 122397 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 122401 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 122406 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122410 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 122412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 122415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122417 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 122420 */     GIR_RootConstrainSelectedInstOperands,
     /* 122421 */     // GIR_Coverage, 5817,
     /* 122421 */     GIR_EraseRootFromParent_Done,
     /* 122422 */   // Label 1926: @122422
     /* 122422 */   GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(122473), // Rule ID 5821 //
     /* 122427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122431 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122435 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 122439 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 122443 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122445 */     // (bitconvert:{ *:[f32] } (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSv1i32:{ *:[f32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 122445 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 122448 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 122452 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 122457 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122461 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 122463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 122466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122468 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 122471 */     GIR_RootConstrainSelectedInstOperands,
     /* 122472 */     // GIR_Coverage, 5821,
     /* 122472 */     GIR_EraseRootFromParent_Done,
     /* 122473 */   // Label 1927: @122473
     /* 122473 */   GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(122510), // Rule ID 5782 //
     /* 122478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 122493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 122497 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122499 */     // (bitconvert:{ *:[f32] } (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn))  =>  (FCVTASSHr:{ *:[f32] } f16:{ *:[f16] }:$Rn)
     /* 122499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSHr),
     /* 122502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122504 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122508 */     GIR_RootConstrainSelectedInstOperands,
     /* 122509 */     // GIR_Coverage, 5782,
     /* 122509 */     GIR_EraseRootFromParent_Done,
     /* 122510 */   // Label 1928: @122510
     /* 122510 */   GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(122547), // Rule ID 5790 //
     /* 122515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 122518 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122522 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122526 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 122530 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 122534 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122536 */     // (bitconvert:{ *:[f32] } (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASSDr:{ *:[f32] } f64:{ *:[f64] }:$Rn)
     /* 122536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 122539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122541 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122545 */     GIR_RootConstrainSelectedInstOperands,
     /* 122546 */     // GIR_Coverage, 5790,
     /* 122546 */     GIR_EraseRootFromParent_Done,
     /* 122547 */   // Label 1929: @122547
     /* 122547 */   GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(122581), // Rule ID 5794 //
     /* 122552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 122564 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 122568 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122570 */     // (bitconvert:{ *:[f32] } (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASv1i32:{ *:[f32] } f32:{ *:[f32] }:$Rn)
     /* 122570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 122573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 122575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 122579 */     GIR_RootConstrainSelectedInstOperands,
     /* 122580 */     // GIR_Coverage, 5794,
     /* 122580 */     GIR_EraseRootFromParent_Done,
     /* 122581 */   // Label 1930: @122581
     /* 122581 */   GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(122605), // Rule ID 7320 //
     /* 122586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122590 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122594 */     // (bitconvert:{ *:[f32] } GPR32:{ *:[i32] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Xn, FPR32:{ *:[i32] })
     /* 122594 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 122599 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122604 */     // GIR_Coverage, 7320,
     /* 122604 */     GIR_Done,
     /* 122605 */   // Label 1931: @122605
     /* 122605 */   GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(122629), // Rule ID 7321 //
     /* 122610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122614 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122618 */     // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$Xn, GPR32:{ *:[i32] })
     /* 122618 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 122623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 122628 */     // GIR_Coverage, 7321,
     /* 122628 */     GIR_Done,
     /* 122629 */   // Label 1932: @122629
     /* 122629 */   GIM_Reject,
     /* 122630 */ // Label 1857: @122630
     /* 122630 */ GIM_Reject,
     /* 122631 */ // Label 1843: @122631
     /* 122631 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(122708), // Rule ID 7722 //
     /* 122636 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 122639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122643 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122647 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 122651 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122654 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 122658 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 122665 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122668 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 122672 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122674 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 122681 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>)  =>  (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 122681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 122684 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 122696 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 122701 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 122706 */   GIR_RootConstrainSelectedInstOperands,
     /* 122707 */   // GIR_Coverage, 7722,
     /* 122707 */   GIR_EraseRootFromParent_Done,
     /* 122708 */ // Label 1933: @122708
     /* 122708 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(122785), // Rule ID 7723 //
     /* 122713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 122716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122720 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122724 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 122728 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 122731 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 122735 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 122742 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 122745 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 122749 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122751 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 122758 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>)  =>  (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 122758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 122761 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 122763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 122773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 122778 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 122783 */   GIR_RootConstrainSelectedInstOperands,
     /* 122784 */   // GIR_Coverage, 7723,
     /* 122784 */   GIR_EraseRootFromParent_Done,
     /* 122785 */ // Label 1934: @122785
     /* 122785 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(122887), // Rule ID 4582 //
     /* 122790 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 122793 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122797 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122801 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 122805 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 122808 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122815 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 122819 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122821 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 122828 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 122828 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 122831 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 122835 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 122840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122845 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 122850 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 122855 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 122860 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 122862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 122865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 122867 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 122870 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 122873 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 122876 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122881 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122886 */   // GIR_Coverage, 4582,
     /* 122886 */   GIR_EraseRootFromParent_Done,
     /* 122887 */ // Label 1935: @122887
     /* 122887 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(122989), // Rule ID 4583 //
     /* 122892 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 122895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122899 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 122903 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 122907 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 122910 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 122917 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 122921 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 122923 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 122930 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 122930 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 122933 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 122937 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 122942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 122947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 122952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 122957 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 122962 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 122964 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 122967 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 122969 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 122972 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 122975 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 122978 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 122983 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 122988 */   // GIR_Coverage, 4583,
     /* 122988 */   GIR_EraseRootFromParent_Done,
     /* 122989 */ // Label 1936: @122989
     /* 122989 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(123091), // Rule ID 4586 //
     /* 122994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 122997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123001 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123005 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123009 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123012 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123019 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123023 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123025 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 123032 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 123032 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 123035 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 123039 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123059 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123064 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123066 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123069 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123071 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123074 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123077 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 123080 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123085 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 123090 */   // GIR_Coverage, 4586,
     /* 123090 */   GIR_EraseRootFromParent_Done,
     /* 123091 */ // Label 1937: @123091
     /* 123091 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(123193), // Rule ID 4587 //
     /* 123096 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123103 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123107 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123111 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123114 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123121 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123125 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123127 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 123134 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 123134 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 123137 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 123141 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123151 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123156 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123161 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123166 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123168 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123171 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123173 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123176 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123179 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 123182 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123187 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 123192 */   // GIR_Coverage, 4587,
     /* 123192 */   GIR_EraseRootFromParent_Done,
     /* 123193 */ // Label 1938: @123193
     /* 123193 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(123295), // Rule ID 4590 //
     /* 123198 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123201 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123205 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123209 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123213 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123216 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 123223 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123227 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123229 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 123236 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 123236 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 123239 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 123243 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123258 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123263 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123268 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123273 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123278 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123281 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 123284 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123289 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 123294 */   // GIR_Coverage, 4590,
     /* 123294 */   GIR_EraseRootFromParent_Done,
     /* 123295 */ // Label 1939: @123295
     /* 123295 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(123397), // Rule ID 4591 //
     /* 123300 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123307 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123311 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123315 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123318 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 123325 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123329 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123331 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 123338 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 123338 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 123341 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 123345 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123355 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 123360 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 123365 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123370 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123377 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123380 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123383 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 123386 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123391 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 123396 */   // GIR_Coverage, 4591,
     /* 123396 */   GIR_EraseRootFromParent_Done,
     /* 123397 */ // Label 1940: @123397
     /* 123397 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(123469), // Rule ID 7724 //
     /* 123402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123409 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123413 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 123417 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 123420 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 123424 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 123431 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 123434 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123438 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123440 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 123447 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>)  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 123447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 123450 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123467 */   GIR_RootConstrainSelectedInstOperands,
     /* 123468 */   // GIR_Coverage, 7724,
     /* 123468 */   GIR_EraseRootFromParent_Done,
     /* 123469 */ // Label 1941: @123469
     /* 123469 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(123541), // Rule ID 7725 //
     /* 123474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123481 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123485 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 123489 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 123492 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 123496 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 123503 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 123506 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123510 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123512 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 123519 */   // (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>)  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 123519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 123522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 123524 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123534 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123539 */   GIR_RootConstrainSelectedInstOperands,
     /* 123540 */   // GIR_Coverage, 7725,
     /* 123540 */   GIR_EraseRootFromParent_Done,
     /* 123541 */ // Label 1942: @123541
     /* 123541 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(123638), // Rule ID 4580 //
     /* 123546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123553 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123557 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123561 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123564 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 123571 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123575 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123577 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 123584 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 123584 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123587 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 123591 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123606 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123611 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123616 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123618 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123621 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123624 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 123627 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123632 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 123637 */   // GIR_Coverage, 4580,
     /* 123637 */   GIR_EraseRootFromParent_Done,
     /* 123638 */ // Label 1943: @123638
     /* 123638 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(123735), // Rule ID 4581 //
     /* 123643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123650 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123654 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123658 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123661 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 123668 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123672 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123674 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 123681 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 123681 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 123684 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 123688 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123703 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123708 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123710 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123713 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123718 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 123724 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123729 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 123734 */   // GIR_Coverage, 4581,
     /* 123734 */   GIR_EraseRootFromParent_Done,
     /* 123735 */ // Label 1944: @123735
     /* 123735 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(123832), // Rule ID 4584 //
     /* 123740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123747 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123751 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123755 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123758 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123765 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123769 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123771 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 123778 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 123778 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 123781 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 123785 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123790 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123795 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123800 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123805 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123810 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123812 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123815 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123818 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 123821 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123826 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 123831 */   // GIR_Coverage, 4584,
     /* 123831 */   GIR_EraseRootFromParent_Done,
     /* 123832 */ // Label 1945: @123832
     /* 123832 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(123929), // Rule ID 4585 //
     /* 123837 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123844 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123848 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123852 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123855 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 123862 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123866 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123868 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 123875 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 123875 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 123878 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 123882 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123887 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123897 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123902 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 123904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 123907 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 123909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 123912 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 123915 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 123918 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123923 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 123928 */   // GIR_Coverage, 4585,
     /* 123928 */   GIR_EraseRootFromParent_Done,
     /* 123929 */ // Label 1946: @123929
     /* 123929 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(124026), // Rule ID 4588 //
     /* 123934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 123937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 123941 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 123945 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 123949 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 123952 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 123959 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 123963 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 123965 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 123972 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 123972 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 123975 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 123979 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 123984 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 123989 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 123994 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 123999 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124009 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124012 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 124015 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124020 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124025 */   // GIR_Coverage, 4588,
     /* 124025 */   GIR_EraseRootFromParent_Done,
     /* 124026 */ // Label 1947: @124026
     /* 124026 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(124123), // Rule ID 4589 //
     /* 124031 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124038 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124042 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 124046 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 124049 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 124056 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 124060 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124062 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 124069 */   // (bitconvert:{ *:[f64] } (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (SUBREG_TO_REG:{ *:[f64] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 124069 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 124072 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 124076 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 124081 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 124086 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 124091 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 124096 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 124098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 124101 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124103 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 124106 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 124109 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 124112 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124117 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124122 */   // GIR_Coverage, 4589,
     /* 124122 */   GIR_EraseRootFromParent_Done,
     /* 124123 */ // Label 1948: @124123
     /* 124123 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(124179), // Rule ID 6395 //
     /* 124128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124135 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124139 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 124143 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 124147 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124151 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 124155 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124157 */   // (bitconvert:{ *:[f64] } (vector_extract:{ *:[i64] } v2i64:{ *:[v2i64] }:$src, 0:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2i64] }:$src, dsub:{ *:[i32] })
     /* 124157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 124160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 124162 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src
     /* 124168 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124173 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 124178 */   // GIR_Coverage, 6395,
     /* 124178 */   GIR_EraseRootFromParent_Done,
     /* 124179 */ // Label 1949: @124179
     /* 124179 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(124232), // Rule ID 5342 //
     /* 124184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124194 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124198 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124202 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124205 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 124210 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124214 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124219 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124221 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTASDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 124221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 124224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124226 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124230 */   GIR_RootConstrainSelectedInstOperands,
     /* 124231 */   // GIR_Coverage, 5342,
     /* 124231 */   GIR_EraseRootFromParent_Done,
     /* 124232 */ // Label 1950: @124232
     /* 124232 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(124285), // Rule ID 5343 //
     /* 124237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124240 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124247 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124251 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124255 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124258 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 124263 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 124267 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 124272 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124274 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTASDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 124274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 124277 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124279 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124283 */   GIR_RootConstrainSelectedInstOperands,
     /* 124284 */   // GIR_Coverage, 5343,
     /* 124284 */   GIR_EraseRootFromParent_Done,
     /* 124285 */ // Label 1951: @124285
     /* 124285 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(124335), // Rule ID 5345 //
     /* 124290 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124293 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124297 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124301 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124305 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124308 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 124313 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124317 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124322 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124324 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTASv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 124324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 124327 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124329 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124333 */   GIR_RootConstrainSelectedInstOperands,
     /* 124334 */   // GIR_Coverage, 5345,
     /* 124334 */   GIR_EraseRootFromParent_Done,
     /* 124335 */ // Label 1952: @124335
     /* 124335 */ GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(124388), // Rule ID 5348 //
     /* 124340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124343 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124350 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124354 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124358 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124361 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 124366 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124370 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124375 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124377 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTAUDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 124377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDHr),
     /* 124380 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124382 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124386 */   GIR_RootConstrainSelectedInstOperands,
     /* 124387 */   // GIR_Coverage, 5348,
     /* 124387 */   GIR_EraseRootFromParent_Done,
     /* 124388 */ // Label 1953: @124388
     /* 124388 */ GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(124441), // Rule ID 5349 //
     /* 124393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124403 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124407 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124411 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124414 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 124419 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 124423 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 124428 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124430 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTAUDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 124430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDSr),
     /* 124433 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124435 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124439 */   GIR_RootConstrainSelectedInstOperands,
     /* 124440 */   // GIR_Coverage, 5349,
     /* 124440 */   GIR_EraseRootFromParent_Done,
     /* 124441 */ // Label 1954: @124441
     /* 124441 */ GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(124491), // Rule ID 5351 //
     /* 124446 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124449 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124453 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124457 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124461 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124464 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 124469 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124473 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124478 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124480 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTAUv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 124480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 124483 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124485 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124489 */   GIR_RootConstrainSelectedInstOperands,
     /* 124490 */   // GIR_Coverage, 5351,
     /* 124490 */   GIR_EraseRootFromParent_Done,
     /* 124491 */ // Label 1955: @124491
     /* 124491 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(124544), // Rule ID 5354 //
     /* 124496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124506 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124510 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124514 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124517 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 124522 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124526 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124531 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124533 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTMSDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 124533 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDHr),
     /* 124536 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124538 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124542 */   GIR_RootConstrainSelectedInstOperands,
     /* 124543 */   // GIR_Coverage, 5354,
     /* 124543 */   GIR_EraseRootFromParent_Done,
     /* 124544 */ // Label 1956: @124544
     /* 124544 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(124597), // Rule ID 5355 //
     /* 124549 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124552 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124559 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124563 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124567 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124570 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 124575 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 124579 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 124584 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124586 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTMSDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 124586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDSr),
     /* 124589 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124591 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124595 */   GIR_RootConstrainSelectedInstOperands,
     /* 124596 */   // GIR_Coverage, 5355,
     /* 124596 */   GIR_EraseRootFromParent_Done,
     /* 124597 */ // Label 1957: @124597
     /* 124597 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(124647), // Rule ID 5357 //
     /* 124602 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124609 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124613 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124617 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124620 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 124625 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124629 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124634 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124636 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTMSv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 124636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 124639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124641 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124645 */   GIR_RootConstrainSelectedInstOperands,
     /* 124646 */   // GIR_Coverage, 5357,
     /* 124646 */   GIR_EraseRootFromParent_Done,
     /* 124647 */ // Label 1958: @124647
     /* 124647 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(124700), // Rule ID 5360 //
     /* 124652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124662 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124666 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124670 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124673 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 124678 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124682 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124687 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124689 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTMUDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 124689 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDHr),
     /* 124692 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124694 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124698 */   GIR_RootConstrainSelectedInstOperands,
     /* 124699 */   // GIR_Coverage, 5360,
     /* 124699 */   GIR_EraseRootFromParent_Done,
     /* 124700 */ // Label 1959: @124700
     /* 124700 */ GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(124753), // Rule ID 5361 //
     /* 124705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124708 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124715 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124719 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124723 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124726 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 124731 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 124735 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 124740 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124742 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTMUDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 124742 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDSr),
     /* 124745 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124747 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124751 */   GIR_RootConstrainSelectedInstOperands,
     /* 124752 */   // GIR_Coverage, 5361,
     /* 124752 */   GIR_EraseRootFromParent_Done,
     /* 124753 */ // Label 1960: @124753
     /* 124753 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(124803), // Rule ID 5363 //
     /* 124758 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124765 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124769 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124773 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124776 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 124781 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124785 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124790 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124792 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTMUv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 124792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 124795 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124797 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124801 */   GIR_RootConstrainSelectedInstOperands,
     /* 124802 */   // GIR_Coverage, 5363,
     /* 124802 */   GIR_EraseRootFromParent_Done,
     /* 124803 */ // Label 1961: @124803
     /* 124803 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(124856), // Rule ID 5366 //
     /* 124808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124811 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124818 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124822 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124826 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124829 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 124834 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124838 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124843 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124845 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTNSDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 124845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSDHr),
     /* 124848 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124850 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124854 */   GIR_RootConstrainSelectedInstOperands,
     /* 124855 */   // GIR_Coverage, 5366,
     /* 124855 */   GIR_EraseRootFromParent_Done,
     /* 124856 */ // Label 1962: @124856
     /* 124856 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(124909), // Rule ID 5367 //
     /* 124861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124871 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124875 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124879 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124882 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 124887 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 124891 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 124896 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124898 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTNSDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 124898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSDSr),
     /* 124901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124903 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124907 */   GIR_RootConstrainSelectedInstOperands,
     /* 124908 */   // GIR_Coverage, 5367,
     /* 124908 */   GIR_EraseRootFromParent_Done,
     /* 124909 */ // Label 1963: @124909
     /* 124909 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(124959), // Rule ID 5369 //
     /* 124914 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124917 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124921 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124925 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124929 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124932 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 124937 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 124941 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124946 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 124948 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTNSv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 124948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i64),
     /* 124951 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 124953 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 124957 */   GIR_RootConstrainSelectedInstOperands,
     /* 124958 */   // GIR_Coverage, 5369,
     /* 124958 */   GIR_EraseRootFromParent_Done,
     /* 124959 */ // Label 1964: @124959
     /* 124959 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(125012), // Rule ID 5372 //
     /* 124964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 124967 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 124970 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 124974 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 124978 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 124982 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 124985 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 124990 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 124994 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 124999 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125001 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTNUDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 125001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUDHr),
     /* 125004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125006 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125010 */   GIR_RootConstrainSelectedInstOperands,
     /* 125011 */   // GIR_Coverage, 5372,
     /* 125011 */   GIR_EraseRootFromParent_Done,
     /* 125012 */ // Label 1965: @125012
     /* 125012 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(125065), // Rule ID 5373 //
     /* 125017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125027 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125031 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125035 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125038 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 125043 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 125047 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 125052 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125054 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTNUDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 125054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUDSr),
     /* 125057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125059 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125063 */   GIR_RootConstrainSelectedInstOperands,
     /* 125064 */   // GIR_Coverage, 5373,
     /* 125064 */   GIR_EraseRootFromParent_Done,
     /* 125065 */ // Label 1966: @125065
     /* 125065 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(125115), // Rule ID 5375 //
     /* 125070 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125077 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125081 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125085 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125088 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 125093 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 125097 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125102 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125104 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTNUv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 125104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i64),
     /* 125107 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125109 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125113 */   GIR_RootConstrainSelectedInstOperands,
     /* 125114 */   // GIR_Coverage, 5375,
     /* 125114 */   GIR_EraseRootFromParent_Done,
     /* 125115 */ // Label 1967: @125115
     /* 125115 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(125168), // Rule ID 5378 //
     /* 125120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125126 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125130 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125134 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125138 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125141 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 125146 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 125150 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 125155 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125157 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTPSDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 125157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDHr),
     /* 125160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125162 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125166 */   GIR_RootConstrainSelectedInstOperands,
     /* 125167 */   // GIR_Coverage, 5378,
     /* 125167 */   GIR_EraseRootFromParent_Done,
     /* 125168 */ // Label 1968: @125168
     /* 125168 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(125221), // Rule ID 5379 //
     /* 125173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125183 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125187 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125191 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125194 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 125199 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 125203 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 125208 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125210 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTPSDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 125210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDSr),
     /* 125213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125215 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125219 */   GIR_RootConstrainSelectedInstOperands,
     /* 125220 */   // GIR_Coverage, 5379,
     /* 125220 */   GIR_EraseRootFromParent_Done,
     /* 125221 */ // Label 1969: @125221
     /* 125221 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(125271), // Rule ID 5381 //
     /* 125226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125233 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125237 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125241 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125244 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 125249 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 125253 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125258 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125260 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTPSv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 125260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 125263 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125265 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125269 */   GIR_RootConstrainSelectedInstOperands,
     /* 125270 */   // GIR_Coverage, 5381,
     /* 125270 */   GIR_EraseRootFromParent_Done,
     /* 125271 */ // Label 1970: @125271
     /* 125271 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(125324), // Rule ID 5384 //
     /* 125276 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125279 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125282 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125286 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125290 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125294 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125297 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 125302 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 125306 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 125311 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125313 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn))  =>  (FCVTPUDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 125313 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDHr),
     /* 125316 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125318 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125322 */   GIR_RootConstrainSelectedInstOperands,
     /* 125323 */   // GIR_Coverage, 5384,
     /* 125323 */   GIR_EraseRootFromParent_Done,
     /* 125324 */ // Label 1971: @125324
     /* 125324 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(125377), // Rule ID 5385 //
     /* 125329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125332 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125339 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125343 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125347 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125350 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 125355 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 125359 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 125364 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125366 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn))  =>  (FCVTPUDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 125366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDSr),
     /* 125369 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125371 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125375 */   GIR_RootConstrainSelectedInstOperands,
     /* 125376 */   // GIR_Coverage, 5385,
     /* 125376 */   GIR_EraseRootFromParent_Done,
     /* 125377 */ // Label 1972: @125377
     /* 125377 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(125427), // Rule ID 5387 //
     /* 125382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125389 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125393 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125397 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125400 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 125405 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 125409 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125414 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125416 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn))  =>  (FCVTPUv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 125416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 125419 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125421 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125425 */   GIR_RootConstrainSelectedInstOperands,
     /* 125426 */   // GIR_Coverage, 5387,
     /* 125426 */   GIR_EraseRootFromParent_Done,
     /* 125427 */ // Label 1973: @125427
     /* 125427 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(125475), // Rule ID 5425 //
     /* 125432 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125435 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125442 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125446 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125450 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125453 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 125458 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 125462 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125464 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn))  =>  (FCVTZSDHr:{ *:[f64] } ?:{ *:[f16] }:$Rn)
     /* 125464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 125467 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125469 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125473 */   GIR_RootConstrainSelectedInstOperands,
     /* 125474 */   // GIR_Coverage, 5425,
     /* 125474 */   GIR_EraseRootFromParent_Done,
     /* 125475 */ // Label 1974: @125475
     /* 125475 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(125523), // Rule ID 5426 //
     /* 125480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125490 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125494 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125498 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125501 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 125506 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 125510 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125512 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[f64] } ?:{ *:[f32] }:$Rn)
     /* 125512 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 125515 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125517 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125521 */   GIR_RootConstrainSelectedInstOperands,
     /* 125522 */   // GIR_Coverage, 5426,
     /* 125522 */   GIR_EraseRootFromParent_Done,
     /* 125523 */ // Label 1975: @125523
     /* 125523 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(125568), // Rule ID 5429 //
     /* 125528 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125535 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125539 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125543 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125546 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 125551 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 125555 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125557 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[f64] } ?:{ *:[f64] }:$Rn)
     /* 125557 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 125560 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125562 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125566 */   GIR_RootConstrainSelectedInstOperands,
     /* 125567 */   // GIR_Coverage, 5429,
     /* 125567 */   GIR_EraseRootFromParent_Done,
     /* 125568 */ // Label 1976: @125568
     /* 125568 */ GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(125616), // Rule ID 5449 //
     /* 125573 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125576 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125583 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125587 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125591 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125594 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 125599 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 125603 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125605 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn))  =>  (FCVTZUDHr:{ *:[f64] } ?:{ *:[f16] }:$Rn)
     /* 125605 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 125608 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125610 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125614 */   GIR_RootConstrainSelectedInstOperands,
     /* 125615 */   // GIR_Coverage, 5449,
     /* 125615 */   GIR_EraseRootFromParent_Done,
     /* 125616 */ // Label 1977: @125616
     /* 125616 */ GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(125664), // Rule ID 5450 //
     /* 125621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125631 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125635 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125639 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125642 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 125647 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 125651 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125653 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn))  =>  (FCVTZUDSr:{ *:[f64] } ?:{ *:[f32] }:$Rn)
     /* 125653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 125656 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125658 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125662 */   GIR_RootConstrainSelectedInstOperands,
     /* 125663 */   // GIR_Coverage, 5450,
     /* 125663 */   GIR_EraseRootFromParent_Done,
     /* 125664 */ // Label 1978: @125664
     /* 125664 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(125709), // Rule ID 5453 //
     /* 125669 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125676 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125680 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 125684 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 125687 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 125692 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 125696 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 125698 */   // (bitconvert:{ *:[f64] } (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn))  =>  (FCVTZUv1i64:{ *:[f64] } ?:{ *:[f64] }:$Rn)
     /* 125698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 125701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125703 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 125707 */   GIR_RootConstrainSelectedInstOperands,
     /* 125708 */   // GIR_Coverage, 5453,
     /* 125708 */   GIR_EraseRootFromParent_Done,
     /* 125709 */ // Label 1979: @125709
     /* 125709 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(125761), // Rule ID 5540 //
     /* 125714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125717 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125724 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125728 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125732 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 125736 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125740 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 125744 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 125748 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 125750 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTPSDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 125750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDSr),
     /* 125753 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125755 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 125759 */   GIR_RootConstrainSelectedInstOperands,
     /* 125760 */   // GIR_Coverage, 5540,
     /* 125760 */   GIR_EraseRootFromParent_Done,
     /* 125761 */ // Label 1980: @125761
     /* 125761 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(125810), // Rule ID 5543 //
     /* 125766 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125769 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125773 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125777 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125781 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 125785 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125789 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 125793 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 125797 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 125799 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTPSv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 125799 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 125802 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125804 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 125808 */   GIR_RootConstrainSelectedInstOperands,
     /* 125809 */   // GIR_Coverage, 5543,
     /* 125809 */   GIR_EraseRootFromParent_Done,
     /* 125810 */ // Label 1981: @125810
     /* 125810 */ GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(125862), // Rule ID 5600 //
     /* 125815 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125818 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125821 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125825 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125829 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125833 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 125837 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125841 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 125845 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 125849 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 125851 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTMSDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 125851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDSr),
     /* 125854 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125856 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 125860 */   GIR_RootConstrainSelectedInstOperands,
     /* 125861 */   // GIR_Coverage, 5600,
     /* 125861 */   GIR_EraseRootFromParent_Done,
     /* 125862 */ // Label 1982: @125862
     /* 125862 */ GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(125911), // Rule ID 5603 //
     /* 125867 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125874 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125878 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125882 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 125886 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125890 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 125894 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 125898 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 125900 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTMSv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 125900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 125903 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125905 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 125909 */   GIR_RootConstrainSelectedInstOperands,
     /* 125910 */   // GIR_Coverage, 5603,
     /* 125910 */   GIR_EraseRootFromParent_Done,
     /* 125911 */ // Label 1983: @125911
     /* 125911 */ GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(125963), // Rule ID 5720 //
     /* 125916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 125919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125926 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125930 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125934 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 125938 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125942 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 125946 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 125950 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 125952 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTASDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 125952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 125955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 125957 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 125961 */   GIR_RootConstrainSelectedInstOperands,
     /* 125962 */   // GIR_Coverage, 5720,
     /* 125962 */   GIR_EraseRootFromParent_Done,
     /* 125963 */ // Label 1984: @125963
     /* 125963 */ GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(126012), // Rule ID 5723 //
     /* 125968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 125971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 125975 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 125979 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 125983 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 125987 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 125991 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 125995 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 125999 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126001 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTASv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 126004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126006 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126010 */   GIR_RootConstrainSelectedInstOperands,
     /* 126011 */   // GIR_Coverage, 5723,
     /* 126011 */   GIR_EraseRootFromParent_Done,
     /* 126012 */ // Label 1985: @126012
     /* 126012 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(126064), // Rule ID 5660 //
     /* 126017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126027 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126031 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 126035 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126039 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126043 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 126047 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 126051 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126053 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTZSDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 126053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 126056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126058 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126062 */   GIR_RootConstrainSelectedInstOperands,
     /* 126063 */   // GIR_Coverage, 5660,
     /* 126063 */   GIR_EraseRootFromParent_Done,
     /* 126064 */ // Label 1986: @126064
     /* 126064 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(126113), // Rule ID 5663 //
     /* 126069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126076 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126080 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 126084 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126088 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126092 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 126096 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 126100 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126102 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTZSv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 126105 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126107 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126111 */   GIR_RootConstrainSelectedInstOperands,
     /* 126112 */   // GIR_Coverage, 5663,
     /* 126112 */   GIR_EraseRootFromParent_Done,
     /* 126113 */ // Label 1987: @126113
     /* 126113 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(126165), // Rule ID 5570 //
     /* 126118 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126121 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126128 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126132 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126136 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126140 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126144 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 126148 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 126152 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126154 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTPUDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 126154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDSr),
     /* 126157 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126159 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126163 */   GIR_RootConstrainSelectedInstOperands,
     /* 126164 */   // GIR_Coverage, 5570,
     /* 126164 */   GIR_EraseRootFromParent_Done,
     /* 126165 */ // Label 1988: @126165
     /* 126165 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(126214), // Rule ID 5573 //
     /* 126170 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126173 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126177 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126181 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126185 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126189 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126193 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 126197 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 126201 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126203 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTPUv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126203 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 126206 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126208 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126212 */   GIR_RootConstrainSelectedInstOperands,
     /* 126213 */   // GIR_Coverage, 5573,
     /* 126213 */   GIR_EraseRootFromParent_Done,
     /* 126214 */ // Label 1989: @126214
     /* 126214 */ GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(126266), // Rule ID 5630 //
     /* 126219 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126222 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126225 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126229 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126233 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126237 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126241 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126245 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 126249 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 126253 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126255 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTMUDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 126255 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDSr),
     /* 126258 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126260 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126264 */   GIR_RootConstrainSelectedInstOperands,
     /* 126265 */   // GIR_Coverage, 5630,
     /* 126265 */   GIR_EraseRootFromParent_Done,
     /* 126266 */ // Label 1990: @126266
     /* 126266 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(126315), // Rule ID 5633 //
     /* 126271 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126274 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126278 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126282 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126286 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126290 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126294 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 126298 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 126302 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126304 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTMUv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 126307 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126309 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126313 */   GIR_RootConstrainSelectedInstOperands,
     /* 126314 */   // GIR_Coverage, 5633,
     /* 126314 */   GIR_EraseRootFromParent_Done,
     /* 126315 */ // Label 1991: @126315
     /* 126315 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(126367), // Rule ID 5750 //
     /* 126320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126323 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126330 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126334 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126338 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126342 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126346 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 126350 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 126354 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126356 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTAUDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 126356 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDSr),
     /* 126359 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126361 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126365 */   GIR_RootConstrainSelectedInstOperands,
     /* 126366 */   // GIR_Coverage, 5750,
     /* 126366 */   GIR_EraseRootFromParent_Done,
     /* 126367 */ // Label 1992: @126367
     /* 126367 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(126416), // Rule ID 5753 //
     /* 126372 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126375 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126379 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126383 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126387 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126391 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126395 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 126399 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 126403 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126405 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTAUv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126405 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 126408 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126410 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126414 */   GIR_RootConstrainSelectedInstOperands,
     /* 126415 */   // GIR_Coverage, 5753,
     /* 126415 */   GIR_EraseRootFromParent_Done,
     /* 126416 */ // Label 1993: @126416
     /* 126416 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(126468), // Rule ID 5690 //
     /* 126421 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126424 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126431 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126435 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126439 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126443 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126447 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 126451 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 126455 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126457 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn)))  =>  (FCVTZUDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 126457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 126460 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126462 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126466 */   GIR_RootConstrainSelectedInstOperands,
     /* 126467 */   // GIR_Coverage, 5690,
     /* 126467 */   GIR_EraseRootFromParent_Done,
     /* 126468 */ // Label 1994: @126468
     /* 126468 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(126517), // Rule ID 5693 //
     /* 126473 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126480 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126484 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126488 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126492 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 126496 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 126500 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 126504 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 126506 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn)))  =>  (FCVTZUv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 126506 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 126509 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126511 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 126515 */   GIR_RootConstrainSelectedInstOperands,
     /* 126516 */   // GIR_Coverage, 5693,
     /* 126516 */   GIR_EraseRootFromParent_Done,
     /* 126517 */ // Label 1995: @126517
     /* 126517 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(126562), // Rule ID 5393 //
     /* 126522 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126532 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126536 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 126540 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 126544 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 126549 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126551 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn))  =>  (FCVTZSDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 126551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 126554 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126556 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126560 */   GIR_RootConstrainSelectedInstOperands,
     /* 126561 */   // GIR_Coverage, 5393,
     /* 126561 */   GIR_EraseRootFromParent_Done,
     /* 126562 */ // Label 1996: @126562
     /* 126562 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(126607), // Rule ID 5395 //
     /* 126567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126577 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126581 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 126585 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126589 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 126594 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126596 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 126596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 126599 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126601 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126605 */   GIR_RootConstrainSelectedInstOperands,
     /* 126606 */   // GIR_Coverage, 5395,
     /* 126606 */   GIR_EraseRootFromParent_Done,
     /* 126607 */ // Label 1997: @126607
     /* 126607 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(126649), // Rule ID 5399 //
     /* 126612 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126615 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126619 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126623 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 126627 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126631 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126636 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126638 */   // (bitconvert:{ *:[f64] } (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 126638 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 126641 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126643 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126647 */   GIR_RootConstrainSelectedInstOperands,
     /* 126648 */   // GIR_Coverage, 5399,
     /* 126648 */   GIR_EraseRootFromParent_Done,
     /* 126649 */ // Label 1998: @126649
     /* 126649 */ GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(126694), // Rule ID 5405 //
     /* 126654 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126664 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126668 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126672 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 126676 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 126681 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126683 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn))  =>  (FCVTZUDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 126683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 126686 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126688 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126692 */   GIR_RootConstrainSelectedInstOperands,
     /* 126693 */   // GIR_Coverage, 5405,
     /* 126693 */   GIR_EraseRootFromParent_Done,
     /* 126694 */ // Label 1999: @126694
     /* 126694 */ GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(126739), // Rule ID 5407 //
     /* 126699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126709 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126713 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126717 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126721 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 126726 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126728 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn))  =>  (FCVTZUDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 126728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 126731 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126733 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126737 */   GIR_RootConstrainSelectedInstOperands,
     /* 126738 */   // GIR_Coverage, 5407,
     /* 126738 */   GIR_EraseRootFromParent_Done,
     /* 126739 */ // Label 2000: @126739
     /* 126739 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(126781), // Rule ID 5411 //
     /* 126744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126751 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126755 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 126759 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126763 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126768 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126770 */   // (bitconvert:{ *:[f64] } (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (FCVTZUv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 126770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 126773 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126775 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126779 */   GIR_RootConstrainSelectedInstOperands,
     /* 126780 */   // GIR_Coverage, 5411,
     /* 126780 */   GIR_EraseRootFromParent_Done,
     /* 126781 */ // Label 2001: @126781
     /* 126781 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(126838), // Rule ID 5813 //
     /* 126786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126789 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126796 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126800 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LLRINT),
     /* 126804 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 126808 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126810 */   // (bitconvert:{ *:[f64] } (llrint:{ *:[i64] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZSDHr:{ *:[f64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 126810 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 126813 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 126817 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 126822 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126826 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 126828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 126831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126833 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 126836 */   GIR_RootConstrainSelectedInstOperands,
     /* 126837 */   // GIR_Coverage, 5813,
     /* 126837 */   GIR_EraseRootFromParent_Done,
     /* 126838 */ // Label 2002: @126838
     /* 126838 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(126895), // Rule ID 5819 //
     /* 126843 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126846 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126853 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126857 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LLRINT),
     /* 126861 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 126865 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126867 */   // (bitconvert:{ *:[f64] } (llrint:{ *:[i64] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[f64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 126867 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 126870 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 126874 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 126879 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126883 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 126885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 126888 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126890 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 126893 */   GIR_RootConstrainSelectedInstOperands,
     /* 126894 */   // GIR_Coverage, 5819,
     /* 126894 */   GIR_EraseRootFromParent_Done,
     /* 126895 */ // Label 2003: @126895
     /* 126895 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(126949), // Rule ID 5825 //
     /* 126900 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126907 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126911 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LLRINT),
     /* 126915 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 126919 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126921 */   // (bitconvert:{ *:[f64] } (llrint:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[f64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 126921 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 126924 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 126928 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 126933 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126937 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 126939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 126942 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 126944 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 126947 */   GIR_RootConstrainSelectedInstOperands,
     /* 126948 */   // GIR_Coverage, 5825,
     /* 126948 */   GIR_EraseRootFromParent_Done,
     /* 126949 */ // Label 2004: @126949
     /* 126949 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(127006), // Rule ID 5811 //
     /* 126954 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 126957 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 126960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 126964 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 126968 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 126972 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 126976 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 126978 */   // (bitconvert:{ *:[f64] } (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZSDHr:{ *:[f64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 126978 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 126981 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 126985 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 126990 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 126994 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 126996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 126999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127001 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127004 */   GIR_RootConstrainSelectedInstOperands,
     /* 127005 */   // GIR_Coverage, 5811,
     /* 127005 */   GIR_EraseRootFromParent_Done,
     /* 127006 */ // Label 2005: @127006
     /* 127006 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(127063), // Rule ID 5815 //
     /* 127011 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 127014 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127021 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127025 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 127029 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 127033 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127035 */   // (bitconvert:{ *:[f64] } (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[f64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 127035 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 127038 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 127042 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127047 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127051 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 127053 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 127056 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127058 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127061 */   GIR_RootConstrainSelectedInstOperands,
     /* 127062 */   // GIR_Coverage, 5815,
     /* 127062 */   GIR_EraseRootFromParent_Done,
     /* 127063 */ // Label 2006: @127063
     /* 127063 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(127117), // Rule ID 5823 //
     /* 127068 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127071 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127075 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127079 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_LRINT),
     /* 127083 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 127087 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127089 */   // (bitconvert:{ *:[f64] } (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[f64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 127089 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127092 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 127096 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127101 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127105 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 127107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 127110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127112 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127115 */   GIR_RootConstrainSelectedInstOperands,
     /* 127116 */   // GIR_Coverage, 5823,
     /* 127116 */   GIR_EraseRootFromParent_Done,
     /* 127117 */ // Label 2007: @127117
     /* 127117 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(127157), // Rule ID 5786 //
     /* 127122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 127125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127132 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127136 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LLROUND),
     /* 127140 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 127144 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127146 */   // (bitconvert:{ *:[f64] } (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn))  =>  (FCVTASDHr:{ *:[f64] } f16:{ *:[f16] }:$Rn)
     /* 127146 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 127149 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127151 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127155 */   GIR_RootConstrainSelectedInstOperands,
     /* 127156 */   // GIR_Coverage, 5786,
     /* 127156 */   GIR_EraseRootFromParent_Done,
     /* 127157 */ // Label 2008: @127157
     /* 127157 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(127197), // Rule ID 5792 //
     /* 127162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 127165 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127168 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127172 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127176 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LLROUND),
     /* 127180 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 127184 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127186 */   // (bitconvert:{ *:[f64] } (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 127186 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 127189 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127191 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127195 */   GIR_RootConstrainSelectedInstOperands,
     /* 127196 */   // GIR_Coverage, 5792,
     /* 127196 */   GIR_EraseRootFromParent_Done,
     /* 127197 */ // Label 2009: @127197
     /* 127197 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(127234), // Rule ID 5798 //
     /* 127202 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127209 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127213 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LLROUND),
     /* 127217 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 127221 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127223 */   // (bitconvert:{ *:[f64] } (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 127223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 127226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127228 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127232 */   GIR_RootConstrainSelectedInstOperands,
     /* 127233 */   // GIR_Coverage, 5798,
     /* 127233 */   GIR_EraseRootFromParent_Done,
     /* 127234 */ // Label 2010: @127234
     /* 127234 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(127274), // Rule ID 5784 //
     /* 127239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 127242 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127245 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127249 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127253 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 127257 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 127261 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127263 */   // (bitconvert:{ *:[f64] } (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn))  =>  (FCVTASDHr:{ *:[f64] } f16:{ *:[f16] }:$Rn)
     /* 127263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 127266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127268 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127272 */   GIR_RootConstrainSelectedInstOperands,
     /* 127273 */   // GIR_Coverage, 5784,
     /* 127273 */   GIR_EraseRootFromParent_Done,
     /* 127274 */ // Label 2011: @127274
     /* 127274 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(127314), // Rule ID 5788 //
     /* 127279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 127282 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127289 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127293 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 127297 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 127301 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127303 */   // (bitconvert:{ *:[f64] } (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASDSr:{ *:[f64] } f32:{ *:[f32] }:$Rn)
     /* 127303 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 127306 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127308 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127312 */   GIR_RootConstrainSelectedInstOperands,
     /* 127313 */   // GIR_Coverage, 5788,
     /* 127313 */   GIR_EraseRootFromParent_Done,
     /* 127314 */ // Label 2012: @127314
     /* 127314 */ GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(127351), // Rule ID 5796 //
     /* 127319 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127322 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127326 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 127330 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LROUND),
     /* 127334 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 127338 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 127340 */   // (bitconvert:{ *:[f64] } (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASv1i64:{ *:[f64] } f64:{ *:[f64] }:$Rn)
     /* 127340 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 127343 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127345 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 127349 */   GIR_RootConstrainSelectedInstOperands,
     /* 127350 */   // GIR_Coverage, 5796,
     /* 127350 */   GIR_EraseRootFromParent_Done,
     /* 127351 */ // Label 2013: @127351
     /* 127351 */ GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(127381), // Rule ID 7295 //
     /* 127356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127359 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 127362 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127366 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127370 */   // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] })
     /* 127370 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127375 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127380 */   // GIR_Coverage, 7295,
     /* 127380 */   GIR_Done,
     /* 127381 */ // Label 2014: @127381
     /* 127381 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(127411), // Rule ID 7296 //
     /* 127386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127389 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 127392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127396 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127400 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] })
     /* 127400 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127405 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127410 */   // GIR_Coverage, 7296,
     /* 127410 */   GIR_Done,
     /* 127411 */ // Label 2015: @127411
     /* 127411 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(127441), // Rule ID 7297 //
     /* 127416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127419 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 127422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127426 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127430 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] })
     /* 127430 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127435 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127440 */   // GIR_Coverage, 7297,
     /* 127440 */   GIR_Done,
     /* 127441 */ // Label 2016: @127441
     /* 127441 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(127471), // Rule ID 7298 //
     /* 127446 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127449 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 127452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127456 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127460 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] })
     /* 127460 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127465 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127470 */   // GIR_Coverage, 7298,
     /* 127470 */   GIR_Done,
     /* 127471 */ // Label 2017: @127471
     /* 127471 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(127501), // Rule ID 7299 //
     /* 127476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 127482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127486 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127490 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] })
     /* 127490 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127495 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127500 */   // GIR_Coverage, 7299,
     /* 127500 */   GIR_Done,
     /* 127501 */ // Label 2018: @127501
     /* 127501 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(127531), // Rule ID 7300 //
     /* 127506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127509 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127516 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127520 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
     /* 127520 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127525 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127530 */   // GIR_Coverage, 7300,
     /* 127530 */   GIR_Done,
     /* 127531 */ // Label 2019: @127531
     /* 127531 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(127581), // Rule ID 7306 //
     /* 127536 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 127539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 127542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127546 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127550 */   // (bitconvert:{ *:[i64] } V64:{ *:[v8i8] }:$Vn)  =>  (REV64v8i8:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v8i8] }:$Vn, GPR64:{ *:[i32] }))
     /* 127550 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127553 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127557 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127562 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 127566 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127571 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 127574 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127576 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127579 */   GIR_RootConstrainSelectedInstOperands,
     /* 127580 */   // GIR_Coverage, 7306,
     /* 127580 */   GIR_EraseRootFromParent_Done,
     /* 127581 */ // Label 2020: @127581
     /* 127581 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(127631), // Rule ID 7307 //
     /* 127586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 127589 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 127592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127596 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127600 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4i16] }:$Vn)  =>  (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4i16] }:$Vn, GPR64:{ *:[i32] }))
     /* 127600 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127603 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127607 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127612 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 127616 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 127624 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127626 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127629 */   GIR_RootConstrainSelectedInstOperands,
     /* 127630 */   // GIR_Coverage, 7307,
     /* 127630 */   GIR_EraseRootFromParent_Done,
     /* 127631 */ // Label 2021: @127631
     /* 127631 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(127681), // Rule ID 7308 //
     /* 127636 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 127639 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 127642 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127646 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127650 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2i32] }:$Vn)  =>  (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2i32] }:$Vn, GPR64:{ *:[i32] }))
     /* 127650 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127653 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127657 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127662 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 127666 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127671 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 127674 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127676 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127679 */   GIR_RootConstrainSelectedInstOperands,
     /* 127680 */   // GIR_Coverage, 7308,
     /* 127680 */   GIR_EraseRootFromParent_Done,
     /* 127681 */ // Label 2022: @127681
     /* 127681 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(127731), // Rule ID 7309 //
     /* 127686 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 127689 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 127692 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127696 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127700 */   // (bitconvert:{ *:[i64] } V64:{ *:[v4f16] }:$Vn)  =>  (REV64v4i16:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v4f16] }:$Vn, GPR64:{ *:[i32] }))
     /* 127700 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127703 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127707 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127712 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 127716 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 127724 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127726 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127729 */   GIR_RootConstrainSelectedInstOperands,
     /* 127730 */   // GIR_Coverage, 7309,
     /* 127730 */   GIR_EraseRootFromParent_Done,
     /* 127731 */ // Label 2023: @127731
     /* 127731 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(127781), // Rule ID 7310 //
     /* 127736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 127739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 127742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127746 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127750 */   // (bitconvert:{ *:[i64] } V64:{ *:[v2f32] }:$Vn)  =>  (REV64v2i32:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v2f32] }:$Vn, GPR64:{ *:[i32] }))
     /* 127750 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 127753 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127757 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 127762 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Vn
     /* 127766 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127771 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 127774 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 127776 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 127779 */   GIR_RootConstrainSelectedInstOperands,
     /* 127780 */   // GIR_Coverage, 7310,
     /* 127780 */   GIR_EraseRootFromParent_Done,
     /* 127781 */ // Label 2024: @127781
     /* 127781 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(127808), // Rule ID 7311 //
     /* 127786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127793 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127797 */   // (bitconvert:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 127797 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127802 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127807 */   // GIR_Coverage, 7311,
     /* 127807 */   GIR_Done,
     /* 127808 */ // Label 2025: @127808
     /* 127808 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(127835), // Rule ID 7312 //
     /* 127813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127820 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127824 */   // (bitconvert:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 127824 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127829 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127834 */   // GIR_Coverage, 7312,
     /* 127834 */   GIR_Done,
     /* 127835 */ // Label 2026: @127835
     /* 127835 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(127862), // Rule ID 7313 //
     /* 127840 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127847 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127851 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1i64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1i64] }:$Vn, GPR64:{ *:[i32] })
     /* 127851 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127856 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127861 */   // GIR_Coverage, 7313,
     /* 127861 */   GIR_Done,
     /* 127862 */ // Label 2027: @127862
     /* 127862 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(127889), // Rule ID 7322 //
     /* 127867 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127874 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127878 */   // (bitconvert:{ *:[f64] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 127878 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127883 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127888 */   // GIR_Coverage, 7322,
     /* 127888 */   GIR_Done,
     /* 127889 */ // Label 2028: @127889
     /* 127889 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(127916), // Rule ID 7323 //
     /* 127894 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127901 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127905 */   // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } FPR64:{ *:[f64] }:$Xn, GPR64:{ *:[i32] })
     /* 127905 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127910 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127915 */   // GIR_Coverage, 7323,
     /* 127915 */   GIR_Done,
     /* 127916 */ // Label 2029: @127916
     /* 127916 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(127943), // Rule ID 7324 //
     /* 127921 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 127924 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127928 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127932 */   // (bitconvert:{ *:[i64] } V64:{ *:[v1f64] }:$Vn)  =>  (COPY_TO_REGCLASS:{ *:[i64] } V64:{ *:[v1f64] }:$Vn, GPR64:{ *:[i32] })
     /* 127932 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127937 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 127942 */   // GIR_Coverage, 7324,
     /* 127942 */   GIR_Done,
     /* 127943 */ // Label 2030: @127943
     /* 127943 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(127975), // Rule ID 7325 //
     /* 127948 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127951 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 127954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127958 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127962 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 127962 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127965 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 127967 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 127969 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127974 */   // GIR_Coverage, 7325,
     /* 127974 */   GIR_EraseRootFromParent_Done,
     /* 127975 */ // Label 2031: @127975
     /* 127975 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(128007), // Rule ID 7326 //
     /* 127980 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 127983 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 127986 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127990 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 127994 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 127994 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 127997 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 127999 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128001 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128006 */   // GIR_Coverage, 7326,
     /* 128006 */   GIR_EraseRootFromParent_Done,
     /* 128007 */ // Label 2032: @128007
     /* 128007 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(128039), // Rule ID 7327 //
     /* 128012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128026 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 128026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128029 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128031 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128033 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128038 */   // GIR_Coverage, 7327,
     /* 128038 */   GIR_EraseRootFromParent_Done,
     /* 128039 */ // Label 2033: @128039
     /* 128039 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(128071), // Rule ID 7328 //
     /* 128044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128047 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128054 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128058 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 128058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128061 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128063 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128065 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128070 */   // GIR_Coverage, 7328,
     /* 128070 */   GIR_EraseRootFromParent_Done,
     /* 128071 */ // Label 2034: @128071
     /* 128071 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(128103), // Rule ID 7329 //
     /* 128076 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128079 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128086 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128090 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 128090 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128093 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128095 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128097 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128102 */   // GIR_Coverage, 7329,
     /* 128102 */   GIR_EraseRootFromParent_Done,
     /* 128103 */ // Label 2035: @128103
     /* 128103 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(128129), // Rule ID 7330 //
     /* 128108 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128111 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128118 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128122 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2i32] }:$src)
     /* 128122 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128127 */   GIR_RootConstrainSelectedInstOperands,
     /* 128128 */   // GIR_Coverage, 7330,
     /* 128128 */   GIR_Done,
     /* 128129 */ // Label 2036: @128129
     /* 128129 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(128155), // Rule ID 7331 //
     /* 128134 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128137 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128144 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128148 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4i16] }:$src)
     /* 128148 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128153 */   GIR_RootConstrainSelectedInstOperands,
     /* 128154 */   // GIR_Coverage, 7331,
     /* 128154 */   GIR_Done,
     /* 128155 */ // Label 2037: @128155
     /* 128155 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(128181), // Rule ID 7332 //
     /* 128160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128170 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128174 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[v1i64] } FPR64:{ *:[v8i8] }:$src)
     /* 128174 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 128179 */   GIR_RootConstrainSelectedInstOperands,
     /* 128180 */   // GIR_Coverage, 7332,
     /* 128180 */   GIR_Done,
     /* 128181 */ // Label 2038: @128181
     /* 128181 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(128207), // Rule ID 7333 //
     /* 128186 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128196 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128200 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[v1i64] } FPR64:{ *:[v4f16] }:$src)
     /* 128200 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128205 */   GIR_RootConstrainSelectedInstOperands,
     /* 128206 */   // GIR_Coverage, 7333,
     /* 128206 */   GIR_Done,
     /* 128207 */ // Label 2039: @128207
     /* 128207 */ GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(128233), // Rule ID 7334 //
     /* 128212 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128215 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128218 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128222 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128226 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[v1i64] } FPR64:{ *:[v2f32] }:$src)
     /* 128226 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128231 */   GIR_RootConstrainSelectedInstOperands,
     /* 128232 */   // GIR_Coverage, 7334,
     /* 128232 */   GIR_Done,
     /* 128233 */ // Label 2040: @128233
     /* 128233 */ GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(128262), // Rule ID 7335 //
     /* 128238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128241 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128245 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128249 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 128249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128252 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128254 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128256 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128261 */   // GIR_Coverage, 7335,
     /* 128261 */   GIR_EraseRootFromParent_Done,
     /* 128262 */ // Label 2041: @128262
     /* 128262 */ GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(128291), // Rule ID 7336 //
     /* 128267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128274 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128278 */   // (bitconvert:{ *:[v1i64] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v1i64] }:$src
     /* 128278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128281 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128283 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128285 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128290 */   // GIR_Coverage, 7336,
     /* 128290 */   GIR_EraseRootFromParent_Done,
     /* 128291 */ // Label 2042: @128291
     /* 128291 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(128323), // Rule ID 7390 //
     /* 128296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128299 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128306 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128310 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128310 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128313 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128315 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128317 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128322 */   // GIR_Coverage, 7390,
     /* 128322 */   GIR_EraseRootFromParent_Done,
     /* 128323 */ // Label 2043: @128323
     /* 128323 */ GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(128355), // Rule ID 7391 //
     /* 128328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128338 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128342 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128345 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128347 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128349 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128354 */   // GIR_Coverage, 7391,
     /* 128354 */   GIR_EraseRootFromParent_Done,
     /* 128355 */ // Label 2044: @128355
     /* 128355 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(128387), // Rule ID 7392 //
     /* 128360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128370 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128374 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128377 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128379 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128381 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128386 */   // GIR_Coverage, 7392,
     /* 128386 */   GIR_EraseRootFromParent_Done,
     /* 128387 */ // Label 2045: @128387
     /* 128387 */ GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(128419), // Rule ID 7393 //
     /* 128392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128402 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128406 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128406 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128409 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128411 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128413 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128418 */   // GIR_Coverage, 7393,
     /* 128418 */   GIR_EraseRootFromParent_Done,
     /* 128419 */ // Label 2046: @128419
     /* 128419 */ GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(128451), // Rule ID 7394 //
     /* 128424 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128427 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128434 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128438 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128441 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128443 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128445 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128450 */   // GIR_Coverage, 7394,
     /* 128450 */   GIR_EraseRootFromParent_Done,
     /* 128451 */ // Label 2047: @128451
     /* 128451 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(128477), // Rule ID 7395 //
     /* 128456 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128459 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128466 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128470 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2i32] }:$src)
     /* 128470 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128475 */   GIR_RootConstrainSelectedInstOperands,
     /* 128476 */   // GIR_Coverage, 7395,
     /* 128476 */   GIR_Done,
     /* 128477 */ // Label 2048: @128477
     /* 128477 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(128503), // Rule ID 7396 //
     /* 128482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128492 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128496 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4i16] }:$src)
     /* 128496 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128501 */   GIR_RootConstrainSelectedInstOperands,
     /* 128502 */   // GIR_Coverage, 7396,
     /* 128502 */   GIR_Done,
     /* 128503 */ // Label 2049: @128503
     /* 128503 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(128529), // Rule ID 7397 //
     /* 128508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128511 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128518 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128522 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[f64] } FPR64:{ *:[v2f32] }:$src)
     /* 128522 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128527 */   GIR_RootConstrainSelectedInstOperands,
     /* 128528 */   // GIR_Coverage, 7397,
     /* 128528 */   GIR_Done,
     /* 128529 */ // Label 2050: @128529
     /* 128529 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(128555), // Rule ID 7398 //
     /* 128534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128537 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128544 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128548 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[f64] } FPR64:{ *:[v8i8] }:$src)
     /* 128548 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 128553 */   GIR_RootConstrainSelectedInstOperands,
     /* 128554 */   // GIR_Coverage, 7398,
     /* 128554 */   GIR_Done,
     /* 128555 */ // Label 2051: @128555
     /* 128555 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(128581), // Rule ID 7399 //
     /* 128560 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128563 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128570 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128574 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[f64] } FPR64:{ *:[v4f16] }:$src)
     /* 128574 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128579 */   GIR_RootConstrainSelectedInstOperands,
     /* 128580 */   // GIR_Coverage, 7399,
     /* 128580 */   GIR_Done,
     /* 128581 */ // Label 2052: @128581
     /* 128581 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(128610), // Rule ID 7400 //
     /* 128586 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128593 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128597 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128600 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128602 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128604 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128609 */   // GIR_Coverage, 7400,
     /* 128609 */   GIR_EraseRootFromParent_Done,
     /* 128610 */ // Label 2053: @128610
     /* 128610 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(128639), // Rule ID 7401 //
     /* 128615 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128622 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128626 */   // (bitconvert:{ *:[f64] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[f64] }:$src
     /* 128626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128629 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128631 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128633 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128638 */   // GIR_Coverage, 7401,
     /* 128638 */   GIR_EraseRootFromParent_Done,
     /* 128639 */ // Label 2054: @128639
     /* 128639 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(128671), // Rule ID 7402 //
     /* 128644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128647 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128654 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128658 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128661 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128663 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128670 */   // GIR_Coverage, 7402,
     /* 128670 */   GIR_EraseRootFromParent_Done,
     /* 128671 */ // Label 2055: @128671
     /* 128671 */ GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(128703), // Rule ID 7403 //
     /* 128676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128686 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128690 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128693 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128695 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128697 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128702 */   // GIR_Coverage, 7403,
     /* 128702 */   GIR_EraseRootFromParent_Done,
     /* 128703 */ // Label 2056: @128703
     /* 128703 */ GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(128735), // Rule ID 7404 //
     /* 128708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128718 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128722 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128725 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128727 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128729 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128734 */   // GIR_Coverage, 7404,
     /* 128734 */   GIR_EraseRootFromParent_Done,
     /* 128735 */ // Label 2057: @128735
     /* 128735 */ GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(128767), // Rule ID 7405 //
     /* 128740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128754 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128757 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128759 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128761 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128766 */   // GIR_Coverage, 7405,
     /* 128766 */   GIR_EraseRootFromParent_Done,
     /* 128767 */ // Label 2058: @128767
     /* 128767 */ GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(128799), // Rule ID 7406 //
     /* 128772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128782 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128786 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128789 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128791 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128793 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128798 */   // GIR_Coverage, 7406,
     /* 128798 */   GIR_EraseRootFromParent_Done,
     /* 128799 */ // Label 2059: @128799
     /* 128799 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(128825), // Rule ID 7407 //
     /* 128804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128807 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128814 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128818 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)  =>  (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2i32] }:$src)
     /* 128818 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128823 */   GIR_RootConstrainSelectedInstOperands,
     /* 128824 */   // GIR_Coverage, 7407,
     /* 128824 */   GIR_Done,
     /* 128825 */ // Label 2060: @128825
     /* 128825 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(128851), // Rule ID 7408 //
     /* 128830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128833 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128840 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128844 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)  =>  (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4i16] }:$src)
     /* 128844 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128849 */   GIR_RootConstrainSelectedInstOperands,
     /* 128850 */   // GIR_Coverage, 7408,
     /* 128850 */   GIR_Done,
     /* 128851 */ // Label 2061: @128851
     /* 128851 */ GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(128877), // Rule ID 7409 //
     /* 128856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 128862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128866 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128870 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)  =>  (REV64v8i8:{ *:[v1f64] } FPR64:{ *:[v8i8] }:$src)
     /* 128870 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 128875 */   GIR_RootConstrainSelectedInstOperands,
     /* 128876 */   // GIR_Coverage, 7409,
     /* 128876 */   GIR_Done,
     /* 128877 */ // Label 2062: @128877
     /* 128877 */ GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(128903), // Rule ID 7410 //
     /* 128882 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128885 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 128888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128892 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128896 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)  =>  (REV64v2i32:{ *:[v1f64] } FPR64:{ *:[v2f32] }:$src)
     /* 128896 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 128901 */   GIR_RootConstrainSelectedInstOperands,
     /* 128902 */   // GIR_Coverage, 7410,
     /* 128902 */   GIR_Done,
     /* 128903 */ // Label 2063: @128903
     /* 128903 */ GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(128929), // Rule ID 7411 //
     /* 128908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 128911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 128914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128922 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)  =>  (REV64v4i16:{ *:[v1f64] } FPR64:{ *:[v4f16] }:$src)
     /* 128922 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 128927 */   GIR_RootConstrainSelectedInstOperands,
     /* 128928 */   // GIR_Coverage, 7411,
     /* 128928 */   GIR_Done,
     /* 128929 */ // Label 2064: @128929
     /* 128929 */ GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(128958), // Rule ID 7412 //
     /* 128934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128937 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128941 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128945 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128945 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128948 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128950 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128952 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128957 */   // GIR_Coverage, 7412,
     /* 128957 */   GIR_EraseRootFromParent_Done,
     /* 128958 */ // Label 2065: @128958
     /* 128958 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(128987), // Rule ID 7413 //
     /* 128963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 128966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128970 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128974 */   // (bitconvert:{ *:[v1f64] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v1f64] }:$src
     /* 128974 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 128977 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 128979 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 128981 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 128986 */   // GIR_Coverage, 7413,
     /* 128986 */   GIR_EraseRootFromParent_Done,
     /* 128987 */ // Label 2066: @128987
     /* 128987 */ GIM_Reject,
     /* 128988 */ // Label 1844: @128988
     /* 128988 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(129020), // Rule ID 7427 //
     /* 128993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 128996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 128999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129003 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129007 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129010 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129012 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129014 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129019 */   // GIR_Coverage, 7427,
     /* 129019 */   GIR_EraseRootFromParent_Done,
     /* 129020 */ // Label 2067: @129020
     /* 129020 */ GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(129052), // Rule ID 7428 //
     /* 129025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 129031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129035 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129039 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129039 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129042 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129044 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129046 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129051 */   // GIR_Coverage, 7428,
     /* 129051 */   GIR_EraseRootFromParent_Done,
     /* 129052 */ // Label 2068: @129052
     /* 129052 */ GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(129084), // Rule ID 7429 //
     /* 129057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 129063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129067 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129071 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129074 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129076 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129078 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129083 */   // GIR_Coverage, 7429,
     /* 129083 */   GIR_EraseRootFromParent_Done,
     /* 129084 */ // Label 2069: @129084
     /* 129084 */ GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(129116), // Rule ID 7430 //
     /* 129089 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129092 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 129095 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129099 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129103 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129106 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129108 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129110 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129115 */   // GIR_Coverage, 7430,
     /* 129115 */   GIR_EraseRootFromParent_Done,
     /* 129116 */ // Label 2070: @129116
     /* 129116 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(129148), // Rule ID 7431 //
     /* 129121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129124 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 129127 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129131 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129135 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129138 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129140 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129142 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129147 */   // GIR_Coverage, 7431,
     /* 129147 */   GIR_EraseRootFromParent_Done,
     /* 129148 */ // Label 2071: @129148
     /* 129148 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(129180), // Rule ID 7432 //
     /* 129153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 129159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129163 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129167 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129167 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129170 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129172 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129174 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129179 */   // GIR_Coverage, 7432,
     /* 129179 */   GIR_EraseRootFromParent_Done,
     /* 129180 */ // Label 2072: @129180
     /* 129180 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(129212), // Rule ID 7433 //
     /* 129185 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129188 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 129191 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129195 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129199 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[f128] }:$src
     /* 129199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129202 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129204 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129206 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129211 */   // GIR_Coverage, 7433,
     /* 129211 */   GIR_EraseRootFromParent_Done,
     /* 129212 */ // Label 2073: @129212
     /* 129212 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(129245), // Rule ID 7434 //
     /* 129217 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129220 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 129223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129227 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129231 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2i64] }:$src)  =>  (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2i64] }:$src, FPR128:{ *:[v2i64] }:$src, 8:{ *:[i32] })
     /* 129231 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129234 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129236 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129238 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129240 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129243 */   GIR_RootConstrainSelectedInstOperands,
     /* 129244 */   // GIR_Coverage, 7434,
     /* 129244 */   GIR_EraseRootFromParent_Done,
     /* 129245 */ // Label 2074: @129245
     /* 129245 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(129316), // Rule ID 7435 //
     /* 129250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129253 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 129256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129260 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129264 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4i32] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4i32] }:$src), 8:{ *:[i32] })
     /* 129264 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 129267 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 129271 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129276 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129280 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 129282 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 129285 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 129289 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129294 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129298 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 129300 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129303 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129305 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129308 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 129311 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129314 */   GIR_RootConstrainSelectedInstOperands,
     /* 129315 */   // GIR_Coverage, 7435,
     /* 129315 */   GIR_EraseRootFromParent_Done,
     /* 129316 */ // Label 2075: @129316
     /* 129316 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(129387), // Rule ID 7436 //
     /* 129321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 129327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129331 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129335 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8i16] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8i16] }:$src), 8:{ *:[i32] })
     /* 129335 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 129338 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 129342 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129347 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129351 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 129353 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 129356 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 129360 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129365 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129369 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 129371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129376 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129379 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 129382 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129385 */   GIR_RootConstrainSelectedInstOperands,
     /* 129386 */   // GIR_Coverage, 7436,
     /* 129386 */   GIR_EraseRootFromParent_Done,
     /* 129387 */ // Label 2076: @129387
     /* 129387 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(129458), // Rule ID 7437 //
     /* 129392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 129398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129402 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129406 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$src), 8:{ *:[i32] })
     /* 129406 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 129409 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 129413 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129418 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129422 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 129424 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 129427 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 129431 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129436 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129440 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 129442 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129445 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129447 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129450 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 129453 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129456 */   GIR_RootConstrainSelectedInstOperands,
     /* 129457 */   // GIR_Coverage, 7437,
     /* 129457 */   GIR_EraseRootFromParent_Done,
     /* 129458 */ // Label 2077: @129458
     /* 129458 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(129491), // Rule ID 7438 //
     /* 129463 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 129469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129477 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v2f64] }:$src)  =>  (EXTv16i8:{ *:[f128] } FPR128:{ *:[v2f64] }:$src, FPR128:{ *:[v2f64] }:$src, 8:{ *:[i32] })
     /* 129477 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129480 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129482 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129484 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129486 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129489 */   GIR_RootConstrainSelectedInstOperands,
     /* 129490 */   // GIR_Coverage, 7438,
     /* 129490 */   GIR_EraseRootFromParent_Done,
     /* 129491 */ // Label 2078: @129491
     /* 129491 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(129562), // Rule ID 7439 //
     /* 129496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129499 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 129502 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129506 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129510 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v4f32] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[v4f32] }:$src), 8:{ *:[i32] })
     /* 129510 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 129513 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 129517 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129522 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129526 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 129528 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 129531 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 129535 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129540 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129544 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 129546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129551 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129554 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 129557 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129560 */   GIR_RootConstrainSelectedInstOperands,
     /* 129561 */   // GIR_Coverage, 7439,
     /* 129561 */   GIR_EraseRootFromParent_Done,
     /* 129562 */ // Label 2079: @129562
     /* 129562 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(129633), // Rule ID 7440 //
     /* 129567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 129573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129577 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 129581 */   // (bitconvert:{ *:[f128] } FPR128:{ *:[v16i8] }:$src)  =>  (EXTv16i8:{ *:[f128] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[v16i8] }:$src), 8:{ *:[i32] })
     /* 129581 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 129584 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 129588 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129593 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129597 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 129599 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 129602 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 129606 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129611 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 129615 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 129617 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 129620 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129622 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129625 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 129628 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 129631 */   GIR_RootConstrainSelectedInstOperands,
     /* 129632 */   // GIR_Coverage, 7440,
     /* 129632 */   GIR_EraseRootFromParent_Done,
     /* 129633 */ // Label 2080: @129633
     /* 129633 */ GIM_Reject,
     /* 129634 */ // Label 1845: @129634
     /* 129634 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(129664), // Rule ID 7292 //
     /* 129639 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129649 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129653 */   // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 129653 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129658 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129663 */   // GIR_Coverage, 7292,
     /* 129663 */   GIR_Done,
     /* 129664 */ // Label 2081: @129664
     /* 129664 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(129694), // Rule ID 7294 //
     /* 129669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129679 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129683 */   // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 129683 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129688 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129693 */   // GIR_Coverage, 7294,
     /* 129693 */   GIR_Done,
     /* 129694 */ // Label 2082: @129694
     /* 129694 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(129744), // Rule ID 7303 //
     /* 129699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129709 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129713 */   // (bitconvert:{ *:[v2i32] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v2i32:{ *:[v2i32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 129713 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 129716 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129720 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129725 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 129729 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 129737 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129739 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129742 */   GIR_RootConstrainSelectedInstOperands,
     /* 129743 */   // GIR_Coverage, 7303,
     /* 129743 */   GIR_EraseRootFromParent_Done,
     /* 129744 */ // Label 2083: @129744
     /* 129744 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(129794), // Rule ID 7305 //
     /* 129749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129752 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129759 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 129763 */   // (bitconvert:{ *:[v2f32] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v2i32:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 129763 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 129766 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129770 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 129775 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 129779 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 129787 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 129789 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 129792 */   GIR_RootConstrainSelectedInstOperands,
     /* 129793 */   // GIR_Coverage, 7305,
     /* 129793 */   GIR_EraseRootFromParent_Done,
     /* 129794 */ // Label 2084: @129794
     /* 129794 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(129826), // Rule ID 7337 //
     /* 129799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129802 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129805 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129809 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129813 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129813 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129816 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129818 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129820 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129825 */   // GIR_Coverage, 7337,
     /* 129825 */   GIR_EraseRootFromParent_Done,
     /* 129826 */ // Label 2085: @129826
     /* 129826 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(129858), // Rule ID 7338 //
     /* 129831 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129834 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 129837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129841 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129845 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129845 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129848 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129850 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129852 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129857 */   // GIR_Coverage, 7338,
     /* 129857 */   GIR_EraseRootFromParent_Done,
     /* 129858 */ // Label 2086: @129858
     /* 129858 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(129890), // Rule ID 7339 //
     /* 129863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129866 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 129869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129873 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129877 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129880 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129882 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129884 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129889 */   // GIR_Coverage, 7339,
     /* 129889 */   GIR_EraseRootFromParent_Done,
     /* 129890 */ // Label 2087: @129890
     /* 129890 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(129922), // Rule ID 7340 //
     /* 129895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129898 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129905 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129909 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129909 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129912 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129914 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129916 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129921 */   // GIR_Coverage, 7340,
     /* 129921 */   GIR_EraseRootFromParent_Done,
     /* 129922 */ // Label 2088: @129922
     /* 129922 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(129954), // Rule ID 7341 //
     /* 129927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129937 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129941 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129941 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129944 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129946 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129948 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129953 */   // GIR_Coverage, 7341,
     /* 129953 */   GIR_EraseRootFromParent_Done,
     /* 129954 */ // Label 2089: @129954
     /* 129954 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(129986), // Rule ID 7342 //
     /* 129959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 129962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 129965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129973 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 129973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 129976 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 129978 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 129980 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 129985 */   // GIR_Coverage, 7342,
     /* 129985 */   GIR_EraseRootFromParent_Done,
     /* 129986 */ // Label 2090: @129986
     /* 129986 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(130012), // Rule ID 7343 //
     /* 129991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 129994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 129997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130001 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130005 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1i64] }:$src)
     /* 130005 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130010 */   GIR_RootConstrainSelectedInstOperands,
     /* 130011 */   // GIR_Coverage, 7343,
     /* 130011 */   GIR_Done,
     /* 130012 */ // Label 2091: @130012
     /* 130012 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(130038), // Rule ID 7344 //
     /* 130017 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130027 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130031 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)  =>  (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4i16] }:$src)
     /* 130031 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 130036 */   GIR_RootConstrainSelectedInstOperands,
     /* 130037 */   // GIR_Coverage, 7344,
     /* 130037 */   GIR_Done,
     /* 130038 */ // Label 2092: @130038
     /* 130038 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(130064), // Rule ID 7345 //
     /* 130043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 130049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130053 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130057 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)  =>  (REV32v8i8:{ *:[v2i32] } FPR64:{ *:[v8i8] }:$src)
     /* 130057 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 130062 */   GIR_RootConstrainSelectedInstOperands,
     /* 130063 */   // GIR_Coverage, 7345,
     /* 130063 */   GIR_Done,
     /* 130064 */ // Label 2093: @130064
     /* 130064 */ GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(130090), // Rule ID 7346 //
     /* 130069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130079 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130083 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[f64] }:$src)
     /* 130083 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130088 */   GIR_RootConstrainSelectedInstOperands,
     /* 130089 */   // GIR_Coverage, 7346,
     /* 130089 */   GIR_Done,
     /* 130090 */ // Label 2094: @130090
     /* 130090 */ GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(130116), // Rule ID 7347 //
     /* 130095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130105 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130109 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v2i32:{ *:[v2i32] } FPR64:{ *:[v1f64] }:$src)
     /* 130109 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130114 */   GIR_RootConstrainSelectedInstOperands,
     /* 130115 */   // GIR_Coverage, 7347,
     /* 130115 */   GIR_Done,
     /* 130116 */ // Label 2095: @130116
     /* 130116 */ GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(130142), // Rule ID 7348 //
     /* 130121 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130124 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130127 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130131 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130135 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)  =>  (REV32v4i16:{ *:[v2i32] } FPR64:{ *:[v4f16] }:$src)
     /* 130135 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 130140 */   GIR_RootConstrainSelectedInstOperands,
     /* 130141 */   // GIR_Coverage, 7348,
     /* 130141 */   GIR_Done,
     /* 130142 */ // Label 2096: @130142
     /* 130142 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(130171), // Rule ID 7349 //
     /* 130147 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 130150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130154 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130158 */   // (bitconvert:{ *:[v2i32] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v2i32] }:$src
     /* 130158 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130161 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130163 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130165 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130170 */   // GIR_Coverage, 7349,
     /* 130170 */   GIR_EraseRootFromParent_Done,
     /* 130171 */ // Label 2097: @130171
     /* 130171 */ GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(130203), // Rule ID 7414 //
     /* 130176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130179 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130186 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130190 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130193 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130195 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130197 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130202 */   // GIR_Coverage, 7414,
     /* 130202 */   GIR_EraseRootFromParent_Done,
     /* 130203 */ // Label 2098: @130203
     /* 130203 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(130235), // Rule ID 7415 //
     /* 130208 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130211 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130214 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130218 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130222 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130225 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130227 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130229 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130234 */   // GIR_Coverage, 7415,
     /* 130234 */   GIR_EraseRootFromParent_Done,
     /* 130235 */ // Label 2099: @130235
     /* 130235 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(130267), // Rule ID 7416 //
     /* 130240 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130243 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 130246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130250 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130254 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130257 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130259 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130261 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130266 */   // GIR_Coverage, 7416,
     /* 130266 */   GIR_EraseRootFromParent_Done,
     /* 130267 */ // Label 2100: @130267
     /* 130267 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(130299), // Rule ID 7417 //
     /* 130272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130275 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130282 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130286 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130286 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130289 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130291 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130293 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130298 */   // GIR_Coverage, 7417,
     /* 130298 */   GIR_EraseRootFromParent_Done,
     /* 130299 */ // Label 2101: @130299
     /* 130299 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(130331), // Rule ID 7418 //
     /* 130304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130307 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130314 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130318 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130318 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130321 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130323 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130325 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130330 */   // GIR_Coverage, 7418,
     /* 130330 */   GIR_EraseRootFromParent_Done,
     /* 130331 */ // Label 2102: @130331
     /* 130331 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(130363), // Rule ID 7419 //
     /* 130336 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130342 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130346 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130350 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130353 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130355 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130357 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130362 */   // GIR_Coverage, 7419,
     /* 130362 */   GIR_EraseRootFromParent_Done,
     /* 130363 */ // Label 2103: @130363
     /* 130363 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(130389), // Rule ID 7420 //
     /* 130368 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130382 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1i64] }:$src)
     /* 130382 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130387 */   GIR_RootConstrainSelectedInstOperands,
     /* 130388 */   // GIR_Coverage, 7420,
     /* 130388 */   GIR_Done,
     /* 130389 */ // Label 2104: @130389
     /* 130389 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(130415), // Rule ID 7421 //
     /* 130394 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130397 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130404 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130408 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)  =>  (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4i16] }:$src)
     /* 130408 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 130413 */   GIR_RootConstrainSelectedInstOperands,
     /* 130414 */   // GIR_Coverage, 7421,
     /* 130414 */   GIR_Done,
     /* 130415 */ // Label 2105: @130415
     /* 130415 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(130441), // Rule ID 7422 //
     /* 130420 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130423 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 130426 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130430 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130434 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)  =>  (REV32v8i8:{ *:[v2f32] } FPR64:{ *:[v8i8] }:$src)
     /* 130434 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 130439 */   GIR_RootConstrainSelectedInstOperands,
     /* 130440 */   // GIR_Coverage, 7422,
     /* 130440 */   GIR_Done,
     /* 130441 */ // Label 2106: @130441
     /* 130441 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(130467), // Rule ID 7423 //
     /* 130446 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130449 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130456 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130460 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[v1f64] }:$src)
     /* 130460 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130465 */   GIR_RootConstrainSelectedInstOperands,
     /* 130466 */   // GIR_Coverage, 7423,
     /* 130466 */   GIR_Done,
     /* 130467 */ // Label 2107: @130467
     /* 130467 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(130493), // Rule ID 7424 //
     /* 130472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 130478 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130482 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130486 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)  =>  (REV64v2i32:{ *:[v2f32] } FPR64:{ *:[f64] }:$src)
     /* 130486 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 130491 */   GIR_RootConstrainSelectedInstOperands,
     /* 130492 */   // GIR_Coverage, 7424,
     /* 130492 */   GIR_Done,
     /* 130493 */ // Label 2108: @130493
     /* 130493 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(130519), // Rule ID 7425 //
     /* 130498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130501 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 130504 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130508 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130512 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)  =>  (REV32v4i16:{ *:[v2f32] } FPR64:{ *:[v4f16] }:$src)
     /* 130512 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 130517 */   GIR_RootConstrainSelectedInstOperands,
     /* 130518 */   // GIR_Coverage, 7425,
     /* 130518 */   GIR_Done,
     /* 130519 */ // Label 2109: @130519
     /* 130519 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(130548), // Rule ID 7426 //
     /* 130524 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 130527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130531 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130535 */   // (bitconvert:{ *:[v2f32] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v2f32] }:$src
     /* 130535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130538 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130540 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130542 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 130547 */   // GIR_Coverage, 7426,
     /* 130547 */   GIR_EraseRootFromParent_Done,
     /* 130548 */ // Label 2110: @130548
     /* 130548 */ GIM_Reject,
     /* 130549 */ // Label 1846: @130549
     /* 130549 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(130581), // Rule ID 7441 //
     /* 130554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130557 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 130560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130564 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130568 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130571 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130573 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130575 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130580 */   // GIR_Coverage, 7441,
     /* 130580 */   GIR_EraseRootFromParent_Done,
     /* 130581 */ // Label 2111: @130581
     /* 130581 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(130613), // Rule ID 7442 //
     /* 130586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130589 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 130592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130596 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130600 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130600 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130603 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130605 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130607 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130612 */   // GIR_Coverage, 7442,
     /* 130612 */   GIR_EraseRootFromParent_Done,
     /* 130613 */ // Label 2112: @130613
     /* 130613 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(130645), // Rule ID 7443 //
     /* 130618 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130621 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 130624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130628 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130632 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130632 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130635 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130637 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130639 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130644 */   // GIR_Coverage, 7443,
     /* 130644 */   GIR_EraseRootFromParent_Done,
     /* 130645 */ // Label 2113: @130645
     /* 130645 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(130677), // Rule ID 7444 //
     /* 130650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 130656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130660 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130664 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130667 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130669 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130671 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130676 */   // GIR_Coverage, 7444,
     /* 130676 */   GIR_EraseRootFromParent_Done,
     /* 130677 */ // Label 2114: @130677
     /* 130677 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(130709), // Rule ID 7445 //
     /* 130682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130685 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 130688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130692 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130696 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130699 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130701 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130703 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130708 */   // GIR_Coverage, 7445,
     /* 130708 */   GIR_EraseRootFromParent_Done,
     /* 130709 */ // Label 2115: @130709
     /* 130709 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(130741), // Rule ID 7446 //
     /* 130714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130717 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 130720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130724 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130728 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130731 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130733 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130735 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130740 */   // GIR_Coverage, 7446,
     /* 130740 */   GIR_EraseRootFromParent_Done,
     /* 130741 */ // Label 2116: @130741
     /* 130741 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(130774), // Rule ID 7447 //
     /* 130746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130749 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 130752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130756 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130760 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v2f64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
     /* 130760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 130763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 130765 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130767 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130769 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 130772 */   GIR_RootConstrainSelectedInstOperands,
     /* 130773 */   // GIR_Coverage, 7447,
     /* 130773 */   GIR_EraseRootFromParent_Done,
     /* 130774 */ // Label 2117: @130774
     /* 130774 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(130800), // Rule ID 7448 //
     /* 130779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 130785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130789 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130793 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)  =>  (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4i32] }:$src)
     /* 130793 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 130798 */   GIR_RootConstrainSelectedInstOperands,
     /* 130799 */   // GIR_Coverage, 7448,
     /* 130799 */   GIR_Done,
     /* 130800 */ // Label 2118: @130800
     /* 130800 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(130826), // Rule ID 7449 //
     /* 130805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 130811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130815 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130819 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)  =>  (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8i16] }:$src)
     /* 130819 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 130824 */   GIR_RootConstrainSelectedInstOperands,
     /* 130825 */   // GIR_Coverage, 7449,
     /* 130825 */   GIR_Done,
     /* 130826 */ // Label 2119: @130826
     /* 130826 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(130852), // Rule ID 7450 //
     /* 130831 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130834 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 130837 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130841 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130845 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)  =>  (REV64v8i16:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src)
     /* 130845 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 130850 */   GIR_RootConstrainSelectedInstOperands,
     /* 130851 */   // GIR_Coverage, 7450,
     /* 130851 */   GIR_Done,
     /* 130852 */ // Label 2120: @130852
     /* 130852 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(130878), // Rule ID 7451 //
     /* 130857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 130863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130871 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)  =>  (REV64v16i8:{ *:[v2f64] } FPR128:{ *:[v16i8] }:$src)
     /* 130871 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 130876 */   GIR_RootConstrainSelectedInstOperands,
     /* 130877 */   // GIR_Coverage, 7451,
     /* 130877 */   GIR_Done,
     /* 130878 */ // Label 2121: @130878
     /* 130878 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(130904), // Rule ID 7452 //
     /* 130883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 130886 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 130889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130893 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130897 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)  =>  (REV64v4i32:{ *:[v2f64] } FPR128:{ *:[v4f32] }:$src)
     /* 130897 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 130902 */   GIR_RootConstrainSelectedInstOperands,
     /* 130903 */   // GIR_Coverage, 7452,
     /* 130903 */   GIR_Done,
     /* 130904 */ // Label 2122: @130904
     /* 130904 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(130933), // Rule ID 7453 //
     /* 130909 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 130912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130916 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130920 */   // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v2f64] }:$src
     /* 130920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130923 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130925 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130927 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130932 */   // GIR_Coverage, 7453,
     /* 130932 */   GIR_EraseRootFromParent_Done,
     /* 130933 */ // Label 2123: @130933
     /* 130933 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(130965), // Rule ID 7467 //
     /* 130938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130941 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 130944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130948 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130952 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 130952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130955 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130957 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130959 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130964 */   // GIR_Coverage, 7467,
     /* 130964 */   GIR_EraseRootFromParent_Done,
     /* 130965 */ // Label 2124: @130965
     /* 130965 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(130997), // Rule ID 7468 //
     /* 130970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 130973 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 130976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130980 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130984 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 130984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 130987 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 130989 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 130991 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 130996 */   // GIR_Coverage, 7468,
     /* 130996 */   GIR_EraseRootFromParent_Done,
     /* 130997 */ // Label 2125: @130997
     /* 130997 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(131029), // Rule ID 7469 //
     /* 131002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131005 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 131008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131012 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131016 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 131016 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131019 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131021 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131023 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131028 */   // GIR_Coverage, 7469,
     /* 131028 */   GIR_EraseRootFromParent_Done,
     /* 131029 */ // Label 2126: @131029
     /* 131029 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(131061), // Rule ID 7470 //
     /* 131034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131037 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 131040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131044 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131048 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 131048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131051 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131053 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131055 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131060 */   // GIR_Coverage, 7470,
     /* 131060 */   GIR_EraseRootFromParent_Done,
     /* 131061 */ // Label 2127: @131061
     /* 131061 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(131093), // Rule ID 7471 //
     /* 131066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 131072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131076 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131080 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 131080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131083 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131085 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131087 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131092 */   // GIR_Coverage, 7471,
     /* 131092 */   GIR_EraseRootFromParent_Done,
     /* 131093 */ // Label 2128: @131093
     /* 131093 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(131125), // Rule ID 7472 //
     /* 131098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 131104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131108 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131112 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 131112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131115 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131117 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131119 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131124 */   // GIR_Coverage, 7472,
     /* 131124 */   GIR_EraseRootFromParent_Done,
     /* 131125 */ // Label 2129: @131125
     /* 131125 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(131158), // Rule ID 7473 //
     /* 131130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131133 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 131136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131140 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131144 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v2i64] } FPR128:{ *:[f128] }:$src, FPR128:{ *:[f128] }:$src, 8:{ *:[i32] })
     /* 131144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 131147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 131149 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131151 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131153 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 131156 */   GIR_RootConstrainSelectedInstOperands,
     /* 131157 */   // GIR_Coverage, 7473,
     /* 131157 */   GIR_EraseRootFromParent_Done,
     /* 131158 */ // Label 2130: @131158
     /* 131158 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(131184), // Rule ID 7474 //
     /* 131163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131166 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 131169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131173 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131177 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)  =>  (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4i32] }:$src)
     /* 131177 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 131182 */   GIR_RootConstrainSelectedInstOperands,
     /* 131183 */   // GIR_Coverage, 7474,
     /* 131183 */   GIR_Done,
     /* 131184 */ // Label 2131: @131184
     /* 131184 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(131210), // Rule ID 7475 //
     /* 131189 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 131195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131199 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131203 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)  =>  (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8i16] }:$src)
     /* 131203 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 131208 */   GIR_RootConstrainSelectedInstOperands,
     /* 131209 */   // GIR_Coverage, 7475,
     /* 131209 */   GIR_Done,
     /* 131210 */ // Label 2132: @131210
     /* 131210 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(131236), // Rule ID 7476 //
     /* 131215 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131218 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 131221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131225 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131229 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)  =>  (REV64v16i8:{ *:[v2i64] } FPR128:{ *:[v16i8] }:$src)
     /* 131229 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 131234 */   GIR_RootConstrainSelectedInstOperands,
     /* 131235 */   // GIR_Coverage, 7476,
     /* 131235 */   GIR_Done,
     /* 131236 */ // Label 2133: @131236
     /* 131236 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(131262), // Rule ID 7477 //
     /* 131241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131244 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 131247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131251 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131255 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)  =>  (REV64v4i32:{ *:[v2i64] } FPR128:{ *:[v4f32] }:$src)
     /* 131255 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 131260 */   GIR_RootConstrainSelectedInstOperands,
     /* 131261 */   // GIR_Coverage, 7477,
     /* 131261 */   GIR_Done,
     /* 131262 */ // Label 2134: @131262
     /* 131262 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(131288), // Rule ID 7478 //
     /* 131267 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131270 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 131273 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131277 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131281 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)  =>  (REV64v8i16:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src)
     /* 131281 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 131286 */   GIR_RootConstrainSelectedInstOperands,
     /* 131287 */   // GIR_Coverage, 7478,
     /* 131287 */   GIR_Done,
     /* 131288 */ // Label 2135: @131288
     /* 131288 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(131317), // Rule ID 7479 //
     /* 131293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 131296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131300 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131304 */   // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v2i64] }:$src
     /* 131304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131307 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131309 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131311 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 131316 */   // GIR_Coverage, 7479,
     /* 131316 */   GIR_EraseRootFromParent_Done,
     /* 131317 */ // Label 2136: @131317
     /* 131317 */ GIM_Reject,
     /* 131318 */ // Label 1847: @131318
     /* 131318 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(131348), // Rule ID 7291 //
     /* 131323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131333 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 131337 */   // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 131337 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131342 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131347 */   // GIR_Coverage, 7291,
     /* 131347 */   GIR_Done,
     /* 131348 */ // Label 2137: @131348
     /* 131348 */ GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(131378), // Rule ID 7293 //
     /* 131353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131363 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 131367 */   // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 131367 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131372 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131377 */   // GIR_Coverage, 7293,
     /* 131377 */   GIR_Done,
     /* 131378 */ // Label 2138: @131378
     /* 131378 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(131428), // Rule ID 7302 //
     /* 131383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131386 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131393 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 131397 */   // (bitconvert:{ *:[v4i16] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v4i16:{ *:[v4i16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 131397 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 131400 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131404 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131409 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 131413 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131418 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 131421 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 131423 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131426 */   GIR_RootConstrainSelectedInstOperands,
     /* 131427 */   // GIR_Coverage, 7302,
     /* 131427 */   GIR_EraseRootFromParent_Done,
     /* 131428 */ // Label 2139: @131428
     /* 131428 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(131478), // Rule ID 7304 //
     /* 131433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131443 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 131447 */   // (bitconvert:{ *:[v4f16] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v4i16:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 131447 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 131450 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131454 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 131459 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 131463 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 131471 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 131473 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 131476 */   GIR_RootConstrainSelectedInstOperands,
     /* 131477 */   // GIR_Coverage, 7304,
     /* 131477 */   GIR_EraseRootFromParent_Done,
     /* 131478 */ // Label 2140: @131478
     /* 131478 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(131510), // Rule ID 7350 //
     /* 131483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131493 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131497 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131500 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131502 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131504 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131509 */   // GIR_Coverage, 7350,
     /* 131509 */   GIR_EraseRootFromParent_Done,
     /* 131510 */ // Label 2141: @131510
     /* 131510 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(131542), // Rule ID 7351 //
     /* 131515 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131518 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131525 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131529 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131529 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131532 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131534 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131536 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131541 */   // GIR_Coverage, 7351,
     /* 131541 */   GIR_EraseRootFromParent_Done,
     /* 131542 */ // Label 2142: @131542
     /* 131542 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(131574), // Rule ID 7352 //
     /* 131547 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131550 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 131553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131557 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131561 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131564 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131566 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131568 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131573 */   // GIR_Coverage, 7352,
     /* 131573 */   GIR_EraseRootFromParent_Done,
     /* 131574 */ // Label 2143: @131574
     /* 131574 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(131606), // Rule ID 7353 //
     /* 131579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131589 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131593 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131596 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131598 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131600 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131605 */   // GIR_Coverage, 7353,
     /* 131605 */   GIR_EraseRootFromParent_Done,
     /* 131606 */ // Label 2144: @131606
     /* 131606 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(131638), // Rule ID 7354 //
     /* 131611 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131614 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131617 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131621 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131625 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131628 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131630 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131632 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131637 */   // GIR_Coverage, 7354,
     /* 131637 */   GIR_EraseRootFromParent_Done,
     /* 131638 */ // Label 2145: @131638
     /* 131638 */ GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(131670), // Rule ID 7355 //
     /* 131643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131646 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131653 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131657 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131660 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131662 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131664 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131669 */   // GIR_Coverage, 7355,
     /* 131669 */   GIR_EraseRootFromParent_Done,
     /* 131670 */ // Label 2146: @131670
     /* 131670 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(131696), // Rule ID 7356 //
     /* 131675 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131678 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131685 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131689 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1i64] }:$src)
     /* 131689 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 131694 */   GIR_RootConstrainSelectedInstOperands,
     /* 131695 */   // GIR_Coverage, 7356,
     /* 131695 */   GIR_Done,
     /* 131696 */ // Label 2147: @131696
     /* 131696 */ GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(131722), // Rule ID 7357 //
     /* 131701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131704 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131707 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131711 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131715 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2i32] }:$src)
     /* 131715 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 131720 */   GIR_RootConstrainSelectedInstOperands,
     /* 131721 */   // GIR_Coverage, 7357,
     /* 131721 */   GIR_Done,
     /* 131722 */ // Label 2148: @131722
     /* 131722 */ GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(131748), // Rule ID 7358 //
     /* 131727 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131730 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 131733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131737 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131741 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)  =>  (REV16v8i8:{ *:[v4i16] } FPR64:{ *:[v8i8] }:$src)
     /* 131741 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 131746 */   GIR_RootConstrainSelectedInstOperands,
     /* 131747 */   // GIR_Coverage, 7358,
     /* 131747 */   GIR_Done,
     /* 131748 */ // Label 2149: @131748
     /* 131748 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(131774), // Rule ID 7359 //
     /* 131753 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131756 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131763 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131767 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[f64] }:$src)
     /* 131767 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 131772 */   GIR_RootConstrainSelectedInstOperands,
     /* 131773 */   // GIR_Coverage, 7359,
     /* 131773 */   GIR_Done,
     /* 131774 */ // Label 2150: @131774
     /* 131774 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(131800), // Rule ID 7360 //
     /* 131779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131789 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131793 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v4i16:{ *:[v4i16] } FPR64:{ *:[v2f32] }:$src)
     /* 131793 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 131798 */   GIR_RootConstrainSelectedInstOperands,
     /* 131799 */   // GIR_Coverage, 7360,
     /* 131799 */   GIR_Done,
     /* 131800 */ // Label 2151: @131800
     /* 131800 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(131826), // Rule ID 7361 //
     /* 131805 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 131808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131815 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131819 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v4i16:{ *:[v4i16] } FPR64:{ *:[v1f64] }:$src)
     /* 131819 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 131824 */   GIR_RootConstrainSelectedInstOperands,
     /* 131825 */   // GIR_Coverage, 7361,
     /* 131825 */   GIR_Done,
     /* 131826 */ // Label 2152: @131826
     /* 131826 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(131855), // Rule ID 7362 //
     /* 131831 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 131834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131838 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131842 */   // (bitconvert:{ *:[v4i16] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v4i16] }:$src
     /* 131842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131845 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131847 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131849 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131854 */   // GIR_Coverage, 7362,
     /* 131854 */   GIR_EraseRootFromParent_Done,
     /* 131855 */ // Label 2153: @131855
     /* 131855 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(131887), // Rule ID 7363 //
     /* 131860 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131863 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131870 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131874 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 131874 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131877 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131879 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131881 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131886 */   // GIR_Coverage, 7363,
     /* 131886 */   GIR_EraseRootFromParent_Done,
     /* 131887 */ // Label 2154: @131887
     /* 131887 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(131919), // Rule ID 7364 //
     /* 131892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131895 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131902 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131906 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 131906 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131909 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131911 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131918 */   // GIR_Coverage, 7364,
     /* 131918 */   GIR_EraseRootFromParent_Done,
     /* 131919 */ // Label 2155: @131919
     /* 131919 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(131951), // Rule ID 7365 //
     /* 131924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131927 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 131930 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131934 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131938 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 131938 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131941 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131943 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131945 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131950 */   // GIR_Coverage, 7365,
     /* 131950 */   GIR_EraseRootFromParent_Done,
     /* 131951 */ // Label 2156: @131951
     /* 131951 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(131983), // Rule ID 7366 //
     /* 131956 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131959 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 131962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131966 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131970 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 131970 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 131973 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 131975 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 131977 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131982 */   // GIR_Coverage, 7366,
     /* 131982 */   GIR_EraseRootFromParent_Done,
     /* 131983 */ // Label 2157: @131983
     /* 131983 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(132015), // Rule ID 7367 //
     /* 131988 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 131991 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 131994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 131998 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132002 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 132002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132005 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132007 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132009 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132014 */   // GIR_Coverage, 7367,
     /* 132014 */   GIR_EraseRootFromParent_Done,
     /* 132015 */ // Label 2158: @132015
     /* 132015 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(132047), // Rule ID 7368 //
     /* 132020 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132023 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 132026 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132030 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132034 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 132034 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132037 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132039 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132041 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132046 */   // GIR_Coverage, 7368,
     /* 132046 */   GIR_EraseRootFromParent_Done,
     /* 132047 */ // Label 2159: @132047
     /* 132047 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(132073), // Rule ID 7369 //
     /* 132052 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132055 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 132058 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132062 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132066 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1i64] }:$src)
     /* 132066 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 132071 */   GIR_RootConstrainSelectedInstOperands,
     /* 132072 */   // GIR_Coverage, 7369,
     /* 132072 */   GIR_Done,
     /* 132073 */ // Label 2160: @132073
     /* 132073 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(132099), // Rule ID 7370 //
     /* 132078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 132084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132088 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132092 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2i32] }:$src)
     /* 132092 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 132097 */   GIR_RootConstrainSelectedInstOperands,
     /* 132098 */   // GIR_Coverage, 7370,
     /* 132098 */   GIR_Done,
     /* 132099 */ // Label 2161: @132099
     /* 132099 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(132125), // Rule ID 7371 //
     /* 132104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132107 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 132110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132114 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132118 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)  =>  (REV16v8i8:{ *:[v4f16] } FPR64:{ *:[v8i8] }:$src)
     /* 132118 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 132123 */   GIR_RootConstrainSelectedInstOperands,
     /* 132124 */   // GIR_Coverage, 7371,
     /* 132124 */   GIR_Done,
     /* 132125 */ // Label 2162: @132125
     /* 132125 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(132151), // Rule ID 7372 //
     /* 132130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132133 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 132136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132140 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132144 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[f64] }:$src)
     /* 132144 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 132149 */   GIR_RootConstrainSelectedInstOperands,
     /* 132150 */   // GIR_Coverage, 7372,
     /* 132150 */   GIR_Done,
     /* 132151 */ // Label 2163: @132151
     /* 132151 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(132177), // Rule ID 7373 //
     /* 132156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132159 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 132162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132166 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132170 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v4i16:{ *:[v4f16] } FPR64:{ *:[v2f32] }:$src)
     /* 132170 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 132175 */   GIR_RootConstrainSelectedInstOperands,
     /* 132176 */   // GIR_Coverage, 7373,
     /* 132176 */   GIR_Done,
     /* 132177 */ // Label 2164: @132177
     /* 132177 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(132203), // Rule ID 7374 //
     /* 132182 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132185 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 132188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132192 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132196 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v4i16:{ *:[v4f16] } FPR64:{ *:[v1f64] }:$src)
     /* 132196 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 132201 */   GIR_RootConstrainSelectedInstOperands,
     /* 132202 */   // GIR_Coverage, 7374,
     /* 132202 */   GIR_Done,
     /* 132203 */ // Label 2165: @132203
     /* 132203 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(132232), // Rule ID 7375 //
     /* 132208 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 132211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132215 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132219 */   // (bitconvert:{ *:[v4f16] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v4f16] }:$src
     /* 132219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132222 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132224 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132226 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 132231 */   // GIR_Coverage, 7375,
     /* 132231 */   GIR_EraseRootFromParent_Done,
     /* 132232 */ // Label 2166: @132232
     /* 132232 */ GIM_Reject,
     /* 132233 */ // Label 1848: @132233
     /* 132233 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(132265), // Rule ID 7454 //
     /* 132238 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132241 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 132244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132248 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132252 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132252 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132255 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132257 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132259 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132264 */   // GIR_Coverage, 7454,
     /* 132264 */   GIR_EraseRootFromParent_Done,
     /* 132265 */ // Label 2167: @132265
     /* 132265 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(132297), // Rule ID 7455 //
     /* 132270 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132273 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132276 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132280 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132284 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132287 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132289 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132291 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132296 */   // GIR_Coverage, 7455,
     /* 132296 */   GIR_EraseRootFromParent_Done,
     /* 132297 */ // Label 2168: @132297
     /* 132297 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(132329), // Rule ID 7456 //
     /* 132302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132305 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132312 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132316 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132319 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132321 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132323 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132328 */   // GIR_Coverage, 7456,
     /* 132328 */   GIR_EraseRootFromParent_Done,
     /* 132329 */ // Label 2169: @132329
     /* 132329 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(132361), // Rule ID 7457 //
     /* 132334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132337 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 132340 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132344 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132348 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132348 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132351 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132353 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132355 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132360 */   // GIR_Coverage, 7457,
     /* 132360 */   GIR_EraseRootFromParent_Done,
     /* 132361 */ // Label 2170: @132361
     /* 132361 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(132393), // Rule ID 7458 //
     /* 132366 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132369 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132372 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132376 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132380 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132380 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132383 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132385 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132387 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132392 */   // GIR_Coverage, 7458,
     /* 132392 */   GIR_EraseRootFromParent_Done,
     /* 132393 */ // Label 2171: @132393
     /* 132393 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(132425), // Rule ID 7459 //
     /* 132398 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132408 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132412 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132415 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132417 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132424 */   // GIR_Coverage, 7459,
     /* 132424 */   GIR_EraseRootFromParent_Done,
     /* 132425 */ // Label 2172: @132425
     /* 132425 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(132496), // Rule ID 7460 //
     /* 132430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132433 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 132436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132440 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132444 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v4f32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 132444 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 132447 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132451 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132456 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 132460 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 132462 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 132465 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132469 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132474 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 132478 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132480 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 132483 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 132485 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132488 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 132491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 132494 */   GIR_RootConstrainSelectedInstOperands,
     /* 132495 */   // GIR_Coverage, 7460,
     /* 132495 */   GIR_EraseRootFromParent_Done,
     /* 132496 */ // Label 2173: @132496
     /* 132496 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(132522), // Rule ID 7461 //
     /* 132501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132504 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132511 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132515 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)  =>  (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8i16] }:$src)
     /* 132515 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 132520 */   GIR_RootConstrainSelectedInstOperands,
     /* 132521 */   // GIR_Coverage, 7461,
     /* 132521 */   GIR_Done,
     /* 132522 */ // Label 2174: @132522
     /* 132522 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(132548), // Rule ID 7462 //
     /* 132527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132530 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132537 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132541 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)  =>  (REV32v8i16:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src)
     /* 132541 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 132546 */   GIR_RootConstrainSelectedInstOperands,
     /* 132547 */   // GIR_Coverage, 7462,
     /* 132547 */   GIR_Done,
     /* 132548 */ // Label 2175: @132548
     /* 132548 */ GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(132574), // Rule ID 7463 //
     /* 132553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132556 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 132559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132563 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132567 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)  =>  (REV32v16i8:{ *:[v4f32] } FPR128:{ *:[v16i8] }:$src)
     /* 132567 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 132572 */   GIR_RootConstrainSelectedInstOperands,
     /* 132573 */   // GIR_Coverage, 7463,
     /* 132573 */   GIR_Done,
     /* 132574 */ // Label 2176: @132574
     /* 132574 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(132600), // Rule ID 7464 //
     /* 132579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132589 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132593 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2i64] }:$src)
     /* 132593 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132598 */   GIR_RootConstrainSelectedInstOperands,
     /* 132599 */   // GIR_Coverage, 7464,
     /* 132599 */   GIR_Done,
     /* 132600 */ // Label 2177: @132600
     /* 132600 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(132626), // Rule ID 7465 //
     /* 132605 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132608 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132611 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132615 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132619 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v4i32:{ *:[v4f32] } FPR128:{ *:[v2f64] }:$src)
     /* 132619 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132624 */   GIR_RootConstrainSelectedInstOperands,
     /* 132625 */   // GIR_Coverage, 7465,
     /* 132625 */   GIR_Done,
     /* 132626 */ // Label 2178: @132626
     /* 132626 */ GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(132655), // Rule ID 7466 //
     /* 132631 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 132634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132638 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132642 */   // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v4f32] }:$src
     /* 132642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132645 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132647 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132649 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132654 */   // GIR_Coverage, 7466,
     /* 132654 */   GIR_EraseRootFromParent_Done,
     /* 132655 */ // Label 2179: @132655
     /* 132655 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(132687), // Rule ID 7480 //
     /* 132660 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132663 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 132666 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132670 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132674 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132674 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132677 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132679 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132681 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132686 */   // GIR_Coverage, 7480,
     /* 132686 */   GIR_EraseRootFromParent_Done,
     /* 132687 */ // Label 2180: @132687
     /* 132687 */ GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(132719), // Rule ID 7481 //
     /* 132692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132702 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132706 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132706 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132709 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132711 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132713 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132718 */   // GIR_Coverage, 7481,
     /* 132718 */   GIR_EraseRootFromParent_Done,
     /* 132719 */ // Label 2181: @132719
     /* 132719 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(132751), // Rule ID 7482 //
     /* 132724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132734 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132738 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132738 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132741 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132743 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132745 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132750 */   // GIR_Coverage, 7482,
     /* 132750 */   GIR_EraseRootFromParent_Done,
     /* 132751 */ // Label 2182: @132751
     /* 132751 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(132783), // Rule ID 7483 //
     /* 132756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132759 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 132762 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132766 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132770 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132773 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132775 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132777 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132782 */   // GIR_Coverage, 7483,
     /* 132782 */   GIR_EraseRootFromParent_Done,
     /* 132783 */ // Label 2183: @132783
     /* 132783 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(132815), // Rule ID 7484 //
     /* 132788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132791 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132798 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132802 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132802 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132805 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132807 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132809 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132814 */   // GIR_Coverage, 7484,
     /* 132814 */   GIR_EraseRootFromParent_Done,
     /* 132815 */ // Label 2184: @132815
     /* 132815 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(132847), // Rule ID 7485 //
     /* 132820 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 132823 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132826 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132830 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132834 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 132834 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 132837 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 132839 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 132841 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132846 */   // GIR_Coverage, 7485,
     /* 132846 */   GIR_EraseRootFromParent_Done,
     /* 132847 */ // Label 2185: @132847
     /* 132847 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(132918), // Rule ID 7486 //
     /* 132852 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 132858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132862 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132866 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v4i32] } (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v4i32:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 132866 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 132869 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132873 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132878 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 132882 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 132884 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 132887 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132891 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 132896 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 132900 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 132902 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 132905 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 132907 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 132910 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 132913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 132916 */   GIR_RootConstrainSelectedInstOperands,
     /* 132917 */   // GIR_Coverage, 7486,
     /* 132917 */   GIR_EraseRootFromParent_Done,
     /* 132918 */ // Label 2186: @132918
     /* 132918 */ GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(132944), // Rule ID 7487 //
     /* 132923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 132929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132933 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132937 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2i64] }:$src)
     /* 132937 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 132942 */   GIR_RootConstrainSelectedInstOperands,
     /* 132943 */   // GIR_Coverage, 7487,
     /* 132943 */   GIR_Done,
     /* 132944 */ // Label 2187: @132944
     /* 132944 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(132970), // Rule ID 7488 //
     /* 132949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132952 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 132955 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132959 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132963 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)  =>  (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8i16] }:$src)
     /* 132963 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 132968 */   GIR_RootConstrainSelectedInstOperands,
     /* 132969 */   // GIR_Coverage, 7488,
     /* 132969 */   GIR_Done,
     /* 132970 */ // Label 2188: @132970
     /* 132970 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(132996), // Rule ID 7489 //
     /* 132975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 132978 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 132981 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132985 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 132989 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)  =>  (REV32v16i8:{ *:[v4i32] } FPR128:{ *:[v16i8] }:$src)
     /* 132989 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 132994 */   GIR_RootConstrainSelectedInstOperands,
     /* 132995 */   // GIR_Coverage, 7489,
     /* 132995 */   GIR_Done,
     /* 132996 */ // Label 2189: @132996
     /* 132996 */ GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(133022), // Rule ID 7490 //
     /* 133001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 133007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133011 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133015 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v4i32:{ *:[v4i32] } FPR128:{ *:[v2f64] }:$src)
     /* 133015 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 133020 */   GIR_RootConstrainSelectedInstOperands,
     /* 133021 */   // GIR_Coverage, 7490,
     /* 133021 */   GIR_Done,
     /* 133022 */ // Label 2190: @133022
     /* 133022 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(133048), // Rule ID 7491 //
     /* 133027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133030 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 133033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133037 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133041 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)  =>  (REV32v8i16:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src)
     /* 133041 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 133046 */   GIR_RootConstrainSelectedInstOperands,
     /* 133047 */   // GIR_Coverage, 7491,
     /* 133047 */   GIR_Done,
     /* 133048 */ // Label 2191: @133048
     /* 133048 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(133077), // Rule ID 7492 //
     /* 133053 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 133056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133060 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133064 */   // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v4i32] }:$src
     /* 133064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133067 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133069 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133071 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133076 */   // GIR_Coverage, 7492,
     /* 133076 */   GIR_EraseRootFromParent_Done,
     /* 133077 */ // Label 2192: @133077
     /* 133077 */ GIM_Reject,
     /* 133078 */ // Label 1849: @133078
     /* 133078 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(133152), // Rule ID 6269 //
     /* 133083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133090 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 133094 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 133098 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 133102 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 133107 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 133109 */   // (bitconvert:{ *:[v8i8] } (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn))  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (FMOVWSr:{ *:[f32] } GPR32:{ *:[i32] }:$Rn), ssub:{ *:[i32] })
     /* 133109 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 133112 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FMOVWSr),
     /* 133116 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133121 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 133125 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 133127 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 133130 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 133132 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 133135 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133138 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 133141 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133146 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 133151 */   // GIR_Coverage, 6269,
     /* 133151 */   GIR_EraseRootFromParent_Done,
     /* 133152 */ // Label 2193: @133152
     /* 133152 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(133182), // Rule ID 7290 //
     /* 133157 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133160 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133167 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 133171 */   // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn)  =>  (COPY_TO_REGCLASS:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 133171 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133176 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133181 */   // GIR_Coverage, 7290,
     /* 133181 */   GIR_Done,
     /* 133182 */ // Label 2194: @133182
     /* 133182 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(133232), // Rule ID 7301 //
     /* 133187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133190 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133193 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133197 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 133201 */   // (bitconvert:{ *:[v8i8] } GPR64:{ *:[i64] }:$Xn)  =>  (REV64v8i8:{ *:[v8i8] } (COPY_TO_REGCLASS:{ *:[i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] }))
     /* 133201 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 133204 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133208 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133213 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Xn
     /* 133217 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133222 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 133225 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 133227 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133230 */   GIR_RootConstrainSelectedInstOperands,
     /* 133231 */   // GIR_Coverage, 7301,
     /* 133231 */   GIR_EraseRootFromParent_Done,
     /* 133232 */ // Label 2195: @133232
     /* 133232 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(133264), // Rule ID 7376 //
     /* 133237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133240 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133247 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133251 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133251 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133254 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133256 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133258 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133263 */   // GIR_Coverage, 7376,
     /* 133263 */   GIR_EraseRootFromParent_Done,
     /* 133264 */ // Label 2196: @133264
     /* 133264 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(133296), // Rule ID 7377 //
     /* 133269 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133272 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 133275 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133279 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133283 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133283 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133286 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133288 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133290 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133295 */   // GIR_Coverage, 7377,
     /* 133295 */   GIR_EraseRootFromParent_Done,
     /* 133296 */ // Label 2197: @133296
     /* 133296 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(133328), // Rule ID 7378 //
     /* 133301 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133304 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133307 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133311 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133315 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133315 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133318 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133320 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133322 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133327 */   // GIR_Coverage, 7378,
     /* 133327 */   GIR_EraseRootFromParent_Done,
     /* 133328 */ // Label 2198: @133328
     /* 133328 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(133360), // Rule ID 7379 //
     /* 133333 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133336 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133343 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133347 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133350 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133352 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133354 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133359 */   // GIR_Coverage, 7379,
     /* 133359 */   GIR_EraseRootFromParent_Done,
     /* 133360 */ // Label 2199: @133360
     /* 133360 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(133392), // Rule ID 7380 //
     /* 133365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 133371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133375 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133379 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133379 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133382 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133384 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133386 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133391 */   // GIR_Coverage, 7380,
     /* 133391 */   GIR_EraseRootFromParent_Done,
     /* 133392 */ // Label 2200: @133392
     /* 133392 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(133424), // Rule ID 7381 //
     /* 133397 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133400 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133403 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133407 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133411 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133414 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133416 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133418 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133423 */   // GIR_Coverage, 7381,
     /* 133423 */   GIR_EraseRootFromParent_Done,
     /* 133424 */ // Label 2201: @133424
     /* 133424 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(133456), // Rule ID 7382 //
     /* 133429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133432 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133439 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133443 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)  =>  FPR64:{ *:[v8i8] }:$src
     /* 133443 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133446 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133448 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133450 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133455 */   // GIR_Coverage, 7382,
     /* 133455 */   GIR_EraseRootFromParent_Done,
     /* 133456 */ // Label 2202: @133456
     /* 133456 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(133482), // Rule ID 7383 //
     /* 133461 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133464 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133467 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133471 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133475 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1i64] }:$src)
     /* 133475 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 133480 */   GIR_RootConstrainSelectedInstOperands,
     /* 133481 */   // GIR_Coverage, 7383,
     /* 133481 */   GIR_Done,
     /* 133482 */ // Label 2203: @133482
     /* 133482 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(133508), // Rule ID 7384 //
     /* 133487 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133490 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 133493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133497 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133501 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)  =>  (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2i32] }:$src)
     /* 133501 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 133506 */   GIR_RootConstrainSelectedInstOperands,
     /* 133507 */   // GIR_Coverage, 7384,
     /* 133507 */   GIR_Done,
     /* 133508 */ // Label 2204: @133508
     /* 133508 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(133534), // Rule ID 7385 //
     /* 133513 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133516 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133523 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133527 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)  =>  (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4i16] }:$src)
     /* 133527 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 133532 */   GIR_RootConstrainSelectedInstOperands,
     /* 133533 */   // GIR_Coverage, 7385,
     /* 133533 */   GIR_Done,
     /* 133534 */ // Label 2205: @133534
     /* 133534 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(133560), // Rule ID 7386 //
     /* 133539 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133542 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133549 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133553 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[f64] }:$src)
     /* 133553 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 133558 */   GIR_RootConstrainSelectedInstOperands,
     /* 133559 */   // GIR_Coverage, 7386,
     /* 133559 */   GIR_Done,
     /* 133560 */ // Label 2206: @133560
     /* 133560 */ GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(133586), // Rule ID 7387 //
     /* 133565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 133571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133575 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133579 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)  =>  (REV32v8i8:{ *:[v8i8] } FPR64:{ *:[v2f32] }:$src)
     /* 133579 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 133584 */   GIR_RootConstrainSelectedInstOperands,
     /* 133585 */   // GIR_Coverage, 7387,
     /* 133585 */   GIR_Done,
     /* 133586 */ // Label 2207: @133586
     /* 133586 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(133612), // Rule ID 7388 //
     /* 133591 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133594 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 133597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133601 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133605 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)  =>  (REV64v8i8:{ *:[v8i8] } FPR64:{ *:[v1f64] }:$src)
     /* 133605 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 133610 */   GIR_RootConstrainSelectedInstOperands,
     /* 133611 */   // GIR_Coverage, 7388,
     /* 133611 */   GIR_Done,
     /* 133612 */ // Label 2208: @133612
     /* 133612 */ GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(133638), // Rule ID 7389 //
     /* 133617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133620 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 133623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133627 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 133631 */   // (bitconvert:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)  =>  (REV16v8i8:{ *:[v8i8] } FPR64:{ *:[v4f16] }:$src)
     /* 133631 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 133636 */   GIR_RootConstrainSelectedInstOperands,
     /* 133637 */   // GIR_Coverage, 7389,
     /* 133637 */   GIR_Done,
     /* 133638 */ // Label 2209: @133638
     /* 133638 */ GIM_Reject,
     /* 133639 */ // Label 1850: @133639
     /* 133639 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(133671), // Rule ID 7493 //
     /* 133644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133647 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 133650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133654 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133658 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133661 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133663 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133670 */   // GIR_Coverage, 7493,
     /* 133670 */   GIR_EraseRootFromParent_Done,
     /* 133671 */ // Label 2210: @133671
     /* 133671 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(133703), // Rule ID 7494 //
     /* 133676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 133682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133686 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133690 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133690 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133693 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133695 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133697 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133702 */   // GIR_Coverage, 7494,
     /* 133702 */   GIR_EraseRootFromParent_Done,
     /* 133703 */ // Label 2211: @133703
     /* 133703 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(133735), // Rule ID 7495 //
     /* 133708 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 133714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133718 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133722 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133725 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133727 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133729 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133734 */   // GIR_Coverage, 7495,
     /* 133734 */   GIR_EraseRootFromParent_Done,
     /* 133735 */ // Label 2212: @133735
     /* 133735 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(133767), // Rule ID 7496 //
     /* 133740 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 133746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133754 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133757 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133759 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133761 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133766 */   // GIR_Coverage, 7496,
     /* 133766 */   GIR_EraseRootFromParent_Done,
     /* 133767 */ // Label 2213: @133767
     /* 133767 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(133799), // Rule ID 7497 //
     /* 133772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 133778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133782 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133786 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133786 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133789 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133791 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133793 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133798 */   // GIR_Coverage, 7497,
     /* 133798 */   GIR_EraseRootFromParent_Done,
     /* 133799 */ // Label 2214: @133799
     /* 133799 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(133831), // Rule ID 7498 //
     /* 133804 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 133807 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 133810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133814 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133818 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 133818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 133821 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 133823 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 133825 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133830 */   // GIR_Coverage, 7498,
     /* 133830 */   GIR_EraseRootFromParent_Done,
     /* 133831 */ // Label 2215: @133831
     /* 133831 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(133902), // Rule ID 7499 //
     /* 133836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133839 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 133842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133846 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133850 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v8i16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 133850 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 133853 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 133857 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133862 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 133866 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 133868 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 133871 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 133875 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 133880 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 133884 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 133886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 133889 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 133891 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 133894 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 133897 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 133900 */   GIR_RootConstrainSelectedInstOperands,
     /* 133901 */   // GIR_Coverage, 7499,
     /* 133901 */   GIR_EraseRootFromParent_Done,
     /* 133902 */ // Label 2216: @133902
     /* 133902 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(133928), // Rule ID 7500 //
     /* 133907 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133910 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 133913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133917 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133921 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2i64] }:$src)
     /* 133921 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 133926 */   GIR_RootConstrainSelectedInstOperands,
     /* 133927 */   // GIR_Coverage, 7500,
     /* 133927 */   GIR_Done,
     /* 133928 */ // Label 2217: @133928
     /* 133928 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(133954), // Rule ID 7501 //
     /* 133933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133936 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 133939 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133943 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133947 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4i32] }:$src)
     /* 133947 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 133952 */   GIR_RootConstrainSelectedInstOperands,
     /* 133953 */   // GIR_Coverage, 7501,
     /* 133953 */   GIR_Done,
     /* 133954 */ // Label 2218: @133954
     /* 133954 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(133980), // Rule ID 7502 //
     /* 133959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 133965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133973 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)  =>  (REV16v16i8:{ *:[v8i16] } FPR128:{ *:[v16i8] }:$src)
     /* 133973 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 133978 */   GIR_RootConstrainSelectedInstOperands,
     /* 133979 */   // GIR_Coverage, 7502,
     /* 133979 */   GIR_Done,
     /* 133980 */ // Label 2219: @133980
     /* 133980 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(134006), // Rule ID 7503 //
     /* 133985 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 133988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 133991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133995 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 133999 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v8i16:{ *:[v8i16] } FPR128:{ *:[v2f64] }:$src)
     /* 133999 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 134004 */   GIR_RootConstrainSelectedInstOperands,
     /* 134005 */   // GIR_Coverage, 7503,
     /* 134005 */   GIR_Done,
     /* 134006 */ // Label 2220: @134006
     /* 134006 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(134032), // Rule ID 7504 //
     /* 134011 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134014 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134021 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134025 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v8i16:{ *:[v8i16] } FPR128:{ *:[v4f32] }:$src)
     /* 134025 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 134030 */   GIR_RootConstrainSelectedInstOperands,
     /* 134031 */   // GIR_Coverage, 7504,
     /* 134031 */   GIR_Done,
     /* 134032 */ // Label 2221: @134032
     /* 134032 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(134061), // Rule ID 7505 //
     /* 134037 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134040 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134044 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134048 */   // (bitconvert:{ *:[v8i16] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v8i16] }:$src
     /* 134048 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134051 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134053 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134055 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134060 */   // GIR_Coverage, 7505,
     /* 134060 */   GIR_EraseRootFromParent_Done,
     /* 134061 */ // Label 2222: @134061
     /* 134061 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(134093), // Rule ID 7506 //
     /* 134066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 134072 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134076 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134080 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134083 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134085 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134087 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134092 */   // GIR_Coverage, 7506,
     /* 134092 */   GIR_EraseRootFromParent_Done,
     /* 134093 */ // Label 2223: @134093
     /* 134093 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(134125), // Rule ID 7507 //
     /* 134098 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134104 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134108 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134112 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134115 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134117 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134119 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134124 */   // GIR_Coverage, 7507,
     /* 134124 */   GIR_EraseRootFromParent_Done,
     /* 134125 */ // Label 2224: @134125
     /* 134125 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(134157), // Rule ID 7508 //
     /* 134130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134133 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134140 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134144 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134147 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134149 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134151 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134156 */   // GIR_Coverage, 7508,
     /* 134156 */   GIR_EraseRootFromParent_Done,
     /* 134157 */ // Label 2225: @134157
     /* 134157 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(134189), // Rule ID 7509 //
     /* 134162 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134165 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 134168 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134172 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134176 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134176 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134179 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134181 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134183 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134188 */   // GIR_Coverage, 7509,
     /* 134188 */   GIR_EraseRootFromParent_Done,
     /* 134189 */ // Label 2226: @134189
     /* 134189 */ GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(134221), // Rule ID 7510 //
     /* 134194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134197 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134204 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134208 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134208 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134211 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134213 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134215 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134220 */   // GIR_Coverage, 7510,
     /* 134220 */   GIR_EraseRootFromParent_Done,
     /* 134221 */ // Label 2227: @134221
     /* 134221 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(134253), // Rule ID 7511 //
     /* 134226 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134229 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134232 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134236 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134240 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134240 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134243 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134245 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134247 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134252 */   // GIR_Coverage, 7511,
     /* 134252 */   GIR_EraseRootFromParent_Done,
     /* 134253 */ // Label 2228: @134253
     /* 134253 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(134324), // Rule ID 7512 //
     /* 134258 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134261 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 134264 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134268 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134272 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v8f16] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v8i16:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 134272 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 134275 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 134279 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134284 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 134288 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 134290 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 134293 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 134297 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134302 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 134306 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 134308 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 134311 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 134313 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134316 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 134319 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 134322 */   GIR_RootConstrainSelectedInstOperands,
     /* 134323 */   // GIR_Coverage, 7512,
     /* 134323 */   GIR_EraseRootFromParent_Done,
     /* 134324 */ // Label 2229: @134324
     /* 134324 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(134350), // Rule ID 7513 //
     /* 134329 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134332 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134339 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134343 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2i64] }:$src)
     /* 134343 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 134348 */   GIR_RootConstrainSelectedInstOperands,
     /* 134349 */   // GIR_Coverage, 7513,
     /* 134349 */   GIR_Done,
     /* 134350 */ // Label 2230: @134350
     /* 134350 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(134376), // Rule ID 7514 //
     /* 134355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134358 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134361 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134365 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134369 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4i32] }:$src)
     /* 134369 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 134374 */   GIR_RootConstrainSelectedInstOperands,
     /* 134375 */   // GIR_Coverage, 7514,
     /* 134375 */   GIR_Done,
     /* 134376 */ // Label 2231: @134376
     /* 134376 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(134402), // Rule ID 7515 //
     /* 134381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 134387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134391 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134395 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)  =>  (REV16v16i8:{ *:[v8f16] } FPR128:{ *:[v16i8] }:$src)
     /* 134395 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 134400 */   GIR_RootConstrainSelectedInstOperands,
     /* 134401 */   // GIR_Coverage, 7515,
     /* 134401 */   GIR_Done,
     /* 134402 */ // Label 2232: @134402
     /* 134402 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(134428), // Rule ID 7516 //
     /* 134407 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134410 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134413 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134417 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134421 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v8i16:{ *:[v8f16] } FPR128:{ *:[v2f64] }:$src)
     /* 134421 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 134426 */   GIR_RootConstrainSelectedInstOperands,
     /* 134427 */   // GIR_Coverage, 7516,
     /* 134427 */   GIR_Done,
     /* 134428 */ // Label 2233: @134428
     /* 134428 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(134454), // Rule ID 7517 //
     /* 134433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134443 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134447 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v8i16:{ *:[v8f16] } FPR128:{ *:[v4f32] }:$src)
     /* 134447 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 134452 */   GIR_RootConstrainSelectedInstOperands,
     /* 134453 */   // GIR_Coverage, 7517,
     /* 134453 */   GIR_Done,
     /* 134454 */ // Label 2234: @134454
     /* 134454 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(134483), // Rule ID 7518 //
     /* 134459 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134466 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134470 */   // (bitconvert:{ *:[v8f16] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v8f16] }:$src
     /* 134470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134473 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134475 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134477 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134482 */   // GIR_Coverage, 7518,
     /* 134482 */   GIR_EraseRootFromParent_Done,
     /* 134483 */ // Label 2235: @134483
     /* 134483 */ GIM_Reject,
     /* 134484 */ // Label 1851: @134484
     /* 134484 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(134516), // Rule ID 7519 //
     /* 134489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 134495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134499 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134503 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134506 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134508 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134510 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134515 */   // GIR_Coverage, 7519,
     /* 134515 */   GIR_EraseRootFromParent_Done,
     /* 134516 */ // Label 2236: @134516
     /* 134516 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(134548), // Rule ID 7520 //
     /* 134521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134524 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134531 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134535 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134535 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134538 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134540 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134542 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134547 */   // GIR_Coverage, 7520,
     /* 134547 */   GIR_EraseRootFromParent_Done,
     /* 134548 */ // Label 2237: @134548
     /* 134548 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(134580), // Rule ID 7521 //
     /* 134553 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134556 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134563 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134567 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134570 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134572 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134574 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134579 */   // GIR_Coverage, 7521,
     /* 134579 */   GIR_EraseRootFromParent_Done,
     /* 134580 */ // Label 2238: @134580
     /* 134580 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(134612), // Rule ID 7522 //
     /* 134585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134588 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134591 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134595 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134599 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134599 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134602 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134604 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134606 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134611 */   // GIR_Coverage, 7522,
     /* 134611 */   GIR_EraseRootFromParent_Done,
     /* 134612 */ // Label 2239: @134612
     /* 134612 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(134644), // Rule ID 7523 //
     /* 134617 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134620 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134627 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134631 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134634 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134636 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134638 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134643 */   // GIR_Coverage, 7523,
     /* 134643 */   GIR_EraseRootFromParent_Done,
     /* 134644 */ // Label 2240: @134644
     /* 134644 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(134676), // Rule ID 7524 //
     /* 134649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134652 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134659 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134663 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134666 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134668 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134670 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134675 */   // GIR_Coverage, 7524,
     /* 134675 */   GIR_EraseRootFromParent_Done,
     /* 134676 */ // Label 2241: @134676
     /* 134676 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(134708), // Rule ID 7525 //
     /* 134681 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 134684 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134691 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134695 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)  =>  FPR128:{ *:[v16i8] }:$src
     /* 134695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134698 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134700 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134702 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134707 */   // GIR_Coverage, 7525,
     /* 134707 */   GIR_EraseRootFromParent_Done,
     /* 134708 */ // Label 2242: @134708
     /* 134708 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(134779), // Rule ID 7526 //
     /* 134713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134716 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s128,
     /* 134719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134723 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134727 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[f128] }:$src)  =>  (EXTv16i8:{ *:[v16i8] } (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), (REV64v16i8:{ *:[f128] } FPR128:{ *:[f128] }:$src), 8:{ *:[i32] })
     /* 134727 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 134730 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 134734 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134739 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 134743 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 134745 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 134748 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 134752 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 134757 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 134761 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 134763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 134766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 134768 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 134771 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 134774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 134777 */   GIR_RootConstrainSelectedInstOperands,
     /* 134778 */   // GIR_Coverage, 7526,
     /* 134778 */   GIR_EraseRootFromParent_Done,
     /* 134779 */ // Label 2243: @134779
     /* 134779 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(134805), // Rule ID 7527 //
     /* 134784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134787 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134794 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134798 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)  =>  (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2i64] }:$src)
     /* 134798 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 134803 */   GIR_RootConstrainSelectedInstOperands,
     /* 134804 */   // GIR_Coverage, 7527,
     /* 134804 */   GIR_Done,
     /* 134805 */ // Label 2244: @134805
     /* 134805 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(134831), // Rule ID 7528 //
     /* 134810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134820 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134824 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)  =>  (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4i32] }:$src)
     /* 134824 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 134829 */   GIR_RootConstrainSelectedInstOperands,
     /* 134830 */   // GIR_Coverage, 7528,
     /* 134830 */   GIR_Done,
     /* 134831 */ // Label 2245: @134831
     /* 134831 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(134857), // Rule ID 7529 //
     /* 134836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134839 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134846 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134850 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)  =>  (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8i16] }:$src)
     /* 134850 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 134855 */   GIR_RootConstrainSelectedInstOperands,
     /* 134856 */   // GIR_Coverage, 7529,
     /* 134856 */   GIR_Done,
     /* 134857 */ // Label 2246: @134857
     /* 134857 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(134883), // Rule ID 7530 //
     /* 134862 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134865 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 134868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134872 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134876 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)  =>  (REV64v16i8:{ *:[v16i8] } FPR128:{ *:[v2f64] }:$src)
     /* 134876 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 134881 */   GIR_RootConstrainSelectedInstOperands,
     /* 134882 */   // GIR_Coverage, 7530,
     /* 134882 */   GIR_Done,
     /* 134883 */ // Label 2247: @134883
     /* 134883 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(134909), // Rule ID 7531 //
     /* 134888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134891 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 134894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134898 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134902 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)  =>  (REV32v16i8:{ *:[v16i8] } FPR128:{ *:[v4f32] }:$src)
     /* 134902 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 134907 */   GIR_RootConstrainSelectedInstOperands,
     /* 134908 */   // GIR_Coverage, 7531,
     /* 134908 */   GIR_Done,
     /* 134909 */ // Label 2248: @134909
     /* 134909 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(134935), // Rule ID 7532 //
     /* 134914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsBE),
     /* 134917 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 134920 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134924 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 134928 */   // (bitconvert:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)  =>  (REV16v16i8:{ *:[v16i8] } FPR128:{ *:[v8f16] }:$src)
     /* 134928 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 134933 */   GIR_RootConstrainSelectedInstOperands,
     /* 134934 */   // GIR_Coverage, 7532,
     /* 134934 */   GIR_Done,
     /* 134935 */ // Label 2249: @134935
     /* 134935 */ GIM_Reject,
     /* 134936 */ // Label 1852: @134936
     /* 134936 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(134968), // Rule ID 11316 //
     /* 134941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 134944 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 134947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134955 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 134955 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134958 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134960 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134962 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134967 */   // GIR_Coverage, 11316,
     /* 134967 */   GIR_EraseRootFromParent_Done,
     /* 134968 */ // Label 2250: @134968
     /* 134968 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(135000), // Rule ID 11317 //
     /* 134973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 134976 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 134979 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134983 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134987 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 134987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 134990 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 134992 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 134994 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 134999 */   // GIR_Coverage, 11317,
     /* 134999 */   GIR_EraseRootFromParent_Done,
     /* 135000 */ // Label 2251: @135000
     /* 135000 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(135032), // Rule ID 11318 //
     /* 135005 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135008 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135015 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135019 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 135019 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135022 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135024 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135026 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135031 */   // GIR_Coverage, 11318,
     /* 135031 */   GIR_EraseRootFromParent_Done,
     /* 135032 */ // Label 2252: @135032
     /* 135032 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(135064), // Rule ID 11319 //
     /* 135037 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135047 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135051 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 135051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135054 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135056 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135058 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135063 */   // GIR_Coverage, 11319,
     /* 135063 */   GIR_EraseRootFromParent_Done,
     /* 135064 */ // Label 2253: @135064
     /* 135064 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(135096), // Rule ID 11320 //
     /* 135069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135079 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135083 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 135083 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135086 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135088 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135090 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135095 */   // GIR_Coverage, 11320,
     /* 135095 */   GIR_EraseRootFromParent_Done,
     /* 135096 */ // Label 2254: @135096
     /* 135096 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(135128), // Rule ID 11321 //
     /* 135101 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135104 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135111 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135115 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 135115 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135118 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135120 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135122 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135127 */   // GIR_Coverage, 11321,
     /* 135127 */   GIR_EraseRootFromParent_Done,
     /* 135128 */ // Label 2255: @135128
     /* 135128 */ GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(135160), // Rule ID 11334 //
     /* 135133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135136 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 135139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135143 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135147 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135147 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135150 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135152 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135154 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135159 */   // GIR_Coverage, 11334,
     /* 135159 */   GIR_EraseRootFromParent_Done,
     /* 135160 */ // Label 2256: @135160
     /* 135160 */ GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(135192), // Rule ID 11335 //
     /* 135165 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135175 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135179 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135179 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135182 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135184 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135186 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135191 */   // GIR_Coverage, 11335,
     /* 135191 */   GIR_EraseRootFromParent_Done,
     /* 135192 */ // Label 2257: @135192
     /* 135192 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(135224), // Rule ID 11336 //
     /* 135197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135200 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135207 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135211 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135211 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135214 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135216 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135218 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135223 */   // GIR_Coverage, 11336,
     /* 135223 */   GIR_EraseRootFromParent_Done,
     /* 135224 */ // Label 2258: @135224
     /* 135224 */ GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(135256), // Rule ID 11337 //
     /* 135229 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135232 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135239 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135243 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135243 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135246 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135248 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135250 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135255 */   // GIR_Coverage, 11337,
     /* 135255 */   GIR_EraseRootFromParent_Done,
     /* 135256 */ // Label 2259: @135256
     /* 135256 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(135288), // Rule ID 11338 //
     /* 135261 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135264 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135267 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135271 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135275 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135278 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135280 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135282 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135287 */   // GIR_Coverage, 11338,
     /* 135287 */   GIR_EraseRootFromParent_Done,
     /* 135288 */ // Label 2260: @135288
     /* 135288 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(135320), // Rule ID 11339 //
     /* 135293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135303 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135307 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135310 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135312 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135314 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135319 */   // GIR_Coverage, 11339,
     /* 135319 */   GIR_EraseRootFromParent_Done,
     /* 135320 */ // Label 2261: @135320
     /* 135320 */ GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(135352), // Rule ID 11344 //
     /* 135325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 135328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135335 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135339 */   // (bitconvert:{ *:[nxv2i64] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv2i64] }:$src
     /* 135339 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135342 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135344 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135346 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135351 */   // GIR_Coverage, 11344,
     /* 135351 */   GIR_EraseRootFromParent_Done,
     /* 135352 */ // Label 2262: @135352
     /* 135352 */ GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(135384), // Rule ID 11345 //
     /* 135357 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 135360 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135367 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135371 */   // (bitconvert:{ *:[nxv2f64] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv2f64] }:$src
     /* 135371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135374 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135376 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135378 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135383 */   // GIR_Coverage, 11345,
     /* 135383 */   GIR_EraseRootFromParent_Done,
     /* 135384 */ // Label 2263: @135384
     /* 135384 */ GIM_Reject,
     /* 135385 */ // Label 1853: @135385
     /* 135385 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(135417), // Rule ID 11310 //
     /* 135390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 135396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135400 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135404 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135404 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135407 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135409 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135411 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135416 */   // GIR_Coverage, 11310,
     /* 135416 */   GIR_EraseRootFromParent_Done,
     /* 135417 */ // Label 2264: @135417
     /* 135417 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(135449), // Rule ID 11311 //
     /* 135422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135432 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135436 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135436 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135439 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135441 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135443 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135448 */   // GIR_Coverage, 11311,
     /* 135448 */   GIR_EraseRootFromParent_Done,
     /* 135449 */ // Label 2265: @135449
     /* 135449 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(135481), // Rule ID 11312 //
     /* 135454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135457 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135464 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135468 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135468 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135471 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135473 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135475 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135480 */   // GIR_Coverage, 11312,
     /* 135480 */   GIR_EraseRootFromParent_Done,
     /* 135481 */ // Label 2266: @135481
     /* 135481 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(135513), // Rule ID 11313 //
     /* 135486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135489 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135496 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135500 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135500 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135503 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135505 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135507 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135512 */   // GIR_Coverage, 11313,
     /* 135512 */   GIR_EraseRootFromParent_Done,
     /* 135513 */ // Label 2267: @135513
     /* 135513 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(135545), // Rule ID 11314 //
     /* 135518 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135521 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135528 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135532 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135532 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135535 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135537 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135539 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135544 */   // GIR_Coverage, 11314,
     /* 135544 */   GIR_EraseRootFromParent_Done,
     /* 135545 */ // Label 2268: @135545
     /* 135545 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(135577), // Rule ID 11315 //
     /* 135550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135560 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135564 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135564 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135567 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135569 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135571 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135576 */   // GIR_Coverage, 11315,
     /* 135576 */   GIR_EraseRootFromParent_Done,
     /* 135577 */ // Label 2269: @135577
     /* 135577 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(135609), // Rule ID 11328 //
     /* 135582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135585 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 135588 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135592 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135596 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135599 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135601 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135603 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135608 */   // GIR_Coverage, 11328,
     /* 135608 */   GIR_EraseRootFromParent_Done,
     /* 135609 */ // Label 2270: @135609
     /* 135609 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(135641), // Rule ID 11329 //
     /* 135614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135617 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135624 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135628 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135628 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135631 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135633 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135635 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135640 */   // GIR_Coverage, 11329,
     /* 135640 */   GIR_EraseRootFromParent_Done,
     /* 135641 */ // Label 2271: @135641
     /* 135641 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(135673), // Rule ID 11330 //
     /* 135646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135649 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135652 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135656 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135660 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135663 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135665 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135667 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135672 */   // GIR_Coverage, 11330,
     /* 135672 */   GIR_EraseRootFromParent_Done,
     /* 135673 */ // Label 2272: @135673
     /* 135673 */ GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(135705), // Rule ID 11331 //
     /* 135678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135681 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135688 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135692 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135695 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135697 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135699 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135704 */   // GIR_Coverage, 11331,
     /* 135704 */   GIR_EraseRootFromParent_Done,
     /* 135705 */ // Label 2273: @135705
     /* 135705 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(135737), // Rule ID 11332 //
     /* 135710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135720 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135724 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135727 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135729 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135731 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135736 */   // GIR_Coverage, 11332,
     /* 135736 */   GIR_EraseRootFromParent_Done,
     /* 135737 */ // Label 2274: @135737
     /* 135737 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(135769), // Rule ID 11333 //
     /* 135742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135752 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135756 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135756 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135759 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135761 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135768 */   // GIR_Coverage, 11333,
     /* 135768 */   GIR_EraseRootFromParent_Done,
     /* 135769 */ // Label 2275: @135769
     /* 135769 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(135801), // Rule ID 11342 //
     /* 135774 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 135777 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135784 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135788 */   // (bitconvert:{ *:[nxv4i32] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv4i32] }:$src
     /* 135788 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135791 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135793 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135795 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135800 */   // GIR_Coverage, 11342,
     /* 135800 */   GIR_EraseRootFromParent_Done,
     /* 135801 */ // Label 2276: @135801
     /* 135801 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(135833), // Rule ID 11343 //
     /* 135806 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 135809 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135812 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135816 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135820 */   // (bitconvert:{ *:[nxv4f32] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv4f32] }:$src
     /* 135820 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135823 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135825 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135827 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135832 */   // GIR_Coverage, 11343,
     /* 135832 */   GIR_EraseRootFromParent_Done,
     /* 135833 */ // Label 2277: @135833
     /* 135833 */ GIM_Reject,
     /* 135834 */ // Label 1854: @135834
     /* 135834 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(135866), // Rule ID 11304 //
     /* 135839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135842 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 135845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135849 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135853 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 135853 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135856 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135858 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135860 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135865 */   // GIR_Coverage, 11304,
     /* 135865 */   GIR_EraseRootFromParent_Done,
     /* 135866 */ // Label 2278: @135866
     /* 135866 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(135898), // Rule ID 11305 //
     /* 135871 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135874 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135881 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135885 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 135885 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135888 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135890 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135892 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135897 */   // GIR_Coverage, 11305,
     /* 135897 */   GIR_EraseRootFromParent_Done,
     /* 135898 */ // Label 2279: @135898
     /* 135898 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(135930), // Rule ID 11306 //
     /* 135903 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135906 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 135909 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135913 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135917 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 135917 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135920 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135922 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135924 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135929 */   // GIR_Coverage, 11306,
     /* 135929 */   GIR_EraseRootFromParent_Done,
     /* 135930 */ // Label 2280: @135930
     /* 135930 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(135962), // Rule ID 11307 //
     /* 135935 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135938 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 135941 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135945 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135949 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 135949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135952 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135954 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135956 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135961 */   // GIR_Coverage, 11307,
     /* 135961 */   GIR_EraseRootFromParent_Done,
     /* 135962 */ // Label 2281: @135962
     /* 135962 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(135994), // Rule ID 11308 //
     /* 135967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 135970 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 135973 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135977 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135981 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 135981 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 135984 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 135986 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 135988 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 135993 */   // GIR_Coverage, 11308,
     /* 135993 */   GIR_EraseRootFromParent_Done,
     /* 135994 */ // Label 2282: @135994
     /* 135994 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(136026), // Rule ID 11309 //
     /* 135999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 136005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136009 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136013 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 136013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136016 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136018 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136020 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136025 */   // GIR_Coverage, 11309,
     /* 136025 */   GIR_EraseRootFromParent_Done,
     /* 136026 */ // Label 2283: @136026
     /* 136026 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(136058), // Rule ID 11322 //
     /* 136031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136034 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 136037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136041 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136045 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv16i8] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136048 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136050 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136052 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136057 */   // GIR_Coverage, 11322,
     /* 136057 */   GIR_EraseRootFromParent_Done,
     /* 136058 */ // Label 2284: @136058
     /* 136058 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(136090), // Rule ID 11323 //
     /* 136063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136066 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 136069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136073 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136077 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136077 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136080 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136082 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136084 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136089 */   // GIR_Coverage, 11323,
     /* 136089 */   GIR_EraseRootFromParent_Done,
     /* 136090 */ // Label 2285: @136090
     /* 136090 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(136122), // Rule ID 11324 //
     /* 136095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 136101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136105 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136109 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136109 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136112 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136114 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136116 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136121 */   // GIR_Coverage, 11324,
     /* 136121 */   GIR_EraseRootFromParent_Done,
     /* 136122 */ // Label 2286: @136122
     /* 136122 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(136154), // Rule ID 11325 //
     /* 136127 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 136133 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136137 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136141 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136141 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136144 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136146 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136148 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136153 */   // GIR_Coverage, 11325,
     /* 136153 */   GIR_EraseRootFromParent_Done,
     /* 136154 */ // Label 2287: @136154
     /* 136154 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(136186), // Rule ID 11326 //
     /* 136159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136162 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 136165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136169 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136173 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136176 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136178 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136180 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136185 */   // GIR_Coverage, 11326,
     /* 136185 */   GIR_EraseRootFromParent_Done,
     /* 136186 */ // Label 2288: @136186
     /* 136186 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(136218), // Rule ID 11327 //
     /* 136191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 136197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136201 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136205 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136208 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136210 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136212 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136217 */   // GIR_Coverage, 11327,
     /* 136217 */   GIR_EraseRootFromParent_Done,
     /* 136218 */ // Label 2289: @136218
     /* 136218 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(136250), // Rule ID 11340 //
     /* 136223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 136226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 136229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136233 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136237 */   // (bitconvert:{ *:[nxv8i16] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv8i16] }:$src
     /* 136237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136240 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136242 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136244 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136249 */   // GIR_Coverage, 11340,
     /* 136249 */   GIR_EraseRootFromParent_Done,
     /* 136250 */ // Label 2290: @136250
     /* 136250 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(136282), // Rule ID 11341 //
     /* 136255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 136258 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 136261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136265 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136269 */   // (bitconvert:{ *:[nxv8f16] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv8f16] }:$src
     /* 136269 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136272 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136274 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136276 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136281 */   // GIR_Coverage, 11341,
     /* 136281 */   GIR_EraseRootFromParent_Done,
     /* 136282 */ // Label 2291: @136282
     /* 136282 */ GIM_Reject,
     /* 136283 */ // Label 1855: @136283
     /* 136283 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(136315), // Rule ID 11298 //
     /* 136288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136291 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 136294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136298 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136302 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136302 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136305 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136307 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136309 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136314 */   // GIR_Coverage, 11298,
     /* 136314 */   GIR_EraseRootFromParent_Done,
     /* 136315 */ // Label 2292: @136315
     /* 136315 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(136347), // Rule ID 11299 //
     /* 136320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136323 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 136326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136330 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136334 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136337 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136339 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136341 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136346 */   // GIR_Coverage, 11299,
     /* 136346 */   GIR_EraseRootFromParent_Done,
     /* 136347 */ // Label 2293: @136347
     /* 136347 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(136379), // Rule ID 11300 //
     /* 136352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 136358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136362 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136366 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136366 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136369 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136371 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136373 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136378 */   // GIR_Coverage, 11300,
     /* 136378 */   GIR_EraseRootFromParent_Done,
     /* 136379 */ // Label 2294: @136379
     /* 136379 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(136411), // Rule ID 11301 //
     /* 136384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 136390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136394 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136398 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136398 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136401 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136403 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136405 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136410 */   // GIR_Coverage, 11301,
     /* 136410 */   GIR_EraseRootFromParent_Done,
     /* 136411 */ // Label 2295: @136411
     /* 136411 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(136443), // Rule ID 11302 //
     /* 136416 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136419 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 136422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136426 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136430 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136433 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136435 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136437 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136442 */   // GIR_Coverage, 11302,
     /* 136442 */   GIR_EraseRootFromParent_Done,
     /* 136443 */ // Label 2296: @136443
     /* 136443 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(136475), // Rule ID 11303 //
     /* 136448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME_IsLE),
     /* 136451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 136454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136458 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136462 */   // (bitconvert:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$src)  =>  ZPR:{ *:[nxv16i8] }:$src
     /* 136462 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136465 */   GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 136467 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 136469 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 136474 */   // GIR_Coverage, 11303,
     /* 136474 */   GIR_EraseRootFromParent_Done,
     /* 136475 */ // Label 2297: @136475
     /* 136475 */ GIM_Reject,
     /* 136476 */ // Label 1856: @136476
     /* 136476 */ GIM_Reject,
     /* 136477 */ // Label 16: @136477
     /* 136477 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(136967),
     /* 136488 */ /*GILLT_s16*//*Label 2298*/ GIMT_Encode4(136528),
     /* 136492 */ /*GILLT_s32*//*Label 2299*/ GIMT_Encode4(136559),
     /* 136496 */ /*GILLT_s64*//*Label 2300*/ GIMT_Encode4(136590), GIMT_Encode4(0),
     /* 136504 */ /*GILLT_v2s32*//*Label 2301*/ GIMT_Encode4(136621),
     /* 136508 */ /*GILLT_v2s64*//*Label 2302*/ GIMT_Encode4(136652),
     /* 136512 */ /*GILLT_v4s16*//*Label 2303*/ GIMT_Encode4(136683),
     /* 136516 */ /*GILLT_v4s32*//*Label 2304*/ GIMT_Encode4(136714), GIMT_Encode4(0),
     /* 136524 */ /*GILLT_v8s16*//*Label 2305*/ GIMT_Encode4(136745),
     /* 136528 */ // Label 2298: @136528
     /* 136528 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(136558), // Rule ID 606 //
     /* 136533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 136536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 136539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 136543 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 136547 */   // (ftrunc:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTZHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 136547 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZHr),
     /* 136552 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136556 */   GIR_RootConstrainSelectedInstOperands,
     /* 136557 */   // GIR_Coverage, 606,
     /* 136557 */   GIR_Done,
     /* 136558 */ // Label 2307: @136558
     /* 136558 */ GIM_Reject,
     /* 136559 */ // Label 2299: @136559
     /* 136559 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(136589), // Rule ID 608 //
     /* 136564 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 136567 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 136570 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136574 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 136578 */   // (ftrunc:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 136578 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZSr),
     /* 136583 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136587 */   GIR_RootConstrainSelectedInstOperands,
     /* 136588 */   // GIR_Coverage, 608,
     /* 136588 */   GIR_Done,
     /* 136589 */ // Label 2308: @136589
     /* 136589 */ GIM_Reject,
     /* 136590 */ // Label 2300: @136590
     /* 136590 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(136620), // Rule ID 610 //
     /* 136595 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 136598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 136601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136605 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136609 */   // (ftrunc:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 136609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZDr),
     /* 136614 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136618 */   GIR_RootConstrainSelectedInstOperands,
     /* 136619 */   // GIR_Coverage, 610,
     /* 136619 */   GIR_Done,
     /* 136620 */ // Label 2309: @136620
     /* 136620 */ GIM_Reject,
     /* 136621 */ // Label 2301: @136621
     /* 136621 */ GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(136651), // Rule ID 963 //
     /* 136626 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 136629 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 136632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136636 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136640 */   // (ftrunc:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTZv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 136640 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f32),
     /* 136645 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136649 */   GIR_RootConstrainSelectedInstOperands,
     /* 136650 */   // GIR_Coverage, 963,
     /* 136650 */   GIR_Done,
     /* 136651 */ // Label 2310: @136651
     /* 136651 */ GIM_Reject,
     /* 136652 */ // Label 2302: @136652
     /* 136652 */ GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(136682), // Rule ID 967 //
     /* 136657 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 136660 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 136663 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136667 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136671 */   // (ftrunc:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTZv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 136671 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv2f64),
     /* 136676 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136680 */   GIR_RootConstrainSelectedInstOperands,
     /* 136681 */   // GIR_Coverage, 967,
     /* 136681 */   GIR_Done,
     /* 136682 */ // Label 2311: @136682
     /* 136682 */ GIM_Reject,
     /* 136683 */ // Label 2303: @136683
     /* 136683 */ GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(136713), // Rule ID 959 //
     /* 136688 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 136691 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 136694 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136698 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136702 */   // (ftrunc:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTZv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 136702 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f16),
     /* 136707 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136711 */   GIR_RootConstrainSelectedInstOperands,
     /* 136712 */   // GIR_Coverage, 959,
     /* 136712 */   GIR_Done,
     /* 136713 */ // Label 2312: @136713
     /* 136713 */ GIM_Reject,
     /* 136714 */ // Label 2304: @136714
     /* 136714 */ GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(136744), // Rule ID 965 //
     /* 136719 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 136722 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 136725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136729 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136733 */   // (ftrunc:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTZv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 136733 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 136738 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136742 */   GIR_RootConstrainSelectedInstOperands,
     /* 136743 */   // GIR_Coverage, 965,
     /* 136743 */   GIR_Done,
     /* 136744 */ // Label 2313: @136744
     /* 136744 */ GIM_Reject,
     /* 136745 */ // Label 2305: @136745
     /* 136745 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(136966),
     /* 136750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 136753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136757 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136761 */   GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(136780), // Rule ID 961 //
     /* 136766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 136769 */     // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTZv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 136769 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv8f16),
     /* 136774 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 136778 */     GIR_RootConstrainSelectedInstOperands,
     /* 136779 */     // GIR_Coverage, 961,
     /* 136779 */     GIR_Done,
     /* 136780 */   // Label 2315: @136780
     /* 136780 */   GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(136965), // Rule ID 7658 //
     /* 136785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 136788 */     // (ftrunc:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTZv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTZv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 136788 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 136791 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 136795 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136800 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 136804 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 136806 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 136809 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 136813 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136818 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 136821 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 136823 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 136826 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 136830 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136835 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 136841 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136846 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136851 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 136854 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 136858 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136863 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 136866 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 136868 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 136871 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTZv4f32),
     /* 136875 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136880 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 136883 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 136885 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 136888 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 136892 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136897 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 136900 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 136902 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 136905 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 136909 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136914 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 136916 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 136919 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 136923 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 136928 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 136931 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 136934 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 136937 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136942 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 136947 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 136952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 136955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 136957 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 136960 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 136963 */     GIR_RootConstrainSelectedInstOperands,
     /* 136964 */     // GIR_Coverage, 7658,
     /* 136964 */     GIR_EraseRootFromParent_Done,
     /* 136965 */   // Label 2316: @136965
     /* 136965 */   GIM_Reject,
     /* 136966 */ // Label 2314: @136966
     /* 136966 */ GIM_Reject,
     /* 136967 */ // Label 2306: @136967
     /* 136967 */ GIM_Reject,
     /* 136968 */ // Label 17: @136968
     /* 136968 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 2325*/ GIMT_Encode4(137458),
     /* 136979 */ /*GILLT_s16*//*Label 2317*/ GIMT_Encode4(137019),
     /* 136983 */ /*GILLT_s32*//*Label 2318*/ GIMT_Encode4(137050),
     /* 136987 */ /*GILLT_s64*//*Label 2319*/ GIMT_Encode4(137081), GIMT_Encode4(0),
     /* 136995 */ /*GILLT_v2s32*//*Label 2320*/ GIMT_Encode4(137112),
     /* 136999 */ /*GILLT_v2s64*//*Label 2321*/ GIMT_Encode4(137143),
     /* 137003 */ /*GILLT_v4s16*//*Label 2322*/ GIMT_Encode4(137174),
     /* 137007 */ /*GILLT_v4s32*//*Label 2323*/ GIMT_Encode4(137205), GIMT_Encode4(0),
     /* 137015 */ /*GILLT_v8s16*//*Label 2324*/ GIMT_Encode4(137236),
     /* 137019 */ // Label 2317: @137019
     /* 137019 */ GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(137049), // Rule ID 570 //
     /* 137024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 137027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 137030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 137034 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 137038 */   // (fround:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTAHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 137038 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAHr),
     /* 137043 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137047 */   GIR_RootConstrainSelectedInstOperands,
     /* 137048 */   // GIR_Coverage, 570,
     /* 137048 */   GIR_Done,
     /* 137049 */ // Label 2326: @137049
     /* 137049 */ GIM_Reject,
     /* 137050 */ // Label 2318: @137050
     /* 137050 */ GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(137080), // Rule ID 572 //
     /* 137055 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 137058 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 137061 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137065 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137069 */   // (fround:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTASr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 137069 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTASr),
     /* 137074 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137078 */   GIR_RootConstrainSelectedInstOperands,
     /* 137079 */   // GIR_Coverage, 572,
     /* 137079 */   GIR_Done,
     /* 137080 */ // Label 2327: @137080
     /* 137080 */ GIM_Reject,
     /* 137081 */ // Label 2319: @137081
     /* 137081 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(137111), // Rule ID 574 //
     /* 137086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 137089 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 137092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137096 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137100 */   // (fround:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTADr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 137100 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTADr),
     /* 137105 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137109 */   GIR_RootConstrainSelectedInstOperands,
     /* 137110 */   // GIR_Coverage, 574,
     /* 137110 */   GIR_Done,
     /* 137111 */ // Label 2328: @137111
     /* 137111 */ GIM_Reject,
     /* 137112 */ // Label 2320: @137112
     /* 137112 */ GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(137142), // Rule ID 903 //
     /* 137117 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 137120 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 137123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137127 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137131 */   // (fround:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 137131 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f32),
     /* 137136 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137140 */   GIR_RootConstrainSelectedInstOperands,
     /* 137141 */   // GIR_Coverage, 903,
     /* 137141 */   GIR_Done,
     /* 137142 */ // Label 2329: @137142
     /* 137142 */ GIM_Reject,
     /* 137143 */ // Label 2321: @137143
     /* 137143 */ GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(137173), // Rule ID 907 //
     /* 137148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 137151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 137154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137162 */   // (fround:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 137162 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv2f64),
     /* 137167 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137171 */   GIR_RootConstrainSelectedInstOperands,
     /* 137172 */   // GIR_Coverage, 907,
     /* 137172 */   GIR_Done,
     /* 137173 */ // Label 2330: @137173
     /* 137173 */ GIM_Reject,
     /* 137174 */ // Label 2322: @137174
     /* 137174 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(137204), // Rule ID 899 //
     /* 137179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 137182 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 137185 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137189 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137193 */   // (fround:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 137193 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f16),
     /* 137198 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137202 */   GIR_RootConstrainSelectedInstOperands,
     /* 137203 */   // GIR_Coverage, 899,
     /* 137203 */   GIR_Done,
     /* 137204 */ // Label 2331: @137204
     /* 137204 */ GIM_Reject,
     /* 137205 */ // Label 2323: @137205
     /* 137205 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(137235), // Rule ID 905 //
     /* 137210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 137213 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 137216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137220 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137224 */   // (fround:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 137224 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 137229 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137233 */   GIR_RootConstrainSelectedInstOperands,
     /* 137234 */   // GIR_Coverage, 905,
     /* 137234 */   GIR_Done,
     /* 137235 */ // Label 2332: @137235
     /* 137235 */ GIM_Reject,
     /* 137236 */ // Label 2324: @137236
     /* 137236 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(137457),
     /* 137241 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 137244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137248 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137252 */   GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(137271), // Rule ID 901 //
     /* 137257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 137260 */     // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 137260 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv8f16),
     /* 137265 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 137269 */     GIR_RootConstrainSelectedInstOperands,
     /* 137270 */     // GIR_Coverage, 901,
     /* 137270 */     GIR_Done,
     /* 137271 */   // Label 2334: @137271
     /* 137271 */   GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(137456), // Rule ID 7652 //
     /* 137276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 137279 */     // (fround:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTAv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTAv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 137279 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 137282 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 137286 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137291 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137295 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 137297 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 137300 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 137304 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137309 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 137312 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 137314 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 137317 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 137321 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137326 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 137332 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137337 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137342 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 137345 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 137349 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137354 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 137357 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 137359 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 137362 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTAv4f32),
     /* 137366 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137371 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 137374 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 137376 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 137379 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 137383 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137388 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 137391 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 137393 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 137396 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 137400 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137405 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 137407 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 137410 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 137414 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137419 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 137422 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 137425 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 137428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137433 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 137438 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 137446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 137448 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137451 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 137454 */     GIR_RootConstrainSelectedInstOperands,
     /* 137455 */     // GIR_Coverage, 7652,
     /* 137455 */     GIR_EraseRootFromParent_Done,
     /* 137456 */   // Label 2335: @137456
     /* 137456 */   GIM_Reject,
     /* 137457 */ // Label 2333: @137457
     /* 137457 */ GIM_Reject,
     /* 137458 */ // Label 2325: @137458
     /* 137458 */ GIM_Reject,
     /* 137459 */ // Label 18: @137459
     /* 137459 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2338*/ GIMT_Encode4(137978),
     /* 137470 */ /*GILLT_s32*//*Label 2336*/ GIMT_Encode4(137478),
     /* 137474 */ /*GILLT_s64*//*Label 2337*/ GIMT_Encode4(137728),
     /* 137478 */ // Label 2336: @137478
     /* 137478 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(137521), // Rule ID 4862 //
     /* 137483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 137486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 137489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137493 */   // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 137493 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 137496 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 137500 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137505 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137509 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137511 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 137514 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137516 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137519 */   GIR_RootConstrainSelectedInstOperands,
     /* 137520 */   // GIR_Coverage, 4862,
     /* 137520 */   GIR_EraseRootFromParent_Done,
     /* 137521 */ // Label 2339: @137521
     /* 137521 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(137561), // Rule ID 4868 //
     /* 137526 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 137529 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137533 */   // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 137533 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 137536 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 137540 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137545 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137549 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 137554 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137556 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137559 */   GIR_RootConstrainSelectedInstOperands,
     /* 137560 */   // GIR_Coverage, 4868,
     /* 137560 */   GIR_EraseRootFromParent_Done,
     /* 137561 */ // Label 2340: @137561
     /* 137561 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(137601), // Rule ID 4870 //
     /* 137566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 137569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 137573 */   // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 137573 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 137576 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 137580 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137585 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137589 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 137594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137596 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137599 */   GIR_RootConstrainSelectedInstOperands,
     /* 137600 */   // GIR_Coverage, 4870,
     /* 137600 */   GIR_EraseRootFromParent_Done,
     /* 137601 */ // Label 2341: @137601
     /* 137601 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(137644), // Rule ID 5799 //
     /* 137606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 137609 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 137612 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137616 */   // (lrint:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSSHr:{ *:[i32] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 137616 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 137619 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 137623 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137628 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137632 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 137637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137639 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137642 */   GIR_RootConstrainSelectedInstOperands,
     /* 137643 */   // GIR_Coverage, 5799,
     /* 137643 */   GIR_EraseRootFromParent_Done,
     /* 137644 */ // Label 2342: @137644
     /* 137644 */ GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(137687), // Rule ID 5800 //
     /* 137649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 137652 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 137655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137659 */   // (lrint:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSSDr:{ *:[i32] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 137659 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 137662 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 137666 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137671 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137675 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137677 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 137680 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137682 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137685 */   GIR_RootConstrainSelectedInstOperands,
     /* 137686 */   // GIR_Coverage, 5800,
     /* 137686 */   GIR_EraseRootFromParent_Done,
     /* 137687 */ // Label 2343: @137687
     /* 137687 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(137727), // Rule ID 5805 //
     /* 137692 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 137695 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 137699 */   // (lrint:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSv1i32:{ *:[i32] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 137699 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 137702 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 137706 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137711 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137715 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137717 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 137720 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137722 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137725 */   GIR_RootConstrainSelectedInstOperands,
     /* 137726 */   // GIR_Coverage, 5805,
     /* 137726 */   GIR_EraseRootFromParent_Done,
     /* 137727 */ // Label 2344: @137727
     /* 137727 */ GIM_Reject,
     /* 137728 */ // Label 2337: @137728
     /* 137728 */ GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(137771), // Rule ID 4864 //
     /* 137733 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 137736 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 137739 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 137743 */   // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 137743 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 137746 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 137750 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137755 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137759 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 137764 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137766 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137769 */   GIR_RootConstrainSelectedInstOperands,
     /* 137770 */   // GIR_Coverage, 4864,
     /* 137770 */   GIR_EraseRootFromParent_Done,
     /* 137771 */ // Label 2345: @137771
     /* 137771 */ GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(137811), // Rule ID 4872 //
     /* 137776 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 137779 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 137783 */   // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 137783 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 137786 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 137790 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137795 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137799 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 137804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137806 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137809 */   GIR_RootConstrainSelectedInstOperands,
     /* 137810 */   // GIR_Coverage, 4872,
     /* 137810 */   GIR_EraseRootFromParent_Done,
     /* 137811 */ // Label 2346: @137811
     /* 137811 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(137851), // Rule ID 4874 //
     /* 137816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 137819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 137823 */   // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 137823 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 137826 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 137830 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137835 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137839 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137841 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 137844 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137846 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137849 */   GIR_RootConstrainSelectedInstOperands,
     /* 137850 */   // GIR_Coverage, 4874,
     /* 137850 */   GIR_EraseRootFromParent_Done,
     /* 137851 */ // Label 2347: @137851
     /* 137851 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(137894), // Rule ID 5801 //
     /* 137856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 137859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 137862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137866 */   // (lrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSDHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 137866 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 137869 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 137873 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137878 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137882 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 137887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137889 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137892 */   GIR_RootConstrainSelectedInstOperands,
     /* 137893 */   // GIR_Coverage, 5801,
     /* 137893 */   GIR_EraseRootFromParent_Done,
     /* 137894 */ // Label 2348: @137894
     /* 137894 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(137937), // Rule ID 5803 //
     /* 137899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 137902 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 137905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137909 */   // (lrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSDSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 137909 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 137912 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 137916 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137921 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137925 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137927 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 137930 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137932 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137935 */   GIR_RootConstrainSelectedInstOperands,
     /* 137936 */   // GIR_Coverage, 5803,
     /* 137936 */   GIR_EraseRootFromParent_Done,
     /* 137937 */ // Label 2349: @137937
     /* 137937 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(137977), // Rule ID 5806 //
     /* 137942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 137945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 137949 */   // (lrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 137949 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 137952 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 137956 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 137961 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 137965 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 137967 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 137970 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 137972 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 137975 */   GIR_RootConstrainSelectedInstOperands,
     /* 137976 */   // GIR_Coverage, 5806,
     /* 137976 */   GIR_EraseRootFromParent_Done,
     /* 137977 */ // Label 2350: @137977
     /* 137977 */ GIM_Reject,
     /* 137978 */ // Label 2338: @137978
     /* 137978 */ GIM_Reject,
     /* 137979 */ // Label 19: @137979
     /* 137979 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(138271),
     /* 137984 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 137987 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2355*/ GIMT_Encode4(138127),
     /* 137998 */   /*GILLT_s16*//*Label 2352*/ GIMT_Encode4(138010),
     /* 138002 */   /*GILLT_s32*//*Label 2353*/ GIMT_Encode4(138051),
     /* 138006 */   /*GILLT_s64*//*Label 2354*/ GIMT_Encode4(138089),
     /* 138010 */   // Label 2352: @138010
     /* 138010 */   GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(138050), // Rule ID 4866 //
     /* 138015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 138018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 138022 */     // (llrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 138022 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 138025 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 138029 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138034 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138038 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 138043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138045 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138048 */     GIR_RootConstrainSelectedInstOperands,
     /* 138049 */     // GIR_Coverage, 4866,
     /* 138049 */     GIR_EraseRootFromParent_Done,
     /* 138050 */   // Label 2356: @138050
     /* 138050 */   GIM_Reject,
     /* 138051 */   // Label 2353: @138051
     /* 138051 */   GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(138088), // Rule ID 4876 //
     /* 138056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 138060 */     // (llrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 138060 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 138063 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 138067 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138072 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138076 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 138081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138083 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138086 */     GIR_RootConstrainSelectedInstOperands,
     /* 138087 */     // GIR_Coverage, 4876,
     /* 138087 */     GIR_EraseRootFromParent_Done,
     /* 138088 */   // Label 2357: @138088
     /* 138088 */   GIM_Reject,
     /* 138089 */   // Label 2354: @138089
     /* 138089 */   GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(138126), // Rule ID 4878 //
     /* 138094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 138098 */     // (llrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 138098 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 138101 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 138105 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138110 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138114 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 138119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138121 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138124 */     GIR_RootConstrainSelectedInstOperands,
     /* 138125 */     // GIR_Coverage, 4878,
     /* 138125 */     GIR_EraseRootFromParent_Done,
     /* 138126 */   // Label 2358: @138126
     /* 138126 */   GIM_Reject,
     /* 138127 */   // Label 2355: @138127
     /* 138127 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 2362*/ GIMT_Encode4(138270),
     /* 138138 */   /*GILLT_s16*//*Label 2359*/ GIMT_Encode4(138150),
     /* 138142 */   /*GILLT_s32*//*Label 2360*/ GIMT_Encode4(138191),
     /* 138146 */   /*GILLT_s64*//*Label 2361*/ GIMT_Encode4(138232),
     /* 138150 */   // Label 2359: @138150
     /* 138150 */   GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(138190), // Rule ID 5802 //
     /* 138155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 138158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138162 */     // (llrint:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSDHr:{ *:[i64] } (FRINTXHr:{ *:[i16] } f16:{ *:[f16] }:$Rn))
     /* 138162 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 138165 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 138169 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138174 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138178 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 138183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138185 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138188 */     GIR_RootConstrainSelectedInstOperands,
     /* 138189 */     // GIR_Coverage, 5802,
     /* 138189 */     GIR_EraseRootFromParent_Done,
     /* 138190 */   // Label 2363: @138190
     /* 138190 */   GIM_Reject,
     /* 138191 */   // Label 2360: @138191
     /* 138191 */   GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(138231), // Rule ID 5804 //
     /* 138196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 138199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138203 */     // (llrint:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSDSr:{ *:[i64] } (FRINTXSr:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 138203 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 138206 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 138210 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138215 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138219 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 138224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138226 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138229 */     GIR_RootConstrainSelectedInstOperands,
     /* 138230 */     // GIR_Coverage, 5804,
     /* 138230 */     GIR_EraseRootFromParent_Done,
     /* 138231 */   // Label 2364: @138231
     /* 138231 */   GIM_Reject,
     /* 138232 */   // Label 2361: @138232
     /* 138232 */   GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(138269), // Rule ID 5807 //
     /* 138237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138241 */     // (llrint:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[i64] } (FRINTXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 138241 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 138244 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 138248 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138253 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138257 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 138259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 138262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 138264 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138267 */     GIR_RootConstrainSelectedInstOperands,
     /* 138268 */     // GIR_Coverage, 5807,
     /* 138268 */     GIR_EraseRootFromParent_Done,
     /* 138269 */   // Label 2365: @138269
     /* 138269 */   GIM_Reject,
     /* 138270 */   // Label 2362: @138270
     /* 138270 */   GIM_Reject,
     /* 138271 */ // Label 2351: @138271
     /* 138271 */ GIM_Reject,
     /* 138272 */ // Label 20: @138272
     /* 138272 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 2374*/ GIMT_Encode4(138762),
     /* 138283 */ /*GILLT_s16*//*Label 2366*/ GIMT_Encode4(138323),
     /* 138287 */ /*GILLT_s32*//*Label 2367*/ GIMT_Encode4(138354),
     /* 138291 */ /*GILLT_s64*//*Label 2368*/ GIMT_Encode4(138385), GIMT_Encode4(0),
     /* 138299 */ /*GILLT_v2s32*//*Label 2369*/ GIMT_Encode4(138416),
     /* 138303 */ /*GILLT_v2s64*//*Label 2370*/ GIMT_Encode4(138447),
     /* 138307 */ /*GILLT_v4s16*//*Label 2371*/ GIMT_Encode4(138478),
     /* 138311 */ /*GILLT_v4s32*//*Label 2372*/ GIMT_Encode4(138509), GIMT_Encode4(0),
     /* 138319 */ /*GILLT_v8s16*//*Label 2373*/ GIMT_Encode4(138540),
     /* 138323 */ // Label 2366: @138323
     /* 138323 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(138353), // Rule ID 588 //
     /* 138328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 138331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 138334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 138338 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 138342 */   // (froundeven:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTNHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 138342 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNHr),
     /* 138347 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138351 */   GIR_RootConstrainSelectedInstOperands,
     /* 138352 */   // GIR_Coverage, 588,
     /* 138352 */   GIR_Done,
     /* 138353 */ // Label 2375: @138353
     /* 138353 */ GIM_Reject,
     /* 138354 */ // Label 2367: @138354
     /* 138354 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(138384), // Rule ID 590 //
     /* 138359 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 138362 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 138365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 138369 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 138373 */   // (froundeven:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTNSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 138373 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNSr),
     /* 138378 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138382 */   GIR_RootConstrainSelectedInstOperands,
     /* 138383 */   // GIR_Coverage, 590,
     /* 138383 */   GIR_Done,
     /* 138384 */ // Label 2376: @138384
     /* 138384 */ GIM_Reject,
     /* 138385 */ // Label 2368: @138385
     /* 138385 */ GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(138415), // Rule ID 592 //
     /* 138390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 138393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 138396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138400 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138404 */   // (froundeven:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTNDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 138404 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNDr),
     /* 138409 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138413 */   GIR_RootConstrainSelectedInstOperands,
     /* 138414 */   // GIR_Coverage, 592,
     /* 138414 */   GIR_Done,
     /* 138415 */ // Label 2377: @138415
     /* 138415 */ GIM_Reject,
     /* 138416 */ // Label 2369: @138416
     /* 138416 */ GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(138446), // Rule ID 933 //
     /* 138421 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 138424 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 138427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138431 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138435 */   // (froundeven:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTNv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 138435 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f32),
     /* 138440 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138444 */   GIR_RootConstrainSelectedInstOperands,
     /* 138445 */   // GIR_Coverage, 933,
     /* 138445 */   GIR_Done,
     /* 138446 */ // Label 2378: @138446
     /* 138446 */ GIM_Reject,
     /* 138447 */ // Label 2370: @138447
     /* 138447 */ GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(138477), // Rule ID 937 //
     /* 138452 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 138455 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 138458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138462 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138466 */   // (froundeven:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTNv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 138466 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv2f64),
     /* 138471 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138475 */   GIR_RootConstrainSelectedInstOperands,
     /* 138476 */   // GIR_Coverage, 937,
     /* 138476 */   GIR_Done,
     /* 138477 */ // Label 2379: @138477
     /* 138477 */ GIM_Reject,
     /* 138478 */ // Label 2371: @138478
     /* 138478 */ GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(138508), // Rule ID 929 //
     /* 138483 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 138486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 138489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138493 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138497 */   // (froundeven:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTNv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 138497 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f16),
     /* 138502 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138506 */   GIR_RootConstrainSelectedInstOperands,
     /* 138507 */   // GIR_Coverage, 929,
     /* 138507 */   GIR_Done,
     /* 138508 */ // Label 2380: @138508
     /* 138508 */ GIM_Reject,
     /* 138509 */ // Label 2372: @138509
     /* 138509 */ GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(138539), // Rule ID 935 //
     /* 138514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 138517 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 138520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138524 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138528 */   // (froundeven:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTNv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 138528 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 138533 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138537 */   GIR_RootConstrainSelectedInstOperands,
     /* 138538 */   // GIR_Coverage, 935,
     /* 138538 */   GIR_Done,
     /* 138539 */ // Label 2381: @138539
     /* 138539 */ GIM_Reject,
     /* 138540 */ // Label 2373: @138540
     /* 138540 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(138761),
     /* 138545 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 138548 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138552 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138556 */   GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(138575), // Rule ID 931 //
     /* 138561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 138564 */     // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTNv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 138564 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv8f16),
     /* 138569 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 138573 */     GIR_RootConstrainSelectedInstOperands,
     /* 138574 */     // GIR_Coverage, 931,
     /* 138574 */     GIR_Done,
     /* 138575 */   // Label 2383: @138575
     /* 138575 */   GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(138760), // Rule ID 7654 //
     /* 138580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 138583 */     // (froundeven:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTNv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTNv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 138583 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 138586 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 138590 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138595 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 138599 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 138601 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 138604 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 138608 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138613 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 138616 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 138618 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 138621 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 138625 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138630 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 138636 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138641 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138646 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 138649 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 138653 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138658 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 138661 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 138663 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 138666 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTNv4f32),
     /* 138670 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138675 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 138678 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 138680 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 138683 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 138687 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138692 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 138695 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 138697 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 138700 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 138704 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138709 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 138711 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 138714 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 138718 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 138723 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 138726 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 138729 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 138732 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138737 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 138742 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 138747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 138750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 138752 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 138755 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 138758 */     GIR_RootConstrainSelectedInstOperands,
     /* 138759 */     // GIR_Coverage, 7654,
     /* 138759 */     GIR_EraseRootFromParent_Done,
     /* 138760 */   // Label 2384: @138760
     /* 138760 */   GIM_Reject,
     /* 138761 */ // Label 2382: @138761
     /* 138761 */ GIM_Reject,
     /* 138762 */ // Label 2374: @138762
     /* 138762 */ GIM_Reject,
     /* 138763 */ // Label 21: @138763
     /* 138763 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(138795), // Rule ID 3998 //
     /* 138768 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 138771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 138775 */   // (readcyclecounter:{ *:[i64] })  =>  (MRS:{ *:[i64] }:{ *:[i32] } 57090:{ *:[i32] })
     /* 138775 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
     /* 138778 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 138780 */   GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(57090),
     /* 138790 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 138793 */   GIR_RootConstrainSelectedInstOperands,
     /* 138794 */   // GIR_Coverage, 3998,
     /* 138794 */   GIR_EraseRootFromParent_Done,
     /* 138795 */ // Label 2385: @138795
     /* 138795 */ GIM_Reject,
     /* 138796 */ // Label 22: @138796
     /* 138796 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 2406*/ GIMT_Encode4(147613),
     /* 138807 */ /*GILLT_s8*//*Label 2386*/ GIMT_Encode4(138903),
     /* 138811 */ /*GILLT_s16*//*Label 2387*/ GIMT_Encode4(139079),
     /* 138815 */ /*GILLT_s32*//*Label 2388*/ GIMT_Encode4(139255),
     /* 138819 */ /*GILLT_s64*//*Label 2389*/ GIMT_Encode4(141529),
     /* 138823 */ /*GILLT_s128*//*Label 2390*/ GIMT_Encode4(144242),
     /* 138827 */ /*GILLT_v2s32*//*Label 2391*/ GIMT_Encode4(144451),
     /* 138831 */ /*GILLT_v2s64*//*Label 2392*/ GIMT_Encode4(144829),
     /* 138835 */ /*GILLT_v4s16*//*Label 2393*/ GIMT_Encode4(145207),
     /* 138839 */ /*GILLT_v4s32*//*Label 2394*/ GIMT_Encode4(145585),
     /* 138843 */ /*GILLT_v8s8*//*Label 2395*/ GIMT_Encode4(145963),
     /* 138847 */ /*GILLT_v8s16*//*Label 2396*/ GIMT_Encode4(146171),
     /* 138851 */ /*GILLT_v16s8*//*Label 2397*/ GIMT_Encode4(146549), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 138863 */ /*GILLT_nxv2s16*//*Label 2398*/ GIMT_Encode4(146757),
     /* 138867 */ /*GILLT_nxv2s32*//*Label 2399*/ GIMT_Encode4(146821),
     /* 138871 */ /*GILLT_nxv2s64*//*Label 2400*/ GIMT_Encode4(146885), GIMT_Encode4(0),
     /* 138879 */ /*GILLT_nxv4s16*//*Label 2401*/ GIMT_Encode4(147059),
     /* 138883 */ /*GILLT_nxv4s32*//*Label 2402*/ GIMT_Encode4(147123), GIMT_Encode4(0),
     /* 138891 */ /*GILLT_nxv8s16*//*Label 2403*/ GIMT_Encode4(147297),
     /* 138895 */ /*GILLT_nxv16s1*//*Label 2404*/ GIMT_Encode4(147471),
     /* 138899 */ /*GILLT_nxv16s8*//*Label 2405*/ GIMT_Encode4(147515),
     /* 138903 */ // Label 2386: @138903
     /* 138903 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(139078),
     /* 138908 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 138911 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 138915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 138919 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 138923 */   GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(138964), // Rule ID 231 //
     /* 138928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 138931 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 138938 */     // (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 138938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 138941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 138943 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138948 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 138962 */     GIR_RootConstrainSelectedInstOperands,
     /* 138963 */     // GIR_Coverage, 231,
     /* 138963 */     GIR_EraseRootFromParent_Done,
     /* 138964 */   // Label 2408: @138964
     /* 138964 */   GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(139005), // Rule ID 232 //
     /* 138969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 138972 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 138979 */     // (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 138979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 138982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 138984 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 138989 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 138994 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 138999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139003 */     GIR_RootConstrainSelectedInstOperands,
     /* 139004 */     // GIR_Coverage, 232,
     /* 139004 */     GIR_EraseRootFromParent_Done,
     /* 139005 */   // Label 2409: @139005
     /* 139005 */   GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(139041), // Rule ID 255 //
     /* 139010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 139020 */     // (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 139020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 139023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139039 */     GIR_RootConstrainSelectedInstOperands,
     /* 139040 */     // GIR_Coverage, 255,
     /* 139040 */     GIR_EraseRootFromParent_Done,
     /* 139041 */   // Label 2410: @139041
     /* 139041 */   GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(139077), // Rule ID 276 //
     /* 139046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139049 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 139056 */     // (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 139056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 139059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139071 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139075 */     GIR_RootConstrainSelectedInstOperands,
     /* 139076 */     // GIR_Coverage, 276,
     /* 139076 */     GIR_EraseRootFromParent_Done,
     /* 139077 */   // Label 2411: @139077
     /* 139077 */   GIM_Reject,
     /* 139078 */ // Label 2407: @139078
     /* 139078 */ GIM_Reject,
     /* 139079 */ // Label 2387: @139079
     /* 139079 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(139254),
     /* 139084 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139087 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 139095 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139099 */   GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(139140), // Rule ID 233 //
     /* 139104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139107 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 139114 */     // (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHroW:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 139114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 139117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139134 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139138 */     GIR_RootConstrainSelectedInstOperands,
     /* 139139 */     // GIR_Coverage, 233,
     /* 139139 */     GIR_EraseRootFromParent_Done,
     /* 139140 */   // Label 2413: @139140
     /* 139140 */   GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(139181), // Rule ID 234 //
     /* 139145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139148 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 139155 */     // (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHroX:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 139155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 139158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139160 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139175 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139179 */     GIR_RootConstrainSelectedInstOperands,
     /* 139180 */     // GIR_Coverage, 234,
     /* 139180 */     GIR_EraseRootFromParent_Done,
     /* 139181 */   // Label 2414: @139181
     /* 139181 */   GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(139217), // Rule ID 256 //
     /* 139186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139189 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 139196 */     // (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRHui:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 139196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 139199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139201 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139206 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139215 */     GIR_RootConstrainSelectedInstOperands,
     /* 139216 */     // GIR_Coverage, 256,
     /* 139216 */     GIR_EraseRootFromParent_Done,
     /* 139217 */   // Label 2415: @139217
     /* 139217 */   GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(139253), // Rule ID 277 //
     /* 139222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139225 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 139232 */     // (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURHi:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 139232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 139235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139251 */     GIR_RootConstrainSelectedInstOperands,
     /* 139252 */     // GIR_Coverage, 277,
     /* 139252 */     GIR_EraseRootFromParent_Done,
     /* 139253 */   // Label 2416: @139253
     /* 139253 */   GIM_Reject,
     /* 139254 */ // Label 2412: @139254
     /* 139254 */ GIM_Reject,
     /* 139255 */ // Label 2388: @139255
     /* 139255 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(139308), // Rule ID 227 //
     /* 139260 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139263 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139267 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139271 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139275 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 139282 */   // (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 139282 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 139285 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139292 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139297 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139302 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139306 */   GIR_RootConstrainSelectedInstOperands,
     /* 139307 */   // GIR_Coverage, 227,
     /* 139307 */   GIR_EraseRootFromParent_Done,
     /* 139308 */ // Label 2417: @139308
     /* 139308 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(139361), // Rule ID 228 //
     /* 139313 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139316 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139324 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139328 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 139335 */   // (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 139335 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 139338 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139345 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139350 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139355 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139359 */   GIR_RootConstrainSelectedInstOperands,
     /* 139360 */   // GIR_Coverage, 228,
     /* 139360 */   GIR_EraseRootFromParent_Done,
     /* 139361 */ // Label 2418: @139361
     /* 139361 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(139417), // Rule ID 235 //
     /* 139366 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139369 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139372 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139376 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 139380 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139384 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 139391 */   // (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSroW:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 139391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 139394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139396 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139401 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139406 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139411 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139415 */   GIR_RootConstrainSelectedInstOperands,
     /* 139416 */   // GIR_Coverage, 235,
     /* 139416 */   GIR_EraseRootFromParent_Done,
     /* 139417 */ // Label 2419: @139417
     /* 139417 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(139473), // Rule ID 236 //
     /* 139422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139425 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139428 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 139436 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 139447 */   // (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSroX:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 139447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 139450 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139462 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139467 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139471 */   GIR_RootConstrainSelectedInstOperands,
     /* 139472 */   // GIR_Coverage, 236,
     /* 139472 */   GIR_EraseRootFromParent_Done,
     /* 139473 */ // Label 2420: @139473
     /* 139473 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(139533), // Rule ID 4216 //
     /* 139478 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139481 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139485 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139496 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139500 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 139507 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 139507 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 139510 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139512 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139517 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139522 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139527 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139531 */   GIR_RootConstrainSelectedInstOperands,
     /* 139532 */   // GIR_Coverage, 4216,
     /* 139532 */   GIR_EraseRootFromParent_Done,
     /* 139533 */ // Label 2421: @139533
     /* 139533 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(139593), // Rule ID 4217 //
     /* 139538 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139541 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139545 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139556 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139560 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 139567 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 139567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 139570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139572 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139577 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139582 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139587 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139591 */   GIR_RootConstrainSelectedInstOperands,
     /* 139592 */   // GIR_Coverage, 4217,
     /* 139592 */   GIR_EraseRootFromParent_Done,
     /* 139593 */ // Label 2422: @139593
     /* 139593 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(139653), // Rule ID 4218 //
     /* 139598 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139601 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139605 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 139612 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139616 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139620 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 139627 */   // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 139627 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 139630 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139642 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139647 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139651 */   GIR_RootConstrainSelectedInstOperands,
     /* 139652 */   // GIR_Coverage, 4218,
     /* 139652 */   GIR_EraseRootFromParent_Done,
     /* 139653 */ // Label 2423: @139653
     /* 139653 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(139713), // Rule ID 4219 //
     /* 139658 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139661 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139665 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 139672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139676 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139680 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 139687 */   // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 139687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 139690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139702 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139707 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139711 */   GIR_RootConstrainSelectedInstOperands,
     /* 139712 */   // GIR_Coverage, 4219,
     /* 139712 */   GIR_EraseRootFromParent_Done,
     /* 139713 */ // Label 2424: @139713
     /* 139713 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(139761), // Rule ID 254 //
     /* 139718 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139721 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139729 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139733 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 139740 */   // (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 139740 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 139743 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139745 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139750 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139755 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139759 */   GIR_RootConstrainSelectedInstOperands,
     /* 139760 */   // GIR_Coverage, 254,
     /* 139760 */   GIR_EraseRootFromParent_Done,
     /* 139761 */ // Label 2425: @139761
     /* 139761 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(139812), // Rule ID 257 //
     /* 139766 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 139769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 139772 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 139780 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139784 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 139791 */   // (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRSui:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 139791 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 139794 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 139806 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139810 */   GIR_RootConstrainSelectedInstOperands,
     /* 139811 */   // GIR_Coverage, 257,
     /* 139811 */   GIR_EraseRootFromParent_Done,
     /* 139812 */ // Label 2426: @139812
     /* 139812 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(139875), // Rule ID 7686 //
     /* 139817 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139820 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139824 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139831 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 139834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139838 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139842 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 139849 */   // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
     /* 139849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 139852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139854 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139859 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139864 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 139869 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139873 */   GIR_RootConstrainSelectedInstOperands,
     /* 139874 */   // GIR_Coverage, 7686,
     /* 139874 */   GIR_EraseRootFromParent_Done,
     /* 139875 */ // Label 2427: @139875
     /* 139875 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(139938), // Rule ID 7688 //
     /* 139880 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139883 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139887 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 139894 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 139897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139901 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139905 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 139912 */   // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
     /* 139912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 139915 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139917 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139922 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139927 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 139932 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139936 */   GIR_RootConstrainSelectedInstOperands,
     /* 139937 */   // GIR_Coverage, 7688,
     /* 139937 */   GIR_EraseRootFromParent_Done,
     /* 139938 */ // Label 2428: @139938
     /* 139938 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(140001), // Rule ID 7698 //
     /* 139943 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 139946 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 139950 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 139957 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 139960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 139964 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 139968 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 139975 */   // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 139975 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 139978 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 139980 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 139985 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 139990 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 139995 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 139999 */   GIR_RootConstrainSelectedInstOperands,
     /* 140000 */   // GIR_Coverage, 7698,
     /* 140000 */   GIR_EraseRootFromParent_Done,
     /* 140001 */ // Label 2429: @140001
     /* 140001 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(140064), // Rule ID 7700 //
     /* 140006 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140009 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140013 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140020 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140027 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140031 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 140038 */   // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 140038 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 140041 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140043 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140048 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140053 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140058 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140062 */   GIR_RootConstrainSelectedInstOperands,
     /* 140063 */   // GIR_Coverage, 7700,
     /* 140063 */   GIR_EraseRootFromParent_Done,
     /* 140064 */ // Label 2430: @140064
     /* 140064 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(140127), // Rule ID 7708 //
     /* 140069 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140072 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140076 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140083 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140090 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140094 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 140101 */   // (atomic_load:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>  =>  (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 140101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 140104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140106 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140111 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140116 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140121 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140125 */   GIR_RootConstrainSelectedInstOperands,
     /* 140126 */   // GIR_Coverage, 7708,
     /* 140126 */   GIR_EraseRootFromParent_Done,
     /* 140127 */ // Label 2431: @140127
     /* 140127 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(140190), // Rule ID 7709 //
     /* 140132 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140135 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140139 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140146 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140153 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140157 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 140164 */   // (atomic_load:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>  =>  (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 140164 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 140167 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140174 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 140179 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 140184 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140188 */   GIR_RootConstrainSelectedInstOperands,
     /* 140189 */   // GIR_Coverage, 7709,
     /* 140189 */   GIR_EraseRootFromParent_Done,
     /* 140190 */ // Label 2432: @140190
     /* 140190 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(140238), // Rule ID 275 //
     /* 140195 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140198 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140210 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 140217 */   // (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 140217 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 140220 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140222 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140227 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140232 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140236 */   GIR_RootConstrainSelectedInstOperands,
     /* 140237 */   // GIR_Coverage, 275,
     /* 140237 */   GIR_EraseRootFromParent_Done,
     /* 140238 */ // Label 2433: @140238
     /* 140238 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(140289), // Rule ID 278 //
     /* 140243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 140246 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140249 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 140257 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140261 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 140268 */   // (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURSi:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 140268 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 140271 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140283 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140287 */   GIR_RootConstrainSelectedInstOperands,
     /* 140288 */   // GIR_Coverage, 278,
     /* 140288 */   GIR_EraseRootFromParent_Done,
     /* 140289 */ // Label 2434: @140289
     /* 140289 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(140344), // Rule ID 4241 //
     /* 140294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140297 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140301 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140312 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140316 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 140323 */   // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 140323 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 140326 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140328 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140333 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140338 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140342 */   GIR_RootConstrainSelectedInstOperands,
     /* 140343 */   // GIR_Coverage, 4241,
     /* 140343 */   GIR_EraseRootFromParent_Done,
     /* 140344 */ // Label 2435: @140344
     /* 140344 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(140399), // Rule ID 4242 //
     /* 140349 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140352 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140356 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140367 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140371 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 140378 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 140378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 140381 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140388 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140393 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140397 */   GIR_RootConstrainSelectedInstOperands,
     /* 140398 */   // GIR_Coverage, 4242,
     /* 140398 */   GIR_EraseRootFromParent_Done,
     /* 140399 */ // Label 2436: @140399
     /* 140399 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(140454), // Rule ID 4243 //
     /* 140404 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140407 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140411 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140422 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140426 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 140433 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 140433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 140436 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140448 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140452 */   GIR_RootConstrainSelectedInstOperands,
     /* 140453 */   // GIR_Coverage, 4243,
     /* 140453 */   GIR_EraseRootFromParent_Done,
     /* 140454 */ // Label 2437: @140454
     /* 140454 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(140509), // Rule ID 4264 //
     /* 140459 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140462 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140466 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140473 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140477 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140481 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 140488 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140488 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 140491 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140493 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140498 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140503 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140507 */   GIR_RootConstrainSelectedInstOperands,
     /* 140508 */   // GIR_Coverage, 4264,
     /* 140508 */   GIR_EraseRootFromParent_Done,
     /* 140509 */ // Label 2438: @140509
     /* 140509 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(140564), // Rule ID 4265 //
     /* 140514 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140517 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140521 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140532 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140536 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 140543 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 140546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140558 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140562 */   GIR_RootConstrainSelectedInstOperands,
     /* 140563 */   // GIR_Coverage, 4265,
     /* 140563 */   GIR_EraseRootFromParent_Done,
     /* 140564 */ // Label 2439: @140564
     /* 140564 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(140619), // Rule ID 4266 //
     /* 140569 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 140572 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140576 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140587 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140591 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 140598 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140598 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 140601 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140608 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140613 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140617 */   GIR_RootConstrainSelectedInstOperands,
     /* 140618 */   // GIR_Coverage, 4266,
     /* 140618 */   GIR_EraseRootFromParent_Done,
     /* 140619 */ // Label 2440: @140619
     /* 140619 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(140677), // Rule ID 7690 //
     /* 140624 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140627 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140631 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140638 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140645 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 140656 */   // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 140656 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 140659 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140661 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140666 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140671 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140675 */   GIR_RootConstrainSelectedInstOperands,
     /* 140676 */   // GIR_Coverage, 7690,
     /* 140676 */   GIR_EraseRootFromParent_Done,
     /* 140677 */ // Label 2441: @140677
     /* 140677 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(140735), // Rule ID 7692 //
     /* 140682 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140685 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140689 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140696 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140703 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140707 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 140714 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22263>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 140717 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140719 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140724 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140729 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140733 */   GIR_RootConstrainSelectedInstOperands,
     /* 140734 */   // GIR_Coverage, 7692,
     /* 140734 */   GIR_EraseRootFromParent_Done,
     /* 140735 */ // Label 2442: @140735
     /* 140735 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(140793), // Rule ID 7702 //
     /* 140740 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140743 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140754 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140761 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140765 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 140772 */   // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 140772 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 140775 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140777 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140782 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140787 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140791 */   GIR_RootConstrainSelectedInstOperands,
     /* 140792 */   // GIR_Coverage, 7702,
     /* 140792 */   GIR_EraseRootFromParent_Done,
     /* 140793 */ // Label 2443: @140793
     /* 140793 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(140851), // Rule ID 7704 //
     /* 140798 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140801 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140805 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 140812 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140819 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140823 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 140830 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22271>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140830 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 140833 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140849 */   GIR_RootConstrainSelectedInstOperands,
     /* 140850 */   // GIR_Coverage, 7704,
     /* 140850 */   GIR_EraseRootFromParent_Done,
     /* 140851 */ // Label 2444: @140851
     /* 140851 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(140909), // Rule ID 7710 //
     /* 140856 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140859 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140863 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140870 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140877 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140881 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 140888 */   // (atomic_load:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>  =>  (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 140888 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 140891 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140907 */   GIR_RootConstrainSelectedInstOperands,
     /* 140908 */   // GIR_Coverage, 7710,
     /* 140908 */   GIR_EraseRootFromParent_Done,
     /* 140909 */ // Label 2445: @140909
     /* 140909 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(140967), // Rule ID 7711 //
     /* 140914 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140917 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140921 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 140928 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140935 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 140939 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 140946 */   // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22279>>  =>  (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 140946 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 140949 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 140951 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 140956 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 140961 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 140965 */   GIR_RootConstrainSelectedInstOperands,
     /* 140966 */   // GIR_Coverage, 7711,
     /* 140966 */   GIR_EraseRootFromParent_Done,
     /* 140967 */ // Label 2446: @140967
     /* 140967 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(141028), // Rule ID 8096 //
     /* 140972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 140975 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 140978 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 140982 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 140989 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 140992 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 140996 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141000 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 141007 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22252>>  =>  (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 141007 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
     /* 141010 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141017 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141022 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141026 */   GIR_RootConstrainSelectedInstOperands,
     /* 141027 */   // GIR_Coverage, 8096,
     /* 141027 */   GIR_EraseRootFromParent_Done,
     /* 141028 */ // Label 2447: @141028
     /* 141028 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(141089), // Rule ID 8098 //
     /* 141033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 141036 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141039 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141043 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 141050 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141057 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141061 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 141068 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22254>>  =>  (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 141068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
     /* 141071 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141078 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141083 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141087 */   GIR_RootConstrainSelectedInstOperands,
     /* 141088 */   // GIR_Coverage, 8098,
     /* 141088 */   GIR_EraseRootFromParent_Done,
     /* 141089 */ // Label 2448: @141089
     /* 141089 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(141150), // Rule ID 8100 //
     /* 141094 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 141097 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141100 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 141111 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141118 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141122 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 141129 */   // (atomic_load:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22256>>  =>  (LDAPURi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 141129 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURi),
     /* 141132 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141134 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141139 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 141144 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141148 */   GIR_RootConstrainSelectedInstOperands,
     /* 141149 */   // GIR_Coverage, 8100,
     /* 141149 */   GIR_EraseRootFromParent_Done,
     /* 141150 */ // Label 2449: @141150
     /* 141150 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(141194), // Rule ID 7676 //
     /* 141155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 141158 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141161 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141165 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 141172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141175 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141179 */   // MIs[0] ptr
     /* 141179 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141183 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141187 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22252>>  =>  (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141187 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRB),
     /* 141192 */   GIR_RootConstrainSelectedInstOperands,
     /* 141193 */   // GIR_Coverage, 7676,
     /* 141193 */   GIR_Done,
     /* 141194 */ // Label 2450: @141194
     /* 141194 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(141238), // Rule ID 7678 //
     /* 141199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 141202 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141205 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141209 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 141216 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141223 */   // MIs[0] ptr
     /* 141223 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141227 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141231 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22254>>  =>  (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141231 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRH),
     /* 141236 */   GIR_RootConstrainSelectedInstOperands,
     /* 141237 */   // GIR_Coverage, 7678,
     /* 141237 */   GIR_Done,
     /* 141238 */ // Label 2451: @141238
     /* 141238 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(141282), // Rule ID 7680 //
     /* 141243 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 141246 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141249 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141253 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 141260 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141263 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141267 */   // MIs[0] ptr
     /* 141267 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141271 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141275 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22256>>  =>  (LDAPRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141275 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRW),
     /* 141280 */   GIR_RootConstrainSelectedInstOperands,
     /* 141281 */   // GIR_Coverage, 7680,
     /* 141281 */   GIR_Done,
     /* 141282 */ // Label 2452: @141282
     /* 141282 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(141323), // Rule ID 7682 //
     /* 141287 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141290 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141294 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 141301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 141304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141308 */   // MIs[0] ptr
     /* 141308 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141312 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141316 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22260>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141316 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 141321 */   GIR_RootConstrainSelectedInstOperands,
     /* 141322 */   // GIR_Coverage, 7682,
     /* 141322 */   GIR_Done,
     /* 141323 */ // Label 2453: @141323
     /* 141323 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(141364), // Rule ID 7684 //
     /* 141328 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141331 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141335 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 141342 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141349 */   // MIs[0] ptr
     /* 141349 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141353 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141357 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_8>><<P:Predicate_anonymous_22252>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141357 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 141362 */   GIR_RootConstrainSelectedInstOperands,
     /* 141363 */   // GIR_Coverage, 7684,
     /* 141363 */   GIR_Done,
     /* 141364 */ // Label 2454: @141364
     /* 141364 */ GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(141405), // Rule ID 7694 //
     /* 141369 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141372 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141376 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 141383 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 141386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141390 */   // MIs[0] ptr
     /* 141390 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141394 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141398 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22268>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141398 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 141403 */   GIR_RootConstrainSelectedInstOperands,
     /* 141404 */   // GIR_Coverage, 7694,
     /* 141404 */   GIR_Done,
     /* 141405 */ // Label 2455: @141405
     /* 141405 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(141446), // Rule ID 7696 //
     /* 141410 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141413 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141417 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 141424 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141431 */   // MIs[0] ptr
     /* 141431 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141435 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141439 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_aext>><<P:Predicate_atomic_load_aext_16>><<P:Predicate_anonymous_22254>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141439 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 141444 */   GIR_RootConstrainSelectedInstOperands,
     /* 141445 */   // GIR_Coverage, 7696,
     /* 141445 */   GIR_Done,
     /* 141446 */ // Label 2456: @141446
     /* 141446 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(141487), // Rule ID 7706 //
     /* 141451 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141454 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141458 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 141465 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 141468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141472 */   // MIs[0] ptr
     /* 141472 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141476 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141480 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22276>>  =>  (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141480 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
     /* 141485 */   GIR_RootConstrainSelectedInstOperands,
     /* 141486 */   // GIR_Coverage, 7706,
     /* 141486 */   GIR_Done,
     /* 141487 */ // Label 2457: @141487
     /* 141487 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(141528), // Rule ID 7707 //
     /* 141492 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 141495 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141499 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 141506 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 141509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 141513 */   // MIs[0] ptr
     /* 141513 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 141517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 141521 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_32>><<P:Predicate_anonymous_22256>>  =>  (LDARW:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 141521 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARW),
     /* 141526 */   GIR_RootConstrainSelectedInstOperands,
     /* 141527 */   // GIR_Coverage, 7707,
     /* 141527 */   GIR_Done,
     /* 141528 */ // Label 2458: @141528
     /* 141528 */ GIM_Reject,
     /* 141529 */ // Label 2389: @141529
     /* 141529 */ GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(141582), // Rule ID 229 //
     /* 141534 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141537 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141541 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141545 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141549 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141556 */   // (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141556 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
     /* 141559 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141561 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141566 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141571 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141576 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141580 */   GIR_RootConstrainSelectedInstOperands,
     /* 141581 */   // GIR_Coverage, 229,
     /* 141581 */   GIR_EraseRootFromParent_Done,
     /* 141582 */ // Label 2459: @141582
     /* 141582 */ GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(141635), // Rule ID 230 //
     /* 141587 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141590 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 141598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141609 */   // (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
     /* 141612 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141624 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141629 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141633 */   GIR_RootConstrainSelectedInstOperands,
     /* 141634 */   // GIR_Coverage, 230,
     /* 141634 */   GIR_EraseRootFromParent_Done,
     /* 141635 */ // Label 2460: @141635
     /* 141635 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(141691), // Rule ID 237 //
     /* 141640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 141643 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141646 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141650 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141654 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141658 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141665 */   // (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 141668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141670 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141675 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141680 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141685 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141689 */   GIR_RootConstrainSelectedInstOperands,
     /* 141690 */   // GIR_Coverage, 237,
     /* 141690 */   GIR_EraseRootFromParent_Done,
     /* 141691 */ // Label 2461: @141691
     /* 141691 */ GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(141747), // Rule ID 238 //
     /* 141696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 141699 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141702 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141710 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141714 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141721 */   // (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 141724 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141726 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141745 */   GIR_RootConstrainSelectedInstOperands,
     /* 141746 */   // GIR_Coverage, 238,
     /* 141746 */   GIR_EraseRootFromParent_Done,
     /* 141747 */ // Label 2462: @141747
     /* 141747 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(141800), // Rule ID 4182 //
     /* 141752 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141755 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141774 */   // (ld:{ *:[v1i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 141777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141789 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141794 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141798 */   GIR_RootConstrainSelectedInstOperands,
     /* 141799 */   // GIR_Coverage, 4182,
     /* 141799 */   GIR_EraseRootFromParent_Done,
     /* 141800 */ // Label 2463: @141800
     /* 141800 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(141853), // Rule ID 4183 //
     /* 141805 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141808 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141812 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141816 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141820 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141827 */   // (ld:{ *:[v1i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 141830 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141842 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141847 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141851 */   GIR_RootConstrainSelectedInstOperands,
     /* 141852 */   // GIR_Coverage, 4183,
     /* 141852 */   GIR_EraseRootFromParent_Done,
     /* 141853 */ // Label 2464: @141853
     /* 141853 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(141906), // Rule ID 4184 //
     /* 141858 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141861 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141865 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141869 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141873 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 141880 */   // (ld:{ *:[v1f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 141880 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 141883 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141885 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141890 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141895 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141900 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141904 */   GIR_RootConstrainSelectedInstOperands,
     /* 141905 */   // GIR_Coverage, 4184,
     /* 141905 */   GIR_EraseRootFromParent_Done,
     /* 141906 */ // Label 2465: @141906
     /* 141906 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(141959), // Rule ID 4185 //
     /* 141911 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141914 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 141922 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141926 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 141933 */   // (ld:{ *:[v1f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 141933 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 141936 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 141938 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 141943 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 141948 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 141953 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 141957 */   GIR_RootConstrainSelectedInstOperands,
     /* 141958 */   // GIR_Coverage, 4185,
     /* 141958 */   GIR_EraseRootFromParent_Done,
     /* 141959 */ // Label 2466: @141959
     /* 141959 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(142051), // Rule ID 4208 //
     /* 141964 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 141967 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 141971 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 141978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 141982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 141986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 141993 */   // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 141993 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 141996 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 142000 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142005 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142010 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142015 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142020 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142024 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142029 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142031 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142034 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142037 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142040 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142045 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142050 */   // GIR_Coverage, 4208,
     /* 142050 */   GIR_EraseRootFromParent_Done,
     /* 142051 */ // Label 2467: @142051
     /* 142051 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(142143), // Rule ID 4209 //
     /* 142056 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142059 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142063 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 142070 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142074 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142078 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 142085 */   // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142085 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142088 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 142092 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142102 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142107 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142112 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142116 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142118 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142121 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142123 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142126 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142129 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142132 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142137 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142142 */   // GIR_Coverage, 4209,
     /* 142142 */   GIR_EraseRootFromParent_Done,
     /* 142143 */ // Label 2468: @142143
     /* 142143 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(142235), // Rule ID 4210 //
     /* 142148 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142151 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142155 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 142162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142166 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 142177 */   // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142177 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142180 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 142184 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142204 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142208 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142215 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142218 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142221 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142224 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142229 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142234 */   // GIR_Coverage, 4210,
     /* 142234 */   GIR_EraseRootFromParent_Done,
     /* 142235 */ // Label 2469: @142235
     /* 142235 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(142327), // Rule ID 4211 //
     /* 142240 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142243 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142247 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 142254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142258 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142262 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 142269 */   // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142269 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142272 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 142276 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142281 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142286 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142291 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142296 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142300 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142302 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142305 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142307 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142310 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142313 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142316 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142321 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142326 */   // GIR_Coverage, 4211,
     /* 142326 */   GIR_EraseRootFromParent_Done,
     /* 142327 */ // Label 2470: @142327
     /* 142327 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(142419), // Rule ID 4212 //
     /* 142332 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142335 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142339 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 142346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142350 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142354 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 142361 */   // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142361 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142364 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 142368 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142373 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142378 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142383 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142388 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142392 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142394 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142397 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142399 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142402 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142405 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142408 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142413 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142418 */   // GIR_Coverage, 4212,
     /* 142418 */   GIR_EraseRootFromParent_Done,
     /* 142419 */ // Label 2471: @142419
     /* 142419 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(142511), // Rule ID 4213 //
     /* 142424 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142427 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142431 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 142438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142442 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142446 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 142453 */   // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142453 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142456 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 142460 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142465 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142470 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142480 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142484 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142489 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142491 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142494 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142497 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142500 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142505 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142510 */   // GIR_Coverage, 4213,
     /* 142510 */   GIR_EraseRootFromParent_Done,
     /* 142511 */ // Label 2472: @142511
     /* 142511 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(142603), // Rule ID 4214 //
     /* 142516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142519 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142523 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 142530 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142534 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142538 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 142545 */   // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142545 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142548 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 142552 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142567 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142572 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142576 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142578 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142581 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142583 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142586 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142589 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142592 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142597 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142602 */   // GIR_Coverage, 4214,
     /* 142602 */   GIR_EraseRootFromParent_Done,
     /* 142603 */ // Label 2473: @142603
     /* 142603 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(142695), // Rule ID 4215 //
     /* 142608 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142611 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142615 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 142622 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142626 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142630 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 142637 */   // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 142637 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 142640 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 142644 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 142649 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142654 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142659 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142664 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142668 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 142670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 142673 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 142675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 142678 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 142681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 142684 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 142689 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 142694 */   // GIR_Coverage, 4215,
     /* 142694 */   GIR_EraseRootFromParent_Done,
     /* 142695 */ // Label 2474: @142695
     /* 142695 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(142743), // Rule ID 253 //
     /* 142700 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142703 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142707 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142711 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142715 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 142722 */   // (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 142722 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
     /* 142725 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 142727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142741 */   GIR_RootConstrainSelectedInstOperands,
     /* 142742 */   // GIR_Coverage, 253,
     /* 142742 */   GIR_EraseRootFromParent_Done,
     /* 142743 */ // Label 2475: @142743
     /* 142743 */ GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(142794), // Rule ID 258 //
     /* 142748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 142751 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142754 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142758 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142762 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142766 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 142773 */   // (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 142773 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 142776 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 142778 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142788 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142792 */   GIR_RootConstrainSelectedInstOperands,
     /* 142793 */   // GIR_Coverage, 258,
     /* 142793 */   GIR_EraseRootFromParent_Done,
     /* 142794 */ // Label 2476: @142794
     /* 142794 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(142857), // Rule ID 7714 //
     /* 142799 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142802 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142806 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142813 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 142816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142820 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142824 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 142831 */   // (atomic_load:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>  =>  (LDRXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 142831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroW),
     /* 142834 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 142836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142855 */   GIR_RootConstrainSelectedInstOperands,
     /* 142856 */   // GIR_Coverage, 7714,
     /* 142856 */   GIR_EraseRootFromParent_Done,
     /* 142857 */ // Label 2477: @142857
     /* 142857 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(142920), // Rule ID 7715 //
     /* 142862 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 142865 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142869 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 142876 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 142879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142883 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142887 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 142894 */   // (atomic_load:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>  =>  (LDRXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 142894 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXroX),
     /* 142897 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 142899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 142909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 142914 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142918 */   GIR_RootConstrainSelectedInstOperands,
     /* 142919 */   // GIR_Coverage, 7715,
     /* 142919 */   GIR_EraseRootFromParent_Done,
     /* 142920 */ // Label 2478: @142920
     /* 142920 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(142968), // Rule ID 274 //
     /* 142925 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142928 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 142936 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142940 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142947 */   // (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 142947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
     /* 142950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 142952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 142957 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 142962 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 142966 */   GIR_RootConstrainSelectedInstOperands,
     /* 142967 */   // GIR_Coverage, 274,
     /* 142967 */   GIR_EraseRootFromParent_Done,
     /* 142968 */ // Label 2479: @142968
     /* 142968 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(143019), // Rule ID 279 //
     /* 142973 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 142976 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 142979 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 142983 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 142987 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 142991 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 142998 */   // (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 142998 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 143001 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143013 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143017 */   GIR_RootConstrainSelectedInstOperands,
     /* 143018 */   // GIR_Coverage, 279,
     /* 143018 */   GIR_EraseRootFromParent_Done,
     /* 143019 */ // Label 2480: @143019
     /* 143019 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(143067), // Rule ID 4227 //
     /* 143024 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143027 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143035 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143039 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 143046 */   // (ld:{ *:[v1f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 143046 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 143049 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143061 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143065 */   GIR_RootConstrainSelectedInstOperands,
     /* 143066 */   // GIR_Coverage, 4227,
     /* 143066 */   GIR_EraseRootFromParent_Done,
     /* 143067 */ // Label 2481: @143067
     /* 143067 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(143115), // Rule ID 4228 //
     /* 143072 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143075 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143083 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143087 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 143094 */   // (ld:{ *:[v1i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 143094 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 143097 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143099 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143109 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143113 */   GIR_RootConstrainSelectedInstOperands,
     /* 143114 */   // GIR_Coverage, 4228,
     /* 143114 */   GIR_EraseRootFromParent_Done,
     /* 143115 */ // Label 2482: @143115
     /* 143115 */ GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(143202), // Rule ID 4244 //
     /* 143120 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143123 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143127 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 143134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143138 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143142 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 143149 */   // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 143149 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143152 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 143156 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143161 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143171 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143175 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143177 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143180 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143182 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143185 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143191 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143196 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143201 */   // GIR_Coverage, 4244,
     /* 143201 */   GIR_EraseRootFromParent_Done,
     /* 143202 */ // Label 2483: @143202
     /* 143202 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(143289), // Rule ID 4245 //
     /* 143207 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143210 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143214 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 143221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143225 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143229 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 143236 */   // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 143236 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143239 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 143243 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143248 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143253 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143258 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143262 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143264 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143267 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143269 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143272 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143275 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143278 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143283 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143288 */   // GIR_Coverage, 4245,
     /* 143288 */   GIR_EraseRootFromParent_Done,
     /* 143289 */ // Label 2484: @143289
     /* 143289 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(143376), // Rule ID 4246 //
     /* 143294 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143297 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143301 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 143308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143312 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143316 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 143323 */   // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 143323 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143326 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 143330 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143335 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143340 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143345 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143349 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143354 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143356 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143359 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143362 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143365 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143370 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143375 */   // GIR_Coverage, 4246,
     /* 143375 */   GIR_EraseRootFromParent_Done,
     /* 143376 */ // Label 2485: @143376
     /* 143376 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(143463), // Rule ID 4247 //
     /* 143381 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143384 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143388 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 143395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143399 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143403 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 143410 */   // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 143410 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143413 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 143417 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143432 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143436 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143441 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143443 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143446 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143449 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143452 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143457 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143462 */   // GIR_Coverage, 4247,
     /* 143462 */   GIR_EraseRootFromParent_Done,
     /* 143463 */ // Label 2486: @143463
     /* 143463 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(143511), // Rule ID 4255 //
     /* 143468 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143471 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143479 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143483 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 143490 */   // (ld:{ *:[v1f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 143490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 143493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143495 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143500 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143505 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143509 */   GIR_RootConstrainSelectedInstOperands,
     /* 143510 */   // GIR_Coverage, 4255,
     /* 143510 */   GIR_EraseRootFromParent_Done,
     /* 143511 */ // Label 2487: @143511
     /* 143511 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(143559), // Rule ID 4256 //
     /* 143516 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143519 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 143527 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143531 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 143538 */   // (ld:{ *:[v1i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 143538 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 143541 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143543 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143548 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143553 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143557 */   GIR_RootConstrainSelectedInstOperands,
     /* 143558 */   // GIR_Coverage, 4256,
     /* 143558 */   GIR_EraseRootFromParent_Done,
     /* 143559 */ // Label 2488: @143559
     /* 143559 */ GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(143646), // Rule ID 4267 //
     /* 143564 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143567 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143571 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 143578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143582 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143586 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 143593 */   // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 143593 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143596 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 143600 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143605 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143610 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143615 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143619 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143624 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143626 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143629 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143632 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143635 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143640 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143645 */   // GIR_Coverage, 4267,
     /* 143645 */   GIR_EraseRootFromParent_Done,
     /* 143646 */ // Label 2489: @143646
     /* 143646 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(143733), // Rule ID 4268 //
     /* 143651 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143654 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143658 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 143665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143669 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143673 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 143680 */   // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 143680 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143683 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 143687 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143692 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143697 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143702 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143706 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143708 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143711 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143713 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143716 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143719 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143722 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143727 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143732 */   // GIR_Coverage, 4268,
     /* 143732 */   GIR_EraseRootFromParent_Done,
     /* 143733 */ // Label 2490: @143733
     /* 143733 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(143820), // Rule ID 4269 //
     /* 143738 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143741 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143745 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 143752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143756 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143760 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 143767 */   // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 143767 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143770 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 143774 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143789 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143793 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143800 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143803 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143806 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143809 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143814 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143819 */   // GIR_Coverage, 4269,
     /* 143819 */   GIR_EraseRootFromParent_Done,
     /* 143820 */ // Label 2491: @143820
     /* 143820 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(143907), // Rule ID 4270 //
     /* 143825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 143828 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143832 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 143839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143843 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143847 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 143854 */   // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 143854 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 143857 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 143861 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 143866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143876 */   GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143880 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 143882 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 143885 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 143887 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 143890 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 143893 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 143896 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 143901 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 143906 */   // GIR_Coverage, 4270,
     /* 143906 */   GIR_EraseRootFromParent_Done,
     /* 143907 */ // Label 2492: @143907
     /* 143907 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(143965), // Rule ID 7716 //
     /* 143912 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 143915 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143919 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 143926 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 143929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 143933 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143937 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 143944 */   // (atomic_load:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>  =>  (LDRXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 143944 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRXui),
     /* 143947 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 143949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 143954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 143959 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 143963 */   GIR_RootConstrainSelectedInstOperands,
     /* 143964 */   // GIR_Coverage, 7716,
     /* 143964 */   GIR_EraseRootFromParent_Done,
     /* 143965 */ // Label 2493: @143965
     /* 143965 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(144023), // Rule ID 7717 //
     /* 143970 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 143973 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 143977 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 143984 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 143987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 143991 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 143995 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144002 */   // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22287>>  =>  (LDURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144002 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURXi),
     /* 144005 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144007 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144012 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144017 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144021 */   GIR_RootConstrainSelectedInstOperands,
     /* 144022 */   // GIR_Coverage, 7717,
     /* 144022 */   GIR_EraseRootFromParent_Done,
     /* 144023 */ // Label 2494: @144023
     /* 144023 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(144084), // Rule ID 8101 //
     /* 144028 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 144031 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 144034 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144038 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 144045 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 144048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 144052 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144056 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144063 */   // (atomic_load:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22258>>  =>  (LDAPURXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURXi),
     /* 144066 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144068 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144073 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144078 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144082 */   GIR_RootConstrainSelectedInstOperands,
     /* 144083 */   // GIR_Coverage, 8101,
     /* 144083 */   GIR_EraseRootFromParent_Done,
     /* 144084 */ // Label 2495: @144084
     /* 144084 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(144115), // Rule ID 7036 //
     /* 144089 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144092 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144100 */   // MIs[0] Rn
     /* 144100 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144104 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144108 */   // (ld:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 144108 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev1d),
     /* 144113 */   GIR_RootConstrainSelectedInstOperands,
     /* 144114 */   // GIR_Coverage, 7036,
     /* 144114 */   GIR_Done,
     /* 144115 */ // Label 2496: @144115
     /* 144115 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(144159), // Rule ID 7681 //
     /* 144120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 144123 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 144126 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144130 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 144137 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 144140 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 144144 */   // MIs[0] ptr
     /* 144144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144148 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144152 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22258>>  =>  (LDAPRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 144152 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRX),
     /* 144157 */   GIR_RootConstrainSelectedInstOperands,
     /* 144158 */   // GIR_Coverage, 7681,
     /* 144158 */   GIR_Done,
     /* 144159 */ // Label 2497: @144159
     /* 144159 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(144200), // Rule ID 7712 //
     /* 144164 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 144167 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144171 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 144178 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 144181 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 144185 */   // MIs[0] ptr
     /* 144185 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144189 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144193 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22284>>  =>  (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 144193 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
     /* 144198 */   GIR_RootConstrainSelectedInstOperands,
     /* 144199 */   // GIR_Coverage, 7712,
     /* 144199 */   GIR_Done,
     /* 144200 */ // Label 2498: @144200
     /* 144200 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(144241), // Rule ID 7713 //
     /* 144205 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 144208 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144212 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 144219 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 144222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 144226 */   // MIs[0] ptr
     /* 144226 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144230 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144234 */   // (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22258>>  =>  (LDARX:{ *:[i64] } GPR64sp:{ *:[i64] }:$ptr)
     /* 144234 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARX),
     /* 144239 */   GIR_RootConstrainSelectedInstOperands,
     /* 144240 */   // GIR_Coverage, 7713,
     /* 144240 */   GIR_Done,
     /* 144241 */ // Label 2499: @144241
     /* 144241 */ GIM_Reject,
     /* 144242 */ // Label 2390: @144242
     /* 144242 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(144450),
     /* 144247 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144250 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144254 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144258 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144262 */   GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(144303), // Rule ID 239 //
     /* 144267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 144270 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 144277 */     // (ld:{ *:[f128] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 144277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 144280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144282 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144287 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144297 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144301 */     GIR_RootConstrainSelectedInstOperands,
     /* 144302 */     // GIR_Coverage, 239,
     /* 144302 */     GIR_EraseRootFromParent_Done,
     /* 144303 */   // Label 2501: @144303
     /* 144303 */   GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(144344), // Rule ID 240 //
     /* 144308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 144311 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 144318 */     // (ld:{ *:[f128] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 144318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 144321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144323 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144328 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144342 */     GIR_RootConstrainSelectedInstOperands,
     /* 144343 */     // GIR_Coverage, 240,
     /* 144343 */     GIR_EraseRootFromParent_Done,
     /* 144344 */   // Label 2502: @144344
     /* 144344 */   GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(144380), // Rule ID 259 //
     /* 144349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 144352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 144359 */     // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 144359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 144362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144378 */     GIR_RootConstrainSelectedInstOperands,
     /* 144379 */     // GIR_Coverage, 259,
     /* 144379 */     GIR_EraseRootFromParent_Done,
     /* 144380 */   // Label 2503: @144380
     /* 144380 */   GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(144416), // Rule ID 280 //
     /* 144385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 144388 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 144395 */     // (ld:{ *:[f128] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 144395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 144398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144400 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144414 */     GIR_RootConstrainSelectedInstOperands,
     /* 144415 */     // GIR_Coverage, 280,
     /* 144415 */     GIR_EraseRootFromParent_Done,
     /* 144416 */   // Label 2504: @144416
     /* 144416 */   GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(144449), // Rule ID 4236 //
     /* 144421 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 144428 */     // (ld:{ *:[f128] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[f128] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 144428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 144431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144447 */     GIR_RootConstrainSelectedInstOperands,
     /* 144448 */     // GIR_Coverage, 4236,
     /* 144448 */     GIR_EraseRootFromParent_Done,
     /* 144449 */   // Label 2505: @144449
     /* 144449 */   GIM_Reject,
     /* 144450 */ // Label 2500: @144450
     /* 144450 */ GIM_Reject,
     /* 144451 */ // Label 2391: @144451
     /* 144451 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(144828),
     /* 144456 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144459 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144463 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 144467 */   GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(144512), // Rule ID 4172 //
     /* 144472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144475 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144479 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 144486 */     // (ld:{ *:[v2i32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 144486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 144489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144510 */     GIR_RootConstrainSelectedInstOperands,
     /* 144511 */     // GIR_Coverage, 4172,
     /* 144511 */     GIR_EraseRootFromParent_Done,
     /* 144512 */   // Label 2507: @144512
     /* 144512 */   GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(144557), // Rule ID 4173 //
     /* 144517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144524 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 144531 */     // (ld:{ *:[v2i32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 144531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 144534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144536 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144555 */     GIR_RootConstrainSelectedInstOperands,
     /* 144556 */     // GIR_Coverage, 4173,
     /* 144556 */     GIR_EraseRootFromParent_Done,
     /* 144557 */   // Label 2508: @144557
     /* 144557 */   GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(144602), // Rule ID 4174 //
     /* 144562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144565 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144569 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 144576 */     // (ld:{ *:[v2f32] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 144576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 144579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144581 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144596 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144600 */     GIR_RootConstrainSelectedInstOperands,
     /* 144601 */     // GIR_Coverage, 4174,
     /* 144601 */     GIR_EraseRootFromParent_Done,
     /* 144602 */   // Label 2509: @144602
     /* 144602 */   GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(144647), // Rule ID 4175 //
     /* 144607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144614 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 144621 */     // (ld:{ *:[v2f32] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 144621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 144624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144636 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144641 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144645 */     GIR_RootConstrainSelectedInstOperands,
     /* 144646 */     // GIR_Coverage, 4175,
     /* 144646 */     GIR_EraseRootFromParent_Done,
     /* 144647 */   // Label 2510: @144647
     /* 144647 */   GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(144687), // Rule ID 4222 //
     /* 144652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144655 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144659 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 144666 */     // (ld:{ *:[v2f32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 144666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 144669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144671 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144676 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144681 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144685 */     GIR_RootConstrainSelectedInstOperands,
     /* 144686 */     // GIR_Coverage, 4222,
     /* 144686 */     GIR_EraseRootFromParent_Done,
     /* 144687 */   // Label 2511: @144687
     /* 144687 */   GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(144727), // Rule ID 4225 //
     /* 144692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144695 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144699 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 144706 */     // (ld:{ *:[v2i32] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 144706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 144709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144711 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144716 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144725 */     GIR_RootConstrainSelectedInstOperands,
     /* 144726 */     // GIR_Coverage, 4225,
     /* 144726 */     GIR_EraseRootFromParent_Done,
     /* 144727 */   // Label 2512: @144727
     /* 144727 */   GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(144767), // Rule ID 4250 //
     /* 144732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144735 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144739 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144746 */     // (ld:{ *:[v2f32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 144749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144761 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144765 */     GIR_RootConstrainSelectedInstOperands,
     /* 144766 */     // GIR_Coverage, 4250,
     /* 144766 */     GIR_EraseRootFromParent_Done,
     /* 144767 */   // Label 2513: @144767
     /* 144767 */   GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(144807), // Rule ID 4251 //
     /* 144772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144775 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144779 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 144786 */     // (ld:{ *:[v2i32] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 144786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 144789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144791 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144796 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 144801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144805 */     GIR_RootConstrainSelectedInstOperands,
     /* 144806 */     // GIR_Coverage, 4251,
     /* 144806 */     GIR_EraseRootFromParent_Done,
     /* 144807 */   // Label 2514: @144807
     /* 144807 */   GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(144827), // Rule ID 7035 //
     /* 144812 */     // MIs[0] Rn
     /* 144812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 144816 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 144820 */     // (ld:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 144820 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2s),
     /* 144825 */     GIR_RootConstrainSelectedInstOperands,
     /* 144826 */     // GIR_Coverage, 7035,
     /* 144826 */     GIR_Done,
     /* 144827 */   // Label 2515: @144827
     /* 144827 */   GIM_Reject,
     /* 144828 */ // Label 2506: @144828
     /* 144828 */ GIM_Reject,
     /* 144829 */ // Label 2392: @144829
     /* 144829 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(145206),
     /* 144834 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 144837 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 144841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 144845 */   GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(144890), // Rule ID 4186 //
     /* 144850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144857 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 144864 */     // (ld:{ *:[v2i64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 144864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 144867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144879 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144888 */     GIR_RootConstrainSelectedInstOperands,
     /* 144889 */     // GIR_Coverage, 4186,
     /* 144889 */     GIR_EraseRootFromParent_Done,
     /* 144890 */   // Label 2517: @144890
     /* 144890 */   GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(144935), // Rule ID 4187 //
     /* 144895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144898 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144902 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 144909 */     // (ld:{ *:[v2i64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 144909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 144912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144933 */     GIR_RootConstrainSelectedInstOperands,
     /* 144934 */     // GIR_Coverage, 4187,
     /* 144934 */     GIR_EraseRootFromParent_Done,
     /* 144935 */   // Label 2518: @144935
     /* 144935 */   GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(144980), // Rule ID 4188 //
     /* 144940 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144943 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144947 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 144954 */     // (ld:{ *:[v2f64] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 144954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 144957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 144959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 144964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 144969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 144974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 144978 */     GIR_RootConstrainSelectedInstOperands,
     /* 144979 */     // GIR_Coverage, 4188,
     /* 144979 */     GIR_EraseRootFromParent_Done,
     /* 144980 */   // Label 2519: @144980
     /* 144980 */   GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(145025), // Rule ID 4189 //
     /* 144985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 144988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 144992 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 144999 */     // (ld:{ *:[v2f64] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 144999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 145002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145004 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145009 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145019 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145023 */     GIR_RootConstrainSelectedInstOperands,
     /* 145024 */     // GIR_Coverage, 4189,
     /* 145024 */     GIR_EraseRootFromParent_Done,
     /* 145025 */   // Label 2520: @145025
     /* 145025 */   GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(145065), // Rule ID 4230 //
     /* 145030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145033 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145037 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145044 */     // (ld:{ *:[v2f64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 145047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145049 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145054 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145063 */     GIR_RootConstrainSelectedInstOperands,
     /* 145064 */     // GIR_Coverage, 4230,
     /* 145064 */     GIR_EraseRootFromParent_Done,
     /* 145065 */   // Label 2521: @145065
     /* 145065 */   GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(145105), // Rule ID 4234 //
     /* 145070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145073 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145077 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145084 */     // (ld:{ *:[v2i64] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 145087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145089 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145103 */     GIR_RootConstrainSelectedInstOperands,
     /* 145104 */     // GIR_Coverage, 4234,
     /* 145104 */     GIR_EraseRootFromParent_Done,
     /* 145105 */   // Label 2522: @145105
     /* 145105 */   GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(145145), // Rule ID 4257 //
     /* 145110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145117 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145124 */     // (ld:{ *:[v2f64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 145127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145143 */     GIR_RootConstrainSelectedInstOperands,
     /* 145144 */     // GIR_Coverage, 4257,
     /* 145144 */     GIR_EraseRootFromParent_Done,
     /* 145145 */   // Label 2523: @145145
     /* 145145 */   GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(145185), // Rule ID 4258 //
     /* 145150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145164 */     // (ld:{ *:[v2i64] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 145167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145183 */     GIR_RootConstrainSelectedInstOperands,
     /* 145184 */     // GIR_Coverage, 4258,
     /* 145184 */     GIR_EraseRootFromParent_Done,
     /* 145185 */   // Label 2524: @145185
     /* 145185 */   GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(145205), // Rule ID 7032 //
     /* 145190 */     // MIs[0] Rn
     /* 145190 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145194 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145198 */     // (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 145198 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev2d),
     /* 145203 */     GIR_RootConstrainSelectedInstOperands,
     /* 145204 */     // GIR_Coverage, 7032,
     /* 145204 */     GIR_Done,
     /* 145205 */   // Label 2525: @145205
     /* 145205 */   GIM_Reject,
     /* 145206 */ // Label 2516: @145206
     /* 145206 */ GIM_Reject,
     /* 145207 */ // Label 2393: @145207
     /* 145207 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(145584),
     /* 145212 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145215 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145223 */   GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(145268), // Rule ID 4178 //
     /* 145228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145231 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 145242 */     // (ld:{ *:[v4i16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 145242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 145245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145247 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145252 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145257 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145262 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145266 */     GIR_RootConstrainSelectedInstOperands,
     /* 145267 */     // GIR_Coverage, 4178,
     /* 145267 */     GIR_EraseRootFromParent_Done,
     /* 145268 */   // Label 2527: @145268
     /* 145268 */   GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(145313), // Rule ID 4179 //
     /* 145273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145276 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145280 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 145287 */     // (ld:{ *:[v4i16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 145287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 145290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145307 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145311 */     GIR_RootConstrainSelectedInstOperands,
     /* 145312 */     // GIR_Coverage, 4179,
     /* 145312 */     GIR_EraseRootFromParent_Done,
     /* 145313 */   // Label 2528: @145313
     /* 145313 */   GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(145358), // Rule ID 4180 //
     /* 145318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145321 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145325 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 145332 */     // (ld:{ *:[v4f16] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 145332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 145335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145356 */     GIR_RootConstrainSelectedInstOperands,
     /* 145357 */     // GIR_Coverage, 4180,
     /* 145357 */     GIR_EraseRootFromParent_Done,
     /* 145358 */   // Label 2529: @145358
     /* 145358 */   GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(145403), // Rule ID 4181 //
     /* 145363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145370 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 145377 */     // (ld:{ *:[v4f16] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 145377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 145380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145397 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145401 */     GIR_RootConstrainSelectedInstOperands,
     /* 145402 */     // GIR_Coverage, 4181,
     /* 145402 */     GIR_EraseRootFromParent_Done,
     /* 145403 */   // Label 2530: @145403
     /* 145403 */   GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(145443), // Rule ID 4224 //
     /* 145408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145411 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145415 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 145422 */     // (ld:{ *:[v4i16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 145422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 145425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145427 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145441 */     GIR_RootConstrainSelectedInstOperands,
     /* 145442 */     // GIR_Coverage, 4224,
     /* 145442 */     GIR_EraseRootFromParent_Done,
     /* 145443 */   // Label 2531: @145443
     /* 145443 */   GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(145483), // Rule ID 4226 //
     /* 145448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145455 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 145462 */     // (ld:{ *:[v4f16] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 145462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 145465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145467 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145472 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145477 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145481 */     GIR_RootConstrainSelectedInstOperands,
     /* 145482 */     // GIR_Coverage, 4226,
     /* 145482 */     GIR_EraseRootFromParent_Done,
     /* 145483 */   // Label 2532: @145483
     /* 145483 */   GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(145523), // Rule ID 4252 //
     /* 145488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145491 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145495 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 145502 */     // (ld:{ *:[v4i16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 145505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145517 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145521 */     GIR_RootConstrainSelectedInstOperands,
     /* 145522 */     // GIR_Coverage, 4252,
     /* 145522 */     GIR_EraseRootFromParent_Done,
     /* 145523 */   // Label 2533: @145523
     /* 145523 */   GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(145563), // Rule ID 4254 //
     /* 145528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 145542 */     // (ld:{ *:[v4f16] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 145545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145561 */     GIR_RootConstrainSelectedInstOperands,
     /* 145562 */     // GIR_Coverage, 4254,
     /* 145562 */     GIR_EraseRootFromParent_Done,
     /* 145563 */   // Label 2534: @145563
     /* 145563 */   GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(145583), // Rule ID 7034 //
     /* 145568 */     // MIs[0] Rn
     /* 145568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145576 */     // (ld:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 145576 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4h),
     /* 145581 */     GIR_RootConstrainSelectedInstOperands,
     /* 145582 */     // GIR_Coverage, 7034,
     /* 145582 */     GIR_Done,
     /* 145583 */   // Label 2535: @145583
     /* 145583 */   GIM_Reject,
     /* 145584 */ // Label 2526: @145584
     /* 145584 */ GIM_Reject,
     /* 145585 */ // Label 2394: @145585
     /* 145585 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(145962),
     /* 145590 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145593 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 145601 */   GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(145646), // Rule ID 4190 //
     /* 145606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145613 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 145620 */     // (ld:{ *:[v4i32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 145620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 145623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145625 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145640 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145644 */     GIR_RootConstrainSelectedInstOperands,
     /* 145645 */     // GIR_Coverage, 4190,
     /* 145645 */     GIR_EraseRootFromParent_Done,
     /* 145646 */   // Label 2537: @145646
     /* 145646 */   GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(145691), // Rule ID 4191 //
     /* 145651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145658 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 145665 */     // (ld:{ *:[v4i32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 145665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 145668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145670 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145675 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145680 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145685 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145689 */     GIR_RootConstrainSelectedInstOperands,
     /* 145690 */     // GIR_Coverage, 4191,
     /* 145690 */     GIR_EraseRootFromParent_Done,
     /* 145691 */   // Label 2538: @145691
     /* 145691 */   GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(145736), // Rule ID 4192 //
     /* 145696 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145699 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145703 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 145710 */     // (ld:{ *:[v4f32] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 145710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 145713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145715 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145720 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145725 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145730 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145734 */     GIR_RootConstrainSelectedInstOperands,
     /* 145735 */     // GIR_Coverage, 4192,
     /* 145735 */     GIR_EraseRootFromParent_Done,
     /* 145736 */   // Label 2539: @145736
     /* 145736 */   GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(145781), // Rule ID 4193 //
     /* 145741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145744 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145748 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 145755 */     // (ld:{ *:[v4f32] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 145755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 145758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145760 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145765 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 145770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 145775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145779 */     GIR_RootConstrainSelectedInstOperands,
     /* 145780 */     // GIR_Coverage, 4193,
     /* 145780 */     GIR_EraseRootFromParent_Done,
     /* 145781 */   // Label 2540: @145781
     /* 145781 */   GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(145821), // Rule ID 4229 //
     /* 145786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145789 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145793 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145800 */     // (ld:{ *:[v4f32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 145803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145815 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145819 */     GIR_RootConstrainSelectedInstOperands,
     /* 145820 */     // GIR_Coverage, 4229,
     /* 145820 */     GIR_EraseRootFromParent_Done,
     /* 145821 */   // Label 2541: @145821
     /* 145821 */   GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(145861), // Rule ID 4233 //
     /* 145826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145829 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145833 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 145840 */     // (ld:{ *:[v4i32] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 145840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 145843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145859 */     GIR_RootConstrainSelectedInstOperands,
     /* 145860 */     // GIR_Coverage, 4233,
     /* 145860 */     GIR_EraseRootFromParent_Done,
     /* 145861 */   // Label 2542: @145861
     /* 145861 */   GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(145901), // Rule ID 4259 //
     /* 145866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145880 */     // (ld:{ *:[v4f32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 145883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145899 */     GIR_RootConstrainSelectedInstOperands,
     /* 145900 */     // GIR_Coverage, 4259,
     /* 145900 */     GIR_EraseRootFromParent_Done,
     /* 145901 */   // Label 2543: @145901
     /* 145901 */   GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(145941), // Rule ID 4260 //
     /* 145906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145909 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 145920 */     // (ld:{ *:[v4i32] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 145920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 145923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 145925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 145930 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 145935 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 145939 */     GIR_RootConstrainSelectedInstOperands,
     /* 145940 */     // GIR_Coverage, 4260,
     /* 145940 */     GIR_EraseRootFromParent_Done,
     /* 145941 */   // Label 2544: @145941
     /* 145941 */   GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(145961), // Rule ID 7031 //
     /* 145946 */     // MIs[0] Rn
     /* 145946 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 145950 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 145954 */     // (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 145954 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev4s),
     /* 145959 */     GIR_RootConstrainSelectedInstOperands,
     /* 145960 */     // GIR_Coverage, 7031,
     /* 145960 */     GIR_Done,
     /* 145961 */   // Label 2545: @145961
     /* 145961 */   GIM_Reject,
     /* 145962 */ // Label 2536: @145962
     /* 145962 */ GIM_Reject,
     /* 145963 */ // Label 2395: @145963
     /* 145963 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(146170),
     /* 145968 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 145971 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 145975 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 145979 */   GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(146024), // Rule ID 4176 //
     /* 145984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 145987 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 145991 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 145998 */     // (ld:{ *:[v8i8] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroW:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 145998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 146001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146003 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146008 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146022 */     GIR_RootConstrainSelectedInstOperands,
     /* 146023 */     // GIR_Coverage, 4176,
     /* 146023 */     GIR_EraseRootFromParent_Done,
     /* 146024 */   // Label 2547: @146024
     /* 146024 */   GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(146069), // Rule ID 4177 //
     /* 146029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146032 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146036 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 146043 */     // (ld:{ *:[v8i8] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDroX:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 146043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 146046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146048 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146053 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146067 */     GIR_RootConstrainSelectedInstOperands,
     /* 146068 */     // GIR_Coverage, 4177,
     /* 146068 */     GIR_EraseRootFromParent_Done,
     /* 146069 */   // Label 2548: @146069
     /* 146069 */   GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(146109), // Rule ID 4223 //
     /* 146074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146081 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 146088 */     // (ld:{ *:[v8i8] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRDui:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 146088 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 146091 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146098 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146103 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146107 */     GIR_RootConstrainSelectedInstOperands,
     /* 146108 */     // GIR_Coverage, 4223,
     /* 146108 */     GIR_EraseRootFromParent_Done,
     /* 146109 */   // Label 2549: @146109
     /* 146109 */   GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(146149), // Rule ID 4253 //
     /* 146114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146117 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146121 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 146128 */     // (ld:{ *:[v8i8] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURDi:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 146128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 146131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146133 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146138 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146143 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146147 */     GIR_RootConstrainSelectedInstOperands,
     /* 146148 */     // GIR_Coverage, 4253,
     /* 146148 */     GIR_EraseRootFromParent_Done,
     /* 146149 */   // Label 2550: @146149
     /* 146149 */   GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(146169), // Rule ID 7033 //
     /* 146154 */     // MIs[0] Rn
     /* 146154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146158 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146162 */     // (ld:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 146162 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8b),
     /* 146167 */     GIR_RootConstrainSelectedInstOperands,
     /* 146168 */     // GIR_Coverage, 7033,
     /* 146168 */     GIR_Done,
     /* 146169 */   // Label 2551: @146169
     /* 146169 */   GIM_Reject,
     /* 146170 */ // Label 2546: @146170
     /* 146170 */ GIM_Reject,
     /* 146171 */ // Label 2396: @146171
     /* 146171 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(146548),
     /* 146176 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146179 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 146187 */   GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(146232), // Rule ID 4194 //
     /* 146192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146195 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146199 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 146206 */     // (ld:{ *:[v8i16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 146206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 146209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146211 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146216 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146221 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146230 */     GIR_RootConstrainSelectedInstOperands,
     /* 146231 */     // GIR_Coverage, 4194,
     /* 146231 */     GIR_EraseRootFromParent_Done,
     /* 146232 */   // Label 2553: @146232
     /* 146232 */   GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(146277), // Rule ID 4195 //
     /* 146237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146244 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 146251 */     // (ld:{ *:[v8i16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 146251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 146254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146275 */     GIR_RootConstrainSelectedInstOperands,
     /* 146276 */     // GIR_Coverage, 4195,
     /* 146276 */     GIR_EraseRootFromParent_Done,
     /* 146277 */   // Label 2554: @146277
     /* 146277 */   GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(146322), // Rule ID 4196 //
     /* 146282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146285 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146289 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 146296 */     // (ld:{ *:[v8f16] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 146296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 146299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146301 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146306 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146311 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146320 */     GIR_RootConstrainSelectedInstOperands,
     /* 146321 */     // GIR_Coverage, 4196,
     /* 146321 */     GIR_EraseRootFromParent_Done,
     /* 146322 */   // Label 2555: @146322
     /* 146322 */   GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(146367), // Rule ID 4197 //
     /* 146327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146330 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 146341 */     // (ld:{ *:[v8f16] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 146341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 146344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146346 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146351 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146356 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146365 */     GIR_RootConstrainSelectedInstOperands,
     /* 146366 */     // GIR_Coverage, 4197,
     /* 146366 */     GIR_EraseRootFromParent_Done,
     /* 146367 */   // Label 2556: @146367
     /* 146367 */   GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(146407), // Rule ID 4232 //
     /* 146372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146375 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146379 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 146386 */     // (ld:{ *:[v8i16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 146386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 146389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146391 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146396 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146405 */     GIR_RootConstrainSelectedInstOperands,
     /* 146406 */     // GIR_Coverage, 4232,
     /* 146406 */     GIR_EraseRootFromParent_Done,
     /* 146407 */   // Label 2557: @146407
     /* 146407 */   GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(146447), // Rule ID 4235 //
     /* 146412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146419 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 146426 */     // (ld:{ *:[v8f16] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 146426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 146429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146431 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146436 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146441 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146445 */     GIR_RootConstrainSelectedInstOperands,
     /* 146446 */     // GIR_Coverage, 4235,
     /* 146446 */     GIR_EraseRootFromParent_Done,
     /* 146447 */   // Label 2558: @146447
     /* 146447 */   GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(146487), // Rule ID 4261 //
     /* 146452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146459 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 146466 */     // (ld:{ *:[v8i16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 146466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 146469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146471 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146481 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146485 */     GIR_RootConstrainSelectedInstOperands,
     /* 146486 */     // GIR_Coverage, 4261,
     /* 146486 */     GIR_EraseRootFromParent_Done,
     /* 146487 */   // Label 2559: @146487
     /* 146487 */   GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(146527), // Rule ID 4263 //
     /* 146492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146499 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 146506 */     // (ld:{ *:[v8f16] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 146506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 146509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146511 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146516 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146525 */     GIR_RootConstrainSelectedInstOperands,
     /* 146526 */     // GIR_Coverage, 4263,
     /* 146526 */     GIR_EraseRootFromParent_Done,
     /* 146527 */   // Label 2560: @146527
     /* 146527 */   GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(146547), // Rule ID 7030 //
     /* 146532 */     // MIs[0] Rn
     /* 146532 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146536 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146540 */     // (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 146540 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev8h),
     /* 146545 */     GIR_RootConstrainSelectedInstOperands,
     /* 146546 */     // GIR_Coverage, 7030,
     /* 146546 */     GIR_Done,
     /* 146547 */   // Label 2561: @146547
     /* 146547 */   GIM_Reject,
     /* 146548 */ // Label 2552: @146548
     /* 146548 */ GIM_Reject,
     /* 146549 */ // Label 2397: @146549
     /* 146549 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(146756),
     /* 146554 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146557 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146561 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 146565 */   GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(146610), // Rule ID 4198 //
     /* 146570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146577 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 146584 */     // (ld:{ *:[v16i8] } (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroW:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 146584 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroW),
     /* 146587 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146599 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146608 */     GIR_RootConstrainSelectedInstOperands,
     /* 146609 */     // GIR_Coverage, 4198,
     /* 146609 */     GIR_EraseRootFromParent_Done,
     /* 146610 */   // Label 2563: @146610
     /* 146610 */   GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(146655), // Rule ID 4199 //
     /* 146615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146618 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146622 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 146629 */     // (ld:{ *:[v16i8] } (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQroX:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 146629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQroX),
     /* 146632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146634 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146639 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 146644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 146649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146653 */     GIR_RootConstrainSelectedInstOperands,
     /* 146654 */     // GIR_Coverage, 4199,
     /* 146654 */     GIR_EraseRootFromParent_Done,
     /* 146655 */   // Label 2564: @146655
     /* 146655 */   GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(146695), // Rule ID 4231 //
     /* 146660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146667 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 146674 */     // (ld:{ *:[v16i8] } (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDRQui:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 146674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRQui),
     /* 146677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146693 */     GIR_RootConstrainSelectedInstOperands,
     /* 146694 */     // GIR_Coverage, 4231,
     /* 146694 */     GIR_EraseRootFromParent_Done,
     /* 146695 */   // Label 2565: @146695
     /* 146695 */   GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(146735), // Rule ID 4262 //
     /* 146700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 146703 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 146707 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 146714 */     // (ld:{ *:[v16i8] } (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDURQi:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 146714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURQi),
     /* 146717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 146719 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 146724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 146729 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146733 */     GIR_RootConstrainSelectedInstOperands,
     /* 146734 */     // GIR_Coverage, 4262,
     /* 146734 */     GIR_EraseRootFromParent_Done,
     /* 146735 */   // Label 2566: @146735
     /* 146735 */   GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(146755), // Rule ID 7029 //
     /* 146740 */     // MIs[0] Rn
     /* 146740 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146744 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 146748 */     // (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1Onev16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 146748 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LD1Onev16b),
     /* 146753 */     GIR_RootConstrainSelectedInstOperands,
     /* 146754 */     // GIR_Coverage, 7029,
     /* 146754 */     GIR_Done,
     /* 146755 */   // Label 2567: @146755
     /* 146755 */   GIM_Reject,
     /* 146756 */ // Label 2562: @146756
     /* 146756 */ GIM_Reject,
     /* 146757 */ // Label 2398: @146757
     /* 146757 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(146820), // Rule ID 11721 //
     /* 146762 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146765 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146768 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 146776 */   // MIs[0] base
     /* 146776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146784 */   // (ld:{ *:[nxv2f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_D_IMM:{ *:[nxv2f16] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146784 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146787 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 146791 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146796 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146799 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_D_IMM),
     /* 146804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 146806 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146809 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146811 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146814 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146818 */   GIR_RootConstrainSelectedInstOperands,
     /* 146819 */   // GIR_Coverage, 11721,
     /* 146819 */   GIR_EraseRootFromParent_Done,
     /* 146820 */ // Label 2568: @146820
     /* 146820 */ GIM_Reject,
     /* 146821 */ // Label 2399: @146821
     /* 146821 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(146884), // Rule ID 11727 //
     /* 146826 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146829 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146832 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 146840 */   // MIs[0] base
     /* 146840 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146844 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146848 */   // (ld:{ *:[nxv2f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_D_IMM:{ *:[nxv2f32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146848 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146851 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 146855 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146860 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146863 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146865 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_D_IMM),
     /* 146868 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 146870 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146873 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146875 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146878 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146882 */   GIR_RootConstrainSelectedInstOperands,
     /* 146883 */   // GIR_Coverage, 11727,
     /* 146883 */   GIR_EraseRootFromParent_Done,
     /* 146884 */ // Label 2569: @146884
     /* 146884 */ GIM_Reject,
     /* 146885 */ // Label 2400: @146885
     /* 146885 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(147058),
     /* 146890 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 146893 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 146897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 146901 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 146905 */   GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(146953), // Rule ID 11712 //
     /* 146910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146913 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146917 */     // (ld:{ *:[nxv2i64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1D_IMM:{ *:[nxv2i64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146917 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146920 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 146924 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146929 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146932 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
     /* 146937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 146939 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146942 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146947 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146951 */     GIR_RootConstrainSelectedInstOperands,
     /* 146952 */     // GIR_Coverage, 11712,
     /* 146952 */     GIR_EraseRootFromParent_Done,
     /* 146953 */   // Label 2571: @146953
     /* 146953 */   GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(147001), // Rule ID 11730 //
     /* 146958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 146961 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 146965 */     // (ld:{ *:[nxv2f64] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1D_IMM:{ *:[nxv2f64] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 146965 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 146968 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 146972 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 146977 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 146980 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 146982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_IMM),
     /* 146985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 146987 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 146990 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 146992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 146995 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 146999 */     GIR_RootConstrainSelectedInstOperands,
     /* 147000 */     // GIR_Coverage, 11730,
     /* 147000 */     GIR_EraseRootFromParent_Done,
     /* 147001 */   // Label 2572: @147001
     /* 147001 */   GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(147029), // Rule ID 11778 //
     /* 147006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147009 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147013 */     // (ld:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147018 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147020 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147027 */     GIR_RootConstrainSelectedInstOperands,
     /* 147028 */     // GIR_Coverage, 11778,
     /* 147028 */     GIR_EraseRootFromParent_Done,
     /* 147029 */   // Label 2573: @147029
     /* 147029 */   GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(147057), // Rule ID 11790 //
     /* 147034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147037 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147041 */     // (ld:{ *:[nxv2f64] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv2f64] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147046 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147055 */     GIR_RootConstrainSelectedInstOperands,
     /* 147056 */     // GIR_Coverage, 11790,
     /* 147056 */     GIR_EraseRootFromParent_Done,
     /* 147057 */   // Label 2574: @147057
     /* 147057 */   GIM_Reject,
     /* 147058 */ // Label 2570: @147058
     /* 147058 */ GIM_Reject,
     /* 147059 */ // Label 2401: @147059
     /* 147059 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(147122), // Rule ID 11718 //
     /* 147064 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147067 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147070 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 147074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 147078 */   // MIs[0] base
     /* 147078 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147082 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147086 */   // (ld:{ *:[nxv4f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_S_IMM:{ *:[nxv4f16] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147086 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147089 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 147093 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147098 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147101 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147103 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_S_IMM),
     /* 147106 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147108 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147111 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147113 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147116 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147120 */   GIR_RootConstrainSelectedInstOperands,
     /* 147121 */   // GIR_Coverage, 11718,
     /* 147121 */   GIR_EraseRootFromParent_Done,
     /* 147122 */ // Label 2575: @147122
     /* 147122 */ GIM_Reject,
     /* 147123 */ // Label 2402: @147123
     /* 147123 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(147296),
     /* 147128 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147131 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 147135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 147139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147143 */   GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(147191), // Rule ID 11700 //
     /* 147148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147151 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147155 */     // (ld:{ *:[nxv4i32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_IMM:{ *:[nxv4i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147155 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147158 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 147162 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147167 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147170 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
     /* 147175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147177 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147180 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147185 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147189 */     GIR_RootConstrainSelectedInstOperands,
     /* 147190 */     // GIR_Coverage, 11700,
     /* 147190 */     GIR_EraseRootFromParent_Done,
     /* 147191 */   // Label 2577: @147191
     /* 147191 */   GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(147239), // Rule ID 11724 //
     /* 147196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147199 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147203 */     // (ld:{ *:[nxv4f32] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1W_IMM:{ *:[nxv4f32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147203 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147206 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 147210 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147215 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147218 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_IMM),
     /* 147223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147225 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147228 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147230 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147233 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147237 */     GIR_RootConstrainSelectedInstOperands,
     /* 147238 */     // GIR_Coverage, 11724,
     /* 147238 */     GIR_EraseRootFromParent_Done,
     /* 147239 */   // Label 2578: @147239
     /* 147239 */   GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(147267), // Rule ID 11774 //
     /* 147244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147247 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147251 */     // (ld:{ *:[nxv4i32] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv4i32] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147256 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147265 */     GIR_RootConstrainSelectedInstOperands,
     /* 147266 */     // GIR_Coverage, 11774,
     /* 147266 */     GIR_EraseRootFromParent_Done,
     /* 147267 */   // Label 2579: @147267
     /* 147267 */   GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(147295), // Rule ID 11786 //
     /* 147272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147275 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147279 */     // (ld:{ *:[nxv4f32] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv4f32] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147284 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147286 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147289 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147293 */     GIR_RootConstrainSelectedInstOperands,
     /* 147294 */     // GIR_Coverage, 11786,
     /* 147294 */     GIR_EraseRootFromParent_Done,
     /* 147295 */   // Label 2580: @147295
     /* 147295 */   GIM_Reject,
     /* 147296 */ // Label 2576: @147296
     /* 147296 */ GIM_Reject,
     /* 147297 */ // Label 2403: @147297
     /* 147297 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(147470),
     /* 147302 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147305 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 147309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 147313 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147317 */   GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(147365), // Rule ID 11679 //
     /* 147322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147325 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147329 */     // (ld:{ *:[nxv8i16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_IMM:{ *:[nxv8i16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147329 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147332 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 147336 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147341 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147344 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
     /* 147349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147351 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147354 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147359 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147363 */     GIR_RootConstrainSelectedInstOperands,
     /* 147364 */     // GIR_Coverage, 11679,
     /* 147364 */     GIR_EraseRootFromParent_Done,
     /* 147365 */   // Label 2582: @147365
     /* 147365 */   GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(147413), // Rule ID 11715 //
     /* 147370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147373 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147377 */     // (ld:{ *:[nxv8f16] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1H_IMM:{ *:[nxv8f16] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147377 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147380 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 147384 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147389 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147392 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1H_IMM),
     /* 147397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147399 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147402 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147407 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147411 */     GIR_RootConstrainSelectedInstOperands,
     /* 147412 */     // GIR_Coverage, 11715,
     /* 147412 */     GIR_EraseRootFromParent_Done,
     /* 147413 */   // Label 2583: @147413
     /* 147413 */   GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(147441), // Rule ID 11770 //
     /* 147418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147421 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147425 */     // (ld:{ *:[nxv8i16] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv8i16] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147430 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147439 */     GIR_RootConstrainSelectedInstOperands,
     /* 147440 */     // GIR_Coverage, 11770,
     /* 147440 */     GIR_EraseRootFromParent_Done,
     /* 147441 */   // Label 2584: @147441
     /* 147441 */   GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(147469), // Rule ID 11782 //
     /* 147446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147449 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147453 */     // (ld:{ *:[nxv8f16] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv8f16] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147458 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147467 */     GIR_RootConstrainSelectedInstOperands,
     /* 147468 */     // GIR_Coverage, 11782,
     /* 147468 */     GIR_EraseRootFromParent_Done,
     /* 147469 */   // Label 2585: @147469
     /* 147469 */   GIM_Reject,
     /* 147470 */ // Label 2581: @147470
     /* 147470 */ GIM_Reject,
     /* 147471 */ // Label 2404: @147471
     /* 147471 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(147514), // Rule ID 2465 //
     /* 147476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147479 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147482 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 147486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 147490 */   // MIs[0] base
     /* 147490 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147494 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147498 */   // (ld:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_PXI:{ *:[nxv16i1] } GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147498 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_PXI),
     /* 147501 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pt]
     /* 147503 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147505 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147508 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147512 */   GIR_RootConstrainSelectedInstOperands,
     /* 147513 */   // GIR_Coverage, 2465,
     /* 147513 */   GIR_EraseRootFromParent_Done,
     /* 147514 */ // Label 2586: @147514
     /* 147514 */ GIM_Reject,
     /* 147515 */ // Label 2405: @147515
     /* 147515 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(147612),
     /* 147520 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147523 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 147527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 147531 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 147535 */   GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(147583), // Rule ID 11647 //
     /* 147540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 147543 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 147547 */     // (ld:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LD1B_IMM:{ *:[nxv16i8] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147547 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 147550 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 147554 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 147559 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 147562 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 147564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1B_IMM),
     /* 147567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147569 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 147572 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147574 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147577 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147581 */     GIR_RootConstrainSelectedInstOperands,
     /* 147582 */     // GIR_Coverage, 11647,
     /* 147582 */     GIR_EraseRootFromParent_Done,
     /* 147583 */   // Label 2588: @147583
     /* 147583 */   GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(147611), // Rule ID 11766 //
     /* 147588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 147591 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 147595 */     // (ld:{ *:[nxv16i8] } GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LDR_ZXI:{ *:[nxv16i8] } GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 147595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDR_ZXI),
     /* 147598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 147600 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 147602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 147605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147609 */     GIR_RootConstrainSelectedInstOperands,
     /* 147610 */     // GIR_Coverage, 11766,
     /* 147610 */     GIR_EraseRootFromParent_Done,
     /* 147611 */   // Label 2589: @147611
     /* 147611 */   GIM_Reject,
     /* 147612 */ // Label 2587: @147612
     /* 147612 */ GIM_Reject,
     /* 147613 */ // Label 2406: @147613
     /* 147613 */ GIM_Reject,
     /* 147614 */ // Label 23: @147614
     /* 147614 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2592*/ GIMT_Encode4(148663),
     /* 147625 */ /*GILLT_s32*//*Label 2590*/ GIMT_Encode4(147633),
     /* 147629 */ /*GILLT_s64*//*Label 2591*/ GIMT_Encode4(148047),
     /* 147633 */ // Label 2590: @147633
     /* 147633 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(148046),
     /* 147638 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 147641 */   GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(147694), // Rule ID 241 //
     /* 147646 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147661 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 147668 */     // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 147668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroW),
     /* 147671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 147683 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 147688 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147692 */     GIR_RootConstrainSelectedInstOperands,
     /* 147693 */     // GIR_Coverage, 241,
     /* 147693 */     GIR_EraseRootFromParent_Done,
     /* 147694 */   // Label 2594: @147694
     /* 147694 */   GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(147747), // Rule ID 242 //
     /* 147699 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147710 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147714 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 147721 */     // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 147721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWroX),
     /* 147724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147726 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 147736 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 147741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147745 */     GIR_RootConstrainSelectedInstOperands,
     /* 147746 */     // GIR_Coverage, 242,
     /* 147746 */     GIR_EraseRootFromParent_Done,
     /* 147747 */   // Label 2595: @147747
     /* 147747 */   GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(147800), // Rule ID 245 //
     /* 147752 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147763 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147767 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 147774 */     // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 147774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroW),
     /* 147777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 147789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 147794 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147798 */     GIR_RootConstrainSelectedInstOperands,
     /* 147799 */     // GIR_Coverage, 245,
     /* 147799 */     GIR_EraseRootFromParent_Done,
     /* 147800 */   // Label 2596: @147800
     /* 147800 */   GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(147853), // Rule ID 246 //
     /* 147805 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147816 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147820 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 147827 */     // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 147827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWroX),
     /* 147830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147832 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147837 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 147842 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 147847 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147851 */     GIR_RootConstrainSelectedInstOperands,
     /* 147852 */     // GIR_Coverage, 246,
     /* 147852 */     GIR_EraseRootFromParent_Done,
     /* 147853 */   // Label 2597: @147853
     /* 147853 */   GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(147901), // Rule ID 262 //
     /* 147858 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147873 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 147880 */     // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 147880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHWui),
     /* 147883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147885 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147890 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 147895 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147899 */     GIR_RootConstrainSelectedInstOperands,
     /* 147900 */     // GIR_Coverage, 262,
     /* 147900 */     GIR_EraseRootFromParent_Done,
     /* 147901 */   // Label 2598: @147901
     /* 147901 */   GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(147949), // Rule ID 264 //
     /* 147906 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 147913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147917 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147921 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 147928 */     // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 147928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBWui),
     /* 147931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147933 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147938 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 147943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147947 */     GIR_RootConstrainSelectedInstOperands,
     /* 147948 */     // GIR_Coverage, 264,
     /* 147948 */     GIR_EraseRootFromParent_Done,
     /* 147949 */   // Label 2599: @147949
     /* 147949 */   GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(147997), // Rule ID 283 //
     /* 147954 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 147961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 147965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 147969 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 147976 */     // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 147976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHWi),
     /* 147979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 147981 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 147986 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 147991 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 147995 */     GIR_RootConstrainSelectedInstOperands,
     /* 147996 */     // GIR_Coverage, 283,
     /* 147996 */     GIR_EraseRootFromParent_Done,
     /* 147997 */   // Label 2600: @147997
     /* 147997 */   GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(148045), // Rule ID 285 //
     /* 148002 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148013 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148017 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 148024 */     // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 148024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBWi),
     /* 148027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148039 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148043 */     GIR_RootConstrainSelectedInstOperands,
     /* 148044 */     // GIR_Coverage, 285,
     /* 148044 */     GIR_EraseRootFromParent_Done,
     /* 148045 */   // Label 2601: @148045
     /* 148045 */   GIM_Reject,
     /* 148046 */ // Label 2593: @148046
     /* 148046 */ GIM_Reject,
     /* 148047 */ // Label 2591: @148047
     /* 148047 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(148662),
     /* 148052 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148055 */   GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(148108), // Rule ID 243 //
     /* 148060 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148075 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 148082 */     // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 148082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroW),
     /* 148085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148087 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148102 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148106 */     GIR_RootConstrainSelectedInstOperands,
     /* 148107 */     // GIR_Coverage, 243,
     /* 148107 */     GIR_EraseRootFromParent_Done,
     /* 148108 */   // Label 2603: @148108
     /* 148108 */   GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(148161), // Rule ID 244 //
     /* 148113 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148124 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148128 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 148135 */     // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 148135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXroX),
     /* 148138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148155 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148159 */     GIR_RootConstrainSelectedInstOperands,
     /* 148160 */     // GIR_Coverage, 244,
     /* 148160 */     GIR_EraseRootFromParent_Done,
     /* 148161 */   // Label 2604: @148161
     /* 148161 */   GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(148214), // Rule ID 247 //
     /* 148166 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148181 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 148188 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 148188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroW),
     /* 148191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148208 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148212 */     GIR_RootConstrainSelectedInstOperands,
     /* 148213 */     // GIR_Coverage, 247,
     /* 148213 */     GIR_EraseRootFromParent_Done,
     /* 148214 */   // Label 2605: @148214
     /* 148214 */   GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(148267), // Rule ID 248 //
     /* 148219 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148230 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148234 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 148241 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 148241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXroX),
     /* 148244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148251 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148256 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148261 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148265 */     GIR_RootConstrainSelectedInstOperands,
     /* 148266 */     // GIR_Coverage, 248,
     /* 148266 */     GIR_EraseRootFromParent_Done,
     /* 148267 */   // Label 2606: @148267
     /* 148267 */   GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(148320), // Rule ID 249 //
     /* 148272 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148287 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 148294 */     // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 148294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroW),
     /* 148297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148299 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148318 */     GIR_RootConstrainSelectedInstOperands,
     /* 148319 */     // GIR_Coverage, 249,
     /* 148319 */     GIR_EraseRootFromParent_Done,
     /* 148320 */   // Label 2607: @148320
     /* 148320 */   GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(148373), // Rule ID 250 //
     /* 148325 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148336 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148340 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 148347 */     // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 148347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWroX),
     /* 148350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148362 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148371 */     GIR_RootConstrainSelectedInstOperands,
     /* 148372 */     // GIR_Coverage, 250,
     /* 148372 */     GIR_EraseRootFromParent_Done,
     /* 148373 */   // Label 2608: @148373
     /* 148373 */   GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(148421), // Rule ID 263 //
     /* 148378 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148393 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 148400 */     // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDRSHXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 148400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSHXui),
     /* 148403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148405 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148410 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148419 */     GIR_RootConstrainSelectedInstOperands,
     /* 148420 */     // GIR_Coverage, 263,
     /* 148420 */     GIR_EraseRootFromParent_Done,
     /* 148421 */   // Label 2609: @148421
     /* 148421 */   GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(148469), // Rule ID 265 //
     /* 148426 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148437 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148441 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 148448 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDRSBXui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 148448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSBXui),
     /* 148451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148453 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148458 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148467 */     GIR_RootConstrainSelectedInstOperands,
     /* 148468 */     // GIR_Coverage, 265,
     /* 148468 */     GIR_EraseRootFromParent_Done,
     /* 148469 */   // Label 2610: @148469
     /* 148469 */   GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(148517), // Rule ID 266 //
     /* 148474 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148489 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 148496 */     // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDRSWui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 148496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRSWui),
     /* 148499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148506 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148511 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148515 */     GIR_RootConstrainSelectedInstOperands,
     /* 148516 */     // GIR_Coverage, 266,
     /* 148516 */     GIR_EraseRootFromParent_Done,
     /* 148517 */   // Label 2611: @148517
     /* 148517 */   GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(148565), // Rule ID 284 //
     /* 148522 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148537 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 148544 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LDURSHXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 148544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSHXi),
     /* 148547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148549 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148559 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148563 */     GIR_RootConstrainSelectedInstOperands,
     /* 148564 */     // GIR_Coverage, 284,
     /* 148564 */     GIR_EraseRootFromParent_Done,
     /* 148565 */   // Label 2612: @148565
     /* 148565 */   GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(148613), // Rule ID 286 //
     /* 148570 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148581 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148585 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 148592 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>  =>  (LDURSBXi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 148592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSBXi),
     /* 148595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148611 */     GIR_RootConstrainSelectedInstOperands,
     /* 148612 */     // GIR_Coverage, 286,
     /* 148612 */     GIR_EraseRootFromParent_Done,
     /* 148613 */   // Label 2613: @148613
     /* 148613 */   GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(148661), // Rule ID 287 //
     /* 148618 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 148625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 148629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 148640 */     // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>>  =>  (LDURSWi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 148640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURSWi),
     /* 148643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 148655 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148659 */     GIR_RootConstrainSelectedInstOperands,
     /* 148660 */     // GIR_Coverage, 287,
     /* 148660 */     GIR_EraseRootFromParent_Done,
     /* 148661 */   // Label 2614: @148661
     /* 148661 */   GIM_Reject,
     /* 148662 */ // Label 2602: @148662
     /* 148662 */ GIM_Reject,
     /* 148663 */ // Label 2592: @148663
     /* 148663 */ GIM_Reject,
     /* 148664 */ // Label 24: @148664
     /* 148664 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2617*/ GIMT_Encode4(151712),
     /* 148675 */ /*GILLT_s32*//*Label 2615*/ GIMT_Encode4(148683),
     /* 148679 */ /*GILLT_s64*//*Label 2616*/ GIMT_Encode4(150222),
     /* 148683 */ // Label 2615: @148683
     /* 148683 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(148739), // Rule ID 223 //
     /* 148688 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148691 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148702 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148706 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 148713 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 148713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 148716 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148718 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148723 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148733 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148737 */   GIR_RootConstrainSelectedInstOperands,
     /* 148738 */   // GIR_Coverage, 223,
     /* 148738 */   GIR_EraseRootFromParent_Done,
     /* 148739 */ // Label 2618: @148739
     /* 148739 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(148795), // Rule ID 224 //
     /* 148744 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148747 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148758 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148762 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 148769 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 148769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 148772 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148789 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148793 */   GIR_RootConstrainSelectedInstOperands,
     /* 148794 */   // GIR_Coverage, 224,
     /* 148794 */   GIR_EraseRootFromParent_Done,
     /* 148795 */ // Label 2619: @148795
     /* 148795 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(148851), // Rule ID 225 //
     /* 148800 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148803 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148810 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148814 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148818 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 148825 */   // (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 148825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 148828 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148830 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148835 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148840 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148845 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148849 */   GIR_RootConstrainSelectedInstOperands,
     /* 148850 */   // GIR_Coverage, 225,
     /* 148850 */   GIR_EraseRootFromParent_Done,
     /* 148851 */ // Label 2620: @148851
     /* 148851 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(148907), // Rule ID 226 //
     /* 148856 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148859 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 148866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148870 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148874 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 148881 */   // (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 148881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 148884 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148886 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148891 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148896 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148901 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148905 */   GIR_RootConstrainSelectedInstOperands,
     /* 148906 */   // GIR_Coverage, 226,
     /* 148906 */   GIR_EraseRootFromParent_Done,
     /* 148907 */ // Label 2621: @148907
     /* 148907 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(148963), // Rule ID 4220 //
     /* 148912 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148915 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148930 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 148937 */   // (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 148937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 148940 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 148947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 148952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 148957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 148961 */   GIR_RootConstrainSelectedInstOperands,
     /* 148962 */   // GIR_Coverage, 4220,
     /* 148962 */   GIR_EraseRootFromParent_Done,
     /* 148963 */ // Label 2622: @148963
     /* 148963 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(149019), // Rule ID 4221 //
     /* 148968 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 148971 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 148978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 148982 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 148986 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 148993 */   // (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 148993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 148996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 148998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 149008 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 149013 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149017 */   GIR_RootConstrainSelectedInstOperands,
     /* 149018 */   // GIR_Coverage, 4221,
     /* 149018 */   GIR_EraseRootFromParent_Done,
     /* 149019 */ // Label 2623: @149019
     /* 149019 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(149070), // Rule ID 260 //
     /* 149024 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149027 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149038 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149042 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 149049 */   // (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 149049 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 149052 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149059 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149064 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149068 */   GIR_RootConstrainSelectedInstOperands,
     /* 149069 */   // GIR_Coverage, 260,
     /* 149069 */   GIR_EraseRootFromParent_Done,
     /* 149070 */ // Label 2624: @149070
     /* 149070 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(149121), // Rule ID 261 //
     /* 149075 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149078 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149085 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149089 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149093 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 149100 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 149100 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 149103 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149115 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149119 */   GIR_RootConstrainSelectedInstOperands,
     /* 149120 */   // GIR_Coverage, 261,
     /* 149120 */   GIR_EraseRootFromParent_Done,
     /* 149121 */ // Label 2625: @149121
     /* 149121 */ GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(149180), // Rule ID 7687 //
     /* 149126 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149136 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 149154 */   // (atomic_load:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$offset)
     /* 149154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 149157 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149159 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149164 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 149169 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 149174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149178 */   GIR_RootConstrainSelectedInstOperands,
     /* 149179 */   // GIR_Coverage, 7687,
     /* 149179 */   GIR_EraseRootFromParent_Done,
     /* 149180 */ // Label 2626: @149180
     /* 149180 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(149239), // Rule ID 7689 //
     /* 149185 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149188 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149195 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149202 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149206 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 149213 */   // (atomic_load:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$offset)
     /* 149213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 149216 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149218 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149223 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 149228 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
     /* 149233 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149237 */   GIR_RootConstrainSelectedInstOperands,
     /* 149238 */   // GIR_Coverage, 7689,
     /* 149238 */   GIR_EraseRootFromParent_Done,
     /* 149239 */ // Label 2627: @149239
     /* 149239 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(149298), // Rule ID 7699 //
     /* 149244 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149247 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149254 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149261 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149265 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 149272 */   // (atomic_load:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 149272 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 149275 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149277 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149282 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 149287 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 149292 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149296 */   GIR_RootConstrainSelectedInstOperands,
     /* 149297 */   // GIR_Coverage, 7699,
     /* 149297 */   GIR_EraseRootFromParent_Done,
     /* 149298 */ // Label 2628: @149298
     /* 149298 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(149357), // Rule ID 7701 //
     /* 149303 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149306 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149313 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149320 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149324 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 149331 */   // (atomic_load:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 149331 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 149334 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149336 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149341 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 149346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 149351 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149355 */   GIR_RootConstrainSelectedInstOperands,
     /* 149356 */   // GIR_Coverage, 7701,
     /* 149356 */   GIR_EraseRootFromParent_Done,
     /* 149357 */ // Label 2629: @149357
     /* 149357 */ GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(149408), // Rule ID 281 //
     /* 149362 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149365 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149372 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149380 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 149387 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 149387 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 149390 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149392 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149397 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149402 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149406 */   GIR_RootConstrainSelectedInstOperands,
     /* 149407 */   // GIR_Coverage, 281,
     /* 149407 */   GIR_EraseRootFromParent_Done,
     /* 149408 */ // Label 2630: @149408
     /* 149408 */ GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(149459), // Rule ID 282 //
     /* 149413 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149416 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149427 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149431 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 149438 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 149438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 149441 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149443 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149448 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149453 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149457 */   GIR_RootConstrainSelectedInstOperands,
     /* 149458 */   // GIR_Coverage, 282,
     /* 149458 */   GIR_EraseRootFromParent_Done,
     /* 149459 */ // Label 2631: @149459
     /* 149459 */ GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(149510), // Rule ID 4239 //
     /* 149464 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149467 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149478 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149482 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 149489 */   // (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 149489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 149492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149494 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149499 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149504 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149508 */   GIR_RootConstrainSelectedInstOperands,
     /* 149509 */   // GIR_Coverage, 4239,
     /* 149509 */   GIR_EraseRootFromParent_Done,
     /* 149510 */ // Label 2632: @149510
     /* 149510 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(149561), // Rule ID 4271 //
     /* 149515 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149518 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149525 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149529 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149533 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 149540 */   // (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 149543 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149545 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149550 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149555 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149559 */   GIR_RootConstrainSelectedInstOperands,
     /* 149560 */   // GIR_Coverage, 4271,
     /* 149560 */   GIR_EraseRootFromParent_Done,
     /* 149561 */ // Label 2633: @149561
     /* 149561 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(149612), // Rule ID 4272 //
     /* 149566 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149569 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149580 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149584 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 149591 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149591 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 149594 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149606 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149610 */   GIR_RootConstrainSelectedInstOperands,
     /* 149611 */   // GIR_Coverage, 4272,
     /* 149611 */   GIR_EraseRootFromParent_Done,
     /* 149612 */ // Label 2634: @149612
     /* 149612 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(149663), // Rule ID 4273 //
     /* 149617 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 149620 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149631 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149635 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 149642 */   // (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149642 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 149645 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149647 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149652 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149657 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149661 */   GIR_RootConstrainSelectedInstOperands,
     /* 149662 */   // GIR_Coverage, 4273,
     /* 149662 */   GIR_EraseRootFromParent_Done,
     /* 149663 */ // Label 2635: @149663
     /* 149663 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(149717), // Rule ID 7691 //
     /* 149668 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149671 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149678 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 149696 */   // (atomic_load:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22263>>  =>  (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 149696 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 149699 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149701 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149706 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149711 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149715 */   GIR_RootConstrainSelectedInstOperands,
     /* 149716 */   // GIR_Coverage, 7691,
     /* 149716 */   GIR_EraseRootFromParent_Done,
     /* 149717 */ // Label 2636: @149717
     /* 149717 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(149771), // Rule ID 7693 //
     /* 149722 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149725 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149732 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149739 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149743 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 149750 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22263>>  =>  (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 149753 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149755 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149760 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149765 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149769 */   GIR_RootConstrainSelectedInstOperands,
     /* 149770 */   // GIR_Coverage, 7693,
     /* 149770 */   GIR_EraseRootFromParent_Done,
     /* 149771 */ // Label 2637: @149771
     /* 149771 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(149825), // Rule ID 7703 //
     /* 149776 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149779 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149786 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149793 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149797 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 149804 */   // (atomic_load:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22271>>  =>  (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 149804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 149807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149809 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149814 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149823 */   GIR_RootConstrainSelectedInstOperands,
     /* 149824 */   // GIR_Coverage, 7703,
     /* 149824 */   GIR_EraseRootFromParent_Done,
     /* 149825 */ // Label 2638: @149825
     /* 149825 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(149879), // Rule ID 7705 //
     /* 149830 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149833 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149840 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149847 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149851 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 149858 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22271>>  =>  (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149858 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 149861 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149873 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149877 */   GIR_RootConstrainSelectedInstOperands,
     /* 149878 */   // GIR_Coverage, 7705,
     /* 149878 */   GIR_EraseRootFromParent_Done,
     /* 149879 */ // Label 2639: @149879
     /* 149879 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(149936), // Rule ID 8097 //
     /* 149884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 149887 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149890 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 149897 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149904 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149908 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 149915 */   // (atomic_load:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22252>>  =>  (LDAPURBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149915 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURBi),
     /* 149918 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149925 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149930 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149934 */   GIR_RootConstrainSelectedInstOperands,
     /* 149935 */   // GIR_Coverage, 8097,
     /* 149935 */   GIR_EraseRootFromParent_Done,
     /* 149936 */ // Label 2640: @149936
     /* 149936 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(149993), // Rule ID 8099 //
     /* 149941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO_UseLDAPUR),
     /* 149944 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 149947 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 149954 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 149957 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 149961 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 149965 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 149972 */   // (atomic_load:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22254>>  =>  (LDAPURHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 149972 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAPURHi),
     /* 149975 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 149977 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 149982 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 149987 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 149991 */   GIR_RootConstrainSelectedInstOperands,
     /* 149992 */   // GIR_Coverage, 8099,
     /* 149992 */   GIR_EraseRootFromParent_Done,
     /* 149993 */ // Label 2641: @149993
     /* 149993 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(150033), // Rule ID 7677 //
     /* 149998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 150001 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150004 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150011 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150018 */   // MIs[0] ptr
     /* 150018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150026 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22252>>  =>  (LDAPRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150026 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRB),
     /* 150031 */   GIR_RootConstrainSelectedInstOperands,
     /* 150032 */   // GIR_Coverage, 7677,
     /* 150032 */   GIR_Done,
     /* 150033 */ // Label 2642: @150033
     /* 150033 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(150073), // Rule ID 7679 //
     /* 150038 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC),
     /* 150041 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150044 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150051 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150058 */   // MIs[0] ptr
     /* 150058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150062 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150066 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22254>>  =>  (LDAPRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150066 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDAPRH),
     /* 150071 */   GIR_RootConstrainSelectedInstOperands,
     /* 150072 */   // GIR_Coverage, 7679,
     /* 150072 */   GIR_Done,
     /* 150073 */ // Label 2643: @150073
     /* 150073 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(150110), // Rule ID 7683 //
     /* 150078 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150081 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150088 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 150091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150095 */   // MIs[0] ptr
     /* 150095 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150099 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150103 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22260>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150103 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 150108 */   GIR_RootConstrainSelectedInstOperands,
     /* 150109 */   // GIR_Coverage, 7683,
     /* 150109 */   GIR_Done,
     /* 150110 */ // Label 2644: @150110
     /* 150110 */ GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(150147), // Rule ID 7685 //
     /* 150115 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150118 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150125 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150132 */   // MIs[0] ptr
     /* 150132 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150136 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150140 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_8>><<P:Predicate_anonymous_22252>>  =>  (LDARB:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150140 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARB),
     /* 150145 */   GIR_RootConstrainSelectedInstOperands,
     /* 150146 */   // GIR_Coverage, 7685,
     /* 150146 */   GIR_Done,
     /* 150147 */ // Label 2645: @150147
     /* 150147 */ GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(150184), // Rule ID 7695 //
     /* 150152 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150155 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150162 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 150165 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150169 */   // MIs[0] ptr
     /* 150169 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150173 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150177 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22268>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150177 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 150182 */   GIR_RootConstrainSelectedInstOperands,
     /* 150183 */   // GIR_Coverage, 7695,
     /* 150183 */   GIR_Done,
     /* 150184 */ // Label 2646: @150184
     /* 150184 */ GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(150221), // Rule ID 7697 //
     /* 150189 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 150192 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150199 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 150202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150206 */   // MIs[0] ptr
     /* 150206 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 150210 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 150214 */   // (atomic_load:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_load_zext>><<P:Predicate_atomic_load_zext_16>><<P:Predicate_anonymous_22254>>  =>  (LDARH:{ *:[i32] } GPR64sp:{ *:[i64] }:$ptr)
     /* 150214 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LDARH),
     /* 150219 */   GIR_RootConstrainSelectedInstOperands,
     /* 150220 */   // GIR_Coverage, 7697,
     /* 150220 */   GIR_Done,
     /* 150221 */ // Label 2647: @150221
     /* 150221 */ GIM_Reject,
     /* 150222 */ // Label 2616: @150222
     /* 150222 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(151711),
     /* 150227 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 150230 */   GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(150315), // Rule ID 4200 //
     /* 150235 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 150257 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 150264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150284 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150288 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150298 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150309 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150314 */     // GIR_Coverage, 4200,
     /* 150314 */     GIR_EraseRootFromParent_Done,
     /* 150315 */   // Label 2649: @150315
     /* 150315 */   GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(150400), // Rule ID 4201 //
     /* 150320 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150335 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 150342 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150342 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150345 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 150349 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150359 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150369 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150373 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150380 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150383 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150389 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150394 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150399 */     // GIR_Coverage, 4201,
     /* 150399 */     GIR_EraseRootFromParent_Done,
     /* 150400 */   // Label 2650: @150400
     /* 150400 */   GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(150485), // Rule ID 4202 //
     /* 150405 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 150427 */     // (ld:{ *:[i64] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150427 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150430 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroW),
     /* 150434 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150439 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150444 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150454 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150458 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150468 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150471 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150474 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150479 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150484 */     // GIR_Coverage, 4202,
     /* 150484 */     GIR_EraseRootFromParent_Done,
     /* 150485 */   // Label 2651: @150485
     /* 150485 */   GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(150570), // Rule ID 4203 //
     /* 150490 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 150497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150501 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150505 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 150512 */     // (ld:{ *:[i64] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150512 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150515 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHroX),
     /* 150519 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150539 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150543 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150550 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150553 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150559 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150564 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150569 */     // GIR_Coverage, 4203,
     /* 150569 */     GIR_EraseRootFromParent_Done,
     /* 150570 */   // Label 2652: @150570
     /* 150570 */   GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(150655), // Rule ID 4204 //
     /* 150575 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150586 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150590 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 150597 */     // (ld:{ *:[i64] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150597 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150600 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroW),
     /* 150604 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150614 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150619 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150624 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150628 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150635 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150638 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150641 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150644 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150649 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150654 */     // GIR_Coverage, 4204,
     /* 150654 */     GIR_EraseRootFromParent_Done,
     /* 150655 */   // Label 2653: @150655
     /* 150655 */   GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(150740), // Rule ID 4205 //
     /* 150660 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 150667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150671 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 150682 */     // (ld:{ *:[i64] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150682 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150685 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWroX),
     /* 150689 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150709 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150713 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150720 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150723 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150729 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150734 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150739 */     // GIR_Coverage, 4205,
     /* 150739 */     GIR_EraseRootFromParent_Done,
     /* 150740 */   // Label 2654: @150740
     /* 150740 */   GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(150825), // Rule ID 4206 //
     /* 150745 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150760 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 150767 */     // (ld:{ *:[i64] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150767 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150770 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroW),
     /* 150774 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150779 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150794 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150798 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150808 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150811 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150814 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150819 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150824 */     // GIR_Coverage, 4206,
     /* 150824 */     GIR_EraseRootFromParent_Done,
     /* 150825 */   // Label 2655: @150825
     /* 150825 */   GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(150910), // Rule ID 4207 //
     /* 150830 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150841 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150845 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 150852 */     // (ld:{ *:[i64] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), sub_32:{ *:[i32] })
     /* 150852 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150855 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBroX),
     /* 150859 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150864 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150869 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 150874 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 150879 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150883 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150893 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150896 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150904 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150909 */     // GIR_Coverage, 4207,
     /* 150909 */     GIR_EraseRootFromParent_Done,
     /* 150910 */   // Label 2656: @150910
     /* 150910 */   GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(150990), // Rule ID 4237 //
     /* 150915 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 150922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150926 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 150930 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 150937 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 150937 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 150940 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 150944 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 150949 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 150954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 150959 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 150963 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 150965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 150968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 150970 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 150973 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 150976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 150979 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 150984 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 150989 */     // GIR_Coverage, 4237,
     /* 150989 */     GIR_EraseRootFromParent_Done,
     /* 150990 */   // Label 2657: @150990
     /* 150990 */   GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(151070), // Rule ID 4238 //
     /* 150995 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 151002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151006 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151010 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 151017 */     // (ld:{ *:[i64] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRHHui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 151017 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151020 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHHui),
     /* 151024 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151029 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151039 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151043 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151053 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151059 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151064 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151069 */     // GIR_Coverage, 4238,
     /* 151069 */     GIR_EraseRootFromParent_Done,
     /* 151070 */   // Label 2658: @151070
     /* 151070 */   GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(151150), // Rule ID 4240 //
     /* 151075 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 151082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151090 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 151097 */     // (ld:{ *:[i64] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRBBui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 151097 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151100 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBBui),
     /* 151104 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151119 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151123 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151130 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151133 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151136 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151139 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151144 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151149 */     // GIR_Coverage, 4240,
     /* 151149 */     GIR_EraseRootFromParent_Done,
     /* 151150 */   // Label 2659: @151150
     /* 151150 */   GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(151230), // Rule ID 4248 //
     /* 151155 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151166 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151170 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 151177 */     // (ld:{ *:[i64] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDRWui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), sub_32:{ *:[i32] })
     /* 151177 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151180 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRWui),
     /* 151184 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151189 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151194 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151199 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151203 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151210 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151213 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151216 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151219 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151224 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151229 */     // GIR_Coverage, 4248,
     /* 151229 */     GIR_EraseRootFromParent_Done,
     /* 151230 */   // Label 2660: @151230
     /* 151230 */   GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(151310), // Rule ID 4274 //
     /* 151235 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 151242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151246 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151250 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 151257 */     // (ld:{ *:[i64] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURWi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURWi),
     /* 151264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151279 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151283 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151293 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151296 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151299 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151304 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151309 */     // GIR_Coverage, 4274,
     /* 151309 */     GIR_EraseRootFromParent_Done,
     /* 151310 */   // Label 2661: @151310
     /* 151310 */   GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(151390), // Rule ID 4275 //
     /* 151315 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 151322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151326 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151330 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 151337 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151337 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151340 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 151344 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151349 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151354 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151359 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151363 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151370 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151373 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151379 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151384 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151389 */     // GIR_Coverage, 4275,
     /* 151389 */     GIR_EraseRootFromParent_Done,
     /* 151390 */   // Label 2662: @151390
     /* 151390 */   GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(151470), // Rule ID 4276 //
     /* 151395 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 151402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151410 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 151417 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151417 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151420 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 151424 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151434 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151439 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151443 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151450 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151453 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151459 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151464 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151469 */     // GIR_Coverage, 4276,
     /* 151469 */     GIR_EraseRootFromParent_Done,
     /* 151470 */   // Label 2663: @151470
     /* 151470 */   GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(151550), // Rule ID 4277 //
     /* 151475 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 151482 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151486 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151490 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 151497 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151497 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151500 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 151504 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151509 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151519 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151523 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151530 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151533 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151539 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151544 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151549 */     // GIR_Coverage, 4277,
     /* 151549 */     GIR_EraseRootFromParent_Done,
     /* 151550 */   // Label 2664: @151550
     /* 151550 */   GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(151630), // Rule ID 4278 //
     /* 151555 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 151562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151566 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151570 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 151577 */     // (ld:{ *:[i64] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURBBi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151577 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151580 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBBi),
     /* 151584 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151594 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151599 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151603 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151613 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151619 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151624 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151629 */     // GIR_Coverage, 4278,
     /* 151629 */     GIR_EraseRootFromParent_Done,
     /* 151630 */   // Label 2665: @151630
     /* 151630 */   GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(151710), // Rule ID 4279 //
     /* 151635 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 151642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 151650 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 151657 */     // (ld:{ *:[i64] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDURHHi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), sub_32:{ *:[i32] })
     /* 151657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 151660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHHi),
     /* 151664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 151674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 151679 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 151683 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 151685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 151690 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 151693 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 151699 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 151704 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 151709 */     // GIR_Coverage, 4279,
     /* 151709 */     GIR_EraseRootFromParent_Done,
     /* 151710 */   // Label 2666: @151710
     /* 151710 */   GIM_Reject,
     /* 151711 */ // Label 2648: @151711
     /* 151711 */ GIM_Reject,
     /* 151712 */ // Label 2617: @151712
     /* 151712 */ GIM_Reject,
     /* 151713 */ // Label 25: @151713
     /* 151713 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(24), /*)*//*default:*//*Label 2687*/ GIMT_Encode4(165538),
     /* 151724 */ /*GILLT_s8*//*Label 2667*/ GIMT_Encode4(151820),
     /* 151728 */ /*GILLT_s16*//*Label 2668*/ GIMT_Encode4(152187),
     /* 151732 */ /*GILLT_s32*//*Label 2669*/ GIMT_Encode4(153326),
     /* 151736 */ /*GILLT_s64*//*Label 2670*/ GIMT_Encode4(158021),
     /* 151740 */ /*GILLT_s128*//*Label 2671*/ GIMT_Encode4(161990),
     /* 151744 */ /*GILLT_v2s32*//*Label 2672*/ GIMT_Encode4(162196),
     /* 151748 */ /*GILLT_v2s64*//*Label 2673*/ GIMT_Encode4(162602),
     /* 151752 */ /*GILLT_v4s16*//*Label 2674*/ GIMT_Encode4(163052),
     /* 151756 */ /*GILLT_v4s32*//*Label 2675*/ GIMT_Encode4(163458),
     /* 151760 */ /*GILLT_v8s8*//*Label 2676*/ GIMT_Encode4(163864),
     /* 151764 */ /*GILLT_v8s16*//*Label 2677*/ GIMT_Encode4(164084),
     /* 151768 */ /*GILLT_v16s8*//*Label 2678*/ GIMT_Encode4(164490), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 151780 */ /*GILLT_nxv2s16*//*Label 2679*/ GIMT_Encode4(164710),
     /* 151784 */ /*GILLT_nxv2s32*//*Label 2680*/ GIMT_Encode4(164770),
     /* 151788 */ /*GILLT_nxv2s64*//*Label 2681*/ GIMT_Encode4(164830), GIMT_Encode4(0),
     /* 151796 */ /*GILLT_nxv4s16*//*Label 2682*/ GIMT_Encode4(165000),
     /* 151800 */ /*GILLT_nxv4s32*//*Label 2683*/ GIMT_Encode4(165060), GIMT_Encode4(0),
     /* 151808 */ /*GILLT_nxv8s16*//*Label 2684*/ GIMT_Encode4(165230),
     /* 151812 */ /*GILLT_nxv16s1*//*Label 2685*/ GIMT_Encode4(165400),
     /* 151816 */ /*GILLT_nxv16s8*//*Label 2686*/ GIMT_Encode4(165444),
     /* 151820 */ // Label 2667: @151820
     /* 151820 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(152186),
     /* 151825 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 151828 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 151832 */   GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(151900), // Rule ID 14248 //
     /* 151837 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 151841 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 151845 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 151849 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 151853 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 151858 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 151862 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 151866 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 151870 */     // MIs[2] Operand 1
     /* 151870 */     // No operand predicates
     /* 151870 */     // MIs[0] Rn
     /* 151870 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151874 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151878 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 151880 */     // (st (vector_extract:{ *:[i8] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 151880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 151883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 151887 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 151890 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 151898 */     GIR_RootConstrainSelectedInstOperands,
     /* 151899 */     // GIR_Coverage, 14248,
     /* 151899 */     GIR_EraseRootFromParent_Done,
     /* 151900 */   // Label 2689: @151900
     /* 151900 */   GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(151999), // Rule ID 14249 //
     /* 151905 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 151909 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 151913 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 151917 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 151921 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 151926 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 151930 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 151934 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 151938 */     // MIs[2] Operand 1
     /* 151938 */     // No operand predicates
     /* 151938 */     // MIs[0] Rn
     /* 151938 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 151942 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 151946 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 151948 */     // (st (vector_extract:{ *:[i8] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 151948 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 151951 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 151955 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 151960 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 151963 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 151967 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 151970 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 151975 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 151980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 151983 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 151986 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 151989 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 151991 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 151997 */     GIR_RootConstrainSelectedInstOperands,
     /* 151998 */     // GIR_Coverage, 14249,
     /* 151998 */     GIR_EraseRootFromParent_Done,
     /* 151999 */   // Label 2690: @151999
     /* 151999 */   GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(152048), // Rule ID 297 //
     /* 152004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 152007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 152011 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152015 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 152022 */     // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBroW FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 152022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroW),
     /* 152025 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 152027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152037 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152042 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152046 */     GIR_RootConstrainSelectedInstOperands,
     /* 152047 */     // GIR_Coverage, 297,
     /* 152047 */     GIR_EraseRootFromParent_Done,
     /* 152048 */   // Label 2691: @152048
     /* 152048 */   GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(152097), // Rule ID 298 //
     /* 152053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 152056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 152060 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 152071 */     // (st FPR8Op:{ *:[i8] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBroX FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 152071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBroX),
     /* 152074 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 152076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152091 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152095 */     GIR_RootConstrainSelectedInstOperands,
     /* 152096 */     // GIR_Coverage, 298,
     /* 152096 */     GIR_EraseRootFromParent_Done,
     /* 152097 */   // Label 2692: @152097
     /* 152097 */   GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(152141), // Rule ID 307 //
     /* 152102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 152105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 152109 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152113 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 152120 */     // (st FPR8Op:{ *:[i8] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRBui FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 152120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBui),
     /* 152123 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 152125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152130 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152135 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152139 */     GIR_RootConstrainSelectedInstOperands,
     /* 152140 */     // GIR_Coverage, 307,
     /* 152140 */     GIR_EraseRootFromParent_Done,
     /* 152141 */   // Label 2693: @152141
     /* 152141 */   GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(152185), // Rule ID 315 //
     /* 152146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 152149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 152153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152157 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 152164 */     // (st FPR8Op:{ *:[i8] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURBi FPR8Op:{ *:[i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 152164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBi),
     /* 152167 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 152169 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 152183 */     GIR_RootConstrainSelectedInstOperands,
     /* 152184 */     // GIR_Coverage, 315,
     /* 152184 */     GIR_EraseRootFromParent_Done,
     /* 152185 */   // Label 2694: @152185
     /* 152185 */   GIM_Reject,
     /* 152186 */ // Label 2688: @152186
     /* 152186 */ GIM_Reject,
     /* 152187 */ // Label 2668: @152187
     /* 152187 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(153325),
     /* 152192 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 152195 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 152199 */   GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(152298), // Rule ID 4704 //
     /* 152204 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152208 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152212 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 152216 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152220 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152225 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152233 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152235 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 152242 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 152242 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152245 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152249 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152254 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152260 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152265 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 152273 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152286 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152291 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152296 */     GIR_RootConstrainSelectedInstOperands,
     /* 152297 */     // GIR_Coverage, 4704,
     /* 152297 */     GIR_EraseRootFromParent_Done,
     /* 152298 */   // Label 2696: @152298
     /* 152298 */   GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(152397), // Rule ID 4705 //
     /* 152303 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152307 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152311 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 152315 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152319 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152324 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152328 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152332 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152334 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 152341 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 152341 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152344 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152348 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152353 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152359 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152364 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 152372 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152375 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152380 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152385 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152390 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152395 */     GIR_RootConstrainSelectedInstOperands,
     /* 152396 */     // GIR_Coverage, 4705,
     /* 152396 */     GIR_EraseRootFromParent_Done,
     /* 152397 */   // Label 2697: @152397
     /* 152397 */   GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(152496), // Rule ID 14246 //
     /* 152402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 152414 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152418 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152423 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152427 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152431 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152433 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 152440 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 152440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152452 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152458 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152463 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 152471 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152474 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152479 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152484 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152489 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152494 */     GIR_RootConstrainSelectedInstOperands,
     /* 152495 */     // GIR_Coverage, 14246,
     /* 152495 */     GIR_EraseRootFromParent_Done,
     /* 152496 */   // Label 2698: @152496
     /* 152496 */   GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(152595), // Rule ID 14247 //
     /* 152501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 152513 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152522 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152526 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152530 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152532 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 152539 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 152539 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152542 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152546 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152551 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152557 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152562 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 152570 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 152583 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 152588 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152593 */     GIR_RootConstrainSelectedInstOperands,
     /* 152594 */     // GIR_Coverage, 14247,
     /* 152594 */     GIR_EraseRootFromParent_Done,
     /* 152595 */   // Label 2699: @152595
     /* 152595 */   GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(152689), // Rule ID 4738 //
     /* 152600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 152612 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152616 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152621 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152629 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152631 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 152638 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 152638 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152641 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152645 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152650 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152656 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152661 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 152669 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152687 */     GIR_RootConstrainSelectedInstOperands,
     /* 152688 */     // GIR_Coverage, 4738,
     /* 152688 */     GIR_EraseRootFromParent_Done,
     /* 152689 */   // Label 2700: @152689
     /* 152689 */   GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(152783), // Rule ID 4765 //
     /* 152694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 152706 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152710 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152715 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152719 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152723 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152725 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 152732 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 152732 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152735 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152739 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152744 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152750 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152755 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 152763 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152766 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152771 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152776 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152781 */     GIR_RootConstrainSelectedInstOperands,
     /* 152782 */     // GIR_Coverage, 4765,
     /* 152782 */     GIR_EraseRootFromParent_Done,
     /* 152783 */   // Label 2701: @152783
     /* 152783 */   GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(152877), // Rule ID 14245 //
     /* 152788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 152800 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152804 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152809 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152817 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152819 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 152826 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 152826 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152829 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152833 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152838 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152844 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152849 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 152857 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152870 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152875 */     GIR_RootConstrainSelectedInstOperands,
     /* 152876 */     // GIR_Coverage, 14245,
     /* 152876 */     GIR_EraseRootFromParent_Done,
     /* 152877 */   // Label 2702: @152877
     /* 152877 */   GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(152971), // Rule ID 14251 //
     /* 152882 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152886 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152890 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 152894 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152898 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152903 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 152907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 152911 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 152913 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 152920 */     // (st (vector_extract:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[i16] } VecListOne64:{ *:[v4i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 152920 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 152923 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 152927 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 152932 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 152938 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 152943 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 152948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 152951 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 152954 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 152959 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 152964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 152969 */     GIR_RootConstrainSelectedInstOperands,
     /* 152970 */     // GIR_Coverage, 14251,
     /* 152970 */     GIR_EraseRootFromParent_Done,
     /* 152971 */   // Label 2703: @152971
     /* 152971 */   GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(153039), // Rule ID 7106 //
     /* 152976 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 152980 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 152984 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 152988 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 152992 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 152997 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 153001 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 153005 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 153009 */     // MIs[2] Operand 1
     /* 153009 */     // No operand predicates
     /* 153009 */     // MIs[0] Rn
     /* 153009 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153013 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153017 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 153019 */     // (st (vector_extract:{ *:[f16] } VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i16 VecListOne128:{ *:[v8f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 153019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 153022 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 153026 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 153029 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153031 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 153037 */     GIR_RootConstrainSelectedInstOperands,
     /* 153038 */     // GIR_Coverage, 7106,
     /* 153038 */     GIR_EraseRootFromParent_Done,
     /* 153039 */   // Label 2704: @153039
     /* 153039 */   GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(153138), // Rule ID 7111 //
     /* 153044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 153056 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153060 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 153065 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 153069 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 153073 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 153077 */     // MIs[2] Operand 1
     /* 153077 */     // No operand predicates
     /* 153077 */     // MIs[0] Rn
     /* 153077 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 153081 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 153085 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 153087 */     // (st (vector_extract:{ *:[f16] } VecListOne64:{ *:[v4f16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 153087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 153090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 153094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153099 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 153102 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 153106 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 153109 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153114 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 153119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 153122 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153125 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 153128 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 153130 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 153136 */     GIR_RootConstrainSelectedInstOperands,
     /* 153137 */     // GIR_Coverage, 7111,
     /* 153137 */     GIR_EraseRootFromParent_Done,
     /* 153138 */   // Label 2705: @153138
     /* 153138 */   GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(153187), // Rule ID 299 //
     /* 153143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 153146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153150 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153154 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 153161 */     // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroW FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 153161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 153164 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 153166 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153171 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153176 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153181 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153185 */     GIR_RootConstrainSelectedInstOperands,
     /* 153186 */     // GIR_Coverage, 299,
     /* 153186 */     GIR_EraseRootFromParent_Done,
     /* 153187 */   // Label 2706: @153187
     /* 153187 */   GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(153236), // Rule ID 300 //
     /* 153192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 153195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153199 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153203 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 153210 */     // (st FPR16Op:{ *:[f16] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHroX FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 153210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 153213 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 153215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153220 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153225 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153234 */     GIR_RootConstrainSelectedInstOperands,
     /* 153235 */     // GIR_Coverage, 300,
     /* 153235 */     GIR_EraseRootFromParent_Done,
     /* 153236 */   // Label 2707: @153236
     /* 153236 */   GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(153280), // Rule ID 308 //
     /* 153241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 153244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153248 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153252 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 153259 */     // (st FPR16Op:{ *:[f16] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRHui FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 153259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 153262 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 153264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153269 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 153274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153278 */     GIR_RootConstrainSelectedInstOperands,
     /* 153279 */     // GIR_Coverage, 308,
     /* 153279 */     GIR_EraseRootFromParent_Done,
     /* 153280 */   // Label 2708: @153280
     /* 153280 */   GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(153324), // Rule ID 316 //
     /* 153285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 153288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153292 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153296 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 153303 */     // (st FPR16Op:{ *:[f16] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURHi FPR16Op:{ *:[f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 153303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 153306 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 153308 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153313 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 153318 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 153322 */     GIR_RootConstrainSelectedInstOperands,
     /* 153323 */     // GIR_Coverage, 316,
     /* 153323 */     GIR_EraseRootFromParent_Done,
     /* 153324 */   // Label 2709: @153324
     /* 153324 */   GIM_Reject,
     /* 153325 */ // Label 2695: @153325
     /* 153325 */ GIM_Reject,
     /* 153326 */ // Label 2669: @153326
     /* 153326 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(153439), // Rule ID 4702 //
     /* 153331 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153334 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153338 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153345 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153349 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153353 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 153357 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153361 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153366 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153370 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153374 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153376 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 153383 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHroW (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 153383 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 153386 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153390 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153395 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 153401 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153406 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroW),
     /* 153414 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153417 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153422 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153432 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153437 */   GIR_RootConstrainSelectedInstOperands,
     /* 153438 */   // GIR_Coverage, 4702,
     /* 153438 */   GIR_EraseRootFromParent_Done,
     /* 153439 */ // Label 2710: @153439
     /* 153439 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(153552), // Rule ID 4703 //
     /* 153444 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153447 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153451 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 153458 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153462 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153466 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 153470 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153474 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153479 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153483 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153487 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153489 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 153496 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHroX (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 153496 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 153499 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153503 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153508 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 153514 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 153519 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153524 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHroX),
     /* 153527 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153545 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153550 */   GIR_RootConstrainSelectedInstOperands,
     /* 153551 */   // GIR_Coverage, 4703,
     /* 153551 */   GIR_EraseRootFromParent_Done,
     /* 153552 */ // Label 2711: @153552
     /* 153552 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(153658), // Rule ID 4706 //
     /* 153557 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153560 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153564 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153568 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153572 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 153576 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153580 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153585 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153589 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153593 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153595 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 153602 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 153602 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 153605 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153609 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153614 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 153620 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 153625 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153630 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 153633 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153636 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153651 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153656 */   GIR_RootConstrainSelectedInstOperands,
     /* 153657 */   // GIR_Coverage, 4706,
     /* 153657 */   GIR_EraseRootFromParent_Done,
     /* 153658 */ // Label 2712: @153658
     /* 153658 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(153764), // Rule ID 4707 //
     /* 153663 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153666 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153670 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153674 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153678 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 153682 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153686 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153691 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153695 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153699 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153701 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 153708 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 153708 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 153711 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153715 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153720 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 153726 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 153731 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153736 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 153739 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153742 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153747 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153752 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153757 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153762 */   GIR_RootConstrainSelectedInstOperands,
     /* 153763 */   // GIR_Coverage, 4707,
     /* 153763 */   GIR_EraseRootFromParent_Done,
     /* 153764 */ // Label 2713: @153764
     /* 153764 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(153870), // Rule ID 4708 //
     /* 153769 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153772 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153776 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153780 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153784 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 153788 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153792 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153797 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153801 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153805 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153807 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 153814 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 153814 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 153817 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153821 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153826 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 153832 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 153837 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 153845 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153848 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153853 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153858 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153863 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153868 */   GIR_RootConstrainSelectedInstOperands,
     /* 153869 */   // GIR_Coverage, 4708,
     /* 153869 */   GIR_EraseRootFromParent_Done,
     /* 153870 */ // Label 2714: @153870
     /* 153870 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(153976), // Rule ID 4709 //
     /* 153875 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153878 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153882 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153886 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153890 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 153894 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 153898 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153903 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 153907 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 153911 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 153913 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 153920 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 153920 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 153923 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 153927 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 153932 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 153938 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 153943 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 153948 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 153951 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 153954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 153959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 153964 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 153969 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 153974 */   GIR_RootConstrainSelectedInstOperands,
     /* 153975 */   // GIR_Coverage, 4709,
     /* 153975 */   GIR_EraseRootFromParent_Done,
     /* 153976 */ // Label 2715: @153976
     /* 153976 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(154082), // Rule ID 14253 //
     /* 153981 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 153984 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 153988 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 153992 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 153996 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 154000 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154004 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154009 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154013 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154017 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 154026 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 154026 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154029 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154033 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154038 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154044 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154049 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 154057 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154060 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154065 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 154070 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 154075 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154080 */   GIR_RootConstrainSelectedInstOperands,
     /* 154081 */   // GIR_Coverage, 14253,
     /* 154081 */   GIR_EraseRootFromParent_Done,
     /* 154082 */ // Label 2716: @154082
     /* 154082 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(154188), // Rule ID 14254 //
     /* 154087 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154090 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154094 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154098 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154102 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 154106 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154110 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154115 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154119 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154123 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154125 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 154132 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 154132 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154135 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154139 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154144 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154150 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154155 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 154163 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154166 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154171 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 154176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 154181 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154186 */   GIR_RootConstrainSelectedInstOperands,
     /* 154187 */   // GIR_Coverage, 14254,
     /* 154187 */   GIR_EraseRootFromParent_Done,
     /* 154188 */ // Label 2717: @154188
     /* 154188 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(154296), // Rule ID 4737 //
     /* 154193 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154196 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154200 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154207 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154211 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154215 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 154219 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154223 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154228 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154232 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154236 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 154245 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 154245 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 154248 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154252 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154257 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 154263 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 154268 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 154276 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154279 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154284 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154289 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154294 */   GIR_RootConstrainSelectedInstOperands,
     /* 154295 */   // GIR_Coverage, 4737,
     /* 154295 */   GIR_EraseRootFromParent_Done,
     /* 154296 */ // Label 2718: @154296
     /* 154296 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(154397), // Rule ID 4739 //
     /* 154301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154304 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154316 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 154320 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154324 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154329 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154333 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154337 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154339 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 154346 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 154346 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154349 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154353 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154358 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154364 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154369 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 154377 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154380 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154385 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154390 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154395 */   GIR_RootConstrainSelectedInstOperands,
     /* 154396 */   // GIR_Coverage, 4739,
     /* 154396 */   GIR_EraseRootFromParent_Done,
     /* 154397 */ // Label 2719: @154397
     /* 154397 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(154498), // Rule ID 4740 //
     /* 154402 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154405 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154409 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154413 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154417 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 154421 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154425 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154430 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154434 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154438 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 154447 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 154447 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154450 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154454 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154459 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154465 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154470 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154475 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 154478 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154481 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154486 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154491 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154496 */   GIR_RootConstrainSelectedInstOperands,
     /* 154497 */   // GIR_Coverage, 4740,
     /* 154497 */   GIR_EraseRootFromParent_Done,
     /* 154498 */ // Label 2720: @154498
     /* 154498 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(154606), // Rule ID 4764 //
     /* 154503 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154506 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154510 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 154517 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154521 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154525 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 154529 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154533 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154538 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154542 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154546 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154548 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 154555 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHi (EXTRACT_SUBREG:{ *:[f16] } VecListOne128:{ *:[v8i16] }:$Vt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 154555 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 154558 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154562 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154567 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Vt
     /* 154573 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 154578 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154583 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHi),
     /* 154586 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154589 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154594 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154599 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154604 */   GIR_RootConstrainSelectedInstOperands,
     /* 154605 */   // GIR_Coverage, 4764,
     /* 154605 */   GIR_EraseRootFromParent_Done,
     /* 154606 */ // Label 2721: @154606
     /* 154606 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(154707), // Rule ID 4766 //
     /* 154611 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154614 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154618 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154622 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154626 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 154630 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154634 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154639 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154643 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154647 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154649 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 154656 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 154656 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154659 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154663 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154668 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154674 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154679 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 154687 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154690 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154695 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154700 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154705 */   GIR_RootConstrainSelectedInstOperands,
     /* 154706 */   // GIR_Coverage, 4766,
     /* 154706 */   GIR_EraseRootFromParent_Done,
     /* 154707 */ // Label 2722: @154707
     /* 154707 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(154808), // Rule ID 4767 //
     /* 154712 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154715 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154719 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154723 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154727 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 154731 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154735 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154740 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154744 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154748 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154750 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 154757 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne128:{ *:[v4f32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 154757 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154760 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154764 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154769 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154775 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154780 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 154785 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 154788 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154791 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154796 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154801 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154806 */   GIR_RootConstrainSelectedInstOperands,
     /* 154807 */   // GIR_Coverage, 4767,
     /* 154807 */   GIR_EraseRootFromParent_Done,
     /* 154808 */ // Label 2723: @154808
     /* 154808 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(154909), // Rule ID 14250 //
     /* 154813 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154816 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154820 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154824 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154828 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 154832 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154836 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154841 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154849 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154851 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 154858 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 154858 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154861 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154865 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154870 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154876 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154881 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154886 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 154889 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154892 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154897 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 154902 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 154907 */   GIR_RootConstrainSelectedInstOperands,
     /* 154908 */   // GIR_Coverage, 14250,
     /* 154908 */   GIR_EraseRootFromParent_Done,
     /* 154909 */ // Label 2724: @154909
     /* 154909 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(155010), // Rule ID 14252 //
     /* 154914 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 154917 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 154921 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 154925 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 154929 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 154933 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 154937 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154942 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 154946 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 154950 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 154952 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 154959 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, 0:{ *:[i64] }), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi (EXTRACT_SUBREG:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 154959 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 154962 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 154966 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 154971 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Vt
     /* 154977 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 154982 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 154987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 154990 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 154993 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 154998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 155003 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 155008 */   GIR_RootConstrainSelectedInstOperands,
     /* 155009 */   // GIR_Coverage, 14252,
     /* 155009 */   GIR_EraseRootFromParent_Done,
     /* 155010 */ // Label 2725: @155010
     /* 155010 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(155092), // Rule ID 7100 //
     /* 155015 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155018 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155022 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155029 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155033 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155037 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 155041 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155045 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155050 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155054 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155058 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 155062 */   // MIs[2] Operand 1
     /* 155062 */   // No operand predicates
     /* 155062 */   // MIs[0] Rn
     /* 155062 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155066 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155070 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155072 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (ST1i8 VecListOne128:{ *:[v16i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155072 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 155075 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155079 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155082 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155084 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155090 */   GIR_RootConstrainSelectedInstOperands,
     /* 155091 */   // GIR_Coverage, 7100,
     /* 155091 */   GIR_EraseRootFromParent_Done,
     /* 155092 */ // Label 2726: @155092
     /* 155092 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(155174), // Rule ID 7101 //
     /* 155097 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155100 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155104 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155111 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155115 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155119 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 155123 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155127 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155132 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155136 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155140 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 155144 */   // MIs[2] Operand 1
     /* 155144 */   // No operand predicates
     /* 155144 */   // MIs[0] Rn
     /* 155144 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155148 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155152 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155154 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (ST1i16 VecListOne128:{ *:[v8i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 155157 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155161 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155164 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155166 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155172 */   GIR_RootConstrainSelectedInstOperands,
     /* 155173 */   // GIR_Coverage, 7101,
     /* 155173 */   GIR_EraseRootFromParent_Done,
     /* 155174 */ // Label 2727: @155174
     /* 155174 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(155249), // Rule ID 7102 //
     /* 155179 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155182 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155186 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155190 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155194 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 155198 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155202 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155207 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155211 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155215 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 155219 */   // MIs[2] Operand 1
     /* 155219 */   // No operand predicates
     /* 155219 */   // MIs[0] Rn
     /* 155219 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155223 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155227 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155229 */   // (st (vector_extract:{ *:[i32] } VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 VecListOne128:{ *:[v4i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 155232 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155236 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155239 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155241 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155247 */   GIR_RootConstrainSelectedInstOperands,
     /* 155248 */   // GIR_Coverage, 7102,
     /* 155248 */   GIR_EraseRootFromParent_Done,
     /* 155249 */ // Label 2728: @155249
     /* 155249 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(155324), // Rule ID 7103 //
     /* 155254 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155257 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155261 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155265 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155269 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 155273 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155277 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155282 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155286 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155290 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 155294 */   // MIs[2] Operand 1
     /* 155294 */   // No operand predicates
     /* 155294 */   // MIs[0] Rn
     /* 155294 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155298 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155302 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155304 */   // (st (vector_extract:{ *:[f32] } VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 VecListOne128:{ *:[v4f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155304 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 155307 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155311 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155314 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155316 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155322 */   GIR_RootConstrainSelectedInstOperands,
     /* 155323 */   // GIR_Coverage, 7103,
     /* 155323 */   GIR_EraseRootFromParent_Done,
     /* 155324 */ // Label 2729: @155324
     /* 155324 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(155437), // Rule ID 7107 //
     /* 155329 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155332 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155336 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155343 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155347 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155351 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 155355 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155359 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155364 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155368 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155372 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 155376 */   // MIs[2] Operand 1
     /* 155376 */   // No operand predicates
     /* 155376 */   // MIs[0] Rn
     /* 155376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155380 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155384 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155386 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v8i8] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (ST1i8 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155386 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 155389 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 155393 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 155398 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 155401 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155405 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 155408 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155413 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155418 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i8),
     /* 155421 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 155424 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155427 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155429 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155435 */   GIR_RootConstrainSelectedInstOperands,
     /* 155436 */   // GIR_Coverage, 7107,
     /* 155436 */   GIR_EraseRootFromParent_Done,
     /* 155437 */ // Label 2730: @155437
     /* 155437 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(155550), // Rule ID 7108 //
     /* 155442 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155445 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155449 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155456 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155460 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155464 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 155468 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155472 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155477 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155481 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155485 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 155489 */   // MIs[2] Operand 1
     /* 155489 */   // No operand predicates
     /* 155489 */   // MIs[0] Rn
     /* 155489 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155493 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155497 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155499 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v4i16] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (ST1i16 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155499 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 155502 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 155506 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 155511 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 155514 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155518 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 155521 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155526 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i16),
     /* 155534 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 155537 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155540 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155542 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155548 */   GIR_RootConstrainSelectedInstOperands,
     /* 155549 */   // GIR_Coverage, 7108,
     /* 155549 */   GIR_EraseRootFromParent_Done,
     /* 155550 */ // Label 2731: @155550
     /* 155550 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(155656), // Rule ID 7109 //
     /* 155555 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155558 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155562 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155566 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155570 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 155574 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155578 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155583 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155587 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155591 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 155595 */   // MIs[2] Operand 1
     /* 155595 */   // No operand predicates
     /* 155595 */   // MIs[0] Rn
     /* 155595 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155599 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155603 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155605 */   // (st (vector_extract:{ *:[i32] } VecListOne64:{ *:[v2i32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155605 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 155608 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 155612 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 155617 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 155620 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155624 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 155627 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155632 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 155640 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 155643 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155646 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155648 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155654 */   GIR_RootConstrainSelectedInstOperands,
     /* 155655 */   // GIR_Coverage, 7109,
     /* 155655 */   GIR_EraseRootFromParent_Done,
     /* 155656 */ // Label 2732: @155656
     /* 155656 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(155762), // Rule ID 7110 //
     /* 155661 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155664 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155668 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 155672 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 155676 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 155680 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 155684 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155689 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 155693 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 155697 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 155701 */   // MIs[2] Operand 1
     /* 155701 */   // No operand predicates
     /* 155701 */   // MIs[0] Rn
     /* 155701 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 155705 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 155709 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 155711 */   // (st (vector_extract:{ *:[f32] } VecListOne64:{ *:[v2f32] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i32 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Vt, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 155711 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 155714 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 155718 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 155723 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 155726 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 155730 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 155733 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 155738 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 155743 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i32),
     /* 155746 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 155749 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 155752 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 155754 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 155760 */   GIR_RootConstrainSelectedInstOperands,
     /* 155761 */   // GIR_Coverage, 7110,
     /* 155761 */   GIR_EraseRootFromParent_Done,
     /* 155762 */ // Label 2733: @155762
     /* 155762 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(155822), // Rule ID 289 //
     /* 155767 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155770 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155774 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155781 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 155789 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 155796 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 155796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 155799 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 155801 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 155806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 155811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 155816 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155820 */   GIR_RootConstrainSelectedInstOperands,
     /* 155821 */   // GIR_Coverage, 289,
     /* 155821 */   GIR_EraseRootFromParent_Done,
     /* 155822 */ // Label 2734: @155822
     /* 155822 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(155882), // Rule ID 290 //
     /* 155827 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155830 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155834 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 155841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155845 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 155849 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 155856 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 155856 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 155859 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 155861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 155866 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 155871 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 155876 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155880 */   GIR_RootConstrainSelectedInstOperands,
     /* 155881 */   // GIR_Coverage, 290,
     /* 155881 */   GIR_EraseRootFromParent_Done,
     /* 155882 */ // Label 2735: @155882
     /* 155882 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(155942), // Rule ID 291 //
     /* 155887 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155890 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155894 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155901 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155905 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 155909 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 155916 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 155916 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 155919 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 155921 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 155926 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 155931 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 155936 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 155940 */   GIR_RootConstrainSelectedInstOperands,
     /* 155941 */   // GIR_Coverage, 291,
     /* 155941 */   GIR_EraseRootFromParent_Done,
     /* 155942 */ // Label 2736: @155942
     /* 155942 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(156002), // Rule ID 292 //
     /* 155947 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 155950 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 155954 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 155961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 155965 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 155969 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 155976 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 155976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 155979 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 155981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 155986 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 155991 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 155996 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156000 */   GIR_RootConstrainSelectedInstOperands,
     /* 156001 */   // GIR_Coverage, 292,
     /* 156001 */   GIR_EraseRootFromParent_Done,
     /* 156002 */ // Label 2737: @156002
     /* 156002 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(156055), // Rule ID 293 //
     /* 156007 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156010 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156018 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156022 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 156029 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWroW GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 156029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 156032 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 156034 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156039 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156049 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156053 */   GIR_RootConstrainSelectedInstOperands,
     /* 156054 */   // GIR_Coverage, 293,
     /* 156054 */   GIR_EraseRootFromParent_Done,
     /* 156055 */ // Label 2738: @156055
     /* 156055 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(156108), // Rule ID 294 //
     /* 156060 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156063 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156071 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156075 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 156082 */   // (st GPR32:{ *:[i32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWroX GPR32:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 156082 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 156085 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 156087 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156092 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156097 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156102 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156106 */   GIR_RootConstrainSelectedInstOperands,
     /* 156107 */   // GIR_Coverage, 294,
     /* 156107 */   GIR_EraseRootFromParent_Done,
     /* 156108 */ // Label 2739: @156108
     /* 156108 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(156164), // Rule ID 301 //
     /* 156113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 156116 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156119 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156127 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156131 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 156138 */   // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroW FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 156138 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 156141 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 156143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156153 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156158 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156162 */   GIR_RootConstrainSelectedInstOperands,
     /* 156163 */   // GIR_Coverage, 301,
     /* 156163 */   GIR_EraseRootFromParent_Done,
     /* 156164 */ // Label 2740: @156164
     /* 156164 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(156220), // Rule ID 302 //
     /* 156169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 156172 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156175 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156183 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156187 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 156194 */   // (st FPR32Op:{ *:[f32] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSroX FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 156194 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 156197 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 156199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156214 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156218 */   GIR_RootConstrainSelectedInstOperands,
     /* 156219 */   // GIR_Coverage, 302,
     /* 156219 */   GIR_EraseRootFromParent_Done,
     /* 156220 */ // Label 2741: @156220
     /* 156220 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(156320), // Rule ID 4731 //
     /* 156225 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156228 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156232 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156239 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 156243 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 156247 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 156251 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156256 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156260 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 156262 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 156269 */   // (st (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rt), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$off))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[f32] }:$Rt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$off)
     /* 156269 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 156272 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 156276 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 156281 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rt
     /* 156287 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 156292 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 156300 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 156303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156308 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // off
     /* 156313 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 156318 */   GIR_RootConstrainSelectedInstOperands,
     /* 156319 */   // GIR_Coverage, 4731,
     /* 156319 */   GIR_EraseRootFromParent_Done,
     /* 156320 */ // Label 2742: @156320
     /* 156320 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(156372), // Rule ID 306 //
     /* 156325 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156328 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156332 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156336 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156340 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 156347 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRWui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 156347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 156350 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 156356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156361 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 156366 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156370 */   GIR_RootConstrainSelectedInstOperands,
     /* 156371 */   // GIR_Coverage, 306,
     /* 156371 */   GIR_EraseRootFromParent_Done,
     /* 156372 */ // Label 2743: @156372
     /* 156372 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(156423), // Rule ID 309 //
     /* 156377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 156380 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156383 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156387 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156391 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156395 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 156402 */   // (st FPR32Op:{ *:[f32] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRSui FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 156402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 156405 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 156407 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156412 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 156417 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156421 */   GIR_RootConstrainSelectedInstOperands,
     /* 156422 */   // GIR_Coverage, 309,
     /* 156422 */   GIR_EraseRootFromParent_Done,
     /* 156423 */ // Label 2744: @156423
     /* 156423 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(156482), // Rule ID 311 //
     /* 156428 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156431 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156435 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156446 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156450 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 156457 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 156457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 156460 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 156466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156471 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 156476 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156480 */   GIR_RootConstrainSelectedInstOperands,
     /* 156481 */   // GIR_Coverage, 311,
     /* 156481 */   GIR_EraseRootFromParent_Done,
     /* 156482 */ // Label 2745: @156482
     /* 156482 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(156541), // Rule ID 312 //
     /* 156487 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 156490 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 156494 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156505 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156509 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 156516 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBui GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 156516 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 156519 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 156525 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156530 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 156535 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156539 */   GIR_RootConstrainSelectedInstOperands,
     /* 156540 */   // GIR_Coverage, 312,
     /* 156540 */   GIR_EraseRootFromParent_Done,
     /* 156541 */ // Label 2746: @156541
     /* 156541 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(156618), // Rule ID 7746 //
     /* 156546 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156549 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156556 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156559 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 156563 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 156567 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 156571 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156576 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156580 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 156582 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 156589 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRSroW FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 156589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroW),
     /* 156592 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 156596 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156601 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156606 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156611 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 156616 */   GIR_RootConstrainSelectedInstOperands,
     /* 156617 */   // GIR_Coverage, 7746,
     /* 156617 */   GIR_EraseRootFromParent_Done,
     /* 156618 */ // Label 2747: @156618
     /* 156618 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(156695), // Rule ID 7747 //
     /* 156623 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156626 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156633 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156636 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 156640 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 156644 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 156648 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 156653 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156657 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 156659 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 156666 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRSroX FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 156666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSroX),
     /* 156669 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 156673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156678 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156683 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156688 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 156693 */   GIR_RootConstrainSelectedInstOperands,
     /* 156694 */   // GIR_Coverage, 7747,
     /* 156694 */   GIR_EraseRootFromParent_Done,
     /* 156695 */ // Label 2748: @156695
     /* 156695 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(156754), // Rule ID 7727 //
     /* 156700 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156703 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156710 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156717 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156721 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 156728 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22302>>  =>  (STRBBroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 156728 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 156731 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 156733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156738 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156743 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156748 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156752 */   GIR_RootConstrainSelectedInstOperands,
     /* 156753 */   // GIR_Coverage, 7727,
     /* 156753 */   GIR_EraseRootFromParent_Done,
     /* 156754 */ // Label 2749: @156754
     /* 156754 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(156813), // Rule ID 7728 //
     /* 156759 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156762 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 156769 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156772 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156776 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156780 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 156787 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22302>>  =>  (STRBBroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 156787 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 156790 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 156792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156802 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156807 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156811 */   GIR_RootConstrainSelectedInstOperands,
     /* 156812 */   // GIR_Coverage, 7728,
     /* 156812 */   GIR_EraseRootFromParent_Done,
     /* 156813 */ // Label 2750: @156813
     /* 156813 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(156872), // Rule ID 7732 //
     /* 156818 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156821 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156828 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156831 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156835 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156839 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 156846 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22309>>  =>  (STRHHroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 156846 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 156849 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 156851 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156856 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156861 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156866 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156870 */   GIR_RootConstrainSelectedInstOperands,
     /* 156871 */   // GIR_Coverage, 7732,
     /* 156871 */   GIR_EraseRootFromParent_Done,
     /* 156872 */ // Label 2751: @156872
     /* 156872 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(156931), // Rule ID 7733 //
     /* 156877 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156880 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 156887 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156898 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 156905 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22309>>  =>  (STRHHroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 156905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 156908 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 156910 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156915 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156920 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156925 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156929 */   GIR_RootConstrainSelectedInstOperands,
     /* 156930 */   // GIR_Coverage, 7733,
     /* 156930 */   GIR_EraseRootFromParent_Done,
     /* 156931 */ // Label 2752: @156931
     /* 156931 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(156990), // Rule ID 7737 //
     /* 156936 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156939 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 156946 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 156949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 156953 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 156957 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 156964 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRWroW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 156964 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 156967 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 156969 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 156974 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 156979 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 156984 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 156988 */   GIR_RootConstrainSelectedInstOperands,
     /* 156989 */   // GIR_Coverage, 7737,
     /* 156989 */   GIR_EraseRootFromParent_Done,
     /* 156990 */ // Label 2753: @156990
     /* 156990 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(157049), // Rule ID 7738 //
     /* 156995 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 156998 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157005 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157012 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157016 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 157023 */   // (atomic_store GPR32:{ *:[i32] }:$val, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRWroX GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 157023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 157026 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157028 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157033 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 157038 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 157043 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157047 */   GIR_RootConstrainSelectedInstOperands,
     /* 157048 */   // GIR_Coverage, 7738,
     /* 157048 */   GIR_EraseRootFromParent_Done,
     /* 157049 */ // Label 2754: @157049
     /* 157049 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(157121), // Rule ID 7748 //
     /* 157054 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157057 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157064 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157067 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 157071 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 157075 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 157079 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 157084 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157088 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 157090 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 157097 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRSui FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 157097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 157100 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 157104 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157109 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157114 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 157119 */   GIR_RootConstrainSelectedInstOperands,
     /* 157120 */   // GIR_Coverage, 7748,
     /* 157120 */   GIR_EraseRootFromParent_Done,
     /* 157121 */ // Label 2755: @157121
     /* 157121 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(157193), // Rule ID 7749 //
     /* 157126 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157129 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157136 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157139 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 157143 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 157147 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 157151 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 157156 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157160 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 157162 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 157169 */   // (atomic_store (bitconvert:{ *:[i32] } FPR32Op:{ *:[f32] }:$val), (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STURSi FPR32Op:{ *:[f32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 157172 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 157176 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157181 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157186 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 157191 */   GIR_RootConstrainSelectedInstOperands,
     /* 157192 */   // GIR_Coverage, 7749,
     /* 157192 */   GIR_EraseRootFromParent_Done,
     /* 157193 */ // Label 2756: @157193
     /* 157193 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(157245), // Rule ID 314 //
     /* 157198 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 157201 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 157205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157209 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157213 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 157220 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURWi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 157220 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 157223 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 157229 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157234 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157239 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157243 */   GIR_RootConstrainSelectedInstOperands,
     /* 157244 */   // GIR_Coverage, 314,
     /* 157244 */   GIR_EraseRootFromParent_Done,
     /* 157245 */ // Label 2757: @157245
     /* 157245 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(157296), // Rule ID 317 //
     /* 157250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 157253 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 157256 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 157260 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 157264 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157268 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 157275 */   // (st FPR32Op:{ *:[f32] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURSi FPR32Op:{ *:[f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 157275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURSi),
     /* 157278 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 157280 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157290 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157294 */   GIR_RootConstrainSelectedInstOperands,
     /* 157295 */   // GIR_Coverage, 317,
     /* 157295 */   GIR_EraseRootFromParent_Done,
     /* 157296 */ // Label 2758: @157296
     /* 157296 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(157355), // Rule ID 320 //
     /* 157301 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 157304 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 157308 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157319 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157323 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 157330 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHHi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 157330 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 157333 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 157339 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157344 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157349 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157353 */   GIR_RootConstrainSelectedInstOperands,
     /* 157354 */   // GIR_Coverage, 320,
     /* 157354 */   GIR_EraseRootFromParent_Done,
     /* 157355 */ // Label 2759: @157355
     /* 157355 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(157414), // Rule ID 321 //
     /* 157360 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 157363 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 157367 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157378 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 157389 */   // (st GPR32z:{ *:[i32] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STURBBi GPR32z:{ *:[i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 157389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 157392 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::WZR), // Rt
     /* 157398 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157403 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157408 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157412 */   GIR_RootConstrainSelectedInstOperands,
     /* 157413 */   // GIR_Coverage, 321,
     /* 157413 */   GIR_EraseRootFromParent_Done,
     /* 157414 */ // Label 2760: @157414
     /* 157414 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(157468), // Rule ID 7729 //
     /* 157419 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157422 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157429 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157432 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157436 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157440 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 157447 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22302>>  =>  (STRBBui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 157447 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 157450 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157452 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157457 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157462 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157466 */   GIR_RootConstrainSelectedInstOperands,
     /* 157467 */   // GIR_Coverage, 7729,
     /* 157467 */   GIR_EraseRootFromParent_Done,
     /* 157468 */ // Label 2761: @157468
     /* 157468 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(157522), // Rule ID 7730 //
     /* 157473 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157476 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157483 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157490 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157494 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 157501 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22302>>  =>  (STURBBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 157504 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157506 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157511 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157516 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157520 */   GIR_RootConstrainSelectedInstOperands,
     /* 157521 */   // GIR_Coverage, 7730,
     /* 157521 */   GIR_EraseRootFromParent_Done,
     /* 157522 */ // Label 2762: @157522
     /* 157522 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(157576), // Rule ID 7734 //
     /* 157527 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157530 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157537 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157544 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157548 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 157555 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22309>>  =>  (STRHHui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 157555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 157558 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157560 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157565 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157570 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157574 */   GIR_RootConstrainSelectedInstOperands,
     /* 157575 */   // GIR_Coverage, 7734,
     /* 157575 */   GIR_EraseRootFromParent_Done,
     /* 157576 */ // Label 2763: @157576
     /* 157576 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(157630), // Rule ID 7735 //
     /* 157581 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157584 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157591 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 157609 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22309>>  =>  (STURHHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 157612 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157614 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157619 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157624 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157628 */   GIR_RootConstrainSelectedInstOperands,
     /* 157629 */   // GIR_Coverage, 7735,
     /* 157629 */   GIR_EraseRootFromParent_Done,
     /* 157630 */ // Label 2764: @157630
     /* 157630 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(157684), // Rule ID 7739 //
     /* 157635 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157638 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157645 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157652 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157656 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 157663 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STRWui GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 157663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 157666 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157668 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157673 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157678 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157682 */   GIR_RootConstrainSelectedInstOperands,
     /* 157683 */   // GIR_Coverage, 7739,
     /* 157683 */   GIR_EraseRootFromParent_Done,
     /* 157684 */ // Label 2765: @157684
     /* 157684 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(157738), // Rule ID 7740 //
     /* 157689 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157692 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157699 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157706 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157710 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 157717 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22316>>  =>  (STURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157717 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 157720 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157722 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157732 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157736 */   GIR_RootConstrainSelectedInstOperands,
     /* 157737 */   // GIR_Coverage, 7740,
     /* 157737 */   GIR_EraseRootFromParent_Done,
     /* 157738 */ // Label 2766: @157738
     /* 157738 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(157795), // Rule ID 8102 //
     /* 157743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 157746 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157749 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157756 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157759 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157763 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157767 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 157774 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22300>>  =>  (STLURBi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURBi),
     /* 157777 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157779 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157784 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157789 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157793 */   GIR_RootConstrainSelectedInstOperands,
     /* 157794 */   // GIR_Coverage, 8102,
     /* 157794 */   GIR_EraseRootFromParent_Done,
     /* 157795 */ // Label 2767: @157795
     /* 157795 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(157852), // Rule ID 8103 //
     /* 157800 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 157803 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157806 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157813 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157820 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157824 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 157831 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22307>>  =>  (STLURHi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURHi),
     /* 157834 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157846 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157850 */   GIR_RootConstrainSelectedInstOperands,
     /* 157851 */   // GIR_Coverage, 8103,
     /* 157851 */   GIR_EraseRootFromParent_Done,
     /* 157852 */ // Label 2768: @157852
     /* 157852 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(157909), // Rule ID 8104 //
     /* 157857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 157860 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157863 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157870 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157877 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 157881 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 157888 */   // (atomic_store GPR32:{ *:[i32] }:$val, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22314>>  =>  (STLURWi GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 157888 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURWi),
     /* 157891 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 157893 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 157898 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 157903 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 157907 */   GIR_RootConstrainSelectedInstOperands,
     /* 157908 */   // GIR_Coverage, 8104,
     /* 157908 */   GIR_EraseRootFromParent_Done,
     /* 157909 */ // Label 2769: @157909
     /* 157909 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(157946), // Rule ID 7726 //
     /* 157914 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157917 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 157924 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157927 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157931 */   // MIs[0] ptr
     /* 157931 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157935 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157939 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_8>><<P:Predicate_anonymous_22300>>  =>  (STLRB GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 157939 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRB),
     /* 157944 */   GIR_RootConstrainSelectedInstOperands,
     /* 157945 */   // GIR_Coverage, 7726,
     /* 157945 */   GIR_Done,
     /* 157946 */ // Label 2770: @157946
     /* 157946 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(157983), // Rule ID 7731 //
     /* 157951 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157954 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 157961 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 157964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 157968 */   // MIs[0] ptr
     /* 157968 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 157972 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 157976 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_16>><<P:Predicate_anonymous_22307>>  =>  (STLRH GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 157976 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRH),
     /* 157981 */   GIR_RootConstrainSelectedInstOperands,
     /* 157982 */   // GIR_Coverage, 7731,
     /* 157982 */   GIR_Done,
     /* 157983 */ // Label 2771: @157983
     /* 157983 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(158020), // Rule ID 7736 //
     /* 157988 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 157991 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 157998 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 158001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 158005 */   // MIs[0] ptr
     /* 158005 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158009 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158013 */   // (atomic_store GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_32>><<P:Predicate_anonymous_22314>>  =>  (STLRW GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 158013 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRW),
     /* 158018 */   GIR_RootConstrainSelectedInstOperands,
     /* 158019 */   // GIR_Coverage, 7736,
     /* 158019 */   GIR_Done,
     /* 158020 */ // Label 2772: @158020
     /* 158020 */ GIM_Reject,
     /* 158021 */ // Label 2670: @158021
     /* 158021 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(158127), // Rule ID 4710 //
     /* 158026 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158029 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158033 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158037 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158041 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158045 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158049 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158054 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158058 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158062 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158064 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 158071 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 158071 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158074 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158078 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158083 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158089 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158094 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 158102 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158105 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158110 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 158115 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 158120 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158125 */   GIR_RootConstrainSelectedInstOperands,
     /* 158126 */   // GIR_Coverage, 4710,
     /* 158126 */   GIR_EraseRootFromParent_Done,
     /* 158127 */ // Label 2773: @158127
     /* 158127 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(158233), // Rule ID 4711 //
     /* 158132 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158135 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158139 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158143 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158147 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158151 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158155 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158160 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158164 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158168 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158170 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 158177 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 158177 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158180 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158184 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158189 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158195 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158200 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 158208 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158211 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158216 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 158221 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 158226 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158231 */   GIR_RootConstrainSelectedInstOperands,
     /* 158232 */   // GIR_Coverage, 4711,
     /* 158232 */   GIR_EraseRootFromParent_Done,
     /* 158233 */ // Label 2774: @158233
     /* 158233 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(158339), // Rule ID 4712 //
     /* 158238 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158241 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158245 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158249 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158253 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158257 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158261 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158266 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158270 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158274 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158276 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 158283 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 158283 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158286 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158290 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158295 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158301 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158306 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 158314 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158317 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 158327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 158332 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158337 */   GIR_RootConstrainSelectedInstOperands,
     /* 158338 */   // GIR_Coverage, 4712,
     /* 158338 */   GIR_EraseRootFromParent_Done,
     /* 158339 */ // Label 2775: @158339
     /* 158339 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(158445), // Rule ID 4713 //
     /* 158344 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158347 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158351 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158355 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158359 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158363 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158367 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158372 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158376 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158380 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158382 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 158389 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 158389 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158392 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158396 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158401 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158407 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158412 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158417 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 158420 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158428 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 158433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 158438 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158443 */   GIR_RootConstrainSelectedInstOperands,
     /* 158444 */   // GIR_Coverage, 4713,
     /* 158444 */   GIR_EraseRootFromParent_Done,
     /* 158445 */ // Label 2776: @158445
     /* 158445 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(158546), // Rule ID 4741 //
     /* 158450 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158453 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158457 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158461 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158465 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158469 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158473 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158478 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158482 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158486 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158488 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 158495 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 158495 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158498 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158502 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158507 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158513 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158518 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 158526 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158529 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158534 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 158539 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158544 */   GIR_RootConstrainSelectedInstOperands,
     /* 158545 */   // GIR_Coverage, 4741,
     /* 158545 */   GIR_EraseRootFromParent_Done,
     /* 158546 */ // Label 2777: @158546
     /* 158546 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(158647), // Rule ID 4742 //
     /* 158551 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158554 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158558 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158562 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158566 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158570 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158574 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158579 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158583 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158587 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158589 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 158596 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 158596 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158599 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158603 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158608 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158614 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158619 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158624 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 158627 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158630 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158635 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 158640 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158645 */   GIR_RootConstrainSelectedInstOperands,
     /* 158646 */   // GIR_Coverage, 4742,
     /* 158646 */   GIR_EraseRootFromParent_Done,
     /* 158647 */ // Label 2778: @158647
     /* 158647 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(158748), // Rule ID 4768 //
     /* 158652 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158655 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158659 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158663 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158667 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158671 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158675 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158680 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158684 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158688 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158690 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 158697 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 158697 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158700 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158704 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158709 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158715 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158720 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158725 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 158728 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158731 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158736 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 158741 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158746 */   GIR_RootConstrainSelectedInstOperands,
     /* 158747 */   // GIR_Coverage, 4768,
     /* 158747 */   GIR_EraseRootFromParent_Done,
     /* 158748 */ // Label 2779: @158748
     /* 158748 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(158849), // Rule ID 4769 //
     /* 158753 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158756 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158760 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158764 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158768 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158772 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158776 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158781 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 158785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 158789 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 158791 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 158798 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, 0:{ *:[i64] }), (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi (EXTRACT_SUBREG:{ *:[i64] } VecListOne128:{ *:[v2f64] }:$Vt, dsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 158798 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 158801 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 158805 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 158810 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Vt
     /* 158816 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 158821 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 158829 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 158832 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 158837 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 158842 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 158847 */   GIR_RootConstrainSelectedInstOperands,
     /* 158848 */   // GIR_Coverage, 4769,
     /* 158848 */   GIR_EraseRootFromParent_Done,
     /* 158849 */ // Label 2780: @158849
     /* 158849 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(158924), // Rule ID 7104 //
     /* 158854 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158857 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158861 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158865 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158869 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158873 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158877 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158882 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 158886 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 158890 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 158894 */   // MIs[2] Operand 1
     /* 158894 */   // No operand predicates
     /* 158894 */   // MIs[0] Rn
     /* 158894 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158898 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158902 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 158904 */   // (st (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i64 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 158904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
     /* 158907 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 158911 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 158914 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158916 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 158922 */   GIR_RootConstrainSelectedInstOperands,
     /* 158923 */   // GIR_Coverage, 7104,
     /* 158923 */   GIR_EraseRootFromParent_Done,
     /* 158924 */ // Label 2781: @158924
     /* 158924 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(158999), // Rule ID 7105 //
     /* 158929 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 158932 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 158936 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 158940 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 158944 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 158948 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 158952 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 158957 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 158961 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 158965 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 158969 */   // MIs[2] Operand 1
     /* 158969 */   // No operand predicates
     /* 158969 */   // MIs[0] Rn
     /* 158969 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 158973 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 158977 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 158979 */   // (st (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1i64 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 158979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1i64),
     /* 158982 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 158986 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 158989 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 158991 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 158997 */   GIR_RootConstrainSelectedInstOperands,
     /* 158998 */   // GIR_Coverage, 7105,
     /* 158998 */   GIR_EraseRootFromParent_Done,
     /* 158999 */ // Label 2782: @158999
     /* 158999 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(159052), // Rule ID 295 //
     /* 159004 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159007 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159011 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159019 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 159026 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXroW GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 159026 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
     /* 159029 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159031 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159036 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159041 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159046 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159050 */   GIR_RootConstrainSelectedInstOperands,
     /* 159051 */   // GIR_Coverage, 295,
     /* 159051 */   GIR_EraseRootFromParent_Done,
     /* 159052 */ // Label 2783: @159052
     /* 159052 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(159105), // Rule ID 296 //
     /* 159057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159060 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159064 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159068 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159072 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 159079 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXroX GPR64:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 159079 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
     /* 159082 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159084 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159089 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159094 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159099 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159103 */   GIR_RootConstrainSelectedInstOperands,
     /* 159104 */   // GIR_Coverage, 296,
     /* 159104 */   GIR_EraseRootFromParent_Done,
     /* 159105 */ // Label 2784: @159105
     /* 159105 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(159161), // Rule ID 303 //
     /* 159110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 159113 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159116 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159124 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159128 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 159135 */   // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 159135 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 159138 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159140 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159145 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159150 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159155 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159159 */   GIR_RootConstrainSelectedInstOperands,
     /* 159160 */   // GIR_Coverage, 303,
     /* 159160 */   GIR_EraseRootFromParent_Done,
     /* 159161 */ // Label 2785: @159161
     /* 159161 */ GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(159217), // Rule ID 304 //
     /* 159166 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 159169 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159172 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159180 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159184 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 159191 */   // (st FPR64Op:{ *:[f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 159191 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 159194 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159201 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159206 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159211 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159215 */   GIR_RootConstrainSelectedInstOperands,
     /* 159216 */   // GIR_Coverage, 304,
     /* 159216 */   GIR_EraseRootFromParent_Done,
     /* 159217 */ // Label 2786: @159217
     /* 159217 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(159306), // Rule ID 4668 //
     /* 159222 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159225 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159229 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 159236 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159240 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159244 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 159251 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend)
     /* 159251 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159254 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159258 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159263 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159269 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159274 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159279 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroW),
     /* 159282 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159285 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159290 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159295 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159300 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159304 */   GIR_RootConstrainSelectedInstOperands,
     /* 159305 */   // GIR_Coverage, 4668,
     /* 159305 */   GIR_EraseRootFromParent_Done,
     /* 159306 */ // Label 2787: @159306
     /* 159306 */ GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(159395), // Rule ID 4669 //
     /* 159311 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159314 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159318 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 159325 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159329 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159333 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 159340 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend)
     /* 159340 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159343 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159347 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159352 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159358 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159363 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159368 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBroX),
     /* 159371 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159374 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159393 */   GIR_RootConstrainSelectedInstOperands,
     /* 159394 */   // GIR_Coverage, 4669,
     /* 159394 */   GIR_EraseRootFromParent_Done,
     /* 159395 */ // Label 2788: @159395
     /* 159395 */ GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(159484), // Rule ID 4670 //
     /* 159400 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159403 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159407 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 159414 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159418 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159422 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 159429 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend)
     /* 159429 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159432 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159436 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159441 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159447 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159452 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159457 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroW),
     /* 159460 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159463 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159468 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159473 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159478 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159482 */   GIR_RootConstrainSelectedInstOperands,
     /* 159483 */   // GIR_Coverage, 4670,
     /* 159483 */   GIR_EraseRootFromParent_Done,
     /* 159484 */ // Label 2789: @159484
     /* 159484 */ GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(159573), // Rule ID 4671 //
     /* 159489 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159492 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159496 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 159503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159507 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159511 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 159518 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend)
     /* 159518 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159521 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159525 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159530 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159536 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159541 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHroX),
     /* 159549 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159552 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159557 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159562 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159567 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159571 */   GIR_RootConstrainSelectedInstOperands,
     /* 159572 */   // GIR_Coverage, 4671,
     /* 159572 */   GIR_EraseRootFromParent_Done,
     /* 159573 */ // Label 2790: @159573
     /* 159573 */ GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(159662), // Rule ID 4672 //
     /* 159578 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159581 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159585 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 159592 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159596 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159600 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 159607 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWroW (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend)
     /* 159607 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159610 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159614 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159619 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159625 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159630 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroW),
     /* 159638 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159641 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159646 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159651 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159656 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159660 */   GIR_RootConstrainSelectedInstOperands,
     /* 159661 */   // GIR_Coverage, 4672,
     /* 159661 */   GIR_EraseRootFromParent_Done,
     /* 159662 */ // Label 2791: @159662
     /* 159662 */ GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(159751), // Rule ID 4673 //
     /* 159667 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159670 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159674 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 159681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159685 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159689 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 159696 */   // (st GPR64:{ *:[i64] }:$Rt, (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWroX (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend)
     /* 159696 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 159699 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 159703 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 159708 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 159714 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 159719 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 159724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWroX),
     /* 159727 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 159730 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159735 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159740 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159745 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159749 */   GIR_RootConstrainSelectedInstOperands,
     /* 159750 */   // GIR_Coverage, 4673,
     /* 159750 */   GIR_EraseRootFromParent_Done,
     /* 159751 */ // Label 2792: @159751
     /* 159751 */ GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(159804), // Rule ID 4684 //
     /* 159756 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159759 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159767 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159771 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 159778 */   // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 159778 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 159781 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159783 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159788 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159793 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159798 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159802 */   GIR_RootConstrainSelectedInstOperands,
     /* 159803 */   // GIR_Coverage, 4684,
     /* 159803 */   GIR_EraseRootFromParent_Done,
     /* 159804 */ // Label 2793: @159804
     /* 159804 */ GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(159857), // Rule ID 4685 //
     /* 159809 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159812 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159820 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159824 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 159831 */   // (st FPR64:{ *:[v1i64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 159831 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 159834 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159836 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159841 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159846 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159851 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159855 */   GIR_RootConstrainSelectedInstOperands,
     /* 159856 */   // GIR_Coverage, 4685,
     /* 159856 */   GIR_EraseRootFromParent_Done,
     /* 159857 */ // Label 2794: @159857
     /* 159857 */ GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(159910), // Rule ID 4686 //
     /* 159862 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159865 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159873 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159877 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 159884 */   // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 159884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 159887 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159889 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159894 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159899 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159904 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159908 */   GIR_RootConstrainSelectedInstOperands,
     /* 159909 */   // GIR_Coverage, 4686,
     /* 159909 */   GIR_EraseRootFromParent_Done,
     /* 159910 */ // Label 2795: @159910
     /* 159910 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(159963), // Rule ID 4687 //
     /* 159915 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159918 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159926 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 159930 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 159937 */   // (st FPR64:{ *:[v1f64] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 159937 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 159940 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 159942 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 159947 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 159952 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 159957 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 159961 */   GIR_RootConstrainSelectedInstOperands,
     /* 159962 */   // GIR_Coverage, 4687,
     /* 159962 */   GIR_EraseRootFromParent_Done,
     /* 159963 */ // Label 2796: @159963
     /* 159963 */ GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(160063), // Rule ID 4729 //
     /* 159968 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 159971 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 159975 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 159982 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 159986 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 159990 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 159994 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 159999 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160003 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160005 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 160012 */   // (st (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rt), (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRSui (EXTRACT_SUBREG:{ *:[i32] } FPR64:{ *:[f64] }:$Rt, ssub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 160012 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 160015 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 160019 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 160024 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rt
     /* 160030 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 160035 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160040 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRSui),
     /* 160043 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 160046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160056 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 160061 */   GIR_RootConstrainSelectedInstOperands,
     /* 160062 */   // GIR_Coverage, 4729,
     /* 160062 */   GIR_EraseRootFromParent_Done,
     /* 160063 */ // Label 2797: @160063
     /* 160063 */ GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(160163), // Rule ID 4730 //
     /* 160068 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160071 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160075 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 160082 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 160086 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 160090 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 160094 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160099 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160103 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160105 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 160112 */   // (st (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rt), (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHui (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[f64] }:$Rt, hsub:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 160112 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 160115 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 160119 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 160124 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rt
     /* 160130 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 160135 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHui),
     /* 160143 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 160146 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160151 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160156 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 160161 */   GIR_RootConstrainSelectedInstOperands,
     /* 160162 */   // GIR_Coverage, 4730,
     /* 160162 */   GIR_EraseRootFromParent_Done,
     /* 160163 */ // Label 2798: @160163
     /* 160163 */ GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(160215), // Rule ID 305 //
     /* 160168 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160171 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160175 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160179 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160183 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 160190 */   // (st GPR64z:{ *:[i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRXui GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 160190 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
     /* 160193 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
     /* 160199 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160204 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160209 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160213 */   GIR_RootConstrainSelectedInstOperands,
     /* 160214 */   // GIR_Coverage, 305,
     /* 160214 */   GIR_EraseRootFromParent_Done,
     /* 160215 */ // Label 2799: @160215
     /* 160215 */ GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(160266), // Rule ID 310 //
     /* 160220 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 160223 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160226 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160230 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160234 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160238 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 160245 */   // (st FPR64Op:{ *:[f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 160245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 160248 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 160250 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160255 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160260 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160264 */   GIR_RootConstrainSelectedInstOperands,
     /* 160265 */   // GIR_Coverage, 310,
     /* 160265 */   GIR_EraseRootFromParent_Done,
     /* 160266 */ // Label 2800: @160266
     /* 160266 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(160314), // Rule ID 4714 //
     /* 160271 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160274 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160282 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160286 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 160293 */   // (st FPR64:{ *:[v1i64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 160293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 160296 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 160298 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160303 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160308 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160312 */   GIR_RootConstrainSelectedInstOperands,
     /* 160313 */   // GIR_Coverage, 4714,
     /* 160313 */   GIR_EraseRootFromParent_Done,
     /* 160314 */ // Label 2801: @160314
     /* 160314 */ GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(160362), // Rule ID 4715 //
     /* 160319 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160322 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160330 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160334 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 160341 */   // (st FPR64:{ *:[v1f64] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 160341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 160344 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 160346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160360 */   GIR_RootConstrainSelectedInstOperands,
     /* 160361 */   // GIR_Coverage, 4715,
     /* 160361 */   GIR_EraseRootFromParent_Done,
     /* 160362 */ // Label 2802: @160362
     /* 160362 */ GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(160446), // Rule ID 4734 //
     /* 160367 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160370 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160374 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 160381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160385 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160389 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 160396 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STRWui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset)
     /* 160396 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 160399 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 160403 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 160408 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 160414 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 160419 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRWui),
     /* 160427 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 160430 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160435 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160440 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160444 */   GIR_RootConstrainSelectedInstOperands,
     /* 160445 */   // GIR_Coverage, 4734,
     /* 160445 */   GIR_EraseRootFromParent_Done,
     /* 160446 */ // Label 2803: @160446
     /* 160446 */ GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(160530), // Rule ID 4735 //
     /* 160451 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160454 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160458 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 160465 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160469 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160473 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 160480 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STRHHui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset)
     /* 160480 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 160483 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 160487 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 160492 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 160498 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 160503 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRHHui),
     /* 160511 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 160514 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160519 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160524 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160528 */   GIR_RootConstrainSelectedInstOperands,
     /* 160529 */   // GIR_Coverage, 4735,
     /* 160529 */   GIR_EraseRootFromParent_Done,
     /* 160530 */ // Label 2804: @160530
     /* 160530 */ GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(160614), // Rule ID 4736 //
     /* 160535 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 160538 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 160542 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 160549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160553 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160557 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 160564 */   // (st GPR64:{ *:[i64] }:$Rt, (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STRBBui (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset)
     /* 160564 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 160567 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 160571 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 160576 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 160582 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 160587 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160592 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRBBui),
     /* 160595 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 160598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160603 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160608 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160612 */   GIR_RootConstrainSelectedInstOperands,
     /* 160613 */   // GIR_Coverage, 4736,
     /* 160613 */   GIR_EraseRootFromParent_Done,
     /* 160614 */ // Label 2805: @160614
     /* 160614 */ GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(160691), // Rule ID 7750 //
     /* 160619 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160622 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160629 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160632 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 160636 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 160640 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 160644 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160649 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160653 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160655 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 160662 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRDroW FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 160662 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 160665 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 160669 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160674 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 160679 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 160684 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 160689 */   GIR_RootConstrainSelectedInstOperands,
     /* 160690 */   // GIR_Coverage, 7750,
     /* 160690 */   GIR_EraseRootFromParent_Done,
     /* 160691 */ // Label 2806: @160691
     /* 160691 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(160768), // Rule ID 7751 //
     /* 160696 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160699 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160706 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160709 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 160713 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 160717 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 160721 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160726 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160730 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160732 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 160739 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRDroX FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 160739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 160742 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 160746 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160751 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 160756 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 160761 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 160766 */   GIR_RootConstrainSelectedInstOperands,
     /* 160767 */   // GIR_Coverage, 7751,
     /* 160767 */   GIR_EraseRootFromParent_Done,
     /* 160768 */ // Label 2807: @160768
     /* 160768 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(160827), // Rule ID 7742 //
     /* 160773 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160776 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160783 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160786 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160790 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160794 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 160801 */   // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRXroW GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 160801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroW),
     /* 160804 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 160806 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160811 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 160816 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 160821 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160825 */   GIR_RootConstrainSelectedInstOperands,
     /* 160826 */   // GIR_Coverage, 7742,
     /* 160826 */   GIR_EraseRootFromParent_Done,
     /* 160827 */ // Label 2808: @160827
     /* 160827 */ GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(160886), // Rule ID 7743 //
     /* 160832 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160835 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160842 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 160849 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160853 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 160860 */   // (atomic_store GPR64:{ *:[i64] }:$val, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRXroX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 160860 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXroX),
     /* 160863 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 160865 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160870 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 160875 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 160880 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 160884 */   GIR_RootConstrainSelectedInstOperands,
     /* 160885 */   // GIR_Coverage, 7743,
     /* 160885 */   GIR_EraseRootFromParent_Done,
     /* 160886 */ // Label 2809: @160886
     /* 160886 */ GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(160958), // Rule ID 7752 //
     /* 160891 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160894 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160901 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160904 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 160908 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 160912 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 160916 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160921 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160925 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160927 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 160934 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRDui FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 160934 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 160937 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 160941 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 160946 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 160951 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 160956 */   GIR_RootConstrainSelectedInstOperands,
     /* 160957 */   // GIR_Coverage, 7752,
     /* 160957 */   GIR_EraseRootFromParent_Done,
     /* 160958 */ // Label 2810: @160958
     /* 160958 */ GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(161030), // Rule ID 7753 //
     /* 160963 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 160966 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 160973 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 160976 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 160980 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 160984 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 160988 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 160993 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 160997 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 160999 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161006 */   // (atomic_store (bitconvert:{ *:[i64] } FPR64Op:{ *:[f64] }:$val), (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STURDi FPR64Op:{ *:[f64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161006 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 161009 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 161013 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161018 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161023 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 161028 */   GIR_RootConstrainSelectedInstOperands,
     /* 161029 */   // GIR_Coverage, 7753,
     /* 161029 */   GIR_EraseRootFromParent_Done,
     /* 161030 */ // Label 2811: @161030
     /* 161030 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(161127), // Rule ID 8094 //
     /* 161035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 161038 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161041 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161048 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161051 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 161055 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 161059 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 161063 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 161067 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 161071 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 161075 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 161079 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 161084 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 161088 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 161092 */   GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 161096 */   // MIs[3] Operand 1
     /* 161096 */   // No operand predicates
     /* 161096 */   // MIs[0] Rn
     /* 161096 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161100 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 161104 */   GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 161106 */   // (atomic_store (bitconvert:{ *:[i64] } (vector_extract:{ *:[f64] } VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22321>>  =>  (STL1 VecListOne128:{ *:[v2f64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 161106 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 161109 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vt
     /* 161113 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 161116 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161118 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
     /* 161125 */   GIR_RootConstrainSelectedInstOperands,
     /* 161126 */   // GIR_Coverage, 8094,
     /* 161126 */   GIR_EraseRootFromParent_Done,
     /* 161127 */ // Label 2812: @161127
     /* 161127 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(161179), // Rule ID 313 //
     /* 161132 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161135 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161143 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161147 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161154 */   // (st GPR64z:{ *:[i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURXi GPR64z:{ *:[i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 161154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
     /* 161157 */   GIR_CopyOrAddZeroReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, GIMT_Encode2(AArch64::XZR), // Rt
     /* 161163 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161168 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161173 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161177 */   GIR_RootConstrainSelectedInstOperands,
     /* 161178 */   // GIR_Coverage, 313,
     /* 161178 */   GIR_EraseRootFromParent_Done,
     /* 161179 */ // Label 2813: @161179
     /* 161179 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(161230), // Rule ID 318 //
     /* 161184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 161187 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161190 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161198 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161202 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161209 */   // (st FPR64Op:{ *:[f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64Op:{ *:[f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 161209 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 161212 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 161214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161219 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161224 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161228 */   GIR_RootConstrainSelectedInstOperands,
     /* 161229 */   // GIR_Coverage, 318,
     /* 161229 */   GIR_EraseRootFromParent_Done,
     /* 161230 */ // Label 2814: @161230
     /* 161230 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(161284), // Rule ID 7744 //
     /* 161235 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161238 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161245 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161252 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161256 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 161263 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STRXui GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 161263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRXui),
     /* 161266 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 161268 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161278 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161282 */   GIR_RootConstrainSelectedInstOperands,
     /* 161283 */   // GIR_Coverage, 7744,
     /* 161283 */   GIR_EraseRootFromParent_Done,
     /* 161284 */ // Label 2815: @161284
     /* 161284 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(161338), // Rule ID 7745 //
     /* 161289 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161292 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161299 */   GIM_CheckAtomicOrderingWeakerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161306 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161310 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161317 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22323>>  =>  (STURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161317 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURXi),
     /* 161320 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 161322 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161327 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161332 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161336 */   GIR_RootConstrainSelectedInstOperands,
     /* 161337 */   // GIR_Coverage, 7745,
     /* 161337 */   GIR_EraseRootFromParent_Done,
     /* 161338 */ // Label 2816: @161338
     /* 161338 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(161395), // Rule ID 8105 //
     /* 161343 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRCPC_IMMO),
     /* 161346 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161349 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161356 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161367 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161374 */   // (atomic_store GPR64:{ *:[i64] }:$val, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22321>>  =>  (STLURXi GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLURXi),
     /* 161377 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 161379 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161384 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161389 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161393 */   GIR_RootConstrainSelectedInstOperands,
     /* 161394 */   // GIR_Coverage, 8105,
     /* 161394 */   GIR_EraseRootFromParent_Done,
     /* 161395 */ // Label 2817: @161395
     /* 161395 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(161443), // Rule ID 4743 //
     /* 161400 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161403 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161411 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161415 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161422 */   // (st FPR64:{ *:[v1f64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161422 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 161425 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 161427 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161432 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161441 */   GIR_RootConstrainSelectedInstOperands,
     /* 161442 */   // GIR_Coverage, 4743,
     /* 161442 */   GIR_EraseRootFromParent_Done,
     /* 161443 */ // Label 2818: @161443
     /* 161443 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(161491), // Rule ID 4744 //
     /* 161448 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161451 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161455 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161459 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161463 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 161470 */   // (st FPR64:{ *:[v1i64] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v1i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 161473 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 161475 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161480 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161485 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161489 */   GIR_RootConstrainSelectedInstOperands,
     /* 161490 */   // GIR_Coverage, 4744,
     /* 161490 */   GIR_EraseRootFromParent_Done,
     /* 161491 */ // Label 2819: @161491
     /* 161491 */ GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(161575), // Rule ID 4759 //
     /* 161496 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161499 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161503 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 161510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161514 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161518 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 161525 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei32>>  =>  (STURWi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161525 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 161528 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 161532 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 161537 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 161543 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 161548 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURWi),
     /* 161556 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 161559 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161564 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161569 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161573 */   GIR_RootConstrainSelectedInstOperands,
     /* 161574 */   // GIR_Coverage, 4759,
     /* 161574 */   GIR_EraseRootFromParent_Done,
     /* 161575 */ // Label 2820: @161575
     /* 161575 */ GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(161659), // Rule ID 4760 //
     /* 161580 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161583 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161587 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 161594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161598 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161602 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 161609 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>>  =>  (STURHHi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161609 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 161612 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 161616 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 161621 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 161627 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 161632 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURHHi),
     /* 161640 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 161643 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161648 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161653 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161657 */   GIR_RootConstrainSelectedInstOperands,
     /* 161658 */   // GIR_Coverage, 4760,
     /* 161658 */   GIR_EraseRootFromParent_Done,
     /* 161659 */ // Label 2821: @161659
     /* 161659 */ GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(161743), // Rule ID 4761 //
     /* 161664 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161667 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161671 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 161678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161682 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 161686 */   GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 161693 */   // (st GPR64:{ *:[i64] }:$Rt, (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>>  =>  (STURBBi (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rt, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 161693 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 161696 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 161700 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 161705 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(20), // Rt
     /* 161711 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 161716 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161721 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURBBi),
     /* 161724 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 161727 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 161732 */   GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 161737 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 161741 */   GIR_RootConstrainSelectedInstOperands,
     /* 161742 */   // GIR_Coverage, 4761,
     /* 161742 */   GIR_EraseRootFromParent_Done,
     /* 161743 */ // Label 2822: @161743
     /* 161743 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(161827), // Rule ID 8093 //
     /* 161748 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 161751 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161754 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161761 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161764 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 161768 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 161772 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 161776 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 161780 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 161785 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 161789 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 161793 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 161797 */   // MIs[2] Operand 1
     /* 161797 */   // No operand predicates
     /* 161797 */   // MIs[0] Rn
     /* 161797 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161801 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 161805 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 161807 */   // (atomic_store (vector_extract:{ *:[i64] } VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22321>>  =>  (STL1 VecListOne128:{ *:[v2i64] }:$Vt, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 161807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 161810 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 161814 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 161817 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161819 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 161825 */   GIR_RootConstrainSelectedInstOperands,
     /* 161826 */   // GIR_Coverage, 8093,
     /* 161826 */   GIR_EraseRootFromParent_Done,
     /* 161827 */ // Label 2823: @161827
     /* 161827 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(161925), // Rule ID 8095 //
     /* 161832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 161835 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161838 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161845 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161848 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 161852 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 161856 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 161860 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161865 */   // MIs[0] Rn
     /* 161865 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161869 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 161873 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 161875 */   // (atomic_store (bitconvert:{ *:[i64] } VecListOne64:{ *:[v1f64] }:$Vt), GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22321>>  =>  (STL1 (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, VecListOne64:{ *:[v1f64] }:$Vt, dsub:{ *:[i32] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn)
     /* 161875 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 161878 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 161882 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 161887 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 161890 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Vt
     /* 161894 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 161897 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 161902 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 161907 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STL1),
     /* 161910 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 161913 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 161916 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 161918 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 161923 */   GIR_RootConstrainSelectedInstOperands,
     /* 161924 */   // GIR_Coverage, 8095,
     /* 161924 */   GIR_EraseRootFromParent_Done,
     /* 161925 */ // Label 2824: @161925
     /* 161925 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(161962), // Rule ID 7741 //
     /* 161930 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 161933 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 161940 */   GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 161943 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 161947 */   // MIs[0] ptr
     /* 161947 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 161955 */   // (atomic_store GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)<<P:Predicate_atomic_store_64>><<P:Predicate_anonymous_22321>>  =>  (STLRX GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$ptr)
     /* 161955 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::STLRX),
     /* 161960 */   GIR_RootConstrainSelectedInstOperands,
     /* 161961 */   // GIR_Coverage, 7741,
     /* 161961 */   GIR_Done,
     /* 161962 */ // Label 2825: @161962
     /* 161962 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(161989), // Rule ID 7044 //
     /* 161967 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161970 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 161974 */   // MIs[0] Rn
     /* 161974 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 161978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 161982 */   // (st v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev1d v1i64:{ *:[v1i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 161982 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev1d),
     /* 161987 */   GIR_RootConstrainSelectedInstOperands,
     /* 161988 */   // GIR_Coverage, 7044,
     /* 161988 */   GIR_Done,
     /* 161989 */ // Label 2826: @161989
     /* 161989 */ GIM_Reject,
     /* 161990 */ // Label 2671: @161990
     /* 161990 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(162195),
     /* 161995 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 161998 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 162002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162006 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162010 */   GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(162051), // Rule ID 4666 //
     /* 162015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
     /* 162018 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 162025 */     // (st FPR128:{ *:[f128] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 162025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 162028 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162045 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162049 */     GIR_RootConstrainSelectedInstOperands,
     /* 162050 */     // GIR_Coverage, 4666,
     /* 162050 */     GIR_EraseRootFromParent_Done,
     /* 162051 */   // Label 2828: @162051
     /* 162051 */   GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(162092), // Rule ID 4667 //
     /* 162056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseSTRQro),
     /* 162059 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 162066 */     // (st FPR128:{ *:[f128] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 162066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 162069 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162071 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162086 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162090 */     GIR_RootConstrainSelectedInstOperands,
     /* 162091 */     // GIR_Coverage, 4667,
     /* 162091 */     GIR_EraseRootFromParent_Done,
     /* 162092 */   // Label 2829: @162092
     /* 162092 */   GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(162125), // Rule ID 4721 //
     /* 162097 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 162104 */     // (st FPR128:{ *:[f128] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 162104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 162107 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162109 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162114 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162123 */     GIR_RootConstrainSelectedInstOperands,
     /* 162124 */     // GIR_Coverage, 4721,
     /* 162124 */     GIR_EraseRootFromParent_Done,
     /* 162125 */   // Label 2830: @162125
     /* 162125 */   GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(162158), // Rule ID 4750 //
     /* 162130 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 162137 */     // (st FPR128:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 162137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 162140 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162156 */     GIR_RootConstrainSelectedInstOperands,
     /* 162157 */     // GIR_Coverage, 4750,
     /* 162157 */     GIR_EraseRootFromParent_Done,
     /* 162158 */   // Label 2831: @162158
     /* 162158 */   GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(162194), // Rule ID 319 //
     /* 162163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 162166 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 162173 */     // (st FPR128Op:{ *:[f128] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128Op:{ *:[f128] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 162173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 162176 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162192 */     GIR_RootConstrainSelectedInstOperands,
     /* 162193 */     // GIR_Coverage, 319,
     /* 162193 */     GIR_EraseRootFromParent_Done,
     /* 162194 */   // Label 2832: @162194
     /* 162194 */   GIM_Reject,
     /* 162195 */ // Label 2827: @162195
     /* 162195 */ GIM_Reject,
     /* 162196 */ // Label 2672: @162196
     /* 162196 */ GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(162601),
     /* 162201 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 162204 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 162208 */   GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(162257), // Rule ID 4674 //
     /* 162213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162220 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162224 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 162231 */     // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 162231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 162234 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162246 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162255 */     GIR_RootConstrainSelectedInstOperands,
     /* 162256 */     // GIR_Coverage, 4674,
     /* 162256 */     GIR_EraseRootFromParent_Done,
     /* 162257 */   // Label 2834: @162257
     /* 162257 */   GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(162306), // Rule ID 4675 //
     /* 162262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162269 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162273 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 162280 */     // (st FPR64:{ *:[v2i32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 162280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 162283 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162285 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162290 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162304 */     GIR_RootConstrainSelectedInstOperands,
     /* 162305 */     // GIR_Coverage, 4675,
     /* 162305 */     GIR_EraseRootFromParent_Done,
     /* 162306 */   // Label 2835: @162306
     /* 162306 */   GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(162355), // Rule ID 4676 //
     /* 162311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162318 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162322 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 162329 */     // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 162329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 162332 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162334 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162353 */     GIR_RootConstrainSelectedInstOperands,
     /* 162354 */     // GIR_Coverage, 4676,
     /* 162354 */     GIR_EraseRootFromParent_Done,
     /* 162355 */   // Label 2836: @162355
     /* 162355 */   GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(162404), // Rule ID 4677 //
     /* 162360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162371 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 162378 */     // (st FPR64:{ *:[v2f32] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 162378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 162381 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162402 */     GIR_RootConstrainSelectedInstOperands,
     /* 162403 */     // GIR_Coverage, 4677,
     /* 162403 */     GIR_EraseRootFromParent_Done,
     /* 162404 */   // Label 2837: @162404
     /* 162404 */   GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(162448), // Rule ID 4716 //
     /* 162409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162416 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162420 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 162427 */     // (st FPR64:{ *:[v2f32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 162427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 162430 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162432 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162446 */     GIR_RootConstrainSelectedInstOperands,
     /* 162447 */     // GIR_Coverage, 4716,
     /* 162447 */     GIR_EraseRootFromParent_Done,
     /* 162448 */   // Label 2838: @162448
     /* 162448 */   GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(162492), // Rule ID 4719 //
     /* 162453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162460 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162464 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 162471 */     // (st FPR64:{ *:[v2i32] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 162471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 162474 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162476 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162481 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162486 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162490 */     GIR_RootConstrainSelectedInstOperands,
     /* 162491 */     // GIR_Coverage, 4719,
     /* 162491 */     GIR_EraseRootFromParent_Done,
     /* 162492 */   // Label 2839: @162492
     /* 162492 */   GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(162536), // Rule ID 4745 //
     /* 162497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162508 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 162515 */     // (st FPR64:{ *:[v2f32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 162515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 162518 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162520 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162525 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162534 */     GIR_RootConstrainSelectedInstOperands,
     /* 162535 */     // GIR_Coverage, 4745,
     /* 162535 */     GIR_EraseRootFromParent_Done,
     /* 162536 */   // Label 2840: @162536
     /* 162536 */   GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(162580), // Rule ID 4748 //
     /* 162541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 162548 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162552 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 162559 */     // (st FPR64:{ *:[v2i32] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v2i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 162559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 162562 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162578 */     GIR_RootConstrainSelectedInstOperands,
     /* 162579 */     // GIR_Coverage, 4748,
     /* 162579 */     GIR_EraseRootFromParent_Done,
     /* 162580 */   // Label 2841: @162580
     /* 162580 */   GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(162600), // Rule ID 7043 //
     /* 162585 */     // MIs[0] Rn
     /* 162585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 162589 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 162593 */     // (st v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev2s v2i32:{ *:[v2i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 162593 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2s),
     /* 162598 */     GIR_RootConstrainSelectedInstOperands,
     /* 162599 */     // GIR_Coverage, 7043,
     /* 162599 */     GIR_Done,
     /* 162600 */   // Label 2842: @162600
     /* 162600 */   GIM_Reject,
     /* 162601 */ // Label 2833: @162601
     /* 162601 */ GIM_Reject,
     /* 162602 */ // Label 2673: @162602
     /* 162602 */ GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(163051),
     /* 162607 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 162610 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 162614 */   GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(162663), // Rule ID 4688 //
     /* 162619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 162622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162630 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 162637 */     // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 162637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 162640 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162652 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162661 */     GIR_RootConstrainSelectedInstOperands,
     /* 162662 */     // GIR_Coverage, 4688,
     /* 162662 */     GIR_EraseRootFromParent_Done,
     /* 162663 */   // Label 2844: @162663
     /* 162663 */   GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(162712), // Rule ID 4689 //
     /* 162668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 162671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162675 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162679 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 162686 */     // (st FPR128:{ *:[v2i64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 162686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 162689 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162691 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162696 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162706 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162710 */     GIR_RootConstrainSelectedInstOperands,
     /* 162711 */     // GIR_Coverage, 4689,
     /* 162711 */     GIR_EraseRootFromParent_Done,
     /* 162712 */   // Label 2845: @162712
     /* 162712 */   GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(162761), // Rule ID 4690 //
     /* 162717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 162720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162724 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162728 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 162735 */     // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 162735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 162738 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162740 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162759 */     GIR_RootConstrainSelectedInstOperands,
     /* 162760 */     // GIR_Coverage, 4690,
     /* 162760 */     GIR_EraseRootFromParent_Done,
     /* 162761 */   // Label 2846: @162761
     /* 162761 */   GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(162810), // Rule ID 4691 //
     /* 162766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 162769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162773 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162777 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 162784 */     // (st FPR128:{ *:[v2f64] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 162784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 162787 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 162799 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 162804 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162808 */     GIR_RootConstrainSelectedInstOperands,
     /* 162809 */     // GIR_Coverage, 4691,
     /* 162809 */     GIR_EraseRootFromParent_Done,
     /* 162810 */   // Label 2847: @162810
     /* 162810 */   GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(162854), // Rule ID 4723 //
     /* 162815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162822 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162826 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 162833 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 162833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 162836 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162838 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162843 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162848 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162852 */     GIR_RootConstrainSelectedInstOperands,
     /* 162853 */     // GIR_Coverage, 4723,
     /* 162853 */     GIR_EraseRootFromParent_Done,
     /* 162854 */   // Label 2848: @162854
     /* 162854 */   GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(162898), // Rule ID 4727 //
     /* 162859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162870 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 162877 */     // (st FPR128:{ *:[v2i64] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 162877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 162880 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162882 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162887 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162892 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162896 */     GIR_RootConstrainSelectedInstOperands,
     /* 162897 */     // GIR_Coverage, 4727,
     /* 162897 */     GIR_EraseRootFromParent_Done,
     /* 162898 */   // Label 2849: @162898
     /* 162898 */   GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(162942), // Rule ID 4752 //
     /* 162903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162914 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 162921 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 162921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 162924 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162940 */     GIR_RootConstrainSelectedInstOperands,
     /* 162941 */     // GIR_Coverage, 4752,
     /* 162941 */     GIR_EraseRootFromParent_Done,
     /* 162942 */   // Label 2850: @162942
     /* 162942 */   GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(162986), // Rule ID 4756 //
     /* 162947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162954 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 162958 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 162965 */     // (st FPR128:{ *:[v2i64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2i64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 162965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 162968 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 162970 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 162975 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 162980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 162984 */     GIR_RootConstrainSelectedInstOperands,
     /* 162985 */     // GIR_Coverage, 4756,
     /* 162985 */     GIR_EraseRootFromParent_Done,
     /* 162986 */   // Label 2851: @162986
     /* 162986 */   GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(163030), // Rule ID 4757 //
     /* 162991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 162994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 162998 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163002 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 163009 */     // (st FPR128:{ *:[v2f64] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v2f64] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 163009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 163012 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163028 */     GIR_RootConstrainSelectedInstOperands,
     /* 163029 */     // GIR_Coverage, 4757,
     /* 163029 */     GIR_EraseRootFromParent_Done,
     /* 163030 */   // Label 2852: @163030
     /* 163030 */   GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(163050), // Rule ID 7040 //
     /* 163035 */     // MIs[0] Rn
     /* 163035 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 163039 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 163043 */     // (st v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev2d v2i64:{ *:[v2i64] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 163043 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev2d),
     /* 163048 */     GIR_RootConstrainSelectedInstOperands,
     /* 163049 */     // GIR_Coverage, 7040,
     /* 163049 */     GIR_Done,
     /* 163050 */   // Label 2853: @163050
     /* 163050 */   GIM_Reject,
     /* 163051 */ // Label 2843: @163051
     /* 163051 */ GIM_Reject,
     /* 163052 */ // Label 2674: @163052
     /* 163052 */ GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(163457),
     /* 163057 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 163060 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 163064 */   GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(163113), // Rule ID 4678 //
     /* 163069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163076 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163080 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 163087 */     // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 163087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 163090 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163092 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163097 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163102 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163111 */     GIR_RootConstrainSelectedInstOperands,
     /* 163112 */     // GIR_Coverage, 4678,
     /* 163112 */     GIR_EraseRootFromParent_Done,
     /* 163113 */   // Label 2855: @163113
     /* 163113 */   GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(163162), // Rule ID 4679 //
     /* 163118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163125 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163129 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 163136 */     // (st FPR64:{ *:[v4i16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 163136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 163139 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163141 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163146 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163151 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163160 */     GIR_RootConstrainSelectedInstOperands,
     /* 163161 */     // GIR_Coverage, 4679,
     /* 163161 */     GIR_EraseRootFromParent_Done,
     /* 163162 */   // Label 2856: @163162
     /* 163162 */   GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(163211), // Rule ID 4682 //
     /* 163167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163178 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 163185 */     // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 163185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 163188 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163190 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163195 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163200 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163209 */     GIR_RootConstrainSelectedInstOperands,
     /* 163210 */     // GIR_Coverage, 4682,
     /* 163210 */     GIR_EraseRootFromParent_Done,
     /* 163211 */   // Label 2857: @163211
     /* 163211 */   GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(163260), // Rule ID 4683 //
     /* 163216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163223 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163227 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 163234 */     // (st FPR64:{ *:[v4f16] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 163234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 163237 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163239 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163244 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163249 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163258 */     GIR_RootConstrainSelectedInstOperands,
     /* 163259 */     // GIR_Coverage, 4683,
     /* 163259 */     GIR_EraseRootFromParent_Done,
     /* 163260 */   // Label 2858: @163260
     /* 163260 */   GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(163304), // Rule ID 4718 //
     /* 163265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163272 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163276 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 163283 */     // (st FPR64:{ *:[v4i16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 163283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 163286 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163288 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163293 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163298 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163302 */     GIR_RootConstrainSelectedInstOperands,
     /* 163303 */     // GIR_Coverage, 4718,
     /* 163303 */     GIR_EraseRootFromParent_Done,
     /* 163304 */   // Label 2859: @163304
     /* 163304 */   GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(163348), // Rule ID 4720 //
     /* 163309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163320 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 163327 */     // (st FPR64:{ *:[v4f16] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 163327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 163330 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163342 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163346 */     GIR_RootConstrainSelectedInstOperands,
     /* 163347 */     // GIR_Coverage, 4720,
     /* 163347 */     GIR_EraseRootFromParent_Done,
     /* 163348 */   // Label 2860: @163348
     /* 163348 */   GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(163392), // Rule ID 4747 //
     /* 163353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163360 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163364 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 163371 */     // (st FPR64:{ *:[v4i16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 163371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 163374 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163390 */     GIR_RootConstrainSelectedInstOperands,
     /* 163391 */     // GIR_Coverage, 4747,
     /* 163391 */     GIR_EraseRootFromParent_Done,
     /* 163392 */   // Label 2861: @163392
     /* 163392 */   GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(163436), // Rule ID 4749 //
     /* 163397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163404 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163408 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 163415 */     // (st FPR64:{ *:[v4f16] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v4f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 163415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 163418 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163420 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163430 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163434 */     GIR_RootConstrainSelectedInstOperands,
     /* 163435 */     // GIR_Coverage, 4749,
     /* 163435 */     GIR_EraseRootFromParent_Done,
     /* 163436 */   // Label 2862: @163436
     /* 163436 */   GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(163456), // Rule ID 7042 //
     /* 163441 */     // MIs[0] Rn
     /* 163441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 163445 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 163449 */     // (st v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev4h v4i16:{ *:[v4i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 163449 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4h),
     /* 163454 */     GIR_RootConstrainSelectedInstOperands,
     /* 163455 */     // GIR_Coverage, 7042,
     /* 163455 */     GIR_Done,
     /* 163456 */   // Label 2863: @163456
     /* 163456 */   GIM_Reject,
     /* 163457 */ // Label 2854: @163457
     /* 163457 */ GIM_Reject,
     /* 163458 */ // Label 2675: @163458
     /* 163458 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(163863),
     /* 163463 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 163466 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 163470 */   GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(163519), // Rule ID 4692 //
     /* 163475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 163478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163482 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163486 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 163493 */     // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 163493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 163496 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163513 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163517 */     GIR_RootConstrainSelectedInstOperands,
     /* 163518 */     // GIR_Coverage, 4692,
     /* 163518 */     GIR_EraseRootFromParent_Done,
     /* 163519 */   // Label 2865: @163519
     /* 163519 */   GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(163568), // Rule ID 4693 //
     /* 163524 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 163527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163531 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163535 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 163542 */     // (st FPR128:{ *:[v4i32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 163542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 163545 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163547 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163552 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163557 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163562 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163566 */     GIR_RootConstrainSelectedInstOperands,
     /* 163567 */     // GIR_Coverage, 4693,
     /* 163567 */     GIR_EraseRootFromParent_Done,
     /* 163568 */   // Label 2866: @163568
     /* 163568 */   GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(163617), // Rule ID 4694 //
     /* 163573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 163576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163580 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163584 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 163591 */     // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 163591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 163594 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163601 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163611 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163615 */     GIR_RootConstrainSelectedInstOperands,
     /* 163616 */     // GIR_Coverage, 4694,
     /* 163616 */     GIR_EraseRootFromParent_Done,
     /* 163617 */   // Label 2867: @163617
     /* 163617 */   GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(163666), // Rule ID 4695 //
     /* 163622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 163625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163629 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163633 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 163640 */     // (st FPR128:{ *:[v4f32] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 163640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 163643 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163655 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163660 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163664 */     GIR_RootConstrainSelectedInstOperands,
     /* 163665 */     // GIR_Coverage, 4695,
     /* 163665 */     GIR_EraseRootFromParent_Done,
     /* 163666 */   // Label 2868: @163666
     /* 163666 */   GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(163710), // Rule ID 4722 //
     /* 163671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163682 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 163689 */     // (st FPR128:{ *:[v4f32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 163689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 163692 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163694 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163708 */     GIR_RootConstrainSelectedInstOperands,
     /* 163709 */     // GIR_Coverage, 4722,
     /* 163709 */     GIR_EraseRootFromParent_Done,
     /* 163710 */   // Label 2869: @163710
     /* 163710 */   GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(163754), // Rule ID 4726 //
     /* 163715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163726 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 163733 */     // (st FPR128:{ *:[v4i32] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 163733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 163736 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163738 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163743 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163752 */     GIR_RootConstrainSelectedInstOperands,
     /* 163753 */     // GIR_Coverage, 4726,
     /* 163753 */     GIR_EraseRootFromParent_Done,
     /* 163754 */   // Label 2870: @163754
     /* 163754 */   GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(163798), // Rule ID 4751 //
     /* 163759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163766 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163770 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 163777 */     // (st FPR128:{ *:[v4f32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4f32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 163777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 163780 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163782 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163787 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163792 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163796 */     GIR_RootConstrainSelectedInstOperands,
     /* 163797 */     // GIR_Coverage, 4751,
     /* 163797 */     GIR_EraseRootFromParent_Done,
     /* 163798 */   // Label 2871: @163798
     /* 163798 */   GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(163842), // Rule ID 4755 //
     /* 163803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 163810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163814 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 163821 */     // (st FPR128:{ *:[v4i32] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v4i32] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 163821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 163824 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163826 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 163836 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163840 */     GIR_RootConstrainSelectedInstOperands,
     /* 163841 */     // GIR_Coverage, 4755,
     /* 163841 */     GIR_EraseRootFromParent_Done,
     /* 163842 */   // Label 2872: @163842
     /* 163842 */   GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(163862), // Rule ID 7039 //
     /* 163847 */     // MIs[0] Rn
     /* 163847 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 163851 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 163855 */     // (st v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev4s v4i32:{ *:[v4i32] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 163855 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev4s),
     /* 163860 */     GIR_RootConstrainSelectedInstOperands,
     /* 163861 */     // GIR_Coverage, 7039,
     /* 163861 */     GIR_Done,
     /* 163862 */   // Label 2873: @163862
     /* 163862 */   GIM_Reject,
     /* 163863 */ // Label 2864: @163863
     /* 163863 */ GIM_Reject,
     /* 163864 */ // Label 2676: @163864
     /* 163864 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(164083),
     /* 163869 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 163872 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 163876 */   GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(163925), // Rule ID 4680 //
     /* 163881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163884 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163888 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163892 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 163899 */     // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroW FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 163899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroW),
     /* 163902 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163919 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163923 */     GIR_RootConstrainSelectedInstOperands,
     /* 163924 */     // GIR_Coverage, 4680,
     /* 163924 */     GIR_EraseRootFromParent_Done,
     /* 163925 */   // Label 2875: @163925
     /* 163925 */   GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(163974), // Rule ID 4681 //
     /* 163930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163937 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163941 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 163948 */     // (st FPR64:{ *:[v8i8] }:$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDroX FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 163948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDroX),
     /* 163951 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 163953 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 163958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 163963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 163968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 163972 */     GIR_RootConstrainSelectedInstOperands,
     /* 163973 */     // GIR_Coverage, 4681,
     /* 163973 */     GIR_EraseRootFromParent_Done,
     /* 163974 */   // Label 2876: @163974
     /* 163974 */   GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(164018), // Rule ID 4717 //
     /* 163979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 163982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 163986 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 163990 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 163997 */     // (st FPR64:{ *:[v8i8] }:$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRDui FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 163997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRDui),
     /* 164000 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164007 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164012 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164016 */     GIR_RootConstrainSelectedInstOperands,
     /* 164017 */     // GIR_Coverage, 4717,
     /* 164017 */     GIR_EraseRootFromParent_Done,
     /* 164018 */   // Label 2877: @164018
     /* 164018 */   GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(164062), // Rule ID 4746 //
     /* 164023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 164030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164034 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 164041 */     // (st FPR64:{ *:[v8i8] }:$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURDi FPR64:{ *:[v8i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 164041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURDi),
     /* 164044 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164056 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164060 */     GIR_RootConstrainSelectedInstOperands,
     /* 164061 */     // GIR_Coverage, 4746,
     /* 164061 */     GIR_EraseRootFromParent_Done,
     /* 164062 */   // Label 2878: @164062
     /* 164062 */   GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(164082), // Rule ID 7041 //
     /* 164067 */     // MIs[0] Rn
     /* 164067 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164071 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 164075 */     // (st v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev8b v8i8:{ *:[v8i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 164075 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8b),
     /* 164080 */     GIR_RootConstrainSelectedInstOperands,
     /* 164081 */     // GIR_Coverage, 7041,
     /* 164081 */     GIR_Done,
     /* 164082 */   // Label 2879: @164082
     /* 164082 */   GIM_Reject,
     /* 164083 */ // Label 2874: @164083
     /* 164083 */ GIM_Reject,
     /* 164084 */ // Label 2677: @164084
     /* 164084 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(164489),
     /* 164089 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 164092 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 164096 */   GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(164145), // Rule ID 4696 //
     /* 164101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164108 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164112 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 164119 */     // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 164119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 164122 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164134 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164143 */     GIR_RootConstrainSelectedInstOperands,
     /* 164144 */     // GIR_Coverage, 4696,
     /* 164144 */     GIR_EraseRootFromParent_Done,
     /* 164145 */   // Label 2881: @164145
     /* 164145 */   GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(164194), // Rule ID 4697 //
     /* 164150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164157 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 164168 */     // (st FPR128:{ *:[v8i16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 164168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 164171 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164188 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164192 */     GIR_RootConstrainSelectedInstOperands,
     /* 164193 */     // GIR_Coverage, 4697,
     /* 164193 */     GIR_EraseRootFromParent_Done,
     /* 164194 */   // Label 2882: @164194
     /* 164194 */   GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(164243), // Rule ID 4700 //
     /* 164199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164210 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 164217 */     // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 164217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 164220 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164222 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164227 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164241 */     GIR_RootConstrainSelectedInstOperands,
     /* 164242 */     // GIR_Coverage, 4700,
     /* 164242 */     GIR_EraseRootFromParent_Done,
     /* 164243 */   // Label 2883: @164243
     /* 164243 */   GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(164292), // Rule ID 4701 //
     /* 164248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164255 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164259 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 164266 */     // (st FPR128:{ *:[v8f16] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 164266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 164269 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164286 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164290 */     GIR_RootConstrainSelectedInstOperands,
     /* 164291 */     // GIR_Coverage, 4701,
     /* 164291 */     GIR_EraseRootFromParent_Done,
     /* 164292 */   // Label 2884: @164292
     /* 164292 */   GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(164336), // Rule ID 4725 //
     /* 164297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164308 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 164315 */     // (st FPR128:{ *:[v8i16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 164315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 164318 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164325 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164330 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164334 */     GIR_RootConstrainSelectedInstOperands,
     /* 164335 */     // GIR_Coverage, 4725,
     /* 164335 */     GIR_EraseRootFromParent_Done,
     /* 164336 */   // Label 2885: @164336
     /* 164336 */   GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(164380), // Rule ID 4728 //
     /* 164341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164352 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 164359 */     // (st FPR128:{ *:[v8f16] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 164359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 164362 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164364 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164369 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164378 */     GIR_RootConstrainSelectedInstOperands,
     /* 164379 */     // GIR_Coverage, 4728,
     /* 164379 */     GIR_EraseRootFromParent_Done,
     /* 164380 */   // Label 2886: @164380
     /* 164380 */   GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(164424), // Rule ID 4754 //
     /* 164385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164392 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164396 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 164403 */     // (st FPR128:{ *:[v8i16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8i16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 164403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 164406 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164408 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164413 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164422 */     GIR_RootConstrainSelectedInstOperands,
     /* 164423 */     // GIR_Coverage, 4754,
     /* 164423 */     GIR_EraseRootFromParent_Done,
     /* 164424 */   // Label 2887: @164424
     /* 164424 */   GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(164468), // Rule ID 4758 //
     /* 164429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164436 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164440 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 164447 */     // (st FPR128:{ *:[v8f16] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v8f16] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 164447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 164450 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164452 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164457 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164466 */     GIR_RootConstrainSelectedInstOperands,
     /* 164467 */     // GIR_Coverage, 4758,
     /* 164467 */     GIR_EraseRootFromParent_Done,
     /* 164468 */   // Label 2888: @164468
     /* 164468 */   GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(164488), // Rule ID 7038 //
     /* 164473 */     // MIs[0] Rn
     /* 164473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 164481 */     // (st v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev8h v8i16:{ *:[v8i16] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 164481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev8h),
     /* 164486 */     GIR_RootConstrainSelectedInstOperands,
     /* 164487 */     // GIR_Coverage, 7038,
     /* 164487 */     GIR_Done,
     /* 164488 */   // Label 2889: @164488
     /* 164488 */   GIM_Reject,
     /* 164489 */ // Label 2880: @164489
     /* 164489 */ GIM_Reject,
     /* 164490 */ // Label 2678: @164490
     /* 164490 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(164709),
     /* 164495 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 164498 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 164502 */   GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(164551), // Rule ID 4698 //
     /* 164507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164514 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164518 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed128),
     /* 164525 */     // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Windexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroW FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend128:{ *:[i32] }:$extend)
     /* 164525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroW),
     /* 164528 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164530 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164545 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164549 */     GIR_RootConstrainSelectedInstOperands,
     /* 164550 */     // GIR_Coverage, 4698,
     /* 164550 */     GIR_EraseRootFromParent_Done,
     /* 164551 */   // Label 2891: @164551
     /* 164551 */   GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(164600), // Rule ID 4699 //
     /* 164556 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE_UseSTRQro),
     /* 164559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164567 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed128),
     /* 164574 */     // (st FPR128:{ *:[v16i8] }:$Rt, (ro_Xindexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQroX FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend128:{ *:[i32] }:$extend)
     /* 164574 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQroX),
     /* 164577 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164584 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 164589 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 164594 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164598 */     GIR_RootConstrainSelectedInstOperands,
     /* 164599 */     // GIR_Coverage, 4699,
     /* 164599 */     GIR_EraseRootFromParent_Done,
     /* 164600 */   // Label 2892: @164600
     /* 164600 */   GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(164644), // Rule ID 4724 //
     /* 164605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164616 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed128),
     /* 164623 */     // (st FPR128:{ *:[v16i8] }:$Rt, (am_indexed128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STRQui FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s16:{ *:[i64] }:$offset)
     /* 164623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STRQui),
     /* 164626 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164633 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164642 */     GIR_RootConstrainSelectedInstOperands,
     /* 164643 */     // GIR_Coverage, 4724,
     /* 164643 */     GIR_EraseRootFromParent_Done,
     /* 164644 */   // Label 2893: @164644
     /* 164644 */   GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(164688), // Rule ID 4753 //
     /* 164649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsLE),
     /* 164652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 164656 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 164660 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled128),
     /* 164667 */     // (st FPR128:{ *:[v16i8] }:$Rt, (am_unscaled128:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STURQi FPR128:{ *:[v16i8] }:$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset)
     /* 164667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STURQi),
     /* 164670 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 164672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 164677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 164682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164686 */     GIR_RootConstrainSelectedInstOperands,
     /* 164687 */     // GIR_Coverage, 4753,
     /* 164687 */     GIR_EraseRootFromParent_Done,
     /* 164688 */   // Label 2894: @164688
     /* 164688 */   GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(164708), // Rule ID 7037 //
     /* 164693 */     // MIs[0] Rn
     /* 164693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164697 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 164701 */     // (st v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1Onev16b v16i8:{ *:[v16i8] }:$Vt, GPR64sp:{ *:[i64] }:$Rn)
     /* 164701 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ST1Onev16b),
     /* 164706 */     GIR_RootConstrainSelectedInstOperands,
     /* 164707 */     // GIR_Coverage, 7037,
     /* 164707 */     GIR_Done,
     /* 164708 */   // Label 2895: @164708
     /* 164708 */   GIM_Reject,
     /* 164709 */ // Label 2890: @164709
     /* 164709 */ GIM_Reject,
     /* 164710 */ // Label 2679: @164710
     /* 164710 */ GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(164769), // Rule ID 11616 //
     /* 164715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 164718 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 164721 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 164725 */   // MIs[0] base
     /* 164725 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164729 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164733 */   // (st nxv2f16:{ *:[nxv2f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_D_IMM ZPR:{ *:[nxv2f16] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164733 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 164736 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 164740 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 164745 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 164748 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 164750 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_D_IMM),
     /* 164753 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164755 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 164758 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164760 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164763 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164767 */   GIR_RootConstrainSelectedInstOperands,
     /* 164768 */   // GIR_Coverage, 11616,
     /* 164768 */   GIR_EraseRootFromParent_Done,
     /* 164769 */ // Label 2896: @164769
     /* 164769 */ GIM_Reject,
     /* 164770 */ // Label 2680: @164770
     /* 164770 */ GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(164829), // Rule ID 11622 //
     /* 164775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 164778 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 164781 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 164785 */   // MIs[0] base
     /* 164785 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164789 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164793 */   // (st nxv2f32:{ *:[nxv2f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_D_IMM ZPR:{ *:[nxv2f32] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164793 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 164796 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 164800 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 164805 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 164808 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 164810 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_D_IMM),
     /* 164813 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164815 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 164818 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164820 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164823 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164827 */   GIR_RootConstrainSelectedInstOperands,
     /* 164828 */   // GIR_Coverage, 11622,
     /* 164828 */   GIR_EraseRootFromParent_Done,
     /* 164829 */ // Label 2897: @164829
     /* 164829 */ GIM_Reject,
     /* 164830 */ // Label 2681: @164830
     /* 164830 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(164999),
     /* 164835 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 164838 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 164842 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 164846 */   GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(164894), // Rule ID 11607 //
     /* 164851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 164854 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164858 */     // (st nxv2i64:{ *:[nxv2i64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1D_IMM ZPR:{ *:[nxv2i64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164858 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 164861 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 164865 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 164870 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 164873 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 164875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
     /* 164878 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164880 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 164883 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164892 */     GIR_RootConstrainSelectedInstOperands,
     /* 164893 */     // GIR_Coverage, 11607,
     /* 164893 */     GIR_EraseRootFromParent_Done,
     /* 164894 */   // Label 2899: @164894
     /* 164894 */   GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(164942), // Rule ID 11625 //
     /* 164899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 164902 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 164906 */     // (st nxv2f64:{ *:[nxv2f64] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1D_IMM ZPR:{ *:[nxv2f64] }:$val, (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164906 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 164909 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 164913 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 164918 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 164921 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 164923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_IMM),
     /* 164926 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164928 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 164931 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164933 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164940 */     GIR_RootConstrainSelectedInstOperands,
     /* 164941 */     // GIR_Coverage, 11625,
     /* 164941 */     GIR_EraseRootFromParent_Done,
     /* 164942 */   // Label 2900: @164942
     /* 164942 */   GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(164970), // Rule ID 11779 //
     /* 164947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 164950 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 164954 */     // (st nxv2i64:{ *:[nxv2i64] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv2i64] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 164957 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164959 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164968 */     GIR_RootConstrainSelectedInstOperands,
     /* 164969 */     // GIR_Coverage, 11779,
     /* 164969 */     GIR_EraseRootFromParent_Done,
     /* 164970 */   // Label 2901: @164970
     /* 164970 */   GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(164998), // Rule ID 11791 //
     /* 164975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 164978 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 164982 */     // (st nxv2f64:{ *:[nxv2f64] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv2f64] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 164982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 164985 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 164987 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 164989 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 164992 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 164996 */     GIR_RootConstrainSelectedInstOperands,
     /* 164997 */     // GIR_Coverage, 11791,
     /* 164997 */     GIR_EraseRootFromParent_Done,
     /* 164998 */   // Label 2902: @164998
     /* 164998 */   GIM_Reject,
     /* 164999 */ // Label 2898: @164999
     /* 164999 */ GIM_Reject,
     /* 165000 */ // Label 2682: @165000
     /* 165000 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(165059), // Rule ID 11613 //
     /* 165005 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165008 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 165011 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 165015 */   // MIs[0] base
     /* 165015 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165019 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165023 */   // (st nxv4f16:{ *:[nxv4f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_S_IMM ZPR:{ *:[nxv4f16] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165023 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165026 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 165030 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165035 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165038 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165040 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_S_IMM),
     /* 165043 */   GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165045 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165048 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165050 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165053 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165057 */   GIR_RootConstrainSelectedInstOperands,
     /* 165058 */   // GIR_Coverage, 11613,
     /* 165058 */   GIR_EraseRootFromParent_Done,
     /* 165059 */ // Label 2903: @165059
     /* 165059 */ GIM_Reject,
     /* 165060 */ // Label 2683: @165060
     /* 165060 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(165229),
     /* 165065 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 165068 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 165072 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165076 */   GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(165124), // Rule ID 11601 //
     /* 165081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165084 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165088 */     // (st nxv4i32:{ *:[nxv4i32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_IMM ZPR:{ *:[nxv4i32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165088 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165091 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 165095 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165100 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165103 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
     /* 165108 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165110 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165113 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165115 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165118 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165122 */     GIR_RootConstrainSelectedInstOperands,
     /* 165123 */     // GIR_Coverage, 11601,
     /* 165123 */     GIR_EraseRootFromParent_Done,
     /* 165124 */   // Label 2905: @165124
     /* 165124 */   GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(165172), // Rule ID 11619 //
     /* 165129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165132 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165136 */     // (st nxv4f32:{ *:[nxv4f32] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1W_IMM ZPR:{ *:[nxv4f32] }:$val, (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165136 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165139 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 165143 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165148 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165151 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_IMM),
     /* 165156 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165158 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165161 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165163 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165166 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165170 */     GIR_RootConstrainSelectedInstOperands,
     /* 165171 */     // GIR_Coverage, 11619,
     /* 165171 */     GIR_EraseRootFromParent_Done,
     /* 165172 */   // Label 2906: @165172
     /* 165172 */   GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(165200), // Rule ID 11775 //
     /* 165177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 165180 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165184 */     // (st nxv4i32:{ *:[nxv4i32] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv4i32] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 165187 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165189 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165194 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165198 */     GIR_RootConstrainSelectedInstOperands,
     /* 165199 */     // GIR_Coverage, 11775,
     /* 165199 */     GIR_EraseRootFromParent_Done,
     /* 165200 */   // Label 2907: @165200
     /* 165200 */   GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(165228), // Rule ID 11787 //
     /* 165205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 165208 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165212 */     // (st nxv4f32:{ *:[nxv4f32] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv4f32] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 165215 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165217 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165219 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165226 */     GIR_RootConstrainSelectedInstOperands,
     /* 165227 */     // GIR_Coverage, 11787,
     /* 165227 */     GIR_EraseRootFromParent_Done,
     /* 165228 */   // Label 2908: @165228
     /* 165228 */   GIM_Reject,
     /* 165229 */ // Label 2904: @165229
     /* 165229 */ GIM_Reject,
     /* 165230 */ // Label 2684: @165230
     /* 165230 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(165399),
     /* 165235 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 165238 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 165242 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165246 */   GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(165294), // Rule ID 11592 //
     /* 165251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165254 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165258 */     // (st nxv8i16:{ *:[nxv8i16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_IMM ZPR:{ *:[nxv8i16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165258 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165261 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 165265 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165270 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165273 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
     /* 165278 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165280 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165283 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165292 */     GIR_RootConstrainSelectedInstOperands,
     /* 165293 */     // GIR_Coverage, 11592,
     /* 165293 */     GIR_EraseRootFromParent_Done,
     /* 165294 */   // Label 2910: @165294
     /* 165294 */   GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(165342), // Rule ID 11610 //
     /* 165299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165306 */     // (st nxv8f16:{ *:[nxv8f16] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1H_IMM ZPR:{ *:[nxv8f16] }:$val, (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165306 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165309 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 165313 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165318 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165321 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1H_IMM),
     /* 165326 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165328 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165331 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165340 */     GIR_RootConstrainSelectedInstOperands,
     /* 165341 */     // GIR_Coverage, 11610,
     /* 165341 */     GIR_EraseRootFromParent_Done,
     /* 165342 */   // Label 2911: @165342
     /* 165342 */   GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(165370), // Rule ID 11771 //
     /* 165347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 165350 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165354 */     // (st nxv8i16:{ *:[nxv8i16] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv8i16] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 165357 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165359 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165368 */     GIR_RootConstrainSelectedInstOperands,
     /* 165369 */     // GIR_Coverage, 11771,
     /* 165369 */     GIR_EraseRootFromParent_Done,
     /* 165370 */   // Label 2912: @165370
     /* 165370 */   GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(165398), // Rule ID 11783 //
     /* 165375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 165378 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165382 */     // (st nxv8f16:{ *:[nxv8f16] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv8f16] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 165385 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165387 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165389 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165392 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165396 */     GIR_RootConstrainSelectedInstOperands,
     /* 165397 */     // GIR_Coverage, 11783,
     /* 165397 */     GIR_EraseRootFromParent_Done,
     /* 165398 */   // Label 2913: @165398
     /* 165398 */   GIM_Reject,
     /* 165399 */ // Label 2909: @165399
     /* 165399 */ GIM_Reject,
     /* 165400 */ // Label 2685: @165400
     /* 165400 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(165443), // Rule ID 2467 //
     /* 165405 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165408 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 165411 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 165415 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 165419 */   // MIs[0] base
     /* 165419 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165423 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165427 */   // (st PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_PXI PPR:{ *:[nxv16i1] }:$Val, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165427 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_PXI),
     /* 165430 */   GIR_RootToRootCopy, /*OpIdx*/0, // Val
     /* 165432 */   GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165434 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165437 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165441 */   GIR_RootConstrainSelectedInstOperands,
     /* 165442 */   // GIR_Coverage, 2467,
     /* 165442 */   GIR_EraseRootFromParent_Done,
     /* 165443 */ // Label 2914: @165443
     /* 165443 */ GIM_Reject,
     /* 165444 */ // Label 2686: @165444
     /* 165444 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(165537),
     /* 165449 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 165452 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 165456 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165460 */   GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(165508), // Rule ID 11578 //
     /* 165465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 165468 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 165472 */     // (st nxv16i8:{ *:[nxv16i8] }:$val, GPR64:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (ST1B_IMM ZPR:{ *:[nxv16i8] }:$val, (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165472 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 165475 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 165479 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 165484 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/31,
     /* 165487 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 165489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1B_IMM),
     /* 165492 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165494 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 165497 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165502 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165506 */     GIR_RootConstrainSelectedInstOperands,
     /* 165507 */     // GIR_Coverage, 11578,
     /* 165507 */     GIR_EraseRootFromParent_Done,
     /* 165508 */   // Label 2916: @165508
     /* 165508 */   GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(165536), // Rule ID 11767 //
     /* 165513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowMisalignedMemAccesses_AllowUnpredicatedLdStLower_HasSVE_or_SME_IsLE),
     /* 165516 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165520 */     // (st nxv16i8:{ *:[nxv16i8] }:$val, GPR64sp:{ *:[i64] }:$base)<<P:Predicate_unindexedstore>><<P:Predicate_store>>  =>  (STR_ZXI ZPR:{ *:[nxv16i8] }:$val, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 165520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STR_ZXI),
     /* 165523 */     GIR_RootToRootCopy, /*OpIdx*/0, // val
     /* 165525 */     GIR_RootToRootCopy, /*OpIdx*/1, // base
     /* 165527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 165530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165534 */     GIR_RootConstrainSelectedInstOperands,
     /* 165535 */     // GIR_Coverage, 11767,
     /* 165535 */     GIR_EraseRootFromParent_Done,
     /* 165536 */   // Label 2917: @165536
     /* 165536 */   GIM_Reject,
     /* 165537 */ // Label 2915: @165537
     /* 165537 */ GIM_Reject,
     /* 165538 */ // Label 2687: @165538
     /* 165538 */ GIM_Reject,
     /* 165539 */ // Label 26: @165539
     /* 165539 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2920*/ GIMT_Encode4(166889),
     /* 165550 */ /*GILLT_s32*//*Label 2918*/ GIMT_Encode4(165558),
     /* 165554 */ /*GILLT_s64*//*Label 2919*/ GIMT_Encode4(166576),
     /* 165558 */ // Label 2918: @165558
     /* 165558 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(166575),
     /* 165563 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 165566 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 165569 */   GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(165624), // Rule ID 7964 //
     /* 165574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165577 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 165584 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 165587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165591 */     // MIs[0] Rn
     /* 165591 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165595 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165603 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165607 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_monotonic>>  =>  (CASW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASW),
     /* 165610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165616 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165618 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165622 */     GIR_RootConstrainSelectedInstOperands,
     /* 165623 */     // GIR_Coverage, 7964,
     /* 165623 */     GIR_EraseRootFromParent_Done,
     /* 165624 */   // Label 2922: @165624
     /* 165624 */   GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(165679), // Rule ID 7965 //
     /* 165629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165632 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 165639 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 165642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165646 */     // MIs[0] Rn
     /* 165646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165650 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165654 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165658 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165662 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acquire>>  =>  (CASAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAW),
     /* 165665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165667 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165669 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165671 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165677 */     GIR_RootConstrainSelectedInstOperands,
     /* 165678 */     // GIR_Coverage, 7965,
     /* 165678 */     GIR_EraseRootFromParent_Done,
     /* 165679 */   // Label 2923: @165679
     /* 165679 */   GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(165734), // Rule ID 7966 //
     /* 165684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165687 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 165694 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 165697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165701 */     // MIs[0] Rn
     /* 165701 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165705 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165709 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165713 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165717 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_release>>  =>  (CASLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLW),
     /* 165720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165722 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165724 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165726 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165732 */     GIR_RootConstrainSelectedInstOperands,
     /* 165733 */     // GIR_Coverage, 7966,
     /* 165733 */     GIR_EraseRootFromParent_Done,
     /* 165734 */   // Label 2924: @165734
     /* 165734 */   GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(165789), // Rule ID 7967 //
     /* 165739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165742 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 165749 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 165752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165756 */     // MIs[0] Rn
     /* 165756 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165760 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165768 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165772 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_acq_rel>>  =>  (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
     /* 165775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165779 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165787 */     GIR_RootConstrainSelectedInstOperands,
     /* 165788 */     // GIR_Coverage, 7967,
     /* 165788 */     GIR_EraseRootFromParent_Done,
     /* 165789 */   // Label 2925: @165789
     /* 165789 */   GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(165844), // Rule ID 7968 //
     /* 165794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165797 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 165804 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 165807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165811 */     // MIs[0] Rn
     /* 165811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165823 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165827 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i32>><<P:Predicate_atomic_cmp_swap_i32_seq_cst>>  =>  (CASALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALW),
     /* 165830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165832 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165834 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165836 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165842 */     GIR_RootConstrainSelectedInstOperands,
     /* 165843 */     // GIR_Coverage, 7968,
     /* 165843 */     GIR_EraseRootFromParent_Done,
     /* 165844 */   // Label 2926: @165844
     /* 165844 */   GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(165899), // Rule ID 7969 //
     /* 165849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165852 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 165859 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 165862 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165866 */     // MIs[0] Rn
     /* 165866 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165870 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165874 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165878 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165882 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_monotonic>>  =>  (CASH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASH),
     /* 165885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165889 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165891 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165897 */     GIR_RootConstrainSelectedInstOperands,
     /* 165898 */     // GIR_Coverage, 7969,
     /* 165898 */     GIR_EraseRootFromParent_Done,
     /* 165899 */   // Label 2927: @165899
     /* 165899 */   GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(165954), // Rule ID 7970 //
     /* 165904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165907 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 165914 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 165917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165921 */     // MIs[0] Rn
     /* 165921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165925 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165937 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acquire>>  =>  (CASAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAH),
     /* 165940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 165946 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 165948 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 165952 */     GIR_RootConstrainSelectedInstOperands,
     /* 165953 */     // GIR_Coverage, 7970,
     /* 165953 */     GIR_EraseRootFromParent_Done,
     /* 165954 */   // Label 2928: @165954
     /* 165954 */   GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(166009), // Rule ID 7971 //
     /* 165959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 165962 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 165969 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 165972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165976 */     // MIs[0] Rn
     /* 165976 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 165980 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 165984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165988 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 165992 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_release>>  =>  (CASLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 165992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLH),
     /* 165995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 165997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 165999 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166001 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166007 */     GIR_RootConstrainSelectedInstOperands,
     /* 166008 */     // GIR_Coverage, 7971,
     /* 166008 */     GIR_EraseRootFromParent_Done,
     /* 166009 */   // Label 2929: @166009
     /* 166009 */   GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(166064), // Rule ID 7972 //
     /* 166014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166017 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 166024 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 166027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166031 */     // MIs[0] Rn
     /* 166031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166035 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166047 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_acq_rel>>  =>  (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
     /* 166050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166056 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166062 */     GIR_RootConstrainSelectedInstOperands,
     /* 166063 */     // GIR_Coverage, 7972,
     /* 166063 */     GIR_EraseRootFromParent_Done,
     /* 166064 */   // Label 2930: @166064
     /* 166064 */   GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(166119), // Rule ID 7973 //
     /* 166069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166072 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 166079 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 166082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166086 */     // MIs[0] Rn
     /* 166086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166098 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166102 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i16>><<P:Predicate_atomic_cmp_swap_i16_seq_cst>>  =>  (CASALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALH),
     /* 166105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166111 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166113 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166117 */     GIR_RootConstrainSelectedInstOperands,
     /* 166118 */     // GIR_Coverage, 7973,
     /* 166118 */     GIR_EraseRootFromParent_Done,
     /* 166119 */   // Label 2931: @166119
     /* 166119 */   GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(166174), // Rule ID 7974 //
     /* 166124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166127 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166134 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 166137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166141 */     // MIs[0] Rn
     /* 166141 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166145 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166149 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166157 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_monotonic>>  =>  (CASB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASB),
     /* 166160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166166 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166168 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166172 */     GIR_RootConstrainSelectedInstOperands,
     /* 166173 */     // GIR_Coverage, 7974,
     /* 166173 */     GIR_EraseRootFromParent_Done,
     /* 166174 */   // Label 2932: @166174
     /* 166174 */   GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(166229), // Rule ID 7975 //
     /* 166179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166182 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166189 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 166192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166196 */     // MIs[0] Rn
     /* 166196 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166200 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166208 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166212 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acquire>>  =>  (CASAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAB),
     /* 166215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166219 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166221 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166227 */     GIR_RootConstrainSelectedInstOperands,
     /* 166228 */     // GIR_Coverage, 7975,
     /* 166228 */     GIR_EraseRootFromParent_Done,
     /* 166229 */   // Label 2933: @166229
     /* 166229 */   GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(166284), // Rule ID 7976 //
     /* 166234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166237 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166244 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 166247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166251 */     // MIs[0] Rn
     /* 166251 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166255 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166263 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166267 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_release>>  =>  (CASLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLB),
     /* 166270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166274 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166276 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166282 */     GIR_RootConstrainSelectedInstOperands,
     /* 166283 */     // GIR_Coverage, 7976,
     /* 166283 */     GIR_EraseRootFromParent_Done,
     /* 166284 */   // Label 2934: @166284
     /* 166284 */   GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(166339), // Rule ID 7977 //
     /* 166289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166292 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166299 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 166302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166306 */     // MIs[0] Rn
     /* 166306 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166310 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166318 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166322 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_acq_rel>>  =>  (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
     /* 166325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166329 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166331 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166333 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166337 */     GIR_RootConstrainSelectedInstOperands,
     /* 166338 */     // GIR_Coverage, 7977,
     /* 166338 */     GIR_EraseRootFromParent_Done,
     /* 166339 */   // Label 2935: @166339
     /* 166339 */   GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(166394), // Rule ID 7978 //
     /* 166344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166347 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166354 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 166357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166361 */     // MIs[0] Rn
     /* 166361 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166365 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166377 */     // (atomic_cmp_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i8>><<P:Predicate_atomic_cmp_swap_i8_seq_cst>>  =>  (CASALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rold, GPR32:{ *:[i32] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALB),
     /* 166380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166386 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166388 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166392 */     GIR_RootConstrainSelectedInstOperands,
     /* 166393 */     // GIR_Coverage, 7978,
     /* 166393 */     GIR_EraseRootFromParent_Done,
     /* 166394 */   // Label 2936: @166394
     /* 166394 */   GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(166454), // Rule ID 14177 //
     /* 166399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 166402 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 166409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166413 */     // MIs[0] addr
     /* 166413 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166417 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166421 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166425 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166429 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i8>>  =>  (CMP_SWAP_8:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 166429 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 166432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_8),
     /* 166435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166437 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 166442 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 166444 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 166446 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 166448 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166452 */     GIR_RootConstrainSelectedInstOperands,
     /* 166453 */     // GIR_Coverage, 14177,
     /* 166453 */     GIR_EraseRootFromParent_Done,
     /* 166454 */   // Label 2937: @166454
     /* 166454 */   GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(166514), // Rule ID 14178 //
     /* 166459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 166462 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 166469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166473 */     // MIs[0] addr
     /* 166473 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166481 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166485 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166489 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i16>>  =>  (CMP_SWAP_16:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 166489 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 166492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_16),
     /* 166495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166497 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 166502 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 166504 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 166506 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 166508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166512 */     GIR_RootConstrainSelectedInstOperands,
     /* 166513 */     // GIR_Coverage, 14178,
     /* 166513 */     GIR_EraseRootFromParent_Done,
     /* 166514 */   // Label 2938: @166514
     /* 166514 */   GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(166574), // Rule ID 14179 //
     /* 166519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 166522 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 166529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166533 */     // MIs[0] addr
     /* 166533 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166537 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166541 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166545 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166549 */     // (atomic_cmp_swap:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)<<P:Predicate_atomic_cmp_swap_i32>>  =>  (CMP_SWAP_32:{ *:[i32] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR32:{ *:[i32] }:$desired, GPR32:{ *:[i32] }:$new)
     /* 166549 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 166552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_32),
     /* 166555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166557 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 166562 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 166564 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 166566 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 166568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166572 */     GIR_RootConstrainSelectedInstOperands,
     /* 166573 */     // GIR_Coverage, 14179,
     /* 166573 */     GIR_EraseRootFromParent_Done,
     /* 166574 */   // Label 2939: @166574
     /* 166574 */   GIM_Reject,
     /* 166575 */ // Label 2921: @166575
     /* 166575 */ GIM_Reject,
     /* 166576 */ // Label 2919: @166576
     /* 166576 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(166888),
     /* 166581 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 166584 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 166587 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 166594 */   GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(166642), // Rule ID 2628 //
     /* 166599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166602 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 166605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166609 */     // MIs[0] Rn
     /* 166609 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166613 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166617 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166621 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166625 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_monotonic>>  =>  (CASX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASX),
     /* 166628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166630 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166632 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166634 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166636 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166640 */     GIR_RootConstrainSelectedInstOperands,
     /* 166641 */     // GIR_Coverage, 2628,
     /* 166641 */     GIR_EraseRootFromParent_Done,
     /* 166642 */   // Label 2941: @166642
     /* 166642 */   GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(166690), // Rule ID 2629 //
     /* 166647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166650 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 166653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166657 */     // MIs[0] Rn
     /* 166657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166661 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166673 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acquire>>  =>  (CASAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASAX),
     /* 166676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166682 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166684 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166688 */     GIR_RootConstrainSelectedInstOperands,
     /* 166689 */     // GIR_Coverage, 2629,
     /* 166689 */     GIR_EraseRootFromParent_Done,
     /* 166690 */   // Label 2942: @166690
     /* 166690 */   GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(166738), // Rule ID 2630 //
     /* 166695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166698 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 166701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166705 */     // MIs[0] Rn
     /* 166705 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166709 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166721 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_release>>  =>  (CASLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASLX),
     /* 166724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166730 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166732 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166736 */     GIR_RootConstrainSelectedInstOperands,
     /* 166737 */     // GIR_Coverage, 2630,
     /* 166737 */     GIR_EraseRootFromParent_Done,
     /* 166738 */   // Label 2943: @166738
     /* 166738 */   GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(166786), // Rule ID 2631 //
     /* 166743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166746 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 166749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166753 */     // MIs[0] Rn
     /* 166753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166757 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166761 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166765 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166769 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_acq_rel>>  =>  (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
     /* 166772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166778 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166780 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166784 */     GIR_RootConstrainSelectedInstOperands,
     /* 166785 */     // GIR_Coverage, 2631,
     /* 166785 */     GIR_EraseRootFromParent_Done,
     /* 166786 */   // Label 2944: @166786
     /* 166786 */   GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(166834), // Rule ID 2632 //
     /* 166791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166794 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 166797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166801 */     // MIs[0] Rn
     /* 166801 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166805 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166817 */     // (atomic_cmp_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew)<<P:Predicate_atomic_cmp_swap_i64>><<P:Predicate_atomic_cmp_swap_i64_seq_cst>>  =>  (CASALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rold, GPR64:{ *:[i64] }:$Rnew, GPR64sp:{ *:[i64] }:$Rn)
     /* 166817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CASALX),
     /* 166820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out]
     /* 166822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rold
     /* 166824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rnew
     /* 166826 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166828 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166832 */     GIR_RootConstrainSelectedInstOperands,
     /* 166833 */     // GIR_Coverage, 2632,
     /* 166833 */     GIR_EraseRootFromParent_Done,
     /* 166834 */   // Label 2945: @166834
     /* 166834 */   GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(166887), // Rule ID 14180 //
     /* 166839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoLSE),
     /* 166842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166846 */     // MIs[0] addr
     /* 166846 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166850 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166854 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166858 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 166862 */     // (atomic_cmp_swap:{ *:[i64] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)<<P:Predicate_atomic_cmp_swap_i64>>  =>  (CMP_SWAP_64:{ *:[i64] }:{ *:[i32] } GPR64:{ *:[i64] }:$addr, GPR64:{ *:[i64] }:$desired, GPR64:{ *:[i64] }:$new)
     /* 166862 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 166865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMP_SWAP_64),
     /* 166868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 166870 */     GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
     /* 166875 */     GIR_RootToRootCopy, /*OpIdx*/1, // addr
     /* 166877 */     GIR_RootToRootCopy, /*OpIdx*/2, // desired
     /* 166879 */     GIR_RootToRootCopy, /*OpIdx*/3, // new
     /* 166881 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166885 */     GIR_RootConstrainSelectedInstOperands,
     /* 166886 */     // GIR_Coverage, 14180,
     /* 166886 */     GIR_EraseRootFromParent_Done,
     /* 166887 */   // Label 2946: @166887
     /* 166887 */   GIM_Reject,
     /* 166888 */ // Label 2940: @166888
     /* 166888 */ GIM_Reject,
     /* 166889 */ // Label 2920: @166889
     /* 166889 */ GIM_Reject,
     /* 166890 */ // Label 27: @166890
     /* 166890 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2949*/ GIMT_Encode4(167881),
     /* 166901 */ /*GILLT_s32*//*Label 2947*/ GIMT_Encode4(166909),
     /* 166905 */ /*GILLT_s64*//*Label 2948*/ GIMT_Encode4(167654),
     /* 166909 */ // Label 2947: @166909
     /* 166909 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(167653),
     /* 166914 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 166917 */   GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(166966), // Rule ID 7949 //
     /* 166922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166925 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 166932 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 166935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166939 */     // MIs[0] Rn
     /* 166939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166943 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166947 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166951 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_monotonic>>  =>  (SWPW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 166951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPW),
     /* 166954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 166956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 166958 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 166960 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 166964 */     GIR_RootConstrainSelectedInstOperands,
     /* 166965 */     // GIR_Coverage, 7949,
     /* 166965 */     GIR_EraseRootFromParent_Done,
     /* 166966 */   // Label 2951: @166966
     /* 166966 */   GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(167015), // Rule ID 7950 //
     /* 166971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 166974 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 166981 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 166984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 166988 */     // MIs[0] Rn
     /* 166988 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 166992 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 166996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167000 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acquire>>  =>  (SWPAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAW),
     /* 167003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167005 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167007 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167013 */     GIR_RootConstrainSelectedInstOperands,
     /* 167014 */     // GIR_Coverage, 7950,
     /* 167014 */     GIR_EraseRootFromParent_Done,
     /* 167015 */   // Label 2952: @167015
     /* 167015 */   GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(167064), // Rule ID 7951 //
     /* 167020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167023 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 167030 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 167033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167037 */     // MIs[0] Rn
     /* 167037 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167041 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167045 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167049 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_release>>  =>  (SWPLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLW),
     /* 167052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167056 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167062 */     GIR_RootConstrainSelectedInstOperands,
     /* 167063 */     // GIR_Coverage, 7951,
     /* 167063 */     GIR_EraseRootFromParent_Done,
     /* 167064 */   // Label 2953: @167064
     /* 167064 */   GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(167113), // Rule ID 7952 //
     /* 167069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167072 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 167079 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 167082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167086 */     // MIs[0] Rn
     /* 167086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167098 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_acq_rel>>  =>  (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
     /* 167101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167103 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167105 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167107 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167111 */     GIR_RootConstrainSelectedInstOperands,
     /* 167112 */     // GIR_Coverage, 7952,
     /* 167112 */     GIR_EraseRootFromParent_Done,
     /* 167113 */   // Label 2954: @167113
     /* 167113 */   GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(167162), // Rule ID 7953 //
     /* 167118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167121 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 167128 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 167131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167135 */     // MIs[0] Rn
     /* 167135 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167139 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167143 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167147 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i32>><<P:Predicate_atomic_swap_i32_seq_cst>>  =>  (SWPALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALW),
     /* 167150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167154 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167160 */     GIR_RootConstrainSelectedInstOperands,
     /* 167161 */     // GIR_Coverage, 7953,
     /* 167161 */     GIR_EraseRootFromParent_Done,
     /* 167162 */   // Label 2955: @167162
     /* 167162 */   GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(167211), // Rule ID 7954 //
     /* 167167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167170 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 167177 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 167180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167184 */     // MIs[0] Rn
     /* 167184 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167188 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167192 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167196 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_monotonic>>  =>  (SWPH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPH),
     /* 167199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167201 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167203 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167205 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167209 */     GIR_RootConstrainSelectedInstOperands,
     /* 167210 */     // GIR_Coverage, 7954,
     /* 167210 */     GIR_EraseRootFromParent_Done,
     /* 167211 */   // Label 2956: @167211
     /* 167211 */   GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(167260), // Rule ID 7955 //
     /* 167216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167219 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 167226 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 167229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167233 */     // MIs[0] Rn
     /* 167233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167237 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167241 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167245 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acquire>>  =>  (SWPAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAH),
     /* 167248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167252 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167254 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167258 */     GIR_RootConstrainSelectedInstOperands,
     /* 167259 */     // GIR_Coverage, 7955,
     /* 167259 */     GIR_EraseRootFromParent_Done,
     /* 167260 */   // Label 2957: @167260
     /* 167260 */   GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(167309), // Rule ID 7956 //
     /* 167265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167268 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 167275 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 167278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167282 */     // MIs[0] Rn
     /* 167282 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167286 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167290 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167294 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_release>>  =>  (SWPLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLH),
     /* 167297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167299 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167301 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167307 */     GIR_RootConstrainSelectedInstOperands,
     /* 167308 */     // GIR_Coverage, 7956,
     /* 167308 */     GIR_EraseRootFromParent_Done,
     /* 167309 */   // Label 2958: @167309
     /* 167309 */   GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(167358), // Rule ID 7957 //
     /* 167314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167317 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 167324 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 167327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167331 */     // MIs[0] Rn
     /* 167331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167343 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_acq_rel>>  =>  (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
     /* 167346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167350 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167356 */     GIR_RootConstrainSelectedInstOperands,
     /* 167357 */     // GIR_Coverage, 7957,
     /* 167357 */     GIR_EraseRootFromParent_Done,
     /* 167358 */   // Label 2959: @167358
     /* 167358 */   GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(167407), // Rule ID 7958 //
     /* 167363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167366 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 167373 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 167376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167380 */     // MIs[0] Rn
     /* 167380 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167384 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167392 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i16>><<P:Predicate_atomic_swap_i16_seq_cst>>  =>  (SWPALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALH),
     /* 167395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167399 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167401 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167405 */     GIR_RootConstrainSelectedInstOperands,
     /* 167406 */     // GIR_Coverage, 7958,
     /* 167406 */     GIR_EraseRootFromParent_Done,
     /* 167407 */   // Label 2960: @167407
     /* 167407 */   GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(167456), // Rule ID 7959 //
     /* 167412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167415 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 167422 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 167425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167429 */     // MIs[0] Rn
     /* 167429 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167433 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167437 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167441 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_monotonic>>  =>  (SWPB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPB),
     /* 167444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167446 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167448 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167450 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167454 */     GIR_RootConstrainSelectedInstOperands,
     /* 167455 */     // GIR_Coverage, 7959,
     /* 167455 */     GIR_EraseRootFromParent_Done,
     /* 167456 */   // Label 2961: @167456
     /* 167456 */   GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(167505), // Rule ID 7960 //
     /* 167461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167464 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 167471 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 167474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167478 */     // MIs[0] Rn
     /* 167478 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167482 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167486 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167490 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acquire>>  =>  (SWPAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAB),
     /* 167493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167497 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167499 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167503 */     GIR_RootConstrainSelectedInstOperands,
     /* 167504 */     // GIR_Coverage, 7960,
     /* 167504 */     GIR_EraseRootFromParent_Done,
     /* 167505 */   // Label 2962: @167505
     /* 167505 */   GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(167554), // Rule ID 7961 //
     /* 167510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167513 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 167520 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 167523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167527 */     // MIs[0] Rn
     /* 167527 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167531 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167539 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_release>>  =>  (SWPLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLB),
     /* 167542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167546 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167552 */     GIR_RootConstrainSelectedInstOperands,
     /* 167553 */     // GIR_Coverage, 7961,
     /* 167553 */     GIR_EraseRootFromParent_Done,
     /* 167554 */   // Label 2963: @167554
     /* 167554 */   GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(167603), // Rule ID 7962 //
     /* 167559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167562 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 167569 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 167572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167576 */     // MIs[0] Rn
     /* 167576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167580 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167588 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_acq_rel>>  =>  (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
     /* 167591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167593 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167595 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167597 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167601 */     GIR_RootConstrainSelectedInstOperands,
     /* 167602 */     // GIR_Coverage, 7962,
     /* 167602 */     GIR_EraseRootFromParent_Done,
     /* 167603 */   // Label 2964: @167603
     /* 167603 */   GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(167652), // Rule ID 7963 //
     /* 167608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167611 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 167618 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 167621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167625 */     // MIs[0] Rn
     /* 167625 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167629 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167633 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167637 */     // (atomic_swap:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_swap_i8>><<P:Predicate_atomic_swap_i8_seq_cst>>  =>  (SWPALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALB),
     /* 167640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167642 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167644 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167646 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167650 */     GIR_RootConstrainSelectedInstOperands,
     /* 167651 */     // GIR_Coverage, 7963,
     /* 167651 */     GIR_EraseRootFromParent_Done,
     /* 167652 */   // Label 2965: @167652
     /* 167652 */   GIM_Reject,
     /* 167653 */ // Label 2950: @167653
     /* 167653 */ GIM_Reject,
     /* 167654 */ // Label 2948: @167654
     /* 167654 */ GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(167880),
     /* 167659 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 167662 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 167669 */   GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(167711), // Rule ID 7944 //
     /* 167674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167677 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 167680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167684 */     // MIs[0] Rn
     /* 167684 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167696 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_monotonic>>  =>  (SWPX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPX),
     /* 167699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167703 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167705 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167709 */     GIR_RootConstrainSelectedInstOperands,
     /* 167710 */     // GIR_Coverage, 7944,
     /* 167710 */     GIR_EraseRootFromParent_Done,
     /* 167711 */   // Label 2967: @167711
     /* 167711 */   GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(167753), // Rule ID 7945 //
     /* 167716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167719 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 167722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167726 */     // MIs[0] Rn
     /* 167726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167730 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167738 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acquire>>  =>  (SWPAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPAX),
     /* 167741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167745 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167747 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167751 */     GIR_RootConstrainSelectedInstOperands,
     /* 167752 */     // GIR_Coverage, 7945,
     /* 167752 */     GIR_EraseRootFromParent_Done,
     /* 167753 */   // Label 2968: @167753
     /* 167753 */   GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(167795), // Rule ID 7946 //
     /* 167758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167761 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 167764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167768 */     // MIs[0] Rn
     /* 167768 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167772 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167780 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_release>>  =>  (SWPLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPLX),
     /* 167783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167787 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167789 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167793 */     GIR_RootConstrainSelectedInstOperands,
     /* 167794 */     // GIR_Coverage, 7946,
     /* 167794 */     GIR_EraseRootFromParent_Done,
     /* 167795 */   // Label 2969: @167795
     /* 167795 */   GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(167837), // Rule ID 7947 //
     /* 167800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167803 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 167806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167810 */     // MIs[0] Rn
     /* 167810 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167814 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167822 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_acq_rel>>  =>  (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
     /* 167825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167829 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167835 */     GIR_RootConstrainSelectedInstOperands,
     /* 167836 */     // GIR_Coverage, 7947,
     /* 167836 */     GIR_EraseRootFromParent_Done,
     /* 167837 */   // Label 2970: @167837
     /* 167837 */   GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(167879), // Rule ID 7948 //
     /* 167842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167845 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 167848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167852 */     // MIs[0] Rn
     /* 167852 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167856 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 167864 */     // (atomic_swap:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_swap_i64>><<P:Predicate_atomic_swap_i64_seq_cst>>  =>  (SWPALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SWPALX),
     /* 167867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167869 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167871 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167873 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167877 */     GIR_RootConstrainSelectedInstOperands,
     /* 167878 */     // GIR_Coverage, 7948,
     /* 167878 */     GIR_EraseRootFromParent_Done,
     /* 167879 */   // Label 2971: @167879
     /* 167879 */   GIM_Reject,
     /* 167880 */ // Label 2966: @167880
     /* 167880 */ GIM_Reject,
     /* 167881 */ // Label 2949: @167881
     /* 167881 */ GIM_Reject,
     /* 167882 */ // Label 28: @167882
     /* 167882 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2974*/ GIMT_Encode4(168873),
     /* 167893 */ /*GILLT_s32*//*Label 2972*/ GIMT_Encode4(167901),
     /* 167897 */ /*GILLT_s64*//*Label 2973*/ GIMT_Encode4(168646),
     /* 167901 */ // Label 2972: @167901
     /* 167901 */ GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(168645),
     /* 167906 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 167909 */   GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(167958), // Rule ID 7789 //
     /* 167914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167917 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 167924 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 167927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167931 */     // MIs[0] Rn
     /* 167931 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167935 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167943 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_monotonic>>  =>  (LDADDW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
     /* 167946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167948 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167950 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 167952 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 167956 */     GIR_RootConstrainSelectedInstOperands,
     /* 167957 */     // GIR_Coverage, 7789,
     /* 167957 */     GIR_EraseRootFromParent_Done,
     /* 167958 */   // Label 2976: @167958
     /* 167958 */   GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(168007), // Rule ID 7790 //
     /* 167963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 167966 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 167973 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 167976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167980 */     // MIs[0] Rn
     /* 167980 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 167984 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 167988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 167992 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acquire>>  =>  (LDADDAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 167992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
     /* 167995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 167997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 167999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168001 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168005 */     GIR_RootConstrainSelectedInstOperands,
     /* 168006 */     // GIR_Coverage, 7790,
     /* 168006 */     GIR_EraseRootFromParent_Done,
     /* 168007 */   // Label 2977: @168007
     /* 168007 */   GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(168056), // Rule ID 7791 //
     /* 168012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168015 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 168022 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 168025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168029 */     // MIs[0] Rn
     /* 168029 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168033 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168037 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168041 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_release>>  =>  (LDADDLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
     /* 168044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168046 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168048 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168050 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168054 */     GIR_RootConstrainSelectedInstOperands,
     /* 168055 */     // GIR_Coverage, 7791,
     /* 168055 */     GIR_EraseRootFromParent_Done,
     /* 168056 */   // Label 2978: @168056
     /* 168056 */   GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(168105), // Rule ID 7792 //
     /* 168061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168064 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 168071 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 168074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168078 */     // MIs[0] Rn
     /* 168078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168086 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168090 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_acq_rel>>  =>  (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 168093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168097 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168103 */     GIR_RootConstrainSelectedInstOperands,
     /* 168104 */     // GIR_Coverage, 7792,
     /* 168104 */     GIR_EraseRootFromParent_Done,
     /* 168105 */   // Label 2979: @168105
     /* 168105 */   GIM_Try, /*On fail goto*//*Label 2980*/ GIMT_Encode4(168154), // Rule ID 7793 //
     /* 168110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168113 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 168120 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 168123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168127 */     // MIs[0] Rn
     /* 168127 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168131 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168139 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i32>><<P:Predicate_atomic_load_add_i32_seq_cst>>  =>  (LDADDALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 168142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168146 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168152 */     GIR_RootConstrainSelectedInstOperands,
     /* 168153 */     // GIR_Coverage, 7793,
     /* 168153 */     GIR_EraseRootFromParent_Done,
     /* 168154 */   // Label 2980: @168154
     /* 168154 */   GIM_Try, /*On fail goto*//*Label 2981*/ GIMT_Encode4(168203), // Rule ID 7794 //
     /* 168159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168162 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 168169 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 168172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168176 */     // MIs[0] Rn
     /* 168176 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168180 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168184 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168188 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_monotonic>>  =>  (LDADDH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
     /* 168191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168195 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168197 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168201 */     GIR_RootConstrainSelectedInstOperands,
     /* 168202 */     // GIR_Coverage, 7794,
     /* 168202 */     GIR_EraseRootFromParent_Done,
     /* 168203 */   // Label 2981: @168203
     /* 168203 */   GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(168252), // Rule ID 7795 //
     /* 168208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168211 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 168218 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 168221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168225 */     // MIs[0] Rn
     /* 168225 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168229 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168233 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168237 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acquire>>  =>  (LDADDAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
     /* 168240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168244 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168246 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168250 */     GIR_RootConstrainSelectedInstOperands,
     /* 168251 */     // GIR_Coverage, 7795,
     /* 168251 */     GIR_EraseRootFromParent_Done,
     /* 168252 */   // Label 2982: @168252
     /* 168252 */   GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(168301), // Rule ID 7796 //
     /* 168257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168260 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 168267 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 168270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168274 */     // MIs[0] Rn
     /* 168274 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168278 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168286 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_release>>  =>  (LDADDLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
     /* 168289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168291 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168293 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168299 */     GIR_RootConstrainSelectedInstOperands,
     /* 168300 */     // GIR_Coverage, 7796,
     /* 168300 */     GIR_EraseRootFromParent_Done,
     /* 168301 */   // Label 2983: @168301
     /* 168301 */   GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(168350), // Rule ID 7797 //
     /* 168306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168309 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 168316 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 168319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168323 */     // MIs[0] Rn
     /* 168323 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168327 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168331 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168335 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_acq_rel>>  =>  (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 168338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168340 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168342 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168344 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168348 */     GIR_RootConstrainSelectedInstOperands,
     /* 168349 */     // GIR_Coverage, 7797,
     /* 168349 */     GIR_EraseRootFromParent_Done,
     /* 168350 */   // Label 2984: @168350
     /* 168350 */   GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(168399), // Rule ID 7798 //
     /* 168355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168358 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 168365 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 168368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168372 */     // MIs[0] Rn
     /* 168372 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168384 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i16>><<P:Predicate_atomic_load_add_i16_seq_cst>>  =>  (LDADDALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 168387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168391 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168393 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168397 */     GIR_RootConstrainSelectedInstOperands,
     /* 168398 */     // GIR_Coverage, 7798,
     /* 168398 */     GIR_EraseRootFromParent_Done,
     /* 168399 */   // Label 2985: @168399
     /* 168399 */   GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(168448), // Rule ID 7799 //
     /* 168404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168407 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 168414 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 168417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168421 */     // MIs[0] Rn
     /* 168421 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168425 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168433 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_monotonic>>  =>  (LDADDB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
     /* 168436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168440 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168446 */     GIR_RootConstrainSelectedInstOperands,
     /* 168447 */     // GIR_Coverage, 7799,
     /* 168447 */     GIR_EraseRootFromParent_Done,
     /* 168448 */   // Label 2986: @168448
     /* 168448 */   GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(168497), // Rule ID 7800 //
     /* 168453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168456 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 168463 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 168466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168470 */     // MIs[0] Rn
     /* 168470 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168474 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168478 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168482 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acquire>>  =>  (LDADDAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
     /* 168485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168489 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168491 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168495 */     GIR_RootConstrainSelectedInstOperands,
     /* 168496 */     // GIR_Coverage, 7800,
     /* 168496 */     GIR_EraseRootFromParent_Done,
     /* 168497 */   // Label 2987: @168497
     /* 168497 */   GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(168546), // Rule ID 7801 //
     /* 168502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168505 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 168512 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 168515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168519 */     // MIs[0] Rn
     /* 168519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168527 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168531 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_release>>  =>  (LDADDLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
     /* 168534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168538 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168540 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168544 */     GIR_RootConstrainSelectedInstOperands,
     /* 168545 */     // GIR_Coverage, 7801,
     /* 168545 */     GIR_EraseRootFromParent_Done,
     /* 168546 */   // Label 2988: @168546
     /* 168546 */   GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(168595), // Rule ID 7802 //
     /* 168551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168554 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 168561 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 168564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168568 */     // MIs[0] Rn
     /* 168568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168580 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_acq_rel>>  =>  (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 168583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168587 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168593 */     GIR_RootConstrainSelectedInstOperands,
     /* 168594 */     // GIR_Coverage, 7802,
     /* 168594 */     GIR_EraseRootFromParent_Done,
     /* 168595 */   // Label 2989: @168595
     /* 168595 */   GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(168644), // Rule ID 7803 //
     /* 168600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168603 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 168610 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 168613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168617 */     // MIs[0] Rn
     /* 168617 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168621 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168629 */     // (atomic_load_add:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_add_i8>><<P:Predicate_atomic_load_add_i8_seq_cst>>  =>  (LDADDALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 168632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168636 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168642 */     GIR_RootConstrainSelectedInstOperands,
     /* 168643 */     // GIR_Coverage, 7803,
     /* 168643 */     GIR_EraseRootFromParent_Done,
     /* 168644 */   // Label 2990: @168644
     /* 168644 */   GIM_Reject,
     /* 168645 */ // Label 2975: @168645
     /* 168645 */ GIM_Reject,
     /* 168646 */ // Label 2973: @168646
     /* 168646 */ GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(168872),
     /* 168651 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 168654 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 168661 */   GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(168703), // Rule ID 2618 //
     /* 168666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168669 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 168672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168676 */     // MIs[0] Rn
     /* 168676 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168680 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168688 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_monotonic>>  =>  (LDADDX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
     /* 168691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168693 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168695 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168697 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168701 */     GIR_RootConstrainSelectedInstOperands,
     /* 168702 */     // GIR_Coverage, 2618,
     /* 168702 */     GIR_EraseRootFromParent_Done,
     /* 168703 */   // Label 2992: @168703
     /* 168703 */   GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(168745), // Rule ID 2619 //
     /* 168708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168711 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 168714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168718 */     // MIs[0] Rn
     /* 168718 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168722 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168730 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acquire>>  =>  (LDADDAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
     /* 168733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168735 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168737 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168739 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168743 */     GIR_RootConstrainSelectedInstOperands,
     /* 168744 */     // GIR_Coverage, 2619,
     /* 168744 */     GIR_EraseRootFromParent_Done,
     /* 168745 */   // Label 2993: @168745
     /* 168745 */   GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(168787), // Rule ID 2620 //
     /* 168750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168753 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 168756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168760 */     // MIs[0] Rn
     /* 168760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168764 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168768 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168772 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_release>>  =>  (LDADDLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
     /* 168775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168779 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168781 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168785 */     GIR_RootConstrainSelectedInstOperands,
     /* 168786 */     // GIR_Coverage, 2620,
     /* 168786 */     GIR_EraseRootFromParent_Done,
     /* 168787 */   // Label 2994: @168787
     /* 168787 */   GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(168829), // Rule ID 2621 //
     /* 168792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168795 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 168798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168802 */     // MIs[0] Rn
     /* 168802 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168806 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168814 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_acq_rel>>  =>  (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168814 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 168817 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168819 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168821 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168823 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168827 */     GIR_RootConstrainSelectedInstOperands,
     /* 168828 */     // GIR_Coverage, 2621,
     /* 168828 */     GIR_EraseRootFromParent_Done,
     /* 168829 */   // Label 2995: @168829
     /* 168829 */   GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(168871), // Rule ID 2622 //
     /* 168834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168837 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 168840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168844 */     // MIs[0] Rn
     /* 168844 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168848 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168852 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 168856 */     // (atomic_load_add:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_add_i64>><<P:Predicate_atomic_load_add_i64_seq_cst>>  =>  (LDADDALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 168856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 168859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 168863 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168865 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168869 */     GIR_RootConstrainSelectedInstOperands,
     /* 168870 */     // GIR_Coverage, 2622,
     /* 168870 */     GIR_EraseRootFromParent_Done,
     /* 168871 */   // Label 2996: @168871
     /* 168871 */   GIM_Reject,
     /* 168872 */ // Label 2991: @168872
     /* 168872 */ GIM_Reject,
     /* 168873 */ // Label 2974: @168873
     /* 168873 */ GIM_Reject,
     /* 168874 */ // Label 29: @168874
     /* 168874 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 2999*/ GIMT_Encode4(170365),
     /* 168885 */ /*GILLT_s32*//*Label 2997*/ GIMT_Encode4(168893),
     /* 168889 */ /*GILLT_s64*//*Label 2998*/ GIMT_Encode4(170013),
     /* 168893 */ // Label 2997: @168893
     /* 168893 */ GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(170012),
     /* 168898 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 168901 */   GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(168975), // Rule ID 7984 //
     /* 168906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168909 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 168916 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 168919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168923 */     // MIs[0] Rn
     /* 168923 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 168927 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 168931 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168935 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_monotonic>>  =>  (LDADDW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 168935 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 168938 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 168942 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 168947 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 168953 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 168957 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 168959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDW),
     /* 168962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 168964 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 168967 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 168969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 168973 */     GIR_RootConstrainSelectedInstOperands,
     /* 168974 */     // GIR_Coverage, 7984,
     /* 168974 */     GIR_EraseRootFromParent_Done,
     /* 168975 */   // Label 3001: @168975
     /* 168975 */   GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(169049), // Rule ID 7985 //
     /* 168980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 168983 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 168990 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 168993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 168997 */     // MIs[0] Rn
     /* 168997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169001 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169009 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acquire>>  =>  (LDADDAW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169009 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169012 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169016 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169021 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169027 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169031 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAW),
     /* 169036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169038 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169047 */     GIR_RootConstrainSelectedInstOperands,
     /* 169048 */     // GIR_Coverage, 7985,
     /* 169048 */     GIR_EraseRootFromParent_Done,
     /* 169049 */   // Label 3002: @169049
     /* 169049 */   GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(169123), // Rule ID 7986 //
     /* 169054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169057 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 169064 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 169067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169071 */     // MIs[0] Rn
     /* 169071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169083 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_release>>  =>  (LDADDLW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169083 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169086 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169090 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169095 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169101 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169105 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLW),
     /* 169110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169112 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169115 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169121 */     GIR_RootConstrainSelectedInstOperands,
     /* 169122 */     // GIR_Coverage, 7986,
     /* 169122 */     GIR_EraseRootFromParent_Done,
     /* 169123 */   // Label 3003: @169123
     /* 169123 */   GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(169197), // Rule ID 7987 //
     /* 169128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169131 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 169138 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 169141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169145 */     // MIs[0] Rn
     /* 169145 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169149 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169153 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169157 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_acq_rel>>  =>  (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169157 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169160 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169164 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169169 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169175 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169179 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 169184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169186 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169189 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169195 */     GIR_RootConstrainSelectedInstOperands,
     /* 169196 */     // GIR_Coverage, 7987,
     /* 169196 */     GIR_EraseRootFromParent_Done,
     /* 169197 */   // Label 3004: @169197
     /* 169197 */   GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(169271), // Rule ID 7988 //
     /* 169202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169205 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 169212 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 169215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169219 */     // MIs[0] Rn
     /* 169219 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169223 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169227 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169231 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i32>><<P:Predicate_atomic_load_sub_i32_seq_cst>>  =>  (LDADDALW:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169231 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169234 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169238 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169243 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169249 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169253 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALW),
     /* 169258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169260 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169263 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169265 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169269 */     GIR_RootConstrainSelectedInstOperands,
     /* 169270 */     // GIR_Coverage, 7988,
     /* 169270 */     GIR_EraseRootFromParent_Done,
     /* 169271 */   // Label 3005: @169271
     /* 169271 */   GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(169345), // Rule ID 7989 //
     /* 169276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169279 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 169286 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 169289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169293 */     // MIs[0] Rn
     /* 169293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169301 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169305 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_monotonic>>  =>  (LDADDH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169305 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169308 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169312 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169317 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169323 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169327 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDH),
     /* 169332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169334 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169337 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169339 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169343 */     GIR_RootConstrainSelectedInstOperands,
     /* 169344 */     // GIR_Coverage, 7989,
     /* 169344 */     GIR_EraseRootFromParent_Done,
     /* 169345 */   // Label 3006: @169345
     /* 169345 */   GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(169419), // Rule ID 7990 //
     /* 169350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169353 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 169360 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 169363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169367 */     // MIs[0] Rn
     /* 169367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169371 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169379 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acquire>>  =>  (LDADDAH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169379 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169382 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169386 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169391 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169397 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169401 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAH),
     /* 169406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169408 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169411 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169413 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169417 */     GIR_RootConstrainSelectedInstOperands,
     /* 169418 */     // GIR_Coverage, 7990,
     /* 169418 */     GIR_EraseRootFromParent_Done,
     /* 169419 */   // Label 3007: @169419
     /* 169419 */   GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(169493), // Rule ID 7991 //
     /* 169424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169427 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 169434 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 169437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169441 */     // MIs[0] Rn
     /* 169441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169445 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169453 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_release>>  =>  (LDADDLH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169453 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169456 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169460 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169465 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169471 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169475 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLH),
     /* 169480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169482 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169485 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169487 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169491 */     GIR_RootConstrainSelectedInstOperands,
     /* 169492 */     // GIR_Coverage, 7991,
     /* 169492 */     GIR_EraseRootFromParent_Done,
     /* 169493 */   // Label 3008: @169493
     /* 169493 */   GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(169567), // Rule ID 7992 //
     /* 169498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169501 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 169508 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 169511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169515 */     // MIs[0] Rn
     /* 169515 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169519 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169527 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_acq_rel>>  =>  (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169527 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169530 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169534 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169539 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169545 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169549 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 169554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169556 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169559 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169561 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169565 */     GIR_RootConstrainSelectedInstOperands,
     /* 169566 */     // GIR_Coverage, 7992,
     /* 169566 */     GIR_EraseRootFromParent_Done,
     /* 169567 */   // Label 3009: @169567
     /* 169567 */   GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(169641), // Rule ID 7993 //
     /* 169572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169575 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 169582 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 169585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169589 */     // MIs[0] Rn
     /* 169589 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169593 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169597 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169601 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i16>><<P:Predicate_atomic_load_sub_i16_seq_cst>>  =>  (LDADDALH:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169601 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169604 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169608 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169613 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169619 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169623 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALH),
     /* 169628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169630 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169633 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169639 */     GIR_RootConstrainSelectedInstOperands,
     /* 169640 */     // GIR_Coverage, 7993,
     /* 169640 */     GIR_EraseRootFromParent_Done,
     /* 169641 */   // Label 3010: @169641
     /* 169641 */   GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(169715), // Rule ID 7994 //
     /* 169646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169649 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 169656 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 169659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169663 */     // MIs[0] Rn
     /* 169663 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169667 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169671 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169675 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_monotonic>>  =>  (LDADDB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169675 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169678 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169682 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169687 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169693 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169697 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDB),
     /* 169702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169704 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169707 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169709 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169713 */     GIR_RootConstrainSelectedInstOperands,
     /* 169714 */     // GIR_Coverage, 7994,
     /* 169714 */     GIR_EraseRootFromParent_Done,
     /* 169715 */   // Label 3011: @169715
     /* 169715 */   GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(169789), // Rule ID 7995 //
     /* 169720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169723 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 169730 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 169733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169737 */     // MIs[0] Rn
     /* 169737 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169741 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169745 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169749 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acquire>>  =>  (LDADDAB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169749 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169752 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169756 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169761 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169767 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169771 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAB),
     /* 169776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169778 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169787 */     GIR_RootConstrainSelectedInstOperands,
     /* 169788 */     // GIR_Coverage, 7995,
     /* 169788 */     GIR_EraseRootFromParent_Done,
     /* 169789 */   // Label 3012: @169789
     /* 169789 */   GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(169863), // Rule ID 7996 //
     /* 169794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169797 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 169804 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 169807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169811 */     // MIs[0] Rn
     /* 169811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169823 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_release>>  =>  (LDADDLB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169823 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169826 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169830 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169835 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169841 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169845 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLB),
     /* 169850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169852 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169855 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169857 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169861 */     GIR_RootConstrainSelectedInstOperands,
     /* 169862 */     // GIR_Coverage, 7996,
     /* 169862 */     GIR_EraseRootFromParent_Done,
     /* 169863 */   // Label 3013: @169863
     /* 169863 */   GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(169937), // Rule ID 7997 //
     /* 169868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169871 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 169878 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 169881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169885 */     // MIs[0] Rn
     /* 169885 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169889 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169897 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_acq_rel>>  =>  (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169897 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169900 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169904 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169909 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169915 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 169924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 169926 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 169929 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 169931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 169935 */     GIR_RootConstrainSelectedInstOperands,
     /* 169936 */     // GIR_Coverage, 7997,
     /* 169936 */     GIR_EraseRootFromParent_Done,
     /* 169937 */   // Label 3014: @169937
     /* 169937 */   GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(170011), // Rule ID 7998 //
     /* 169942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 169945 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 169952 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 169955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169959 */     // MIs[0] Rn
     /* 169959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 169963 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 169967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 169971 */     // (atomic_load_sub:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_sub_i8>><<P:Predicate_atomic_load_sub_i8_seq_cst>>  =>  (LDADDALB:{ *:[i32] } (SUBWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 169971 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 169974 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBWrr),
     /* 169978 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 169983 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 169989 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 169993 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 169995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALB),
     /* 169998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170000 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170003 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170009 */     GIR_RootConstrainSelectedInstOperands,
     /* 170010 */     // GIR_Coverage, 7998,
     /* 170010 */     GIR_EraseRootFromParent_Done,
     /* 170011 */   // Label 3015: @170011
     /* 170011 */   GIM_Reject,
     /* 170012 */ // Label 3000: @170012
     /* 170012 */ GIM_Reject,
     /* 170013 */ // Label 2998: @170013
     /* 170013 */ GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(170364),
     /* 170018 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 170021 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 170028 */   GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(170095), // Rule ID 7979 //
     /* 170033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170036 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 170039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170043 */     // MIs[0] Rn
     /* 170043 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170047 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170055 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_monotonic>>  =>  (LDADDX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170055 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170058 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 170062 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170067 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170073 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170077 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDX),
     /* 170082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170084 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170087 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170089 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170093 */     GIR_RootConstrainSelectedInstOperands,
     /* 170094 */     // GIR_Coverage, 7979,
     /* 170094 */     GIR_EraseRootFromParent_Done,
     /* 170095 */   // Label 3017: @170095
     /* 170095 */   GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(170162), // Rule ID 7980 //
     /* 170100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170103 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 170106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170110 */     // MIs[0] Rn
     /* 170110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170114 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170122 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acquire>>  =>  (LDADDAX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170122 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170125 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 170129 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170134 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170140 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170144 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDAX),
     /* 170149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170151 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170154 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170156 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170160 */     GIR_RootConstrainSelectedInstOperands,
     /* 170161 */     // GIR_Coverage, 7980,
     /* 170161 */     GIR_EraseRootFromParent_Done,
     /* 170162 */   // Label 3018: @170162
     /* 170162 */   GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(170229), // Rule ID 7981 //
     /* 170167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170170 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 170173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170177 */     // MIs[0] Rn
     /* 170177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170189 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_release>>  =>  (LDADDLX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170189 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170192 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 170196 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170201 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170207 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170211 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDLX),
     /* 170216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170218 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170221 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170227 */     GIR_RootConstrainSelectedInstOperands,
     /* 170228 */     // GIR_Coverage, 7981,
     /* 170228 */     GIR_EraseRootFromParent_Done,
     /* 170229 */   // Label 3019: @170229
     /* 170229 */   GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(170296), // Rule ID 7982 //
     /* 170234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170237 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 170240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170244 */     // MIs[0] Rn
     /* 170244 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170248 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170252 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170256 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_acq_rel>>  =>  (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170256 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170259 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 170263 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170268 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170274 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170278 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 170283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170285 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170288 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170294 */     GIR_RootConstrainSelectedInstOperands,
     /* 170295 */     // GIR_Coverage, 7982,
     /* 170295 */     GIR_EraseRootFromParent_Done,
     /* 170296 */   // Label 3020: @170296
     /* 170296 */   GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(170363), // Rule ID 7983 //
     /* 170301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170304 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 170307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170311 */     // MIs[0] Rn
     /* 170311 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170315 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170319 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 170323 */     // (atomic_load_sub:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_sub_i64>><<P:Predicate_atomic_load_sub_i64_seq_cst>>  =>  (LDADDALX:{ *:[i64] } (SUBXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170323 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 170326 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SUBXrr),
     /* 170330 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170335 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170341 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170345 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDADDALX),
     /* 170350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170352 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170355 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170357 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170361 */     GIR_RootConstrainSelectedInstOperands,
     /* 170362 */     // GIR_Coverage, 7983,
     /* 170362 */     GIR_EraseRootFromParent_Done,
     /* 170363 */   // Label 3021: @170363
     /* 170363 */   GIM_Reject,
     /* 170364 */ // Label 3016: @170364
     /* 170364 */ GIM_Reject,
     /* 170365 */ // Label 2999: @170365
     /* 170365 */ GIM_Reject,
     /* 170366 */ // Label 30: @170366
     /* 170366 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3024*/ GIMT_Encode4(171857),
     /* 170377 */ /*GILLT_s32*//*Label 3022*/ GIMT_Encode4(170385),
     /* 170381 */ /*GILLT_s64*//*Label 3023*/ GIMT_Encode4(171505),
     /* 170385 */ // Label 3022: @170385
     /* 170385 */ GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(171504),
     /* 170390 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 170393 */   GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(170467), // Rule ID 8004 //
     /* 170398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170401 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 170408 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 170411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170415 */     // MIs[0] Rn
     /* 170415 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170427 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_monotonic>>  =>  (LDCLRW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170427 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170430 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170434 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170439 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170445 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170449 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRW),
     /* 170454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170456 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170459 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170461 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170465 */     GIR_RootConstrainSelectedInstOperands,
     /* 170466 */     // GIR_Coverage, 8004,
     /* 170466 */     GIR_EraseRootFromParent_Done,
     /* 170467 */   // Label 3026: @170467
     /* 170467 */   GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(170541), // Rule ID 8005 //
     /* 170472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170475 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 170482 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 170485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170489 */     // MIs[0] Rn
     /* 170489 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170493 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170497 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170501 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acquire>>  =>  (LDCLRAW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170501 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170504 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170508 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170513 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170523 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAW),
     /* 170528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170530 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170533 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170535 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170539 */     GIR_RootConstrainSelectedInstOperands,
     /* 170540 */     // GIR_Coverage, 8005,
     /* 170540 */     GIR_EraseRootFromParent_Done,
     /* 170541 */   // Label 3027: @170541
     /* 170541 */   GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(170615), // Rule ID 8006 //
     /* 170546 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170549 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 170556 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 170559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170563 */     // MIs[0] Rn
     /* 170563 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170567 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170571 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170575 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_release>>  =>  (LDCLRLW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170575 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170578 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170582 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170587 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170593 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170597 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLW),
     /* 170602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170604 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170607 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170609 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170613 */     GIR_RootConstrainSelectedInstOperands,
     /* 170614 */     // GIR_Coverage, 8006,
     /* 170614 */     GIR_EraseRootFromParent_Done,
     /* 170615 */   // Label 3028: @170615
     /* 170615 */   GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(170689), // Rule ID 8007 //
     /* 170620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170623 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 170630 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 170633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170637 */     // MIs[0] Rn
     /* 170637 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170641 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170645 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170649 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_acq_rel>>  =>  (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170649 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170652 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170656 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170661 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170667 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170671 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
     /* 170676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170681 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170683 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170687 */     GIR_RootConstrainSelectedInstOperands,
     /* 170688 */     // GIR_Coverage, 8007,
     /* 170688 */     GIR_EraseRootFromParent_Done,
     /* 170689 */   // Label 3029: @170689
     /* 170689 */   GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(170763), // Rule ID 8008 //
     /* 170694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170697 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 170704 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 170707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170711 */     // MIs[0] Rn
     /* 170711 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170715 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170719 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170723 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i32>><<P:Predicate_atomic_load_and_i32_seq_cst>>  =>  (LDCLRALW:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170723 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170726 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170730 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170735 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170741 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170745 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALW),
     /* 170750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170752 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170755 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170761 */     GIR_RootConstrainSelectedInstOperands,
     /* 170762 */     // GIR_Coverage, 8008,
     /* 170762 */     GIR_EraseRootFromParent_Done,
     /* 170763 */   // Label 3030: @170763
     /* 170763 */   GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(170837), // Rule ID 8009 //
     /* 170768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170771 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 170778 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 170781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170785 */     // MIs[0] Rn
     /* 170785 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170789 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170797 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_monotonic>>  =>  (LDCLRH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170797 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170800 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170804 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170809 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170815 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170819 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRH),
     /* 170824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170826 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170829 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170831 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170835 */     GIR_RootConstrainSelectedInstOperands,
     /* 170836 */     // GIR_Coverage, 8009,
     /* 170836 */     GIR_EraseRootFromParent_Done,
     /* 170837 */   // Label 3031: @170837
     /* 170837 */   GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(170911), // Rule ID 8010 //
     /* 170842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170845 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 170852 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 170855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170859 */     // MIs[0] Rn
     /* 170859 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170863 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170867 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170871 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acquire>>  =>  (LDCLRAH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170871 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170874 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170878 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170883 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170889 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170893 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAH),
     /* 170898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170900 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170903 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170905 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170909 */     GIR_RootConstrainSelectedInstOperands,
     /* 170910 */     // GIR_Coverage, 8010,
     /* 170910 */     GIR_EraseRootFromParent_Done,
     /* 170911 */   // Label 3032: @170911
     /* 170911 */   GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(170985), // Rule ID 8011 //
     /* 170916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170919 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 170926 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 170929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170933 */     // MIs[0] Rn
     /* 170933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 170937 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 170941 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 170945 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_release>>  =>  (LDCLRLH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 170945 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 170948 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 170952 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 170957 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 170963 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 170967 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 170969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLH),
     /* 170972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 170974 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 170977 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 170979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 170983 */     GIR_RootConstrainSelectedInstOperands,
     /* 170984 */     // GIR_Coverage, 8011,
     /* 170984 */     GIR_EraseRootFromParent_Done,
     /* 170985 */   // Label 3033: @170985
     /* 170985 */   GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(171059), // Rule ID 8012 //
     /* 170990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 170993 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 171000 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 171003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171007 */     // MIs[0] Rn
     /* 171007 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171011 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171019 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_acq_rel>>  =>  (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171019 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171022 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171026 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171031 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171037 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171041 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
     /* 171046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171048 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171051 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171053 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171057 */     GIR_RootConstrainSelectedInstOperands,
     /* 171058 */     // GIR_Coverage, 8012,
     /* 171058 */     GIR_EraseRootFromParent_Done,
     /* 171059 */   // Label 3034: @171059
     /* 171059 */   GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(171133), // Rule ID 8013 //
     /* 171064 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171067 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 171074 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 171077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171081 */     // MIs[0] Rn
     /* 171081 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171085 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171089 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171093 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i16>><<P:Predicate_atomic_load_and_i16_seq_cst>>  =>  (LDCLRALH:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171105 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171111 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171115 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALH),
     /* 171120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171122 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171125 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171131 */     GIR_RootConstrainSelectedInstOperands,
     /* 171132 */     // GIR_Coverage, 8013,
     /* 171132 */     GIR_EraseRootFromParent_Done,
     /* 171133 */   // Label 3035: @171133
     /* 171133 */   GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(171207), // Rule ID 8014 //
     /* 171138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171141 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 171148 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 171151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171155 */     // MIs[0] Rn
     /* 171155 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171163 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171167 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_monotonic>>  =>  (LDCLRB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171167 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171170 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171174 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171179 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171185 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171189 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRB),
     /* 171194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171196 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171199 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171201 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171205 */     GIR_RootConstrainSelectedInstOperands,
     /* 171206 */     // GIR_Coverage, 8014,
     /* 171206 */     GIR_EraseRootFromParent_Done,
     /* 171207 */   // Label 3036: @171207
     /* 171207 */   GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(171281), // Rule ID 8015 //
     /* 171212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171215 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 171222 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 171225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171229 */     // MIs[0] Rn
     /* 171229 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171241 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acquire>>  =>  (LDCLRAB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171241 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171244 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171248 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171253 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171259 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171263 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAB),
     /* 171268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171270 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171273 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171279 */     GIR_RootConstrainSelectedInstOperands,
     /* 171280 */     // GIR_Coverage, 8015,
     /* 171280 */     GIR_EraseRootFromParent_Done,
     /* 171281 */   // Label 3037: @171281
     /* 171281 */   GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(171355), // Rule ID 8016 //
     /* 171286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171289 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 171296 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 171299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171303 */     // MIs[0] Rn
     /* 171303 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171307 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171311 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171315 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_release>>  =>  (LDCLRLB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171315 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171318 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171322 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171327 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171333 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171337 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLB),
     /* 171342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171344 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171347 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171353 */     GIR_RootConstrainSelectedInstOperands,
     /* 171354 */     // GIR_Coverage, 8016,
     /* 171354 */     GIR_EraseRootFromParent_Done,
     /* 171355 */   // Label 3038: @171355
     /* 171355 */   GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(171429), // Rule ID 8017 //
     /* 171360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171363 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 171370 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 171373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171377 */     // MIs[0] Rn
     /* 171377 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171381 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171389 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_acq_rel>>  =>  (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171389 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171392 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171396 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171401 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171407 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171411 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
     /* 171416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171418 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171421 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171427 */     GIR_RootConstrainSelectedInstOperands,
     /* 171428 */     // GIR_Coverage, 8017,
     /* 171428 */     GIR_EraseRootFromParent_Done,
     /* 171429 */   // Label 3039: @171429
     /* 171429 */   GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(171503), // Rule ID 8018 //
     /* 171434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171437 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 171444 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 171447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171451 */     // MIs[0] Rn
     /* 171451 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171455 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171463 */     // (atomic_load_and:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_and_i8>><<P:Predicate_atomic_load_and_i8_seq_cst>>  =>  (LDCLRALB:{ *:[i32] } (ORNWrr:{ *:[i32] } WZR:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171463 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 171466 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNWrr),
     /* 171470 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171475 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171481 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171485 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALB),
     /* 171490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171492 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171495 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171497 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171501 */     GIR_RootConstrainSelectedInstOperands,
     /* 171502 */     // GIR_Coverage, 8018,
     /* 171502 */     GIR_EraseRootFromParent_Done,
     /* 171503 */   // Label 3040: @171503
     /* 171503 */   GIM_Reject,
     /* 171504 */ // Label 3025: @171504
     /* 171504 */ GIM_Reject,
     /* 171505 */ // Label 3023: @171505
     /* 171505 */ GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(171856),
     /* 171510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 171513 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 171520 */   GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(171587), // Rule ID 7999 //
     /* 171525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171528 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 171531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171535 */     // MIs[0] Rn
     /* 171535 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171539 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171547 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_monotonic>>  =>  (LDCLRX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171547 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 171550 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 171554 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171559 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171565 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171569 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRX),
     /* 171574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171576 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171579 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171581 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171585 */     GIR_RootConstrainSelectedInstOperands,
     /* 171586 */     // GIR_Coverage, 7999,
     /* 171586 */     GIR_EraseRootFromParent_Done,
     /* 171587 */   // Label 3042: @171587
     /* 171587 */   GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(171654), // Rule ID 8000 //
     /* 171592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171595 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 171598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171602 */     // MIs[0] Rn
     /* 171602 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171606 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171614 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acquire>>  =>  (LDCLRAX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171614 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 171617 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 171621 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171626 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171632 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171636 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRAX),
     /* 171641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171643 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171646 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171648 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171652 */     GIR_RootConstrainSelectedInstOperands,
     /* 171653 */     // GIR_Coverage, 8000,
     /* 171653 */     GIR_EraseRootFromParent_Done,
     /* 171654 */   // Label 3043: @171654
     /* 171654 */   GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(171721), // Rule ID 8001 //
     /* 171659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171662 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 171665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171669 */     // MIs[0] Rn
     /* 171669 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171673 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171677 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171681 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_release>>  =>  (LDCLRLX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171681 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 171684 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 171688 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171693 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171699 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171703 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRLX),
     /* 171708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171710 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171713 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171719 */     GIR_RootConstrainSelectedInstOperands,
     /* 171720 */     // GIR_Coverage, 8001,
     /* 171720 */     GIR_EraseRootFromParent_Done,
     /* 171721 */   // Label 3044: @171721
     /* 171721 */   GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(171788), // Rule ID 8002 //
     /* 171726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171729 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 171732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171736 */     // MIs[0] Rn
     /* 171736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171748 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_acq_rel>>  =>  (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171748 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 171751 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 171755 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171760 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171766 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171770 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
     /* 171775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171777 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171780 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171782 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171786 */     GIR_RootConstrainSelectedInstOperands,
     /* 171787 */     // GIR_Coverage, 8002,
     /* 171787 */     GIR_EraseRootFromParent_Done,
     /* 171788 */   // Label 3045: @171788
     /* 171788 */   GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(171855), // Rule ID 8003 //
     /* 171793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171796 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 171799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171803 */     // MIs[0] Rn
     /* 171803 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171807 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171811 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 171815 */     // (atomic_load_and:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_and_i64>><<P:Predicate_atomic_load_and_i64_seq_cst>>  =>  (LDCLRALX:{ *:[i64] } (ORNXrr:{ *:[i64] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64sp:{ *:[i64] }:$Rn)
     /* 171815 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 171818 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ORNXrr),
     /* 171822 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 171827 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 171833 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 171837 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 171839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDCLRALX),
     /* 171842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171844 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 171847 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171853 */     GIR_RootConstrainSelectedInstOperands,
     /* 171854 */     // GIR_Coverage, 8003,
     /* 171854 */     GIR_EraseRootFromParent_Done,
     /* 171855 */   // Label 3046: @171855
     /* 171855 */   GIM_Reject,
     /* 171856 */ // Label 3041: @171856
     /* 171856 */ GIM_Reject,
     /* 171857 */ // Label 3024: @171857
     /* 171857 */ GIM_Reject,
     /* 171858 */ // Label 31: @171858
     /* 171858 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3049*/ GIMT_Encode4(172849),
     /* 171869 */ /*GILLT_s32*//*Label 3047*/ GIMT_Encode4(171877),
     /* 171873 */ /*GILLT_s64*//*Label 3048*/ GIMT_Encode4(172622),
     /* 171877 */ // Label 3047: @171877
     /* 171877 */ GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(172621),
     /* 171882 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 171885 */   GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(171934), // Rule ID 7809 //
     /* 171890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171893 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 171900 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 171903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171907 */     // MIs[0] Rn
     /* 171907 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171911 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171919 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_monotonic>>  =>  (LDSETW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 171919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETW),
     /* 171922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171924 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 171926 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171928 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171932 */     GIR_RootConstrainSelectedInstOperands,
     /* 171933 */     // GIR_Coverage, 7809,
     /* 171933 */     GIR_EraseRootFromParent_Done,
     /* 171934 */   // Label 3051: @171934
     /* 171934 */   GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(171983), // Rule ID 7810 //
     /* 171939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171942 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 171949 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 171952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171956 */     // MIs[0] Rn
     /* 171956 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 171960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 171964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 171968 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acquire>>  =>  (LDSETAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 171968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAW),
     /* 171971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 171973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 171975 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 171977 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 171981 */     GIR_RootConstrainSelectedInstOperands,
     /* 171982 */     // GIR_Coverage, 7810,
     /* 171982 */     GIR_EraseRootFromParent_Done,
     /* 171983 */   // Label 3052: @171983
     /* 171983 */   GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(172032), // Rule ID 7811 //
     /* 171988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 171991 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 171998 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 172001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172005 */     // MIs[0] Rn
     /* 172005 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172009 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172017 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_release>>  =>  (LDSETLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLW),
     /* 172020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172024 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172026 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172030 */     GIR_RootConstrainSelectedInstOperands,
     /* 172031 */     // GIR_Coverage, 7811,
     /* 172031 */     GIR_EraseRootFromParent_Done,
     /* 172032 */   // Label 3053: @172032
     /* 172032 */   GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(172081), // Rule ID 7812 //
     /* 172037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172040 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 172047 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 172050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172054 */     // MIs[0] Rn
     /* 172054 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172058 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172062 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172066 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_acq_rel>>  =>  (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
     /* 172069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172073 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172075 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172079 */     GIR_RootConstrainSelectedInstOperands,
     /* 172080 */     // GIR_Coverage, 7812,
     /* 172080 */     GIR_EraseRootFromParent_Done,
     /* 172081 */   // Label 3054: @172081
     /* 172081 */   GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(172130), // Rule ID 7813 //
     /* 172086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172089 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 172096 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 172099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172103 */     // MIs[0] Rn
     /* 172103 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172107 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172115 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i32>><<P:Predicate_atomic_load_or_i32_seq_cst>>  =>  (LDSETALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALW),
     /* 172118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172120 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172122 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172128 */     GIR_RootConstrainSelectedInstOperands,
     /* 172129 */     // GIR_Coverage, 7813,
     /* 172129 */     GIR_EraseRootFromParent_Done,
     /* 172130 */   // Label 3055: @172130
     /* 172130 */   GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(172179), // Rule ID 7814 //
     /* 172135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172138 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 172145 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 172148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172152 */     // MIs[0] Rn
     /* 172152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172156 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172160 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172164 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_monotonic>>  =>  (LDSETH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETH),
     /* 172167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172171 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172173 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172177 */     GIR_RootConstrainSelectedInstOperands,
     /* 172178 */     // GIR_Coverage, 7814,
     /* 172178 */     GIR_EraseRootFromParent_Done,
     /* 172179 */   // Label 3056: @172179
     /* 172179 */   GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(172228), // Rule ID 7815 //
     /* 172184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172187 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 172194 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 172197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172201 */     // MIs[0] Rn
     /* 172201 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172205 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172213 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acquire>>  =>  (LDSETAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAH),
     /* 172216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172218 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172220 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172222 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172226 */     GIR_RootConstrainSelectedInstOperands,
     /* 172227 */     // GIR_Coverage, 7815,
     /* 172227 */     GIR_EraseRootFromParent_Done,
     /* 172228 */   // Label 3057: @172228
     /* 172228 */   GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(172277), // Rule ID 7816 //
     /* 172233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172236 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 172243 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 172246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172250 */     // MIs[0] Rn
     /* 172250 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172254 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172262 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_release>>  =>  (LDSETLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLH),
     /* 172265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172269 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172271 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172275 */     GIR_RootConstrainSelectedInstOperands,
     /* 172276 */     // GIR_Coverage, 7816,
     /* 172276 */     GIR_EraseRootFromParent_Done,
     /* 172277 */   // Label 3058: @172277
     /* 172277 */   GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(172326), // Rule ID 7817 //
     /* 172282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172285 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 172292 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 172295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172299 */     // MIs[0] Rn
     /* 172299 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172303 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172307 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172311 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_acq_rel>>  =>  (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
     /* 172314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172316 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172318 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172320 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172324 */     GIR_RootConstrainSelectedInstOperands,
     /* 172325 */     // GIR_Coverage, 7817,
     /* 172325 */     GIR_EraseRootFromParent_Done,
     /* 172326 */   // Label 3059: @172326
     /* 172326 */   GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(172375), // Rule ID 7818 //
     /* 172331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172334 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 172341 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 172344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172348 */     // MIs[0] Rn
     /* 172348 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172352 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172356 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172360 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i16>><<P:Predicate_atomic_load_or_i16_seq_cst>>  =>  (LDSETALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALH),
     /* 172363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172365 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172367 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172369 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172373 */     GIR_RootConstrainSelectedInstOperands,
     /* 172374 */     // GIR_Coverage, 7818,
     /* 172374 */     GIR_EraseRootFromParent_Done,
     /* 172375 */   // Label 3060: @172375
     /* 172375 */   GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(172424), // Rule ID 7819 //
     /* 172380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172383 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 172390 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 172393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172397 */     // MIs[0] Rn
     /* 172397 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172409 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_monotonic>>  =>  (LDSETB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETB),
     /* 172412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172416 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172418 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172422 */     GIR_RootConstrainSelectedInstOperands,
     /* 172423 */     // GIR_Coverage, 7819,
     /* 172423 */     GIR_EraseRootFromParent_Done,
     /* 172424 */   // Label 3061: @172424
     /* 172424 */   GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(172473), // Rule ID 7820 //
     /* 172429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172432 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 172439 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 172442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172446 */     // MIs[0] Rn
     /* 172446 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172450 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172458 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acquire>>  =>  (LDSETAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAB),
     /* 172461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172465 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172471 */     GIR_RootConstrainSelectedInstOperands,
     /* 172472 */     // GIR_Coverage, 7820,
     /* 172472 */     GIR_EraseRootFromParent_Done,
     /* 172473 */   // Label 3062: @172473
     /* 172473 */   GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(172522), // Rule ID 7821 //
     /* 172478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172481 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 172488 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 172491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172495 */     // MIs[0] Rn
     /* 172495 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172499 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172507 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_release>>  =>  (LDSETLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLB),
     /* 172510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172514 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172516 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172520 */     GIR_RootConstrainSelectedInstOperands,
     /* 172521 */     // GIR_Coverage, 7821,
     /* 172521 */     GIR_EraseRootFromParent_Done,
     /* 172522 */   // Label 3063: @172522
     /* 172522 */   GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(172571), // Rule ID 7822 //
     /* 172527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172530 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 172537 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 172540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172544 */     // MIs[0] Rn
     /* 172544 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172548 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172552 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172556 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_acq_rel>>  =>  (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
     /* 172559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172563 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172565 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172569 */     GIR_RootConstrainSelectedInstOperands,
     /* 172570 */     // GIR_Coverage, 7822,
     /* 172570 */     GIR_EraseRootFromParent_Done,
     /* 172571 */   // Label 3064: @172571
     /* 172571 */   GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(172620), // Rule ID 7823 //
     /* 172576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172579 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 172586 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 172589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172593 */     // MIs[0] Rn
     /* 172593 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172597 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172601 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172605 */     // (atomic_load_or:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_or_i8>><<P:Predicate_atomic_load_or_i8_seq_cst>>  =>  (LDSETALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALB),
     /* 172608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172610 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172612 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172614 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172618 */     GIR_RootConstrainSelectedInstOperands,
     /* 172619 */     // GIR_Coverage, 7823,
     /* 172619 */     GIR_EraseRootFromParent_Done,
     /* 172620 */   // Label 3065: @172620
     /* 172620 */   GIM_Reject,
     /* 172621 */ // Label 3050: @172621
     /* 172621 */ GIM_Reject,
     /* 172622 */ // Label 3048: @172622
     /* 172622 */ GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(172848),
     /* 172627 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 172630 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 172637 */   GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(172679), // Rule ID 7804 //
     /* 172642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172645 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 172648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172652 */     // MIs[0] Rn
     /* 172652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172656 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172664 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_monotonic>>  =>  (LDSETX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETX),
     /* 172667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172669 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172671 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172677 */     GIR_RootConstrainSelectedInstOperands,
     /* 172678 */     // GIR_Coverage, 7804,
     /* 172678 */     GIR_EraseRootFromParent_Done,
     /* 172679 */   // Label 3067: @172679
     /* 172679 */   GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(172721), // Rule ID 7805 //
     /* 172684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172687 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 172690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172694 */     // MIs[0] Rn
     /* 172694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172698 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172706 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acquire>>  =>  (LDSETAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETAX),
     /* 172709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172713 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172719 */     GIR_RootConstrainSelectedInstOperands,
     /* 172720 */     // GIR_Coverage, 7805,
     /* 172720 */     GIR_EraseRootFromParent_Done,
     /* 172721 */   // Label 3068: @172721
     /* 172721 */   GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(172763), // Rule ID 7806 //
     /* 172726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172729 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 172732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172736 */     // MIs[0] Rn
     /* 172736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172748 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_release>>  =>  (LDSETLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETLX),
     /* 172751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172755 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172761 */     GIR_RootConstrainSelectedInstOperands,
     /* 172762 */     // GIR_Coverage, 7806,
     /* 172762 */     GIR_EraseRootFromParent_Done,
     /* 172763 */   // Label 3069: @172763
     /* 172763 */   GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(172805), // Rule ID 7807 //
     /* 172768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172771 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 172774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172778 */     // MIs[0] Rn
     /* 172778 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172782 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172786 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172790 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_acq_rel>>  =>  (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
     /* 172793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172797 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172799 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172803 */     GIR_RootConstrainSelectedInstOperands,
     /* 172804 */     // GIR_Coverage, 7807,
     /* 172804 */     GIR_EraseRootFromParent_Done,
     /* 172805 */   // Label 3070: @172805
     /* 172805 */   GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(172847), // Rule ID 7808 //
     /* 172810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172813 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 172816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172820 */     // MIs[0] Rn
     /* 172820 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172824 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 172832 */     // (atomic_load_or:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_or_i64>><<P:Predicate_atomic_load_or_i64_seq_cst>>  =>  (LDSETALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSETALX),
     /* 172835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172839 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172841 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172845 */     GIR_RootConstrainSelectedInstOperands,
     /* 172846 */     // GIR_Coverage, 7808,
     /* 172846 */     GIR_EraseRootFromParent_Done,
     /* 172847 */   // Label 3071: @172847
     /* 172847 */   GIM_Reject,
     /* 172848 */ // Label 3066: @172848
     /* 172848 */ GIM_Reject,
     /* 172849 */ // Label 3049: @172849
     /* 172849 */ GIM_Reject,
     /* 172850 */ // Label 32: @172850
     /* 172850 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3074*/ GIMT_Encode4(173841),
     /* 172861 */ /*GILLT_s32*//*Label 3072*/ GIMT_Encode4(172869),
     /* 172865 */ /*GILLT_s64*//*Label 3073*/ GIMT_Encode4(173614),
     /* 172869 */ // Label 3072: @172869
     /* 172869 */ GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(173613),
     /* 172874 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 172877 */   GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(172926), // Rule ID 7829 //
     /* 172882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172885 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 172892 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 172895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172899 */     // MIs[0] Rn
     /* 172899 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172903 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172907 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172911 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_monotonic>>  =>  (LDEORW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORW),
     /* 172914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172916 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172918 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172920 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172924 */     GIR_RootConstrainSelectedInstOperands,
     /* 172925 */     // GIR_Coverage, 7829,
     /* 172925 */     GIR_EraseRootFromParent_Done,
     /* 172926 */   // Label 3076: @172926
     /* 172926 */   GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(172975), // Rule ID 7830 //
     /* 172931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172934 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 172941 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 172944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172948 */     // MIs[0] Rn
     /* 172948 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 172952 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 172956 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172960 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acquire>>  =>  (LDEORAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 172960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAW),
     /* 172963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 172965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 172967 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 172969 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 172973 */     GIR_RootConstrainSelectedInstOperands,
     /* 172974 */     // GIR_Coverage, 7830,
     /* 172974 */     GIR_EraseRootFromParent_Done,
     /* 172975 */   // Label 3077: @172975
     /* 172975 */   GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(173024), // Rule ID 7831 //
     /* 172980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 172983 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 172990 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 172993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 172997 */     // MIs[0] Rn
     /* 172997 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173001 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173009 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_release>>  =>  (LDEORLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLW),
     /* 173012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173016 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173018 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173022 */     GIR_RootConstrainSelectedInstOperands,
     /* 173023 */     // GIR_Coverage, 7831,
     /* 173023 */     GIR_EraseRootFromParent_Done,
     /* 173024 */   // Label 3078: @173024
     /* 173024 */   GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(173073), // Rule ID 7832 //
     /* 173029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173032 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 173039 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 173042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173046 */     // MIs[0] Rn
     /* 173046 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173050 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173054 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173058 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_acq_rel>>  =>  (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
     /* 173061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173063 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173065 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173067 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173071 */     GIR_RootConstrainSelectedInstOperands,
     /* 173072 */     // GIR_Coverage, 7832,
     /* 173072 */     GIR_EraseRootFromParent_Done,
     /* 173073 */   // Label 3079: @173073
     /* 173073 */   GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(173122), // Rule ID 7833 //
     /* 173078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173081 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 173088 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 173091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173095 */     // MIs[0] Rn
     /* 173095 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173099 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173103 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173107 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i32>><<P:Predicate_atomic_load_xor_i32_seq_cst>>  =>  (LDEORALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALW),
     /* 173110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173112 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173114 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173116 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173120 */     GIR_RootConstrainSelectedInstOperands,
     /* 173121 */     // GIR_Coverage, 7833,
     /* 173121 */     GIR_EraseRootFromParent_Done,
     /* 173122 */   // Label 3080: @173122
     /* 173122 */   GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(173171), // Rule ID 7834 //
     /* 173127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173130 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 173137 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 173140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173144 */     // MIs[0] Rn
     /* 173144 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173148 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173156 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_monotonic>>  =>  (LDEORH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORH),
     /* 173159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173163 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173165 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173169 */     GIR_RootConstrainSelectedInstOperands,
     /* 173170 */     // GIR_Coverage, 7834,
     /* 173170 */     GIR_EraseRootFromParent_Done,
     /* 173171 */   // Label 3081: @173171
     /* 173171 */   GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(173220), // Rule ID 7835 //
     /* 173176 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173179 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 173186 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 173189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173193 */     // MIs[0] Rn
     /* 173193 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173197 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173201 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173205 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acquire>>  =>  (LDEORAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAH),
     /* 173208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173210 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173212 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173214 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173218 */     GIR_RootConstrainSelectedInstOperands,
     /* 173219 */     // GIR_Coverage, 7835,
     /* 173219 */     GIR_EraseRootFromParent_Done,
     /* 173220 */   // Label 3082: @173220
     /* 173220 */   GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(173269), // Rule ID 7836 //
     /* 173225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173228 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 173235 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 173238 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173242 */     // MIs[0] Rn
     /* 173242 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173246 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173254 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_release>>  =>  (LDEORLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLH),
     /* 173257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173261 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173263 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173267 */     GIR_RootConstrainSelectedInstOperands,
     /* 173268 */     // GIR_Coverage, 7836,
     /* 173268 */     GIR_EraseRootFromParent_Done,
     /* 173269 */   // Label 3083: @173269
     /* 173269 */   GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(173318), // Rule ID 7837 //
     /* 173274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173277 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 173284 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 173287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173291 */     // MIs[0] Rn
     /* 173291 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173295 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173303 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_acq_rel>>  =>  (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
     /* 173306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173310 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173312 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173316 */     GIR_RootConstrainSelectedInstOperands,
     /* 173317 */     // GIR_Coverage, 7837,
     /* 173317 */     GIR_EraseRootFromParent_Done,
     /* 173318 */   // Label 3084: @173318
     /* 173318 */   GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(173367), // Rule ID 7838 //
     /* 173323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173326 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 173333 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 173336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173340 */     // MIs[0] Rn
     /* 173340 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173344 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173352 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i16>><<P:Predicate_atomic_load_xor_i16_seq_cst>>  =>  (LDEORALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALH),
     /* 173355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173359 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173365 */     GIR_RootConstrainSelectedInstOperands,
     /* 173366 */     // GIR_Coverage, 7838,
     /* 173366 */     GIR_EraseRootFromParent_Done,
     /* 173367 */   // Label 3085: @173367
     /* 173367 */   GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(173416), // Rule ID 7839 //
     /* 173372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173375 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 173382 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 173385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173389 */     // MIs[0] Rn
     /* 173389 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173393 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173397 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173401 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_monotonic>>  =>  (LDEORB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORB),
     /* 173404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173408 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173414 */     GIR_RootConstrainSelectedInstOperands,
     /* 173415 */     // GIR_Coverage, 7839,
     /* 173415 */     GIR_EraseRootFromParent_Done,
     /* 173416 */   // Label 3086: @173416
     /* 173416 */   GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(173465), // Rule ID 7840 //
     /* 173421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173424 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 173431 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 173434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173438 */     // MIs[0] Rn
     /* 173438 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173442 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173446 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173450 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acquire>>  =>  (LDEORAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAB),
     /* 173453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173457 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173459 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173463 */     GIR_RootConstrainSelectedInstOperands,
     /* 173464 */     // GIR_Coverage, 7840,
     /* 173464 */     GIR_EraseRootFromParent_Done,
     /* 173465 */   // Label 3087: @173465
     /* 173465 */   GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(173514), // Rule ID 7841 //
     /* 173470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173473 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 173480 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 173483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173487 */     // MIs[0] Rn
     /* 173487 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173491 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173495 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173499 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_release>>  =>  (LDEORLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLB),
     /* 173502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173506 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173508 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173512 */     GIR_RootConstrainSelectedInstOperands,
     /* 173513 */     // GIR_Coverage, 7841,
     /* 173513 */     GIR_EraseRootFromParent_Done,
     /* 173514 */   // Label 3088: @173514
     /* 173514 */   GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(173563), // Rule ID 7842 //
     /* 173519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173522 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 173529 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 173532 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173536 */     // MIs[0] Rn
     /* 173536 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173540 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173548 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_acq_rel>>  =>  (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
     /* 173551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173553 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173555 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173557 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173561 */     GIR_RootConstrainSelectedInstOperands,
     /* 173562 */     // GIR_Coverage, 7842,
     /* 173562 */     GIR_EraseRootFromParent_Done,
     /* 173563 */   // Label 3089: @173563
     /* 173563 */   GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(173612), // Rule ID 7843 //
     /* 173568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173571 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 173578 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 173581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173585 */     // MIs[0] Rn
     /* 173585 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173589 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173593 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173597 */     // (atomic_load_xor:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_xor_i8>><<P:Predicate_atomic_load_xor_i8_seq_cst>>  =>  (LDEORALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALB),
     /* 173600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173604 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173606 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173610 */     GIR_RootConstrainSelectedInstOperands,
     /* 173611 */     // GIR_Coverage, 7843,
     /* 173611 */     GIR_EraseRootFromParent_Done,
     /* 173612 */   // Label 3090: @173612
     /* 173612 */   GIM_Reject,
     /* 173613 */ // Label 3075: @173613
     /* 173613 */ GIM_Reject,
     /* 173614 */ // Label 3073: @173614
     /* 173614 */ GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(173840),
     /* 173619 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 173622 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 173629 */   GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(173671), // Rule ID 7824 //
     /* 173634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173637 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 173640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173644 */     // MIs[0] Rn
     /* 173644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173652 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173656 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_monotonic>>  =>  (LDEORX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORX),
     /* 173659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173663 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173665 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173669 */     GIR_RootConstrainSelectedInstOperands,
     /* 173670 */     // GIR_Coverage, 7824,
     /* 173670 */     GIR_EraseRootFromParent_Done,
     /* 173671 */   // Label 3092: @173671
     /* 173671 */   GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(173713), // Rule ID 7825 //
     /* 173676 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173679 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 173682 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173686 */     // MIs[0] Rn
     /* 173686 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173690 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173698 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acquire>>  =>  (LDEORAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORAX),
     /* 173701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173703 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173705 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173707 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173711 */     GIR_RootConstrainSelectedInstOperands,
     /* 173712 */     // GIR_Coverage, 7825,
     /* 173712 */     GIR_EraseRootFromParent_Done,
     /* 173713 */   // Label 3093: @173713
     /* 173713 */   GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(173755), // Rule ID 7826 //
     /* 173718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173721 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 173724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173728 */     // MIs[0] Rn
     /* 173728 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173732 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173740 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_release>>  =>  (LDEORLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORLX),
     /* 173743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173747 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173749 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173753 */     GIR_RootConstrainSelectedInstOperands,
     /* 173754 */     // GIR_Coverage, 7826,
     /* 173754 */     GIR_EraseRootFromParent_Done,
     /* 173755 */   // Label 3094: @173755
     /* 173755 */   GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(173797), // Rule ID 7827 //
     /* 173760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173763 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 173766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173770 */     // MIs[0] Rn
     /* 173770 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173774 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173778 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173782 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_acq_rel>>  =>  (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
     /* 173785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173789 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173791 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173795 */     GIR_RootConstrainSelectedInstOperands,
     /* 173796 */     // GIR_Coverage, 7827,
     /* 173796 */     GIR_EraseRootFromParent_Done,
     /* 173797 */   // Label 3095: @173797
     /* 173797 */   GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(173839), // Rule ID 7828 //
     /* 173802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173805 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 173808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173812 */     // MIs[0] Rn
     /* 173812 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173816 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 173824 */     // (atomic_load_xor:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_xor_i64>><<P:Predicate_atomic_load_xor_i64_seq_cst>>  =>  (LDEORALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDEORALX),
     /* 173827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173831 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173833 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173837 */     GIR_RootConstrainSelectedInstOperands,
     /* 173838 */     // GIR_Coverage, 7828,
     /* 173838 */     GIR_EraseRootFromParent_Done,
     /* 173839 */   // Label 3096: @173839
     /* 173839 */   GIM_Reject,
     /* 173840 */ // Label 3091: @173840
     /* 173840 */ GIM_Reject,
     /* 173841 */ // Label 3074: @173841
     /* 173841 */ GIM_Reject,
     /* 173842 */ // Label 33: @173842
     /* 173842 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3099*/ GIMT_Encode4(174833),
     /* 173853 */ /*GILLT_s32*//*Label 3097*/ GIMT_Encode4(173861),
     /* 173857 */ /*GILLT_s64*//*Label 3098*/ GIMT_Encode4(174606),
     /* 173861 */ // Label 3097: @173861
     /* 173861 */ GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(174605),
     /* 173866 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 173869 */   GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(173918), // Rule ID 7869 //
     /* 173874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173877 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 173884 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 173887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173891 */     // MIs[0] Rn
     /* 173891 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173895 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173903 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_monotonic>>  =>  (LDSMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXW),
     /* 173906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173908 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173910 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173912 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173916 */     GIR_RootConstrainSelectedInstOperands,
     /* 173917 */     // GIR_Coverage, 7869,
     /* 173917 */     GIR_EraseRootFromParent_Done,
     /* 173918 */   // Label 3101: @173918
     /* 173918 */   GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(173967), // Rule ID 7870 //
     /* 173923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173926 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 173933 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 173936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173940 */     // MIs[0] Rn
     /* 173940 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173944 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173952 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acquire>>  =>  (LDSMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 173952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAW),
     /* 173955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 173957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 173959 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 173961 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 173965 */     GIR_RootConstrainSelectedInstOperands,
     /* 173966 */     // GIR_Coverage, 7870,
     /* 173966 */     GIR_EraseRootFromParent_Done,
     /* 173967 */   // Label 3102: @173967
     /* 173967 */   GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(174016), // Rule ID 7871 //
     /* 173972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 173975 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 173982 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 173985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 173989 */     // MIs[0] Rn
     /* 173989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 173993 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 173997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174001 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_release>>  =>  (LDSMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLW),
     /* 174004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174014 */     GIR_RootConstrainSelectedInstOperands,
     /* 174015 */     // GIR_Coverage, 7871,
     /* 174015 */     GIR_EraseRootFromParent_Done,
     /* 174016 */   // Label 3103: @174016
     /* 174016 */   GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(174065), // Rule ID 7872 //
     /* 174021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174024 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 174031 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 174034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174038 */     // MIs[0] Rn
     /* 174038 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174046 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174050 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_acq_rel>>  =>  (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
     /* 174053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174055 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174057 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174059 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174063 */     GIR_RootConstrainSelectedInstOperands,
     /* 174064 */     // GIR_Coverage, 7872,
     /* 174064 */     GIR_EraseRootFromParent_Done,
     /* 174065 */   // Label 3104: @174065
     /* 174065 */   GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(174114), // Rule ID 7873 //
     /* 174070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174073 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 174080 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 174083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174087 */     // MIs[0] Rn
     /* 174087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174091 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174099 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i32>><<P:Predicate_atomic_load_max_i32_seq_cst>>  =>  (LDSMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALW),
     /* 174102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174106 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174112 */     GIR_RootConstrainSelectedInstOperands,
     /* 174113 */     // GIR_Coverage, 7873,
     /* 174113 */     GIR_EraseRootFromParent_Done,
     /* 174114 */   // Label 3105: @174114
     /* 174114 */   GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(174163), // Rule ID 7874 //
     /* 174119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174122 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 174129 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 174132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174136 */     // MIs[0] Rn
     /* 174136 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174140 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174148 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_monotonic>>  =>  (LDSMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXH),
     /* 174151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174155 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174157 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174161 */     GIR_RootConstrainSelectedInstOperands,
     /* 174162 */     // GIR_Coverage, 7874,
     /* 174162 */     GIR_EraseRootFromParent_Done,
     /* 174163 */   // Label 3106: @174163
     /* 174163 */   GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(174212), // Rule ID 7875 //
     /* 174168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174171 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 174178 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 174181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174185 */     // MIs[0] Rn
     /* 174185 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174189 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174197 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acquire>>  =>  (LDSMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAH),
     /* 174200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174202 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174204 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174206 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174210 */     GIR_RootConstrainSelectedInstOperands,
     /* 174211 */     // GIR_Coverage, 7875,
     /* 174211 */     GIR_EraseRootFromParent_Done,
     /* 174212 */   // Label 3107: @174212
     /* 174212 */   GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(174261), // Rule ID 7876 //
     /* 174217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174220 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 174227 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 174230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174234 */     // MIs[0] Rn
     /* 174234 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174238 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174242 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174246 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_release>>  =>  (LDSMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLH),
     /* 174249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174251 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174253 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174255 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174259 */     GIR_RootConstrainSelectedInstOperands,
     /* 174260 */     // GIR_Coverage, 7876,
     /* 174260 */     GIR_EraseRootFromParent_Done,
     /* 174261 */   // Label 3108: @174261
     /* 174261 */   GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(174310), // Rule ID 7877 //
     /* 174266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174269 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 174276 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 174279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174283 */     // MIs[0] Rn
     /* 174283 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174287 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174291 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174295 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_acq_rel>>  =>  (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
     /* 174298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174300 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174302 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174308 */     GIR_RootConstrainSelectedInstOperands,
     /* 174309 */     // GIR_Coverage, 7877,
     /* 174309 */     GIR_EraseRootFromParent_Done,
     /* 174310 */   // Label 3109: @174310
     /* 174310 */   GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(174359), // Rule ID 7878 //
     /* 174315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174318 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 174325 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 174328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174332 */     // MIs[0] Rn
     /* 174332 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174336 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174340 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174344 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i16>><<P:Predicate_atomic_load_max_i16_seq_cst>>  =>  (LDSMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALH),
     /* 174347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174351 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174353 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174357 */     GIR_RootConstrainSelectedInstOperands,
     /* 174358 */     // GIR_Coverage, 7878,
     /* 174358 */     GIR_EraseRootFromParent_Done,
     /* 174359 */   // Label 3110: @174359
     /* 174359 */   GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(174408), // Rule ID 7879 //
     /* 174364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174367 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 174374 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 174377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174381 */     // MIs[0] Rn
     /* 174381 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174385 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174389 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174393 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_monotonic>>  =>  (LDSMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXB),
     /* 174396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174400 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174402 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174406 */     GIR_RootConstrainSelectedInstOperands,
     /* 174407 */     // GIR_Coverage, 7879,
     /* 174407 */     GIR_EraseRootFromParent_Done,
     /* 174408 */   // Label 3111: @174408
     /* 174408 */   GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(174457), // Rule ID 7880 //
     /* 174413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174416 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 174423 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 174426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174430 */     // MIs[0] Rn
     /* 174430 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174434 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174438 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174442 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acquire>>  =>  (LDSMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAB),
     /* 174445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174449 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174455 */     GIR_RootConstrainSelectedInstOperands,
     /* 174456 */     // GIR_Coverage, 7880,
     /* 174456 */     GIR_EraseRootFromParent_Done,
     /* 174457 */   // Label 3112: @174457
     /* 174457 */   GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(174506), // Rule ID 7881 //
     /* 174462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174465 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 174472 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 174475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174479 */     // MIs[0] Rn
     /* 174479 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174483 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174487 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174491 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_release>>  =>  (LDSMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLB),
     /* 174494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174498 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174500 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174504 */     GIR_RootConstrainSelectedInstOperands,
     /* 174505 */     // GIR_Coverage, 7881,
     /* 174505 */     GIR_EraseRootFromParent_Done,
     /* 174506 */   // Label 3113: @174506
     /* 174506 */   GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(174555), // Rule ID 7882 //
     /* 174511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174514 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 174521 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 174524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174528 */     // MIs[0] Rn
     /* 174528 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174532 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174540 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_acq_rel>>  =>  (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
     /* 174543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174547 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174553 */     GIR_RootConstrainSelectedInstOperands,
     /* 174554 */     // GIR_Coverage, 7882,
     /* 174554 */     GIR_EraseRootFromParent_Done,
     /* 174555 */   // Label 3114: @174555
     /* 174555 */   GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(174604), // Rule ID 7883 //
     /* 174560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174563 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 174570 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 174573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174577 */     // MIs[0] Rn
     /* 174577 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174581 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174585 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174589 */     // (atomic_load_max:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_max_i8>><<P:Predicate_atomic_load_max_i8_seq_cst>>  =>  (LDSMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALB),
     /* 174592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174594 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174596 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174598 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174602 */     GIR_RootConstrainSelectedInstOperands,
     /* 174603 */     // GIR_Coverage, 7883,
     /* 174603 */     GIR_EraseRootFromParent_Done,
     /* 174604 */   // Label 3115: @174604
     /* 174604 */   GIM_Reject,
     /* 174605 */ // Label 3100: @174605
     /* 174605 */ GIM_Reject,
     /* 174606 */ // Label 3098: @174606
     /* 174606 */ GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(174832),
     /* 174611 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 174614 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 174621 */   GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(174663), // Rule ID 7864 //
     /* 174626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174629 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 174632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174636 */     // MIs[0] Rn
     /* 174636 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174640 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174648 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_monotonic>>  =>  (LDSMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXX),
     /* 174651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174655 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174657 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174661 */     GIR_RootConstrainSelectedInstOperands,
     /* 174662 */     // GIR_Coverage, 7864,
     /* 174662 */     GIR_EraseRootFromParent_Done,
     /* 174663 */   // Label 3117: @174663
     /* 174663 */   GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(174705), // Rule ID 7865 //
     /* 174668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174671 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 174674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174678 */     // MIs[0] Rn
     /* 174678 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174682 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174686 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174690 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acquire>>  =>  (LDSMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXAX),
     /* 174693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174697 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174699 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174703 */     GIR_RootConstrainSelectedInstOperands,
     /* 174704 */     // GIR_Coverage, 7865,
     /* 174704 */     GIR_EraseRootFromParent_Done,
     /* 174705 */   // Label 3118: @174705
     /* 174705 */   GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(174747), // Rule ID 7866 //
     /* 174710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174713 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 174716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174720 */     // MIs[0] Rn
     /* 174720 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174724 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174732 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_release>>  =>  (LDSMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXLX),
     /* 174735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174739 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174741 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174745 */     GIR_RootConstrainSelectedInstOperands,
     /* 174746 */     // GIR_Coverage, 7866,
     /* 174746 */     GIR_EraseRootFromParent_Done,
     /* 174747 */   // Label 3119: @174747
     /* 174747 */   GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(174789), // Rule ID 7867 //
     /* 174752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174755 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 174758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174762 */     // MIs[0] Rn
     /* 174762 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174766 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174774 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_acq_rel>>  =>  (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
     /* 174777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174779 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174781 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174787 */     GIR_RootConstrainSelectedInstOperands,
     /* 174788 */     // GIR_Coverage, 7867,
     /* 174788 */     GIR_EraseRootFromParent_Done,
     /* 174789 */   // Label 3120: @174789
     /* 174789 */   GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(174831), // Rule ID 7868 //
     /* 174794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174797 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 174800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174804 */     // MIs[0] Rn
     /* 174804 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174808 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174812 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 174816 */     // (atomic_load_max:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_max_i64>><<P:Predicate_atomic_load_max_i64_seq_cst>>  =>  (LDSMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMAXALX),
     /* 174819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174823 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174825 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174829 */     GIR_RootConstrainSelectedInstOperands,
     /* 174830 */     // GIR_Coverage, 7868,
     /* 174830 */     GIR_EraseRootFromParent_Done,
     /* 174831 */   // Label 3121: @174831
     /* 174831 */   GIM_Reject,
     /* 174832 */ // Label 3116: @174832
     /* 174832 */ GIM_Reject,
     /* 174833 */ // Label 3099: @174833
     /* 174833 */ GIM_Reject,
     /* 174834 */ // Label 34: @174834
     /* 174834 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3124*/ GIMT_Encode4(175825),
     /* 174845 */ /*GILLT_s32*//*Label 3122*/ GIMT_Encode4(174853),
     /* 174849 */ /*GILLT_s64*//*Label 3123*/ GIMT_Encode4(175598),
     /* 174853 */ // Label 3122: @174853
     /* 174853 */ GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(175597),
     /* 174858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 174861 */   GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(174910), // Rule ID 7889 //
     /* 174866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174869 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 174876 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 174879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174883 */     // MIs[0] Rn
     /* 174883 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174887 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174891 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174895 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_monotonic>>  =>  (LDSMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINW),
     /* 174898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174902 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174908 */     GIR_RootConstrainSelectedInstOperands,
     /* 174909 */     // GIR_Coverage, 7889,
     /* 174909 */     GIR_EraseRootFromParent_Done,
     /* 174910 */   // Label 3126: @174910
     /* 174910 */   GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(174959), // Rule ID 7890 //
     /* 174915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174918 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 174925 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 174928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174932 */     // MIs[0] Rn
     /* 174932 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174936 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174944 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acquire>>  =>  (LDSMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAW),
     /* 174947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 174951 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 174953 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 174957 */     GIR_RootConstrainSelectedInstOperands,
     /* 174958 */     // GIR_Coverage, 7890,
     /* 174958 */     GIR_EraseRootFromParent_Done,
     /* 174959 */   // Label 3127: @174959
     /* 174959 */   GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(175008), // Rule ID 7891 //
     /* 174964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 174967 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 174974 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 174977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174981 */     // MIs[0] Rn
     /* 174981 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 174985 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 174989 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 174993 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_release>>  =>  (LDSMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 174993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLW),
     /* 174996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 174998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175000 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175002 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175006 */     GIR_RootConstrainSelectedInstOperands,
     /* 175007 */     // GIR_Coverage, 7891,
     /* 175007 */     GIR_EraseRootFromParent_Done,
     /* 175008 */   // Label 3128: @175008
     /* 175008 */   GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(175057), // Rule ID 7892 //
     /* 175013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175016 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 175023 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 175026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175030 */     // MIs[0] Rn
     /* 175030 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175034 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175042 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_acq_rel>>  =>  (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
     /* 175045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175047 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175049 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175051 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175055 */     GIR_RootConstrainSelectedInstOperands,
     /* 175056 */     // GIR_Coverage, 7892,
     /* 175056 */     GIR_EraseRootFromParent_Done,
     /* 175057 */   // Label 3129: @175057
     /* 175057 */   GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(175106), // Rule ID 7893 //
     /* 175062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175065 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 175072 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 175075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175079 */     // MIs[0] Rn
     /* 175079 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175083 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175087 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175091 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i32>><<P:Predicate_atomic_load_min_i32_seq_cst>>  =>  (LDSMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALW),
     /* 175094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175098 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175104 */     GIR_RootConstrainSelectedInstOperands,
     /* 175105 */     // GIR_Coverage, 7893,
     /* 175105 */     GIR_EraseRootFromParent_Done,
     /* 175106 */   // Label 3130: @175106
     /* 175106 */   GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(175155), // Rule ID 7894 //
     /* 175111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175114 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 175121 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 175124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175128 */     // MIs[0] Rn
     /* 175128 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175132 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175136 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175140 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_monotonic>>  =>  (LDSMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175140 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINH),
     /* 175143 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175145 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175147 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175153 */     GIR_RootConstrainSelectedInstOperands,
     /* 175154 */     // GIR_Coverage, 7894,
     /* 175154 */     GIR_EraseRootFromParent_Done,
     /* 175155 */   // Label 3131: @175155
     /* 175155 */   GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(175204), // Rule ID 7895 //
     /* 175160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175163 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 175170 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 175173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175177 */     // MIs[0] Rn
     /* 175177 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175189 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acquire>>  =>  (LDSMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAH),
     /* 175192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175196 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175202 */     GIR_RootConstrainSelectedInstOperands,
     /* 175203 */     // GIR_Coverage, 7895,
     /* 175203 */     GIR_EraseRootFromParent_Done,
     /* 175204 */   // Label 3132: @175204
     /* 175204 */   GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(175253), // Rule ID 7896 //
     /* 175209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175212 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 175219 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 175222 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175226 */     // MIs[0] Rn
     /* 175226 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175230 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175234 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175238 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_release>>  =>  (LDSMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLH),
     /* 175241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175245 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175251 */     GIR_RootConstrainSelectedInstOperands,
     /* 175252 */     // GIR_Coverage, 7896,
     /* 175252 */     GIR_EraseRootFromParent_Done,
     /* 175253 */   // Label 3133: @175253
     /* 175253 */   GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(175302), // Rule ID 7897 //
     /* 175258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175261 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 175268 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 175271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175275 */     // MIs[0] Rn
     /* 175275 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175279 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175283 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175287 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_acq_rel>>  =>  (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
     /* 175290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175294 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175296 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175300 */     GIR_RootConstrainSelectedInstOperands,
     /* 175301 */     // GIR_Coverage, 7897,
     /* 175301 */     GIR_EraseRootFromParent_Done,
     /* 175302 */   // Label 3134: @175302
     /* 175302 */   GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(175351), // Rule ID 7898 //
     /* 175307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175310 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 175317 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 175320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175324 */     // MIs[0] Rn
     /* 175324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175328 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175336 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i16>><<P:Predicate_atomic_load_min_i16_seq_cst>>  =>  (LDSMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALH),
     /* 175339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175343 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175345 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175349 */     GIR_RootConstrainSelectedInstOperands,
     /* 175350 */     // GIR_Coverage, 7898,
     /* 175350 */     GIR_EraseRootFromParent_Done,
     /* 175351 */   // Label 3135: @175351
     /* 175351 */   GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(175400), // Rule ID 7899 //
     /* 175356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175359 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 175366 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 175369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175373 */     // MIs[0] Rn
     /* 175373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175377 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175381 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175385 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_monotonic>>  =>  (LDSMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINB),
     /* 175388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175392 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175398 */     GIR_RootConstrainSelectedInstOperands,
     /* 175399 */     // GIR_Coverage, 7899,
     /* 175399 */     GIR_EraseRootFromParent_Done,
     /* 175400 */   // Label 3136: @175400
     /* 175400 */   GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(175449), // Rule ID 7900 //
     /* 175405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175408 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 175415 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 175418 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175422 */     // MIs[0] Rn
     /* 175422 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175426 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175434 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acquire>>  =>  (LDSMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAB),
     /* 175437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175441 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175443 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175447 */     GIR_RootConstrainSelectedInstOperands,
     /* 175448 */     // GIR_Coverage, 7900,
     /* 175448 */     GIR_EraseRootFromParent_Done,
     /* 175449 */   // Label 3137: @175449
     /* 175449 */   GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(175498), // Rule ID 7901 //
     /* 175454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175457 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 175464 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 175467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175471 */     // MIs[0] Rn
     /* 175471 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175475 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175483 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_release>>  =>  (LDSMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLB),
     /* 175486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175490 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175492 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175496 */     GIR_RootConstrainSelectedInstOperands,
     /* 175497 */     // GIR_Coverage, 7901,
     /* 175497 */     GIR_EraseRootFromParent_Done,
     /* 175498 */   // Label 3138: @175498
     /* 175498 */   GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(175547), // Rule ID 7902 //
     /* 175503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175506 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 175513 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 175516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175520 */     // MIs[0] Rn
     /* 175520 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175524 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175528 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175532 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_acq_rel>>  =>  (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
     /* 175535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175539 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175541 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175545 */     GIR_RootConstrainSelectedInstOperands,
     /* 175546 */     // GIR_Coverage, 7902,
     /* 175546 */     GIR_EraseRootFromParent_Done,
     /* 175547 */   // Label 3139: @175547
     /* 175547 */   GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(175596), // Rule ID 7903 //
     /* 175552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175555 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 175562 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 175565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175569 */     // MIs[0] Rn
     /* 175569 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175573 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175581 */     // (atomic_load_min:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_min_i8>><<P:Predicate_atomic_load_min_i8_seq_cst>>  =>  (LDSMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALB),
     /* 175584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175586 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175588 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175590 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175594 */     GIR_RootConstrainSelectedInstOperands,
     /* 175595 */     // GIR_Coverage, 7903,
     /* 175595 */     GIR_EraseRootFromParent_Done,
     /* 175596 */   // Label 3140: @175596
     /* 175596 */   GIM_Reject,
     /* 175597 */ // Label 3125: @175597
     /* 175597 */ GIM_Reject,
     /* 175598 */ // Label 3123: @175598
     /* 175598 */ GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(175824),
     /* 175603 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 175606 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 175613 */   GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(175655), // Rule ID 7884 //
     /* 175618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175621 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 175624 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175628 */     // MIs[0] Rn
     /* 175628 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175632 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175636 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175640 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_monotonic>>  =>  (LDSMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINX),
     /* 175643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175647 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175649 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175653 */     GIR_RootConstrainSelectedInstOperands,
     /* 175654 */     // GIR_Coverage, 7884,
     /* 175654 */     GIR_EraseRootFromParent_Done,
     /* 175655 */   // Label 3142: @175655
     /* 175655 */   GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(175697), // Rule ID 7885 //
     /* 175660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175663 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 175666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175670 */     // MIs[0] Rn
     /* 175670 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175678 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175682 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acquire>>  =>  (LDSMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINAX),
     /* 175685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175689 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175691 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175695 */     GIR_RootConstrainSelectedInstOperands,
     /* 175696 */     // GIR_Coverage, 7885,
     /* 175696 */     GIR_EraseRootFromParent_Done,
     /* 175697 */   // Label 3143: @175697
     /* 175697 */   GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(175739), // Rule ID 7886 //
     /* 175702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175705 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 175708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175712 */     // MIs[0] Rn
     /* 175712 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175716 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175724 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_release>>  =>  (LDSMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINLX),
     /* 175727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175729 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175731 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175733 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175737 */     GIR_RootConstrainSelectedInstOperands,
     /* 175738 */     // GIR_Coverage, 7886,
     /* 175738 */     GIR_EraseRootFromParent_Done,
     /* 175739 */   // Label 3144: @175739
     /* 175739 */   GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(175781), // Rule ID 7887 //
     /* 175744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175747 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 175750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175754 */     // MIs[0] Rn
     /* 175754 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175758 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175766 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_acq_rel>>  =>  (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
     /* 175769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175773 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175775 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175779 */     GIR_RootConstrainSelectedInstOperands,
     /* 175780 */     // GIR_Coverage, 7887,
     /* 175780 */     GIR_EraseRootFromParent_Done,
     /* 175781 */   // Label 3145: @175781
     /* 175781 */   GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(175823), // Rule ID 7888 //
     /* 175786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175789 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 175792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175796 */     // MIs[0] Rn
     /* 175796 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175800 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175804 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 175808 */     // (atomic_load_min:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_min_i64>><<P:Predicate_atomic_load_min_i64_seq_cst>>  =>  (LDSMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDSMINALX),
     /* 175811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175815 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175821 */     GIR_RootConstrainSelectedInstOperands,
     /* 175822 */     // GIR_Coverage, 7888,
     /* 175822 */     GIR_EraseRootFromParent_Done,
     /* 175823 */   // Label 3146: @175823
     /* 175823 */   GIM_Reject,
     /* 175824 */ // Label 3141: @175824
     /* 175824 */ GIM_Reject,
     /* 175825 */ // Label 3124: @175825
     /* 175825 */ GIM_Reject,
     /* 175826 */ // Label 35: @175826
     /* 175826 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3149*/ GIMT_Encode4(176817),
     /* 175837 */ /*GILLT_s32*//*Label 3147*/ GIMT_Encode4(175845),
     /* 175841 */ /*GILLT_s64*//*Label 3148*/ GIMT_Encode4(176590),
     /* 175845 */ // Label 3147: @175845
     /* 175845 */ GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(176589),
     /* 175850 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 175853 */   GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(175902), // Rule ID 7909 //
     /* 175858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175861 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 175868 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 175871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175875 */     // MIs[0] Rn
     /* 175875 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175879 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175883 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175887 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_monotonic>>  =>  (LDUMAXW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXW),
     /* 175890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175894 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175900 */     GIR_RootConstrainSelectedInstOperands,
     /* 175901 */     // GIR_Coverage, 7909,
     /* 175901 */     GIR_EraseRootFromParent_Done,
     /* 175902 */   // Label 3151: @175902
     /* 175902 */   GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(175951), // Rule ID 7910 //
     /* 175907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175910 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 175917 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 175920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175924 */     // MIs[0] Rn
     /* 175924 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175928 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175932 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175936 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acquire>>  =>  (LDUMAXAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAW),
     /* 175939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175943 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175945 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175949 */     GIR_RootConstrainSelectedInstOperands,
     /* 175950 */     // GIR_Coverage, 7910,
     /* 175950 */     GIR_EraseRootFromParent_Done,
     /* 175951 */   // Label 3152: @175951
     /* 175951 */   GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(176000), // Rule ID 7911 //
     /* 175956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 175959 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 175966 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 175969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175973 */     // MIs[0] Rn
     /* 175973 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 175977 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 175981 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 175985 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_release>>  =>  (LDUMAXLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 175985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLW),
     /* 175988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 175990 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 175992 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 175994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 175998 */     GIR_RootConstrainSelectedInstOperands,
     /* 175999 */     // GIR_Coverage, 7911,
     /* 175999 */     GIR_EraseRootFromParent_Done,
     /* 176000 */   // Label 3153: @176000
     /* 176000 */   GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(176049), // Rule ID 7912 //
     /* 176005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176008 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 176015 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 176018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176022 */     // MIs[0] Rn
     /* 176022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176026 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176034 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_acq_rel>>  =>  (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
     /* 176037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176047 */     GIR_RootConstrainSelectedInstOperands,
     /* 176048 */     // GIR_Coverage, 7912,
     /* 176048 */     GIR_EraseRootFromParent_Done,
     /* 176049 */   // Label 3154: @176049
     /* 176049 */   GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(176098), // Rule ID 7913 //
     /* 176054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176057 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 176064 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 176067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176071 */     // MIs[0] Rn
     /* 176071 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176083 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i32>><<P:Predicate_atomic_load_umax_i32_seq_cst>>  =>  (LDUMAXALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALW),
     /* 176086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176090 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176092 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176096 */     GIR_RootConstrainSelectedInstOperands,
     /* 176097 */     // GIR_Coverage, 7913,
     /* 176097 */     GIR_EraseRootFromParent_Done,
     /* 176098 */   // Label 3155: @176098
     /* 176098 */   GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(176147), // Rule ID 7914 //
     /* 176103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176106 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 176113 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 176116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176120 */     // MIs[0] Rn
     /* 176120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176124 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176128 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176132 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_monotonic>>  =>  (LDUMAXH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXH),
     /* 176135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176139 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176141 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176145 */     GIR_RootConstrainSelectedInstOperands,
     /* 176146 */     // GIR_Coverage, 7914,
     /* 176146 */     GIR_EraseRootFromParent_Done,
     /* 176147 */   // Label 3156: @176147
     /* 176147 */   GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(176196), // Rule ID 7915 //
     /* 176152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176155 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 176162 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 176165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176169 */     // MIs[0] Rn
     /* 176169 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176173 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176181 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acquire>>  =>  (LDUMAXAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAH),
     /* 176184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176188 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176194 */     GIR_RootConstrainSelectedInstOperands,
     /* 176195 */     // GIR_Coverage, 7915,
     /* 176195 */     GIR_EraseRootFromParent_Done,
     /* 176196 */   // Label 3157: @176196
     /* 176196 */   GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(176245), // Rule ID 7916 //
     /* 176201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176204 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 176211 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 176214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176218 */     // MIs[0] Rn
     /* 176218 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176222 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176226 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176230 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_release>>  =>  (LDUMAXLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLH),
     /* 176233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176237 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176239 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176243 */     GIR_RootConstrainSelectedInstOperands,
     /* 176244 */     // GIR_Coverage, 7916,
     /* 176244 */     GIR_EraseRootFromParent_Done,
     /* 176245 */   // Label 3158: @176245
     /* 176245 */   GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(176294), // Rule ID 7917 //
     /* 176250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176253 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 176260 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 176263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176267 */     // MIs[0] Rn
     /* 176267 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176271 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176279 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_acq_rel>>  =>  (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
     /* 176282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176286 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176292 */     GIR_RootConstrainSelectedInstOperands,
     /* 176293 */     // GIR_Coverage, 7917,
     /* 176293 */     GIR_EraseRootFromParent_Done,
     /* 176294 */   // Label 3159: @176294
     /* 176294 */   GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(176343), // Rule ID 7918 //
     /* 176299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176302 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 176309 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 176312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176316 */     // MIs[0] Rn
     /* 176316 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176320 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176328 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i16>><<P:Predicate_atomic_load_umax_i16_seq_cst>>  =>  (LDUMAXALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALH),
     /* 176331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176333 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176335 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176337 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176341 */     GIR_RootConstrainSelectedInstOperands,
     /* 176342 */     // GIR_Coverage, 7918,
     /* 176342 */     GIR_EraseRootFromParent_Done,
     /* 176343 */   // Label 3160: @176343
     /* 176343 */   GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(176392), // Rule ID 7919 //
     /* 176348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176351 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 176358 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 176361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176365 */     // MIs[0] Rn
     /* 176365 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176369 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176377 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_monotonic>>  =>  (LDUMAXB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXB),
     /* 176380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176384 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176386 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176390 */     GIR_RootConstrainSelectedInstOperands,
     /* 176391 */     // GIR_Coverage, 7919,
     /* 176391 */     GIR_EraseRootFromParent_Done,
     /* 176392 */   // Label 3161: @176392
     /* 176392 */   GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(176441), // Rule ID 7920 //
     /* 176397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176400 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 176407 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 176410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176414 */     // MIs[0] Rn
     /* 176414 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176418 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176422 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176426 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acquire>>  =>  (LDUMAXAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAB),
     /* 176429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176431 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176433 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176435 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176439 */     GIR_RootConstrainSelectedInstOperands,
     /* 176440 */     // GIR_Coverage, 7920,
     /* 176440 */     GIR_EraseRootFromParent_Done,
     /* 176441 */   // Label 3162: @176441
     /* 176441 */   GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(176490), // Rule ID 7921 //
     /* 176446 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176449 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 176456 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 176459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176463 */     // MIs[0] Rn
     /* 176463 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176467 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176471 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176475 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_release>>  =>  (LDUMAXLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLB),
     /* 176478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176482 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176488 */     GIR_RootConstrainSelectedInstOperands,
     /* 176489 */     // GIR_Coverage, 7921,
     /* 176489 */     GIR_EraseRootFromParent_Done,
     /* 176490 */   // Label 3163: @176490
     /* 176490 */   GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(176539), // Rule ID 7922 //
     /* 176495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176498 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 176505 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 176508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176512 */     // MIs[0] Rn
     /* 176512 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176516 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176524 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_acq_rel>>  =>  (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
     /* 176527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176531 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176533 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176537 */     GIR_RootConstrainSelectedInstOperands,
     /* 176538 */     // GIR_Coverage, 7922,
     /* 176538 */     GIR_EraseRootFromParent_Done,
     /* 176539 */   // Label 3164: @176539
     /* 176539 */   GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(176588), // Rule ID 7923 //
     /* 176544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176547 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 176554 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 176557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176561 */     // MIs[0] Rn
     /* 176561 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176565 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176573 */     // (atomic_load_umax:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umax_i8>><<P:Predicate_atomic_load_umax_i8_seq_cst>>  =>  (LDUMAXALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALB),
     /* 176576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176580 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176586 */     GIR_RootConstrainSelectedInstOperands,
     /* 176587 */     // GIR_Coverage, 7923,
     /* 176587 */     GIR_EraseRootFromParent_Done,
     /* 176588 */   // Label 3165: @176588
     /* 176588 */   GIM_Reject,
     /* 176589 */ // Label 3150: @176589
     /* 176589 */ GIM_Reject,
     /* 176590 */ // Label 3148: @176590
     /* 176590 */ GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(176816),
     /* 176595 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 176598 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 176605 */   GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(176647), // Rule ID 7904 //
     /* 176610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176613 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 176616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176620 */     // MIs[0] Rn
     /* 176620 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176624 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176632 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_monotonic>>  =>  (LDUMAXX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXX),
     /* 176635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176639 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176641 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176645 */     GIR_RootConstrainSelectedInstOperands,
     /* 176646 */     // GIR_Coverage, 7904,
     /* 176646 */     GIR_EraseRootFromParent_Done,
     /* 176647 */   // Label 3167: @176647
     /* 176647 */   GIM_Try, /*On fail goto*//*Label 3168*/ GIMT_Encode4(176689), // Rule ID 7905 //
     /* 176652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176655 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 176658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176662 */     // MIs[0] Rn
     /* 176662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176666 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176674 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acquire>>  =>  (LDUMAXAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXAX),
     /* 176677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176681 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176683 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176687 */     GIR_RootConstrainSelectedInstOperands,
     /* 176688 */     // GIR_Coverage, 7905,
     /* 176688 */     GIR_EraseRootFromParent_Done,
     /* 176689 */   // Label 3168: @176689
     /* 176689 */   GIM_Try, /*On fail goto*//*Label 3169*/ GIMT_Encode4(176731), // Rule ID 7906 //
     /* 176694 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176697 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 176700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176704 */     // MIs[0] Rn
     /* 176704 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176708 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176712 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176716 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_release>>  =>  (LDUMAXLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXLX),
     /* 176719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176723 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176725 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176729 */     GIR_RootConstrainSelectedInstOperands,
     /* 176730 */     // GIR_Coverage, 7906,
     /* 176730 */     GIR_EraseRootFromParent_Done,
     /* 176731 */   // Label 3169: @176731
     /* 176731 */   GIM_Try, /*On fail goto*//*Label 3170*/ GIMT_Encode4(176773), // Rule ID 7907 //
     /* 176736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176739 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 176742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176746 */     // MIs[0] Rn
     /* 176746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176750 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176754 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176758 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_acq_rel>>  =>  (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
     /* 176761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176765 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176771 */     GIR_RootConstrainSelectedInstOperands,
     /* 176772 */     // GIR_Coverage, 7907,
     /* 176772 */     GIR_EraseRootFromParent_Done,
     /* 176773 */   // Label 3170: @176773
     /* 176773 */   GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(176815), // Rule ID 7908 //
     /* 176778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176781 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 176784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176788 */     // MIs[0] Rn
     /* 176788 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176792 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176796 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 176800 */     // (atomic_load_umax:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umax_i64>><<P:Predicate_atomic_load_umax_i64_seq_cst>>  =>  (LDUMAXALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMAXALX),
     /* 176803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176807 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176809 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176813 */     GIR_RootConstrainSelectedInstOperands,
     /* 176814 */     // GIR_Coverage, 7908,
     /* 176814 */     GIR_EraseRootFromParent_Done,
     /* 176815 */   // Label 3171: @176815
     /* 176815 */   GIM_Reject,
     /* 176816 */ // Label 3166: @176816
     /* 176816 */ GIM_Reject,
     /* 176817 */ // Label 3149: @176817
     /* 176817 */ GIM_Reject,
     /* 176818 */ // Label 36: @176818
     /* 176818 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 3174*/ GIMT_Encode4(177809),
     /* 176829 */ /*GILLT_s32*//*Label 3172*/ GIMT_Encode4(176837),
     /* 176833 */ /*GILLT_s64*//*Label 3173*/ GIMT_Encode4(177582),
     /* 176837 */ // Label 3172: @176837
     /* 176837 */ GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(177581),
     /* 176842 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 176845 */   GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(176894), // Rule ID 7929 //
     /* 176850 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176853 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 176860 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 176863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176867 */     // MIs[0] Rn
     /* 176867 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176871 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176879 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_monotonic>>  =>  (LDUMINW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINW),
     /* 176882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176886 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176888 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176892 */     GIR_RootConstrainSelectedInstOperands,
     /* 176893 */     // GIR_Coverage, 7929,
     /* 176893 */     GIR_EraseRootFromParent_Done,
     /* 176894 */   // Label 3176: @176894
     /* 176894 */   GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(176943), // Rule ID 7930 //
     /* 176899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176902 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 176909 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 176912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176916 */     // MIs[0] Rn
     /* 176916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176920 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176924 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176928 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acquire>>  =>  (LDUMINAW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAW),
     /* 176931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176935 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176937 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176941 */     GIR_RootConstrainSelectedInstOperands,
     /* 176942 */     // GIR_Coverage, 7930,
     /* 176942 */     GIR_EraseRootFromParent_Done,
     /* 176943 */   // Label 3177: @176943
     /* 176943 */   GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(176992), // Rule ID 7931 //
     /* 176948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 176951 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 176958 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 176961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176965 */     // MIs[0] Rn
     /* 176965 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 176969 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 176973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 176977 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_release>>  =>  (LDUMINLW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 176977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLW),
     /* 176980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 176982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 176984 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 176986 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 176990 */     GIR_RootConstrainSelectedInstOperands,
     /* 176991 */     // GIR_Coverage, 7931,
     /* 176991 */     GIR_EraseRootFromParent_Done,
     /* 176992 */   // Label 3178: @176992
     /* 176992 */   GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(177041), // Rule ID 7932 //
     /* 176997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177000 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 177007 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 177010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177014 */     // MIs[0] Rn
     /* 177014 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177022 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177026 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_acq_rel>>  =>  (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
     /* 177029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177031 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177033 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177035 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177039 */     GIR_RootConstrainSelectedInstOperands,
     /* 177040 */     // GIR_Coverage, 7932,
     /* 177040 */     GIR_EraseRootFromParent_Done,
     /* 177041 */   // Label 3179: @177041
     /* 177041 */   GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(177090), // Rule ID 7933 //
     /* 177046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177049 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 177056 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 177059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177063 */     // MIs[0] Rn
     /* 177063 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177075 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i32>><<P:Predicate_atomic_load_umin_i32_seq_cst>>  =>  (LDUMINALW:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALW),
     /* 177078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177082 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177088 */     GIR_RootConstrainSelectedInstOperands,
     /* 177089 */     // GIR_Coverage, 7933,
     /* 177089 */     GIR_EraseRootFromParent_Done,
     /* 177090 */   // Label 3180: @177090
     /* 177090 */   GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(177139), // Rule ID 7934 //
     /* 177095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177098 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177105 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 177108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177112 */     // MIs[0] Rn
     /* 177112 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177116 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177124 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_monotonic>>  =>  (LDUMINH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINH),
     /* 177127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177131 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177133 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177137 */     GIR_RootConstrainSelectedInstOperands,
     /* 177138 */     // GIR_Coverage, 7934,
     /* 177138 */     GIR_EraseRootFromParent_Done,
     /* 177139 */   // Label 3181: @177139
     /* 177139 */   GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(177188), // Rule ID 7935 //
     /* 177144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177147 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177154 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 177157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177161 */     // MIs[0] Rn
     /* 177161 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177165 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177173 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acquire>>  =>  (LDUMINAH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAH),
     /* 177176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177180 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177182 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177186 */     GIR_RootConstrainSelectedInstOperands,
     /* 177187 */     // GIR_Coverage, 7935,
     /* 177187 */     GIR_EraseRootFromParent_Done,
     /* 177188 */   // Label 3182: @177188
     /* 177188 */   GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(177237), // Rule ID 7936 //
     /* 177193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177196 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177203 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 177206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177210 */     // MIs[0] Rn
     /* 177210 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177214 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177218 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177222 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_release>>  =>  (LDUMINLH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLH),
     /* 177225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177227 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177229 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177231 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177235 */     GIR_RootConstrainSelectedInstOperands,
     /* 177236 */     // GIR_Coverage, 7936,
     /* 177236 */     GIR_EraseRootFromParent_Done,
     /* 177237 */   // Label 3183: @177237
     /* 177237 */   GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(177286), // Rule ID 7937 //
     /* 177242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177245 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177252 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 177255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177259 */     // MIs[0] Rn
     /* 177259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177263 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177267 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177271 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_acq_rel>>  =>  (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
     /* 177274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177276 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177278 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177280 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177284 */     GIR_RootConstrainSelectedInstOperands,
     /* 177285 */     // GIR_Coverage, 7937,
     /* 177285 */     GIR_EraseRootFromParent_Done,
     /* 177286 */   // Label 3184: @177286
     /* 177286 */   GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(177335), // Rule ID 7938 //
     /* 177291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177294 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177301 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 177304 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177308 */     // MIs[0] Rn
     /* 177308 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177312 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177316 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177320 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i16>><<P:Predicate_atomic_load_umin_i16_seq_cst>>  =>  (LDUMINALH:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALH),
     /* 177323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177327 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177329 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177333 */     GIR_RootConstrainSelectedInstOperands,
     /* 177334 */     // GIR_Coverage, 7938,
     /* 177334 */     GIR_EraseRootFromParent_Done,
     /* 177335 */   // Label 3185: @177335
     /* 177335 */   GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(177384), // Rule ID 7939 //
     /* 177340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177343 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 177350 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 177353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177357 */     // MIs[0] Rn
     /* 177357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177361 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177369 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_monotonic>>  =>  (LDUMINB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINB),
     /* 177372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177376 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177382 */     GIR_RootConstrainSelectedInstOperands,
     /* 177383 */     // GIR_Coverage, 7939,
     /* 177383 */     GIR_EraseRootFromParent_Done,
     /* 177384 */   // Label 3186: @177384
     /* 177384 */   GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(177433), // Rule ID 7940 //
     /* 177389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177392 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 177399 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 177402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177406 */     // MIs[0] Rn
     /* 177406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177418 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acquire>>  =>  (LDUMINAB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAB),
     /* 177421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177425 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177427 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177431 */     GIR_RootConstrainSelectedInstOperands,
     /* 177432 */     // GIR_Coverage, 7940,
     /* 177432 */     GIR_EraseRootFromParent_Done,
     /* 177433 */   // Label 3187: @177433
     /* 177433 */   GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(177482), // Rule ID 7941 //
     /* 177438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177441 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 177448 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 177451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177455 */     // MIs[0] Rn
     /* 177455 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177459 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177463 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177467 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_release>>  =>  (LDUMINLB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLB),
     /* 177470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177474 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177476 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177480 */     GIR_RootConstrainSelectedInstOperands,
     /* 177481 */     // GIR_Coverage, 7941,
     /* 177481 */     GIR_EraseRootFromParent_Done,
     /* 177482 */   // Label 3188: @177482
     /* 177482 */   GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(177531), // Rule ID 7942 //
     /* 177487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177490 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 177497 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 177500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177504 */     // MIs[0] Rn
     /* 177504 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177508 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177516 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_acq_rel>>  =>  (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
     /* 177519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177523 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177525 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177529 */     GIR_RootConstrainSelectedInstOperands,
     /* 177530 */     // GIR_Coverage, 7942,
     /* 177530 */     GIR_EraseRootFromParent_Done,
     /* 177531 */   // Label 3189: @177531
     /* 177531 */   GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(177580), // Rule ID 7943 //
     /* 177536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177539 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 177546 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 177549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177553 */     // MIs[0] Rn
     /* 177553 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177557 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177561 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 177565 */     // (atomic_load_umin:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm)<<P:Predicate_atomic_load_umin_i8>><<P:Predicate_atomic_load_umin_i8_seq_cst>>  =>  (LDUMINALB:{ *:[i32] } GPR32:{ *:[i32] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALB),
     /* 177568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177572 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177574 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177578 */     GIR_RootConstrainSelectedInstOperands,
     /* 177579 */     // GIR_Coverage, 7943,
     /* 177579 */     GIR_EraseRootFromParent_Done,
     /* 177580 */   // Label 3190: @177580
     /* 177580 */   GIM_Reject,
     /* 177581 */ // Label 3175: @177581
     /* 177581 */ GIM_Reject,
     /* 177582 */ // Label 3173: @177582
     /* 177582 */ GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(177808),
     /* 177587 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 177590 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 177597 */   GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(177639), // Rule ID 7924 //
     /* 177602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177605 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 177608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177612 */     // MIs[0] Rn
     /* 177612 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177616 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177624 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_monotonic>>  =>  (LDUMINX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINX),
     /* 177627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177631 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177633 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177637 */     GIR_RootConstrainSelectedInstOperands,
     /* 177638 */     // GIR_Coverage, 7924,
     /* 177638 */     GIR_EraseRootFromParent_Done,
     /* 177639 */   // Label 3192: @177639
     /* 177639 */   GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(177681), // Rule ID 7925 //
     /* 177644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177647 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 177650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177654 */     // MIs[0] Rn
     /* 177654 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177658 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177662 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177666 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acquire>>  =>  (LDUMINAX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINAX),
     /* 177669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177673 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177675 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177679 */     GIR_RootConstrainSelectedInstOperands,
     /* 177680 */     // GIR_Coverage, 7925,
     /* 177680 */     GIR_EraseRootFromParent_Done,
     /* 177681 */   // Label 3193: @177681
     /* 177681 */   GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(177723), // Rule ID 7926 //
     /* 177686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177689 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 177692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177696 */     // MIs[0] Rn
     /* 177696 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177700 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177704 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177708 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_release>>  =>  (LDUMINLX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINLX),
     /* 177711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177715 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177717 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177721 */     GIR_RootConstrainSelectedInstOperands,
     /* 177722 */     // GIR_Coverage, 7926,
     /* 177722 */     GIR_EraseRootFromParent_Done,
     /* 177723 */   // Label 3194: @177723
     /* 177723 */   GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(177765), // Rule ID 7927 //
     /* 177728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177731 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 177734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177738 */     // MIs[0] Rn
     /* 177738 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177742 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177746 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177750 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_acq_rel>>  =>  (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
     /* 177753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177757 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177759 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177763 */     GIR_RootConstrainSelectedInstOperands,
     /* 177764 */     // GIR_Coverage, 7927,
     /* 177764 */     GIR_EraseRootFromParent_Done,
     /* 177765 */   // Label 3195: @177765
     /* 177765 */   GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(177807), // Rule ID 7928 //
     /* 177770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSE),
     /* 177773 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 177776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177780 */     // MIs[0] Rn
     /* 177780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177784 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 177788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 177792 */     // (atomic_load_umin:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)<<P:Predicate_atomic_load_umin_i64>><<P:Predicate_atomic_load_umin_i64_seq_cst>>  =>  (LDUMINALX:{ *:[i64] } GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 177792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDUMINALX),
     /* 177795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177799 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177801 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177805 */     GIR_RootConstrainSelectedInstOperands,
     /* 177806 */     // GIR_Coverage, 7928,
     /* 177806 */     GIR_EraseRootFromParent_Done,
     /* 177807 */   // Label 3196: @177807
     /* 177807 */   GIM_Reject,
     /* 177808 */ // Label 3191: @177808
     /* 177808 */ GIM_Reject,
     /* 177809 */ // Label 3174: @177809
     /* 177809 */ GIM_Reject,
     /* 177810 */ // Label 37: @177810
     /* 177810 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 3200*/ GIMT_Encode4(178514),
     /* 177821 */ /*GILLT_s16*//*Label 3197*/ GIMT_Encode4(177833),
     /* 177825 */ /*GILLT_s32*//*Label 3198*/ GIMT_Encode4(178060),
     /* 177829 */ /*GILLT_s64*//*Label 3199*/ GIMT_Encode4(178287),
     /* 177833 */ // Label 3197: @177833
     /* 177833 */ GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(178059),
     /* 177838 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 177841 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 177848 */   GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(177890), // Rule ID 2623 //
     /* 177853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 177856 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 177859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177863 */     // MIs[0] Rn
     /* 177863 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177875 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_monotonic>>  =>  (LDFADDH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 177875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDH),
     /* 177878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177882 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177884 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177888 */     GIR_RootConstrainSelectedInstOperands,
     /* 177889 */     // GIR_Coverage, 2623,
     /* 177889 */     GIR_EraseRootFromParent_Done,
     /* 177890 */   // Label 3202: @177890
     /* 177890 */   GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(177932), // Rule ID 2624 //
     /* 177895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 177898 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 177901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177905 */     // MIs[0] Rn
     /* 177905 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177909 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177917 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_acquire>>  =>  (LDFADDAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 177917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAH),
     /* 177920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177924 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177926 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177930 */     GIR_RootConstrainSelectedInstOperands,
     /* 177931 */     // GIR_Coverage, 2624,
     /* 177931 */     GIR_EraseRootFromParent_Done,
     /* 177932 */   // Label 3203: @177932
     /* 177932 */   GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(177974), // Rule ID 2625 //
     /* 177937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 177940 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 177943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177947 */     // MIs[0] Rn
     /* 177947 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177951 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177959 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_release>>  =>  (LDFADDLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 177959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLH),
     /* 177962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 177964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 177966 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 177968 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 177972 */     GIR_RootConstrainSelectedInstOperands,
     /* 177973 */     // GIR_Coverage, 2625,
     /* 177973 */     GIR_EraseRootFromParent_Done,
     /* 177974 */   // Label 3204: @177974
     /* 177974 */   GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(178016), // Rule ID 2626 //
     /* 177979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 177982 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 177985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 177989 */     // MIs[0] Rn
     /* 177989 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 177993 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 177997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178001 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_acq_rel>>  =>  (LDFADDALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALH),
     /* 178004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178010 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178014 */     GIR_RootConstrainSelectedInstOperands,
     /* 178015 */     // GIR_Coverage, 2626,
     /* 178015 */     GIR_EraseRootFromParent_Done,
     /* 178016 */   // Label 3205: @178016
     /* 178016 */   GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(178058), // Rule ID 2627 //
     /* 178021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178024 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 178027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178031 */     // MIs[0] Rn
     /* 178031 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178035 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178043 */     // (atomic_load_fadd:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fadd_f16>><<P:Predicate_atomic_load_fadd_f16_seq_cst>>  =>  (LDFADDALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALH),
     /* 178046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178050 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178056 */     GIR_RootConstrainSelectedInstOperands,
     /* 178057 */     // GIR_Coverage, 2627,
     /* 178057 */     GIR_EraseRootFromParent_Done,
     /* 178058 */   // Label 3206: @178058
     /* 178058 */   GIM_Reject,
     /* 178059 */ // Label 3201: @178059
     /* 178059 */ GIM_Reject,
     /* 178060 */ // Label 3198: @178060
     /* 178060 */ GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(178286),
     /* 178065 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 178068 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 178075 */   GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(178117), // Rule ID 8019 //
     /* 178080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178083 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 178086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178090 */     // MIs[0] Rn
     /* 178090 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178102 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_monotonic>>  =>  (LDFADDS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDS),
     /* 178105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178109 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178111 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178115 */     GIR_RootConstrainSelectedInstOperands,
     /* 178116 */     // GIR_Coverage, 8019,
     /* 178116 */     GIR_EraseRootFromParent_Done,
     /* 178117 */   // Label 3208: @178117
     /* 178117 */   GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(178159), // Rule ID 8020 //
     /* 178122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178125 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 178128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178132 */     // MIs[0] Rn
     /* 178132 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178136 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178144 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_acquire>>  =>  (LDFADDAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAS),
     /* 178147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178149 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178151 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178153 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178157 */     GIR_RootConstrainSelectedInstOperands,
     /* 178158 */     // GIR_Coverage, 8020,
     /* 178158 */     GIR_EraseRootFromParent_Done,
     /* 178159 */   // Label 3209: @178159
     /* 178159 */   GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(178201), // Rule ID 8021 //
     /* 178164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178167 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 178170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178174 */     // MIs[0] Rn
     /* 178174 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178178 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178182 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178186 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_release>>  =>  (LDFADDLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLS),
     /* 178189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178191 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178193 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178195 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178199 */     GIR_RootConstrainSelectedInstOperands,
     /* 178200 */     // GIR_Coverage, 8021,
     /* 178200 */     GIR_EraseRootFromParent_Done,
     /* 178201 */   // Label 3210: @178201
     /* 178201 */   GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(178243), // Rule ID 8022 //
     /* 178206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178209 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 178212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178216 */     // MIs[0] Rn
     /* 178216 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178220 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178228 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_acq_rel>>  =>  (LDFADDALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALS),
     /* 178231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178235 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178237 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178241 */     GIR_RootConstrainSelectedInstOperands,
     /* 178242 */     // GIR_Coverage, 8022,
     /* 178242 */     GIR_EraseRootFromParent_Done,
     /* 178243 */   // Label 3211: @178243
     /* 178243 */   GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(178285), // Rule ID 8023 //
     /* 178248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178251 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 178254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178258 */     // MIs[0] Rn
     /* 178258 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178262 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178266 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178270 */     // (atomic_load_fadd:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fadd_f32>><<P:Predicate_atomic_load_fadd_f32_seq_cst>>  =>  (LDFADDALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALS),
     /* 178273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178277 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178283 */     GIR_RootConstrainSelectedInstOperands,
     /* 178284 */     // GIR_Coverage, 8023,
     /* 178284 */     GIR_EraseRootFromParent_Done,
     /* 178285 */   // Label 3212: @178285
     /* 178285 */   GIM_Reject,
     /* 178286 */ // Label 3207: @178286
     /* 178286 */ GIM_Reject,
     /* 178287 */ // Label 3199: @178287
     /* 178287 */ GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(178513),
     /* 178292 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 178295 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 178302 */   GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(178344), // Rule ID 8024 //
     /* 178307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178310 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 178313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178317 */     // MIs[0] Rn
     /* 178317 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178329 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_monotonic>>  =>  (LDFADDD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDD),
     /* 178332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178336 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178338 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178342 */     GIR_RootConstrainSelectedInstOperands,
     /* 178343 */     // GIR_Coverage, 8024,
     /* 178343 */     GIR_EraseRootFromParent_Done,
     /* 178344 */   // Label 3214: @178344
     /* 178344 */   GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(178386), // Rule ID 8025 //
     /* 178349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178352 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 178355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178359 */     // MIs[0] Rn
     /* 178359 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178363 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178371 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_acquire>>  =>  (LDFADDAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDAD),
     /* 178374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178384 */     GIR_RootConstrainSelectedInstOperands,
     /* 178385 */     // GIR_Coverage, 8025,
     /* 178385 */     GIR_EraseRootFromParent_Done,
     /* 178386 */   // Label 3215: @178386
     /* 178386 */   GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(178428), // Rule ID 8026 //
     /* 178391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178394 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 178397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178401 */     // MIs[0] Rn
     /* 178401 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178405 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178413 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_release>>  =>  (LDFADDLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDLD),
     /* 178416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178420 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178422 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178426 */     GIR_RootConstrainSelectedInstOperands,
     /* 178427 */     // GIR_Coverage, 8026,
     /* 178427 */     GIR_EraseRootFromParent_Done,
     /* 178428 */   // Label 3216: @178428
     /* 178428 */   GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(178470), // Rule ID 8027 //
     /* 178433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178436 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 178439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178443 */     // MIs[0] Rn
     /* 178443 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178447 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178451 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178455 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_acq_rel>>  =>  (LDFADDALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALD),
     /* 178458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178460 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178462 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178464 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178468 */     GIR_RootConstrainSelectedInstOperands,
     /* 178469 */     // GIR_Coverage, 8027,
     /* 178469 */     GIR_EraseRootFromParent_Done,
     /* 178470 */   // Label 3217: @178470
     /* 178470 */   GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(178512), // Rule ID 8028 //
     /* 178475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178478 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 178481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178485 */     // MIs[0] Rn
     /* 178485 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178489 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178493 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178497 */     // (atomic_load_fadd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fadd_f64>><<P:Predicate_atomic_load_fadd_f64_seq_cst>>  =>  (LDFADDALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFADDALD),
     /* 178500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178504 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178510 */     GIR_RootConstrainSelectedInstOperands,
     /* 178511 */     // GIR_Coverage, 8028,
     /* 178511 */     GIR_EraseRootFromParent_Done,
     /* 178512 */   // Label 3218: @178512
     /* 178512 */   GIM_Reject,
     /* 178513 */ // Label 3213: @178513
     /* 178513 */ GIM_Reject,
     /* 178514 */ // Label 3200: @178514
     /* 178514 */ GIM_Reject,
     /* 178515 */ // Label 38: @178515
     /* 178515 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 3222*/ GIMT_Encode4(179219),
     /* 178526 */ /*GILLT_s16*//*Label 3219*/ GIMT_Encode4(178538),
     /* 178530 */ /*GILLT_s32*//*Label 3220*/ GIMT_Encode4(178765),
     /* 178534 */ /*GILLT_s64*//*Label 3221*/ GIMT_Encode4(178992),
     /* 178538 */ // Label 3219: @178538
     /* 178538 */ GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(178764),
     /* 178543 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 178546 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 178553 */   GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(178595), // Rule ID 8029 //
     /* 178558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178561 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 178564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178568 */     // MIs[0] Rn
     /* 178568 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178580 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_monotonic>>  =>  (LDFMAXNMH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMH),
     /* 178583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178587 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178589 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178593 */     GIR_RootConstrainSelectedInstOperands,
     /* 178594 */     // GIR_Coverage, 8029,
     /* 178594 */     GIR_EraseRootFromParent_Done,
     /* 178595 */   // Label 3224: @178595
     /* 178595 */   GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(178637), // Rule ID 8030 //
     /* 178600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178603 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 178606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178610 */     // MIs[0] Rn
     /* 178610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178614 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178622 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_acquire>>  =>  (LDFMAXNMAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAH),
     /* 178625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178627 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178629 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178631 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178635 */     GIR_RootConstrainSelectedInstOperands,
     /* 178636 */     // GIR_Coverage, 8030,
     /* 178636 */     GIR_EraseRootFromParent_Done,
     /* 178637 */   // Label 3225: @178637
     /* 178637 */   GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(178679), // Rule ID 8031 //
     /* 178642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178645 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 178648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178652 */     // MIs[0] Rn
     /* 178652 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178656 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178664 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_release>>  =>  (LDFMAXNMLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLH),
     /* 178667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178669 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178671 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178673 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178677 */     GIR_RootConstrainSelectedInstOperands,
     /* 178678 */     // GIR_Coverage, 8031,
     /* 178678 */     GIR_EraseRootFromParent_Done,
     /* 178679 */   // Label 3226: @178679
     /* 178679 */   GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(178721), // Rule ID 8032 //
     /* 178684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178687 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 178690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178694 */     // MIs[0] Rn
     /* 178694 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178698 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178706 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_acq_rel>>  =>  (LDFMAXNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALH),
     /* 178709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178713 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178715 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178719 */     GIR_RootConstrainSelectedInstOperands,
     /* 178720 */     // GIR_Coverage, 8032,
     /* 178720 */     GIR_EraseRootFromParent_Done,
     /* 178721 */   // Label 3227: @178721
     /* 178721 */   GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(178763), // Rule ID 8033 //
     /* 178726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178729 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 178732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178736 */     // MIs[0] Rn
     /* 178736 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 178748 */     // (atomic_load_fmax:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmax_f16>><<P:Predicate_atomic_load_fmax_f16_seq_cst>>  =>  (LDFMAXNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALH),
     /* 178751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178755 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178757 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178761 */     GIR_RootConstrainSelectedInstOperands,
     /* 178762 */     // GIR_Coverage, 8033,
     /* 178762 */     GIR_EraseRootFromParent_Done,
     /* 178763 */   // Label 3228: @178763
     /* 178763 */   GIM_Reject,
     /* 178764 */ // Label 3223: @178764
     /* 178764 */ GIM_Reject,
     /* 178765 */ // Label 3220: @178765
     /* 178765 */ GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(178991),
     /* 178770 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 178773 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 178780 */   GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(178822), // Rule ID 8034 //
     /* 178785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178788 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 178791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178795 */     // MIs[0] Rn
     /* 178795 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178799 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178803 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178807 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_monotonic>>  =>  (LDFMAXNMS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMS),
     /* 178810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178814 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178816 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178820 */     GIR_RootConstrainSelectedInstOperands,
     /* 178821 */     // GIR_Coverage, 8034,
     /* 178821 */     GIR_EraseRootFromParent_Done,
     /* 178822 */   // Label 3230: @178822
     /* 178822 */   GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(178864), // Rule ID 8035 //
     /* 178827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178830 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 178833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178837 */     // MIs[0] Rn
     /* 178837 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178841 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178845 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178849 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_acquire>>  =>  (LDFMAXNMAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAS),
     /* 178852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178856 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178858 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178862 */     GIR_RootConstrainSelectedInstOperands,
     /* 178863 */     // GIR_Coverage, 8035,
     /* 178863 */     GIR_EraseRootFromParent_Done,
     /* 178864 */   // Label 3231: @178864
     /* 178864 */   GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(178906), // Rule ID 8036 //
     /* 178869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178872 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 178875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178879 */     // MIs[0] Rn
     /* 178879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178883 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178891 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_release>>  =>  (LDFMAXNMLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLS),
     /* 178894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178900 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178904 */     GIR_RootConstrainSelectedInstOperands,
     /* 178905 */     // GIR_Coverage, 8036,
     /* 178905 */     GIR_EraseRootFromParent_Done,
     /* 178906 */   // Label 3232: @178906
     /* 178906 */   GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(178948), // Rule ID 8037 //
     /* 178911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178914 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 178917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178921 */     // MIs[0] Rn
     /* 178921 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178925 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178933 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_acq_rel>>  =>  (LDFMAXNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALS),
     /* 178936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178940 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178946 */     GIR_RootConstrainSelectedInstOperands,
     /* 178947 */     // GIR_Coverage, 8037,
     /* 178947 */     GIR_EraseRootFromParent_Done,
     /* 178948 */   // Label 3233: @178948
     /* 178948 */   GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(178990), // Rule ID 8038 //
     /* 178953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 178956 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 178959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178963 */     // MIs[0] Rn
     /* 178963 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 178967 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 178971 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 178975 */     // (atomic_load_fmax:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmax_f32>><<P:Predicate_atomic_load_fmax_f32_seq_cst>>  =>  (LDFMAXNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 178975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALS),
     /* 178978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 178980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 178982 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 178984 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 178988 */     GIR_RootConstrainSelectedInstOperands,
     /* 178989 */     // GIR_Coverage, 8038,
     /* 178989 */     GIR_EraseRootFromParent_Done,
     /* 178990 */   // Label 3234: @178990
     /* 178990 */   GIM_Reject,
     /* 178991 */ // Label 3229: @178991
     /* 178991 */ GIM_Reject,
     /* 178992 */ // Label 3221: @178992
     /* 178992 */ GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(179218),
     /* 178997 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179000 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 179007 */   GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(179049), // Rule ID 8039 //
     /* 179012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179015 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 179018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179022 */     // MIs[0] Rn
     /* 179022 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179026 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179030 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179034 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_monotonic>>  =>  (LDFMAXNMD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMD),
     /* 179037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179039 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179043 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179047 */     GIR_RootConstrainSelectedInstOperands,
     /* 179048 */     // GIR_Coverage, 8039,
     /* 179048 */     GIR_EraseRootFromParent_Done,
     /* 179049 */   // Label 3236: @179049
     /* 179049 */   GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(179091), // Rule ID 8040 //
     /* 179054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179057 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 179060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179064 */     // MIs[0] Rn
     /* 179064 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179068 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179076 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_acquire>>  =>  (LDFMAXNMAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMAD),
     /* 179079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179085 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179089 */     GIR_RootConstrainSelectedInstOperands,
     /* 179090 */     // GIR_Coverage, 8040,
     /* 179090 */     GIR_EraseRootFromParent_Done,
     /* 179091 */   // Label 3237: @179091
     /* 179091 */   GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(179133), // Rule ID 8041 //
     /* 179096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179099 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 179102 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179106 */     // MIs[0] Rn
     /* 179106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179110 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179114 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179118 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_release>>  =>  (LDFMAXNMLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMLD),
     /* 179121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179125 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179131 */     GIR_RootConstrainSelectedInstOperands,
     /* 179132 */     // GIR_Coverage, 8041,
     /* 179132 */     GIR_EraseRootFromParent_Done,
     /* 179133 */   // Label 3238: @179133
     /* 179133 */   GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(179175), // Rule ID 8042 //
     /* 179138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179141 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 179144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179148 */     // MIs[0] Rn
     /* 179148 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179152 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179160 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_acq_rel>>  =>  (LDFMAXNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALD),
     /* 179163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179167 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179173 */     GIR_RootConstrainSelectedInstOperands,
     /* 179174 */     // GIR_Coverage, 8042,
     /* 179174 */     GIR_EraseRootFromParent_Done,
     /* 179175 */   // Label 3239: @179175
     /* 179175 */   GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(179217), // Rule ID 8043 //
     /* 179180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179183 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 179186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179190 */     // MIs[0] Rn
     /* 179190 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179194 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179202 */     // (atomic_load_fmax:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmax_f64>><<P:Predicate_atomic_load_fmax_f64_seq_cst>>  =>  (LDFMAXNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXNMALD),
     /* 179205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179211 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179215 */     GIR_RootConstrainSelectedInstOperands,
     /* 179216 */     // GIR_Coverage, 8043,
     /* 179216 */     GIR_EraseRootFromParent_Done,
     /* 179217 */   // Label 3240: @179217
     /* 179217 */   GIM_Reject,
     /* 179218 */ // Label 3235: @179218
     /* 179218 */ GIM_Reject,
     /* 179219 */ // Label 3222: @179219
     /* 179219 */ GIM_Reject,
     /* 179220 */ // Label 39: @179220
     /* 179220 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 3244*/ GIMT_Encode4(179924),
     /* 179231 */ /*GILLT_s16*//*Label 3241*/ GIMT_Encode4(179243),
     /* 179235 */ /*GILLT_s32*//*Label 3242*/ GIMT_Encode4(179470),
     /* 179239 */ /*GILLT_s64*//*Label 3243*/ GIMT_Encode4(179697),
     /* 179243 */ // Label 3241: @179243
     /* 179243 */ GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(179469),
     /* 179248 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 179251 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 179258 */   GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(179300), // Rule ID 8044 //
     /* 179263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179266 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 179269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179273 */     // MIs[0] Rn
     /* 179273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179277 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179281 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179285 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_monotonic>>  =>  (LDFMINNMH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMH),
     /* 179288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179290 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179292 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179294 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179298 */     GIR_RootConstrainSelectedInstOperands,
     /* 179299 */     // GIR_Coverage, 8044,
     /* 179299 */     GIR_EraseRootFromParent_Done,
     /* 179300 */   // Label 3246: @179300
     /* 179300 */   GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(179342), // Rule ID 8045 //
     /* 179305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179308 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 179311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179315 */     // MIs[0] Rn
     /* 179315 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179319 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179323 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179327 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_acquire>>  =>  (LDFMINNMAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAH),
     /* 179330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179334 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179340 */     GIR_RootConstrainSelectedInstOperands,
     /* 179341 */     // GIR_Coverage, 8045,
     /* 179341 */     GIR_EraseRootFromParent_Done,
     /* 179342 */   // Label 3247: @179342
     /* 179342 */   GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(179384), // Rule ID 8046 //
     /* 179347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179350 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 179353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179357 */     // MIs[0] Rn
     /* 179357 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179361 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179369 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_release>>  =>  (LDFMINNMLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLH),
     /* 179372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179376 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179378 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179382 */     GIR_RootConstrainSelectedInstOperands,
     /* 179383 */     // GIR_Coverage, 8046,
     /* 179383 */     GIR_EraseRootFromParent_Done,
     /* 179384 */   // Label 3248: @179384
     /* 179384 */   GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(179426), // Rule ID 8047 //
     /* 179389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179392 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 179395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179399 */     // MIs[0] Rn
     /* 179399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179403 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179411 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_acq_rel>>  =>  (LDFMINNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALH),
     /* 179414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179418 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179424 */     GIR_RootConstrainSelectedInstOperands,
     /* 179425 */     // GIR_Coverage, 8047,
     /* 179425 */     GIR_EraseRootFromParent_Done,
     /* 179426 */   // Label 3249: @179426
     /* 179426 */   GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(179468), // Rule ID 8048 //
     /* 179431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179434 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 179437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179441 */     // MIs[0] Rn
     /* 179441 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179445 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179453 */     // (atomic_load_fmin:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmin_f16>><<P:Predicate_atomic_load_fmin_f16_seq_cst>>  =>  (LDFMINNMALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALH),
     /* 179456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179460 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179462 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179466 */     GIR_RootConstrainSelectedInstOperands,
     /* 179467 */     // GIR_Coverage, 8048,
     /* 179467 */     GIR_EraseRootFromParent_Done,
     /* 179468 */   // Label 3250: @179468
     /* 179468 */   GIM_Reject,
     /* 179469 */ // Label 3245: @179469
     /* 179469 */ GIM_Reject,
     /* 179470 */ // Label 3242: @179470
     /* 179470 */ GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(179696),
     /* 179475 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 179478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 179485 */   GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(179527), // Rule ID 8049 //
     /* 179490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179493 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 179496 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179500 */     // MIs[0] Rn
     /* 179500 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179504 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179508 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179512 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_monotonic>>  =>  (LDFMINNMS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMS),
     /* 179515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179519 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179521 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179525 */     GIR_RootConstrainSelectedInstOperands,
     /* 179526 */     // GIR_Coverage, 8049,
     /* 179526 */     GIR_EraseRootFromParent_Done,
     /* 179527 */   // Label 3252: @179527
     /* 179527 */   GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(179569), // Rule ID 8050 //
     /* 179532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179535 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 179538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179542 */     // MIs[0] Rn
     /* 179542 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179546 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179554 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_acquire>>  =>  (LDFMINNMAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAS),
     /* 179557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179561 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179563 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179567 */     GIR_RootConstrainSelectedInstOperands,
     /* 179568 */     // GIR_Coverage, 8050,
     /* 179568 */     GIR_EraseRootFromParent_Done,
     /* 179569 */   // Label 3253: @179569
     /* 179569 */   GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(179611), // Rule ID 8051 //
     /* 179574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179577 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 179580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179584 */     // MIs[0] Rn
     /* 179584 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179588 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179592 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179596 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_release>>  =>  (LDFMINNMLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLS),
     /* 179599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179601 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179603 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179605 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179609 */     GIR_RootConstrainSelectedInstOperands,
     /* 179610 */     // GIR_Coverage, 8051,
     /* 179610 */     GIR_EraseRootFromParent_Done,
     /* 179611 */   // Label 3254: @179611
     /* 179611 */   GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(179653), // Rule ID 8052 //
     /* 179616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179619 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 179622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179626 */     // MIs[0] Rn
     /* 179626 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179630 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179634 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179638 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_acq_rel>>  =>  (LDFMINNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALS),
     /* 179641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179645 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179647 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179651 */     GIR_RootConstrainSelectedInstOperands,
     /* 179652 */     // GIR_Coverage, 8052,
     /* 179652 */     GIR_EraseRootFromParent_Done,
     /* 179653 */   // Label 3255: @179653
     /* 179653 */   GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(179695), // Rule ID 8053 //
     /* 179658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179661 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 179664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179668 */     // MIs[0] Rn
     /* 179668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179672 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179676 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 179680 */     // (atomic_load_fmin:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmin_f32>><<P:Predicate_atomic_load_fmin_f32_seq_cst>>  =>  (LDFMINNMALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALS),
     /* 179683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179687 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179689 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179693 */     GIR_RootConstrainSelectedInstOperands,
     /* 179694 */     // GIR_Coverage, 8053,
     /* 179694 */     GIR_EraseRootFromParent_Done,
     /* 179695 */   // Label 3256: @179695
     /* 179695 */   GIM_Reject,
     /* 179696 */ // Label 3251: @179696
     /* 179696 */ GIM_Reject,
     /* 179697 */ // Label 3243: @179697
     /* 179697 */ GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(179923),
     /* 179702 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 179705 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 179712 */   GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(179754), // Rule ID 8054 //
     /* 179717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179720 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 179723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179727 */     // MIs[0] Rn
     /* 179727 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179731 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179739 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_monotonic>>  =>  (LDFMINNMD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMD),
     /* 179742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179746 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179748 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179752 */     GIR_RootConstrainSelectedInstOperands,
     /* 179753 */     // GIR_Coverage, 8054,
     /* 179753 */     GIR_EraseRootFromParent_Done,
     /* 179754 */   // Label 3258: @179754
     /* 179754 */   GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(179796), // Rule ID 8055 //
     /* 179759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179762 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 179765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179769 */     // MIs[0] Rn
     /* 179769 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179773 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179781 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_acquire>>  =>  (LDFMINNMAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMAD),
     /* 179784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179788 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179794 */     GIR_RootConstrainSelectedInstOperands,
     /* 179795 */     // GIR_Coverage, 8055,
     /* 179795 */     GIR_EraseRootFromParent_Done,
     /* 179796 */   // Label 3259: @179796
     /* 179796 */   GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(179838), // Rule ID 8056 //
     /* 179801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179804 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 179807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179811 */     // MIs[0] Rn
     /* 179811 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179823 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_release>>  =>  (LDFMINNMLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMLD),
     /* 179826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179830 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179832 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179836 */     GIR_RootConstrainSelectedInstOperands,
     /* 179837 */     // GIR_Coverage, 8056,
     /* 179837 */     GIR_EraseRootFromParent_Done,
     /* 179838 */   // Label 3260: @179838
     /* 179838 */   GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(179880), // Rule ID 8057 //
     /* 179843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179846 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 179849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179853 */     // MIs[0] Rn
     /* 179853 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179857 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179865 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_acq_rel>>  =>  (LDFMINNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALD),
     /* 179868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179872 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179874 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179878 */     GIR_RootConstrainSelectedInstOperands,
     /* 179879 */     // GIR_Coverage, 8057,
     /* 179879 */     GIR_EraseRootFromParent_Done,
     /* 179880 */   // Label 3261: @179880
     /* 179880 */   GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(179922), // Rule ID 8058 //
     /* 179885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179888 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 179891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179895 */     // MIs[0] Rn
     /* 179895 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179899 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179907 */     // (atomic_load_fmin:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmin_f64>><<P:Predicate_atomic_load_fmin_f64_seq_cst>>  =>  (LDFMINNMALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINNMALD),
     /* 179910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179914 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179916 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 179920 */     GIR_RootConstrainSelectedInstOperands,
     /* 179921 */     // GIR_Coverage, 8058,
     /* 179921 */     GIR_EraseRootFromParent_Done,
     /* 179922 */   // Label 3262: @179922
     /* 179922 */   GIM_Reject,
     /* 179923 */ // Label 3257: @179923
     /* 179923 */ GIM_Reject,
     /* 179924 */ // Label 3244: @179924
     /* 179924 */ GIM_Reject,
     /* 179925 */ // Label 40: @179925
     /* 179925 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 3266*/ GIMT_Encode4(180629),
     /* 179936 */ /*GILLT_s16*//*Label 3263*/ GIMT_Encode4(179948),
     /* 179940 */ /*GILLT_s32*//*Label 3264*/ GIMT_Encode4(180175),
     /* 179944 */ /*GILLT_s64*//*Label 3265*/ GIMT_Encode4(180402),
     /* 179948 */ // Label 3263: @179948
     /* 179948 */ GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(180174),
     /* 179953 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 179956 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 179963 */   GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(180005), // Rule ID 8059 //
     /* 179968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 179971 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 179974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179978 */     // MIs[0] Rn
     /* 179978 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 179982 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 179986 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 179990 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_monotonic>>  =>  (LDFMAXH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 179990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXH),
     /* 179993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 179995 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 179997 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 179999 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180003 */     GIR_RootConstrainSelectedInstOperands,
     /* 180004 */     // GIR_Coverage, 8059,
     /* 180004 */     GIR_EraseRootFromParent_Done,
     /* 180005 */   // Label 3268: @180005
     /* 180005 */   GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(180047), // Rule ID 8060 //
     /* 180010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180013 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 180016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180020 */     // MIs[0] Rn
     /* 180020 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180024 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180032 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_acquire>>  =>  (LDFMAXAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAH),
     /* 180035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180039 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180041 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180045 */     GIR_RootConstrainSelectedInstOperands,
     /* 180046 */     // GIR_Coverage, 8060,
     /* 180046 */     GIR_EraseRootFromParent_Done,
     /* 180047 */   // Label 3269: @180047
     /* 180047 */   GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(180089), // Rule ID 8061 //
     /* 180052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180055 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 180058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180062 */     // MIs[0] Rn
     /* 180062 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180066 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180074 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_release>>  =>  (LDFMAXLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLH),
     /* 180077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180079 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180081 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180087 */     GIR_RootConstrainSelectedInstOperands,
     /* 180088 */     // GIR_Coverage, 8061,
     /* 180088 */     GIR_EraseRootFromParent_Done,
     /* 180089 */   // Label 3270: @180089
     /* 180089 */   GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(180131), // Rule ID 8062 //
     /* 180094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180097 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 180100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180104 */     // MIs[0] Rn
     /* 180104 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180108 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180112 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180116 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_acq_rel>>  =>  (LDFMAXALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALH),
     /* 180119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180123 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180125 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180129 */     GIR_RootConstrainSelectedInstOperands,
     /* 180130 */     // GIR_Coverage, 8062,
     /* 180130 */     GIR_EraseRootFromParent_Done,
     /* 180131 */   // Label 3271: @180131
     /* 180131 */   GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(180173), // Rule ID 8063 //
     /* 180136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180139 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 180142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180146 */     // MIs[0] Rn
     /* 180146 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180150 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180158 */     // (atomic_load_fmaximum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f16>><<P:Predicate_atomic_load_fmaximum_f16_seq_cst>>  =>  (LDFMAXALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALH),
     /* 180161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180165 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180171 */     GIR_RootConstrainSelectedInstOperands,
     /* 180172 */     // GIR_Coverage, 8063,
     /* 180172 */     GIR_EraseRootFromParent_Done,
     /* 180173 */   // Label 3272: @180173
     /* 180173 */   GIM_Reject,
     /* 180174 */ // Label 3267: @180174
     /* 180174 */ GIM_Reject,
     /* 180175 */ // Label 3264: @180175
     /* 180175 */ GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(180401),
     /* 180180 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 180183 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 180190 */   GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(180232), // Rule ID 8064 //
     /* 180195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180198 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 180201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180205 */     // MIs[0] Rn
     /* 180205 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180213 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180217 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_monotonic>>  =>  (LDFMAXS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXS),
     /* 180220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180224 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180226 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180230 */     GIR_RootConstrainSelectedInstOperands,
     /* 180231 */     // GIR_Coverage, 8064,
     /* 180231 */     GIR_EraseRootFromParent_Done,
     /* 180232 */   // Label 3274: @180232
     /* 180232 */   GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(180274), // Rule ID 8065 //
     /* 180237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180240 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 180243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180247 */     // MIs[0] Rn
     /* 180247 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180251 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180259 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_acquire>>  =>  (LDFMAXAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAS),
     /* 180262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180266 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180268 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180272 */     GIR_RootConstrainSelectedInstOperands,
     /* 180273 */     // GIR_Coverage, 8065,
     /* 180273 */     GIR_EraseRootFromParent_Done,
     /* 180274 */   // Label 3275: @180274
     /* 180274 */   GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(180316), // Rule ID 8066 //
     /* 180279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180282 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 180285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180289 */     // MIs[0] Rn
     /* 180289 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180293 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180297 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180301 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_release>>  =>  (LDFMAXLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLS),
     /* 180304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180308 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180310 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180314 */     GIR_RootConstrainSelectedInstOperands,
     /* 180315 */     // GIR_Coverage, 8066,
     /* 180315 */     GIR_EraseRootFromParent_Done,
     /* 180316 */   // Label 3276: @180316
     /* 180316 */   GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(180358), // Rule ID 8067 //
     /* 180321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180324 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 180327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180331 */     // MIs[0] Rn
     /* 180331 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180343 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_acq_rel>>  =>  (LDFMAXALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALS),
     /* 180346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180350 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180352 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180356 */     GIR_RootConstrainSelectedInstOperands,
     /* 180357 */     // GIR_Coverage, 8067,
     /* 180357 */     GIR_EraseRootFromParent_Done,
     /* 180358 */   // Label 3277: @180358
     /* 180358 */   GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(180400), // Rule ID 8068 //
     /* 180363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180366 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 180369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180373 */     // MIs[0] Rn
     /* 180373 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180377 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180381 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180385 */     // (atomic_load_fmaximum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f32>><<P:Predicate_atomic_load_fmaximum_f32_seq_cst>>  =>  (LDFMAXALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALS),
     /* 180388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180392 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180394 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180398 */     GIR_RootConstrainSelectedInstOperands,
     /* 180399 */     // GIR_Coverage, 8068,
     /* 180399 */     GIR_EraseRootFromParent_Done,
     /* 180400 */   // Label 3278: @180400
     /* 180400 */   GIM_Reject,
     /* 180401 */ // Label 3273: @180401
     /* 180401 */ GIM_Reject,
     /* 180402 */ // Label 3265: @180402
     /* 180402 */ GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(180628),
     /* 180407 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 180410 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 180417 */   GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(180459), // Rule ID 8069 //
     /* 180422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180425 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 180428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180432 */     // MIs[0] Rn
     /* 180432 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180436 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180444 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_monotonic>>  =>  (LDFMAXD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXD),
     /* 180447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180451 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180453 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180457 */     GIR_RootConstrainSelectedInstOperands,
     /* 180458 */     // GIR_Coverage, 8069,
     /* 180458 */     GIR_EraseRootFromParent_Done,
     /* 180459 */   // Label 3280: @180459
     /* 180459 */   GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(180501), // Rule ID 8070 //
     /* 180464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180467 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 180470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180474 */     // MIs[0] Rn
     /* 180474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180486 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_acquire>>  =>  (LDFMAXAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXAD),
     /* 180489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180491 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180493 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180495 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180499 */     GIR_RootConstrainSelectedInstOperands,
     /* 180500 */     // GIR_Coverage, 8070,
     /* 180500 */     GIR_EraseRootFromParent_Done,
     /* 180501 */   // Label 3281: @180501
     /* 180501 */   GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(180543), // Rule ID 8071 //
     /* 180506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180509 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 180512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180516 */     // MIs[0] Rn
     /* 180516 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180520 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180524 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180528 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_release>>  =>  (LDFMAXLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXLD),
     /* 180531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180537 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180541 */     GIR_RootConstrainSelectedInstOperands,
     /* 180542 */     // GIR_Coverage, 8071,
     /* 180542 */     GIR_EraseRootFromParent_Done,
     /* 180543 */   // Label 3282: @180543
     /* 180543 */   GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(180585), // Rule ID 8072 //
     /* 180548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180551 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 180554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180558 */     // MIs[0] Rn
     /* 180558 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180566 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180570 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_acq_rel>>  =>  (LDFMAXALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALD),
     /* 180573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180577 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180579 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180583 */     GIR_RootConstrainSelectedInstOperands,
     /* 180584 */     // GIR_Coverage, 8072,
     /* 180584 */     GIR_EraseRootFromParent_Done,
     /* 180585 */   // Label 3283: @180585
     /* 180585 */   GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(180627), // Rule ID 8073 //
     /* 180590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180593 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 180596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180600 */     // MIs[0] Rn
     /* 180600 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180604 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180608 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180612 */     // (atomic_load_fmaximum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fmaximum_f64>><<P:Predicate_atomic_load_fmaximum_f64_seq_cst>>  =>  (LDFMAXALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMAXALD),
     /* 180615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180619 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180621 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180625 */     GIR_RootConstrainSelectedInstOperands,
     /* 180626 */     // GIR_Coverage, 8073,
     /* 180626 */     GIR_EraseRootFromParent_Done,
     /* 180627 */   // Label 3284: @180627
     /* 180627 */   GIM_Reject,
     /* 180628 */ // Label 3279: @180628
     /* 180628 */ GIM_Reject,
     /* 180629 */ // Label 3266: @180629
     /* 180629 */ GIM_Reject,
     /* 180630 */ // Label 41: @180630
     /* 180630 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 3288*/ GIMT_Encode4(181334),
     /* 180641 */ /*GILLT_s16*//*Label 3285*/ GIMT_Encode4(180653),
     /* 180645 */ /*GILLT_s32*//*Label 3286*/ GIMT_Encode4(180880),
     /* 180649 */ /*GILLT_s64*//*Label 3287*/ GIMT_Encode4(181107),
     /* 180653 */ // Label 3285: @180653
     /* 180653 */ GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(180879),
     /* 180658 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 180661 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 180668 */   GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(180710), // Rule ID 8074 //
     /* 180673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180676 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 180679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180683 */     // MIs[0] Rn
     /* 180683 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180687 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180695 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_monotonic>>  =>  (LDFMINH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINH),
     /* 180698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180702 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180708 */     GIR_RootConstrainSelectedInstOperands,
     /* 180709 */     // GIR_Coverage, 8074,
     /* 180709 */     GIR_EraseRootFromParent_Done,
     /* 180710 */   // Label 3290: @180710
     /* 180710 */   GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(180752), // Rule ID 8075 //
     /* 180715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180718 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 180721 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180725 */     // MIs[0] Rn
     /* 180725 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180737 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_acquire>>  =>  (LDFMINAH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAH),
     /* 180740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180744 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180746 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180750 */     GIR_RootConstrainSelectedInstOperands,
     /* 180751 */     // GIR_Coverage, 8075,
     /* 180751 */     GIR_EraseRootFromParent_Done,
     /* 180752 */   // Label 3291: @180752
     /* 180752 */   GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(180794), // Rule ID 8076 //
     /* 180757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180760 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 180763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180767 */     // MIs[0] Rn
     /* 180767 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180771 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180775 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180779 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_release>>  =>  (LDFMINLH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLH),
     /* 180782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180786 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180788 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180792 */     GIR_RootConstrainSelectedInstOperands,
     /* 180793 */     // GIR_Coverage, 8076,
     /* 180793 */     GIR_EraseRootFromParent_Done,
     /* 180794 */   // Label 3292: @180794
     /* 180794 */   GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(180836), // Rule ID 8077 //
     /* 180799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180802 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 180805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180809 */     // MIs[0] Rn
     /* 180809 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180813 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180821 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_acq_rel>>  =>  (LDFMINALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALH),
     /* 180824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180828 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180830 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180834 */     GIR_RootConstrainSelectedInstOperands,
     /* 180835 */     // GIR_Coverage, 8077,
     /* 180835 */     GIR_EraseRootFromParent_Done,
     /* 180836 */   // Label 3293: @180836
     /* 180836 */   GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(180878), // Rule ID 8078 //
     /* 180841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180844 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 180847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180851 */     // MIs[0] Rn
     /* 180851 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180855 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 180863 */     // (atomic_load_fminimum:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, FPR16:{ *:[f16] }:$Rm)<<P:Predicate_atomic_load_fminimum_f16>><<P:Predicate_atomic_load_fminimum_f16_seq_cst>>  =>  (LDFMINALH:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALH),
     /* 180866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180870 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180872 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180876 */     GIR_RootConstrainSelectedInstOperands,
     /* 180877 */     // GIR_Coverage, 8078,
     /* 180877 */     GIR_EraseRootFromParent_Done,
     /* 180878 */   // Label 3294: @180878
     /* 180878 */   GIM_Reject,
     /* 180879 */ // Label 3289: @180879
     /* 180879 */ GIM_Reject,
     /* 180880 */ // Label 3286: @180880
     /* 180880 */ GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(181106),
     /* 180885 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 180888 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 180895 */   GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(180937), // Rule ID 8079 //
     /* 180900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180903 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 180906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180910 */     // MIs[0] Rn
     /* 180910 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180914 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180918 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180922 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_monotonic>>  =>  (LDFMINS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINS),
     /* 180925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180929 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180931 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180935 */     GIR_RootConstrainSelectedInstOperands,
     /* 180936 */     // GIR_Coverage, 8079,
     /* 180936 */     GIR_EraseRootFromParent_Done,
     /* 180937 */   // Label 3296: @180937
     /* 180937 */   GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(180979), // Rule ID 8080 //
     /* 180942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180945 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 180948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180952 */     // MIs[0] Rn
     /* 180952 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180956 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 180960 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180964 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_acquire>>  =>  (LDFMINAS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 180964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAS),
     /* 180967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 180969 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 180971 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 180973 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 180977 */     GIR_RootConstrainSelectedInstOperands,
     /* 180978 */     // GIR_Coverage, 8080,
     /* 180978 */     GIR_EraseRootFromParent_Done,
     /* 180979 */   // Label 3297: @180979
     /* 180979 */   GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(181021), // Rule ID 8081 //
     /* 180984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 180987 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 180990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 180994 */     // MIs[0] Rn
     /* 180994 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 180998 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181006 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_release>>  =>  (LDFMINLS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLS),
     /* 181009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181013 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181015 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181019 */     GIR_RootConstrainSelectedInstOperands,
     /* 181020 */     // GIR_Coverage, 8081,
     /* 181020 */     GIR_EraseRootFromParent_Done,
     /* 181021 */   // Label 3298: @181021
     /* 181021 */   GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(181063), // Rule ID 8082 //
     /* 181026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181029 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 181032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181036 */     // MIs[0] Rn
     /* 181036 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181040 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181048 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_acq_rel>>  =>  (LDFMINALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALS),
     /* 181051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181055 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181057 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181061 */     GIR_RootConstrainSelectedInstOperands,
     /* 181062 */     // GIR_Coverage, 8082,
     /* 181062 */     GIR_EraseRootFromParent_Done,
     /* 181063 */   // Label 3299: @181063
     /* 181063 */   GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(181105), // Rule ID 8083 //
     /* 181068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181071 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 181074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181078 */     // MIs[0] Rn
     /* 181078 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181082 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181086 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181090 */     // (atomic_load_fminimum:{ *:[f32] } FPR64:{ *:[i64] }:$Rn, FPR32:{ *:[f32] }:$Rm)<<P:Predicate_atomic_load_fminimum_f32>><<P:Predicate_atomic_load_fminimum_f32_seq_cst>>  =>  (LDFMINALS:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALS),
     /* 181093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181097 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181099 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181103 */     GIR_RootConstrainSelectedInstOperands,
     /* 181104 */     // GIR_Coverage, 8083,
     /* 181104 */     GIR_EraseRootFromParent_Done,
     /* 181105 */   // Label 3300: @181105
     /* 181105 */   GIM_Reject,
     /* 181106 */ // Label 3295: @181106
     /* 181106 */ GIM_Reject,
     /* 181107 */ // Label 3287: @181107
     /* 181107 */ GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(181333),
     /* 181112 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 181115 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 181122 */   GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(181164), // Rule ID 8084 //
     /* 181127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181130 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Monotonic,
     /* 181133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181137 */     // MIs[0] Rn
     /* 181137 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181141 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181149 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_monotonic>>  =>  (LDFMIND:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMIND),
     /* 181152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181156 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181162 */     GIR_RootConstrainSelectedInstOperands,
     /* 181163 */     // GIR_Coverage, 8084,
     /* 181163 */     GIR_EraseRootFromParent_Done,
     /* 181164 */   // Label 3302: @181164
     /* 181164 */   GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(181206), // Rule ID 8085 //
     /* 181169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181172 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 181175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181179 */     // MIs[0] Rn
     /* 181179 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181183 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181187 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181191 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_acquire>>  =>  (LDFMINAD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINAD),
     /* 181194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181198 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181200 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181204 */     GIR_RootConstrainSelectedInstOperands,
     /* 181205 */     // GIR_Coverage, 8085,
     /* 181205 */     GIR_EraseRootFromParent_Done,
     /* 181206 */   // Label 3303: @181206
     /* 181206 */   GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(181248), // Rule ID 8086 //
     /* 181211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181214 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Release,
     /* 181217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181221 */     // MIs[0] Rn
     /* 181221 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181233 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_release>>  =>  (LDFMINLD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINLD),
     /* 181236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181240 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181242 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181246 */     GIR_RootConstrainSelectedInstOperands,
     /* 181247 */     // GIR_Coverage, 8086,
     /* 181247 */     GIR_EraseRootFromParent_Done,
     /* 181248 */   // Label 3304: @181248
     /* 181248 */   GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(181290), // Rule ID 8087 //
     /* 181253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181256 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::AcquireRelease,
     /* 181259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181263 */     // MIs[0] Rn
     /* 181263 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181267 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181275 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_acq_rel>>  =>  (LDFMINALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALD),
     /* 181278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181282 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181284 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181288 */     GIR_RootConstrainSelectedInstOperands,
     /* 181289 */     // GIR_Coverage, 8087,
     /* 181289 */     GIR_EraseRootFromParent_Done,
     /* 181290 */   // Label 3305: @181290
     /* 181290 */   GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(181332), // Rule ID 8088 //
     /* 181295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLSFE),
     /* 181298 */     GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::SequentiallyConsistent,
     /* 181301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181305 */     // MIs[0] Rn
     /* 181305 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 181309 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181313 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181317 */     // (atomic_load_fminimum:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[f64] }:$Rm)<<P:Predicate_atomic_load_fminimum_f64>><<P:Predicate_atomic_load_fminimum_f64_seq_cst>>  =>  (LDFMINALD:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[i64] }:$Rn)
     /* 181317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDFMINALD),
     /* 181320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 181322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 181324 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 181326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181330 */     GIR_RootConstrainSelectedInstOperands,
     /* 181331 */     // GIR_Coverage, 8088,
     /* 181331 */     GIR_EraseRootFromParent_Done,
     /* 181332 */   // Label 3306: @181332
     /* 181332 */   GIM_Reject,
     /* 181333 */ // Label 3301: @181333
     /* 181333 */ GIM_Reject,
     /* 181334 */ // Label 3288: @181334
     /* 181334 */ GIM_Reject,
     /* 181335 */ // Label 42: @181335
     /* 181335 */ GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(181362), // Rule ID 7674 //
     /* 181340 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181343 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/0, 4,
     /* 181347 */   // MIs[0] Operand 1
     /* 181347 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 181350 */   // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] }))  =>  (DMB 9:{ *:[i32] })
     /* 181350 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 181353 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 181356 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181360 */   GIR_RootConstrainSelectedInstOperands,
     /* 181361 */   // GIR_Coverage, 7674,
     /* 181361 */   GIR_EraseRootFromParent_Done,
     /* 181362 */ // Label 3307: @181362
     /* 181362 */ GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(181385), // Rule ID 7675 //
     /* 181367 */   // MIs[0] Operand 0
     /* 181367 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 181370 */   // MIs[0] Operand 1
     /* 181370 */   GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 181373 */   // (atomic_fence (timm:{ *:[iPTR] }), (timm:{ *:[iPTR] }))  =>  (DMB 11:{ *:[i32] })
     /* 181373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 181376 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
     /* 181379 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 181383 */   GIR_RootConstrainSelectedInstOperands,
     /* 181384 */   // GIR_Coverage, 7675,
     /* 181384 */   GIR_EraseRootFromParent_Done,
     /* 181385 */ // Label 3308: @181385
     /* 181385 */ GIM_Reject,
     /* 181386 */ // Label 43: @181386
     /* 181386 */ GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(196203),
     /* 181391 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 181394 */   GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(181485), // Rule ID 7140 //
     /* 181399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
     /* 181402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
     /* 181407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 181410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 181413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181417 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 181421 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 181425 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 181428 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
     /* 181433 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 181437 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 181441 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181446 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 181453 */     // (intrinsic_wo_chain:{ *:[v16i8] } 538:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 536:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESMCrrTied:{ *:[v16i8] } (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
     /* 181453 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 181456 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
     /* 181460 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 181465 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /* 181469 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
     /* 181473 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 181475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrrTied),
     /* 181478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181480 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 181483 */     GIR_RootConstrainSelectedInstOperands,
     /* 181484 */     // GIR_Coverage, 7140,
     /* 181484 */     GIR_EraseRootFromParent_Done,
     /* 181485 */   // Label 3310: @181485
     /* 181485 */   GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(181576), // Rule ID 7141 //
     /* 181490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFuseAES),
     /* 181493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
     /* 181498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 181501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 181504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181508 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 181512 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 181516 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 181519 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
     /* 181524 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 181528 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 181532 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181542 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 181544 */     // (intrinsic_wo_chain:{ *:[v16i8] } 537:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[v16i8] } 535:{ *:[iPTR] }, V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))  =>  (AESIMCrrTied:{ *:[v16i8] } (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$src1, V128:{ *:[v16i8] }:$src2))
     /* 181544 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 181547 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
     /* 181551 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 181556 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1
     /* 181560 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // src2
     /* 181564 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 181566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrrTied),
     /* 181569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181571 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 181574 */     GIR_RootConstrainSelectedInstOperands,
     /* 181575 */     // GIR_Coverage, 7141,
     /* 181575 */     GIR_EraseRootFromParent_Done,
     /* 181576 */   // Label 3311: @181576
     /* 181576 */   GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(181637), // Rule ID 4969 //
     /* 181581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvthf2fp),
     /* 181586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 181589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 181592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181596 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 181600 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 181604 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 181608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 181613 */     // MIs[1] Operand 2
     /* 181613 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 181624 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 181626 */     // (intrinsic_wo_chain:{ *:[v4f32] } 792:{ *:[iPTR] }, (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }))  =>  (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8i16] }:$Rn)
     /* 181626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 181629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 181635 */     GIR_RootConstrainSelectedInstOperands,
     /* 181636 */     // GIR_Coverage, 4969,
     /* 181636 */     GIR_EraseRootFromParent_Done,
     /* 181637 */   // Label 3312: @181637
     /* 181637 */   GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(181677), // Rule ID 2690 //
     /* 181642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 181645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntb),
     /* 181650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181657 */     // MIs[0] pattern
     /* 181657 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 181660 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 181665 */     // (intrinsic_wo_chain:{ *:[i64] } 1363:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTB_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 181665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTB_XPiI),
     /* 181668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181670 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 181672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 181675 */     GIR_RootConstrainSelectedInstOperands,
     /* 181676 */     // GIR_Coverage, 2690,
     /* 181676 */     GIR_EraseRootFromParent_Done,
     /* 181677 */   // Label 3313: @181677
     /* 181677 */   GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(181717), // Rule ID 10667 //
     /* 181682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 181685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnth),
     /* 181690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181697 */     // MIs[0] pattern
     /* 181697 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 181700 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 181705 */     // (intrinsic_wo_chain:{ *:[i64] } 1365:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTH_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 181705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTH_XPiI),
     /* 181708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181710 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 181712 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 181715 */     GIR_RootConstrainSelectedInstOperands,
     /* 181716 */     // GIR_Coverage, 10667,
     /* 181716 */     GIR_EraseRootFromParent_Done,
     /* 181717 */   // Label 3314: @181717
     /* 181717 */   GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(181757), // Rule ID 10670 //
     /* 181722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 181725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntw),
     /* 181730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181737 */     // MIs[0] pattern
     /* 181737 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 181740 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 181745 */     // (intrinsic_wo_chain:{ *:[i64] } 1371:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTW_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 181745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTW_XPiI),
     /* 181748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181750 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 181752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 181755 */     GIR_RootConstrainSelectedInstOperands,
     /* 181756 */     // GIR_Coverage, 10670,
     /* 181756 */     GIR_EraseRootFromParent_Done,
     /* 181757 */   // Label 3315: @181757
     /* 181757 */   GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(181797), // Rule ID 10673 //
     /* 181762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 181765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntd),
     /* 181770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181777 */     // MIs[0] pattern
     /* 181777 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 181780 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 181785 */     // (intrinsic_wo_chain:{ *:[i64] } 1364:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern)  =>  (CNTD_XPiI:{ *:[i64] } (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, 1:{ *:[i32] })
     /* 181785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTD_XPiI),
     /* 181788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181790 */     GIR_RootToRootCopy, /*OpIdx*/2, // pattern
     /* 181792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 181795 */     GIR_RootConstrainSelectedInstOperands,
     /* 181796 */     // GIR_Coverage, 10673,
     /* 181796 */     GIR_EraseRootFromParent_Done,
     /* 181797 */   // Label 3316: @181797
     /* 181797 */   GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(181836), // Rule ID 58 //
     /* 181802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasJS),
     /* 181805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_fjcvtzs),
     /* 181810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 181813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 181816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 181820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 181824 */     // (intrinsic_wo_chain:{ *:[i32] } 570:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FJCVTZS:{ *:[i32] }:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 181824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FJCVTZS),
     /* 181827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181831 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 181834 */     GIR_RootConstrainSelectedInstOperands,
     /* 181835 */     // GIR_Coverage, 58,
     /* 181835 */     GIR_EraseRootFromParent_Done,
     /* 181836 */   // Label 3317: @181836
     /* 181836 */   GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(181872), // Rule ID 340 //
     /* 181841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 181844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 181849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 181852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 181855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 181859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 181863 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 181863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
     /* 181866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181870 */     GIR_RootConstrainSelectedInstOperands,
     /* 181871 */     // GIR_Coverage, 340,
     /* 181871 */     GIR_EraseRootFromParent_Done,
     /* 181872 */   // Label 3318: @181872
     /* 181872 */   GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(181908), // Rule ID 341 //
     /* 181877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 181880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 181885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 181891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181895 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 181899 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 181899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 181902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181906 */     GIR_RootConstrainSelectedInstOperands,
     /* 181907 */     // GIR_Coverage, 341,
     /* 181907 */     GIR_EraseRootFromParent_Done,
     /* 181908 */   // Label 3319: @181908
     /* 181908 */   GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(181944), // Rule ID 342 //
     /* 181913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 181916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 181921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 181924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 181927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 181931 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181935 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 181935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 181938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181940 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181942 */     GIR_RootConstrainSelectedInstOperands,
     /* 181943 */     // GIR_Coverage, 342,
     /* 181943 */     GIR_EraseRootFromParent_Done,
     /* 181944 */   // Label 3320: @181944
     /* 181944 */   GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(181980), // Rule ID 343 //
     /* 181949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 181952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 181957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 181960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 181963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 181967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 181971 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 181971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 181974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 181976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 181978 */     GIR_RootConstrainSelectedInstOperands,
     /* 181979 */     // GIR_Coverage, 343,
     /* 181979 */     GIR_EraseRootFromParent_Done,
     /* 181980 */   // Label 3321: @181980
     /* 181980 */   GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(182016), // Rule ID 344 //
     /* 181985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 181988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 181993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 181996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 181999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182003 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182007 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 182007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 182010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182012 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182014 */     GIR_RootConstrainSelectedInstOperands,
     /* 182015 */     // GIR_Coverage, 344,
     /* 182015 */     GIR_EraseRootFromParent_Done,
     /* 182016 */   // Label 3322: @182016
     /* 182016 */   GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(182052), // Rule ID 345 //
     /* 182021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 182029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182043 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 182043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 182046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182050 */     GIR_RootConstrainSelectedInstOperands,
     /* 182051 */     // GIR_Coverage, 345,
     /* 182051 */     GIR_EraseRootFromParent_Done,
     /* 182052 */   // Label 3323: @182052
     /* 182052 */   GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(182088), // Rule ID 346 //
     /* 182057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182075 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182079 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 182079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWHr),
     /* 182082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182084 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182086 */     GIR_RootConstrainSelectedInstOperands,
     /* 182087 */     // GIR_Coverage, 346,
     /* 182087 */     GIR_EraseRootFromParent_Done,
     /* 182088 */   // Label 3324: @182088
     /* 182088 */   GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(182124), // Rule ID 347 //
     /* 182093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182101 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182115 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 182115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXHr),
     /* 182118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182120 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182122 */     GIR_RootConstrainSelectedInstOperands,
     /* 182123 */     // GIR_Coverage, 347,
     /* 182123 */     GIR_EraseRootFromParent_Done,
     /* 182124 */   // Label 3325: @182124
     /* 182124 */   GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(182160), // Rule ID 348 //
     /* 182129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182151 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 182151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
     /* 182154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182158 */     GIR_RootConstrainSelectedInstOperands,
     /* 182159 */     // GIR_Coverage, 348,
     /* 182159 */     GIR_EraseRootFromParent_Done,
     /* 182160 */   // Label 3326: @182160
     /* 182160 */   GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(182196), // Rule ID 349 //
     /* 182165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182183 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182187 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 182187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
     /* 182190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182194 */     GIR_RootConstrainSelectedInstOperands,
     /* 182195 */     // GIR_Coverage, 349,
     /* 182195 */     GIR_EraseRootFromParent_Done,
     /* 182196 */   // Label 3327: @182196
     /* 182196 */   GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(182232), // Rule ID 350 //
     /* 182201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182223 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 182223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
     /* 182226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182230 */     GIR_RootConstrainSelectedInstOperands,
     /* 182231 */     // GIR_Coverage, 350,
     /* 182231 */     GIR_EraseRootFromParent_Done,
     /* 182232 */   // Label 3328: @182232
     /* 182232 */   GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(182268), // Rule ID 351 //
     /* 182237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 182245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182259 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 182259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
     /* 182262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182266 */     GIR_RootConstrainSelectedInstOperands,
     /* 182267 */     // GIR_Coverage, 351,
     /* 182267 */     GIR_EraseRootFromParent_Done,
     /* 182268 */   // Label 3329: @182268
     /* 182268 */   GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(182304), // Rule ID 352 //
     /* 182273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182291 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182295 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 182295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWHr),
     /* 182298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182300 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182302 */     GIR_RootConstrainSelectedInstOperands,
     /* 182303 */     // GIR_Coverage, 352,
     /* 182303 */     GIR_EraseRootFromParent_Done,
     /* 182304 */   // Label 3330: @182304
     /* 182304 */   GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(182340), // Rule ID 353 //
     /* 182309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182327 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182331 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 182331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXHr),
     /* 182334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182336 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182338 */     GIR_RootConstrainSelectedInstOperands,
     /* 182339 */     // GIR_Coverage, 353,
     /* 182339 */     GIR_EraseRootFromParent_Done,
     /* 182340 */   // Label 3331: @182340
     /* 182340 */   GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(182376), // Rule ID 354 //
     /* 182345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182363 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182367 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 182367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
     /* 182370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182372 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182374 */     GIR_RootConstrainSelectedInstOperands,
     /* 182375 */     // GIR_Coverage, 354,
     /* 182375 */     GIR_EraseRootFromParent_Done,
     /* 182376 */   // Label 3332: @182376
     /* 182376 */   GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(182412), // Rule ID 355 //
     /* 182381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182403 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 182403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
     /* 182406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182410 */     GIR_RootConstrainSelectedInstOperands,
     /* 182411 */     // GIR_Coverage, 355,
     /* 182411 */     GIR_EraseRootFromParent_Done,
     /* 182412 */   // Label 3333: @182412
     /* 182412 */   GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(182448), // Rule ID 356 //
     /* 182417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182435 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182439 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 182439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
     /* 182442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182446 */     GIR_RootConstrainSelectedInstOperands,
     /* 182447 */     // GIR_Coverage, 356,
     /* 182447 */     GIR_EraseRootFromParent_Done,
     /* 182448 */   // Label 3334: @182448
     /* 182448 */   GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(182484), // Rule ID 357 //
     /* 182453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 182461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182471 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182475 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 182475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
     /* 182478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182482 */     GIR_RootConstrainSelectedInstOperands,
     /* 182483 */     // GIR_Coverage, 357,
     /* 182483 */     GIR_EraseRootFromParent_Done,
     /* 182484 */   // Label 3335: @182484
     /* 182484 */   GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(182520), // Rule ID 358 //
     /* 182489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182507 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182511 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 182511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWHr),
     /* 182514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182518 */     GIR_RootConstrainSelectedInstOperands,
     /* 182519 */     // GIR_Coverage, 358,
     /* 182519 */     GIR_EraseRootFromParent_Done,
     /* 182520 */   // Label 3336: @182520
     /* 182520 */   GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(182556), // Rule ID 359 //
     /* 182525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182547 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 182547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXHr),
     /* 182550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182554 */     GIR_RootConstrainSelectedInstOperands,
     /* 182555 */     // GIR_Coverage, 359,
     /* 182555 */     GIR_EraseRootFromParent_Done,
     /* 182556 */   // Label 3337: @182556
     /* 182556 */   GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(182592), // Rule ID 360 //
     /* 182561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182564 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182569 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182572 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182579 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182583 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 182583 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
     /* 182586 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182588 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182590 */     GIR_RootConstrainSelectedInstOperands,
     /* 182591 */     // GIR_Coverage, 360,
     /* 182591 */     GIR_EraseRootFromParent_Done,
     /* 182592 */   // Label 3338: @182592
     /* 182592 */   GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(182628), // Rule ID 361 //
     /* 182597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182600 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182605 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182608 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182619 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 182619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
     /* 182622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182624 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182626 */     GIR_RootConstrainSelectedInstOperands,
     /* 182627 */     // GIR_Coverage, 361,
     /* 182627 */     GIR_EraseRootFromParent_Done,
     /* 182628 */   // Label 3339: @182628
     /* 182628 */   GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(182664), // Rule ID 362 //
     /* 182633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182651 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182655 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 182655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
     /* 182658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182662 */     GIR_RootConstrainSelectedInstOperands,
     /* 182663 */     // GIR_Coverage, 362,
     /* 182663 */     GIR_EraseRootFromParent_Done,
     /* 182664 */   // Label 3340: @182664
     /* 182664 */   GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(182700), // Rule ID 363 //
     /* 182669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 182677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182687 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182691 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 182691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
     /* 182694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182698 */     GIR_RootConstrainSelectedInstOperands,
     /* 182699 */     // GIR_Coverage, 363,
     /* 182699 */     GIR_EraseRootFromParent_Done,
     /* 182700 */   // Label 3341: @182700
     /* 182700 */   GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(182736), // Rule ID 364 //
     /* 182705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182727 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 182727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWHr),
     /* 182730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182734 */     GIR_RootConstrainSelectedInstOperands,
     /* 182735 */     // GIR_Coverage, 364,
     /* 182735 */     GIR_EraseRootFromParent_Done,
     /* 182736 */   // Label 3342: @182736
     /* 182736 */   GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(182772), // Rule ID 365 //
     /* 182741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182759 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182763 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 182763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXHr),
     /* 182766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182770 */     GIR_RootConstrainSelectedInstOperands,
     /* 182771 */     // GIR_Coverage, 365,
     /* 182771 */     GIR_EraseRootFromParent_Done,
     /* 182772 */   // Label 3343: @182772
     /* 182772 */   GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(182808), // Rule ID 366 //
     /* 182777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182799 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 182799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWSr),
     /* 182802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182804 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182806 */     GIR_RootConstrainSelectedInstOperands,
     /* 182807 */     // GIR_Coverage, 366,
     /* 182807 */     GIR_EraseRootFromParent_Done,
     /* 182808 */   // Label 3344: @182808
     /* 182808 */   GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(182844), // Rule ID 367 //
     /* 182813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 182827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182831 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 182835 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 182835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXSr),
     /* 182838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182842 */     GIR_RootConstrainSelectedInstOperands,
     /* 182843 */     // GIR_Coverage, 367,
     /* 182843 */     GIR_EraseRootFromParent_Done,
     /* 182844 */   // Label 3345: @182844
     /* 182844 */   GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(182880), // Rule ID 368 //
     /* 182849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182867 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182871 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 182871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUWDr),
     /* 182874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182876 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182878 */     GIR_RootConstrainSelectedInstOperands,
     /* 182879 */     // GIR_Coverage, 368,
     /* 182879 */     GIR_EraseRootFromParent_Done,
     /* 182880 */   // Label 3346: @182880
     /* 182880 */   GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(182916), // Rule ID 369 //
     /* 182885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 182893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 182899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 182907 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 182907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSUXDr),
     /* 182910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182914 */     GIR_RootConstrainSelectedInstOperands,
     /* 182915 */     // GIR_Coverage, 369,
     /* 182915 */     GIR_EraseRootFromParent_Done,
     /* 182916 */   // Label 3347: @182916
     /* 182916 */   GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(182952), // Rule ID 370 //
     /* 182921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 182929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 182932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 182939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182943 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 182943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWHr),
     /* 182946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182948 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182950 */     GIR_RootConstrainSelectedInstOperands,
     /* 182951 */     // GIR_Coverage, 370,
     /* 182951 */     GIR_EraseRootFromParent_Done,
     /* 182952 */   // Label 3348: @182952
     /* 182952 */   GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(182988), // Rule ID 371 //
     /* 182957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 182960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 182965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 182968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 182971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 182975 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 182979 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 182979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXHr),
     /* 182982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 182984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 182986 */     GIR_RootConstrainSelectedInstOperands,
     /* 182987 */     // GIR_Coverage, 371,
     /* 182987 */     GIR_EraseRootFromParent_Done,
     /* 182988 */   // Label 3349: @182988
     /* 182988 */   GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(183024), // Rule ID 372 //
     /* 182993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 182996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 183001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183011 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183015 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 183015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWSr),
     /* 183018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183020 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183022 */     GIR_RootConstrainSelectedInstOperands,
     /* 183023 */     // GIR_Coverage, 372,
     /* 183023 */     GIR_EraseRootFromParent_Done,
     /* 183024 */   // Label 3350: @183024
     /* 183024 */   GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(183060), // Rule ID 373 //
     /* 183029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183032 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 183037 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183040 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183047 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183051 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXSr),
     /* 183054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183058 */     GIR_RootConstrainSelectedInstOperands,
     /* 183059 */     // GIR_Coverage, 373,
     /* 183059 */     GIR_EraseRootFromParent_Done,
     /* 183060 */   // Label 3351: @183060
     /* 183060 */   GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(183096), // Rule ID 374 //
     /* 183065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 183073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183087 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUWDr),
     /* 183090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183092 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183094 */     GIR_RootConstrainSelectedInstOperands,
     /* 183095 */     // GIR_Coverage, 374,
     /* 183095 */     GIR_EraseRootFromParent_Done,
     /* 183096 */   // Label 3352: @183096
     /* 183096 */   GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(183132), // Rule ID 375 //
     /* 183101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 183109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183123 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 183123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUUXDr),
     /* 183126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183130 */     GIR_RootConstrainSelectedInstOperands,
     /* 183131 */     // GIR_Coverage, 375,
     /* 183131 */     GIR_EraseRootFromParent_Done,
     /* 183132 */   // Label 3353: @183132
     /* 183132 */   GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(183168), // Rule ID 376 //
     /* 183137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 183140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183159 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 183159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWHr),
     /* 183162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183164 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183166 */     GIR_RootConstrainSelectedInstOperands,
     /* 183167 */     // GIR_Coverage, 376,
     /* 183167 */     GIR_EraseRootFromParent_Done,
     /* 183168 */   // Label 3354: @183168
     /* 183168 */   GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(183204), // Rule ID 377 //
     /* 183173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 183176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183191 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183195 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 183195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXHr),
     /* 183198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183202 */     GIR_RootConstrainSelectedInstOperands,
     /* 183203 */     // GIR_Coverage, 377,
     /* 183203 */     GIR_EraseRootFromParent_Done,
     /* 183204 */   // Label 3355: @183204
     /* 183204 */   GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(183240), // Rule ID 378 //
     /* 183209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183227 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183231 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 183231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
     /* 183234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183238 */     GIR_RootConstrainSelectedInstOperands,
     /* 183239 */     // GIR_Coverage, 378,
     /* 183239 */     GIR_EraseRootFromParent_Done,
     /* 183240 */   // Label 3356: @183240
     /* 183240 */   GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(183276), // Rule ID 379 //
     /* 183245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183263 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183267 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
     /* 183270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183274 */     GIR_RootConstrainSelectedInstOperands,
     /* 183275 */     // GIR_Coverage, 379,
     /* 183275 */     GIR_EraseRootFromParent_Done,
     /* 183276 */   // Label 3357: @183276
     /* 183276 */   GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(183312), // Rule ID 380 //
     /* 183281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183303 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
     /* 183306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183310 */     GIR_RootConstrainSelectedInstOperands,
     /* 183311 */     // GIR_Coverage, 380,
     /* 183311 */     GIR_EraseRootFromParent_Done,
     /* 183312 */   // Label 3358: @183312
     /* 183312 */   GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(183348), // Rule ID 381 //
     /* 183317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 183325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183335 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183339 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 183339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
     /* 183342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183346 */     GIR_RootConstrainSelectedInstOperands,
     /* 183347 */     // GIR_Coverage, 381,
     /* 183347 */     GIR_EraseRootFromParent_Done,
     /* 183348 */   // Label 3359: @183348
     /* 183348 */   GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(183384), // Rule ID 382 //
     /* 183353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 183356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183371 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183375 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 183375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWHr),
     /* 183378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183380 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183382 */     GIR_RootConstrainSelectedInstOperands,
     /* 183383 */     // GIR_Coverage, 382,
     /* 183383 */     GIR_EraseRootFromParent_Done,
     /* 183384 */   // Label 3360: @183384
     /* 183384 */   GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(183420), // Rule ID 383 //
     /* 183389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 183392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183411 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 183411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXHr),
     /* 183414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183418 */     GIR_RootConstrainSelectedInstOperands,
     /* 183419 */     // GIR_Coverage, 383,
     /* 183419 */     GIR_EraseRootFromParent_Done,
     /* 183420 */   // Label 3361: @183420
     /* 183420 */   GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(183456), // Rule ID 384 //
     /* 183425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183447 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 183447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
     /* 183450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183454 */     GIR_RootConstrainSelectedInstOperands,
     /* 183455 */     // GIR_Coverage, 384,
     /* 183455 */     GIR_EraseRootFromParent_Done,
     /* 183456 */   // Label 3362: @183456
     /* 183456 */   GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(183492), // Rule ID 385 //
     /* 183461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183483 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
     /* 183486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183490 */     GIR_RootConstrainSelectedInstOperands,
     /* 183491 */     // GIR_Coverage, 385,
     /* 183491 */     GIR_EraseRootFromParent_Done,
     /* 183492 */   // Label 3363: @183492
     /* 183492 */   GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(183528), // Rule ID 386 //
     /* 183497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 183515 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183519 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
     /* 183522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183526 */     GIR_RootConstrainSelectedInstOperands,
     /* 183527 */     // GIR_Coverage, 386,
     /* 183527 */     GIR_EraseRootFromParent_Done,
     /* 183528 */   // Label 3364: @183528
     /* 183528 */   GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(183564), // Rule ID 387 //
     /* 183533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 183536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 183541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 183551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183555 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 183555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
     /* 183558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183562 */     GIR_RootConstrainSelectedInstOperands,
     /* 183563 */     // GIR_Coverage, 387,
     /* 183563 */     GIR_EraseRootFromParent_Done,
     /* 183564 */   // Label 3365: @183564
     /* 183564 */   GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(183600), // Rule ID 436 //
     /* 183569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 183577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183591 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 183594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183596 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183598 */     GIR_RootConstrainSelectedInstOperands,
     /* 183599 */     // GIR_Coverage, 436,
     /* 183599 */     GIR_EraseRootFromParent_Done,
     /* 183600 */   // Label 3366: @183600
     /* 183600 */   GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(183636), // Rule ID 437 //
     /* 183605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 183613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183623 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183627 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 183627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSHr),
     /* 183630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183634 */     GIR_RootConstrainSelectedInstOperands,
     /* 183635 */     // GIR_Coverage, 437,
     /* 183635 */     GIR_EraseRootFromParent_Done,
     /* 183636 */   // Label 3367: @183636
     /* 183636 */   GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(183672), // Rule ID 438 //
     /* 183641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 183649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183659 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183663 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 183663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 183666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183668 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183670 */     GIR_RootConstrainSelectedInstOperands,
     /* 183671 */     // GIR_Coverage, 438,
     /* 183671 */     GIR_EraseRootFromParent_Done,
     /* 183672 */   // Label 3368: @183672
     /* 183672 */   GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(183708), // Rule ID 439 //
     /* 183677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 183685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183699 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 183702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183704 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183706 */     GIR_RootConstrainSelectedInstOperands,
     /* 183707 */     // GIR_Coverage, 439,
     /* 183707 */     GIR_EraseRootFromParent_Done,
     /* 183708 */   // Label 3369: @183708
     /* 183708 */   GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(183744), // Rule ID 440 //
     /* 183713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 183721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183735 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSDr),
     /* 183738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183742 */     GIR_RootConstrainSelectedInstOperands,
     /* 183743 */     // GIR_Coverage, 440,
     /* 183743 */     GIR_EraseRootFromParent_Done,
     /* 183744 */   // Label 3370: @183744
     /* 183744 */   GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(183780), // Rule ID 441 //
     /* 183749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 183757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183767 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183771 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 183771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSHr),
     /* 183774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183778 */     GIR_RootConstrainSelectedInstOperands,
     /* 183779 */     // GIR_Coverage, 441,
     /* 183779 */     GIR_EraseRootFromParent_Done,
     /* 183780 */   // Label 3371: @183780
     /* 183780 */   GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(183816), // Rule ID 442 //
     /* 183785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183788 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 183793 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183803 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183807 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 183807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDHr),
     /* 183810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183814 */     GIR_RootConstrainSelectedInstOperands,
     /* 183815 */     // GIR_Coverage, 442,
     /* 183815 */     GIR_EraseRootFromParent_Done,
     /* 183816 */   // Label 3372: @183816
     /* 183816 */   GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(183852), // Rule ID 443 //
     /* 183821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183824 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 183829 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183843 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDSr),
     /* 183846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183848 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183850 */     GIR_RootConstrainSelectedInstOperands,
     /* 183851 */     // GIR_Coverage, 443,
     /* 183851 */     GIR_EraseRootFromParent_Done,
     /* 183852 */   // Label 3373: @183852
     /* 183852 */   GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(183888), // Rule ID 444 //
     /* 183857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 183865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 183871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183879 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 183879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSDr),
     /* 183882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183886 */     GIR_RootConstrainSelectedInstOperands,
     /* 183887 */     // GIR_Coverage, 444,
     /* 183887 */     GIR_EraseRootFromParent_Done,
     /* 183888 */   // Label 3374: @183888
     /* 183888 */   GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(183924), // Rule ID 445 //
     /* 183893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 183901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 183904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183911 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183915 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 183915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSHr),
     /* 183918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183922 */     GIR_RootConstrainSelectedInstOperands,
     /* 183923 */     // GIR_Coverage, 445,
     /* 183923 */     GIR_EraseRootFromParent_Done,
     /* 183924 */   // Label 3375: @183924
     /* 183924 */   GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(183960), // Rule ID 446 //
     /* 183929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 183937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 183943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183947 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 183951 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 183951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDHr),
     /* 183954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183958 */     GIR_RootConstrainSelectedInstOperands,
     /* 183959 */     // GIR_Coverage, 446,
     /* 183959 */     GIR_EraseRootFromParent_Done,
     /* 183960 */   // Label 3376: @183960
     /* 183960 */   GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(183996), // Rule ID 447 //
     /* 183965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 183968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 183973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 183976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 183979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 183983 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 183987 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 183987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDSr),
     /* 183990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 183992 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 183994 */     GIR_RootConstrainSelectedInstOperands,
     /* 183995 */     // GIR_Coverage, 447,
     /* 183995 */     GIR_EraseRootFromParent_Done,
     /* 183996 */   // Label 3377: @183996
     /* 183996 */   GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(184032), // Rule ID 448 //
     /* 184001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 184009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184019 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184023 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 184023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSDr),
     /* 184026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184030 */     GIR_RootConstrainSelectedInstOperands,
     /* 184031 */     // GIR_Coverage, 448,
     /* 184031 */     GIR_EraseRootFromParent_Done,
     /* 184032 */   // Label 3378: @184032
     /* 184032 */   GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(184068), // Rule ID 449 //
     /* 184037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 184045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184055 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184059 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 184059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSHr),
     /* 184062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184066 */     GIR_RootConstrainSelectedInstOperands,
     /* 184067 */     // GIR_Coverage, 449,
     /* 184067 */     GIR_EraseRootFromParent_Done,
     /* 184068 */   // Label 3379: @184068
     /* 184068 */   GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(184104), // Rule ID 450 //
     /* 184073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 184081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184091 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184095 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 184095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDHr),
     /* 184098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184102 */     GIR_RootConstrainSelectedInstOperands,
     /* 184103 */     // GIR_Coverage, 450,
     /* 184103 */     GIR_EraseRootFromParent_Done,
     /* 184104 */   // Label 3380: @184104
     /* 184104 */   GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(184140), // Rule ID 451 //
     /* 184109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 184117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184127 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184131 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 184131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDSr),
     /* 184134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184138 */     GIR_RootConstrainSelectedInstOperands,
     /* 184139 */     // GIR_Coverage, 451,
     /* 184139 */     GIR_EraseRootFromParent_Done,
     /* 184140 */   // Label 3381: @184140
     /* 184140 */   GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(184176), // Rule ID 452 //
     /* 184145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184148 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 184153 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184156 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184163 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184167 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 184167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSSDr),
     /* 184170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184174 */     GIR_RootConstrainSelectedInstOperands,
     /* 184175 */     // GIR_Coverage, 452,
     /* 184175 */     GIR_EraseRootFromParent_Done,
     /* 184176 */   // Label 3382: @184176
     /* 184176 */   GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(184212), // Rule ID 453 //
     /* 184181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 184189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184199 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184203 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 184203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSSHr),
     /* 184206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184210 */     GIR_RootConstrainSelectedInstOperands,
     /* 184211 */     // GIR_Coverage, 453,
     /* 184211 */     GIR_EraseRootFromParent_Done,
     /* 184212 */   // Label 3383: @184212
     /* 184212 */   GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(184248), // Rule ID 454 //
     /* 184217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 184225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184239 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 184239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSDHr),
     /* 184242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184244 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184246 */     GIR_RootConstrainSelectedInstOperands,
     /* 184247 */     // GIR_Coverage, 454,
     /* 184247 */     GIR_EraseRootFromParent_Done,
     /* 184248 */   // Label 3384: @184248
     /* 184248 */   GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(184284), // Rule ID 455 //
     /* 184253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 184261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184275 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 184275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSDSr),
     /* 184278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184282 */     GIR_RootConstrainSelectedInstOperands,
     /* 184283 */     // GIR_Coverage, 455,
     /* 184283 */     GIR_EraseRootFromParent_Done,
     /* 184284 */   // Label 3385: @184284
     /* 184284 */   GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(184320), // Rule ID 456 //
     /* 184289 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184292 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 184297 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184307 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184311 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 184311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUSDr),
     /* 184314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184316 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184318 */     GIR_RootConstrainSelectedInstOperands,
     /* 184319 */     // GIR_Coverage, 456,
     /* 184319 */     GIR_EraseRootFromParent_Done,
     /* 184320 */   // Label 3386: @184320
     /* 184320 */   GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(184356), // Rule ID 457 //
     /* 184325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 184333 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184336 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184347 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 184347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUSHr),
     /* 184350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184352 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184354 */     GIR_RootConstrainSelectedInstOperands,
     /* 184355 */     // GIR_Coverage, 457,
     /* 184355 */     GIR_EraseRootFromParent_Done,
     /* 184356 */   // Label 3387: @184356
     /* 184356 */   GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(184392), // Rule ID 458 //
     /* 184361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 184369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184383 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 184383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUDHr),
     /* 184386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184390 */     GIR_RootConstrainSelectedInstOperands,
     /* 184391 */     // GIR_Coverage, 458,
     /* 184391 */     GIR_EraseRootFromParent_Done,
     /* 184392 */   // Label 3388: @184392
     /* 184392 */   GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(184428), // Rule ID 459 //
     /* 184397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 184405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184419 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 184419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUDSr),
     /* 184422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184426 */     GIR_RootConstrainSelectedInstOperands,
     /* 184427 */     // GIR_Coverage, 459,
     /* 184427 */     GIR_EraseRootFromParent_Done,
     /* 184428 */   // Label 3389: @184428
     /* 184428 */   GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(184464), // Rule ID 460 //
     /* 184433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 184441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184451 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184455 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 184455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSDr),
     /* 184458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184460 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184462 */     GIR_RootConstrainSelectedInstOperands,
     /* 184463 */     // GIR_Coverage, 460,
     /* 184463 */     GIR_EraseRootFromParent_Done,
     /* 184464 */   // Label 3390: @184464
     /* 184464 */   GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(184500), // Rule ID 461 //
     /* 184469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 184477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184487 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184491 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 184491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSHr),
     /* 184494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184498 */     GIR_RootConstrainSelectedInstOperands,
     /* 184499 */     // GIR_Coverage, 461,
     /* 184499 */     GIR_EraseRootFromParent_Done,
     /* 184500 */   // Label 3391: @184500
     /* 184500 */   GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(184536), // Rule ID 462 //
     /* 184505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 184513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184527 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 184527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDHr),
     /* 184530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184534 */     GIR_RootConstrainSelectedInstOperands,
     /* 184535 */     // GIR_Coverage, 462,
     /* 184535 */     GIR_EraseRootFromParent_Done,
     /* 184536 */   // Label 3392: @184536
     /* 184536 */   GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(184572), // Rule ID 463 //
     /* 184541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 184549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184559 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184563 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 184563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDSr),
     /* 184566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184570 */     GIR_RootConstrainSelectedInstOperands,
     /* 184571 */     // GIR_Coverage, 463,
     /* 184571 */     GIR_EraseRootFromParent_Done,
     /* 184572 */   // Label 3393: @184572
     /* 184572 */   GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(184608), // Rule ID 464 //
     /* 184577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 184585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184599 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 184599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSDr),
     /* 184602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184606 */     GIR_RootConstrainSelectedInstOperands,
     /* 184607 */     // GIR_Coverage, 464,
     /* 184607 */     GIR_EraseRootFromParent_Done,
     /* 184608 */   // Label 3394: @184608
     /* 184608 */   GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(184644), // Rule ID 465 //
     /* 184613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 184621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184631 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184635 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 184635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSHr),
     /* 184638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184642 */     GIR_RootConstrainSelectedInstOperands,
     /* 184643 */     // GIR_Coverage, 465,
     /* 184643 */     GIR_EraseRootFromParent_Done,
     /* 184644 */   // Label 3395: @184644
     /* 184644 */   GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(184680), // Rule ID 466 //
     /* 184649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 184657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 184663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184667 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 184671 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 184671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDHr),
     /* 184674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184678 */     GIR_RootConstrainSelectedInstOperands,
     /* 184679 */     // GIR_Coverage, 466,
     /* 184679 */     GIR_EraseRootFromParent_Done,
     /* 184680 */   // Label 3396: @184680
     /* 184680 */   GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(184716), // Rule ID 467 //
     /* 184685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 184688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 184693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184703 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184707 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 184707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDSr),
     /* 184710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184714 */     GIR_RootConstrainSelectedInstOperands,
     /* 184715 */     // GIR_Coverage, 467,
     /* 184715 */     GIR_EraseRootFromParent_Done,
     /* 184716 */   // Label 3397: @184716
     /* 184716 */   GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(184752), // Rule ID 617 //
     /* 184721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
     /* 184729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184739 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184743 */     // (intrinsic_wo_chain:{ *:[f32] } 572:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT32ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 184743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZSr),
     /* 184746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184748 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184750 */     GIR_RootConstrainSelectedInstOperands,
     /* 184751 */     // GIR_Coverage, 617,
     /* 184751 */     GIR_EraseRootFromParent_Done,
     /* 184752 */   // Label 3398: @184752
     /* 184752 */   GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(184788), // Rule ID 618 //
     /* 184757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32z),
     /* 184765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184775 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184779 */     // (intrinsic_wo_chain:{ *:[f64] } 572:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT32ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 184779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
     /* 184782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184786 */     GIR_RootConstrainSelectedInstOperands,
     /* 184787 */     // GIR_Coverage, 618,
     /* 184787 */     GIR_EraseRootFromParent_Done,
     /* 184788 */   // Label 3399: @184788
     /* 184788 */   GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(184824), // Rule ID 619 //
     /* 184793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
     /* 184801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184811 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184815 */     // (intrinsic_wo_chain:{ *:[f32] } 574:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT64ZSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 184815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZSr),
     /* 184818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184822 */     GIR_RootConstrainSelectedInstOperands,
     /* 184823 */     // GIR_Coverage, 619,
     /* 184823 */     GIR_EraseRootFromParent_Done,
     /* 184824 */   // Label 3400: @184824
     /* 184824 */   GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(184860), // Rule ID 620 //
     /* 184829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64z),
     /* 184837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184847 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184851 */     // (intrinsic_wo_chain:{ *:[f64] } 574:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT64ZDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 184851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
     /* 184854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184858 */     GIR_RootConstrainSelectedInstOperands,
     /* 184859 */     // GIR_Coverage, 620,
     /* 184859 */     GIR_EraseRootFromParent_Done,
     /* 184860 */   // Label 3401: @184860
     /* 184860 */   GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(184896), // Rule ID 621 //
     /* 184865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
     /* 184873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184883 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184887 */     // (intrinsic_wo_chain:{ *:[f32] } 571:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT32XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 184887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XSr),
     /* 184890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184894 */     GIR_RootConstrainSelectedInstOperands,
     /* 184895 */     // GIR_Coverage, 621,
     /* 184895 */     GIR_EraseRootFromParent_Done,
     /* 184896 */   // Label 3402: @184896
     /* 184896 */   GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(184932), // Rule ID 622 //
     /* 184901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint32x),
     /* 184909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184919 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184923 */     // (intrinsic_wo_chain:{ *:[f64] } 571:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT32XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 184923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
     /* 184926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184930 */     GIR_RootConstrainSelectedInstOperands,
     /* 184931 */     // GIR_Coverage, 622,
     /* 184931 */     GIR_EraseRootFromParent_Done,
     /* 184932 */   // Label 3403: @184932
     /* 184932 */   GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(184968), // Rule ID 623 //
     /* 184937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184940 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
     /* 184945 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 184948 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 184951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 184959 */     // (intrinsic_wo_chain:{ *:[f32] } 573:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRINT64XSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 184959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XSr),
     /* 184962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 184964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 184966 */     GIR_RootConstrainSelectedInstOperands,
     /* 184967 */     // GIR_Coverage, 623,
     /* 184967 */     GIR_EraseRootFromParent_Done,
     /* 184968 */   // Label 3404: @184968
     /* 184968 */   GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(185004), // Rule ID 624 //
     /* 184973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 184976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_frint64x),
     /* 184981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 184984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 184987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184991 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 184995 */     // (intrinsic_wo_chain:{ *:[f64] } 573:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRINT64XDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 184995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
     /* 184998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185000 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185002 */     GIR_RootConstrainSelectedInstOperands,
     /* 185003 */     // GIR_Coverage, 624,
     /* 185003 */     GIR_EraseRootFromParent_Done,
     /* 185004 */   // Label 3405: @185004
     /* 185004 */   GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(185040), // Rule ID 740 //
     /* 185009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 185020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 185023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185027 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185031 */     // (intrinsic_wo_chain:{ *:[v8i8] } 599:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (CLSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 185031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i8),
     /* 185034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185038 */     GIR_RootConstrainSelectedInstOperands,
     /* 185039 */     // GIR_Coverage, 740,
     /* 185039 */     GIR_EraseRootFromParent_Done,
     /* 185040 */   // Label 3406: @185040
     /* 185040 */   GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(185076), // Rule ID 741 //
     /* 185045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185053 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 185056 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 185059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185067 */     // (intrinsic_wo_chain:{ *:[v16i8] } 599:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (CLSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 185067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv16i8),
     /* 185070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185074 */     GIR_RootConstrainSelectedInstOperands,
     /* 185075 */     // GIR_Coverage, 741,
     /* 185075 */     GIR_EraseRootFromParent_Done,
     /* 185076 */   // Label 3407: @185076
     /* 185076 */   GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(185112), // Rule ID 742 //
     /* 185081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185099 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185103 */     // (intrinsic_wo_chain:{ *:[v4i16] } 599:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (CLSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 185103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i16),
     /* 185106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185110 */     GIR_RootConstrainSelectedInstOperands,
     /* 185111 */     // GIR_Coverage, 742,
     /* 185111 */     GIR_EraseRootFromParent_Done,
     /* 185112 */   // Label 3408: @185112
     /* 185112 */   GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(185148), // Rule ID 743 //
     /* 185117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185139 */     // (intrinsic_wo_chain:{ *:[v8i16] } 599:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (CLSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 185139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv8i16),
     /* 185142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185146 */     GIR_RootConstrainSelectedInstOperands,
     /* 185147 */     // GIR_Coverage, 743,
     /* 185147 */     GIR_EraseRootFromParent_Done,
     /* 185148 */   // Label 3409: @185148
     /* 185148 */   GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(185184), // Rule ID 744 //
     /* 185153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 185164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 185167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185175 */     // (intrinsic_wo_chain:{ *:[v2i32] } 599:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (CLSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 185175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv2i32),
     /* 185178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185182 */     GIR_RootConstrainSelectedInstOperands,
     /* 185183 */     // GIR_Coverage, 744,
     /* 185183 */     GIR_EraseRootFromParent_Done,
     /* 185184 */   // Label 3410: @185184
     /* 185184 */   GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(185220), // Rule ID 745 //
     /* 185189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_cls),
     /* 185197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 185200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 185203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185207 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185211 */     // (intrinsic_wo_chain:{ *:[v4i32] } 599:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (CLSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 185211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSv4i32),
     /* 185214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185218 */     GIR_RootConstrainSelectedInstOperands,
     /* 185219 */     // GIR_Coverage, 745,
     /* 185219 */     GIR_EraseRootFromParent_Done,
     /* 185220 */   // Label 3411: @185220
     /* 185220 */   GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(185256), // Rule ID 826 //
     /* 185225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 185233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185243 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185247 */     // (intrinsic_wo_chain:{ *:[v4i16] } 607:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTASv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 185247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f16),
     /* 185250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185254 */     GIR_RootConstrainSelectedInstOperands,
     /* 185255 */     // GIR_Coverage, 826,
     /* 185255 */     GIR_EraseRootFromParent_Done,
     /* 185256 */   // Label 3412: @185256
     /* 185256 */   GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(185292), // Rule ID 827 //
     /* 185261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 185269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185272 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185279 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185283 */     // (intrinsic_wo_chain:{ *:[v8i16] } 607:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTASv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 185283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv8f16),
     /* 185286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185290 */     GIR_RootConstrainSelectedInstOperands,
     /* 185291 */     // GIR_Coverage, 827,
     /* 185291 */     GIR_EraseRootFromParent_Done,
     /* 185292 */   // Label 3413: @185292
     /* 185292 */   GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(185328), // Rule ID 828 //
     /* 185297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 185305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 185308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 185311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185319 */     // (intrinsic_wo_chain:{ *:[v2i32] } 607:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTASv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 185319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f32),
     /* 185322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185326 */     GIR_RootConstrainSelectedInstOperands,
     /* 185327 */     // GIR_Coverage, 828,
     /* 185327 */     GIR_EraseRootFromParent_Done,
     /* 185328 */   // Label 3414: @185328
     /* 185328 */   GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(185364), // Rule ID 829 //
     /* 185333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 185341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 185344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 185347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185355 */     // (intrinsic_wo_chain:{ *:[v4i32] } 607:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTASv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 185355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv4f32),
     /* 185358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185362 */     GIR_RootConstrainSelectedInstOperands,
     /* 185363 */     // GIR_Coverage, 829,
     /* 185363 */     GIR_EraseRootFromParent_Done,
     /* 185364 */   // Label 3415: @185364
     /* 185364 */   GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(185400), // Rule ID 830 //
     /* 185369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 185377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 185380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 185383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185387 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185391 */     // (intrinsic_wo_chain:{ *:[v2i64] } 607:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTASv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 185391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv2f64),
     /* 185394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185398 */     GIR_RootConstrainSelectedInstOperands,
     /* 185399 */     // GIR_Coverage, 830,
     /* 185399 */     GIR_EraseRootFromParent_Done,
     /* 185400 */   // Label 3416: @185400
     /* 185400 */   GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(185436), // Rule ID 831 //
     /* 185405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 185413 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185416 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185427 */     // (intrinsic_wo_chain:{ *:[v4i16] } 608:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTAUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 185427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f16),
     /* 185430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185434 */     GIR_RootConstrainSelectedInstOperands,
     /* 185435 */     // GIR_Coverage, 831,
     /* 185435 */     GIR_EraseRootFromParent_Done,
     /* 185436 */   // Label 3417: @185436
     /* 185436 */   GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(185472), // Rule ID 832 //
     /* 185441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 185449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185463 */     // (intrinsic_wo_chain:{ *:[v8i16] } 608:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTAUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 185463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv8f16),
     /* 185466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185470 */     GIR_RootConstrainSelectedInstOperands,
     /* 185471 */     // GIR_Coverage, 832,
     /* 185471 */     GIR_EraseRootFromParent_Done,
     /* 185472 */   // Label 3418: @185472
     /* 185472 */   GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(185508), // Rule ID 833 //
     /* 185477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 185485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 185488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 185491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185495 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185499 */     // (intrinsic_wo_chain:{ *:[v2i32] } 608:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTAUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 185499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f32),
     /* 185502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185506 */     GIR_RootConstrainSelectedInstOperands,
     /* 185507 */     // GIR_Coverage, 833,
     /* 185507 */     GIR_EraseRootFromParent_Done,
     /* 185508 */   // Label 3419: @185508
     /* 185508 */   GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(185544), // Rule ID 834 //
     /* 185513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 185521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 185524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 185527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185535 */     // (intrinsic_wo_chain:{ *:[v4i32] } 608:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTAUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 185535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv4f32),
     /* 185538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185542 */     GIR_RootConstrainSelectedInstOperands,
     /* 185543 */     // GIR_Coverage, 834,
     /* 185543 */     GIR_EraseRootFromParent_Done,
     /* 185544 */   // Label 3420: @185544
     /* 185544 */   GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(185580), // Rule ID 835 //
     /* 185549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 185557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 185560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 185563 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185567 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185571 */     // (intrinsic_wo_chain:{ *:[v2i64] } 608:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTAUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 185571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv2f64),
     /* 185574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185578 */     GIR_RootConstrainSelectedInstOperands,
     /* 185579 */     // GIR_Coverage, 835,
     /* 185579 */     GIR_EraseRootFromParent_Done,
     /* 185580 */   // Label 3421: @185580
     /* 185580 */   GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(185616), // Rule ID 836 //
     /* 185585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185588 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 185593 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185596 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185603 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185607 */     // (intrinsic_wo_chain:{ *:[v4i16] } 609:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTMSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 185607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f16),
     /* 185610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185614 */     GIR_RootConstrainSelectedInstOperands,
     /* 185615 */     // GIR_Coverage, 836,
     /* 185615 */     GIR_EraseRootFromParent_Done,
     /* 185616 */   // Label 3422: @185616
     /* 185616 */   GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(185652), // Rule ID 837 //
     /* 185621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 185629 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185632 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185639 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185643 */     // (intrinsic_wo_chain:{ *:[v8i16] } 609:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTMSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 185643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv8f16),
     /* 185646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185650 */     GIR_RootConstrainSelectedInstOperands,
     /* 185651 */     // GIR_Coverage, 837,
     /* 185651 */     GIR_EraseRootFromParent_Done,
     /* 185652 */   // Label 3423: @185652
     /* 185652 */   GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(185688), // Rule ID 838 //
     /* 185657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 185665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 185668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 185671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185675 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185679 */     // (intrinsic_wo_chain:{ *:[v2i32] } 609:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTMSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 185679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f32),
     /* 185682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185684 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185686 */     GIR_RootConstrainSelectedInstOperands,
     /* 185687 */     // GIR_Coverage, 838,
     /* 185687 */     GIR_EraseRootFromParent_Done,
     /* 185688 */   // Label 3424: @185688
     /* 185688 */   GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(185724), // Rule ID 839 //
     /* 185693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 185701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 185704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 185707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185711 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185715 */     // (intrinsic_wo_chain:{ *:[v4i32] } 609:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTMSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 185715 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv4f32),
     /* 185718 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185720 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185722 */     GIR_RootConstrainSelectedInstOperands,
     /* 185723 */     // GIR_Coverage, 839,
     /* 185723 */     GIR_EraseRootFromParent_Done,
     /* 185724 */   // Label 3425: @185724
     /* 185724 */   GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(185760), // Rule ID 840 //
     /* 185729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 185737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 185740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 185743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185747 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185751 */     // (intrinsic_wo_chain:{ *:[v2i64] } 609:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTMSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 185751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv2f64),
     /* 185754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185758 */     GIR_RootConstrainSelectedInstOperands,
     /* 185759 */     // GIR_Coverage, 840,
     /* 185759 */     GIR_EraseRootFromParent_Done,
     /* 185760 */   // Label 3426: @185760
     /* 185760 */   GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(185796), // Rule ID 841 //
     /* 185765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 185773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185783 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185787 */     // (intrinsic_wo_chain:{ *:[v4i16] } 610:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTMUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 185787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f16),
     /* 185790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185794 */     GIR_RootConstrainSelectedInstOperands,
     /* 185795 */     // GIR_Coverage, 841,
     /* 185795 */     GIR_EraseRootFromParent_Done,
     /* 185796 */   // Label 3427: @185796
     /* 185796 */   GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(185832), // Rule ID 842 //
     /* 185801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 185809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185823 */     // (intrinsic_wo_chain:{ *:[v8i16] } 610:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTMUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 185823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv8f16),
     /* 185826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185830 */     GIR_RootConstrainSelectedInstOperands,
     /* 185831 */     // GIR_Coverage, 842,
     /* 185831 */     GIR_EraseRootFromParent_Done,
     /* 185832 */   // Label 3428: @185832
     /* 185832 */   GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(185868), // Rule ID 843 //
     /* 185837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 185845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 185848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 185851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185855 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185859 */     // (intrinsic_wo_chain:{ *:[v2i32] } 610:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTMUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 185859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f32),
     /* 185862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185866 */     GIR_RootConstrainSelectedInstOperands,
     /* 185867 */     // GIR_Coverage, 843,
     /* 185867 */     GIR_EraseRootFromParent_Done,
     /* 185868 */   // Label 3429: @185868
     /* 185868 */   GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(185904), // Rule ID 844 //
     /* 185873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 185881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 185884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 185887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185891 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185895 */     // (intrinsic_wo_chain:{ *:[v4i32] } 610:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTMUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 185895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv4f32),
     /* 185898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185902 */     GIR_RootConstrainSelectedInstOperands,
     /* 185903 */     // GIR_Coverage, 844,
     /* 185903 */     GIR_EraseRootFromParent_Done,
     /* 185904 */   // Label 3430: @185904
     /* 185904 */   GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(185940), // Rule ID 845 //
     /* 185909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 185912 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 185917 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 185920 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 185923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185927 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185931 */     // (intrinsic_wo_chain:{ *:[v2i64] } 610:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTMUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 185931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv2f64),
     /* 185934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185938 */     GIR_RootConstrainSelectedInstOperands,
     /* 185939 */     // GIR_Coverage, 845,
     /* 185939 */     GIR_EraseRootFromParent_Done,
     /* 185940 */   // Label 3431: @185940
     /* 185940 */   GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(185976), // Rule ID 846 //
     /* 185945 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185948 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 185953 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 185956 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 185959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185963 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 185967 */     // (intrinsic_wo_chain:{ *:[v4i16] } 611:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTNSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 185967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f16),
     /* 185970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 185972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 185974 */     GIR_RootConstrainSelectedInstOperands,
     /* 185975 */     // GIR_Coverage, 846,
     /* 185975 */     GIR_EraseRootFromParent_Done,
     /* 185976 */   // Label 3432: @185976
     /* 185976 */   GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(186012), // Rule ID 847 //
     /* 185981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 185984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 185989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 185992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 185995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 185999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186003 */     // (intrinsic_wo_chain:{ *:[v8i16] } 611:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 186003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv8f16),
     /* 186006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186008 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186010 */     GIR_RootConstrainSelectedInstOperands,
     /* 186011 */     // GIR_Coverage, 847,
     /* 186011 */     GIR_EraseRootFromParent_Done,
     /* 186012 */   // Label 3433: @186012
     /* 186012 */   GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(186048), // Rule ID 848 //
     /* 186017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 186025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186039 */     // (intrinsic_wo_chain:{ *:[v2i32] } 611:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTNSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 186039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f32),
     /* 186042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186046 */     GIR_RootConstrainSelectedInstOperands,
     /* 186047 */     // GIR_Coverage, 848,
     /* 186047 */     GIR_EraseRootFromParent_Done,
     /* 186048 */   // Label 3434: @186048
     /* 186048 */   GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(186084), // Rule ID 849 //
     /* 186053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 186061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186075 */     // (intrinsic_wo_chain:{ *:[v4i32] } 611:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 186075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv4f32),
     /* 186078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186082 */     GIR_RootConstrainSelectedInstOperands,
     /* 186083 */     // GIR_Coverage, 849,
     /* 186083 */     GIR_EraseRootFromParent_Done,
     /* 186084 */   // Label 3435: @186084
     /* 186084 */   GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(186120), // Rule ID 850 //
     /* 186089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 186097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186107 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186111 */     // (intrinsic_wo_chain:{ *:[v2i64] } 611:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 186111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv2f64),
     /* 186114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186116 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186118 */     GIR_RootConstrainSelectedInstOperands,
     /* 186119 */     // GIR_Coverage, 850,
     /* 186119 */     GIR_EraseRootFromParent_Done,
     /* 186120 */   // Label 3436: @186120
     /* 186120 */   GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(186156), // Rule ID 851 //
     /* 186125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 186133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186143 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186147 */     // (intrinsic_wo_chain:{ *:[v4i16] } 612:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTNUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 186147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f16),
     /* 186150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186154 */     GIR_RootConstrainSelectedInstOperands,
     /* 186155 */     // GIR_Coverage, 851,
     /* 186155 */     GIR_EraseRootFromParent_Done,
     /* 186156 */   // Label 3437: @186156
     /* 186156 */   GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(186192), // Rule ID 852 //
     /* 186161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 186169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 186172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 186175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186179 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186183 */     // (intrinsic_wo_chain:{ *:[v8i16] } 612:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 186183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv8f16),
     /* 186186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186190 */     GIR_RootConstrainSelectedInstOperands,
     /* 186191 */     // GIR_Coverage, 852,
     /* 186191 */     GIR_EraseRootFromParent_Done,
     /* 186192 */   // Label 3438: @186192
     /* 186192 */   GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(186228), // Rule ID 853 //
     /* 186197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 186205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186208 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186215 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186219 */     // (intrinsic_wo_chain:{ *:[v2i32] } 612:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTNUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 186219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f32),
     /* 186222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186226 */     GIR_RootConstrainSelectedInstOperands,
     /* 186227 */     // GIR_Coverage, 853,
     /* 186227 */     GIR_EraseRootFromParent_Done,
     /* 186228 */   // Label 3439: @186228
     /* 186228 */   GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(186264), // Rule ID 854 //
     /* 186233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 186241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186251 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186255 */     // (intrinsic_wo_chain:{ *:[v4i32] } 612:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 186255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv4f32),
     /* 186258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186260 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186262 */     GIR_RootConstrainSelectedInstOperands,
     /* 186263 */     // GIR_Coverage, 854,
     /* 186263 */     GIR_EraseRootFromParent_Done,
     /* 186264 */   // Label 3440: @186264
     /* 186264 */   GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(186300), // Rule ID 855 //
     /* 186269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 186277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186287 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186291 */     // (intrinsic_wo_chain:{ *:[v2i64] } 612:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 186291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv2f64),
     /* 186294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186298 */     GIR_RootConstrainSelectedInstOperands,
     /* 186299 */     // GIR_Coverage, 855,
     /* 186299 */     GIR_EraseRootFromParent_Done,
     /* 186300 */   // Label 3441: @186300
     /* 186300 */   GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(186336), // Rule ID 856 //
     /* 186305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 186313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186323 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186327 */     // (intrinsic_wo_chain:{ *:[v4i16] } 613:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTPSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 186327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f16),
     /* 186330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186334 */     GIR_RootConstrainSelectedInstOperands,
     /* 186335 */     // GIR_Coverage, 856,
     /* 186335 */     GIR_EraseRootFromParent_Done,
     /* 186336 */   // Label 3442: @186336
     /* 186336 */   GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(186372), // Rule ID 857 //
     /* 186341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 186349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 186352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 186355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186359 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186363 */     // (intrinsic_wo_chain:{ *:[v8i16] } 613:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTPSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 186363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv8f16),
     /* 186366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186370 */     GIR_RootConstrainSelectedInstOperands,
     /* 186371 */     // GIR_Coverage, 857,
     /* 186371 */     GIR_EraseRootFromParent_Done,
     /* 186372 */   // Label 3443: @186372
     /* 186372 */   GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(186408), // Rule ID 858 //
     /* 186377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 186385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186399 */     // (intrinsic_wo_chain:{ *:[v2i32] } 613:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTPSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 186399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f32),
     /* 186402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186406 */     GIR_RootConstrainSelectedInstOperands,
     /* 186407 */     // GIR_Coverage, 858,
     /* 186407 */     GIR_EraseRootFromParent_Done,
     /* 186408 */   // Label 3444: @186408
     /* 186408 */   GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(186444), // Rule ID 859 //
     /* 186413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 186421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186431 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186435 */     // (intrinsic_wo_chain:{ *:[v4i32] } 613:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTPSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 186435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv4f32),
     /* 186438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186442 */     GIR_RootConstrainSelectedInstOperands,
     /* 186443 */     // GIR_Coverage, 859,
     /* 186443 */     GIR_EraseRootFromParent_Done,
     /* 186444 */   // Label 3445: @186444
     /* 186444 */   GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(186480), // Rule ID 860 //
     /* 186449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 186457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186467 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186471 */     // (intrinsic_wo_chain:{ *:[v2i64] } 613:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTPSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 186471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv2f64),
     /* 186474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186476 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186478 */     GIR_RootConstrainSelectedInstOperands,
     /* 186479 */     // GIR_Coverage, 860,
     /* 186479 */     GIR_EraseRootFromParent_Done,
     /* 186480 */   // Label 3446: @186480
     /* 186480 */   GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(186516), // Rule ID 861 //
     /* 186485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 186493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186507 */     // (intrinsic_wo_chain:{ *:[v4i16] } 614:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCVTPUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 186507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f16),
     /* 186510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186514 */     GIR_RootConstrainSelectedInstOperands,
     /* 186515 */     // GIR_Coverage, 861,
     /* 186515 */     GIR_EraseRootFromParent_Done,
     /* 186516 */   // Label 3447: @186516
     /* 186516 */   GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(186552), // Rule ID 862 //
     /* 186521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186524 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 186529 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 186532 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 186535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186543 */     // (intrinsic_wo_chain:{ *:[v8i16] } 614:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCVTPUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 186543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv8f16),
     /* 186546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186550 */     GIR_RootConstrainSelectedInstOperands,
     /* 186551 */     // GIR_Coverage, 862,
     /* 186551 */     GIR_EraseRootFromParent_Done,
     /* 186552 */   // Label 3448: @186552
     /* 186552 */   GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(186588), // Rule ID 863 //
     /* 186557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 186565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186571 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186575 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186579 */     // (intrinsic_wo_chain:{ *:[v2i32] } 614:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCVTPUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 186579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f32),
     /* 186582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186586 */     GIR_RootConstrainSelectedInstOperands,
     /* 186587 */     // GIR_Coverage, 863,
     /* 186587 */     GIR_EraseRootFromParent_Done,
     /* 186588 */   // Label 3449: @186588
     /* 186588 */   GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(186624), // Rule ID 864 //
     /* 186593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 186601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186615 */     // (intrinsic_wo_chain:{ *:[v4i32] } 614:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTPUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 186615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv4f32),
     /* 186618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186620 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186622 */     GIR_RootConstrainSelectedInstOperands,
     /* 186623 */     // GIR_Coverage, 864,
     /* 186623 */     GIR_EraseRootFromParent_Done,
     /* 186624 */   // Label 3450: @186624
     /* 186624 */   GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(186660), // Rule ID 865 //
     /* 186629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 186637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186647 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186651 */     // (intrinsic_wo_chain:{ *:[v2i64] } 614:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTPUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 186651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv2f64),
     /* 186654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186656 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186658 */     GIR_RootConstrainSelectedInstOperands,
     /* 186659 */     // GIR_Coverage, 865,
     /* 186659 */     GIR_EraseRootFromParent_Done,
     /* 186660 */   // Label 3451: @186660
     /* 186660 */   GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(186696), // Rule ID 866 //
     /* 186665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtxn),
     /* 186673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186676 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186687 */     // (intrinsic_wo_chain:{ *:[v2f32] } 615:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
     /* 186687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv2f32),
     /* 186690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186694 */     GIR_RootConstrainSelectedInstOperands,
     /* 186695 */     // GIR_Coverage, 866,
     /* 186695 */     GIR_EraseRootFromParent_Done,
     /* 186696 */   // Label 3452: @186696
     /* 186696 */   GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(186732), // Rule ID 893 //
     /* 186701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 186709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 186712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 186715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186719 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186723 */     // (intrinsic_wo_chain:{ *:[v4f16] } 657:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FRECPEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 186723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f16),
     /* 186726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186730 */     GIR_RootConstrainSelectedInstOperands,
     /* 186731 */     // GIR_Coverage, 893,
     /* 186731 */     GIR_EraseRootFromParent_Done,
     /* 186732 */   // Label 3453: @186732
     /* 186732 */   GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(186768), // Rule ID 894 //
     /* 186737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 186740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 186745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 186748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 186751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186755 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186759 */     // (intrinsic_wo_chain:{ *:[v8f16] } 657:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FRECPEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 186759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv8f16),
     /* 186762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186766 */     GIR_RootConstrainSelectedInstOperands,
     /* 186767 */     // GIR_Coverage, 894,
     /* 186767 */     GIR_EraseRootFromParent_Done,
     /* 186768 */   // Label 3454: @186768
     /* 186768 */   GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(186804), // Rule ID 895 //
     /* 186773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 186781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186791 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186795 */     // (intrinsic_wo_chain:{ *:[v2f32] } 657:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRECPEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 186795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f32),
     /* 186798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186802 */     GIR_RootConstrainSelectedInstOperands,
     /* 186803 */     // GIR_Coverage, 895,
     /* 186803 */     GIR_EraseRootFromParent_Done,
     /* 186804 */   // Label 3455: @186804
     /* 186804 */   GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(186840), // Rule ID 896 //
     /* 186809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186812 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 186817 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186820 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186827 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186831 */     // (intrinsic_wo_chain:{ *:[v4f32] } 657:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRECPEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 186831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv4f32),
     /* 186834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186836 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186838 */     GIR_RootConstrainSelectedInstOperands,
     /* 186839 */     // GIR_Coverage, 896,
     /* 186839 */     GIR_EraseRootFromParent_Done,
     /* 186840 */   // Label 3456: @186840
     /* 186840 */   GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(186876), // Rule ID 897 //
     /* 186845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 186848 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 186853 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186856 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186863 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186867 */     // (intrinsic_wo_chain:{ *:[v2f64] } 657:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRECPEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 186867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv2f64),
     /* 186870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186874 */     GIR_RootConstrainSelectedInstOperands,
     /* 186875 */     // GIR_Coverage, 897,
     /* 186875 */     GIR_EraseRootFromParent_Done,
     /* 186876 */   // Label 3457: @186876
     /* 186876 */   GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(186912), // Rule ID 968 //
     /* 186881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 186884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 186889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 186892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 186895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 186903 */     // (intrinsic_wo_chain:{ *:[v2f32] } 661:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT32Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 186903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f32),
     /* 186906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186908 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186910 */     GIR_RootConstrainSelectedInstOperands,
     /* 186911 */     // GIR_Coverage, 968,
     /* 186911 */     GIR_EraseRootFromParent_Done,
     /* 186912 */   // Label 3458: @186912
     /* 186912 */   GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(186948), // Rule ID 969 //
     /* 186917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 186920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 186925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 186928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 186931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186935 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186939 */     // (intrinsic_wo_chain:{ *:[v4f32] } 661:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT32Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 186939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv4f32),
     /* 186942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186946 */     GIR_RootConstrainSelectedInstOperands,
     /* 186947 */     // GIR_Coverage, 969,
     /* 186947 */     GIR_EraseRootFromParent_Done,
     /* 186948 */   // Label 3459: @186948
     /* 186948 */   GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(186984), // Rule ID 970 //
     /* 186953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 186956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 186961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 186964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 186967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186971 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 186975 */     // (intrinsic_wo_chain:{ *:[v2f64] } 661:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT32Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 186975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Zv2f64),
     /* 186978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 186980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 186982 */     GIR_RootConstrainSelectedInstOperands,
     /* 186983 */     // GIR_Coverage, 970,
     /* 186983 */     GIR_EraseRootFromParent_Done,
     /* 186984 */   // Label 3460: @186984
     /* 186984 */   GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(187020), // Rule ID 971 //
     /* 186989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 186992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 186997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187007 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187011 */     // (intrinsic_wo_chain:{ *:[v2f32] } 663:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT64Zv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 187011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f32),
     /* 187014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187016 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187018 */     GIR_RootConstrainSelectedInstOperands,
     /* 187019 */     // GIR_Coverage, 971,
     /* 187019 */     GIR_EraseRootFromParent_Done,
     /* 187020 */   // Label 3461: @187020
     /* 187020 */   GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(187056), // Rule ID 972 //
     /* 187025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 187033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187047 */     // (intrinsic_wo_chain:{ *:[v4f32] } 663:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT64Zv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 187047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv4f32),
     /* 187050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187054 */     GIR_RootConstrainSelectedInstOperands,
     /* 187055 */     // GIR_Coverage, 972,
     /* 187055 */     GIR_EraseRootFromParent_Done,
     /* 187056 */   // Label 3462: @187056
     /* 187056 */   GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(187092), // Rule ID 973 //
     /* 187061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 187069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187083 */     // (intrinsic_wo_chain:{ *:[v2f64] } 663:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT64Zv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 187083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Zv2f64),
     /* 187086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187090 */     GIR_RootConstrainSelectedInstOperands,
     /* 187091 */     // GIR_Coverage, 973,
     /* 187091 */     GIR_EraseRootFromParent_Done,
     /* 187092 */   // Label 3463: @187092
     /* 187092 */   GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(187128), // Rule ID 974 //
     /* 187097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 187105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187115 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187119 */     // (intrinsic_wo_chain:{ *:[v2f32] } 660:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT32Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 187119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f32),
     /* 187122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187124 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187126 */     GIR_RootConstrainSelectedInstOperands,
     /* 187127 */     // GIR_Coverage, 974,
     /* 187127 */     GIR_EraseRootFromParent_Done,
     /* 187128 */   // Label 3464: @187128
     /* 187128 */   GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(187164), // Rule ID 975 //
     /* 187133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 187141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187151 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187155 */     // (intrinsic_wo_chain:{ *:[v4f32] } 660:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT32Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 187155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv4f32),
     /* 187158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187160 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187162 */     GIR_RootConstrainSelectedInstOperands,
     /* 187163 */     // GIR_Coverage, 975,
     /* 187163 */     GIR_EraseRootFromParent_Done,
     /* 187164 */   // Label 3465: @187164
     /* 187164 */   GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(187200), // Rule ID 976 //
     /* 187169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 187177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187187 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187191 */     // (intrinsic_wo_chain:{ *:[v2f64] } 660:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT32Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 187191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32Xv2f64),
     /* 187194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187198 */     GIR_RootConstrainSelectedInstOperands,
     /* 187199 */     // GIR_Coverage, 976,
     /* 187199 */     GIR_EraseRootFromParent_Done,
     /* 187200 */   // Label 3466: @187200
     /* 187200 */   GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(187236), // Rule ID 977 //
     /* 187205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187208 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 187213 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187216 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187223 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187227 */     // (intrinsic_wo_chain:{ *:[v2f32] } 662:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRINT64Xv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 187227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f32),
     /* 187230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187234 */     GIR_RootConstrainSelectedInstOperands,
     /* 187235 */     // GIR_Coverage, 977,
     /* 187235 */     GIR_EraseRootFromParent_Done,
     /* 187236 */   // Label 3467: @187236
     /* 187236 */   GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(187272), // Rule ID 978 //
     /* 187241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 187249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187263 */     // (intrinsic_wo_chain:{ *:[v4f32] } 662:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRINT64Xv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 187263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv4f32),
     /* 187266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187270 */     GIR_RootConstrainSelectedInstOperands,
     /* 187271 */     // GIR_Coverage, 978,
     /* 187271 */     GIR_EraseRootFromParent_Done,
     /* 187272 */   // Label 3468: @187272
     /* 187272 */   GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(187308), // Rule ID 979 //
     /* 187277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFRInt3264),
     /* 187280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 187285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187299 */     // (intrinsic_wo_chain:{ *:[v2f64] } 662:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRINT64Xv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 187299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64Xv2f64),
     /* 187302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187306 */     GIR_RootConstrainSelectedInstOperands,
     /* 187307 */     // GIR_Coverage, 979,
     /* 187307 */     GIR_EraseRootFromParent_Done,
     /* 187308 */   // Label 3469: @187308
     /* 187308 */   GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(187344), // Rule ID 980 //
     /* 187313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 187321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 187324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 187327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187331 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187335 */     // (intrinsic_wo_chain:{ *:[v4f16] } 664:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FRSQRTEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 187335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f16),
     /* 187338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187340 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187342 */     GIR_RootConstrainSelectedInstOperands,
     /* 187343 */     // GIR_Coverage, 980,
     /* 187343 */     GIR_EraseRootFromParent_Done,
     /* 187344 */   // Label 3470: @187344
     /* 187344 */   GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(187380), // Rule ID 981 //
     /* 187349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 187352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 187357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187371 */     // (intrinsic_wo_chain:{ *:[v8f16] } 664:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FRSQRTEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 187371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv8f16),
     /* 187374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187378 */     GIR_RootConstrainSelectedInstOperands,
     /* 187379 */     // GIR_Coverage, 981,
     /* 187379 */     GIR_EraseRootFromParent_Done,
     /* 187380 */   // Label 3471: @187380
     /* 187380 */   GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(187416), // Rule ID 982 //
     /* 187385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 187393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187403 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187407 */     // (intrinsic_wo_chain:{ *:[v2f32] } 664:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FRSQRTEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 187407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f32),
     /* 187410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187412 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187414 */     GIR_RootConstrainSelectedInstOperands,
     /* 187415 */     // GIR_Coverage, 982,
     /* 187415 */     GIR_EraseRootFromParent_Done,
     /* 187416 */   // Label 3472: @187416
     /* 187416 */   GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(187452), // Rule ID 983 //
     /* 187421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 187429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187439 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187443 */     // (intrinsic_wo_chain:{ *:[v4f32] } 664:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FRSQRTEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 187443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv4f32),
     /* 187446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187450 */     GIR_RootConstrainSelectedInstOperands,
     /* 187451 */     // GIR_Coverage, 983,
     /* 187451 */     GIR_EraseRootFromParent_Done,
     /* 187452 */   // Label 3473: @187452
     /* 187452 */   GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(187488), // Rule ID 984 //
     /* 187457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 187465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187479 */     // (intrinsic_wo_chain:{ *:[v2f64] } 664:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FRSQRTEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 187479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv2f64),
     /* 187482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187484 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187486 */     GIR_RootConstrainSelectedInstOperands,
     /* 187487 */     // GIR_Coverage, 984,
     /* 187487 */     GIR_EraseRootFromParent_Done,
     /* 187488 */   // Label 3474: @187488
     /* 187488 */   GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(187524), // Rule ID 1031 //
     /* 187493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 187504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 187507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187511 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187515 */     // (intrinsic_wo_chain:{ *:[v4i16] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 187515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
     /* 187518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187520 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187522 */     GIR_RootConstrainSelectedInstOperands,
     /* 187523 */     // GIR_Coverage, 1031,
     /* 187523 */     GIR_EraseRootFromParent_Done,
     /* 187524 */   // Label 3475: @187524
     /* 187524 */   GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(187560), // Rule ID 1033 //
     /* 187529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 187543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187547 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187551 */     // (intrinsic_wo_chain:{ *:[v8i16] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 187551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
     /* 187554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187558 */     GIR_RootConstrainSelectedInstOperands,
     /* 187559 */     // GIR_Coverage, 1033,
     /* 187559 */     GIR_EraseRootFromParent_Done,
     /* 187560 */   // Label 3476: @187560
     /* 187560 */   GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(187596), // Rule ID 1035 //
     /* 187565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 187579 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187583 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187587 */     // (intrinsic_wo_chain:{ *:[v2i32] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 187587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
     /* 187590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187594 */     GIR_RootConstrainSelectedInstOperands,
     /* 187595 */     // GIR_Coverage, 1035,
     /* 187595 */     GIR_EraseRootFromParent_Done,
     /* 187596 */   // Label 3477: @187596
     /* 187596 */   GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(187632), // Rule ID 1037 //
     /* 187601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187604 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187609 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187612 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187619 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187623 */     // (intrinsic_wo_chain:{ *:[v4i32] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 187623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
     /* 187626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187630 */     GIR_RootConstrainSelectedInstOperands,
     /* 187631 */     // GIR_Coverage, 1037,
     /* 187631 */     GIR_EraseRootFromParent_Done,
     /* 187632 */   // Label 3478: @187632
     /* 187632 */   GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(187668), // Rule ID 1039 //
     /* 187637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 187648 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187659 */     // (intrinsic_wo_chain:{ *:[v1i64] } 685:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 187659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 187662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187666 */     GIR_RootConstrainSelectedInstOperands,
     /* 187667 */     // GIR_Coverage, 1039,
     /* 187667 */     GIR_EraseRootFromParent_Done,
     /* 187668 */   // Label 3479: @187668
     /* 187668 */   GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(187704), // Rule ID 1041 //
     /* 187673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 187681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187695 */     // (intrinsic_wo_chain:{ *:[v2i64] } 685:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 187695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
     /* 187698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187702 */     GIR_RootConstrainSelectedInstOperands,
     /* 187703 */     // GIR_Coverage, 1041,
     /* 187703 */     GIR_EraseRootFromParent_Done,
     /* 187704 */   // Label 3480: @187704
     /* 187704 */   GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(187740), // Rule ID 1052 //
     /* 187709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 187720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 187723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187731 */     // (intrinsic_wo_chain:{ *:[v8i8] } 703:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SQABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 187731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i8),
     /* 187734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187738 */     GIR_RootConstrainSelectedInstOperands,
     /* 187739 */     // GIR_Coverage, 1052,
     /* 187739 */     GIR_EraseRootFromParent_Done,
     /* 187740 */   // Label 3481: @187740
     /* 187740 */   GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(187776), // Rule ID 1053 //
     /* 187745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 187756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 187759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187767 */     // (intrinsic_wo_chain:{ *:[v16i8] } 703:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SQABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 187767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv16i8),
     /* 187770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187772 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187774 */     GIR_RootConstrainSelectedInstOperands,
     /* 187775 */     // GIR_Coverage, 1053,
     /* 187775 */     GIR_EraseRootFromParent_Done,
     /* 187776 */   // Label 3482: @187776
     /* 187776 */   GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(187812), // Rule ID 1054 //
     /* 187781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 187792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 187795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187799 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187803 */     // (intrinsic_wo_chain:{ *:[v4i16] } 703:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SQABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 187803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i16),
     /* 187806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187810 */     GIR_RootConstrainSelectedInstOperands,
     /* 187811 */     // GIR_Coverage, 1054,
     /* 187811 */     GIR_EraseRootFromParent_Done,
     /* 187812 */   // Label 3483: @187812
     /* 187812 */   GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(187848), // Rule ID 1055 //
     /* 187817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 187828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 187831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187835 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187839 */     // (intrinsic_wo_chain:{ *:[v8i16] } 703:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SQABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 187839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv8i16),
     /* 187842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187844 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187846 */     GIR_RootConstrainSelectedInstOperands,
     /* 187847 */     // GIR_Coverage, 1055,
     /* 187847 */     GIR_EraseRootFromParent_Done,
     /* 187848 */   // Label 3484: @187848
     /* 187848 */   GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(187884), // Rule ID 1056 //
     /* 187853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 187864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 187867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187875 */     // (intrinsic_wo_chain:{ *:[v2i32] } 703:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SQABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 187875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i32),
     /* 187878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187882 */     GIR_RootConstrainSelectedInstOperands,
     /* 187883 */     // GIR_Coverage, 1056,
     /* 187883 */     GIR_EraseRootFromParent_Done,
     /* 187884 */   // Label 3485: @187884
     /* 187884 */   GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(187920), // Rule ID 1057 //
     /* 187889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 187900 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 187903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187907 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187911 */     // (intrinsic_wo_chain:{ *:[v4i32] } 703:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SQABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 187911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv4i32),
     /* 187914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187916 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187918 */     GIR_RootConstrainSelectedInstOperands,
     /* 187919 */     // GIR_Coverage, 1057,
     /* 187919 */     GIR_EraseRootFromParent_Done,
     /* 187920 */   // Label 3486: @187920
     /* 187920 */   GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(187956), // Rule ID 1058 //
     /* 187925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 187933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 187936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 187939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187943 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 187947 */     // (intrinsic_wo_chain:{ *:[v2i64] } 703:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (SQABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 187947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv2i64),
     /* 187950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187954 */     GIR_RootConstrainSelectedInstOperands,
     /* 187955 */     // GIR_Coverage, 1058,
     /* 187955 */     GIR_EraseRootFromParent_Done,
     /* 187956 */   // Label 3487: @187956
     /* 187956 */   GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(187992), // Rule ID 1059 //
     /* 187961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 187964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 187969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 187972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 187975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 187983 */     // (intrinsic_wo_chain:{ *:[v8i8] } 710:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SQNEGv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 187983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i8),
     /* 187986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 187988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 187990 */     GIR_RootConstrainSelectedInstOperands,
     /* 187991 */     // GIR_Coverage, 1059,
     /* 187991 */     GIR_EraseRootFromParent_Done,
     /* 187992 */   // Label 3488: @187992
     /* 187992 */   GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(188028), // Rule ID 1060 //
     /* 187997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 188008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 188011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188019 */     // (intrinsic_wo_chain:{ *:[v16i8] } 710:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SQNEGv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 188019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv16i8),
     /* 188022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188024 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188026 */     GIR_RootConstrainSelectedInstOperands,
     /* 188027 */     // GIR_Coverage, 1060,
     /* 188027 */     GIR_EraseRootFromParent_Done,
     /* 188028 */   // Label 3489: @188028
     /* 188028 */   GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(188064), // Rule ID 1061 //
     /* 188033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 188044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 188047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188055 */     // (intrinsic_wo_chain:{ *:[v4i16] } 710:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SQNEGv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 188055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i16),
     /* 188058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188062 */     GIR_RootConstrainSelectedInstOperands,
     /* 188063 */     // GIR_Coverage, 1061,
     /* 188063 */     GIR_EraseRootFromParent_Done,
     /* 188064 */   // Label 3490: @188064
     /* 188064 */   GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(188100), // Rule ID 1062 //
     /* 188069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 188080 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 188083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188087 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188091 */     // (intrinsic_wo_chain:{ *:[v8i16] } 710:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SQNEGv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 188091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv8i16),
     /* 188094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188098 */     GIR_RootConstrainSelectedInstOperands,
     /* 188099 */     // GIR_Coverage, 1062,
     /* 188099 */     GIR_EraseRootFromParent_Done,
     /* 188100 */   // Label 3491: @188100
     /* 188100 */   GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(188136), // Rule ID 1063 //
     /* 188105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188108 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188113 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188116 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188123 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188127 */     // (intrinsic_wo_chain:{ *:[v2i32] } 710:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (SQNEGv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 188127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i32),
     /* 188130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188134 */     GIR_RootConstrainSelectedInstOperands,
     /* 188135 */     // GIR_Coverage, 1063,
     /* 188135 */     GIR_EraseRootFromParent_Done,
     /* 188136 */   // Label 3492: @188136
     /* 188136 */   GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(188172), // Rule ID 1064 //
     /* 188141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188159 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188163 */     // (intrinsic_wo_chain:{ *:[v4i32] } 710:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (SQNEGv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 188163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv4i32),
     /* 188166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188170 */     GIR_RootConstrainSelectedInstOperands,
     /* 188171 */     // GIR_Coverage, 1064,
     /* 188171 */     GIR_EraseRootFromParent_Done,
     /* 188172 */   // Label 3493: @188172
     /* 188172 */   GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(188208), // Rule ID 1065 //
     /* 188177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 188185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 188188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 188191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188195 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188199 */     // (intrinsic_wo_chain:{ *:[v2i64] } 710:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (SQNEGv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 188199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv2i64),
     /* 188202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188206 */     GIR_RootConstrainSelectedInstOperands,
     /* 188207 */     // GIR_Coverage, 1065,
     /* 188207 */     GIR_EraseRootFromParent_Done,
     /* 188208 */   // Label 3494: @188208
     /* 188208 */   GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(188244), // Rule ID 1092 //
     /* 188213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188216 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188221 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 188224 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 188227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188235 */     // (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 188235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
     /* 188238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188242 */     GIR_RootConstrainSelectedInstOperands,
     /* 188243 */     // GIR_Coverage, 1092,
     /* 188243 */     GIR_EraseRootFromParent_Done,
     /* 188244 */   // Label 3495: @188244
     /* 188244 */   GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(188280), // Rule ID 1094 //
     /* 188249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 188260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 188263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188267 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188271 */     // (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 188271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
     /* 188274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188276 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188278 */     GIR_RootConstrainSelectedInstOperands,
     /* 188279 */     // GIR_Coverage, 1094,
     /* 188279 */     GIR_EraseRootFromParent_Done,
     /* 188280 */   // Label 3496: @188280
     /* 188280 */   GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(188316), // Rule ID 1096 //
     /* 188285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 188299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188303 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188307 */     // (intrinsic_wo_chain:{ *:[v2i32] } 750:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 188307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
     /* 188310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188314 */     GIR_RootConstrainSelectedInstOperands,
     /* 188315 */     // GIR_Coverage, 1096,
     /* 188315 */     GIR_EraseRootFromParent_Done,
     /* 188316 */   // Label 3497: @188316
     /* 188316 */   GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(188352), // Rule ID 1098 //
     /* 188321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 188335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188343 */     // (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 188343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
     /* 188346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188350 */     GIR_RootConstrainSelectedInstOperands,
     /* 188351 */     // GIR_Coverage, 1098,
     /* 188351 */     GIR_EraseRootFromParent_Done,
     /* 188352 */   // Label 3498: @188352
     /* 188352 */   GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(188388), // Rule ID 1100 //
     /* 188357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 188368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188379 */     // (intrinsic_wo_chain:{ *:[v1i64] } 750:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 188379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 188382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188386 */     GIR_RootConstrainSelectedInstOperands,
     /* 188387 */     // GIR_Coverage, 1100,
     /* 188387 */     GIR_EraseRootFromParent_Done,
     /* 188388 */   // Label 3499: @188388
     /* 188388 */   GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(188424), // Rule ID 1102 //
     /* 188393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 188401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 188404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188411 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188415 */     // (intrinsic_wo_chain:{ *:[v2i64] } 750:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 188415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
     /* 188418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188420 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188422 */     GIR_RootConstrainSelectedInstOperands,
     /* 188423 */     // GIR_Coverage, 1102,
     /* 188423 */     GIR_EraseRootFromParent_Done,
     /* 188424 */   // Label 3500: @188424
     /* 188424 */   GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(188460), // Rule ID 1116 //
     /* 188429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
     /* 188437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188447 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188451 */     // (intrinsic_wo_chain:{ *:[v2i32] } 771:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (URECPEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 188451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv2i32),
     /* 188454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188458 */     GIR_RootConstrainSelectedInstOperands,
     /* 188459 */     // GIR_Coverage, 1116,
     /* 188459 */     GIR_EraseRootFromParent_Done,
     /* 188460 */   // Label 3501: @188460
     /* 188460 */   GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(188496), // Rule ID 1117 //
     /* 188465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urecpe),
     /* 188473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188483 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188487 */     // (intrinsic_wo_chain:{ *:[v4i32] } 771:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (URECPEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 188487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPEv4i32),
     /* 188490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188492 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188494 */     GIR_RootConstrainSelectedInstOperands,
     /* 188495 */     // GIR_Coverage, 1117,
     /* 188495 */     GIR_EraseRootFromParent_Done,
     /* 188496 */   // Label 3502: @188496
     /* 188496 */   GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(188532), // Rule ID 1118 //
     /* 188501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188504 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
     /* 188509 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 188512 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 188515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188519 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188523 */     // (intrinsic_wo_chain:{ *:[v2i32] } 774:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (URSQRTEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 188523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv2i32),
     /* 188526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188528 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188530 */     GIR_RootConstrainSelectedInstOperands,
     /* 188531 */     // GIR_Coverage, 1118,
     /* 188531 */     GIR_EraseRootFromParent_Done,
     /* 188532 */   // Label 3503: @188532
     /* 188532 */   GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(188568), // Rule ID 1119 //
     /* 188537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 188540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ursqrte),
     /* 188545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 188548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 188551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188555 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 188559 */     // (intrinsic_wo_chain:{ *:[v4i32] } 774:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (URSQRTEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 188559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTEv4i32),
     /* 188562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188566 */     GIR_RootConstrainSelectedInstOperands,
     /* 188567 */     // GIR_Coverage, 1119,
     /* 188567 */     GIR_EraseRootFromParent_Done,
     /* 188568 */   // Label 3504: @188568
     /* 188568 */   GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(188604), // Rule ID 1659 //
     /* 188573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 188581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 188584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 188587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188591 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188595 */     // (intrinsic_wo_chain:{ *:[i64] } 607:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTASv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 188595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 188598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188602 */     GIR_RootConstrainSelectedInstOperands,
     /* 188603 */     // GIR_Coverage, 1659,
     /* 188603 */     GIR_EraseRootFromParent_Done,
     /* 188604 */   // Label 3505: @188604
     /* 188604 */   GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(188640), // Rule ID 1660 //
     /* 188609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 188617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188627 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188631 */     // (intrinsic_wo_chain:{ *:[i32] } 607:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTASv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 188631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 188634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188638 */     GIR_RootConstrainSelectedInstOperands,
     /* 188639 */     // GIR_Coverage, 1660,
     /* 188639 */     GIR_EraseRootFromParent_Done,
     /* 188640 */   // Label 3506: @188640
     /* 188640 */   GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(188676), // Rule ID 1661 //
     /* 188645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 188648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 188653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 188656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 188659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188663 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188667 */     // (intrinsic_wo_chain:{ *:[i16] } 607:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTASv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 188667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1f16),
     /* 188670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188674 */     GIR_RootConstrainSelectedInstOperands,
     /* 188675 */     // GIR_Coverage, 1661,
     /* 188675 */     GIR_EraseRootFromParent_Done,
     /* 188676 */   // Label 3507: @188676
     /* 188676 */   GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(188712), // Rule ID 1662 //
     /* 188681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188684 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 188689 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 188692 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 188695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188699 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188703 */     // (intrinsic_wo_chain:{ *:[i64] } 608:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTAUv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 188703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 188706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188710 */     GIR_RootConstrainSelectedInstOperands,
     /* 188711 */     // GIR_Coverage, 1662,
     /* 188711 */     GIR_EraseRootFromParent_Done,
     /* 188712 */   // Label 3508: @188712
     /* 188712 */   GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(188748), // Rule ID 1663 //
     /* 188717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188720 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 188725 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188728 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188731 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188739 */     // (intrinsic_wo_chain:{ *:[i32] } 608:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTAUv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 188739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i32),
     /* 188742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188746 */     GIR_RootConstrainSelectedInstOperands,
     /* 188747 */     // GIR_Coverage, 1663,
     /* 188747 */     GIR_EraseRootFromParent_Done,
     /* 188748 */   // Label 3509: @188748
     /* 188748 */   GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(188784), // Rule ID 1664 //
     /* 188753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 188756 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 188761 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 188764 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 188767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188771 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188775 */     // (intrinsic_wo_chain:{ *:[i16] } 608:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTAUv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 188775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1f16),
     /* 188778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188782 */     GIR_RootConstrainSelectedInstOperands,
     /* 188783 */     // GIR_Coverage, 1664,
     /* 188783 */     GIR_EraseRootFromParent_Done,
     /* 188784 */   // Label 3510: @188784
     /* 188784 */   GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(188820), // Rule ID 1665 //
     /* 188789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 188797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 188800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 188803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188807 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188811 */     // (intrinsic_wo_chain:{ *:[i64] } 609:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMSv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 188811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 188814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188818 */     GIR_RootConstrainSelectedInstOperands,
     /* 188819 */     // GIR_Coverage, 1665,
     /* 188819 */     GIR_EraseRootFromParent_Done,
     /* 188820 */   // Label 3511: @188820
     /* 188820 */   GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(188856), // Rule ID 1666 //
     /* 188825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 188833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188839 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188847 */     // (intrinsic_wo_chain:{ *:[i32] } 609:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMSv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 188847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i32),
     /* 188850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188854 */     GIR_RootConstrainSelectedInstOperands,
     /* 188855 */     // GIR_Coverage, 1666,
     /* 188855 */     GIR_EraseRootFromParent_Done,
     /* 188856 */   // Label 3512: @188856
     /* 188856 */   GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(188892), // Rule ID 1667 //
     /* 188861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 188864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 188869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 188872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 188875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188883 */     // (intrinsic_wo_chain:{ *:[i16] } 609:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMSv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 188883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1f16),
     /* 188886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188890 */     GIR_RootConstrainSelectedInstOperands,
     /* 188891 */     // GIR_Coverage, 1667,
     /* 188891 */     GIR_EraseRootFromParent_Done,
     /* 188892 */   // Label 3513: @188892
     /* 188892 */   GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(188928), // Rule ID 1668 //
     /* 188897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 188905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 188908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 188911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188915 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 188919 */     // (intrinsic_wo_chain:{ *:[i64] } 610:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTMUv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 188919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 188922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188924 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188926 */     GIR_RootConstrainSelectedInstOperands,
     /* 188927 */     // GIR_Coverage, 1668,
     /* 188927 */     GIR_EraseRootFromParent_Done,
     /* 188928 */   // Label 3514: @188928
     /* 188928 */   GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(188964), // Rule ID 1669 //
     /* 188933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 188936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 188941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 188944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 188947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 188955 */     // (intrinsic_wo_chain:{ *:[i32] } 610:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTMUv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 188955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i32),
     /* 188958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188962 */     GIR_RootConstrainSelectedInstOperands,
     /* 188963 */     // GIR_Coverage, 1669,
     /* 188963 */     GIR_EraseRootFromParent_Done,
     /* 188964 */   // Label 3515: @188964
     /* 188964 */   GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(189000), // Rule ID 1670 //
     /* 188969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 188972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 188977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 188980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 188983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188987 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 188991 */     // (intrinsic_wo_chain:{ *:[i16] } 610:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTMUv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 188991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1f16),
     /* 188994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 188996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 188998 */     GIR_RootConstrainSelectedInstOperands,
     /* 188999 */     // GIR_Coverage, 1670,
     /* 188999 */     GIR_EraseRootFromParent_Done,
     /* 189000 */   // Label 3516: @189000
     /* 189000 */   GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(189036), // Rule ID 1671 //
     /* 189005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 189013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189023 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189027 */     // (intrinsic_wo_chain:{ *:[i64] } 611:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNSv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 189027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i64),
     /* 189030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189032 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189034 */     GIR_RootConstrainSelectedInstOperands,
     /* 189035 */     // GIR_Coverage, 1671,
     /* 189035 */     GIR_EraseRootFromParent_Done,
     /* 189036 */   // Label 3517: @189036
     /* 189036 */   GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(189072), // Rule ID 1672 //
     /* 189041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 189049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189063 */     // (intrinsic_wo_chain:{ *:[i32] } 611:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNSv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 189063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i32),
     /* 189066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189070 */     GIR_RootConstrainSelectedInstOperands,
     /* 189071 */     // GIR_Coverage, 1672,
     /* 189071 */     GIR_EraseRootFromParent_Done,
     /* 189072 */   // Label 3518: @189072
     /* 189072 */   GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(189108), // Rule ID 1673 //
     /* 189077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 189080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 189085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 189091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189099 */     // (intrinsic_wo_chain:{ *:[i16] } 611:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNSv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 189099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1f16),
     /* 189102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189106 */     GIR_RootConstrainSelectedInstOperands,
     /* 189107 */     // GIR_Coverage, 1673,
     /* 189107 */     GIR_EraseRootFromParent_Done,
     /* 189108 */   // Label 3519: @189108
     /* 189108 */   GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(189144), // Rule ID 1674 //
     /* 189113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 189121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189135 */     // (intrinsic_wo_chain:{ *:[i64] } 612:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTNUv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 189135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i64),
     /* 189138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189142 */     GIR_RootConstrainSelectedInstOperands,
     /* 189143 */     // GIR_Coverage, 1674,
     /* 189143 */     GIR_EraseRootFromParent_Done,
     /* 189144 */   // Label 3520: @189144
     /* 189144 */   GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(189180), // Rule ID 1675 //
     /* 189149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 189157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189167 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189171 */     // (intrinsic_wo_chain:{ *:[i32] } 612:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTNUv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 189171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i32),
     /* 189174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189176 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189178 */     GIR_RootConstrainSelectedInstOperands,
     /* 189179 */     // GIR_Coverage, 1675,
     /* 189179 */     GIR_EraseRootFromParent_Done,
     /* 189180 */   // Label 3521: @189180
     /* 189180 */   GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(189216), // Rule ID 1676 //
     /* 189185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 189188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 189193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 189199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189207 */     // (intrinsic_wo_chain:{ *:[i16] } 612:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTNUv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 189207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1f16),
     /* 189210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189214 */     GIR_RootConstrainSelectedInstOperands,
     /* 189215 */     // GIR_Coverage, 1676,
     /* 189215 */     GIR_EraseRootFromParent_Done,
     /* 189216 */   // Label 3522: @189216
     /* 189216 */   GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(189252), // Rule ID 1677 //
     /* 189221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 189229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189232 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189239 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189243 */     // (intrinsic_wo_chain:{ *:[i64] } 613:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPSv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 189243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 189246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189250 */     GIR_RootConstrainSelectedInstOperands,
     /* 189251 */     // GIR_Coverage, 1677,
     /* 189251 */     GIR_EraseRootFromParent_Done,
     /* 189252 */   // Label 3523: @189252
     /* 189252 */   GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(189288), // Rule ID 1678 //
     /* 189257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 189265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189279 */     // (intrinsic_wo_chain:{ *:[i32] } 613:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPSv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 189279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i32),
     /* 189282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189286 */     GIR_RootConstrainSelectedInstOperands,
     /* 189287 */     // GIR_Coverage, 1678,
     /* 189287 */     GIR_EraseRootFromParent_Done,
     /* 189288 */   // Label 3524: @189288
     /* 189288 */   GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(189324), // Rule ID 1679 //
     /* 189293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 189296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 189301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 189307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189311 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189315 */     // (intrinsic_wo_chain:{ *:[i16] } 613:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPSv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 189315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1f16),
     /* 189318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189320 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189322 */     GIR_RootConstrainSelectedInstOperands,
     /* 189323 */     // GIR_Coverage, 1679,
     /* 189323 */     GIR_EraseRootFromParent_Done,
     /* 189324 */   // Label 3525: @189324
     /* 189324 */   GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(189360), // Rule ID 1680 //
     /* 189329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 189337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189347 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189351 */     // (intrinsic_wo_chain:{ *:[i64] } 614:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTPUv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 189351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 189354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189356 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189358 */     GIR_RootConstrainSelectedInstOperands,
     /* 189359 */     // GIR_Coverage, 1680,
     /* 189359 */     GIR_EraseRootFromParent_Done,
     /* 189360 */   // Label 3526: @189360
     /* 189360 */   GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(189396), // Rule ID 1681 //
     /* 189365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 189368 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 189373 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189376 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189383 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189387 */     // (intrinsic_wo_chain:{ *:[i32] } 614:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FCVTPUv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 189387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i32),
     /* 189390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189394 */     GIR_RootConstrainSelectedInstOperands,
     /* 189395 */     // GIR_Coverage, 1681,
     /* 189395 */     GIR_EraseRootFromParent_Done,
     /* 189396 */   // Label 3527: @189396
     /* 189396 */   GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(189432), // Rule ID 1682 //
     /* 189401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 189404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 189409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 189415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189423 */     // (intrinsic_wo_chain:{ *:[i16] } 614:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FCVTPUv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 189423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1f16),
     /* 189426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189430 */     GIR_RootConstrainSelectedInstOperands,
     /* 189431 */     // GIR_Coverage, 1682,
     /* 189431 */     GIR_EraseRootFromParent_Done,
     /* 189432 */   // Label 3528: @189432
     /* 189432 */   GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(189468), // Rule ID 1683 //
     /* 189437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fcvtxn),
     /* 189445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189455 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189459 */     // (intrinsic_wo_chain:{ *:[f32] } 812:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 189459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv1i64),
     /* 189462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189466 */     GIR_RootConstrainSelectedInstOperands,
     /* 189467 */     // GIR_Coverage, 1683,
     /* 189467 */     GIR_EraseRootFromParent_Done,
     /* 189468 */   // Label 3529: @189468
     /* 189468 */   GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(189504), // Rule ID 1701 //
     /* 189473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 189481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189484 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189495 */     // (intrinsic_wo_chain:{ *:[i64] } 703:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn)  =>  (SQABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 189495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
     /* 189498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189502 */     GIR_RootConstrainSelectedInstOperands,
     /* 189503 */     // GIR_Coverage, 1701,
     /* 189503 */     GIR_EraseRootFromParent_Done,
     /* 189504 */   // Label 3530: @189504
     /* 189504 */   GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(189540), // Rule ID 1702 //
     /* 189509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 189517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189527 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189531 */     // (intrinsic_wo_chain:{ *:[i32] } 703:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SQABSv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 189531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i32),
     /* 189534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189538 */     GIR_RootConstrainSelectedInstOperands,
     /* 189539 */     // GIR_Coverage, 1702,
     /* 189539 */     GIR_EraseRootFromParent_Done,
     /* 189540 */   // Label 3531: @189540
     /* 189540 */   GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(189576), // Rule ID 1703 //
     /* 189545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 189553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 189556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189563 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189567 */     // (intrinsic_wo_chain:{ *:[i64] } 710:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn)  =>  (SQNEGv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 189567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
     /* 189570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189574 */     GIR_RootConstrainSelectedInstOperands,
     /* 189575 */     // GIR_Coverage, 1703,
     /* 189575 */     GIR_EraseRootFromParent_Done,
     /* 189576 */   // Label 3532: @189576
     /* 189576 */   GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(189612), // Rule ID 1704 //
     /* 189581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 189589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 189595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189603 */     // (intrinsic_wo_chain:{ *:[i32] } 710:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SQNEGv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 189603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i32),
     /* 189606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189610 */     GIR_RootConstrainSelectedInstOperands,
     /* 189611 */     // GIR_Coverage, 1704,
     /* 189611 */     GIR_EraseRootFromParent_Done,
     /* 189612 */   // Label 3533: @189612
     /* 189612 */   GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(189648), // Rule ID 1705 //
     /* 189617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtn),
     /* 189625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189635 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189639 */     // (intrinsic_wo_chain:{ *:[f32] } 688:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (SQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 189639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv1i32),
     /* 189642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189646 */     GIR_RootConstrainSelectedInstOperands,
     /* 189647 */     // GIR_Coverage, 1705,
     /* 189647 */     GIR_EraseRootFromParent_Done,
     /* 189648 */   // Label 3534: @189648
     /* 189648 */   GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(189684), // Rule ID 1706 //
     /* 189653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_sqxtun),
     /* 189661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189671 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189675 */     // (intrinsic_wo_chain:{ *:[f32] } 689:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (SQXTUNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 189675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv1i32),
     /* 189678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189680 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189682 */     GIR_RootConstrainSelectedInstOperands,
     /* 189683 */     // GIR_Coverage, 1706,
     /* 189683 */     GIR_EraseRootFromParent_Done,
     /* 189684 */   // Label 3535: @189684
     /* 189684 */   GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(189720), // Rule ID 1712 //
     /* 189689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_scalar_uqxtn),
     /* 189697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 189703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189707 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189711 */     // (intrinsic_wo_chain:{ *:[f32] } 690:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (UQXTNv1i32:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 189711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv1i32),
     /* 189714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189718 */     GIR_RootConstrainSelectedInstOperands,
     /* 189719 */     // GIR_Coverage, 1712,
     /* 189719 */     GIR_EraseRootFromParent_Done,
     /* 189720 */   // Label 3536: @189720
     /* 189720 */   GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(189756), // Rule ID 1974 //
     /* 189725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 189733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189747 */     // (intrinsic_wo_chain:{ *:[f16] } 621:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 189747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
     /* 189750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189754 */     GIR_RootConstrainSelectedInstOperands,
     /* 189755 */     // GIR_Coverage, 1974,
     /* 189755 */     GIR_EraseRootFromParent_Done,
     /* 189756 */   // Label 3537: @189756
     /* 189756 */   GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(189792), // Rule ID 1976 //
     /* 189761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 189769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189779 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189783 */     // (intrinsic_wo_chain:{ *:[f16] } 621:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 189783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
     /* 189786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189790 */     GIR_RootConstrainSelectedInstOperands,
     /* 189791 */     // GIR_Coverage, 1976,
     /* 189791 */     GIR_EraseRootFromParent_Done,
     /* 189792 */   // Label 3538: @189792
     /* 189792 */   GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(189828), // Rule ID 1978 //
     /* 189797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 189805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189819 */     // (intrinsic_wo_chain:{ *:[f32] } 621:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 189819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
     /* 189822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189824 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189826 */     GIR_RootConstrainSelectedInstOperands,
     /* 189827 */     // GIR_Coverage, 1978,
     /* 189827 */     GIR_EraseRootFromParent_Done,
     /* 189828 */   // Label 3539: @189828
     /* 189828 */   GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(189864), // Rule ID 1980 //
     /* 189833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 189841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189851 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189855 */     // (intrinsic_wo_chain:{ *:[f16] } 623:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 189855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
     /* 189858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189860 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189862 */     GIR_RootConstrainSelectedInstOperands,
     /* 189863 */     // GIR_Coverage, 1980,
     /* 189863 */     GIR_EraseRootFromParent_Done,
     /* 189864 */   // Label 3540: @189864
     /* 189864 */   GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(189900), // Rule ID 1982 //
     /* 189869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 189877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189891 */     // (intrinsic_wo_chain:{ *:[f16] } 623:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 189891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
     /* 189894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189898 */     GIR_RootConstrainSelectedInstOperands,
     /* 189899 */     // GIR_Coverage, 1982,
     /* 189899 */     GIR_EraseRootFromParent_Done,
     /* 189900 */   // Label 3541: @189900
     /* 189900 */   GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(189936), // Rule ID 1984 //
     /* 189905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 189908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 189913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 189916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 189919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 189923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189927 */     // (intrinsic_wo_chain:{ *:[f32] } 623:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 189927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
     /* 189930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189932 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189934 */     GIR_RootConstrainSelectedInstOperands,
     /* 189935 */     // GIR_Coverage, 1984,
     /* 189935 */     GIR_EraseRootFromParent_Done,
     /* 189936 */   // Label 3542: @189936
     /* 189936 */   GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(189972), // Rule ID 1986 //
     /* 189941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 189949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 189955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189959 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 189963 */     // (intrinsic_wo_chain:{ *:[f16] } 627:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 189963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
     /* 189966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 189968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 189970 */     GIR_RootConstrainSelectedInstOperands,
     /* 189971 */     // GIR_Coverage, 1986,
     /* 189971 */     GIR_EraseRootFromParent_Done,
     /* 189972 */   // Label 3543: @189972
     /* 189972 */   GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(190008), // Rule ID 1988 //
     /* 189977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 189980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 189985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 189988 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 189991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 189995 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 189999 */     // (intrinsic_wo_chain:{ *:[f16] } 627:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 189999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
     /* 190002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190004 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190006 */     GIR_RootConstrainSelectedInstOperands,
     /* 190007 */     // GIR_Coverage, 1988,
     /* 190007 */     GIR_EraseRootFromParent_Done,
     /* 190008 */   // Label 3544: @190008
     /* 190008 */   GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(190044), // Rule ID 1990 //
     /* 190013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 190021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 190024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 190031 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190035 */     // (intrinsic_wo_chain:{ *:[f32] } 627:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 190035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
     /* 190038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190040 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190042 */     GIR_RootConstrainSelectedInstOperands,
     /* 190043 */     // GIR_Coverage, 1990,
     /* 190043 */     GIR_EraseRootFromParent_Done,
     /* 190044 */   // Label 3545: @190044
     /* 190044 */   GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(190080), // Rule ID 1992 //
     /* 190049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 190057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 190060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 190067 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190071 */     // (intrinsic_wo_chain:{ *:[f16] } 629:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn)  =>  (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 190071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
     /* 190074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190076 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190078 */     GIR_RootConstrainSelectedInstOperands,
     /* 190079 */     // GIR_Coverage, 1992,
     /* 190079 */     GIR_EraseRootFromParent_Done,
     /* 190080 */   // Label 3546: @190080
     /* 190080 */   GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(190116), // Rule ID 1994 //
     /* 190085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 190088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 190093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 190096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 190099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 190103 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190107 */     // (intrinsic_wo_chain:{ *:[f16] } 629:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn)  =>  (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 190107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
     /* 190110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190112 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190114 */     GIR_RootConstrainSelectedInstOperands,
     /* 190115 */     // GIR_Coverage, 1994,
     /* 190115 */     GIR_EraseRootFromParent_Done,
     /* 190116 */   // Label 3547: @190116
     /* 190116 */   GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(190152), // Rule ID 1996 //
     /* 190121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 190129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 190132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 190139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190143 */     // (intrinsic_wo_chain:{ *:[f32] } 629:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 190143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
     /* 190146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190150 */     GIR_RootConstrainSelectedInstOperands,
     /* 190151 */     // GIR_Coverage, 1996,
     /* 190151 */     GIR_EraseRootFromParent_Done,
     /* 190152 */   // Label 3548: @190152
     /* 190152 */   GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(190188), // Rule ID 2336 //
     /* 190157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 190160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesmc),
     /* 190165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 190168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 190171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190179 */     // (intrinsic_wo_chain:{ *:[v16i8] } 538:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (AESMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 190179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMCrr),
     /* 190182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190186 */     GIR_RootConstrainSelectedInstOperands,
     /* 190187 */     // GIR_Coverage, 2336,
     /* 190187 */     GIR_EraseRootFromParent_Done,
     /* 190188 */   // Label 3549: @190188
     /* 190188 */   GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(190224), // Rule ID 2337 //
     /* 190193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 190196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesimc),
     /* 190201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 190204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 190207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190215 */     // (intrinsic_wo_chain:{ *:[v16i8] } 537:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (AESIMCrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 190215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMCrr),
     /* 190218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190222 */     GIR_RootConstrainSelectedInstOperands,
     /* 190223 */     // GIR_Coverage, 2337,
     /* 190223 */     GIR_EraseRootFromParent_Done,
     /* 190224 */   // Label 3550: @190224
     /* 190224 */   GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(190260), // Rule ID 2345 //
     /* 190229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 190232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1h),
     /* 190237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 190240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 190243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 190247 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 190251 */     // (intrinsic_wo_chain:{ *:[i32] } 545:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn)  =>  (SHA1Hrr:{ *:[i32] } FPR32:{ *:[i32] }:$Rn)
     /* 190251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Hrr),
     /* 190254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190256 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190258 */     GIR_RootConstrainSelectedInstOperands,
     /* 190259 */     // GIR_Coverage, 2345,
     /* 190259 */     GIR_EraseRootFromParent_Done,
     /* 190260 */   // Label 3551: @190260
     /* 190260 */   GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(190296), // Rule ID 2549 //
     /* 190265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190268 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqabs),
     /* 190273 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190276 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190283 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190287 */     // (intrinsic_wo_chain:{ *:[v1i64] } 703:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (SQABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 190287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABSv1i64),
     /* 190290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190294 */     GIR_RootConstrainSelectedInstOperands,
     /* 190295 */     // GIR_Coverage, 2549,
     /* 190295 */     GIR_EraseRootFromParent_Done,
     /* 190296 */   // Label 3552: @190296
     /* 190296 */   GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(190335), // Rule ID 3630 //
     /* 190301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190304 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 190309 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 190312 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 190315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190319 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190323 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1679:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn)  =>  (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, 0:{ *:[i32] })
     /* 190323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
     /* 190326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 190328 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 190330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190333 */     GIR_RootConstrainSelectedInstOperands,
     /* 190334 */     // GIR_Coverage, 3630,
     /* 190334 */     GIR_EraseRootFromParent_Done,
     /* 190335 */   // Label 3553: @190335
     /* 190335 */   GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(190374), // Rule ID 3631 //
     /* 190340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 190348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 190351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 190354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190362 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1679:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn)  =>  (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, 0:{ *:[i32] })
     /* 190362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
     /* 190365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 190367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 190369 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190372 */     GIR_RootConstrainSelectedInstOperands,
     /* 190373 */     // GIR_Coverage, 3631,
     /* 190373 */     GIR_EraseRootFromParent_Done,
     /* 190374 */   // Label 3554: @190374
     /* 190374 */   GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(190413), // Rule ID 3632 //
     /* 190379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 190387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 190390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 190393 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190397 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190401 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1679:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn)  =>  (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, 0:{ *:[i32] })
     /* 190401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
     /* 190404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 190406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 190408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190411 */     GIR_RootConstrainSelectedInstOperands,
     /* 190412 */     // GIR_Coverage, 3632,
     /* 190412 */     GIR_EraseRootFromParent_Done,
     /* 190413 */   // Label 3555: @190413
     /* 190413 */   GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(190452), // Rule ID 3633 //
     /* 190418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane_zero),
     /* 190426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 190429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 190432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190436 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190440 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1679:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn)  =>  (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, 0:{ *:[i32] })
     /* 190440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
     /* 190443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 190445 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 190447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190450 */     GIR_RootConstrainSelectedInstOperands,
     /* 190451 */     // GIR_Coverage, 3633,
     /* 190451 */     GIR_EraseRootFromParent_Done,
     /* 190452 */   // Label 3556: @190452
     /* 190452 */   GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(190508), // Rule ID 3637 //
     /* 190457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 190465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 190468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 190471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190479 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1681:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn)  =>  (PMOV_ZIP_B:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i64] }, PPR8:{ *:[nxv16i1] }:$Pn)
     /* 190479 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 190482 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 190486 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 190491 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 190493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_B),
     /* 190496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 190498 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 190501 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 190506 */     GIR_RootConstrainSelectedInstOperands,
     /* 190507 */     // GIR_Coverage, 3637,
     /* 190507 */     GIR_EraseRootFromParent_Done,
     /* 190508 */   // Label 3557: @190508
     /* 190508 */   GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(190564), // Rule ID 3638 //
     /* 190513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 190521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 190524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 190527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190535 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1681:{ *:[iPTR] }, PPR16:{ *:[nxv8i1] }:$Pn)  =>  (PMOV_ZIP_H:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR16:{ *:[nxv8i1] }:$Pn)
     /* 190535 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 190538 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 190542 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 190547 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 190549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
     /* 190552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 190554 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 190557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 190562 */     GIR_RootConstrainSelectedInstOperands,
     /* 190563 */     // GIR_Coverage, 3638,
     /* 190563 */     GIR_EraseRootFromParent_Done,
     /* 190564 */   // Label 3558: @190564
     /* 190564 */   GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(190620), // Rule ID 3639 //
     /* 190569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 190577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 190580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 190583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190591 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1681:{ *:[iPTR] }, PPR32:{ *:[nxv4i1] }:$Pn)  =>  (PMOV_ZIP_S:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR32:{ *:[nxv4i1] }:$Pn)
     /* 190591 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 190594 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 190598 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 190603 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 190605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
     /* 190608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 190610 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 190613 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190616 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 190618 */     GIR_RootConstrainSelectedInstOperands,
     /* 190619 */     // GIR_Coverage, 3639,
     /* 190619 */     GIR_EraseRootFromParent_Done,
     /* 190620 */   // Label 3559: @190620
     /* 190620 */   GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(190676), // Rule ID 3640 //
     /* 190625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 190628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_zeroing),
     /* 190633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 190636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 190639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 190643 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 190647 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1681:{ *:[iPTR] }, PPR64:{ *:[nxv2i1] }:$Pn)  =>  (PMOV_ZIP_D:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), 0:{ *:[i32] }, PPR64:{ *:[nxv2i1] }:$Pn)
     /* 190647 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 190650 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 190654 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 190659 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 190661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
     /* 190664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 190666 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 190669 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 190672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 190674 */     GIR_RootConstrainSelectedInstOperands,
     /* 190675 */     // GIR_Coverage, 3640,
     /* 190675 */     GIR_EraseRootFromParent_Done,
     /* 190676 */   // Label 3560: @190676
     /* 190676 */   GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(190709), // Rule ID 4857 //
     /* 190681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32z),
     /* 190686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190696 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190700 */     // (intrinsic_wo_chain:{ *:[v1f64] } 661:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT32ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32ZDr),
     /* 190703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190705 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190707 */     GIR_RootConstrainSelectedInstOperands,
     /* 190708 */     // GIR_Coverage, 4857,
     /* 190708 */     GIR_EraseRootFromParent_Done,
     /* 190709 */   // Label 3561: @190709
     /* 190709 */   GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(190742), // Rule ID 4858 //
     /* 190714 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64z),
     /* 190719 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190729 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190733 */     // (intrinsic_wo_chain:{ *:[v1f64] } 663:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT64ZDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64ZDr),
     /* 190736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190740 */     GIR_RootConstrainSelectedInstOperands,
     /* 190741 */     // GIR_Coverage, 4858,
     /* 190741 */     GIR_EraseRootFromParent_Done,
     /* 190742 */   // Label 3562: @190742
     /* 190742 */   GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(190775), // Rule ID 4859 //
     /* 190747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint32x),
     /* 190752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190766 */     // (intrinsic_wo_chain:{ *:[v1f64] } 660:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT32XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT32XDr),
     /* 190769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190773 */     GIR_RootConstrainSelectedInstOperands,
     /* 190774 */     // GIR_Coverage, 4859,
     /* 190774 */     GIR_EraseRootFromParent_Done,
     /* 190775 */   // Label 3563: @190775
     /* 190775 */   GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(190808), // Rule ID 4860 //
     /* 190780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frint64x),
     /* 190785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190799 */     // (intrinsic_wo_chain:{ *:[v1f64] } 662:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRINT64XDr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190799 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRINT64XDr),
     /* 190802 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190804 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190806 */     GIR_RootConstrainSelectedInstOperands,
     /* 190807 */     // GIR_Coverage, 4860,
     /* 190807 */     GIR_EraseRootFromParent_Done,
     /* 190808 */   // Label 3564: @190808
     /* 190808 */   GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(190841), // Rule ID 4968 //
     /* 190813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvthf2fp),
     /* 190818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 190821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 190824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190832 */     // (intrinsic_wo_chain:{ *:[v4f32] } 792:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4i16] }:$Rn)
     /* 190832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 190835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190839 */     GIR_RootConstrainSelectedInstOperands,
     /* 190840 */     // GIR_Coverage, 4968,
     /* 190840 */     GIR_EraseRootFromParent_Done,
     /* 190841 */   // Label 3565: @190841
     /* 190841 */   GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(190874), // Rule ID 4978 //
     /* 190846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2hf),
     /* 190851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 190854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 190857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190861 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 190865 */     // (intrinsic_wo_chain:{ *:[v4i16] } 789:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNv4i16:{ *:[v4i16] } V128:{ *:[v4f32] }:$Rn)
     /* 190865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 190868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190872 */     GIR_RootConstrainSelectedInstOperands,
     /* 190873 */     // GIR_Coverage, 4978,
     /* 190873 */     GIR_EraseRootFromParent_Done,
     /* 190874 */   // Label 3566: @190874
     /* 190874 */   GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(190910), // Rule ID 5314 //
     /* 190879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 190882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqneg),
     /* 190887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190890 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190897 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190901 */     // (intrinsic_wo_chain:{ *:[v1i64] } 710:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn)  =>  (SQNEGv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 190901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEGv1i64),
     /* 190904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190906 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190908 */     GIR_RootConstrainSelectedInstOperands,
     /* 190909 */     // GIR_Coverage, 5314,
     /* 190909 */     GIR_EraseRootFromParent_Done,
     /* 190910 */   // Label 3567: @190910
     /* 190910 */   GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(190943), // Rule ID 5839 //
     /* 190915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtas),
     /* 190920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190930 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190934 */     // (intrinsic_wo_chain:{ *:[v1i64] } 607:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTASv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 190937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190941 */     GIR_RootConstrainSelectedInstOperands,
     /* 190942 */     // GIR_Coverage, 5839,
     /* 190942 */     GIR_EraseRootFromParent_Done,
     /* 190943 */   // Label 3568: @190943
     /* 190943 */   GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(190976), // Rule ID 5840 //
     /* 190948 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtau),
     /* 190953 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190956 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190963 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190967 */     // (intrinsic_wo_chain:{ *:[v1i64] } 608:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTAUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 190967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 190970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 190972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 190974 */     GIR_RootConstrainSelectedInstOperands,
     /* 190975 */     // GIR_Coverage, 5840,
     /* 190975 */     GIR_EraseRootFromParent_Done,
     /* 190976 */   // Label 3569: @190976
     /* 190976 */   GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(191009), // Rule ID 5841 //
     /* 190981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtms),
     /* 190986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 190989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 190992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 190996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191000 */     // (intrinsic_wo_chain:{ *:[v1i64] } 609:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTMSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 191003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191005 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191007 */     GIR_RootConstrainSelectedInstOperands,
     /* 191008 */     // GIR_Coverage, 5841,
     /* 191008 */     GIR_EraseRootFromParent_Done,
     /* 191009 */   // Label 3570: @191009
     /* 191009 */   GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(191042), // Rule ID 5842 //
     /* 191014 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtmu),
     /* 191019 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191029 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191033 */     // (intrinsic_wo_chain:{ *:[v1i64] } 610:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTMUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 191036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191040 */     GIR_RootConstrainSelectedInstOperands,
     /* 191041 */     // GIR_Coverage, 5842,
     /* 191041 */     GIR_EraseRootFromParent_Done,
     /* 191042 */   // Label 3571: @191042
     /* 191042 */   GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(191075), // Rule ID 5843 //
     /* 191047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtns),
     /* 191052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191062 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191066 */     // (intrinsic_wo_chain:{ *:[v1i64] } 611:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTNSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNSv1i64),
     /* 191069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191071 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191073 */     GIR_RootConstrainSelectedInstOperands,
     /* 191074 */     // GIR_Coverage, 5843,
     /* 191074 */     GIR_EraseRootFromParent_Done,
     /* 191075 */   // Label 3572: @191075
     /* 191075 */   GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(191108), // Rule ID 5844 //
     /* 191080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtnu),
     /* 191085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191099 */     // (intrinsic_wo_chain:{ *:[v1i64] } 612:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTNUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNUv1i64),
     /* 191102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191106 */     GIR_RootConstrainSelectedInstOperands,
     /* 191107 */     // GIR_Coverage, 5844,
     /* 191107 */     GIR_EraseRootFromParent_Done,
     /* 191108 */   // Label 3573: @191108
     /* 191108 */   GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(191141), // Rule ID 5845 //
     /* 191113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtps),
     /* 191118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191128 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191132 */     // (intrinsic_wo_chain:{ *:[v1i64] } 613:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTPSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 191135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191139 */     GIR_RootConstrainSelectedInstOperands,
     /* 191140 */     // GIR_Coverage, 5845,
     /* 191140 */     GIR_EraseRootFromParent_Done,
     /* 191141 */   // Label 3574: @191141
     /* 191141 */   GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(191174), // Rule ID 5846 //
     /* 191146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtpu),
     /* 191151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191165 */     // (intrinsic_wo_chain:{ *:[v1i64] } 614:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTPUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 191168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191170 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191172 */     GIR_RootConstrainSelectedInstOperands,
     /* 191173 */     // GIR_Coverage, 5846,
     /* 191173 */     GIR_EraseRootFromParent_Done,
     /* 191174 */   // Label 3575: @191174
     /* 191174 */   GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(191207), // Rule ID 5847 //
     /* 191179 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 191184 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191187 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191194 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191198 */     // (intrinsic_wo_chain:{ *:[v1i64] } 616:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 191201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191205 */     GIR_RootConstrainSelectedInstOperands,
     /* 191206 */     // GIR_Coverage, 5847,
     /* 191206 */     GIR_EraseRootFromParent_Done,
     /* 191207 */   // Label 3576: @191207
     /* 191207 */   GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(191240), // Rule ID 5848 //
     /* 191212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 191217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191227 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191231 */     // (intrinsic_wo_chain:{ *:[v1i64] } 617:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCVTZUv1i64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 191234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191238 */     GIR_RootConstrainSelectedInstOperands,
     /* 191239 */     // GIR_Coverage, 5848,
     /* 191239 */     GIR_EraseRootFromParent_Done,
     /* 191240 */   // Label 3577: @191240
     /* 191240 */   GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(191273), // Rule ID 5849 //
     /* 191245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 191250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 191253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 191256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191264 */     // (intrinsic_wo_chain:{ *:[f16] } 657:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRECPEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 191264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1f16),
     /* 191267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191271 */     GIR_RootConstrainSelectedInstOperands,
     /* 191272 */     // GIR_Coverage, 5849,
     /* 191272 */     GIR_EraseRootFromParent_Done,
     /* 191273 */   // Label 3578: @191273
     /* 191273 */   GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(191306), // Rule ID 5850 //
     /* 191278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 191283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 191289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191293 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191297 */     // (intrinsic_wo_chain:{ *:[f32] } 657:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRECPEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 191297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i32),
     /* 191300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191304 */     GIR_RootConstrainSelectedInstOperands,
     /* 191305 */     // GIR_Coverage, 5850,
     /* 191305 */     GIR_EraseRootFromParent_Done,
     /* 191306 */   // Label 3579: @191306
     /* 191306 */   GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(191339), // Rule ID 5851 //
     /* 191311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 191316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191326 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191330 */     // (intrinsic_wo_chain:{ *:[f64] } 657:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRECPEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 191330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
     /* 191333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191337 */     GIR_RootConstrainSelectedInstOperands,
     /* 191338 */     // GIR_Coverage, 5851,
     /* 191338 */     GIR_EraseRootFromParent_Done,
     /* 191339 */   // Label 3580: @191339
     /* 191339 */   GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(191372), // Rule ID 5852 //
     /* 191344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpe),
     /* 191349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191359 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191363 */     // (intrinsic_wo_chain:{ *:[v1f64] } 657:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRECPEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPEv1i64),
     /* 191366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191370 */     GIR_RootConstrainSelectedInstOperands,
     /* 191371 */     // GIR_Coverage, 5852,
     /* 191371 */     GIR_EraseRootFromParent_Done,
     /* 191372 */   // Label 3581: @191372
     /* 191372 */   GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(191405), // Rule ID 5864 //
     /* 191377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 191382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 191385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 191388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191396 */     // (intrinsic_wo_chain:{ *:[f16] } 659:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRECPXv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 191396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1f16),
     /* 191399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191403 */     GIR_RootConstrainSelectedInstOperands,
     /* 191404 */     // GIR_Coverage, 5864,
     /* 191404 */     GIR_EraseRootFromParent_Done,
     /* 191405 */   // Label 3582: @191405
     /* 191405 */   GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(191438), // Rule ID 5865 //
     /* 191410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 191415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 191421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191429 */     // (intrinsic_wo_chain:{ *:[f32] } 659:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRECPXv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 191429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i32),
     /* 191432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191434 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191436 */     GIR_RootConstrainSelectedInstOperands,
     /* 191437 */     // GIR_Coverage, 5865,
     /* 191437 */     GIR_EraseRootFromParent_Done,
     /* 191438 */   // Label 3583: @191438
     /* 191438 */   GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(191471), // Rule ID 5866 //
     /* 191443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecpx),
     /* 191448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191462 */     // (intrinsic_wo_chain:{ *:[f64] } 659:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRECPXv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 191462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPXv1i64),
     /* 191465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191467 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191469 */     GIR_RootConstrainSelectedInstOperands,
     /* 191470 */     // GIR_Coverage, 5866,
     /* 191470 */     GIR_EraseRootFromParent_Done,
     /* 191471 */   // Label 3584: @191471
     /* 191471 */   GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(191504), // Rule ID 5867 //
     /* 191476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 191481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 191484 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 191487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 191495 */     // (intrinsic_wo_chain:{ *:[f16] } 664:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn)  =>  (FRSQRTEv1f16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 191495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1f16),
     /* 191498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191502 */     GIR_RootConstrainSelectedInstOperands,
     /* 191503 */     // GIR_Coverage, 5867,
     /* 191503 */     GIR_EraseRootFromParent_Done,
     /* 191504 */   // Label 3585: @191504
     /* 191504 */   GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(191537), // Rule ID 5868 //
     /* 191509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 191514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 191520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191524 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191528 */     // (intrinsic_wo_chain:{ *:[f32] } 664:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn)  =>  (FRSQRTEv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 191528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i32),
     /* 191531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191535 */     GIR_RootConstrainSelectedInstOperands,
     /* 191536 */     // GIR_Coverage, 5868,
     /* 191536 */     GIR_EraseRootFromParent_Done,
     /* 191537 */   // Label 3586: @191537
     /* 191537 */   GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(191570), // Rule ID 5869 //
     /* 191542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 191547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191557 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191561 */     // (intrinsic_wo_chain:{ *:[f64] } 664:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn)  =>  (FRSQRTEv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 191561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
     /* 191564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191566 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191568 */     GIR_RootConstrainSelectedInstOperands,
     /* 191569 */     // GIR_Coverage, 5869,
     /* 191569 */     GIR_EraseRootFromParent_Done,
     /* 191570 */   // Label 3587: @191570
     /* 191570 */   GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(191603), // Rule ID 5870 //
     /* 191575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrte),
     /* 191580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 191586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191590 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191594 */     // (intrinsic_wo_chain:{ *:[v1f64] } 664:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FRSQRTEv1i64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 191594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTEv1i64),
     /* 191597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191599 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191601 */     GIR_RootConstrainSelectedInstOperands,
     /* 191602 */     // GIR_Coverage, 5870,
     /* 191602 */     GIR_EraseRootFromParent_Done,
     /* 191603 */   // Label 3588: @191603
     /* 191603 */   GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(191636), // Rule ID 6212 //
     /* 191608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 191613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191623 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191627 */     // (intrinsic_wo_chain:{ *:[f32] } 604:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 191627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 191630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191634 */     GIR_RootConstrainSelectedInstOperands,
     /* 191635 */     // GIR_Coverage, 6212,
     /* 191635 */     GIR_EraseRootFromParent_Done,
     /* 191636 */   // Label 3589: @191636
     /* 191636 */   GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(191721), // Rule ID 6213 //
     /* 191641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 191646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 191652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191656 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191660 */     // (intrinsic_wo_chain:{ *:[f32] } 604:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
     /* 191660 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 191663 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 191667 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 191672 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 191676 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 191680 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 191682 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 191685 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 191689 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 191694 */     GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 191701 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191706 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 191714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191716 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 191719 */     GIR_RootConstrainSelectedInstOperands,
     /* 191720 */     // GIR_Coverage, 6213,
     /* 191720 */     GIR_EraseRootFromParent_Done,
     /* 191721 */   // Label 3590: @191721
     /* 191721 */   GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(191754), // Rule ID 6214 //
     /* 191726 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddv),
     /* 191731 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191734 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191741 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191745 */     // (intrinsic_wo_chain:{ *:[f64] } 604:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 191745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 191748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191752 */     GIR_RootConstrainSelectedInstOperands,
     /* 191753 */     // GIR_Coverage, 6214,
     /* 191753 */     GIR_EraseRootFromParent_Done,
     /* 191754 */   // Label 3591: @191754
     /* 191754 */   GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(191787), // Rule ID 6216 //
     /* 191759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 191764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191774 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191778 */     // (intrinsic_wo_chain:{ *:[f32] } 621:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 191778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
     /* 191781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191785 */     GIR_RootConstrainSelectedInstOperands,
     /* 191786 */     // GIR_Coverage, 6216,
     /* 191786 */     GIR_EraseRootFromParent_Done,
     /* 191787 */   // Label 3592: @191787
     /* 191787 */   GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(191820), // Rule ID 6218 //
     /* 191792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmv),
     /* 191797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191807 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191811 */     // (intrinsic_wo_chain:{ *:[f64] } 621:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 191811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
     /* 191814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191818 */     GIR_RootConstrainSelectedInstOperands,
     /* 191819 */     // GIR_Coverage, 6218,
     /* 191819 */     GIR_EraseRootFromParent_Done,
     /* 191820 */   // Label 3593: @191820
     /* 191820 */   GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(191853), // Rule ID 6220 //
     /* 191825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 191830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191844 */     // (intrinsic_wo_chain:{ *:[f32] } 623:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 191844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
     /* 191847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191851 */     GIR_RootConstrainSelectedInstOperands,
     /* 191852 */     // GIR_Coverage, 6220,
     /* 191852 */     GIR_EraseRootFromParent_Done,
     /* 191853 */   // Label 3594: @191853
     /* 191853 */   GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(191886), // Rule ID 6222 //
     /* 191858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxv),
     /* 191863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191873 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191877 */     // (intrinsic_wo_chain:{ *:[f64] } 623:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 191877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
     /* 191880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191882 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191884 */     GIR_RootConstrainSelectedInstOperands,
     /* 191885 */     // GIR_Coverage, 6222,
     /* 191885 */     GIR_EraseRootFromParent_Done,
     /* 191886 */   // Label 3595: @191886
     /* 191886 */   GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(191919), // Rule ID 6224 //
     /* 191891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 191896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191906 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191910 */     // (intrinsic_wo_chain:{ *:[f32] } 627:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 191910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
     /* 191913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191915 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191917 */     GIR_RootConstrainSelectedInstOperands,
     /* 191918 */     // GIR_Coverage, 6224,
     /* 191918 */     GIR_EraseRootFromParent_Done,
     /* 191919 */   // Label 3596: @191919
     /* 191919 */   GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(191952), // Rule ID 6226 //
     /* 191924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmv),
     /* 191929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 191935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 191943 */     // (intrinsic_wo_chain:{ *:[f64] } 627:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 191943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
     /* 191946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191948 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191950 */     GIR_RootConstrainSelectedInstOperands,
     /* 191951 */     // GIR_Coverage, 6226,
     /* 191951 */     GIR_EraseRootFromParent_Done,
     /* 191952 */   // Label 3597: @191952
     /* 191952 */   GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(191985), // Rule ID 6228 //
     /* 191957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 191962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 191965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 191968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 191972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 191976 */     // (intrinsic_wo_chain:{ *:[f32] } 629:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn)  =>  (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 191976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
     /* 191979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 191981 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 191983 */     GIR_RootConstrainSelectedInstOperands,
     /* 191984 */     // GIR_Coverage, 6228,
     /* 191984 */     GIR_EraseRootFromParent_Done,
     /* 191985 */   // Label 3598: @191985
     /* 191985 */   GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(192018), // Rule ID 6230 //
     /* 191990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminv),
     /* 191995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 191998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 192001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192005 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192009 */     // (intrinsic_wo_chain:{ *:[f64] } 629:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn)  =>  (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 192009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
     /* 192012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192016 */     GIR_RootConstrainSelectedInstOperands,
     /* 192017 */     // GIR_Coverage, 6230,
     /* 192017 */     GIR_EraseRootFromParent_Done,
     /* 192018 */   // Label 3599: @192018
     /* 192018 */   GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(192051), // Rule ID 14184 //
     /* 192023 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192028 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 192031 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 192034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 192038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192042 */     // (intrinsic_wo_chain:{ *:[i8] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 192042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 192045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192047 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192049 */     GIR_RootConstrainSelectedInstOperands,
     /* 192050 */     // GIR_Coverage, 14184,
     /* 192050 */     GIR_EraseRootFromParent_Done,
     /* 192051 */   // Label 3600: @192051
     /* 192051 */   GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(192084), // Rule ID 14186 //
     /* 192056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 192064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 192067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 192071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192075 */     // (intrinsic_wo_chain:{ *:[i8] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 192075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 192078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192082 */     GIR_RootConstrainSelectedInstOperands,
     /* 192083 */     // GIR_Coverage, 14186,
     /* 192083 */     GIR_EraseRootFromParent_Done,
     /* 192084 */   // Label 3601: @192084
     /* 192084 */   GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(192117), // Rule ID 14188 //
     /* 192089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 192097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 192104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192108 */     // (intrinsic_wo_chain:{ *:[i16] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 192108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 192111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192113 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192115 */     GIR_RootConstrainSelectedInstOperands,
     /* 192116 */     // GIR_Coverage, 14188,
     /* 192116 */     GIR_EraseRootFromParent_Done,
     /* 192117 */   // Label 3602: @192117
     /* 192117 */   GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(192150), // Rule ID 14190 //
     /* 192122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 192130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 192137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192141 */     // (intrinsic_wo_chain:{ *:[i16] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 192141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 192144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192148 */     GIR_RootConstrainSelectedInstOperands,
     /* 192149 */     // GIR_Coverage, 14190,
     /* 192149 */     GIR_EraseRootFromParent_Done,
     /* 192150 */   // Label 3603: @192150
     /* 192150 */   GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(192265), // Rule ID 14191 //
     /* 192155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 192163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192166 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192170 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192174 */     // (intrinsic_wo_chain:{ *:[i32] } 687:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 192174 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 192177 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 192181 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192186 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192190 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192192 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 192195 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192199 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192204 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192206 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 192209 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192213 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192218 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192221 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192224 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 192227 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192232 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192237 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192247 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 192254 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192259 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192264 */     // GIR_Coverage, 14191,
     /* 192264 */     GIR_EraseRootFromParent_Done,
     /* 192265 */   // Label 3604: @192265
     /* 192265 */   GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(192298), // Rule ID 14193 //
     /* 192270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 192278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 192281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 192285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192289 */     // (intrinsic_wo_chain:{ *:[i8] } 752:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 192289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 192292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192294 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192296 */     GIR_RootConstrainSelectedInstOperands,
     /* 192297 */     // GIR_Coverage, 14193,
     /* 192297 */     GIR_EraseRootFromParent_Done,
     /* 192298 */   // Label 3605: @192298
     /* 192298 */   GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(192331), // Rule ID 14195 //
     /* 192303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 192311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 192314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 192318 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192322 */     // (intrinsic_wo_chain:{ *:[i8] } 752:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 192322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 192325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192329 */     GIR_RootConstrainSelectedInstOperands,
     /* 192330 */     // GIR_Coverage, 14195,
     /* 192330 */     GIR_EraseRootFromParent_Done,
     /* 192331 */   // Label 3606: @192331
     /* 192331 */   GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(192364), // Rule ID 14197 //
     /* 192336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 192344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 192347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 192351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192355 */     // (intrinsic_wo_chain:{ *:[i16] } 752:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 192355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 192358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192362 */     GIR_RootConstrainSelectedInstOperands,
     /* 192363 */     // GIR_Coverage, 14197,
     /* 192363 */     GIR_EraseRootFromParent_Done,
     /* 192364 */   // Label 3607: @192364
     /* 192364 */   GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(192397), // Rule ID 14199 //
     /* 192369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 192377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 192380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 192384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192388 */     // (intrinsic_wo_chain:{ *:[i16] } 752:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 192388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 192391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 192393 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 192395 */     GIR_RootConstrainSelectedInstOperands,
     /* 192396 */     // GIR_Coverage, 14199,
     /* 192396 */     GIR_EraseRootFromParent_Done,
     /* 192397 */   // Label 3608: @192397
     /* 192397 */   GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(192512), // Rule ID 14200 //
     /* 192402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 192410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 192413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192417 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192421 */     // (intrinsic_wo_chain:{ *:[i32] } 752:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 192421 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 192424 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 192428 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192433 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192437 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192439 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 192442 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192446 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192451 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192453 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 192456 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192460 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192465 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192468 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192471 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 192474 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192479 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192484 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192494 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 192501 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192506 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192511 */     // GIR_Coverage, 14200,
     /* 192511 */     GIR_EraseRootFromParent_Done,
     /* 192512 */   // Label 3609: @192512
     /* 192512 */   GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(192631), // Rule ID 14201 //
     /* 192517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 192525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192532 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192536 */     // (intrinsic_wo_chain:{ *:[i32] } 687:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 192536 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 192539 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 192543 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192548 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192552 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192556 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192558 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 192561 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192565 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192570 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192572 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 192575 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192579 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192584 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192587 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192590 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 192593 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192598 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192603 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192613 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 192620 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192625 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192630 */     // GIR_Coverage, 14201,
     /* 192630 */     GIR_EraseRootFromParent_Done,
     /* 192631 */   // Label 3610: @192631
     /* 192631 */   GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(192746), // Rule ID 14202 //
     /* 192636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 192641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 192644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 192647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192651 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192655 */     // (intrinsic_wo_chain:{ *:[i64] } 687:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
     /* 192655 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 192658 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 192662 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192667 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192671 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192673 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 192676 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192680 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192685 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192687 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 192690 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192694 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192699 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192702 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192705 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 192708 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192713 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192718 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192728 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 192735 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192740 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192745 */     // GIR_Coverage, 14202,
     /* 192745 */     GIR_EraseRootFromParent_Done,
     /* 192746 */   // Label 3611: @192746
     /* 192746 */   GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(192865), // Rule ID 14203 //
     /* 192751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 192759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 192762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192766 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192770 */     // (intrinsic_wo_chain:{ *:[i32] } 752:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 192770 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 192773 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 192777 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192782 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192786 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192790 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192792 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 192795 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192799 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192804 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192806 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 192809 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192813 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192818 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192821 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192824 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 192827 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192832 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192837 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192847 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 192854 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 192859 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192864 */     // GIR_Coverage, 14203,
     /* 192864 */     GIR_EraseRootFromParent_Done,
     /* 192865 */   // Label 3612: @192865
     /* 192865 */   GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(192980), // Rule ID 14204 //
     /* 192870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 192875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 192878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 192881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192889 */     // (intrinsic_wo_chain:{ *:[i64] } 752:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn), dsub:{ *:[i32] }), dsub:{ *:[i32] })
     /* 192889 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 192892 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 192896 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192901 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 192905 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 192907 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 192910 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 192914 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 192921 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 192924 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 192928 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 192933 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 192936 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 192939 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 192942 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192947 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192952 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 192960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 192962 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 192969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 192974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 192979 */     // GIR_Coverage, 14204,
     /* 192979 */     GIR_EraseRootFromParent_Done,
     /* 192980 */   // Label 3613: @192980
     /* 192980 */   GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(193013), // Rule ID 14206 //
     /* 192985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 192990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 192993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 192996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193004 */     // (intrinsic_wo_chain:{ *:[i8] } 697:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 193004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 193007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193009 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193011 */     GIR_RootConstrainSelectedInstOperands,
     /* 193012 */     // GIR_Coverage, 14206,
     /* 193012 */     GIR_EraseRootFromParent_Done,
     /* 193013 */   // Label 3614: @193013
     /* 193013 */   GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(193046), // Rule ID 14208 //
     /* 193018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 193023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 193026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193033 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193037 */     // (intrinsic_wo_chain:{ *:[i8] } 697:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 193037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 193040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193042 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193044 */     GIR_RootConstrainSelectedInstOperands,
     /* 193045 */     // GIR_Coverage, 14208,
     /* 193045 */     GIR_EraseRootFromParent_Done,
     /* 193046 */   // Label 3615: @193046
     /* 193046 */   GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(193079), // Rule ID 14210 //
     /* 193051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 193056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193066 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193070 */     // (intrinsic_wo_chain:{ *:[i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 193070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 193073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193077 */     GIR_RootConstrainSelectedInstOperands,
     /* 193078 */     // GIR_Coverage, 14210,
     /* 193078 */     GIR_EraseRootFromParent_Done,
     /* 193079 */   // Label 3616: @193079
     /* 193079 */   GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(193112), // Rule ID 14212 //
     /* 193084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 193089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193099 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193103 */     // (intrinsic_wo_chain:{ *:[i16] } 697:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 193103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 193106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193110 */     GIR_RootConstrainSelectedInstOperands,
     /* 193111 */     // GIR_Coverage, 14212,
     /* 193111 */     GIR_EraseRootFromParent_Done,
     /* 193112 */   // Label 3617: @193112
     /* 193112 */   GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(193227), // Rule ID 14213 //
     /* 193117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 193122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193136 */     // (intrinsic_wo_chain:{ *:[i32] } 697:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193136 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 193139 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
     /* 193143 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193148 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193152 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 193154 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 193157 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 193161 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193166 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 193168 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 193171 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 193175 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193180 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 193183 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 193186 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 193189 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193194 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193199 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 193207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 193209 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 193216 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193221 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193226 */     // GIR_Coverage, 14213,
     /* 193226 */     GIR_EraseRootFromParent_Done,
     /* 193227 */   // Label 3618: @193227
     /* 193227 */   GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(193346), // Rule ID 14214 //
     /* 193232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 193237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193247 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193251 */     // (intrinsic_wo_chain:{ *:[i32] } 697:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193251 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 193254 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 193258 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193263 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193267 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193271 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 193273 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 193276 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 193280 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193285 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 193287 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 193290 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 193294 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193299 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 193302 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 193305 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 193308 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193313 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193318 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 193326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 193328 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 193335 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193340 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193345 */     // GIR_Coverage, 14214,
     /* 193345 */     GIR_EraseRootFromParent_Done,
     /* 193346 */   // Label 3619: @193346
     /* 193346 */   GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(193379), // Rule ID 14216 //
     /* 193351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 193359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 193362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193370 */     // (intrinsic_wo_chain:{ *:[i8] } 700:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 193370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 193373 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193375 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193377 */     GIR_RootConstrainSelectedInstOperands,
     /* 193378 */     // GIR_Coverage, 14216,
     /* 193378 */     GIR_EraseRootFromParent_Done,
     /* 193379 */   // Label 3620: @193379
     /* 193379 */   GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(193412), // Rule ID 14218 //
     /* 193384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 193392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193403 */     // (intrinsic_wo_chain:{ *:[i8] } 700:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 193403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 193406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193410 */     GIR_RootConstrainSelectedInstOperands,
     /* 193411 */     // GIR_Coverage, 14218,
     /* 193411 */     GIR_EraseRootFromParent_Done,
     /* 193412 */   // Label 3621: @193412
     /* 193412 */   GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(193445), // Rule ID 14220 //
     /* 193417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193436 */     // (intrinsic_wo_chain:{ *:[i16] } 700:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 193436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 193439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193443 */     GIR_RootConstrainSelectedInstOperands,
     /* 193444 */     // GIR_Coverage, 14220,
     /* 193444 */     GIR_EraseRootFromParent_Done,
     /* 193445 */   // Label 3622: @193445
     /* 193445 */   GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(193478), // Rule ID 14222 //
     /* 193450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193469 */     // (intrinsic_wo_chain:{ *:[i16] } 700:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 193469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 193472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193476 */     GIR_RootConstrainSelectedInstOperands,
     /* 193477 */     // GIR_Coverage, 14222,
     /* 193477 */     GIR_EraseRootFromParent_Done,
     /* 193478 */   // Label 3623: @193478
     /* 193478 */   GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(193593), // Rule ID 14223 //
     /* 193483 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193488 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193502 */     // (intrinsic_wo_chain:{ *:[i32] } 700:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193502 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 193505 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
     /* 193509 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193514 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193518 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 193520 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 193523 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 193527 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193532 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 193534 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 193537 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 193541 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193546 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 193549 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 193552 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 193555 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193560 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193565 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 193573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 193575 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 193582 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193587 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193592 */     // GIR_Coverage, 14223,
     /* 193592 */     GIR_EraseRootFromParent_Done,
     /* 193593 */   // Label 3624: @193593
     /* 193593 */   GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(193712), // Rule ID 14224 //
     /* 193598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 193603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193617 */     // (intrinsic_wo_chain:{ *:[i32] } 700:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193617 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 193620 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 193624 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193629 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193633 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193637 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 193639 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 193642 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 193646 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193651 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 193653 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 193656 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 193660 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193665 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 193668 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 193671 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 193674 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193679 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193684 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 193692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 193694 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 193701 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193706 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193711 */     // GIR_Coverage, 14224,
     /* 193711 */     GIR_EraseRootFromParent_Done,
     /* 193712 */   // Label 3625: @193712
     /* 193712 */   GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(193745), // Rule ID 14226 //
     /* 193717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193722 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 193725 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 193728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193736 */     // (intrinsic_wo_chain:{ *:[i8] } 758:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 193736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 193739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193743 */     GIR_RootConstrainSelectedInstOperands,
     /* 193744 */     // GIR_Coverage, 14226,
     /* 193744 */     GIR_EraseRootFromParent_Done,
     /* 193745 */   // Label 3626: @193745
     /* 193745 */   GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(193778), // Rule ID 14228 //
     /* 193750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 193758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 193761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 193765 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193769 */     // (intrinsic_wo_chain:{ *:[i8] } 758:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 193769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 193772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193776 */     GIR_RootConstrainSelectedInstOperands,
     /* 193777 */     // GIR_Coverage, 14228,
     /* 193777 */     GIR_EraseRootFromParent_Done,
     /* 193778 */   // Label 3627: @193778
     /* 193778 */   GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(193811), // Rule ID 14230 //
     /* 193783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 193794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193798 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193802 */     // (intrinsic_wo_chain:{ *:[i16] } 758:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 193802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 193805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193809 */     GIR_RootConstrainSelectedInstOperands,
     /* 193810 */     // GIR_Coverage, 14230,
     /* 193810 */     GIR_EraseRootFromParent_Done,
     /* 193811 */   // Label 3628: @193811
     /* 193811 */   GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(193844), // Rule ID 14232 //
     /* 193816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 193824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 193827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 193831 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193835 */     // (intrinsic_wo_chain:{ *:[i16] } 758:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 193835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 193838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 193840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 193842 */     GIR_RootConstrainSelectedInstOperands,
     /* 193843 */     // GIR_Coverage, 14232,
     /* 193843 */     GIR_EraseRootFromParent_Done,
     /* 193844 */   // Label 3629: @193844
     /* 193844 */   GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(193959), // Rule ID 14233 //
     /* 193849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 193860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193868 */     // (intrinsic_wo_chain:{ *:[i32] } 758:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193868 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 193871 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
     /* 193875 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193880 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193884 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 193886 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 193889 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 193893 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193898 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 193900 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 193903 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 193907 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193912 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 193915 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 193918 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 193921 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193926 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193931 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 193939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 193941 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 193948 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193953 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 193958 */     // GIR_Coverage, 14233,
     /* 193958 */     GIR_EraseRootFromParent_Done,
     /* 193959 */   // Label 3630: @193959
     /* 193959 */   GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(194078), // Rule ID 14234 //
     /* 193964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 193969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 193972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 193975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 193979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 193983 */     // (intrinsic_wo_chain:{ *:[i32] } 758:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 193983 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 193986 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 193990 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 193995 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 193999 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 194003 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 194005 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 194008 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 194012 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194017 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 194019 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 194022 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 194026 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194031 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 194034 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 194037 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 194040 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194045 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194050 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 194058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 194060 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 194067 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194077 */     // GIR_Coverage, 14234,
     /* 194077 */     GIR_EraseRootFromParent_Done,
     /* 194078 */   // Label 3631: @194078
     /* 194078 */   GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(194111), // Rule ID 14236 //
     /* 194083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 194091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 194094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 194098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194102 */     // (intrinsic_wo_chain:{ *:[i8] } 761:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 194102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 194105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194109 */     GIR_RootConstrainSelectedInstOperands,
     /* 194110 */     // GIR_Coverage, 14236,
     /* 194110 */     GIR_EraseRootFromParent_Done,
     /* 194111 */   // Label 3632: @194111
     /* 194111 */   GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(194144), // Rule ID 14238 //
     /* 194116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8,
     /* 194124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 194127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 194131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194135 */     // (intrinsic_wo_chain:{ *:[i8] } 761:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 194135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 194138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194142 */     GIR_RootConstrainSelectedInstOperands,
     /* 194143 */     // GIR_Coverage, 14238,
     /* 194143 */     GIR_EraseRootFromParent_Done,
     /* 194144 */   // Label 3633: @194144
     /* 194144 */   GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(194177), // Rule ID 14240 //
     /* 194149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 194157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 194160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 194164 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194168 */     // (intrinsic_wo_chain:{ *:[i16] } 761:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn)  =>  (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 194168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 194171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194175 */     GIR_RootConstrainSelectedInstOperands,
     /* 194176 */     // GIR_Coverage, 14240,
     /* 194176 */     GIR_EraseRootFromParent_Done,
     /* 194177 */   // Label 3634: @194177
     /* 194177 */   GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(194210), // Rule ID 14242 //
     /* 194182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 194190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 194193 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 194197 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194201 */     // (intrinsic_wo_chain:{ *:[i16] } 761:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn)  =>  (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 194201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 194204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194208 */     GIR_RootConstrainSelectedInstOperands,
     /* 194209 */     // GIR_Coverage, 14242,
     /* 194209 */     GIR_EraseRootFromParent_Done,
     /* 194210 */   // Label 3635: @194210
     /* 194210 */   GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(194325), // Rule ID 14243 //
     /* 194215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 194223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 194226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194230 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194234 */     // (intrinsic_wo_chain:{ *:[i32] } 761:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn), ssub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 194234 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 194237 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
     /* 194241 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194246 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 194250 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 194252 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 194255 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 194259 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194264 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 194266 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 194269 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 194273 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194278 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 194281 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 194284 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 194287 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194292 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194297 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 194305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 194307 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 194314 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194319 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194324 */     // GIR_Coverage, 14243,
     /* 194324 */     GIR_EraseRootFromParent_Done,
     /* 194325 */   // Label 3636: @194325
     /* 194325 */   GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(194444), // Rule ID 14244 //
     /* 194330 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 194335 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 194338 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 194341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194345 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194349 */     // (intrinsic_wo_chain:{ *:[i32] } 761:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] }), ssub:{ *:[i32] })
     /* 194349 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 194352 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 194356 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194361 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 194365 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 194369 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 194371 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 194374 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 194378 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194383 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 194385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 194388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 194392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 194397 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 194400 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 194403 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 194406 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194411 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194416 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 194424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 194426 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 194433 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 194438 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194443 */     // GIR_Coverage, 14244,
     /* 194443 */     GIR_EraseRootFromParent_Done,
     /* 194444 */   // Label 3637: @194444
     /* 194444 */   GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(194476), // Rule ID 2426 //
     /* 194449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b16),
     /* 194457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 194460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 194463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194467 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1721:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 194467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_H),
     /* 194470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 194474 */     GIR_RootConstrainSelectedInstOperands,
     /* 194475 */     // GIR_Coverage, 2426,
     /* 194475 */     GIR_EraseRootFromParent_Done,
     /* 194476 */   // Label 3638: @194476
     /* 194476 */   GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(194508), // Rule ID 2427 //
     /* 194481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194484 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b32),
     /* 194489 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 194492 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 194495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194499 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1722:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 194499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_S),
     /* 194502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 194506 */     GIR_RootConstrainSelectedInstOperands,
     /* 194507 */     // GIR_Coverage, 2427,
     /* 194507 */     GIR_EraseRootFromParent_Done,
     /* 194508 */   // Label 3639: @194508
     /* 194508 */   GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(194540), // Rule ID 2428 //
     /* 194513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rev_b64),
     /* 194521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 194524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 194527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194531 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1723:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn)  =>  (REV_PP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn)
     /* 194531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV_PP_D),
     /* 194534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 194538 */     GIR_RootConstrainSelectedInstOperands,
     /* 194539 */     // GIR_Coverage, 2428,
     /* 194539 */     GIR_EraseRootFromParent_Done,
     /* 194540 */   // Label 3640: @194540
     /* 194540 */   GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(194572), // Rule ID 3159 //
     /* 194545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 194548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 194553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 194556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 194559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194563 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1906:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (SQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 194563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_B),
     /* 194566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194570 */     GIR_RootConstrainSelectedInstOperands,
     /* 194571 */     // GIR_Coverage, 3159,
     /* 194571 */     GIR_EraseRootFromParent_Done,
     /* 194572 */   // Label 3641: @194572
     /* 194572 */   GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(194604), // Rule ID 3160 //
     /* 194577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 194580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 194585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 194588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 194591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194595 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1906:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (SQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 194595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_H),
     /* 194598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194602 */     GIR_RootConstrainSelectedInstOperands,
     /* 194603 */     // GIR_Coverage, 3160,
     /* 194603 */     GIR_EraseRootFromParent_Done,
     /* 194604 */   // Label 3642: @194604
     /* 194604 */   GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(194636), // Rule ID 3161 //
     /* 194609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 194612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnb),
     /* 194617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 194620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 194623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194627 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1906:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (SQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 194627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNB_ZZ_S),
     /* 194630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194634 */     GIR_RootConstrainSelectedInstOperands,
     /* 194635 */     // GIR_Coverage, 3161,
     /* 194635 */     GIR_EraseRootFromParent_Done,
     /* 194636 */   // Label 3643: @194636
     /* 194636 */   GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(194668), // Rule ID 3419 //
     /* 194641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 194649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 194652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 194655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194659 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1714:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
     /* 194659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 194662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194666 */     GIR_RootConstrainSelectedInstOperands,
     /* 194667 */     // GIR_Coverage, 3419,
     /* 194667 */     GIR_EraseRootFromParent_Done,
     /* 194668 */   // Label 3644: @194668
     /* 194668 */   GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(194700), // Rule ID 3420 //
     /* 194673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 194681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 194684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 194687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194691 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1714:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
     /* 194691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 194694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194698 */     GIR_RootConstrainSelectedInstOperands,
     /* 194699 */     // GIR_Coverage, 3420,
     /* 194699 */     GIR_EraseRootFromParent_Done,
     /* 194700 */   // Label 3645: @194700
     /* 194700 */   GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(194732), // Rule ID 3421 //
     /* 194705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 194708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpklo),
     /* 194713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 194716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 194719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 194723 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1714:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (PUNPKLO_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
     /* 194723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 194726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 194728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194730 */     GIR_RootConstrainSelectedInstOperands,
     /* 194731 */     // GIR_Coverage, 3421,
     /* 194731 */     GIR_EraseRootFromParent_Done,
     /* 194732 */   // Label 3646: @194732
     /* 194732 */   GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(194764), // Rule ID 3511 //
     /* 194737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 194740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 194745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 194748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 194751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194755 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1458:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (FEXPA_ZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i16] }:$Op1)
     /* 194755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_H),
     /* 194758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194760 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194762 */     GIR_RootConstrainSelectedInstOperands,
     /* 194763 */     // GIR_Coverage, 3511,
     /* 194763 */     GIR_EraseRootFromParent_Done,
     /* 194764 */   // Label 3647: @194764
     /* 194764 */   GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(194796), // Rule ID 3512 //
     /* 194769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 194772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 194777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 194780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 194783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194787 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1458:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (FEXPA_ZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i32] }:$Op1)
     /* 194787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_S),
     /* 194790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194794 */     GIR_RootConstrainSelectedInstOperands,
     /* 194795 */     // GIR_Coverage, 3512,
     /* 194795 */     GIR_EraseRootFromParent_Done,
     /* 194796 */   // Label 3648: @194796
     /* 194796 */   GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(194828), // Rule ID 3513 //
     /* 194801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_FEXPA),
     /* 194804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fexpa_x),
     /* 194809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 194812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 194815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194819 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1458:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (FEXPA_ZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i64] }:$Op1)
     /* 194819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FEXPA_ZZ_D),
     /* 194822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 194824 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194826 */     GIR_RootConstrainSelectedInstOperands,
     /* 194827 */     // GIR_Coverage, 3513,
     /* 194827 */     GIR_EraseRootFromParent_Done,
     /* 194828 */   // Label 3649: @194828
     /* 194828 */   GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(194860), // Rule ID 3538 //
     /* 194833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 194836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesmc),
     /* 194841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 194844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 194847 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 194851 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1292:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (AESMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
     /* 194851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESMC_ZZ_B),
     /* 194854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 194856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 194858 */     GIR_RootConstrainSelectedInstOperands,
     /* 194859 */     // GIR_Coverage, 3538,
     /* 194859 */     GIR_EraseRootFromParent_Done,
     /* 194860 */   // Label 3650: @194860
     /* 194860 */   GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(194889), // Rule ID 5008 //
     /* 194865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 194870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 194873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 194876 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194880 */     // (intrinsic_wo_chain:{ *:[v4i16] } 616:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
     /* 194880 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 194883 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194885 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194887 */     GIR_RootConstrainSelectedInstOperands,
     /* 194888 */     // GIR_Coverage, 5008,
     /* 194888 */     GIR_EraseRootFromParent_Done,
     /* 194889 */   // Label 3651: @194889
     /* 194889 */   GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(194918), // Rule ID 5009 //
     /* 194894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 194899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 194902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 194905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194909 */     // (intrinsic_wo_chain:{ *:[v8i16] } 616:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
     /* 194909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 194912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194916 */     GIR_RootConstrainSelectedInstOperands,
     /* 194917 */     // GIR_Coverage, 5009,
     /* 194917 */     GIR_EraseRootFromParent_Done,
     /* 194918 */   // Label 3652: @194918
     /* 194918 */   GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(194947), // Rule ID 5010 //
     /* 194923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 194928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 194931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 194934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 194938 */     // (intrinsic_wo_chain:{ *:[v2i32] } 616:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
     /* 194938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 194941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194945 */     GIR_RootConstrainSelectedInstOperands,
     /* 194946 */     // GIR_Coverage, 5010,
     /* 194946 */     GIR_EraseRootFromParent_Done,
     /* 194947 */   // Label 3653: @194947
     /* 194947 */   GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(194976), // Rule ID 5011 //
     /* 194952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 194957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 194960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 194963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194967 */     // (intrinsic_wo_chain:{ *:[v4i32] } 616:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
     /* 194967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 194970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 194972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 194974 */     GIR_RootConstrainSelectedInstOperands,
     /* 194975 */     // GIR_Coverage, 5011,
     /* 194975 */     GIR_EraseRootFromParent_Done,
     /* 194976 */   // Label 3654: @194976
     /* 194976 */   GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(195005), // Rule ID 5012 //
     /* 194981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 194986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 194989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 194992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 194996 */     // (intrinsic_wo_chain:{ *:[v2i64] } 616:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
     /* 194996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 194999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195003 */     GIR_RootConstrainSelectedInstOperands,
     /* 195004 */     // GIR_Coverage, 5012,
     /* 195004 */     GIR_EraseRootFromParent_Done,
     /* 195005 */   // Label 3655: @195005
     /* 195005 */   GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(195034), // Rule ID 5013 //
     /* 195010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 195018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 195021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195025 */     // (intrinsic_wo_chain:{ *:[v4i16] } 617:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } ?:{ *:[v4f16] }:$Rn)
     /* 195025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 195028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195032 */     GIR_RootConstrainSelectedInstOperands,
     /* 195033 */     // GIR_Coverage, 5013,
     /* 195033 */     GIR_EraseRootFromParent_Done,
     /* 195034 */   // Label 3656: @195034
     /* 195034 */   GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(195063), // Rule ID 5014 //
     /* 195039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 195047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 195050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195054 */     // (intrinsic_wo_chain:{ *:[v8i16] } 617:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } ?:{ *:[v8f16] }:$Rn)
     /* 195054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 195057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195061 */     GIR_RootConstrainSelectedInstOperands,
     /* 195062 */     // GIR_Coverage, 5014,
     /* 195062 */     GIR_EraseRootFromParent_Done,
     /* 195063 */   // Label 3657: @195063
     /* 195063 */   GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(195092), // Rule ID 5015 //
     /* 195068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 195076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 195079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195083 */     // (intrinsic_wo_chain:{ *:[v2i32] } 617:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } ?:{ *:[v2f32] }:$Rn)
     /* 195083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 195086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195090 */     GIR_RootConstrainSelectedInstOperands,
     /* 195091 */     // GIR_Coverage, 5015,
     /* 195091 */     GIR_EraseRootFromParent_Done,
     /* 195092 */   // Label 3658: @195092
     /* 195092 */   GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(195121), // Rule ID 5016 //
     /* 195097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 195105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 195108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195112 */     // (intrinsic_wo_chain:{ *:[v4i32] } 617:{ *:[iPTR] }, v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } ?:{ *:[v4f32] }:$Rn)
     /* 195112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 195115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195119 */     GIR_RootConstrainSelectedInstOperands,
     /* 195120 */     // GIR_Coverage, 5016,
     /* 195120 */     GIR_EraseRootFromParent_Done,
     /* 195121 */   // Label 3659: @195121
     /* 195121 */   GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(195150), // Rule ID 5017 //
     /* 195126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 195134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 195137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 195141 */     // (intrinsic_wo_chain:{ *:[v2i64] } 617:{ *:[iPTR] }, v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } ?:{ *:[v2f64] }:$Rn)
     /* 195141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 195144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195148 */     GIR_RootConstrainSelectedInstOperands,
     /* 195149 */     // GIR_Coverage, 5017,
     /* 195149 */     GIR_EraseRootFromParent_Done,
     /* 195150 */   // Label 3660: @195150
     /* 195150 */   GIM_Try, /*On fail goto*//*Label 3661*/ GIMT_Encode4(195182), // Rule ID 5412 //
     /* 195155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 195158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195173 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 195173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 195176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195180 */     GIR_RootConstrainSelectedInstOperands,
     /* 195181 */     // GIR_Coverage, 5412,
     /* 195181 */     GIR_EraseRootFromParent_Done,
     /* 195182 */   // Label 3661: @195182
     /* 195182 */   GIM_Try, /*On fail goto*//*Label 3662*/ GIMT_Encode4(195214), // Rule ID 5413 //
     /* 195187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 195190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195205 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 195205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 195208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195210 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195212 */     GIR_RootConstrainSelectedInstOperands,
     /* 195213 */     // GIR_Coverage, 5413,
     /* 195213 */     GIR_EraseRootFromParent_Done,
     /* 195214 */   // Label 3662: @195214
     /* 195214 */   GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(195243), // Rule ID 5414 //
     /* 195219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195234 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 195234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 195237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195239 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195241 */     GIR_RootConstrainSelectedInstOperands,
     /* 195242 */     // GIR_Coverage, 5414,
     /* 195242 */     GIR_EraseRootFromParent_Done,
     /* 195243 */   // Label 3663: @195243
     /* 195243 */   GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(195272), // Rule ID 5415 //
     /* 195248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195263 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 195263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 195266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195270 */     GIR_RootConstrainSelectedInstOperands,
     /* 195271 */     // GIR_Coverage, 5415,
     /* 195271 */     GIR_EraseRootFromParent_Done,
     /* 195272 */   // Label 3664: @195272
     /* 195272 */   GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(195301), // Rule ID 5416 //
     /* 195277 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195282 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195285 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195288 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195292 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 195292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 195295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195299 */     GIR_RootConstrainSelectedInstOperands,
     /* 195300 */     // GIR_Coverage, 5416,
     /* 195300 */     GIR_EraseRootFromParent_Done,
     /* 195301 */   // Label 3665: @195301
     /* 195301 */   GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(195330), // Rule ID 5417 //
     /* 195306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195321 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 195321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 195324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195326 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195328 */     GIR_RootConstrainSelectedInstOperands,
     /* 195329 */     // GIR_Coverage, 5417,
     /* 195329 */     GIR_EraseRootFromParent_Done,
     /* 195330 */   // Label 3666: @195330
     /* 195330 */   GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(195362), // Rule ID 5418 //
     /* 195335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195346 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195353 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSSHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 195353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 195356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195360 */     GIR_RootConstrainSelectedInstOperands,
     /* 195361 */     // GIR_Coverage, 5418,
     /* 195361 */     GIR_EraseRootFromParent_Done,
     /* 195362 */   // Label 3667: @195362
     /* 195362 */   GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(195394), // Rule ID 5419 //
     /* 195367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195385 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZSDHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 195385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 195388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195392 */     GIR_RootConstrainSelectedInstOperands,
     /* 195393 */     // GIR_Coverage, 5419,
     /* 195393 */     GIR_EraseRootFromParent_Done,
     /* 195394 */   // Label 3668: @195394
     /* 195394 */   GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(195426), // Rule ID 5420 //
     /* 195399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195417 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSDSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 195417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 195420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195424 */     GIR_RootConstrainSelectedInstOperands,
     /* 195425 */     // GIR_Coverage, 5420,
     /* 195425 */     GIR_EraseRootFromParent_Done,
     /* 195426 */   // Label 3669: @195426
     /* 195426 */   GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(195458), // Rule ID 5421 //
     /* 195431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195449 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSSDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 195449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 195452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195454 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195456 */     GIR_RootConstrainSelectedInstOperands,
     /* 195457 */     // GIR_Coverage, 5421,
     /* 195457 */     GIR_EraseRootFromParent_Done,
     /* 195458 */   // Label 3670: @195458
     /* 195458 */   GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(195487), // Rule ID 5422 //
     /* 195463 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195468 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195471 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195478 */     // (intrinsic_wo_chain:{ *:[i32] } 616:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZSv1i32:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 195478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 195481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195483 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195485 */     GIR_RootConstrainSelectedInstOperands,
     /* 195486 */     // GIR_Coverage, 5422,
     /* 195486 */     GIR_EraseRootFromParent_Done,
     /* 195487 */   // Label 3671: @195487
     /* 195487 */   GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(195516), // Rule ID 5423 //
     /* 195492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzs),
     /* 195497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195507 */     // (intrinsic_wo_chain:{ *:[i64] } 616:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 195507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 195510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195514 */     GIR_RootConstrainSelectedInstOperands,
     /* 195515 */     // GIR_Coverage, 5423,
     /* 195515 */     GIR_EraseRootFromParent_Done,
     /* 195516 */   // Label 3672: @195516
     /* 195516 */   GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(195548), // Rule ID 5436 //
     /* 195521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 195524 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195529 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195532 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195539 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 195539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 195542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195546 */     GIR_RootConstrainSelectedInstOperands,
     /* 195547 */     // GIR_Coverage, 5436,
     /* 195547 */     GIR_EraseRootFromParent_Done,
     /* 195548 */   // Label 3673: @195548
     /* 195548 */   GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(195580), // Rule ID 5437 //
     /* 195553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 195556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195571 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 195571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 195574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195578 */     GIR_RootConstrainSelectedInstOperands,
     /* 195579 */     // GIR_Coverage, 5437,
     /* 195579 */     GIR_EraseRootFromParent_Done,
     /* 195580 */   // Label 3674: @195580
     /* 195580 */   GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(195609), // Rule ID 5438 //
     /* 195585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195600 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 195600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 195603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195607 */     GIR_RootConstrainSelectedInstOperands,
     /* 195608 */     // GIR_Coverage, 5438,
     /* 195608 */     GIR_EraseRootFromParent_Done,
     /* 195609 */   // Label 3675: @195609
     /* 195609 */   GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(195638), // Rule ID 5439 //
     /* 195614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195629 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 195629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 195632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195636 */     GIR_RootConstrainSelectedInstOperands,
     /* 195637 */     // GIR_Coverage, 5439,
     /* 195637 */     GIR_EraseRootFromParent_Done,
     /* 195638 */   // Label 3676: @195638
     /* 195638 */   GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(195667), // Rule ID 5440 //
     /* 195643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 195658 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 195658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 195661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195663 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195665 */     GIR_RootConstrainSelectedInstOperands,
     /* 195666 */     // GIR_Coverage, 5440,
     /* 195666 */     GIR_EraseRootFromParent_Done,
     /* 195667 */   // Label 3677: @195667
     /* 195667 */   GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(195696), // Rule ID 5441 //
     /* 195672 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195677 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195680 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 195687 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 195687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 195690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195694 */     GIR_RootConstrainSelectedInstOperands,
     /* 195695 */     // GIR_Coverage, 5441,
     /* 195695 */     GIR_EraseRootFromParent_Done,
     /* 195696 */   // Label 3678: @195696
     /* 195696 */   GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(195728), // Rule ID 5442 //
     /* 195701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195704 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195709 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195712 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195719 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUSHr:{ *:[i32] } ?:{ *:[f16] }:$Rn)
     /* 195719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 195722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195726 */     GIR_RootConstrainSelectedInstOperands,
     /* 195727 */     // GIR_Coverage, 5442,
     /* 195727 */     GIR_EraseRootFromParent_Done,
     /* 195728 */   // Label 3679: @195728
     /* 195728 */   GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(195760), // Rule ID 5443 //
     /* 195733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 195747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195751 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f16:{ *:[f16] }:$Rn)  =>  (FCVTZUDHr:{ *:[i64] } ?:{ *:[f16] }:$Rn)
     /* 195751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 195754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195758 */     GIR_RootConstrainSelectedInstOperands,
     /* 195759 */     // GIR_Coverage, 5443,
     /* 195759 */     GIR_EraseRootFromParent_Done,
     /* 195760 */   // Label 3680: @195760
     /* 195760 */   GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(195792), // Rule ID 5444 //
     /* 195765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195783 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUDSr:{ *:[i64] } ?:{ *:[f32] }:$Rn)
     /* 195783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 195786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195790 */     GIR_RootConstrainSelectedInstOperands,
     /* 195791 */     // GIR_Coverage, 5444,
     /* 195791 */     GIR_EraseRootFromParent_Done,
     /* 195792 */   // Label 3681: @195792
     /* 195792 */   GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(195824), // Rule ID 5445 //
     /* 195797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 195800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195815 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUSDr:{ *:[i32] } ?:{ *:[f64] }:$Rn)
     /* 195815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 195818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195822 */     GIR_RootConstrainSelectedInstOperands,
     /* 195823 */     // GIR_Coverage, 5445,
     /* 195823 */     GIR_EraseRootFromParent_Done,
     /* 195824 */   // Label 3682: @195824
     /* 195824 */   GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(195853), // Rule ID 5446 //
     /* 195829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 195837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 195840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 195844 */     // (intrinsic_wo_chain:{ *:[i32] } 617:{ *:[iPTR] }, f32:{ *:[f32] }:$Rn)  =>  (FCVTZUv1i32:{ *:[i32] } ?:{ *:[f32] }:$Rn)
     /* 195844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 195847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195849 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195851 */     GIR_RootConstrainSelectedInstOperands,
     /* 195852 */     // GIR_Coverage, 5446,
     /* 195852 */     GIR_EraseRootFromParent_Done,
     /* 195853 */   // Label 3683: @195853
     /* 195853 */   GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(195882), // Rule ID 5447 //
     /* 195858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fcvtzu),
     /* 195863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 195866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 195869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 195873 */     // (intrinsic_wo_chain:{ *:[i64] } 617:{ *:[iPTR] }, f64:{ *:[f64] }:$Rn)  =>  (FCVTZUv1i64:{ *:[i64] } ?:{ *:[f64] }:$Rn)
     /* 195873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 195876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 195878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 195880 */     GIR_RootConstrainSelectedInstOperands,
     /* 195881 */     // GIR_Coverage, 5447,
     /* 195881 */     GIR_EraseRootFromParent_Done,
     /* 195882 */   // Label 3684: @195882
     /* 195882 */   GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(195914), // Rule ID 9135 //
     /* 195887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 195890 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 195895 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 195898 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 195901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 195905 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1713:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv8i1] } ?:{ *:[nxv16i1] }:$Op1)
     /* 195905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 195908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 195910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 195912 */     GIR_RootConstrainSelectedInstOperands,
     /* 195913 */     // GIR_Coverage, 9135,
     /* 195913 */     GIR_EraseRootFromParent_Done,
     /* 195914 */   // Label 3685: @195914
     /* 195914 */   GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(195946), // Rule ID 9136 //
     /* 195919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 195922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 195927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 195930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 195933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 195937 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1713:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv4i1] } ?:{ *:[nxv8i1] }:$Op1)
     /* 195937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 195940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 195942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 195944 */     GIR_RootConstrainSelectedInstOperands,
     /* 195945 */     // GIR_Coverage, 9136,
     /* 195945 */     GIR_EraseRootFromParent_Done,
     /* 195946 */   // Label 3686: @195946
     /* 195946 */   GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(195978), // Rule ID 9137 //
     /* 195951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 195954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_punpkhi),
     /* 195959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 195962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 195965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 195969 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1713:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1)  =>  (PUNPKHI_PP:{ *:[nxv2i1] } ?:{ *:[nxv4i1] }:$Op1)
     /* 195969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 195972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 195974 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 195976 */     GIR_RootConstrainSelectedInstOperands,
     /* 195977 */     // GIR_Coverage, 9137,
     /* 195977 */     GIR_EraseRootFromParent_Done,
     /* 195978 */   // Label 3687: @195978
     /* 195978 */   GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(196010), // Rule ID 12638 //
     /* 195983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 195986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 195991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 195994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 195997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196001 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2103:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (UQXTNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 196001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_B),
     /* 196004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196008 */     GIR_RootConstrainSelectedInstOperands,
     /* 196009 */     // GIR_Coverage, 12638,
     /* 196009 */     GIR_EraseRootFromParent_Done,
     /* 196010 */   // Label 3688: @196010
     /* 196010 */   GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(196042), // Rule ID 12639 //
     /* 196015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 196018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 196023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 196026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 196029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196033 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2103:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (UQXTNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 196033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_H),
     /* 196036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196040 */     GIR_RootConstrainSelectedInstOperands,
     /* 196041 */     // GIR_Coverage, 12639,
     /* 196041 */     GIR_EraseRootFromParent_Done,
     /* 196042 */   // Label 3689: @196042
     /* 196042 */   GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(196074), // Rule ID 12640 //
     /* 196047 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 196050 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnb),
     /* 196055 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 196058 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 196061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196065 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2103:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (UQXTNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 196065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNB_ZZ_S),
     /* 196068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196070 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196072 */     GIR_RootConstrainSelectedInstOperands,
     /* 196073 */     // GIR_Coverage, 12640,
     /* 196073 */     GIR_EraseRootFromParent_Done,
     /* 196074 */   // Label 3690: @196074
     /* 196074 */   GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(196106), // Rule ID 12641 //
     /* 196079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 196082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 196087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 196090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 196093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196097 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1908:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1)  =>  (SQXTUNB_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1)
     /* 196097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_B),
     /* 196100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196104 */     GIR_RootConstrainSelectedInstOperands,
     /* 196105 */     // GIR_Coverage, 12641,
     /* 196105 */     GIR_EraseRootFromParent_Done,
     /* 196106 */   // Label 3691: @196106
     /* 196106 */   GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(196138), // Rule ID 12642 //
     /* 196111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 196114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 196119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 196122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 196125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196129 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1908:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1)  =>  (SQXTUNB_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1)
     /* 196129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_H),
     /* 196132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196136 */     GIR_RootConstrainSelectedInstOperands,
     /* 196137 */     // GIR_Coverage, 12642,
     /* 196137 */     GIR_EraseRootFromParent_Done,
     /* 196138 */   // Label 3692: @196138
     /* 196138 */   GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(196170), // Rule ID 12643 //
     /* 196143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 196146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunb),
     /* 196151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 196154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 196157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196161 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1908:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1)  =>  (SQXTUNB_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1)
     /* 196161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNB_ZZ_S),
     /* 196164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 196166 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196168 */     GIR_RootConstrainSelectedInstOperands,
     /* 196169 */     // GIR_Coverage, 12643,
     /* 196169 */     GIR_EraseRootFromParent_Done,
     /* 196170 */   // Label 3693: @196170
     /* 196170 */   GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(196202), // Rule ID 12957 //
     /* 196175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 196178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesimc),
     /* 196183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 196186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 196189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 196193 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1291:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (AESIMC_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1)
     /* 196193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESIMC_ZZ_B),
     /* 196196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 196198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 196200 */     GIR_RootConstrainSelectedInstOperands,
     /* 196201 */     // GIR_Coverage, 12957,
     /* 196201 */     GIR_EraseRootFromParent_Done,
     /* 196202 */   // Label 3694: @196202
     /* 196202 */   GIM_Reject,
     /* 196203 */ // Label 3309: @196203
     /* 196203 */ GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(237517),
     /* 196208 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 196211 */   GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(196395), // Rule ID 2604 //
     /* 196216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196219 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 196224 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196227 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196230 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196233 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196241 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 196245 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 196249 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 196253 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 196257 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 196261 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 196265 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 196268 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 196273 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196277 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196281 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196286 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 196290 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 196294 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196298 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 196302 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 196306 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196310 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 196314 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 196319 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 196323 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 196327 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 196331 */     // MIs[5] Operand 1
     /* 196331 */     // No operand predicates
     /* 196331 */     // MIs[3] Operand 2
     /* 196331 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /* 196342 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 196346 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /* 196348 */     // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 196348 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 196351 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 196355 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 196360 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 196366 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196371 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 196379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 196381 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 196383 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 196386 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /* 196390 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // idx
     /* 196393 */     GIR_RootConstrainSelectedInstOperands,
     /* 196394 */     // GIR_Coverage, 2604,
     /* 196394 */     GIR_EraseRootFromParent_Done,
     /* 196395 */   // Label 3696: @196395
     /* 196395 */   GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(196579), // Rule ID 6897 //
     /* 196400 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196403 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 196408 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196411 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196414 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196421 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196425 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 196429 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 196433 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 196437 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 196441 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 196445 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 196449 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 196452 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 196457 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196461 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196465 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196470 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 196474 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 196478 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196482 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 196486 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 196490 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196494 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 196498 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 196503 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/2, // MIs[5]
     /* 196507 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 196511 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 196515 */     // MIs[5] Operand 1
     /* 196515 */     // No operand predicates
     /* 196515 */     // MIs[3] Operand 2
     /* 196515 */     GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(0),
     /* 196526 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 196530 */     GIM_CheckIsSafeToFold, /*NumInsns*/5,
     /* 196532 */     // (intrinsic_wo_chain:{ *:[i32] } 723:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 196532 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 196535 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 196539 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 196544 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 196550 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196555 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 196563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 196565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 196567 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 196570 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rm
     /* 196574 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // idx
     /* 196577 */     GIR_RootConstrainSelectedInstOperands,
     /* 196578 */     // GIR_Coverage, 6897,
     /* 196578 */     GIR_EraseRootFromParent_Done,
     /* 196579 */   // Label 3697: @196579
     /* 196579 */   GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(196740), // Rule ID 2605 //
     /* 196584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 196592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196605 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196609 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 196613 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 196617 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 196621 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 196625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 196629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 196633 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 196636 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 196641 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196645 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196649 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196654 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 196658 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 196662 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196666 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 196670 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 196675 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 196679 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 196683 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 196687 */     // MIs[4] Operand 1
     /* 196687 */     // No operand predicates
     /* 196687 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 196691 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 196693 */     // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 196693 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 196696 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 196700 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 196705 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 196711 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196716 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 196724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 196726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 196728 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 196731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 196735 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 196738 */     GIR_RootConstrainSelectedInstOperands,
     /* 196739 */     // GIR_Coverage, 2605,
     /* 196739 */     GIR_EraseRootFromParent_Done,
     /* 196740 */   // Label 3698: @196740
     /* 196740 */   GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(196901), // Rule ID 6898 //
     /* 196745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 196753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 196756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 196759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 196762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196766 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 196770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 196774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 196778 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 196782 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 196786 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 196790 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 196794 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 196797 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 196802 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196806 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196810 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196815 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/3, // MIs[3]
     /* 196819 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 196823 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196827 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 196831 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 196836 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 196840 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 196844 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 196848 */     // MIs[4] Operand 1
     /* 196848 */     // No operand predicates
     /* 196848 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 196852 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 196854 */     // (intrinsic_wo_chain:{ *:[i32] } 723:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 196854 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 196857 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 196861 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 196866 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 196872 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 196877 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 196882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 196885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 196887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 196889 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 196892 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 196896 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 196899 */     GIR_RootConstrainSelectedInstOperands,
     /* 196900 */     // GIR_Coverage, 6898,
     /* 196900 */     GIR_EraseRootFromParent_Done,
     /* 196901 */   // Label 3699: @196901
     /* 196901 */   GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(197011), // Rule ID 2116 //
     /* 196906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 196909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 196914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 196917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 196920 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 196923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 196927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 196931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 196935 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196939 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 196943 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 196947 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 196951 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 196955 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 196960 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 196964 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 196968 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 196972 */     // MIs[3] Operand 1
     /* 196972 */     // No operand predicates
     /* 196972 */     // MIs[1] Operand 2
     /* 196972 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 196983 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 196985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 196992 */     // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (SQDMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 196992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv8i16_indexed),
     /* 196995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 196997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 197002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 197006 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 197009 */     GIR_RootConstrainSelectedInstOperands,
     /* 197010 */     // GIR_Coverage, 2116,
     /* 197010 */     GIR_EraseRootFromParent_Done,
     /* 197011 */   // Label 3700: @197011
     /* 197011 */   GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(197121), // Rule ID 2119 //
     /* 197016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 197024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 197027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 197030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 197033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197037 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 197041 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197045 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197049 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 197053 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 197057 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197061 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 197065 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197070 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 197074 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 197078 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 197082 */     // MIs[3] Operand 1
     /* 197082 */     // No operand predicates
     /* 197082 */     // MIs[1] Operand 2
     /* 197082 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 197093 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 197095 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 197102 */     // (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (SQDMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 197102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i32_indexed),
     /* 197105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 197107 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 197112 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 197116 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 197119 */     GIR_RootConstrainSelectedInstOperands,
     /* 197120 */     // GIR_Coverage, 2119,
     /* 197120 */     GIR_EraseRootFromParent_Done,
     /* 197121 */   // Label 3701: @197121
     /* 197121 */   GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(197243), // Rule ID 7566 //
     /* 197126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 197131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 197134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 197137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 197140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 197148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197156 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197161 */     // MIs[1] Operand 2
     /* 197161 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 197172 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 197176 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197180 */     // MIs[2] Rn
     /* 197180 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 197185 */     // MIs[2] Operand 2
     /* 197185 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 197196 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197198 */     // (intrinsic_wo_chain:{ *:[v2i32] } 594:{ *:[iPTR] }, (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (ADDPv4i32:{ *:[f128] } ?:{ *:[v4i32] }:$Rn, ?:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 197198 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 197201 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /* 197205 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197210 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197214 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197218 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 197220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197225 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 197232 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197237 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197242 */     // GIR_Coverage, 7566,
     /* 197242 */     GIR_EraseRootFromParent_Done,
     /* 197243 */   // Label 3702: @197243
     /* 197243 */   GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(197365), // Rule ID 7568 //
     /* 197248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 197253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 197256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 197259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 197262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197266 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 197270 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197274 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 197278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197283 */     // MIs[1] Operand 2
     /* 197283 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 197294 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 197298 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197302 */     // MIs[2] Rn
     /* 197302 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 197307 */     // MIs[2] Operand 2
     /* 197307 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 197318 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197320 */     // (intrinsic_wo_chain:{ *:[v4i16] } 594:{ *:[iPTR] }, (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (ADDPv8i16:{ *:[f128] } ?:{ *:[v8i16] }:$Rn, ?:{ *:[v8i16] }:$Rn), dsub:{ *:[i32] })
     /* 197320 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 197323 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /* 197327 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197332 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197336 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197340 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 197342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197347 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 197354 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197359 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197364 */     // GIR_Coverage, 7568,
     /* 197364 */     GIR_EraseRootFromParent_Done,
     /* 197365 */   // Label 3703: @197365
     /* 197365 */   GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(197487), // Rule ID 7570 //
     /* 197370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 197375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 197378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 197381 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 197384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 197392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197396 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 197400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197405 */     // MIs[1] Operand 2
     /* 197405 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 197416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 197420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197424 */     // MIs[2] Rn
     /* 197424 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 197429 */     // MIs[2] Operand 2
     /* 197429 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 197440 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197442 */     // (intrinsic_wo_chain:{ *:[v8i8] } 594:{ *:[iPTR] }, (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (ADDPv16i8:{ *:[f128] } ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rn), dsub:{ *:[i32] })
     /* 197442 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 197445 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /* 197449 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197454 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197458 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 197464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197469 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 197476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197486 */     // GIR_Coverage, 7570,
     /* 197486 */     GIR_EraseRootFromParent_Done,
     /* 197487 */   // Label 3704: @197487
     /* 197487 */   GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(197609), // Rule ID 7572 //
     /* 197492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 197497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 197500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 197503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 197506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 197514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197522 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197527 */     // MIs[1] Operand 2
     /* 197527 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 197538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 197542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197546 */     // MIs[2] Rn
     /* 197546 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 197551 */     // MIs[2] Operand 2
     /* 197551 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 197562 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197564 */     // (intrinsic_wo_chain:{ *:[v2f32] } 603:{ *:[iPTR] }, (extract_subvector:{ *:[v2f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2f32] } FPR128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (FADDPv4f32:{ *:[f128] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] })
     /* 197564 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 197567 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 197571 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197576 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197580 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197584 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 197586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197591 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 197598 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197603 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197608 */     // GIR_Coverage, 7572,
     /* 197608 */     GIR_EraseRootFromParent_Done,
     /* 197609 */   // Label 3705: @197609
     /* 197609 */   GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(197731), // Rule ID 7574 //
     /* 197614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 197619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 197622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 197625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 197628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 197636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197640 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 197644 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197649 */     // MIs[1] Operand 2
     /* 197649 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 197660 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 197664 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 197668 */     // MIs[2] Rn
     /* 197668 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 197673 */     // MIs[2] Operand 2
     /* 197673 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 197684 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197686 */     // (intrinsic_wo_chain:{ *:[v4f16] } 603:{ *:[iPTR] }, (extract_subvector:{ *:[v4f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4f16] } FPR128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] }))  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (FADDPv8f16:{ *:[f128] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rn), dsub:{ *:[i32] })
     /* 197686 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 197689 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 197693 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197698 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197702 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 197706 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 197708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197713 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 197720 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197725 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197730 */     // GIR_Coverage, 7574,
     /* 197730 */     GIR_EraseRootFromParent_Done,
     /* 197731 */   // Label 3706: @197731
     /* 197731 */   GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(197914), // Rule ID 2602 //
     /* 197736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 197744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197750 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197757 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 197765 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 197769 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197773 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 197777 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 197781 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 197785 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 197788 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 197793 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 197797 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 197801 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197806 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197811 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 197815 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 197817 */     // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (SQDMLALv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 197817 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 197820 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 197824 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197829 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 197831 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 197834 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 197838 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197843 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 197846 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /* 197850 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 197853 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197858 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 197863 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197868 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 197871 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 197875 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 197880 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 197886 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 197891 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv1i32_indexed),
     /* 197899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 197901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 197903 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 197906 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 197909 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 197912 */     GIR_RootConstrainSelectedInstOperands,
     /* 197913 */     // GIR_Coverage, 2602,
     /* 197913 */     GIR_EraseRootFromParent_Done,
     /* 197914 */   // Label 3707: @197914
     /* 197914 */   GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(198097), // Rule ID 6895 //
     /* 197919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 197922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 197927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 197930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 197933 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 197936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 197944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 197948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 197952 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 197956 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 197960 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 197964 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 197968 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
     /* 197971 */     GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 197976 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 197980 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 197984 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197989 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 197994 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 197998 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 198000 */     // (intrinsic_wo_chain:{ *:[i32] } 723:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, (vector_extract:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), 0:{ *:[i64] }))  =>  (SQDMLSLv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V64:{ *:[v4i16] }:$Rn, hsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v4i16] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 198000 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 198003 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 198007 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198012 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 198014 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 198017 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 198021 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198026 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 198029 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/3, // Rm
     /* 198033 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 198036 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198041 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198046 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198051 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 198054 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198058 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198063 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 198069 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 198074 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv1i32_indexed),
     /* 198082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 198084 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 198086 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198089 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 198092 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 198095 */     GIR_RootConstrainSelectedInstOperands,
     /* 198096 */     // GIR_Coverage, 6895,
     /* 198096 */     GIR_EraseRootFromParent_Done,
     /* 198097 */   // Label 3708: @198097
     /* 198097 */   GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(198201), // Rule ID 14477 //
     /* 198102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 198105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 198113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 198116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 198119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198123 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198127 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 198131 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198135 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 198139 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 198143 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198147 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 198151 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 198156 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 198160 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198164 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 198168 */     // MIs[3] Operand 1
     /* 198168 */     // No operand predicates
     /* 198168 */     // MIs[1] Operand 2
     /* 198168 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 198179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198183 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198185 */     // (intrinsic_wo_chain:{ *:[v4f16] } 635:{ *:[iPTR] }, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 198185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 198188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198192 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 198196 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 198199 */     GIR_RootConstrainSelectedInstOperands,
     /* 198200 */     // GIR_Coverage, 14477,
     /* 198200 */     GIR_EraseRootFromParent_Done,
     /* 198201 */   // Label 3709: @198201
     /* 198201 */   GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(198305), // Rule ID 14480 //
     /* 198206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 198217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 198220 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 198223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 198235 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 198243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 198247 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198251 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 198255 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198260 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 198264 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198268 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 198272 */     // MIs[3] Operand 1
     /* 198272 */     // No operand predicates
     /* 198272 */     // MIs[1] Operand 2
     /* 198272 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 198283 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198287 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198289 */     // (intrinsic_wo_chain:{ *:[v2f32] } 635:{ *:[iPTR] }, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 198289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 198292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 198296 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 198300 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 198303 */     GIR_RootConstrainSelectedInstOperands,
     /* 198304 */     // GIR_Coverage, 14480,
     /* 198304 */     GIR_EraseRootFromParent_Done,
     /* 198305 */   // Label 3710: @198305
     /* 198305 */   GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(198436), // Rule ID 2558 //
     /* 198310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 198313 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198318 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 198321 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 198324 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 198327 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 198331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198343 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 198347 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198352 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 198356 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 198360 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198364 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198368 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 198372 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198377 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 198381 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198385 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 198389 */     // MIs[3] Operand 1
     /* 198389 */     // No operand predicates
     /* 198389 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198391 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 198391 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 198394 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198398 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198403 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 198409 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 198414 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 198422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198424 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 198431 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 198434 */     GIR_RootConstrainSelectedInstOperands,
     /* 198435 */     // GIR_Coverage, 2558,
     /* 198435 */     GIR_EraseRootFromParent_Done,
     /* 198436 */   // Label 3711: @198436
     /* 198436 */   GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(198567), // Rule ID 2559 //
     /* 198441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 198452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 198455 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 198458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198462 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198466 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198470 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198474 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 198478 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198483 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 198487 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 198491 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198495 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198499 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 198503 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198508 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 198512 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198516 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 198520 */     // MIs[3] Operand 1
     /* 198520 */     // No operand predicates
     /* 198520 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198522 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 198522 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 198525 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198529 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198534 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 198540 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198545 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 198553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198555 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198558 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 198562 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 198565 */     GIR_RootConstrainSelectedInstOperands,
     /* 198566 */     // GIR_Coverage, 2559,
     /* 198566 */     GIR_EraseRootFromParent_Done,
     /* 198567 */   // Label 3712: @198567
     /* 198567 */   GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(198698), // Rule ID 2560 //
     /* 198572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 198583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 198586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 198589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198593 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198597 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198601 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 198605 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 198609 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198614 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 198618 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 198622 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198626 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 198630 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 198634 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198639 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 198643 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198647 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 198651 */     // MIs[3] Operand 1
     /* 198651 */     // No operand predicates
     /* 198651 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198653 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 198653 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 198656 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198660 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198665 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 198671 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198676 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 198684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198686 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 198693 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 198696 */     GIR_RootConstrainSelectedInstOperands,
     /* 198697 */     // GIR_Coverage, 2560,
     /* 198697 */     GIR_EraseRootFromParent_Done,
     /* 198698 */   // Label 3713: @198698
     /* 198698 */   GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(198829), // Rule ID 14669 //
     /* 198703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 198706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 198714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 198717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 198720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 198724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198728 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198732 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198736 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 198740 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198745 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 198749 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198753 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 198757 */     // MIs[2] Operand 1
     /* 198757 */     // No operand predicates
     /* 198757 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 198761 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198765 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 198769 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 198773 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198778 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 198782 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198784 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 198784 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 198787 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198791 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198796 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 198802 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 198807 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 198815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198817 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198820 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 198824 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 198827 */     GIR_RootConstrainSelectedInstOperands,
     /* 198828 */     // GIR_Coverage, 14669,
     /* 198828 */     GIR_EraseRootFromParent_Done,
     /* 198829 */   // Label 3714: @198829
     /* 198829 */   GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(198960), // Rule ID 14670 //
     /* 198834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 198845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 198848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 198851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198855 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198859 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198863 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198867 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 198871 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198876 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 198880 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 198884 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 198888 */     // MIs[2] Operand 1
     /* 198888 */     // No operand predicates
     /* 198888 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 198892 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198896 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 198900 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 198904 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198909 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 198913 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 198915 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 198915 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 198918 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 198922 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 198927 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 198933 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 198938 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 198943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 198946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 198948 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 198951 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 198955 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 198958 */     GIR_RootConstrainSelectedInstOperands,
     /* 198959 */     // GIR_Coverage, 14670,
     /* 198959 */     GIR_EraseRootFromParent_Done,
     /* 198960 */   // Label 3715: @198960
     /* 198960 */   GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(199091), // Rule ID 14671 //
     /* 198965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 198968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 198973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 198976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 198979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 198982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 198986 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 198990 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 198994 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 198998 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 199002 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 199011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199015 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 199019 */     // MIs[2] Operand 1
     /* 199019 */     // No operand predicates
     /* 199019 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 199023 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 199027 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 199031 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 199035 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199040 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 199044 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199046 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULXv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 199046 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 199049 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 199053 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 199058 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 199064 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199069 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 199077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199079 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 199082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 199086 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 199089 */     GIR_RootConstrainSelectedInstOperands,
     /* 199090 */     // GIR_Coverage, 14671,
     /* 199090 */     GIR_EraseRootFromParent_Done,
     /* 199091 */   // Label 3716: @199091
     /* 199091 */   GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(199195), // Rule ID 2018 //
     /* 199096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 199099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 199104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 199107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199110 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199117 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199121 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199125 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199129 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199133 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199137 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 199141 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199145 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199149 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 199154 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199158 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199162 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 199166 */     // MIs[3] Operand 1
     /* 199166 */     // No operand predicates
     /* 199166 */     // MIs[1] Operand 2
     /* 199166 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199177 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199179 */     // (intrinsic_wo_chain:{ *:[v4f16] } 635:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 199182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199190 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199193 */     GIR_RootConstrainSelectedInstOperands,
     /* 199194 */     // GIR_Coverage, 2018,
     /* 199194 */     GIR_EraseRootFromParent_Done,
     /* 199195 */   // Label 3717: @199195
     /* 199195 */   GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(199299), // Rule ID 2048 //
     /* 199200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 199208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 199211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199221 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199225 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199229 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199233 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199237 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199241 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 199245 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199249 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199253 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 199258 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199262 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199266 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 199270 */     // MIs[3] Operand 1
     /* 199270 */     // No operand predicates
     /* 199270 */     // MIs[1] Operand 2
     /* 199270 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199281 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199283 */     // (intrinsic_wo_chain:{ *:[v4i16] } 705:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16_indexed),
     /* 199286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199294 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199297 */     GIR_RootConstrainSelectedInstOperands,
     /* 199298 */     // GIR_Coverage, 2048,
     /* 199298 */     GIR_EraseRootFromParent_Done,
     /* 199299 */   // Label 3718: @199299
     /* 199299 */   GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(199403), // Rule ID 2055 //
     /* 199304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 199312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 199315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199329 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199333 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199337 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199341 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199345 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 199349 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199353 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199357 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 199362 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199366 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199370 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 199374 */     // MIs[3] Operand 1
     /* 199374 */     // No operand predicates
     /* 199374 */     // MIs[1] Operand 2
     /* 199374 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199385 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199387 */     // (intrinsic_wo_chain:{ *:[v4i16] } 713:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16_indexed),
     /* 199390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199398 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199401 */     GIR_RootConstrainSelectedInstOperands,
     /* 199402 */     // GIR_Coverage, 2055,
     /* 199402 */     GIR_EraseRootFromParent_Done,
     /* 199403 */   // Label 3719: @199403
     /* 199403 */   GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(199507), // Rule ID 2114 //
     /* 199408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 199416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 199419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199433 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199437 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199441 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 199453 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 199457 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199461 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 199466 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199470 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199474 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 199478 */     // MIs[3] Operand 1
     /* 199478 */     // No operand predicates
     /* 199478 */     // MIs[1] Operand 2
     /* 199478 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199489 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199491 */     // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_indexed),
     /* 199494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199498 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199502 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199505 */     GIR_RootConstrainSelectedInstOperands,
     /* 199506 */     // GIR_Coverage, 2114,
     /* 199506 */     GIR_EraseRootFromParent_Done,
     /* 199507 */   // Label 3720: @199507
     /* 199507 */   GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(199611), // Rule ID 2021 //
     /* 199512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 199520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199549 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199553 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 199557 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199561 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199565 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199570 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199574 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199578 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 199582 */     // MIs[3] Operand 1
     /* 199582 */     // No operand predicates
     /* 199582 */     // MIs[1] Operand 2
     /* 199582 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199593 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199595 */     // (intrinsic_wo_chain:{ *:[v2f32] } 635:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 199598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199606 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199609 */     GIR_RootConstrainSelectedInstOperands,
     /* 199610 */     // GIR_Coverage, 2021,
     /* 199610 */     GIR_EraseRootFromParent_Done,
     /* 199611 */   // Label 3721: @199611
     /* 199611 */   GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(199715), // Rule ID 2051 //
     /* 199616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 199624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 199661 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199665 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199669 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199674 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199678 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199682 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 199686 */     // MIs[3] Operand 1
     /* 199686 */     // No operand predicates
     /* 199686 */     // MIs[1] Operand 2
     /* 199686 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199697 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199699 */     // (intrinsic_wo_chain:{ *:[v2i32] } 705:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32_indexed),
     /* 199702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199704 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199710 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199713 */     GIR_RootConstrainSelectedInstOperands,
     /* 199714 */     // GIR_Coverage, 2051,
     /* 199714 */     GIR_EraseRootFromParent_Done,
     /* 199715 */   // Label 3722: @199715
     /* 199715 */   GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(199819), // Rule ID 2058 //
     /* 199720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 199728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 199731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199741 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199745 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199749 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199753 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199757 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199761 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 199765 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199769 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199773 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199778 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199782 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199786 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 199790 */     // MIs[3] Operand 1
     /* 199790 */     // No operand predicates
     /* 199790 */     // MIs[1] Operand 2
     /* 199790 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199801 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199803 */     // (intrinsic_wo_chain:{ *:[v2i32] } 713:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32_indexed),
     /* 199806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199810 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199814 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199817 */     GIR_RootConstrainSelectedInstOperands,
     /* 199818 */     // GIR_Coverage, 2058,
     /* 199818 */     GIR_EraseRootFromParent_Done,
     /* 199819 */   // Label 3723: @199819
     /* 199819 */   GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(199923), // Rule ID 2117 //
     /* 199824 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199827 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 199832 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 199835 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199838 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 199841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199845 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 199849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 199853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 199857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 199865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 199869 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 199873 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 199877 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199882 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 199886 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 199890 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 199894 */     // MIs[3] Operand 1
     /* 199894 */     // No operand predicates
     /* 199894 */     // MIs[1] Operand 2
     /* 199894 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 199905 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 199907 */     // (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 199907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_indexed),
     /* 199910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 199914 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 199918 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 199921 */     GIR_RootConstrainSelectedInstOperands,
     /* 199922 */     // GIR_Coverage, 2117,
     /* 199922 */     GIR_EraseRootFromParent_Done,
     /* 199923 */   // Label 3724: @199923
     /* 199923 */   GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(199980), // Rule ID 1782 //
     /* 199928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 199936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 199939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 199942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 199945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 199949 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 199956 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 199963 */     // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (SQDMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 199963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv8i16_v4i32),
     /* 199966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 199968 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 199973 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 199978 */     GIR_RootConstrainSelectedInstOperands,
     /* 199979 */     // GIR_Coverage, 1782,
     /* 199979 */     GIR_EraseRootFromParent_Done,
     /* 199980 */   // Label 3725: @199980
     /* 199980 */   GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(200037), // Rule ID 1784 //
     /* 199985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 199988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 199993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 199996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 199999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 200002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200006 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 200013 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 200020 */     // (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (SQDMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 200020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i32_v2i64),
     /* 200023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200025 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 200030 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 200035 */     GIR_RootConstrainSelectedInstOperands,
     /* 200036 */     // GIR_Coverage, 1784,
     /* 200036 */     GIR_EraseRootFromParent_Done,
     /* 200037 */   // Label 3726: @200037
     /* 200037 */   GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(200139), // Rule ID 6918 //
     /* 200042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 200047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 200050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200057 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200061 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 200065 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 200069 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 200073 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200078 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 200089 */     // MIs[0] imm
     /* 200089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 200092 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 200097 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200099 */     // (intrinsic_wo_chain:{ *:[f16] } 791:{ *:[iPTR] }, (and:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 200099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 200102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200111 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 200117 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200122 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 200130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200132 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200135 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 200137 */     GIR_RootConstrainSelectedInstOperands,
     /* 200138 */     // GIR_Coverage, 6918,
     /* 200138 */     GIR_EraseRootFromParent_Done,
     /* 200139 */   // Label 3727: @200139
     /* 200139 */   GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(200236), // Rule ID 14914 //
     /* 200144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 200147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 200155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 200158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 200161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 200177 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200181 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200186 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200190 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200194 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200196 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 200196 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 200199 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200203 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200208 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 200214 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200219 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 200227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200231 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200234 */     GIR_RootConstrainSelectedInstOperands,
     /* 200235 */     // GIR_Coverage, 14914,
     /* 200235 */     GIR_EraseRootFromParent_Done,
     /* 200236 */   // Label 3728: @200236
     /* 200236 */   GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(200333), // Rule ID 14915 //
     /* 200241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 200244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 200258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200262 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200266 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200270 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 200274 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200278 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200283 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200287 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200291 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200293 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 200293 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 200296 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200300 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200305 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 200311 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200316 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 200324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200328 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200331 */     GIR_RootConstrainSelectedInstOperands,
     /* 200332 */     // GIR_Coverage, 14915,
     /* 200332 */     GIR_EraseRootFromParent_Done,
     /* 200333 */   // Label 3729: @200333
     /* 200333 */   GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(200430), // Rule ID 14916 //
     /* 200338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 200341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 200355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200359 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200363 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200367 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 200371 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200375 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200380 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200384 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200388 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200390 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 200390 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 200393 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200397 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200402 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 200408 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200413 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 200421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200423 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200425 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200428 */     GIR_RootConstrainSelectedInstOperands,
     /* 200429 */     // GIR_Coverage, 14916,
     /* 200429 */     GIR_EraseRootFromParent_Done,
     /* 200430 */   // Label 3730: @200430
     /* 200430 */   GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(200527), // Rule ID 5299 //
     /* 200435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 200438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 200446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 200449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 200452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200456 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 200464 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200468 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 200472 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200476 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200481 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200485 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200487 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 200487 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 200490 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200494 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200499 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 200505 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 200510 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 200518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200520 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200522 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200525 */     GIR_RootConstrainSelectedInstOperands,
     /* 200526 */     // GIR_Coverage, 5299,
     /* 200526 */     GIR_EraseRootFromParent_Done,
     /* 200527 */   // Label 3731: @200527
     /* 200527 */   GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(200624), // Rule ID 5300 //
     /* 200532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 200535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 200543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 200546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 200549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200553 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200557 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 200561 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200565 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 200569 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200573 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200578 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200582 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200584 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 200584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 200587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200596 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 200602 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 200607 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 200615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200619 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200622 */     GIR_RootConstrainSelectedInstOperands,
     /* 200623 */     // GIR_Coverage, 5300,
     /* 200623 */     GIR_EraseRootFromParent_Done,
     /* 200624 */   // Label 3732: @200624
     /* 200624 */   GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(200721), // Rule ID 5301 //
     /* 200629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 200632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 200640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 200643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 200646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 200658 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 200662 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 200666 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200670 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200675 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 200679 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 200681 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 200681 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 200684 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 200688 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 200693 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 200699 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200704 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 200712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200714 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 200716 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 200719 */     GIR_RootConstrainSelectedInstOperands,
     /* 200720 */     // GIR_Coverage, 5301,
     /* 200720 */     GIR_EraseRootFromParent_Done,
     /* 200721 */   // Label 3733: @200721
     /* 200721 */   GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(200802), // Rule ID 14478 //
     /* 200726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 200729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 200737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 200740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 200743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200747 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200751 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 200755 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 200759 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200763 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 200768 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 200772 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 200776 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 200780 */     // MIs[2] Operand 1
     /* 200780 */     // No operand predicates
     /* 200780 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200784 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 200786 */     // (intrinsic_wo_chain:{ *:[v4f16] } 635:{ *:[iPTR] }, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 200786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 200789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200791 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 200797 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 200800 */     GIR_RootConstrainSelectedInstOperands,
     /* 200801 */     // GIR_Coverage, 14478,
     /* 200801 */     GIR_EraseRootFromParent_Done,
     /* 200802 */   // Label 3734: @200802
     /* 200802 */   GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(200883), // Rule ID 14479 //
     /* 200807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 200810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 200818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 200821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 200824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200832 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 200836 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 200840 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200844 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 200849 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 200853 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 200857 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 200861 */     // MIs[2] Operand 1
     /* 200861 */     // No operand predicates
     /* 200861 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200865 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 200867 */     // (intrinsic_wo_chain:{ *:[v8f16] } 635:{ *:[iPTR] }, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 200867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
     /* 200870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 200878 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 200881 */     GIR_RootConstrainSelectedInstOperands,
     /* 200882 */     // GIR_Coverage, 14479,
     /* 200882 */     GIR_EraseRootFromParent_Done,
     /* 200883 */   // Label 3735: @200883
     /* 200883 */   GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(200964), // Rule ID 14481 //
     /* 200888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 200891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 200899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 200902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 200905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 200917 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 200921 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 200925 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200930 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 200934 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 200938 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 200942 */     // MIs[2] Operand 1
     /* 200942 */     // No operand predicates
     /* 200942 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 200946 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 200948 */     // (intrinsic_wo_chain:{ *:[v2f32] } 635:{ *:[iPTR] }, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 200948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 200951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 200953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 200955 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 200959 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 200962 */     GIR_RootConstrainSelectedInstOperands,
     /* 200963 */     // GIR_Coverage, 14481,
     /* 200963 */     GIR_EraseRootFromParent_Done,
     /* 200964 */   // Label 3736: @200964
     /* 200964 */   GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(201045), // Rule ID 14482 //
     /* 200969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 200972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 200977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 200980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 200983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 200986 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 200990 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 200994 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 200998 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 201002 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201006 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201011 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201015 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201019 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 201023 */     // MIs[2] Operand 1
     /* 201023 */     // No operand predicates
     /* 201023 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201027 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201029 */     // (intrinsic_wo_chain:{ *:[v4f32] } 635:{ *:[iPTR] }, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
     /* 201032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201034 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 201036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201040 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201043 */     GIR_RootConstrainSelectedInstOperands,
     /* 201044 */     // GIR_Coverage, 14482,
     /* 201044 */     GIR_EraseRootFromParent_Done,
     /* 201045 */   // Label 3737: @201045
     /* 201045 */   GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(201126), // Rule ID 14483 //
     /* 201050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 201061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 201064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 201067 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201071 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 201075 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 201079 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 201083 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201087 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201092 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201096 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201100 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 201104 */     // MIs[2] Operand 1
     /* 201104 */     // No operand predicates
     /* 201104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201108 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201110 */     // (intrinsic_wo_chain:{ *:[v2f64] } 635:{ *:[iPTR] }, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
     /* 201113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201115 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 201117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201121 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201124 */     GIR_RootConstrainSelectedInstOperands,
     /* 201125 */     // GIR_Coverage, 14483,
     /* 201125 */     GIR_EraseRootFromParent_Done,
     /* 201126 */   // Label 3738: @201126
     /* 201126 */   GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(201207), // Rule ID 14484 //
     /* 201131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 201134 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201139 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 201142 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 201145 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 201148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 201152 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 201156 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 201160 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201164 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201168 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201173 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201177 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201181 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201185 */     // MIs[2] Operand 1
     /* 201185 */     // No operand predicates
     /* 201185 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 201189 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201191 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 201194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 201198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201202 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201205 */     GIR_RootConstrainSelectedInstOperands,
     /* 201206 */     // GIR_Coverage, 14484,
     /* 201206 */     GIR_EraseRootFromParent_Done,
     /* 201207 */   // Label 3739: @201207
     /* 201207 */   GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(201288), // Rule ID 14485 //
     /* 201212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 201223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 201229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 201237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 201241 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 201245 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201249 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201254 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201258 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201262 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 201266 */     // MIs[2] Operand 1
     /* 201266 */     // No operand predicates
     /* 201266 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201270 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201272 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 201275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 201279 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201283 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201286 */     GIR_RootConstrainSelectedInstOperands,
     /* 201287 */     // GIR_Coverage, 14485,
     /* 201287 */     GIR_EraseRootFromParent_Done,
     /* 201288 */   // Label 3740: @201288
     /* 201288 */   GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(201369), // Rule ID 14486 //
     /* 201293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 201304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 201307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 201310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201314 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 201318 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 201322 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 201326 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201330 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201335 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201339 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201343 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 201347 */     // MIs[2] Operand 1
     /* 201347 */     // No operand predicates
     /* 201347 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201353 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 201356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 201360 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201364 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201367 */     GIR_RootConstrainSelectedInstOperands,
     /* 201368 */     // GIR_Coverage, 14486,
     /* 201368 */     GIR_EraseRootFromParent_Done,
     /* 201369 */   // Label 3741: @201369
     /* 201369 */   GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(201467), // Rule ID 6915 //
     /* 201374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 201379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 201382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 201385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 201389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 201393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 201397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 201401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201406 */     // MIs[1] Operand 2
     /* 201406 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 201417 */     // MIs[0] imm
     /* 201417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 201420 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 201425 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 201427 */     // (intrinsic_wo_chain:{ *:[f16] } 790:{ *:[iPTR] }, (sext_inreg:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 201427 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 201430 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 201434 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 201439 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 201445 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 201450 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 201455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 201458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201460 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 201463 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 201465 */     GIR_RootConstrainSelectedInstOperands,
     /* 201466 */     // GIR_Coverage, 6915,
     /* 201466 */     GIR_EraseRootFromParent_Done,
     /* 201467 */   // Label 3742: @201467
     /* 201467 */   GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(201548), // Rule ID 2019 //
     /* 201472 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 201475 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201480 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 201483 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 201486 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 201489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201493 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201497 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201501 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201505 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201509 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201513 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201518 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201522 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201526 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201530 */     // MIs[2] Operand 1
     /* 201530 */     // No operand predicates
     /* 201530 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201532 */     // (intrinsic_wo_chain:{ *:[v4f16] } 635:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i16_indexed),
     /* 201535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201543 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201546 */     GIR_RootConstrainSelectedInstOperands,
     /* 201547 */     // GIR_Coverage, 2019,
     /* 201547 */     GIR_EraseRootFromParent_Done,
     /* 201548 */   // Label 3743: @201548
     /* 201548 */   GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(201629), // Rule ID 2020 //
     /* 201553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 201556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 201561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 201564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 201567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 201570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201594 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201607 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201611 */     // MIs[2] Operand 1
     /* 201611 */     // No operand predicates
     /* 201611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201613 */     // (intrinsic_wo_chain:{ *:[v8f16] } 635:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8i16_indexed),
     /* 201616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201620 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201624 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201627 */     GIR_RootConstrainSelectedInstOperands,
     /* 201628 */     // GIR_Coverage, 2020,
     /* 201628 */     GIR_EraseRootFromParent_Done,
     /* 201629 */   // Label 3744: @201629
     /* 201629 */   GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(201710), // Rule ID 2049 //
     /* 201634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 201642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 201645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 201648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 201651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201659 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201663 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201667 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201671 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201675 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201688 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201692 */     // MIs[2] Operand 1
     /* 201692 */     // No operand predicates
     /* 201692 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201694 */     // (intrinsic_wo_chain:{ *:[v4i16] } 705:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16_indexed),
     /* 201697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201699 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201701 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201705 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201708 */     GIR_RootConstrainSelectedInstOperands,
     /* 201709 */     // GIR_Coverage, 2049,
     /* 201709 */     GIR_EraseRootFromParent_Done,
     /* 201710 */   // Label 3745: @201710
     /* 201710 */   GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(201791), // Rule ID 2050 //
     /* 201715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 201723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 201726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 201729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 201732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201740 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201744 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201748 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201752 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201756 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201769 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201773 */     // MIs[2] Operand 1
     /* 201773 */     // No operand predicates
     /* 201773 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201775 */     // (intrinsic_wo_chain:{ *:[v8i16] } 705:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16_indexed),
     /* 201778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201782 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201786 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201789 */     GIR_RootConstrainSelectedInstOperands,
     /* 201790 */     // GIR_Coverage, 2050,
     /* 201790 */     GIR_EraseRootFromParent_Done,
     /* 201791 */   // Label 3746: @201791
     /* 201791 */   GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(201872), // Rule ID 2056 //
     /* 201796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 201804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 201807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 201810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 201813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201833 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201837 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201842 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201846 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201850 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201854 */     // MIs[2] Operand 1
     /* 201854 */     // No operand predicates
     /* 201854 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201856 */     // (intrinsic_wo_chain:{ *:[v4i16] } 713:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMULHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16_indexed),
     /* 201859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201867 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201870 */     GIR_RootConstrainSelectedInstOperands,
     /* 201871 */     // GIR_Coverage, 2056,
     /* 201871 */     GIR_EraseRootFromParent_Done,
     /* 201872 */   // Label 3747: @201872
     /* 201872 */   GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(201953), // Rule ID 2057 //
     /* 201877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 201885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 201888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 201891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 201894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201898 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 201923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 201927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 201931 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 201935 */     // MIs[2] Operand 1
     /* 201935 */     // No operand predicates
     /* 201935 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 201937 */     // (intrinsic_wo_chain:{ *:[v8i16] } 713:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMULHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 201937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16_indexed),
     /* 201940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 201942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 201944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 201948 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 201951 */     GIR_RootConstrainSelectedInstOperands,
     /* 201952 */     // GIR_Coverage, 2057,
     /* 201952 */     GIR_EraseRootFromParent_Done,
     /* 201953 */   // Label 3748: @201953
     /* 201953 */   GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(202034), // Rule ID 2115 //
     /* 201958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 201961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 201966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 201969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 201972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 201975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 201979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 201983 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 201987 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 201991 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 201995 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 201999 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 202004 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202008 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202012 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 202016 */     // MIs[2] Operand 1
     /* 202016 */     // No operand predicates
     /* 202016 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202018 */     // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQDMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_indexed),
     /* 202021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202029 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202032 */     GIR_RootConstrainSelectedInstOperands,
     /* 202033 */     // GIR_Coverage, 2115,
     /* 202033 */     GIR_EraseRootFromParent_Done,
     /* 202034 */   // Label 3749: @202034
     /* 202034 */   GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(202115), // Rule ID 2022 //
     /* 202039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 202050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 202053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 202056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202060 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202076 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202093 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202097 */     // MIs[2] Operand 1
     /* 202097 */     // No operand predicates
     /* 202097 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202099 */     // (intrinsic_wo_chain:{ *:[v2f32] } 635:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i32_indexed),
     /* 202102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202106 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202110 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202113 */     GIR_RootConstrainSelectedInstOperands,
     /* 202114 */     // GIR_Coverage, 2022,
     /* 202114 */     GIR_EraseRootFromParent_Done,
     /* 202115 */   // Label 3750: @202115
     /* 202115 */   GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(202196), // Rule ID 2023 //
     /* 202120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 202131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 202134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 202137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202141 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202153 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202157 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202161 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202166 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202170 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202174 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202178 */     // MIs[2] Operand 1
     /* 202178 */     // No operand predicates
     /* 202178 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202180 */     // (intrinsic_wo_chain:{ *:[v4f32] } 635:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4i32_indexed),
     /* 202183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202185 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202187 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202191 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202194 */     GIR_RootConstrainSelectedInstOperands,
     /* 202195 */     // GIR_Coverage, 2023,
     /* 202195 */     GIR_EraseRootFromParent_Done,
     /* 202196 */   // Label 3751: @202196
     /* 202196 */   GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(202277), // Rule ID 2052 //
     /* 202201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 202209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 202212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 202215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 202218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202222 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202226 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202230 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202234 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202238 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202242 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202247 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202251 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202255 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202259 */     // MIs[2] Operand 1
     /* 202259 */     // No operand predicates
     /* 202259 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202261 */     // (intrinsic_wo_chain:{ *:[v2i32] } 705:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32_indexed),
     /* 202264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202268 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202272 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202275 */     GIR_RootConstrainSelectedInstOperands,
     /* 202276 */     // GIR_Coverage, 2052,
     /* 202276 */     GIR_EraseRootFromParent_Done,
     /* 202277 */   // Label 3752: @202277
     /* 202277 */   GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(202358), // Rule ID 2053 //
     /* 202282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 202290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 202293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 202296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 202299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202303 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202307 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202311 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202315 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202319 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202323 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202328 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202332 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202336 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202340 */     // MIs[2] Operand 1
     /* 202340 */     // No operand predicates
     /* 202340 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202342 */     // (intrinsic_wo_chain:{ *:[v4i32] } 705:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32_indexed),
     /* 202345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202353 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202356 */     GIR_RootConstrainSelectedInstOperands,
     /* 202357 */     // GIR_Coverage, 2053,
     /* 202357 */     GIR_EraseRootFromParent_Done,
     /* 202358 */   // Label 3753: @202358
     /* 202358 */   GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(202439), // Rule ID 2059 //
     /* 202363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 202371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 202374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 202377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 202380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202396 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202400 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202404 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202409 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202413 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202417 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202421 */     // MIs[2] Operand 1
     /* 202421 */     // No operand predicates
     /* 202421 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202423 */     // (intrinsic_wo_chain:{ *:[v2i32] } 713:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32_indexed),
     /* 202426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202434 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202437 */     GIR_RootConstrainSelectedInstOperands,
     /* 202438 */     // GIR_Coverage, 2059,
     /* 202438 */     GIR_EraseRootFromParent_Done,
     /* 202439 */   // Label 3754: @202439
     /* 202439 */   GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(202520), // Rule ID 2060 //
     /* 202444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 202452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 202455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 202458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 202461 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202465 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202469 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202473 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202477 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202481 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202485 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202490 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202494 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202498 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202502 */     // MIs[2] Operand 1
     /* 202502 */     // No operand predicates
     /* 202502 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202504 */     // (intrinsic_wo_chain:{ *:[v4i32] } 713:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32_indexed),
     /* 202507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202509 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202511 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202515 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202518 */     GIR_RootConstrainSelectedInstOperands,
     /* 202519 */     // GIR_Coverage, 2060,
     /* 202519 */     GIR_EraseRootFromParent_Done,
     /* 202520 */   // Label 3755: @202520
     /* 202520 */   GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(202601), // Rule ID 2118 //
     /* 202525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 202533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 202536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 202539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 202542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202546 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202554 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 202558 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202562 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202566 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202579 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202583 */     // MIs[2] Operand 1
     /* 202583 */     // No operand predicates
     /* 202583 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202585 */     // (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_indexed),
     /* 202588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202590 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202596 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202599 */     GIR_RootConstrainSelectedInstOperands,
     /* 202600 */     // GIR_Coverage, 2118,
     /* 202600 */     GIR_EraseRootFromParent_Done,
     /* 202601 */   // Label 3756: @202601
     /* 202601 */   GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(202682), // Rule ID 2024 //
     /* 202606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 202617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 202620 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 202623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202627 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 202639 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 202643 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202647 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202660 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 202664 */     // MIs[2] Operand 1
     /* 202664 */     // No operand predicates
     /* 202664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202666 */     // (intrinsic_wo_chain:{ *:[v2f64] } 635:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2i64_indexed),
     /* 202669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202673 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202677 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202680 */     GIR_RootConstrainSelectedInstOperands,
     /* 202681 */     // GIR_Coverage, 2024,
     /* 202681 */     GIR_EraseRootFromParent_Done,
     /* 202682 */   // Label 3757: @202682
     /* 202682 */   GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(202763), // Rule ID 2025 //
     /* 202687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 202690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 202698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 202701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 202704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 202712 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202716 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 202720 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 202724 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202728 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 202733 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202737 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202741 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 202745 */     // MIs[2] Operand 1
     /* 202745 */     // No operand predicates
     /* 202745 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202747 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULXv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i16_indexed),
     /* 202750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202758 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202761 */     GIR_RootConstrainSelectedInstOperands,
     /* 202762 */     // GIR_Coverage, 2025,
     /* 202762 */     GIR_EraseRootFromParent_Done,
     /* 202763 */   // Label 3758: @202763
     /* 202763 */   GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(202844), // Rule ID 2026 //
     /* 202768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 202782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 202785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202789 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 202801 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202805 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202809 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202814 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202818 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202822 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202826 */     // MIs[2] Operand 1
     /* 202826 */     // No operand predicates
     /* 202826 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202828 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULXv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i32_indexed),
     /* 202831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202833 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202839 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202842 */     GIR_RootConstrainSelectedInstOperands,
     /* 202843 */     // GIR_Coverage, 2026,
     /* 202843 */     GIR_EraseRootFromParent_Done,
     /* 202844 */   // Label 3759: @202844
     /* 202844 */   GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(202925), // Rule ID 2027 //
     /* 202849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 202857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 202860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 202863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 202866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 202874 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202878 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 202882 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 202886 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202890 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202895 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202899 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202903 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 202907 */     // MIs[2] Operand 1
     /* 202907 */     // No operand predicates
     /* 202907 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202909 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULXv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv1i64_indexed),
     /* 202912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202916 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 202920 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 202923 */     GIR_RootConstrainSelectedInstOperands,
     /* 202924 */     // GIR_Coverage, 2027,
     /* 202924 */     GIR_EraseRootFromParent_Done,
     /* 202925 */   // Label 3760: @202925
     /* 202925 */   GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(203006), // Rule ID 2054 //
     /* 202930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 202933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 202938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 202941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 202944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 202947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 202955 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 202959 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 202963 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 202967 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 202971 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 202976 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 202980 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 202984 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 202988 */     // MIs[2] Operand 1
     /* 202988 */     // No operand predicates
     /* 202988 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 202990 */     // (intrinsic_wo_chain:{ *:[i32] } 705:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 202990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32_indexed),
     /* 202993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 202995 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 202997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 203001 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 203004 */     GIR_RootConstrainSelectedInstOperands,
     /* 203005 */     // GIR_Coverage, 2054,
     /* 203005 */     GIR_EraseRootFromParent_Done,
     /* 203006 */   // Label 3761: @203006
     /* 203006 */   GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(203087), // Rule ID 2061 //
     /* 203011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203014 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 203019 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 203025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 203028 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 203040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 203044 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 203048 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 203052 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203057 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 203061 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 203065 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 203069 */     // MIs[2] Operand 1
     /* 203069 */     // No operand predicates
     /* 203069 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 203071 */     // (intrinsic_wo_chain:{ *:[i32] } 713:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMULHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 203071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32_indexed),
     /* 203074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203076 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203078 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 203082 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 203085 */     GIR_RootConstrainSelectedInstOperands,
     /* 203086 */     // GIR_Coverage, 2061,
     /* 203086 */     GIR_EraseRootFromParent_Done,
     /* 203087 */   // Label 3762: @203087
     /* 203087 */   GIM_Try, /*On fail goto*//*Label 3763*/ GIMT_Encode4(203165), // Rule ID 6902 //
     /* 203092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulls_scalar),
     /* 203097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 203103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 203106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203110 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203114 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 203118 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 203122 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 203126 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 203130 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203135 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 203139 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 203143 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 203147 */     // MIs[2] Operand 1
     /* 203147 */     // No operand predicates
     /* 203147 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 203149 */     // (intrinsic_wo_chain:{ *:[i64] } 709:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQDMULLv1i64_indexed:{ *:[i64] } FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Vm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 203149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv1i64_indexed),
     /* 203152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
     /* 203160 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 203163 */     GIR_RootConstrainSelectedInstOperands,
     /* 203164 */     // GIR_Coverage, 6902,
     /* 203164 */     GIR_EraseRootFromParent_Done,
     /* 203165 */   // Label 3763: @203165
     /* 203165 */   GIM_Try, /*On fail goto*//*Label 3764*/ GIMT_Encode4(203212), // Rule ID 3990 //
     /* 203170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 203173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 203178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203192 */     // MIs[0] Operand 3
     /* 203192 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
     /* 203203 */     // (intrinsic_wo_chain:{ *:[i64] } 310:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 0:{ *:[i32] })  =>  (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 203203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
     /* 203206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 203210 */     GIR_RootConstrainSelectedInstOperands,
     /* 203211 */     // GIR_Coverage, 3990,
     /* 203211 */     GIR_EraseRootFromParent_Done,
     /* 203212 */   // Label 3764: @203212
     /* 203212 */   GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(203259), // Rule ID 3991 //
     /* 203217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 203220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 203225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203239 */     // MIs[0] Operand 3
     /* 203239 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
     /* 203250 */     // (intrinsic_wo_chain:{ *:[i64] } 310:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 1:{ *:[i32] })  =>  (XPACI:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 203250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACI),
     /* 203253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203255 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 203257 */     GIR_RootConstrainSelectedInstOperands,
     /* 203258 */     // GIR_Coverage, 3991,
     /* 203258 */     GIR_EraseRootFromParent_Done,
     /* 203259 */   // Label 3765: @203259
     /* 203259 */   GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(203306), // Rule ID 3992 //
     /* 203264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 203267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 203272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203286 */     // MIs[0] Operand 3
     /* 203286 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
     /* 203297 */     // (intrinsic_wo_chain:{ *:[i64] } 310:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 2:{ *:[i32] })  =>  (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 203297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
     /* 203300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 203304 */     GIR_RootConstrainSelectedInstOperands,
     /* 203305 */     // GIR_Coverage, 3992,
     /* 203305 */     GIR_EraseRootFromParent_Done,
     /* 203306 */   // Label 3766: @203306
     /* 203306 */   GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(203353), // Rule ID 3993 //
     /* 203311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 203314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_strip),
     /* 203319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 203322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203329 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 203333 */     // MIs[0] Operand 3
     /* 203333 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
     /* 203344 */     // (intrinsic_wo_chain:{ *:[i64] } 310:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, 3:{ *:[i32] })  =>  (XPACD:{ *:[i64] } GPR64:{ *:[i64] }:$Rd)
     /* 203344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XPACD),
     /* 203347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 203351 */     GIR_RootConstrainSelectedInstOperands,
     /* 203352 */     // GIR_Coverage, 3993,
     /* 203352 */     GIR_EraseRootFromParent_Done,
     /* 203353 */   // Label 3767: @203353
     /* 203353 */   GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(203417), // Rule ID 6968 //
     /* 203358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 203363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 203366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 203369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203377 */     // MIs[0] Operand 3
     /* 203377 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(8),
     /* 203388 */     // (intrinsic_wo_chain:{ *:[v8i8] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vn, 8:{ *:[i32] })  =>  (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Vn, (MOVIv2d_ns:{ *:[v8i16] } 0:{ *:[i32] }))
     /* 203388 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 203391 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 203395 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 203400 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 203403 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 203405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
     /* 203408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203410 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 203412 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 203415 */     GIR_RootConstrainSelectedInstOperands,
     /* 203416 */     // GIR_Coverage, 6968,
     /* 203416 */     GIR_EraseRootFromParent_Done,
     /* 203417 */   // Label 3768: @203417
     /* 203417 */   GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(203481), // Rule ID 6969 //
     /* 203422 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 203427 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 203430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 203433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203437 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203441 */     // MIs[0] Operand 3
     /* 203441 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(16),
     /* 203452 */     // (intrinsic_wo_chain:{ *:[v4i16] } 682:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, 16:{ *:[i32] })  =>  (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn, (MOVIv2d_ns:{ *:[v4i32] } 0:{ *:[i32] }))
     /* 203452 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 203455 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 203459 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 203464 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 203467 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 203469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
     /* 203472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 203476 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 203479 */     GIR_RootConstrainSelectedInstOperands,
     /* 203480 */     // GIR_Coverage, 6969,
     /* 203480 */     GIR_EraseRootFromParent_Done,
     /* 203481 */   // Label 3769: @203481
     /* 203481 */   GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(203545), // Rule ID 6970 //
     /* 203486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 203491 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 203494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 203497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203501 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203505 */     // MIs[0] Operand 3
     /* 203505 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(32),
     /* 203516 */     // (intrinsic_wo_chain:{ *:[v2i32] } 682:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, 32:{ *:[i32] })  =>  (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn, (MOVIv2d_ns:{ *:[v2i64] } 0:{ *:[i32] }))
     /* 203516 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 203519 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 203523 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 203528 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 203531 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 203533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
     /* 203536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203538 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 203540 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 203543 */     GIR_RootConstrainSelectedInstOperands,
     /* 203544 */     // GIR_Coverage, 6970,
     /* 203544 */     GIR_EraseRootFromParent_Done,
     /* 203545 */   // Label 3770: @203545
     /* 203545 */   GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(203591), // Rule ID 2140 //
     /* 203550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203553 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrn),
     /* 203558 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203561 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203572 */     // MIs[0] imm
     /* 203572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203575 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203580 */     // (intrinsic_wo_chain:{ *:[i32] } 717:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNs),
     /* 203583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203587 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203589 */     GIR_RootConstrainSelectedInstOperands,
     /* 203590 */     // GIR_Coverage, 2140,
     /* 203590 */     GIR_EraseRootFromParent_Done,
     /* 203591 */   // Label 3771: @203591
     /* 203591 */   GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(203637), // Rule ID 2141 //
     /* 203596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshrun),
     /* 203604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203618 */     // MIs[0] imm
     /* 203618 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203621 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203626 */     // (intrinsic_wo_chain:{ *:[i32] } 718:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQRSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNs),
     /* 203629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203631 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203633 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203635 */     GIR_RootConstrainSelectedInstOperands,
     /* 203636 */     // GIR_Coverage, 2141,
     /* 203636 */     GIR_EraseRootFromParent_Done,
     /* 203637 */   // Label 3772: @203637
     /* 203637 */   GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(203683), // Rule ID 2146 //
     /* 203642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrn),
     /* 203650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203664 */     // MIs[0] imm
     /* 203664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203667 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203672 */     // (intrinsic_wo_chain:{ *:[i32] } 721:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNs),
     /* 203675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203679 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203681 */     GIR_RootConstrainSelectedInstOperands,
     /* 203682 */     // GIR_Coverage, 2146,
     /* 203682 */     GIR_EraseRootFromParent_Done,
     /* 203683 */   // Label 3773: @203683
     /* 203683 */   GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(203729), // Rule ID 2147 //
     /* 203688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshrun),
     /* 203696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203710 */     // MIs[0] imm
     /* 203710 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203713 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203718 */     // (intrinsic_wo_chain:{ *:[i32] } 722:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SQSHRUNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNs),
     /* 203721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203723 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203725 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203727 */     GIR_RootConstrainSelectedInstOperands,
     /* 203728 */     // GIR_Coverage, 2147,
     /* 203728 */     GIR_EraseRootFromParent_Done,
     /* 203729 */   // Label 3774: @203729
     /* 203729 */   GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(203775), // Rule ID 2154 //
     /* 203734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshrn),
     /* 203742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203752 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203756 */     // MIs[0] imm
     /* 203756 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203759 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203764 */     // (intrinsic_wo_chain:{ *:[i32] } 766:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQRSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNs),
     /* 203767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203769 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203771 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203773 */     GIR_RootConstrainSelectedInstOperands,
     /* 203774 */     // GIR_Coverage, 2154,
     /* 203774 */     GIR_EraseRootFromParent_Done,
     /* 203775 */   // Label 3775: @203775
     /* 203775 */   GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(203821), // Rule ID 2157 //
     /* 203780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshrn),
     /* 203788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 203791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 203794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 203798 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203802 */     // MIs[0] imm
     /* 203802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203805 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203810 */     // (intrinsic_wo_chain:{ *:[i32] } 768:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UQSHRNs:{ *:[i32] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNs),
     /* 203813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203817 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203819 */     GIR_RootConstrainSelectedInstOperands,
     /* 203820 */     // GIR_Coverage, 2157,
     /* 203820 */     GIR_EraseRootFromParent_Done,
     /* 203821 */   // Label 3776: @203821
     /* 203821 */   GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(203867), // Rule ID 2163 //
     /* 203826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 203829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 203834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 203837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 203840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203848 */     // MIs[0] imm
     /* 203848 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203851 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 203856 */     // (intrinsic_wo_chain:{ *:[v4i16] } 787:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (FCVTZSv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i16_shift),
     /* 203859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203861 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203863 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203865 */     GIR_RootConstrainSelectedInstOperands,
     /* 203866 */     // GIR_Coverage, 2163,
     /* 203866 */     GIR_EraseRootFromParent_Done,
     /* 203867 */   // Label 3777: @203867
     /* 203867 */   GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(203913), // Rule ID 2164 //
     /* 203872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 203875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 203880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 203883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 203886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203890 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203894 */     // MIs[0] imm
     /* 203894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203897 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 203902 */     // (intrinsic_wo_chain:{ *:[v8i16] } 787:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (FCVTZSv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8i16_shift),
     /* 203905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203909 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203911 */     GIR_RootConstrainSelectedInstOperands,
     /* 203912 */     // GIR_Coverage, 2164,
     /* 203912 */     GIR_EraseRootFromParent_Done,
     /* 203913 */   // Label 3778: @203913
     /* 203913 */   GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(203959), // Rule ID 2165 //
     /* 203918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 203926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 203929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 203932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 203940 */     // MIs[0] imm
     /* 203940 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203943 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203948 */     // (intrinsic_wo_chain:{ *:[v2i32] } 787:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203948 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i32_shift),
     /* 203951 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203953 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 203955 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 203957 */     GIR_RootConstrainSelectedInstOperands,
     /* 203958 */     // GIR_Coverage, 2165,
     /* 203958 */     GIR_EraseRootFromParent_Done,
     /* 203959 */   // Label 3779: @203959
     /* 203959 */   GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(204005), // Rule ID 2166 //
     /* 203964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 203967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 203972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 203975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 203978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 203986 */     // MIs[0] imm
     /* 203986 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 203989 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 203994 */     // (intrinsic_wo_chain:{ *:[v4i32] } 787:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 203994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4i32_shift),
     /* 203997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 203999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204001 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204003 */     GIR_RootConstrainSelectedInstOperands,
     /* 204004 */     // GIR_Coverage, 2166,
     /* 204004 */     GIR_EraseRootFromParent_Done,
     /* 204005 */   // Label 3780: @204005
     /* 204005 */   GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(204051), // Rule ID 2167 //
     /* 204010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204013 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 204018 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 204021 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 204024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204032 */     // MIs[0] imm
     /* 204032 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204035 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 204040 */     // (intrinsic_wo_chain:{ *:[v2i64] } 787:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2i64_shift),
     /* 204043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204045 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204047 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204049 */     GIR_RootConstrainSelectedInstOperands,
     /* 204050 */     // GIR_Coverage, 2167,
     /* 204050 */     GIR_EraseRootFromParent_Done,
     /* 204051 */   // Label 3781: @204051
     /* 204051 */   GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(204097), // Rule ID 2168 //
     /* 204056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204059 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 204064 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 204067 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 204070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204078 */     // MIs[0] imm
     /* 204078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204081 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204086 */     // (intrinsic_wo_chain:{ *:[v4i16] } 788:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (FCVTZUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i16_shift),
     /* 204089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204091 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204093 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204095 */     GIR_RootConstrainSelectedInstOperands,
     /* 204096 */     // GIR_Coverage, 2168,
     /* 204096 */     GIR_EraseRootFromParent_Done,
     /* 204097 */   // Label 3782: @204097
     /* 204097 */   GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(204143), // Rule ID 2169 //
     /* 204102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 204110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 204113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 204116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204124 */     // MIs[0] imm
     /* 204124 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204127 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204132 */     // (intrinsic_wo_chain:{ *:[v8i16] } 788:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (FCVTZUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8i16_shift),
     /* 204135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204139 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204141 */     GIR_RootConstrainSelectedInstOperands,
     /* 204142 */     // GIR_Coverage, 2169,
     /* 204142 */     GIR_EraseRootFromParent_Done,
     /* 204143 */   // Label 3783: @204143
     /* 204143 */   GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(204189), // Rule ID 2170 //
     /* 204148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 204156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 204159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 204162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204166 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204170 */     // MIs[0] imm
     /* 204170 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204173 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204178 */     // (intrinsic_wo_chain:{ *:[v2i32] } 788:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204178 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i32_shift),
     /* 204181 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204183 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204185 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204187 */     GIR_RootConstrainSelectedInstOperands,
     /* 204188 */     // GIR_Coverage, 2170,
     /* 204188 */     GIR_EraseRootFromParent_Done,
     /* 204189 */   // Label 3784: @204189
     /* 204189 */   GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(204235), // Rule ID 2171 //
     /* 204194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 204202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 204205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 204208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204216 */     // MIs[0] imm
     /* 204216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204219 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204224 */     // (intrinsic_wo_chain:{ *:[v4i32] } 788:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4i32_shift),
     /* 204227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204231 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204233 */     GIR_RootConstrainSelectedInstOperands,
     /* 204234 */     // GIR_Coverage, 2171,
     /* 204234 */     GIR_EraseRootFromParent_Done,
     /* 204235 */   // Label 3785: @204235
     /* 204235 */   GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(204281), // Rule ID 2172 //
     /* 204240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 204248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 204251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 204254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204262 */     // MIs[0] imm
     /* 204262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204265 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 204270 */     // (intrinsic_wo_chain:{ *:[v2i64] } 788:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2i64_shift),
     /* 204273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204277 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204279 */     GIR_RootConstrainSelectedInstOperands,
     /* 204280 */     // GIR_Coverage, 2172,
     /* 204280 */     GIR_EraseRootFromParent_Done,
     /* 204281 */   // Label 3786: @204281
     /* 204281 */   GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(204327), // Rule ID 2173 //
     /* 204286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 204294 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 204297 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 204300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204308 */     // MIs[0] imm
     /* 204308 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204311 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204316 */     // (intrinsic_wo_chain:{ *:[v4f16] } 790:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i16_shift),
     /* 204319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204321 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204323 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204325 */     GIR_RootConstrainSelectedInstOperands,
     /* 204326 */     // GIR_Coverage, 2173,
     /* 204326 */     GIR_EraseRootFromParent_Done,
     /* 204327 */   // Label 3787: @204327
     /* 204327 */   GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(204373), // Rule ID 2174 //
     /* 204332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204335 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 204340 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 204343 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 204346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204350 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204354 */     // MIs[0] imm
     /* 204354 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204357 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204362 */     // (intrinsic_wo_chain:{ *:[v8f16] } 790:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8i16_shift),
     /* 204365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204369 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204371 */     GIR_RootConstrainSelectedInstOperands,
     /* 204372 */     // GIR_Coverage, 2174,
     /* 204372 */     GIR_EraseRootFromParent_Done,
     /* 204373 */   // Label 3788: @204373
     /* 204373 */   GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(204419), // Rule ID 2175 //
     /* 204378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 204386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 204389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 204392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204400 */     // MIs[0] imm
     /* 204400 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204403 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204408 */     // (intrinsic_wo_chain:{ *:[v2f32] } 790:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i32_shift),
     /* 204411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204415 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204417 */     GIR_RootConstrainSelectedInstOperands,
     /* 204418 */     // GIR_Coverage, 2175,
     /* 204418 */     GIR_EraseRootFromParent_Done,
     /* 204419 */   // Label 3789: @204419
     /* 204419 */   GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(204465), // Rule ID 2176 //
     /* 204424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 204432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 204435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 204438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204446 */     // MIs[0] imm
     /* 204446 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204449 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204454 */     // (intrinsic_wo_chain:{ *:[v4f32] } 790:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4i32_shift),
     /* 204457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204461 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204463 */     GIR_RootConstrainSelectedInstOperands,
     /* 204464 */     // GIR_Coverage, 2176,
     /* 204464 */     GIR_EraseRootFromParent_Done,
     /* 204465 */   // Label 3790: @204465
     /* 204465 */   GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(204511), // Rule ID 2177 //
     /* 204470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 204478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 204481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 204484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204492 */     // MIs[0] imm
     /* 204492 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204495 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 204500 */     // (intrinsic_wo_chain:{ *:[v2f64] } 790:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2i64_shift),
     /* 204503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204507 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204509 */     GIR_RootConstrainSelectedInstOperands,
     /* 204510 */     // GIR_Coverage, 2177,
     /* 204510 */     GIR_EraseRootFromParent_Done,
     /* 204511 */   // Label 3791: @204511
     /* 204511 */   GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(204557), // Rule ID 2179 //
     /* 204516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 204524 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 204527 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 204530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204534 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204538 */     // MIs[0] imm
     /* 204538 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204541 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 204546 */     // (intrinsic_wo_chain:{ *:[v8i8] } 682:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)  =>  (RSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204546 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv8i8_shift),
     /* 204549 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204551 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204553 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204555 */     GIR_RootConstrainSelectedInstOperands,
     /* 204556 */     // GIR_Coverage, 2179,
     /* 204556 */     GIR_EraseRootFromParent_Done,
     /* 204557 */   // Label 3792: @204557
     /* 204557 */   GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(204603), // Rule ID 2181 //
     /* 204562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 204570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 204573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 204576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204584 */     // MIs[0] imm
     /* 204584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204587 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 204592 */     // (intrinsic_wo_chain:{ *:[v4i16] } 682:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)  =>  (RSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv4i16_shift),
     /* 204595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204599 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204601 */     GIR_RootConstrainSelectedInstOperands,
     /* 204602 */     // GIR_Coverage, 2181,
     /* 204602 */     GIR_EraseRootFromParent_Done,
     /* 204603 */   // Label 3793: @204603
     /* 204603 */   GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(204649), // Rule ID 2183 //
     /* 204608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rshrn),
     /* 204616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 204619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 204622 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204626 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204630 */     // MIs[0] imm
     /* 204630 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204633 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 204638 */     // (intrinsic_wo_chain:{ *:[v2i32] } 682:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)  =>  (RSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNv2i32_shift),
     /* 204641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204645 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204647 */     GIR_RootConstrainSelectedInstOperands,
     /* 204648 */     // GIR_Coverage, 2183,
     /* 204648 */     GIR_EraseRootFromParent_Done,
     /* 204649 */   // Label 3794: @204649
     /* 204649 */   GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(204695), // Rule ID 2275 //
     /* 204654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 204662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 204665 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 204668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204672 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204676 */     // MIs[0] imm
     /* 204676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204679 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204684 */     // (intrinsic_wo_chain:{ *:[v4f16] } 791:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFv4i16_shift:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i16_shift),
     /* 204687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204691 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204693 */     GIR_RootConstrainSelectedInstOperands,
     /* 204694 */     // GIR_Coverage, 2275,
     /* 204694 */     GIR_EraseRootFromParent_Done,
     /* 204695 */   // Label 3795: @204695
     /* 204695 */   GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(204741), // Rule ID 2276 //
     /* 204700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 204703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 204708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 204711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 204714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204722 */     // MIs[0] imm
     /* 204722 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204725 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 204730 */     // (intrinsic_wo_chain:{ *:[v8f16] } 791:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFv8i16_shift:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8i16_shift),
     /* 204733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204735 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204737 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204739 */     GIR_RootConstrainSelectedInstOperands,
     /* 204740 */     // GIR_Coverage, 2276,
     /* 204740 */     GIR_EraseRootFromParent_Done,
     /* 204741 */   // Label 3796: @204741
     /* 204741 */   GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(204787), // Rule ID 2277 //
     /* 204746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 204754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 204757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 204760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 204768 */     // MIs[0] imm
     /* 204768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204776 */     // (intrinsic_wo_chain:{ *:[v2f32] } 791:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFv2i32_shift:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i32_shift),
     /* 204779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204781 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204783 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204785 */     GIR_RootConstrainSelectedInstOperands,
     /* 204786 */     // GIR_Coverage, 2277,
     /* 204786 */     GIR_EraseRootFromParent_Done,
     /* 204787 */   // Label 3797: @204787
     /* 204787 */   GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(204833), // Rule ID 2278 //
     /* 204792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 204800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 204803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 204806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204810 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204814 */     // MIs[0] imm
     /* 204814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204817 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 204822 */     // (intrinsic_wo_chain:{ *:[v4f32] } 791:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFv4i32_shift:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4i32_shift),
     /* 204825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204829 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204831 */     GIR_RootConstrainSelectedInstOperands,
     /* 204832 */     // GIR_Coverage, 2278,
     /* 204832 */     GIR_EraseRootFromParent_Done,
     /* 204833 */   // Label 3798: @204833
     /* 204833 */   GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(204879), // Rule ID 2279 //
     /* 204838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 204841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 204846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 204849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 204852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204856 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 204860 */     // MIs[0] imm
     /* 204860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204863 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 204868 */     // (intrinsic_wo_chain:{ *:[v2f64] } 791:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFv2i64_shift:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 204868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2i64_shift),
     /* 204871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 204873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 204875 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 204877 */     GIR_RootConstrainSelectedInstOperands,
     /* 204878 */     // GIR_Coverage, 2279,
     /* 204878 */     GIR_EraseRootFromParent_Done,
     /* 204879 */   // Label 3799: @204879
     /* 204879 */   GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(204925), // Rule ID 3626 //
     /* 204884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 204887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 204892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 204895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 204898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204906 */     // MIs[0] Idx
     /* 204906 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204909 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_0),
     /* 204914 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1678:{ *:[iPTR] }, ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx)  =>  (PMOV_PZI_B:{ *:[nxv16i1] } ZPRAny:{ *:[nxv16i8] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_0>>:$Idx)
     /* 204914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_B),
     /* 204917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 204919 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 204921 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 204923 */     GIR_RootConstrainSelectedInstOperands,
     /* 204924 */     // GIR_Coverage, 3626,
     /* 204924 */     GIR_EraseRootFromParent_Done,
     /* 204925 */   // Label 3800: @204925
     /* 204925 */   GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(204971), // Rule ID 3627 //
     /* 204930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 204933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 204938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 204941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 204944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204952 */     // MIs[0] Idx
     /* 204952 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 204955 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 204960 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1678:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx)  =>  (PMOV_PZI_H:{ *:[nxv8i1] } ZPRAny:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Idx)
     /* 204960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_H),
     /* 204963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 204965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 204967 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 204969 */     GIR_RootConstrainSelectedInstOperands,
     /* 204970 */     // GIR_Coverage, 3627,
     /* 204970 */     GIR_EraseRootFromParent_Done,
     /* 204971 */   // Label 3801: @204971
     /* 204971 */   GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(205017), // Rule ID 3628 //
     /* 204976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 204979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 204984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 204987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 204990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 204994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 204998 */     // MIs[0] Idx
     /* 204998 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205001 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 205006 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1678:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx)  =>  (PMOV_PZI_S:{ *:[nxv4i1] } ZPRAny:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Idx)
     /* 205006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_S),
     /* 205009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 205013 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 205015 */     GIR_RootConstrainSelectedInstOperands,
     /* 205016 */     // GIR_Coverage, 3628,
     /* 205016 */     GIR_EraseRootFromParent_Done,
     /* 205017 */   // Label 3802: @205017
     /* 205017 */   GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(205063), // Rule ID 3629 //
     /* 205022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 205025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_pred_lane),
     /* 205030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 205033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 205036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 205040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 205044 */     // MIs[0] Idx
     /* 205044 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205047 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 205052 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1678:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx)  =>  (PMOV_PZI_D:{ *:[nxv2i1] } ZPRAny:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Idx)
     /* 205052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_PZI_D),
     /* 205055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 205057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 205059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Idx
     /* 205061 */     GIR_RootConstrainSelectedInstOperands,
     /* 205062 */     // GIR_Coverage, 3629,
     /* 205062 */     GIR_EraseRootFromParent_Done,
     /* 205063 */   // Label 3803: @205063
     /* 205063 */   GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(205106), // Rule ID 6903 //
     /* 205068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 205073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 205076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205087 */     // MIs[0] imm
     /* 205087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205090 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 205095 */     // (intrinsic_wo_chain:{ *:[i32] } 787:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZSs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 205095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSs),
     /* 205098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205102 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205104 */     GIR_RootConstrainSelectedInstOperands,
     /* 205105 */     // GIR_Coverage, 6903,
     /* 205105 */     GIR_EraseRootFromParent_Done,
     /* 205106 */   // Label 3804: @205106
     /* 205106 */   GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(205149), // Rule ID 6904 //
     /* 205111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 205116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 205119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205122 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205126 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205130 */     // MIs[0] imm
     /* 205130 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205133 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 205138 */     // (intrinsic_wo_chain:{ *:[i32] } 788:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (FCVTZUs:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 205138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUs),
     /* 205141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205143 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205145 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205147 */     GIR_RootConstrainSelectedInstOperands,
     /* 205148 */     // GIR_Coverage, 6904,
     /* 205148 */     GIR_EraseRootFromParent_Done,
     /* 205149 */   // Label 3805: @205149
     /* 205149 */   GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(205192), // Rule ID 6905 //
     /* 205154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 205159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205173 */     // MIs[0] imm
     /* 205173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205176 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205181 */     // (intrinsic_wo_chain:{ *:[i64] } 787:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
     /* 205184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205188 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205190 */     GIR_RootConstrainSelectedInstOperands,
     /* 205191 */     // GIR_Coverage, 6905,
     /* 205191 */     GIR_EraseRootFromParent_Done,
     /* 205192 */   // Label 3806: @205192
     /* 205192 */   GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(205235), // Rule ID 6906 //
     /* 205197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 205202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205216 */     // MIs[0] imm
     /* 205216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205219 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205224 */     // (intrinsic_wo_chain:{ *:[i64] } 788:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
     /* 205227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205231 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205233 */     GIR_RootConstrainSelectedInstOperands,
     /* 205234 */     // GIR_Coverage, 6906,
     /* 205234 */     GIR_EraseRootFromParent_Done,
     /* 205235 */   // Label 3807: @205235
     /* 205235 */   GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(205278), // Rule ID 6907 //
     /* 205240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 205245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205251 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205255 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205259 */     // MIs[0] imm
     /* 205259 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205262 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205267 */     // (intrinsic_wo_chain:{ *:[v1i64] } 787:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZSd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSd),
     /* 205270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205274 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205276 */     GIR_RootConstrainSelectedInstOperands,
     /* 205277 */     // GIR_Coverage, 6907,
     /* 205277 */     GIR_EraseRootFromParent_Done,
     /* 205278 */   // Label 3808: @205278
     /* 205278 */   GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(205321), // Rule ID 6908 //
     /* 205283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 205288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205298 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205302 */     // MIs[0] imm
     /* 205302 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205305 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205310 */     // (intrinsic_wo_chain:{ *:[v1i64] } 788:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (FCVTZUd:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUd),
     /* 205313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205315 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205317 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205319 */     GIR_RootConstrainSelectedInstOperands,
     /* 205320 */     // GIR_Coverage, 6908,
     /* 205320 */     GIR_EraseRootFromParent_Done,
     /* 205321 */   // Label 3809: @205321
     /* 205321 */   GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(205364), // Rule ID 6909 //
     /* 205326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 205331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 205334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205341 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205345 */     // MIs[0] imm
     /* 205345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205348 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 205353 */     // (intrinsic_wo_chain:{ *:[f32] } 791:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (UCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 205353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFs),
     /* 205356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205360 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205362 */     GIR_RootConstrainSelectedInstOperands,
     /* 205363 */     // GIR_Coverage, 6909,
     /* 205363 */     GIR_EraseRootFromParent_Done,
     /* 205364 */   // Label 3810: @205364
     /* 205364 */   GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(205407), // Rule ID 6910 //
     /* 205369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 205374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205388 */     // MIs[0] imm
     /* 205388 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205391 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205396 */     // (intrinsic_wo_chain:{ *:[f64] } 791:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
     /* 205399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205403 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205405 */     GIR_RootConstrainSelectedInstOperands,
     /* 205406 */     // GIR_Coverage, 6910,
     /* 205406 */     GIR_EraseRootFromParent_Done,
     /* 205407 */   // Label 3811: @205407
     /* 205407 */   GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(205450), // Rule ID 6911 //
     /* 205412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 205417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205427 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205431 */     // MIs[0] imm
     /* 205431 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205434 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205439 */     // (intrinsic_wo_chain:{ *:[v1f64] } 790:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
     /* 205442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205444 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205446 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205448 */     GIR_RootConstrainSelectedInstOperands,
     /* 205449 */     // GIR_Coverage, 6911,
     /* 205449 */     GIR_EraseRootFromParent_Done,
     /* 205450 */   // Label 3812: @205450
     /* 205450 */   GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(205493), // Rule ID 6912 //
     /* 205455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 205460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205470 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205474 */     // MIs[0] imm
     /* 205474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205477 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205482 */     // (intrinsic_wo_chain:{ *:[f64] } 790:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SCVTFd:{ *:[f64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFd),
     /* 205485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205489 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205491 */     GIR_RootConstrainSelectedInstOperands,
     /* 205492 */     // GIR_Coverage, 6912,
     /* 205492 */     GIR_EraseRootFromParent_Done,
     /* 205493 */   // Label 3813: @205493
     /* 205493 */   GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(205536), // Rule ID 6913 //
     /* 205498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 205503 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205506 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205513 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205517 */     // MIs[0] imm
     /* 205517 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205520 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205525 */     // (intrinsic_wo_chain:{ *:[v1f64] } 791:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (UCVTFd:{ *:[v1f64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 205525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFd),
     /* 205528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205530 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205532 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205534 */     GIR_RootConstrainSelectedInstOperands,
     /* 205535 */     // GIR_Coverage, 6913,
     /* 205535 */     GIR_EraseRootFromParent_Done,
     /* 205536 */   // Label 3814: @205536
     /* 205536 */   GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(205579), // Rule ID 6914 //
     /* 205541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 205546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 205549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205556 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205560 */     // MIs[0] imm
     /* 205560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205563 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 205568 */     // (intrinsic_wo_chain:{ *:[f32] } 790:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SCVTFs:{ *:[f32] } FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)
     /* 205568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFs),
     /* 205571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 205575 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205577 */     GIR_RootConstrainSelectedInstOperands,
     /* 205578 */     // GIR_Coverage, 6914,
     /* 205578 */     GIR_EraseRootFromParent_Done,
     /* 205579 */   // Label 3815: @205579
     /* 205579 */   GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(205651), // Rule ID 6916 //
     /* 205584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 205589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 205592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205603 */     // MIs[0] imm
     /* 205603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205606 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 205611 */     // (intrinsic_wo_chain:{ *:[f16] } 790:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 205611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 205614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 205618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205623 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 205629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205634 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 205642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205644 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 205647 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205649 */     GIR_RootConstrainSelectedInstOperands,
     /* 205650 */     // GIR_Coverage, 6916,
     /* 205650 */     GIR_EraseRootFromParent_Done,
     /* 205651 */   // Label 3816: @205651
     /* 205651 */   GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(205723), // Rule ID 6917 //
     /* 205656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxs2fp),
     /* 205661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 205664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205671 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205675 */     // MIs[0] imm
     /* 205675 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205678 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 205683 */     // (intrinsic_wo_chain:{ *:[f16] } 790:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 205683 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 205686 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 205690 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205695 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 205701 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205706 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFh),
     /* 205714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205716 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 205719 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205721 */     GIR_RootConstrainSelectedInstOperands,
     /* 205722 */     // GIR_Coverage, 6917,
     /* 205722 */     GIR_EraseRootFromParent_Done,
     /* 205723 */   // Label 3817: @205723
     /* 205723 */   GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(205795), // Rule ID 6919 //
     /* 205728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 205733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 205736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 205739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205747 */     // MIs[0] imm
     /* 205747 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205750 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 205755 */     // (intrinsic_wo_chain:{ *:[f16] } 791:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR32:{ *:[i32] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 205755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 205758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 205762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205767 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 205773 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205778 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 205786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205788 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 205791 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205793 */     GIR_RootConstrainSelectedInstOperands,
     /* 205794 */     // GIR_Coverage, 6919,
     /* 205794 */     GIR_EraseRootFromParent_Done,
     /* 205795 */   // Label 3818: @205795
     /* 205795 */   GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(205867), // Rule ID 6920 //
     /* 205800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfxu2fp),
     /* 205805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 205808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 205811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205819 */     // MIs[0] imm
     /* 205819 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205822 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 205827 */     // (intrinsic_wo_chain:{ *:[f16] } 791:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (UCVTFh:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR64:{ *:[i64] }:$Rn, hsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)
     /* 205827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 205830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 205834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205839 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 205845 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205850 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFh),
     /* 205858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 205860 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 205863 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 205865 */     GIR_RootConstrainSelectedInstOperands,
     /* 205866 */     // GIR_Coverage, 6920,
     /* 205866 */     GIR_EraseRootFromParent_Done,
     /* 205867 */   // Label 3819: @205867
     /* 205867 */   GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(205965), // Rule ID 6921 //
     /* 205872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 205877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 205880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 205883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205887 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205891 */     // MIs[0] imm
     /* 205891 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205894 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 205899 */     // (intrinsic_wo_chain:{ *:[i32] } 787:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
     /* 205899 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 205902 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
     /* 205906 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205911 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 205915 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // imm
     /* 205919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 205921 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 205924 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 205928 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 205933 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 205935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 205938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 205940 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 205943 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 205946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 205949 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 205959 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205964 */     // GIR_Coverage, 6921,
     /* 205964 */     GIR_EraseRootFromParent_Done,
     /* 205965 */   // Label 3820: @205965
     /* 205965 */   GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(206063), // Rule ID 6922 //
     /* 205970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxs),
     /* 205975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 205978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 205981 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 205985 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 205989 */     // MIs[0] imm
     /* 205989 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 205992 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 205997 */     // (intrinsic_wo_chain:{ *:[i64] } 787:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZSh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
     /* 205997 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 206000 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSh),
     /* 206004 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206009 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 206013 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // imm
     /* 206017 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 206019 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 206022 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 206026 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206031 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 206033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 206036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 206038 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 206041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 206044 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 206047 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 206052 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 206057 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 206062 */     // GIR_Coverage, 6922,
     /* 206062 */     GIR_EraseRootFromParent_Done,
     /* 206063 */   // Label 3821: @206063
     /* 206063 */   GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(206161), // Rule ID 6923 //
     /* 206068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 206073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 206076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 206079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 206083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 206087 */     // MIs[0] imm
     /* 206087 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206090 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 206095 */     // (intrinsic_wo_chain:{ *:[i32] } 788:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm), hsub:{ *:[i32] })
     /* 206095 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 206098 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
     /* 206102 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206107 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 206111 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // imm
     /* 206115 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 206117 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 206120 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 206124 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206129 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 206131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 206134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 206136 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 206139 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 206142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 206145 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 206150 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 206155 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 206160 */     // GIR_Coverage, 6923,
     /* 206160 */     GIR_EraseRootFromParent_Done,
     /* 206161 */   // Label 3822: @206161
     /* 206161 */   GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(206259), // Rule ID 6924 //
     /* 206166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcvtfp2fxu),
     /* 206171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 206174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 206177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 206181 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 206185 */     // MIs[0] imm
     /* 206185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206188 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 206193 */     // (intrinsic_wo_chain:{ *:[i64] } 788:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (FCVTZUh:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm), hsub:{ *:[i32] })
     /* 206193 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 206196 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUh),
     /* 206200 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206205 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 206209 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // imm
     /* 206213 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 206215 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 206218 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 206222 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 206227 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 206229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 206232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 206234 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 206237 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 206240 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 206243 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 206248 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 206253 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 206258 */     // GIR_Coverage, 6924,
     /* 206258 */     GIR_EraseRootFromParent_Done,
     /* 206259 */   // Label 3823: @206259
     /* 206259 */   GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(206317), // Rule ID 7627 //
     /* 206264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
     /* 206269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 206272 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 206275 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 206278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 206282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 206286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 206290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 206294 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm64_0_65535),
     /* 206298 */     // MIs[1] Operand 1
     /* 206298 */     // No operand predicates
     /* 206298 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 206300 */     // (intrinsic_wo_chain:{ *:[i64] } 306:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm)  =>  (MOVKXi:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm64_0_65535>>:$imm), 48:{ *:[i32] })
     /* 206300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVKXi),
     /* 206303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 206305 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 206307 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // imm
     /* 206312 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/48,
     /* 206315 */     GIR_RootConstrainSelectedInstOperands,
     /* 206316 */     // GIR_Coverage, 7627,
     /* 206316 */     GIR_EraseRootFromParent_Done,
     /* 206317 */   // Label 3824: @206317
     /* 206317 */   GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(206359), // Rule ID 3111 //
     /* 206322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 206330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 206336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206340 */     // MIs[0] Op2
     /* 206340 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206343 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 206348 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1920:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)  =>  (SSHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)
     /* 206348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_H),
     /* 206351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206353 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206355 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206357 */     GIR_RootConstrainSelectedInstOperands,
     /* 206358 */     // GIR_Coverage, 3111,
     /* 206358 */     GIR_EraseRootFromParent_Done,
     /* 206359 */   // Label 3825: @206359
     /* 206359 */   GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(206401), // Rule ID 3112 //
     /* 206364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206367 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 206372 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206375 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206378 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206382 */     // MIs[0] Op2
     /* 206382 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206385 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 206390 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1920:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)  =>  (SSHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)
     /* 206390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_S),
     /* 206393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206395 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206397 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206399 */     GIR_RootConstrainSelectedInstOperands,
     /* 206400 */     // GIR_Coverage, 3112,
     /* 206400 */     GIR_EraseRootFromParent_Done,
     /* 206401 */   // Label 3826: @206401
     /* 206401 */   GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(206443), // Rule ID 3113 //
     /* 206406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206409 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllb),
     /* 206414 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206417 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206424 */     // MIs[0] Op2
     /* 206424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206427 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 206432 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1920:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)  =>  (SSHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)
     /* 206432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLB_ZZI_D),
     /* 206435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206441 */     GIR_RootConstrainSelectedInstOperands,
     /* 206442 */     // GIR_Coverage, 3113,
     /* 206442 */     GIR_EraseRootFromParent_Done,
     /* 206443 */   // Label 3827: @206443
     /* 206443 */   GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(206485), // Rule ID 3147 //
     /* 206448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 206456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 206459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206466 */     // MIs[0] Op2
     /* 206466 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206469 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 206474 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1900:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (SQSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 206474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_B),
     /* 206477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206481 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206483 */     GIR_RootConstrainSelectedInstOperands,
     /* 206484 */     // GIR_Coverage, 3147,
     /* 206484 */     GIR_EraseRootFromParent_Done,
     /* 206485 */   // Label 3828: @206485
     /* 206485 */   GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(206527), // Rule ID 3148 //
     /* 206490 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206493 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 206498 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206501 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206508 */     // MIs[0] Op2
     /* 206508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206511 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 206516 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1900:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (SQSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 206516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_H),
     /* 206519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206523 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206525 */     GIR_RootConstrainSelectedInstOperands,
     /* 206526 */     // GIR_Coverage, 3148,
     /* 206526 */     GIR_EraseRootFromParent_Done,
     /* 206527 */   // Label 3829: @206527
     /* 206527 */   GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(206569), // Rule ID 3149 //
     /* 206532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunb),
     /* 206540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206546 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206550 */     // MIs[0] Op2
     /* 206550 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206553 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 206558 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1900:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (SQSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 206558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNB_ZZI_S),
     /* 206561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206567 */     GIR_RootConstrainSelectedInstOperands,
     /* 206568 */     // GIR_Coverage, 3149,
     /* 206568 */     GIR_EraseRootFromParent_Done,
     /* 206569 */   // Label 3830: @206569
     /* 206569 */   GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(206611), // Rule ID 3612 //
     /* 206574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 206585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 206588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206592 */     // MIs[0] Op2
     /* 206592 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206595 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 206600 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1376:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2)  =>  (DUPQ_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Op2)
     /* 206600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_B),
     /* 206603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206607 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206609 */     GIR_RootConstrainSelectedInstOperands,
     /* 206610 */     // GIR_Coverage, 3612,
     /* 206610 */     GIR_EraseRootFromParent_Done,
     /* 206611 */   // Label 3831: @206611
     /* 206611 */   GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(206653), // Rule ID 3613 //
     /* 206616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206634 */     // MIs[0] Op2
     /* 206634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206637 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 206642 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1376:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)  =>  (DUPQ_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
     /* 206642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
     /* 206645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206651 */     GIR_RootConstrainSelectedInstOperands,
     /* 206652 */     // GIR_Coverage, 3613,
     /* 206652 */     GIR_EraseRootFromParent_Done,
     /* 206653 */   // Label 3832: @206653
     /* 206653 */   GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(206695), // Rule ID 3614 //
     /* 206658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206676 */     // MIs[0] Op2
     /* 206676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206679 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 206684 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1376:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)  =>  (DUPQ_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
     /* 206684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
     /* 206687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206693 */     GIR_RootConstrainSelectedInstOperands,
     /* 206694 */     // GIR_Coverage, 3614,
     /* 206694 */     GIR_EraseRootFromParent_Done,
     /* 206695 */   // Label 3833: @206695
     /* 206695 */   GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(206737), // Rule ID 3615 //
     /* 206700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206718 */     // MIs[0] Op2
     /* 206718 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206721 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 206726 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1376:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)  =>  (DUPQ_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
     /* 206726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
     /* 206729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206731 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206733 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206735 */     GIR_RootConstrainSelectedInstOperands,
     /* 206736 */     // GIR_Coverage, 3615,
     /* 206736 */     GIR_EraseRootFromParent_Done,
     /* 206737 */   // Label 3834: @206737
     /* 206737 */   GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(206779), // Rule ID 3616 //
     /* 206742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206745 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206750 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206753 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206760 */     // MIs[0] Op2
     /* 206760 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206763 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 206768 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1376:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)  =>  (DUPQ_ZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op2)
     /* 206768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_H),
     /* 206771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206773 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206777 */     GIR_RootConstrainSelectedInstOperands,
     /* 206778 */     // GIR_Coverage, 3616,
     /* 206778 */     GIR_EraseRootFromParent_Done,
     /* 206779 */   // Label 3835: @206779
     /* 206779 */   GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(206821), // Rule ID 3617 //
     /* 206784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206787 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206792 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206802 */     // MIs[0] Op2
     /* 206802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206805 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 206810 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1376:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)  =>  (DUPQ_ZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op2)
     /* 206810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_S),
     /* 206813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206819 */     GIR_RootConstrainSelectedInstOperands,
     /* 206820 */     // GIR_Coverage, 3617,
     /* 206820 */     GIR_EraseRootFromParent_Done,
     /* 206821 */   // Label 3836: @206821
     /* 206821 */   GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(206863), // Rule ID 3618 //
     /* 206826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 206829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 206834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 206837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206844 */     // MIs[0] Op2
     /* 206844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206847 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 206852 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1376:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)  =>  (DUPQ_ZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op2)
     /* 206852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPQ_ZZI_D),
     /* 206855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206859 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206861 */     GIR_RootConstrainSelectedInstOperands,
     /* 206862 */     // GIR_Coverage, 3618,
     /* 206862 */     GIR_EraseRootFromParent_Done,
     /* 206863 */   // Label 3837: @206863
     /* 206863 */   GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(206905), // Rule ID 12575 //
     /* 206868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 206876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 206879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 206882 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206886 */     // MIs[0] Op2
     /* 206886 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206889 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 206894 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1893:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (SQRSHRUNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 206894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_B),
     /* 206897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206903 */     GIR_RootConstrainSelectedInstOperands,
     /* 206904 */     // GIR_Coverage, 12575,
     /* 206904 */     GIR_EraseRootFromParent_Done,
     /* 206905 */   // Label 3838: @206905
     /* 206905 */   GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(206947), // Rule ID 12576 //
     /* 206910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 206918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 206921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 206924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206928 */     // MIs[0] Op2
     /* 206928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206931 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 206936 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1893:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (SQRSHRUNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 206936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_H),
     /* 206939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206945 */     GIR_RootConstrainSelectedInstOperands,
     /* 206946 */     // GIR_Coverage, 12576,
     /* 206946 */     GIR_EraseRootFromParent_Done,
     /* 206947 */   // Label 3839: @206947
     /* 206947 */   GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(206989), // Rule ID 12577 //
     /* 206952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunb),
     /* 206960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 206963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 206966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 206970 */     // MIs[0] Op2
     /* 206970 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 206973 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 206978 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1893:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (SQRSHRUNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 206978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNB_ZZI_S),
     /* 206981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 206983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 206985 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 206987 */     GIR_RootConstrainSelectedInstOperands,
     /* 206988 */     // GIR_Coverage, 12577,
     /* 206988 */     GIR_EraseRootFromParent_Done,
     /* 206989 */   // Label 3840: @206989
     /* 206989 */   GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(207031), // Rule ID 12578 //
     /* 206994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 206997 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 207002 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207012 */     // MIs[0] Op2
     /* 207012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207015 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207020 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1770:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (SHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_B),
     /* 207023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207027 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207029 */     GIR_RootConstrainSelectedInstOperands,
     /* 207030 */     // GIR_Coverage, 12578,
     /* 207030 */     GIR_EraseRootFromParent_Done,
     /* 207031 */   // Label 3841: @207031
     /* 207031 */   GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(207073), // Rule ID 12579 //
     /* 207036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207039 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 207044 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207047 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207054 */     // MIs[0] Op2
     /* 207054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207057 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207062 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1770:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (SHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_H),
     /* 207065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207071 */     GIR_RootConstrainSelectedInstOperands,
     /* 207072 */     // GIR_Coverage, 12579,
     /* 207072 */     GIR_EraseRootFromParent_Done,
     /* 207073 */   // Label 3842: @207073
     /* 207073 */   GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(207115), // Rule ID 12580 //
     /* 207078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnb),
     /* 207086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207092 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207096 */     // MIs[0] Op2
     /* 207096 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207099 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207104 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1770:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (SHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207104 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNB_ZZI_S),
     /* 207107 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207109 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207111 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207113 */     GIR_RootConstrainSelectedInstOperands,
     /* 207114 */     // GIR_Coverage, 12580,
     /* 207114 */     GIR_EraseRootFromParent_Done,
     /* 207115 */   // Label 3843: @207115
     /* 207115 */   GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(207157), // Rule ID 12582 //
     /* 207120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 207128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207138 */     // MIs[0] Op2
     /* 207138 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207141 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207146 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1728:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (RSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_B),
     /* 207149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207151 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207155 */     GIR_RootConstrainSelectedInstOperands,
     /* 207156 */     // GIR_Coverage, 12582,
     /* 207156 */     GIR_EraseRootFromParent_Done,
     /* 207157 */   // Label 3844: @207157
     /* 207157 */   GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(207199), // Rule ID 12584 //
     /* 207162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 207170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207180 */     // MIs[0] Op2
     /* 207180 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207183 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207188 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1728:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (RSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_H),
     /* 207191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207195 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207197 */     GIR_RootConstrainSelectedInstOperands,
     /* 207198 */     // GIR_Coverage, 12584,
     /* 207198 */     GIR_EraseRootFromParent_Done,
     /* 207199 */   // Label 3845: @207199
     /* 207199 */   GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(207241), // Rule ID 12586 //
     /* 207204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnb),
     /* 207212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207218 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207222 */     // MIs[0] Op2
     /* 207222 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207225 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207230 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1728:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (RSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNB_ZZI_S),
     /* 207233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207237 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207239 */     GIR_RootConstrainSelectedInstOperands,
     /* 207240 */     // GIR_Coverage, 12586,
     /* 207240 */     GIR_EraseRootFromParent_Done,
     /* 207241 */   // Label 3846: @207241
     /* 207241 */   GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(207283), // Rule ID 12587 //
     /* 207246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 207254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207264 */     // MIs[0] Op2
     /* 207264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207267 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207272 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1898:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (SQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_B),
     /* 207275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207279 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207281 */     GIR_RootConstrainSelectedInstOperands,
     /* 207282 */     // GIR_Coverage, 12587,
     /* 207282 */     GIR_EraseRootFromParent_Done,
     /* 207283 */   // Label 3847: @207283
     /* 207283 */   GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(207325), // Rule ID 12588 //
     /* 207288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 207296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207306 */     // MIs[0] Op2
     /* 207306 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207309 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207314 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1898:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (SQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_H),
     /* 207317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207321 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207323 */     GIR_RootConstrainSelectedInstOperands,
     /* 207324 */     // GIR_Coverage, 12588,
     /* 207324 */     GIR_EraseRootFromParent_Done,
     /* 207325 */   // Label 3848: @207325
     /* 207325 */   GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(207367), // Rule ID 12589 //
     /* 207330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207333 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnb),
     /* 207338 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207341 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207344 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207348 */     // MIs[0] Op2
     /* 207348 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207351 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207356 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1898:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (SQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNB_ZZI_S),
     /* 207359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207363 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207365 */     GIR_RootConstrainSelectedInstOperands,
     /* 207366 */     // GIR_Coverage, 12589,
     /* 207366 */     GIR_EraseRootFromParent_Done,
     /* 207367 */   // Label 3849: @207367
     /* 207367 */   GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(207409), // Rule ID 12590 //
     /* 207372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207375 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 207380 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207383 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207390 */     // MIs[0] Op2
     /* 207390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207393 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207398 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1887:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (SQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_B),
     /* 207401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207407 */     GIR_RootConstrainSelectedInstOperands,
     /* 207408 */     // GIR_Coverage, 12590,
     /* 207408 */     GIR_EraseRootFromParent_Done,
     /* 207409 */   // Label 3850: @207409
     /* 207409 */   GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(207451), // Rule ID 12591 //
     /* 207414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 207422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207432 */     // MIs[0] Op2
     /* 207432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207435 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207440 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1887:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (SQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_H),
     /* 207443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207445 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207447 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207449 */     GIR_RootConstrainSelectedInstOperands,
     /* 207450 */     // GIR_Coverage, 12591,
     /* 207450 */     GIR_EraseRootFromParent_Done,
     /* 207451 */   // Label 3851: @207451
     /* 207451 */   GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(207493), // Rule ID 12592 //
     /* 207456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnb),
     /* 207464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207474 */     // MIs[0] Op2
     /* 207474 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207477 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207482 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1887:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (SQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNB_ZZI_S),
     /* 207485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207491 */     GIR_RootConstrainSelectedInstOperands,
     /* 207492 */     // GIR_Coverage, 12592,
     /* 207492 */     GIR_EraseRootFromParent_Done,
     /* 207493 */   // Label 3852: @207493
     /* 207493 */   GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(207535), // Rule ID 12593 //
     /* 207498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 207506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207512 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207516 */     // MIs[0] Op2
     /* 207516 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207519 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207524 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2097:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (UQSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_B),
     /* 207527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207529 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207531 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207533 */     GIR_RootConstrainSelectedInstOperands,
     /* 207534 */     // GIR_Coverage, 12593,
     /* 207534 */     GIR_EraseRootFromParent_Done,
     /* 207535 */   // Label 3853: @207535
     /* 207535 */   GIM_Try, /*On fail goto*//*Label 3854*/ GIMT_Encode4(207577), // Rule ID 12594 //
     /* 207540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207543 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 207548 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207558 */     // MIs[0] Op2
     /* 207558 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207561 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207566 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2097:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (UQSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_H),
     /* 207569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207575 */     GIR_RootConstrainSelectedInstOperands,
     /* 207576 */     // GIR_Coverage, 12594,
     /* 207576 */     GIR_EraseRootFromParent_Done,
     /* 207577 */   // Label 3854: @207577
     /* 207577 */   GIM_Try, /*On fail goto*//*Label 3855*/ GIMT_Encode4(207619), // Rule ID 12595 //
     /* 207582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnb),
     /* 207590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207600 */     // MIs[0] Op2
     /* 207600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207603 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207608 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2097:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (UQSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207608 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNB_ZZI_S),
     /* 207611 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207615 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207617 */     GIR_RootConstrainSelectedInstOperands,
     /* 207618 */     // GIR_Coverage, 12595,
     /* 207618 */     GIR_EraseRootFromParent_Done,
     /* 207619 */   // Label 3855: @207619
     /* 207619 */   GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(207661), // Rule ID 12596 //
     /* 207624 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207627 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 207632 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 207635 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207642 */     // MIs[0] Op2
     /* 207642 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207645 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 207650 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2093:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)  =>  (UQRSHRNB_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op2)
     /* 207650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_B),
     /* 207653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207657 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207659 */     GIR_RootConstrainSelectedInstOperands,
     /* 207660 */     // GIR_Coverage, 12596,
     /* 207660 */     GIR_EraseRootFromParent_Done,
     /* 207661 */   // Label 3856: @207661
     /* 207661 */   GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(207703), // Rule ID 12597 //
     /* 207666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 207674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207684 */     // MIs[0] Op2
     /* 207684 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207687 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 207692 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2093:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)  =>  (UQRSHRNB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op2)
     /* 207692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_H),
     /* 207695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207697 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207699 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207701 */     GIR_RootConstrainSelectedInstOperands,
     /* 207702 */     // GIR_Coverage, 12597,
     /* 207702 */     GIR_EraseRootFromParent_Done,
     /* 207703 */   // Label 3857: @207703
     /* 207703 */   GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(207745), // Rule ID 12598 //
     /* 207708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnb),
     /* 207716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 207722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207726 */     // MIs[0] Op2
     /* 207726 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207729 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 207734 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2093:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)  =>  (UQRSHRNB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op2)
     /* 207734 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNB_ZZI_S),
     /* 207737 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207739 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207743 */     GIR_RootConstrainSelectedInstOperands,
     /* 207744 */     // GIR_Coverage, 12598,
     /* 207744 */     GIR_EraseRootFromParent_Done,
     /* 207745 */   // Label 3858: @207745
     /* 207745 */   GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(207787), // Rule ID 12656 //
     /* 207750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207753 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 207758 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207761 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 207764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207768 */     // MIs[0] Op2
     /* 207768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 207776 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1921:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)  =>  (SSHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)
     /* 207776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_H),
     /* 207779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207781 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207783 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207785 */     GIR_RootConstrainSelectedInstOperands,
     /* 207786 */     // GIR_Coverage, 12656,
     /* 207786 */     GIR_EraseRootFromParent_Done,
     /* 207787 */   // Label 3859: @207787
     /* 207787 */   GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(207829), // Rule ID 12657 //
     /* 207792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 207800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207810 */     // MIs[0] Op2
     /* 207810 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207813 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 207818 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1921:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)  =>  (SSHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)
     /* 207818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_S),
     /* 207821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207823 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207825 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207827 */     GIR_RootConstrainSelectedInstOperands,
     /* 207828 */     // GIR_Coverage, 12657,
     /* 207828 */     GIR_EraseRootFromParent_Done,
     /* 207829 */   // Label 3860: @207829
     /* 207829 */   GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(207871), // Rule ID 12658 //
     /* 207834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sshllt),
     /* 207842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207852 */     // MIs[0] Op2
     /* 207852 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207855 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 207860 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1921:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)  =>  (SSHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)
     /* 207860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLT_ZZI_D),
     /* 207863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207869 */     GIR_RootConstrainSelectedInstOperands,
     /* 207870 */     // GIR_Coverage, 12658,
     /* 207870 */     GIR_EraseRootFromParent_Done,
     /* 207871 */   // Label 3861: @207871
     /* 207871 */   GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(207913), // Rule ID 12659 //
     /* 207876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 207884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 207887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 207890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207894 */     // MIs[0] Op2
     /* 207894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207897 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 207902 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2118:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)  =>  (USHLLB_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)
     /* 207902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_H),
     /* 207905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207909 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207911 */     GIR_RootConstrainSelectedInstOperands,
     /* 207912 */     // GIR_Coverage, 12659,
     /* 207912 */     GIR_EraseRootFromParent_Done,
     /* 207913 */   // Label 3862: @207913
     /* 207913 */   GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(207955), // Rule ID 12660 //
     /* 207918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 207926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 207929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 207932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207936 */     // MIs[0] Op2
     /* 207936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207939 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 207944 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2118:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)  =>  (USHLLB_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)
     /* 207944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_S),
     /* 207947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207951 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207953 */     GIR_RootConstrainSelectedInstOperands,
     /* 207954 */     // GIR_Coverage, 12660,
     /* 207954 */     GIR_EraseRootFromParent_Done,
     /* 207955 */   // Label 3863: @207955
     /* 207955 */   GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(207997), // Rule ID 12661 //
     /* 207960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 207963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllb),
     /* 207968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 207971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 207974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 207978 */     // MIs[0] Op2
     /* 207978 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 207981 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 207986 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2118:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)  =>  (USHLLB_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)
     /* 207986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLB_ZZI_D),
     /* 207989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 207991 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 207993 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 207995 */     GIR_RootConstrainSelectedInstOperands,
     /* 207996 */     // GIR_Coverage, 12661,
     /* 207996 */     GIR_EraseRootFromParent_Done,
     /* 207997 */   // Label 3864: @207997
     /* 207997 */   GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(208039), // Rule ID 12662 //
     /* 208002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 208005 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 208010 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 208013 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 208016 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208020 */     // MIs[0] Op2
     /* 208020 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 208023 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 208028 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2119:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)  =>  (USHLLT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op2)
     /* 208028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_H),
     /* 208031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208035 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208037 */     GIR_RootConstrainSelectedInstOperands,
     /* 208038 */     // GIR_Coverage, 12662,
     /* 208038 */     GIR_EraseRootFromParent_Done,
     /* 208039 */   // Label 3865: @208039
     /* 208039 */   GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(208081), // Rule ID 12663 //
     /* 208044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 208047 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 208052 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 208055 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 208058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208062 */     // MIs[0] Op2
     /* 208062 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 208065 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 208070 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2119:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)  =>  (USHLLT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op2)
     /* 208070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_S),
     /* 208073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208077 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208079 */     GIR_RootConstrainSelectedInstOperands,
     /* 208080 */     // GIR_Coverage, 12663,
     /* 208080 */     GIR_EraseRootFromParent_Done,
     /* 208081 */   // Label 3866: @208081
     /* 208081 */   GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(208123), // Rule ID 12664 //
     /* 208086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 208089 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ushllt),
     /* 208094 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 208097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 208100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 208104 */     // MIs[0] Op2
     /* 208104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 208107 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 208112 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2119:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)  =>  (USHLLT_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op2)
     /* 208112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLT_ZZI_D),
     /* 208115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 208117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 208119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 208121 */     GIR_RootConstrainSelectedInstOperands,
     /* 208122 */     // GIR_Coverage, 12664,
     /* 208122 */     GIR_EraseRootFromParent_Done,
     /* 208123 */   // Label 3867: @208123
     /* 208123 */   GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(208168), // Rule ID 55 //
     /* 208128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 208131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign_generic),
     /* 208136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 208139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 208142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 208149 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 208153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 208157 */     // (intrinsic_wo_chain:{ *:[i64] } 309:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (PACGA:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
     /* 208157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PACGA),
     /* 208160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208166 */     GIR_RootConstrainSelectedInstOperands,
     /* 208167 */     // GIR_Coverage, 55,
     /* 208167 */     GIR_EraseRootFromParent_Done,
     /* 208168 */   // Label 3868: @208168
     /* 208168 */   GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(208213), // Rule ID 117 //
     /* 208173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32b),
     /* 208181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208187 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208194 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208198 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208202 */     // (intrinsic_wo_chain:{ *:[i32] } 527:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Brr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Brr),
     /* 208205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208209 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208211 */     GIR_RootConstrainSelectedInstOperands,
     /* 208212 */     // GIR_Coverage, 117,
     /* 208212 */     GIR_EraseRootFromParent_Done,
     /* 208213 */   // Label 3869: @208213
     /* 208213 */   GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(208258), // Rule ID 118 //
     /* 208218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32h),
     /* 208226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208239 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208243 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208247 */     // (intrinsic_wo_chain:{ *:[i32] } 532:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Hrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Hrr),
     /* 208250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208254 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208256 */     GIR_RootConstrainSelectedInstOperands,
     /* 208257 */     // GIR_Coverage, 118,
     /* 208257 */     GIR_EraseRootFromParent_Done,
     /* 208258 */   // Label 3870: @208258
     /* 208258 */   GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(208303), // Rule ID 119 //
     /* 208263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32w),
     /* 208271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208292 */     // (intrinsic_wo_chain:{ *:[i32] } 533:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32Wrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Wrr),
     /* 208295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208301 */     GIR_RootConstrainSelectedInstOperands,
     /* 208302 */     // GIR_Coverage, 119,
     /* 208302 */     GIR_EraseRootFromParent_Done,
     /* 208303 */   // Label 3871: @208303
     /* 208303 */   GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(208348), // Rule ID 120 //
     /* 208308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32x),
     /* 208316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208329 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208333 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 208337 */     // (intrinsic_wo_chain:{ *:[i32] } 534:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (CRC32Xrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 208337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32Xrr),
     /* 208340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208342 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208346 */     GIR_RootConstrainSelectedInstOperands,
     /* 208347 */     // GIR_Coverage, 120,
     /* 208347 */     GIR_EraseRootFromParent_Done,
     /* 208348 */   // Label 3872: @208348
     /* 208348 */   GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(208393), // Rule ID 121 //
     /* 208353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cb),
     /* 208361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208374 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208378 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208382 */     // (intrinsic_wo_chain:{ *:[i32] } 528:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CBrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CBrr),
     /* 208385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208387 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208389 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208391 */     GIR_RootConstrainSelectedInstOperands,
     /* 208392 */     // GIR_Coverage, 121,
     /* 208392 */     GIR_EraseRootFromParent_Done,
     /* 208393 */   // Label 3873: @208393
     /* 208393 */   GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(208438), // Rule ID 122 //
     /* 208398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32ch),
     /* 208406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208423 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208427 */     // (intrinsic_wo_chain:{ *:[i32] } 529:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CHrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CHrr),
     /* 208430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208436 */     GIR_RootConstrainSelectedInstOperands,
     /* 208437 */     // GIR_Coverage, 122,
     /* 208437 */     GIR_EraseRootFromParent_Done,
     /* 208438 */   // Label 3874: @208438
     /* 208438 */   GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(208483), // Rule ID 123 //
     /* 208443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cw),
     /* 208451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 208460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208464 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208468 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208472 */     // (intrinsic_wo_chain:{ *:[i32] } 530:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (CRC32CWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 208472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CWrr),
     /* 208475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208481 */     GIR_RootConstrainSelectedInstOperands,
     /* 208482 */     // GIR_Coverage, 123,
     /* 208482 */     GIR_EraseRootFromParent_Done,
     /* 208483 */   // Label 3875: @208483
     /* 208483 */   GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(208528), // Rule ID 124 //
     /* 208488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC),
     /* 208491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crc32cx),
     /* 208496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 208499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 208502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 208505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208509 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 208513 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 208517 */     // (intrinsic_wo_chain:{ *:[i32] } 531:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (CRC32CXrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 208517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CRC32CXrr),
     /* 208520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 208522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 208524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 208526 */     GIR_RootConstrainSelectedInstOperands,
     /* 208527 */     // GIR_Coverage, 124,
     /* 208527 */     GIR_EraseRootFromParent_Done,
     /* 208528 */   // Label 3876: @208528
     /* 208528 */   GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(208573), // Rule ID 1072 //
     /* 208533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 208544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 208547 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 208550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208558 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208562 */     // (intrinsic_wo_chain:{ *:[v8i8] } 740:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (SUQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /* 208562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i8),
     /* 208565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208569 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208571 */     GIR_RootConstrainSelectedInstOperands,
     /* 208572 */     // GIR_Coverage, 1072,
     /* 208572 */     GIR_EraseRootFromParent_Done,
     /* 208573 */   // Label 3877: @208573
     /* 208573 */   GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(208618), // Rule ID 1073 //
     /* 208578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 208589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 208592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 208595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208603 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208607 */     // (intrinsic_wo_chain:{ *:[v16i8] } 740:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (SUQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 208607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv16i8),
     /* 208610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208616 */     GIR_RootConstrainSelectedInstOperands,
     /* 208617 */     // GIR_Coverage, 1073,
     /* 208617 */     GIR_EraseRootFromParent_Done,
     /* 208618 */   // Label 3878: @208618
     /* 208618 */   GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(208663), // Rule ID 1074 //
     /* 208623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 208634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 208637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 208640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208652 */     // (intrinsic_wo_chain:{ *:[v4i16] } 740:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (SUQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /* 208652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i16),
     /* 208655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208661 */     GIR_RootConstrainSelectedInstOperands,
     /* 208662 */     // GIR_Coverage, 1074,
     /* 208662 */     GIR_EraseRootFromParent_Done,
     /* 208663 */   // Label 3879: @208663
     /* 208663 */   GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(208708), // Rule ID 1075 //
     /* 208668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 208679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 208682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 208685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208689 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208693 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208697 */     // (intrinsic_wo_chain:{ *:[v8i16] } 740:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)  =>  (SUQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /* 208697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv8i16),
     /* 208700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208706 */     GIR_RootConstrainSelectedInstOperands,
     /* 208707 */     // GIR_Coverage, 1075,
     /* 208707 */     GIR_EraseRootFromParent_Done,
     /* 208708 */   // Label 3880: @208708
     /* 208708 */   GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(208753), // Rule ID 1076 //
     /* 208713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 208724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 208727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 208730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208738 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208742 */     // (intrinsic_wo_chain:{ *:[v2i32] } 740:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (SUQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /* 208742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i32),
     /* 208745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208751 */     GIR_RootConstrainSelectedInstOperands,
     /* 208752 */     // GIR_Coverage, 1076,
     /* 208752 */     GIR_EraseRootFromParent_Done,
     /* 208753 */   // Label 3881: @208753
     /* 208753 */   GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(208798), // Rule ID 1077 //
     /* 208758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 208769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 208772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 208775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208779 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208783 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208787 */     // (intrinsic_wo_chain:{ *:[v4i32] } 740:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SUQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 208787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv4i32),
     /* 208790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208796 */     GIR_RootConstrainSelectedInstOperands,
     /* 208797 */     // GIR_Coverage, 1077,
     /* 208797 */     GIR_EraseRootFromParent_Done,
     /* 208798 */   // Label 3882: @208798
     /* 208798 */   GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(208843), // Rule ID 1078 //
     /* 208803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 208811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 208814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 208817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 208820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208824 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208828 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208832 */     // (intrinsic_wo_chain:{ *:[v2i64] } 740:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)  =>  (SUQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
     /* 208832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv2i64),
     /* 208835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208839 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208841 */     GIR_RootConstrainSelectedInstOperands,
     /* 208842 */     // GIR_Coverage, 1078,
     /* 208842 */     GIR_EraseRootFromParent_Done,
     /* 208843 */   // Label 3883: @208843
     /* 208843 */   GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(208888), // Rule ID 1120 //
     /* 208848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 208856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 208859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 208862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 208865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208869 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208873 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208877 */     // (intrinsic_wo_chain:{ *:[v8i8] } 779:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)  =>  (USQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn)
     /* 208877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i8),
     /* 208880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208882 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208884 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208886 */     GIR_RootConstrainSelectedInstOperands,
     /* 208887 */     // GIR_Coverage, 1120,
     /* 208887 */     GIR_EraseRootFromParent_Done,
     /* 208888 */   // Label 3884: @208888
     /* 208888 */   GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(208933), // Rule ID 1121 //
     /* 208893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 208901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 208904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 208907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 208910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208914 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208918 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 208922 */     // (intrinsic_wo_chain:{ *:[v16i8] } 779:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (USQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 208922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv16i8),
     /* 208925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208929 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208931 */     GIR_RootConstrainSelectedInstOperands,
     /* 208932 */     // GIR_Coverage, 1121,
     /* 208932 */     GIR_EraseRootFromParent_Done,
     /* 208933 */   // Label 3885: @208933
     /* 208933 */   GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(208978), // Rule ID 1122 //
     /* 208938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 208946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 208949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 208952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 208955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208959 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208963 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 208967 */     // (intrinsic_wo_chain:{ *:[v4i16] } 779:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)  =>  (USQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn)
     /* 208967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i16),
     /* 208970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 208972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 208974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 208976 */     GIR_RootConstrainSelectedInstOperands,
     /* 208977 */     // GIR_Coverage, 1122,
     /* 208977 */     GIR_EraseRootFromParent_Done,
     /* 208978 */   // Label 3886: @208978
     /* 208978 */   GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(209023), // Rule ID 1123 //
     /* 208983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 208986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 208991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 208994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 208997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 209000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209004 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209008 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209012 */     // (intrinsic_wo_chain:{ *:[v8i16] } 779:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)  =>  (USQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn)
     /* 209012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv8i16),
     /* 209015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 209017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 209019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 209021 */     GIR_RootConstrainSelectedInstOperands,
     /* 209022 */     // GIR_Coverage, 1123,
     /* 209022 */     GIR_EraseRootFromParent_Done,
     /* 209023 */   // Label 3887: @209023
     /* 209023 */   GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(209068), // Rule ID 1124 //
     /* 209028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 209036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 209039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 209042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 209045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209049 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209053 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209057 */     // (intrinsic_wo_chain:{ *:[v2i32] } 779:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)  =>  (USQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn)
     /* 209057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i32),
     /* 209060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 209062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 209064 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 209066 */     GIR_RootConstrainSelectedInstOperands,
     /* 209067 */     // GIR_Coverage, 1124,
     /* 209067 */     GIR_EraseRootFromParent_Done,
     /* 209068 */   // Label 3888: @209068
     /* 209068 */   GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(209113), // Rule ID 1125 //
     /* 209073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 209081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 209084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 209087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 209090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209098 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209102 */     // (intrinsic_wo_chain:{ *:[v4i32] } 779:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (USQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 209102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv4i32),
     /* 209105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 209107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 209109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 209111 */     GIR_RootConstrainSelectedInstOperands,
     /* 209112 */     // GIR_Coverage, 1125,
     /* 209112 */     GIR_EraseRootFromParent_Done,
     /* 209113 */   // Label 3889: @209113
     /* 209113 */   GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(209158), // Rule ID 1126 //
     /* 209118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 209126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 209129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 209132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 209135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209143 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209147 */     // (intrinsic_wo_chain:{ *:[v2i64] } 779:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)  =>  (USQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn)
     /* 209147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv2i64),
     /* 209150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 209152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 209154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 209156 */     GIR_RootConstrainSelectedInstOperands,
     /* 209157 */     // GIR_Coverage, 1126,
     /* 209157 */     GIR_EraseRootFromParent_Done,
     /* 209158 */   // Label 3890: @209158
     /* 209158 */   GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(209203), // Rule ID 1138 //
     /* 209163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 209174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 209177 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 209180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209184 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209188 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209192 */     // (intrinsic_wo_chain:{ *:[v8i8] } 594:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ADDPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 209192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i8),
     /* 209195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209199 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209201 */     GIR_RootConstrainSelectedInstOperands,
     /* 209202 */     // GIR_Coverage, 1138,
     /* 209202 */     GIR_EraseRootFromParent_Done,
     /* 209203 */   // Label 3891: @209203
     /* 209203 */   GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(209248), // Rule ID 1140 //
     /* 209208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209211 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209216 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 209219 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 209222 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 209225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209233 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209237 */     // (intrinsic_wo_chain:{ *:[v16i8] } 594:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ADDPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 209237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv16i8),
     /* 209240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209244 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209246 */     GIR_RootConstrainSelectedInstOperands,
     /* 209247 */     // GIR_Coverage, 1140,
     /* 209247 */     GIR_EraseRootFromParent_Done,
     /* 209248 */   // Label 3892: @209248
     /* 209248 */   GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(209293), // Rule ID 1142 //
     /* 209253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 209264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 209267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 209270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209274 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209278 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209282 */     // (intrinsic_wo_chain:{ *:[v4i16] } 594:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ADDPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 209282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i16),
     /* 209285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209291 */     GIR_RootConstrainSelectedInstOperands,
     /* 209292 */     // GIR_Coverage, 1142,
     /* 209292 */     GIR_EraseRootFromParent_Done,
     /* 209293 */   // Label 3893: @209293
     /* 209293 */   GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(209338), // Rule ID 1144 //
     /* 209298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 209309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 209312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 209315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209319 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209323 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209327 */     // (intrinsic_wo_chain:{ *:[v8i16] } 594:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 209327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv8i16),
     /* 209330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209334 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209336 */     GIR_RootConstrainSelectedInstOperands,
     /* 209337 */     // GIR_Coverage, 1144,
     /* 209337 */     GIR_EraseRootFromParent_Done,
     /* 209338 */   // Label 3894: @209338
     /* 209338 */   GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(209383), // Rule ID 1146 //
     /* 209343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 209354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 209357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 209360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209364 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209368 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209372 */     // (intrinsic_wo_chain:{ *:[v2i32] } 594:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ADDPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 209372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 209375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209381 */     GIR_RootConstrainSelectedInstOperands,
     /* 209382 */     // GIR_Coverage, 1146,
     /* 209382 */     GIR_EraseRootFromParent_Done,
     /* 209383 */   // Label 3895: @209383
     /* 209383 */   GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(209428), // Rule ID 1148 //
     /* 209388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 209399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 209402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 209405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209413 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209417 */     // (intrinsic_wo_chain:{ *:[v4i32] } 594:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 209417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv4i32),
     /* 209420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209426 */     GIR_RootConstrainSelectedInstOperands,
     /* 209427 */     // GIR_Coverage, 1148,
     /* 209427 */     GIR_EraseRootFromParent_Done,
     /* 209428 */   // Label 3896: @209428
     /* 209428 */   GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(209473), // Rule ID 1150 //
     /* 209433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addp),
     /* 209441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 209444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 209447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 209450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209462 */     // (intrinsic_wo_chain:{ *:[v2i64] } 594:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDPv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 209462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64),
     /* 209465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209467 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209469 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209471 */     GIR_RootConstrainSelectedInstOperands,
     /* 209472 */     // GIR_Coverage, 1150,
     /* 209472 */     GIR_EraseRootFromParent_Done,
     /* 209473 */   // Label 3897: @209473
     /* 209473 */   GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(209518), // Rule ID 1193 //
     /* 209478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 209486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 209489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 209492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 209495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209507 */     // (intrinsic_wo_chain:{ *:[v4f16] } 600:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FABDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 209507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
     /* 209510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209514 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209516 */     GIR_RootConstrainSelectedInstOperands,
     /* 209517 */     // GIR_Coverage, 1193,
     /* 209517 */     GIR_EraseRootFromParent_Done,
     /* 209518 */   // Label 3898: @209518
     /* 209518 */   GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(209563), // Rule ID 1194 //
     /* 209523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 209531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 209534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 209537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 209540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209548 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209552 */     // (intrinsic_wo_chain:{ *:[v8f16] } 600:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FABDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 209552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
     /* 209555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209561 */     GIR_RootConstrainSelectedInstOperands,
     /* 209562 */     // GIR_Coverage, 1194,
     /* 209562 */     GIR_EraseRootFromParent_Done,
     /* 209563 */   // Label 3899: @209563
     /* 209563 */   GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(209608), // Rule ID 1195 //
     /* 209568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 209576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 209579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 209582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 209585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209597 */     // (intrinsic_wo_chain:{ *:[v2f32] } 600:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FABDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 209597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
     /* 209600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209604 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209606 */     GIR_RootConstrainSelectedInstOperands,
     /* 209607 */     // GIR_Coverage, 1195,
     /* 209607 */     GIR_EraseRootFromParent_Done,
     /* 209608 */   // Label 3900: @209608
     /* 209608 */   GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(209653), // Rule ID 1196 //
     /* 209613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 209621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 209624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 209627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 209630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209634 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209638 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209642 */     // (intrinsic_wo_chain:{ *:[v4f32] } 600:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FABDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 209642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
     /* 209645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209651 */     GIR_RootConstrainSelectedInstOperands,
     /* 209652 */     // GIR_Coverage, 1196,
     /* 209652 */     GIR_EraseRootFromParent_Done,
     /* 209653 */   // Label 3901: @209653
     /* 209653 */   GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(209698), // Rule ID 1197 //
     /* 209658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 209666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 209669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 209672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 209675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209679 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209683 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209687 */     // (intrinsic_wo_chain:{ *:[v2f64] } 600:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FABDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 209687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
     /* 209690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209694 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209696 */     GIR_RootConstrainSelectedInstOperands,
     /* 209697 */     // GIR_Coverage, 1197,
     /* 209697 */     GIR_EraseRootFromParent_Done,
     /* 209698 */   // Label 3902: @209698
     /* 209698 */   GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(209743), // Rule ID 1199 //
     /* 209703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 209711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 209714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 209717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 209720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209724 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209728 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209732 */     // (intrinsic_wo_chain:{ *:[v4i16] } 601:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 209732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
     /* 209735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209739 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209741 */     GIR_RootConstrainSelectedInstOperands,
     /* 209742 */     // GIR_Coverage, 1199,
     /* 209742 */     GIR_EraseRootFromParent_Done,
     /* 209743 */   // Label 3903: @209743
     /* 209743 */   GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(209788), // Rule ID 1201 //
     /* 209748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 209756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 209759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 209762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 209765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209773 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209777 */     // (intrinsic_wo_chain:{ *:[v8i16] } 601:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 209777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
     /* 209780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209782 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209784 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209786 */     GIR_RootConstrainSelectedInstOperands,
     /* 209787 */     // GIR_Coverage, 1201,
     /* 209787 */     GIR_EraseRootFromParent_Done,
     /* 209788 */   // Label 3904: @209788
     /* 209788 */   GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(209833), // Rule ID 1203 //
     /* 209793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 209801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 209804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 209807 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 209810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209822 */     // (intrinsic_wo_chain:{ *:[v2i32] } 601:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 209822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
     /* 209825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209831 */     GIR_RootConstrainSelectedInstOperands,
     /* 209832 */     // GIR_Coverage, 1203,
     /* 209832 */     GIR_EraseRootFromParent_Done,
     /* 209833 */   // Label 3905: @209833
     /* 209833 */   GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(209878), // Rule ID 1205 //
     /* 209838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 209846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 209849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 209852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 209855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209863 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209867 */     // (intrinsic_wo_chain:{ *:[v4i32] } 601:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 209867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
     /* 209870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209874 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209876 */     GIR_RootConstrainSelectedInstOperands,
     /* 209877 */     // GIR_Coverage, 1205,
     /* 209877 */     GIR_EraseRootFromParent_Done,
     /* 209878 */   // Label 3906: @209878
     /* 209878 */   GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(209923), // Rule ID 1207 //
     /* 209883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 209886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 209891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 209894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 209897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 209900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209904 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209908 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209912 */     // (intrinsic_wo_chain:{ *:[v2i64] } 601:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 209912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
     /* 209915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209921 */     GIR_RootConstrainSelectedInstOperands,
     /* 209922 */     // GIR_Coverage, 1207,
     /* 209922 */     GIR_EraseRootFromParent_Done,
     /* 209923 */   // Label 3907: @209923
     /* 209923 */   GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(209968), // Rule ID 1209 //
     /* 209928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 209936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 209939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 209942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 209945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209949 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209953 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 209957 */     // (intrinsic_wo_chain:{ *:[v4i16] } 602:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 209957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
     /* 209960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 209962 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 209964 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 209966 */     GIR_RootConstrainSelectedInstOperands,
     /* 209967 */     // GIR_Coverage, 1209,
     /* 209967 */     GIR_EraseRootFromParent_Done,
     /* 209968 */   // Label 3908: @209968
     /* 209968 */   GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(210013), // Rule ID 1211 //
     /* 209973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 209976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 209981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 209984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 209987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 209990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 209998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210002 */     // (intrinsic_wo_chain:{ *:[v8i16] } 602:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 210002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
     /* 210005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210011 */     GIR_RootConstrainSelectedInstOperands,
     /* 210012 */     // GIR_Coverage, 1211,
     /* 210012 */     GIR_EraseRootFromParent_Done,
     /* 210013 */   // Label 3909: @210013
     /* 210013 */   GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(210058), // Rule ID 1213 //
     /* 210018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 210026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 210029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 210032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 210035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210047 */     // (intrinsic_wo_chain:{ *:[v2i32] } 602:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 210047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
     /* 210050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210056 */     GIR_RootConstrainSelectedInstOperands,
     /* 210057 */     // GIR_Coverage, 1213,
     /* 210057 */     GIR_EraseRootFromParent_Done,
     /* 210058 */   // Label 3910: @210058
     /* 210058 */   GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(210103), // Rule ID 1215 //
     /* 210063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 210071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 210074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 210077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 210080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210088 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210092 */     // (intrinsic_wo_chain:{ *:[v4i32] } 602:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 210092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
     /* 210095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210097 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210099 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210101 */     GIR_RootConstrainSelectedInstOperands,
     /* 210102 */     // GIR_Coverage, 1215,
     /* 210102 */     GIR_EraseRootFromParent_Done,
     /* 210103 */   // Label 3911: @210103
     /* 210103 */   GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(210148), // Rule ID 1217 //
     /* 210108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 210116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 210119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 210122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 210125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210133 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210137 */     // (intrinsic_wo_chain:{ *:[v2i64] } 602:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 210137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
     /* 210140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210146 */     GIR_RootConstrainSelectedInstOperands,
     /* 210147 */     // GIR_Coverage, 1217,
     /* 210147 */     GIR_EraseRootFromParent_Done,
     /* 210148 */   // Label 3912: @210148
     /* 210148 */   GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(210193), // Rule ID 1219 //
     /* 210153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 210161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 210164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 210167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 210170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210178 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210182 */     // (intrinsic_wo_chain:{ *:[v4f16] } 603:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 210182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
     /* 210185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210189 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210191 */     GIR_RootConstrainSelectedInstOperands,
     /* 210192 */     // GIR_Coverage, 1219,
     /* 210192 */     GIR_EraseRootFromParent_Done,
     /* 210193 */   // Label 3913: @210193
     /* 210193 */   GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(210238), // Rule ID 1221 //
     /* 210198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 210206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 210209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 210212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 210215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210223 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210227 */     // (intrinsic_wo_chain:{ *:[v8f16] } 603:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 210227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 210230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210234 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210236 */     GIR_RootConstrainSelectedInstOperands,
     /* 210237 */     // GIR_Coverage, 1221,
     /* 210237 */     GIR_EraseRootFromParent_Done,
     /* 210238 */   // Label 3914: @210238
     /* 210238 */   GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(210283), // Rule ID 1223 //
     /* 210243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 210251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 210254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 210257 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 210260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210268 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210272 */     // (intrinsic_wo_chain:{ *:[v2f32] } 603:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 210272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f32),
     /* 210275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210279 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210281 */     GIR_RootConstrainSelectedInstOperands,
     /* 210282 */     // GIR_Coverage, 1223,
     /* 210282 */     GIR_EraseRootFromParent_Done,
     /* 210283 */   // Label 3915: @210283
     /* 210283 */   GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(210328), // Rule ID 1225 //
     /* 210288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 210296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 210299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 210302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 210305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210313 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210317 */     // (intrinsic_wo_chain:{ *:[v4f32] } 603:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 210317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 210320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210326 */     GIR_RootConstrainSelectedInstOperands,
     /* 210327 */     // GIR_Coverage, 1225,
     /* 210327 */     GIR_EraseRootFromParent_Done,
     /* 210328 */   // Label 3916: @210328
     /* 210328 */   GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(210373), // Rule ID 1227 //
     /* 210333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_faddp),
     /* 210341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 210344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 210347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 210350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210358 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210362 */     // (intrinsic_wo_chain:{ *:[v2f64] } 603:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 210362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 210365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210369 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210371 */     GIR_RootConstrainSelectedInstOperands,
     /* 210372 */     // GIR_Coverage, 1227,
     /* 210372 */     GIR_EraseRootFromParent_Done,
     /* 210373 */   // Label 3917: @210373
     /* 210373 */   GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(210418), // Rule ID 1263 //
     /* 210378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 210386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 210389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 210392 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 210395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210403 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210407 */     // (intrinsic_wo_chain:{ *:[v4f16] } 620:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 210407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f16),
     /* 210410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210412 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210414 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210416 */     GIR_RootConstrainSelectedInstOperands,
     /* 210417 */     // GIR_Coverage, 1263,
     /* 210417 */     GIR_EraseRootFromParent_Done,
     /* 210418 */   // Label 3918: @210418
     /* 210418 */   GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(210463), // Rule ID 1264 //
     /* 210423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 210431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 210434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 210437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 210440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210452 */     // (intrinsic_wo_chain:{ *:[v8f16] } 620:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 210452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv8f16),
     /* 210455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210461 */     GIR_RootConstrainSelectedInstOperands,
     /* 210462 */     // GIR_Coverage, 1264,
     /* 210462 */     GIR_EraseRootFromParent_Done,
     /* 210463 */   // Label 3919: @210463
     /* 210463 */   GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(210508), // Rule ID 1265 //
     /* 210468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 210476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 210479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 210482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 210485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210489 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210493 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210497 */     // (intrinsic_wo_chain:{ *:[v2f32] } 620:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 210497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f32),
     /* 210500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210504 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210506 */     GIR_RootConstrainSelectedInstOperands,
     /* 210507 */     // GIR_Coverage, 1265,
     /* 210507 */     GIR_EraseRootFromParent_Done,
     /* 210508 */   // Label 3920: @210508
     /* 210508 */   GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(210553), // Rule ID 1266 //
     /* 210513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 210521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 210524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 210527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 210530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210534 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210538 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210542 */     // (intrinsic_wo_chain:{ *:[v4f32] } 620:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 210542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv4f32),
     /* 210545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210551 */     GIR_RootConstrainSelectedInstOperands,
     /* 210552 */     // GIR_Coverage, 1266,
     /* 210552 */     GIR_EraseRootFromParent_Done,
     /* 210553 */   // Label 3921: @210553
     /* 210553 */   GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(210598), // Rule ID 1267 //
     /* 210558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxnmp),
     /* 210566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 210569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 210572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 210575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210579 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210583 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210587 */     // (intrinsic_wo_chain:{ *:[v2f64] } 620:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 210587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2f64),
     /* 210590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210594 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210596 */     GIR_RootConstrainSelectedInstOperands,
     /* 210597 */     // GIR_Coverage, 1267,
     /* 210597 */     GIR_EraseRootFromParent_Done,
     /* 210598 */   // Label 3922: @210598
     /* 210598 */   GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(210643), // Rule ID 1278 //
     /* 210603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 210611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 210614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 210617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 210620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210628 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210632 */     // (intrinsic_wo_chain:{ *:[v4f16] } 622:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 210632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f16),
     /* 210635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210641 */     GIR_RootConstrainSelectedInstOperands,
     /* 210642 */     // GIR_Coverage, 1278,
     /* 210642 */     GIR_EraseRootFromParent_Done,
     /* 210643 */   // Label 3923: @210643
     /* 210643 */   GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(210688), // Rule ID 1279 //
     /* 210648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 210656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 210659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 210662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 210665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210673 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210677 */     // (intrinsic_wo_chain:{ *:[v8f16] } 622:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 210677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv8f16),
     /* 210680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210686 */     GIR_RootConstrainSelectedInstOperands,
     /* 210687 */     // GIR_Coverage, 1279,
     /* 210687 */     GIR_EraseRootFromParent_Done,
     /* 210688 */   // Label 3924: @210688
     /* 210688 */   GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(210733), // Rule ID 1280 //
     /* 210693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 210701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 210704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 210707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 210710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210718 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210722 */     // (intrinsic_wo_chain:{ *:[v2f32] } 622:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 210722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f32),
     /* 210725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210729 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210731 */     GIR_RootConstrainSelectedInstOperands,
     /* 210732 */     // GIR_Coverage, 1280,
     /* 210732 */     GIR_EraseRootFromParent_Done,
     /* 210733 */   // Label 3925: @210733
     /* 210733 */   GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(210778), // Rule ID 1281 //
     /* 210738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 210746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 210749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 210752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 210755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210759 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210763 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210767 */     // (intrinsic_wo_chain:{ *:[v4f32] } 622:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 210767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv4f32),
     /* 210770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210772 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210774 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210776 */     GIR_RootConstrainSelectedInstOperands,
     /* 210777 */     // GIR_Coverage, 1281,
     /* 210777 */     GIR_EraseRootFromParent_Done,
     /* 210778 */   // Label 3926: @210778
     /* 210778 */   GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(210823), // Rule ID 1282 //
     /* 210783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmaxp),
     /* 210791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 210794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 210797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 210800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210804 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210808 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210812 */     // (intrinsic_wo_chain:{ *:[v2f64] } 622:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 210812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2f64),
     /* 210815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210817 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210819 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210821 */     GIR_RootConstrainSelectedInstOperands,
     /* 210822 */     // GIR_Coverage, 1282,
     /* 210822 */     GIR_EraseRootFromParent_Done,
     /* 210823 */   // Label 3927: @210823
     /* 210823 */   GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(210868), // Rule ID 1293 //
     /* 210828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 210836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 210839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 210842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 210845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210849 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210853 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210857 */     // (intrinsic_wo_chain:{ *:[v4f16] } 626:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 210857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f16),
     /* 210860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210862 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210864 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210866 */     GIR_RootConstrainSelectedInstOperands,
     /* 210867 */     // GIR_Coverage, 1293,
     /* 210867 */     GIR_EraseRootFromParent_Done,
     /* 210868 */   // Label 3928: @210868
     /* 210868 */   GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(210913), // Rule ID 1294 //
     /* 210873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 210876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 210881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 210884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 210887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 210890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210894 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210898 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210902 */     // (intrinsic_wo_chain:{ *:[v8f16] } 626:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 210902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv8f16),
     /* 210905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210909 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210911 */     GIR_RootConstrainSelectedInstOperands,
     /* 210912 */     // GIR_Coverage, 1294,
     /* 210912 */     GIR_EraseRootFromParent_Done,
     /* 210913 */   // Label 3929: @210913
     /* 210913 */   GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(210958), // Rule ID 1295 //
     /* 210918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 210926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 210929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 210932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 210935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210943 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 210947 */     // (intrinsic_wo_chain:{ *:[v2f32] } 626:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 210947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f32),
     /* 210950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 210956 */     GIR_RootConstrainSelectedInstOperands,
     /* 210957 */     // GIR_Coverage, 1295,
     /* 210957 */     GIR_EraseRootFromParent_Done,
     /* 210958 */   // Label 3930: @210958
     /* 210958 */   GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(211003), // Rule ID 1296 //
     /* 210963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 210966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 210971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 210974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 210977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 210980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210988 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 210992 */     // (intrinsic_wo_chain:{ *:[v4f32] } 626:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 210992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv4f32),
     /* 210995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 210997 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 210999 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211001 */     GIR_RootConstrainSelectedInstOperands,
     /* 211002 */     // GIR_Coverage, 1296,
     /* 211002 */     GIR_EraseRootFromParent_Done,
     /* 211003 */   // Label 3931: @211003
     /* 211003 */   GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(211048), // Rule ID 1297 //
     /* 211008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211011 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminnmp),
     /* 211016 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 211019 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 211022 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 211025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211029 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211033 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211037 */     // (intrinsic_wo_chain:{ *:[v2f64] } 626:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 211037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2f64),
     /* 211040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211042 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211044 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211046 */     GIR_RootConstrainSelectedInstOperands,
     /* 211047 */     // GIR_Coverage, 1297,
     /* 211047 */     GIR_EraseRootFromParent_Done,
     /* 211048 */   // Label 3932: @211048
     /* 211048 */   GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(211093), // Rule ID 1308 //
     /* 211053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 211061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 211064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 211067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 211070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211078 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211082 */     // (intrinsic_wo_chain:{ *:[v4f16] } 628:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 211082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f16),
     /* 211085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211091 */     GIR_RootConstrainSelectedInstOperands,
     /* 211092 */     // GIR_Coverage, 1308,
     /* 211092 */     GIR_EraseRootFromParent_Done,
     /* 211093 */   // Label 3933: @211093
     /* 211093 */   GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(211138), // Rule ID 1309 //
     /* 211098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 211106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 211109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 211112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 211115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211123 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211127 */     // (intrinsic_wo_chain:{ *:[v8f16] } 628:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 211127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv8f16),
     /* 211130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211136 */     GIR_RootConstrainSelectedInstOperands,
     /* 211137 */     // GIR_Coverage, 1309,
     /* 211137 */     GIR_EraseRootFromParent_Done,
     /* 211138 */   // Label 3934: @211138
     /* 211138 */   GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(211183), // Rule ID 1310 //
     /* 211143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 211151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 211154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 211157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 211160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211164 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211168 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211172 */     // (intrinsic_wo_chain:{ *:[v2f32] } 628:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 211172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f32),
     /* 211175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211181 */     GIR_RootConstrainSelectedInstOperands,
     /* 211182 */     // GIR_Coverage, 1310,
     /* 211182 */     GIR_EraseRootFromParent_Done,
     /* 211183 */   // Label 3935: @211183
     /* 211183 */   GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(211228), // Rule ID 1311 //
     /* 211188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 211196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 211199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 211202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 211205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211213 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211217 */     // (intrinsic_wo_chain:{ *:[v4f32] } 628:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 211217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv4f32),
     /* 211220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211224 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211226 */     GIR_RootConstrainSelectedInstOperands,
     /* 211227 */     // GIR_Coverage, 1311,
     /* 211227 */     GIR_EraseRootFromParent_Done,
     /* 211228 */   // Label 3936: @211228
     /* 211228 */   GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(211273), // Rule ID 1312 //
     /* 211233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fminp),
     /* 211241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 211244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 211247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 211250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211254 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211258 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211262 */     // (intrinsic_wo_chain:{ *:[v2f64] } 628:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 211262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2f64),
     /* 211265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211271 */     GIR_RootConstrainSelectedInstOperands,
     /* 211272 */     // GIR_Coverage, 1312,
     /* 211272 */     GIR_EraseRootFromParent_Done,
     /* 211273 */   // Label 3937: @211273
     /* 211273 */   GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(211318), // Rule ID 1343 //
     /* 211278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 211286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 211289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 211292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 211295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211307 */     // (intrinsic_wo_chain:{ *:[v4f16] } 635:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 211307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f16),
     /* 211310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211316 */     GIR_RootConstrainSelectedInstOperands,
     /* 211317 */     // GIR_Coverage, 1343,
     /* 211317 */     GIR_EraseRootFromParent_Done,
     /* 211318 */   // Label 3938: @211318
     /* 211318 */   GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(211363), // Rule ID 1344 //
     /* 211323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211326 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 211331 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 211334 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 211337 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 211340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211344 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211348 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211352 */     // (intrinsic_wo_chain:{ *:[v8f16] } 635:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 211352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv8f16),
     /* 211355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211359 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211361 */     GIR_RootConstrainSelectedInstOperands,
     /* 211362 */     // GIR_Coverage, 1344,
     /* 211362 */     GIR_EraseRootFromParent_Done,
     /* 211363 */   // Label 3939: @211363
     /* 211363 */   GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(211408), // Rule ID 1345 //
     /* 211368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211371 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 211376 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 211379 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 211382 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 211385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211389 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211393 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211397 */     // (intrinsic_wo_chain:{ *:[v2f32] } 635:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 211397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f32),
     /* 211400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211402 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211404 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211406 */     GIR_RootConstrainSelectedInstOperands,
     /* 211407 */     // GIR_Coverage, 1345,
     /* 211407 */     GIR_EraseRootFromParent_Done,
     /* 211408 */   // Label 3940: @211408
     /* 211408 */   GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(211453), // Rule ID 1346 //
     /* 211413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 211421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 211424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 211427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 211430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211434 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211438 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211442 */     // (intrinsic_wo_chain:{ *:[v4f32] } 635:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 211442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv4f32),
     /* 211445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211449 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211451 */     GIR_RootConstrainSelectedInstOperands,
     /* 211452 */     // GIR_Coverage, 1346,
     /* 211452 */     GIR_EraseRootFromParent_Done,
     /* 211453 */   // Label 3941: @211453
     /* 211453 */   GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(211498), // Rule ID 1347 //
     /* 211458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 211466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 211469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 211472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 211475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211483 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211487 */     // (intrinsic_wo_chain:{ *:[v2f64] } 635:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 211487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULXv2f64),
     /* 211490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211492 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211494 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211496 */     GIR_RootConstrainSelectedInstOperands,
     /* 211497 */     // GIR_Coverage, 1347,
     /* 211497 */     GIR_EraseRootFromParent_Done,
     /* 211498 */   // Label 3942: @211498
     /* 211498 */   GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(211543), // Rule ID 1358 //
     /* 211503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 211511 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 211514 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 211517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 211520 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211524 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211528 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211532 */     // (intrinsic_wo_chain:{ *:[v4f16] } 658:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FRECPSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 211532 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f16),
     /* 211535 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211539 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211541 */     GIR_RootConstrainSelectedInstOperands,
     /* 211542 */     // GIR_Coverage, 1358,
     /* 211542 */     GIR_EraseRootFromParent_Done,
     /* 211543 */   // Label 3943: @211543
     /* 211543 */   GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(211588), // Rule ID 1359 //
     /* 211548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 211556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 211559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 211562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 211565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211573 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211577 */     // (intrinsic_wo_chain:{ *:[v8f16] } 658:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FRECPSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 211577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv8f16),
     /* 211580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211582 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211584 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211586 */     GIR_RootConstrainSelectedInstOperands,
     /* 211587 */     // GIR_Coverage, 1359,
     /* 211587 */     GIR_EraseRootFromParent_Done,
     /* 211588 */   // Label 3944: @211588
     /* 211588 */   GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(211633), // Rule ID 1360 //
     /* 211593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 211601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 211604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 211607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 211610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211618 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211622 */     // (intrinsic_wo_chain:{ *:[v2f32] } 658:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FRECPSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 211622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f32),
     /* 211625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211627 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211629 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211631 */     GIR_RootConstrainSelectedInstOperands,
     /* 211632 */     // GIR_Coverage, 1360,
     /* 211632 */     GIR_EraseRootFromParent_Done,
     /* 211633 */   // Label 3945: @211633
     /* 211633 */   GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(211678), // Rule ID 1361 //
     /* 211638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 211646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 211649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 211652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 211655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211659 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211663 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211667 */     // (intrinsic_wo_chain:{ *:[v4f32] } 658:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FRECPSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 211667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv4f32),
     /* 211670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211676 */     GIR_RootConstrainSelectedInstOperands,
     /* 211677 */     // GIR_Coverage, 1361,
     /* 211677 */     GIR_EraseRootFromParent_Done,
     /* 211678 */   // Label 3946: @211678
     /* 211678 */   GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(211723), // Rule ID 1362 //
     /* 211683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 211691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 211694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 211697 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 211700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211704 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211708 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211712 */     // (intrinsic_wo_chain:{ *:[v2f64] } 658:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FRECPSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 211712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPSv2f64),
     /* 211715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211721 */     GIR_RootConstrainSelectedInstOperands,
     /* 211722 */     // GIR_Coverage, 1362,
     /* 211722 */     GIR_EraseRootFromParent_Done,
     /* 211723 */   // Label 3947: @211723
     /* 211723 */   GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(211768), // Rule ID 1363 //
     /* 211728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 211736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 211739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 211742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 211745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211749 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211753 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211757 */     // (intrinsic_wo_chain:{ *:[v4f16] } 665:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FRSQRTSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 211757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f16),
     /* 211760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211762 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211764 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211766 */     GIR_RootConstrainSelectedInstOperands,
     /* 211767 */     // GIR_Coverage, 1363,
     /* 211767 */     GIR_EraseRootFromParent_Done,
     /* 211768 */   // Label 3948: @211768
     /* 211768 */   GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(211813), // Rule ID 1364 //
     /* 211773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 211776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 211781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 211784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 211787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 211790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211794 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211798 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211802 */     // (intrinsic_wo_chain:{ *:[v8f16] } 665:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FRSQRTSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 211802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv8f16),
     /* 211805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211809 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211811 */     GIR_RootConstrainSelectedInstOperands,
     /* 211812 */     // GIR_Coverage, 1364,
     /* 211812 */     GIR_EraseRootFromParent_Done,
     /* 211813 */   // Label 3949: @211813
     /* 211813 */   GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(211858), // Rule ID 1365 //
     /* 211818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 211826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 211829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 211832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 211835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211847 */     // (intrinsic_wo_chain:{ *:[v2f32] } 665:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FRSQRTSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 211847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f32),
     /* 211850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211854 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211856 */     GIR_RootConstrainSelectedInstOperands,
     /* 211857 */     // GIR_Coverage, 1365,
     /* 211857 */     GIR_EraseRootFromParent_Done,
     /* 211858 */   // Label 3950: @211858
     /* 211858 */   GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(211903), // Rule ID 1366 //
     /* 211863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 211871 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 211874 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 211877 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 211880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211884 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211888 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211892 */     // (intrinsic_wo_chain:{ *:[v4f32] } 665:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FRSQRTSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 211892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv4f32),
     /* 211895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211899 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211901 */     GIR_RootConstrainSelectedInstOperands,
     /* 211902 */     // GIR_Coverage, 1366,
     /* 211902 */     GIR_EraseRootFromParent_Done,
     /* 211903 */   // Label 3951: @211903
     /* 211903 */   GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(211948), // Rule ID 1367 //
     /* 211908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 211916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 211919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 211922 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 211925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 211937 */     // (intrinsic_wo_chain:{ *:[v2f64] } 665:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FRSQRTSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 211937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTSv2f64),
     /* 211940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211946 */     GIR_RootConstrainSelectedInstOperands,
     /* 211947 */     // GIR_Coverage, 1367,
     /* 211947 */     GIR_EraseRootFromParent_Done,
     /* 211948 */   // Label 3952: @211948
     /* 211948 */   GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(211993), // Rule ID 1384 //
     /* 211953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 211956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
     /* 211961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 211964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 211967 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 211970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211974 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211978 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 211982 */     // (intrinsic_wo_chain:{ *:[v8i8] } 678:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (PMULv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 211982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv8i8),
     /* 211985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 211987 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 211989 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 211991 */     GIR_RootConstrainSelectedInstOperands,
     /* 211992 */     // GIR_Coverage, 1384,
     /* 211992 */     GIR_EraseRootFromParent_Done,
     /* 211993 */   // Label 3953: @211993
     /* 211993 */   GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(212038), // Rule ID 1385 //
     /* 211998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212001 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_pmul),
     /* 212006 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 212009 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 212012 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 212015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212019 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212023 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212027 */     // (intrinsic_wo_chain:{ *:[v16i8] } 678:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (PMULv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 212027 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULv16i8),
     /* 212030 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212032 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212034 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212036 */     GIR_RootConstrainSelectedInstOperands,
     /* 212037 */     // GIR_Coverage, 1385,
     /* 212037 */     GIR_EraseRootFromParent_Done,
     /* 212038 */   // Label 3954: @212038
     /* 212038 */   GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(212083), // Rule ID 1404 //
     /* 212043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 212054 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 212057 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 212060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212064 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212068 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212072 */     // (intrinsic_wo_chain:{ *:[v8i8] } 694:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 212072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i8),
     /* 212075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212079 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212081 */     GIR_RootConstrainSelectedInstOperands,
     /* 212082 */     // GIR_Coverage, 1404,
     /* 212082 */     GIR_EraseRootFromParent_Done,
     /* 212083 */   // Label 3955: @212083
     /* 212083 */   GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(212128), // Rule ID 1405 //
     /* 212088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212091 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212096 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 212099 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 212102 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 212105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212109 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212113 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212117 */     // (intrinsic_wo_chain:{ *:[v16i8] } 694:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 212117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv16i8),
     /* 212120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212126 */     GIR_RootConstrainSelectedInstOperands,
     /* 212127 */     // GIR_Coverage, 1405,
     /* 212127 */     GIR_EraseRootFromParent_Done,
     /* 212128 */   // Label 3956: @212128
     /* 212128 */   GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(212173), // Rule ID 1406 //
     /* 212133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 212144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 212147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 212150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212158 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212162 */     // (intrinsic_wo_chain:{ *:[v4i16] } 694:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 212162 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i16),
     /* 212165 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212167 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212169 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212171 */     GIR_RootConstrainSelectedInstOperands,
     /* 212172 */     // GIR_Coverage, 1406,
     /* 212172 */     GIR_EraseRootFromParent_Done,
     /* 212173 */   // Label 3957: @212173
     /* 212173 */   GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(212218), // Rule ID 1407 //
     /* 212178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 212189 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 212192 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 212195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212199 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212203 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212207 */     // (intrinsic_wo_chain:{ *:[v8i16] } 694:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 212207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv8i16),
     /* 212210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212214 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212216 */     GIR_RootConstrainSelectedInstOperands,
     /* 212217 */     // GIR_Coverage, 1407,
     /* 212217 */     GIR_EraseRootFromParent_Done,
     /* 212218 */   // Label 3958: @212218
     /* 212218 */   GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(212263), // Rule ID 1408 //
     /* 212223 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212226 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212231 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 212234 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 212237 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 212240 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212244 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212248 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212252 */     // (intrinsic_wo_chain:{ *:[v2i32] } 694:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 212252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv2i32),
     /* 212255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212257 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212259 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212261 */     GIR_RootConstrainSelectedInstOperands,
     /* 212262 */     // GIR_Coverage, 1408,
     /* 212262 */     GIR_EraseRootFromParent_Done,
     /* 212263 */   // Label 3959: @212263
     /* 212263 */   GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(212308), // Rule ID 1409 //
     /* 212268 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212271 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_shsub),
     /* 212276 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 212279 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 212282 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 212285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212297 */     // (intrinsic_wo_chain:{ *:[v4i32] } 694:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 212297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBv4i32),
     /* 212300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212306 */     GIR_RootConstrainSelectedInstOperands,
     /* 212307 */     // GIR_Coverage, 1409,
     /* 212307 */     GIR_EraseRootFromParent_Done,
     /* 212308 */   // Label 3960: @212308
     /* 212308 */   GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(212353), // Rule ID 1410 //
     /* 212313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 212324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 212327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 212330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212334 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212338 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212342 */     // (intrinsic_wo_chain:{ *:[v8i8] } 696:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 212342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i8),
     /* 212345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212349 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212351 */     GIR_RootConstrainSelectedInstOperands,
     /* 212352 */     // GIR_Coverage, 1410,
     /* 212352 */     GIR_EraseRootFromParent_Done,
     /* 212353 */   // Label 3961: @212353
     /* 212353 */   GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(212398), // Rule ID 1411 //
     /* 212358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 212369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 212372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 212375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212383 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212387 */     // (intrinsic_wo_chain:{ *:[v16i8] } 696:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 212387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv16i8),
     /* 212390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212394 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212396 */     GIR_RootConstrainSelectedInstOperands,
     /* 212397 */     // GIR_Coverage, 1411,
     /* 212397 */     GIR_EraseRootFromParent_Done,
     /* 212398 */   // Label 3962: @212398
     /* 212398 */   GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(212443), // Rule ID 1412 //
     /* 212403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 212414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 212417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 212420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212428 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212432 */     // (intrinsic_wo_chain:{ *:[v4i16] } 696:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 212432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i16),
     /* 212435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212441 */     GIR_RootConstrainSelectedInstOperands,
     /* 212442 */     // GIR_Coverage, 1412,
     /* 212442 */     GIR_EraseRootFromParent_Done,
     /* 212443 */   // Label 3963: @212443
     /* 212443 */   GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(212488), // Rule ID 1413 //
     /* 212448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 212459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 212462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 212465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212469 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212473 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212477 */     // (intrinsic_wo_chain:{ *:[v8i16] } 696:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 212477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv8i16),
     /* 212480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212482 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212486 */     GIR_RootConstrainSelectedInstOperands,
     /* 212487 */     // GIR_Coverage, 1413,
     /* 212487 */     GIR_EraseRootFromParent_Done,
     /* 212488 */   // Label 3964: @212488
     /* 212488 */   GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(212533), // Rule ID 1414 //
     /* 212493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 212504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 212507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 212510 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212514 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212518 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212522 */     // (intrinsic_wo_chain:{ *:[v2i32] } 696:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 212522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 212525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212527 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212529 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212531 */     GIR_RootConstrainSelectedInstOperands,
     /* 212532 */     // GIR_Coverage, 1414,
     /* 212532 */     GIR_EraseRootFromParent_Done,
     /* 212533 */   // Label 3965: @212533
     /* 212533 */   GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(212578), // Rule ID 1415 //
     /* 212538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxp),
     /* 212546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 212549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 212552 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 212555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212559 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212563 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212567 */     // (intrinsic_wo_chain:{ *:[v4i32] } 696:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 212567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv4i32),
     /* 212570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212572 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212574 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212576 */     GIR_RootConstrainSelectedInstOperands,
     /* 212577 */     // GIR_Coverage, 1415,
     /* 212577 */     GIR_EraseRootFromParent_Done,
     /* 212578 */   // Label 3966: @212578
     /* 212578 */   GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(212623), // Rule ID 1422 //
     /* 212583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212586 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212591 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 212594 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 212597 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 212600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212608 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212612 */     // (intrinsic_wo_chain:{ *:[v8i8] } 699:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 212612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i8),
     /* 212615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212619 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212621 */     GIR_RootConstrainSelectedInstOperands,
     /* 212622 */     // GIR_Coverage, 1422,
     /* 212622 */     GIR_EraseRootFromParent_Done,
     /* 212623 */   // Label 3967: @212623
     /* 212623 */   GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(212668), // Rule ID 1423 //
     /* 212628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212631 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212636 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 212639 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 212642 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 212645 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212649 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212653 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212657 */     // (intrinsic_wo_chain:{ *:[v16i8] } 699:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 212657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv16i8),
     /* 212660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212666 */     GIR_RootConstrainSelectedInstOperands,
     /* 212667 */     // GIR_Coverage, 1423,
     /* 212667 */     GIR_EraseRootFromParent_Done,
     /* 212668 */   // Label 3968: @212668
     /* 212668 */   GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(212713), // Rule ID 1424 //
     /* 212673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 212684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 212687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 212690 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212698 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212702 */     // (intrinsic_wo_chain:{ *:[v4i16] } 699:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 212702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i16),
     /* 212705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212709 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212711 */     GIR_RootConstrainSelectedInstOperands,
     /* 212712 */     // GIR_Coverage, 1424,
     /* 212712 */     GIR_EraseRootFromParent_Done,
     /* 212713 */   // Label 3969: @212713
     /* 212713 */   GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(212758), // Rule ID 1425 //
     /* 212718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 212729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 212732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 212735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212739 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212743 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212747 */     // (intrinsic_wo_chain:{ *:[v8i16] } 699:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 212747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv8i16),
     /* 212750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212754 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212756 */     GIR_RootConstrainSelectedInstOperands,
     /* 212757 */     // GIR_Coverage, 1425,
     /* 212757 */     GIR_EraseRootFromParent_Done,
     /* 212758 */   // Label 3970: @212758
     /* 212758 */   GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(212803), // Rule ID 1426 //
     /* 212763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 212774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 212777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 212780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212788 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212792 */     // (intrinsic_wo_chain:{ *:[v2i32] } 699:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 212792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 212795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212799 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212801 */     GIR_RootConstrainSelectedInstOperands,
     /* 212802 */     // GIR_Coverage, 1426,
     /* 212802 */     GIR_EraseRootFromParent_Done,
     /* 212803 */   // Label 3971: @212803
     /* 212803 */   GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(212848), // Rule ID 1427 //
     /* 212808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminp),
     /* 212816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 212819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 212822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 212825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212829 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212833 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212837 */     // (intrinsic_wo_chain:{ *:[v4i32] } 699:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 212837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINPv4i32),
     /* 212840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212844 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212846 */     GIR_RootConstrainSelectedInstOperands,
     /* 212847 */     // GIR_Coverage, 1427,
     /* 212847 */     GIR_EraseRootFromParent_Done,
     /* 212848 */   // Label 3972: @212848
     /* 212848 */   GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(212893), // Rule ID 1441 //
     /* 212853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 212861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 212864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 212867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 212870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212874 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212878 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212882 */     // (intrinsic_wo_chain:{ *:[v4i16] } 705:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 212882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i16),
     /* 212885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212889 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212891 */     GIR_RootConstrainSelectedInstOperands,
     /* 212892 */     // GIR_Coverage, 1441,
     /* 212892 */     GIR_EraseRootFromParent_Done,
     /* 212893 */   // Label 3973: @212893
     /* 212893 */   GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(212938), // Rule ID 1442 //
     /* 212898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 212906 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 212909 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 212912 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 212915 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212919 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212923 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 212927 */     // (intrinsic_wo_chain:{ *:[v8i16] } 705:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 212927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv8i16),
     /* 212930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212932 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212934 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212936 */     GIR_RootConstrainSelectedInstOperands,
     /* 212937 */     // GIR_Coverage, 1442,
     /* 212937 */     GIR_EraseRootFromParent_Done,
     /* 212938 */   // Label 3974: @212938
     /* 212938 */   GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(212983), // Rule ID 1443 //
     /* 212943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 212951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 212954 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 212957 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 212960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212968 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 212972 */     // (intrinsic_wo_chain:{ *:[v2i32] } 705:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 212972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv2i32),
     /* 212975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 212977 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 212979 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 212981 */     GIR_RootConstrainSelectedInstOperands,
     /* 212982 */     // GIR_Coverage, 1443,
     /* 212982 */     GIR_EraseRootFromParent_Done,
     /* 212983 */   // Label 3975: @212983
     /* 212983 */   GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(213028), // Rule ID 1444 //
     /* 212988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 212991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 212996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 212999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 213002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 213005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213009 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213013 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213017 */     // (intrinsic_wo_chain:{ *:[v4i32] } 705:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 213017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv4i32),
     /* 213020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213024 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213026 */     GIR_RootConstrainSelectedInstOperands,
     /* 213027 */     // GIR_Coverage, 1444,
     /* 213027 */     GIR_EraseRootFromParent_Done,
     /* 213028 */   // Label 3976: @213028
     /* 213028 */   GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(213073), // Rule ID 1445 //
     /* 213033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 213041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 213044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 213047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 213050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213054 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213058 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213062 */     // (intrinsic_wo_chain:{ *:[v4i16] } 713:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMULHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 213062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i16),
     /* 213065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213071 */     GIR_RootConstrainSelectedInstOperands,
     /* 213072 */     // GIR_Coverage, 1445,
     /* 213072 */     GIR_EraseRootFromParent_Done,
     /* 213073 */   // Label 3977: @213073
     /* 213073 */   GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(213118), // Rule ID 1446 //
     /* 213078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 213086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 213089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 213092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 213095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213099 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213103 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213107 */     // (intrinsic_wo_chain:{ *:[v8i16] } 713:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMULHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 213107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv8i16),
     /* 213110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213112 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213114 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213116 */     GIR_RootConstrainSelectedInstOperands,
     /* 213117 */     // GIR_Coverage, 1446,
     /* 213117 */     GIR_EraseRootFromParent_Done,
     /* 213118 */   // Label 3978: @213118
     /* 213118 */   GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(213163), // Rule ID 1447 //
     /* 213123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 213131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 213134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 213137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 213140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213148 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213152 */     // (intrinsic_wo_chain:{ *:[v2i32] } 713:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMULHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 213152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv2i32),
     /* 213155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213157 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213159 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213161 */     GIR_RootConstrainSelectedInstOperands,
     /* 213162 */     // GIR_Coverage, 1447,
     /* 213162 */     GIR_EraseRootFromParent_Done,
     /* 213163 */   // Label 3979: @213163
     /* 213163 */   GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(213208), // Rule ID 1448 //
     /* 213168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 213176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 213179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 213182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 213185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213189 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213193 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213197 */     // (intrinsic_wo_chain:{ *:[v4i32] } 713:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMULHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 213197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv4i32),
     /* 213200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213202 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213204 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213206 */     GIR_RootConstrainSelectedInstOperands,
     /* 213207 */     // GIR_Coverage, 1448,
     /* 213207 */     GIR_EraseRootFromParent_Done,
     /* 213208 */   // Label 3980: @213208
     /* 213208 */   GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(213253), // Rule ID 1449 //
     /* 213213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213216 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213221 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 213224 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 213227 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 213230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213234 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213238 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213242 */     // (intrinsic_wo_chain:{ *:[v8i8] } 716:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 213242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i8),
     /* 213245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213247 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213249 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213251 */     GIR_RootConstrainSelectedInstOperands,
     /* 213252 */     // GIR_Coverage, 1449,
     /* 213252 */     GIR_EraseRootFromParent_Done,
     /* 213253 */   // Label 3981: @213253
     /* 213253 */   GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(213298), // Rule ID 1450 //
     /* 213258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 213269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 213272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 213275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213279 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213283 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213287 */     // (intrinsic_wo_chain:{ *:[v16i8] } 716:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 213287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv16i8),
     /* 213290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213296 */     GIR_RootConstrainSelectedInstOperands,
     /* 213297 */     // GIR_Coverage, 1450,
     /* 213297 */     GIR_EraseRootFromParent_Done,
     /* 213298 */   // Label 3982: @213298
     /* 213298 */   GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(213343), // Rule ID 1451 //
     /* 213303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 213314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 213317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 213320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213328 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213332 */     // (intrinsic_wo_chain:{ *:[v4i16] } 716:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 213332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i16),
     /* 213335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213337 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213339 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213341 */     GIR_RootConstrainSelectedInstOperands,
     /* 213342 */     // GIR_Coverage, 1451,
     /* 213342 */     GIR_EraseRootFromParent_Done,
     /* 213343 */   // Label 3983: @213343
     /* 213343 */   GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(213388), // Rule ID 1452 //
     /* 213348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 213359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 213362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 213365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213377 */     // (intrinsic_wo_chain:{ *:[v8i16] } 716:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 213377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv8i16),
     /* 213380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213386 */     GIR_RootConstrainSelectedInstOperands,
     /* 213387 */     // GIR_Coverage, 1452,
     /* 213387 */     GIR_EraseRootFromParent_Done,
     /* 213388 */   // Label 3984: @213388
     /* 213388 */   GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(213433), // Rule ID 1453 //
     /* 213393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 213404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 213407 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 213410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213418 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213422 */     // (intrinsic_wo_chain:{ *:[v2i32] } 716:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 213422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i32),
     /* 213425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213427 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213429 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213431 */     GIR_RootConstrainSelectedInstOperands,
     /* 213432 */     // GIR_Coverage, 1453,
     /* 213432 */     GIR_EraseRootFromParent_Done,
     /* 213433 */   // Label 3985: @213433
     /* 213433 */   GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(213478), // Rule ID 1454 //
     /* 213438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 213449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 213452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 213455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213463 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213467 */     // (intrinsic_wo_chain:{ *:[v4i32] } 716:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 213467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv4i32),
     /* 213470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213474 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213476 */     GIR_RootConstrainSelectedInstOperands,
     /* 213477 */     // GIR_Coverage, 1454,
     /* 213477 */     GIR_EraseRootFromParent_Done,
     /* 213478 */   // Label 3986: @213478
     /* 213478 */   GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(213523), // Rule ID 1455 //
     /* 213483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 213491 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 213494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 213497 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 213500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213508 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213512 */     // (intrinsic_wo_chain:{ *:[v2i64] } 716:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 213512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv2i64),
     /* 213515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213519 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213521 */     GIR_RootConstrainSelectedInstOperands,
     /* 213522 */     // GIR_Coverage, 1455,
     /* 213522 */     GIR_EraseRootFromParent_Done,
     /* 213523 */   // Label 3987: @213523
     /* 213523 */   GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(213568), // Rule ID 1456 //
     /* 213528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 213539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 213542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 213545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213553 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213557 */     // (intrinsic_wo_chain:{ *:[v8i8] } 719:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 213557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i8),
     /* 213560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213562 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213564 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213566 */     GIR_RootConstrainSelectedInstOperands,
     /* 213567 */     // GIR_Coverage, 1456,
     /* 213567 */     GIR_EraseRootFromParent_Done,
     /* 213568 */   // Label 3988: @213568
     /* 213568 */   GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(213613), // Rule ID 1457 //
     /* 213573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 213584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 213587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 213590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213594 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213598 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213602 */     // (intrinsic_wo_chain:{ *:[v16i8] } 719:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 213602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv16i8),
     /* 213605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213607 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213609 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213611 */     GIR_RootConstrainSelectedInstOperands,
     /* 213612 */     // GIR_Coverage, 1457,
     /* 213612 */     GIR_EraseRootFromParent_Done,
     /* 213613 */   // Label 3989: @213613
     /* 213613 */   GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(213658), // Rule ID 1458 //
     /* 213618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 213629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 213632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 213635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213639 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213643 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213647 */     // (intrinsic_wo_chain:{ *:[v4i16] } 719:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 213647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i16),
     /* 213650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213656 */     GIR_RootConstrainSelectedInstOperands,
     /* 213657 */     // GIR_Coverage, 1458,
     /* 213657 */     GIR_EraseRootFromParent_Done,
     /* 213658 */   // Label 3990: @213658
     /* 213658 */   GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(213703), // Rule ID 1459 //
     /* 213663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 213674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 213677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 213680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213688 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213692 */     // (intrinsic_wo_chain:{ *:[v8i16] } 719:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 213692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv8i16),
     /* 213695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213697 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213699 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213701 */     GIR_RootConstrainSelectedInstOperands,
     /* 213702 */     // GIR_Coverage, 1459,
     /* 213702 */     GIR_EraseRootFromParent_Done,
     /* 213703 */   // Label 3991: @213703
     /* 213703 */   GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(213748), // Rule ID 1460 //
     /* 213708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 213719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 213722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 213725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213729 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213733 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213737 */     // (intrinsic_wo_chain:{ *:[v2i32] } 719:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 213737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i32),
     /* 213740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213746 */     GIR_RootConstrainSelectedInstOperands,
     /* 213747 */     // GIR_Coverage, 1460,
     /* 213747 */     GIR_EraseRootFromParent_Done,
     /* 213748 */   // Label 3992: @213748
     /* 213748 */   GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(213793), // Rule ID 1461 //
     /* 213753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213756 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213761 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 213764 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 213767 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 213770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213774 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213778 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213782 */     // (intrinsic_wo_chain:{ *:[v4i32] } 719:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 213782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv4i32),
     /* 213785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213789 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213791 */     GIR_RootConstrainSelectedInstOperands,
     /* 213792 */     // GIR_Coverage, 1461,
     /* 213792 */     GIR_EraseRootFromParent_Done,
     /* 213793 */   // Label 3993: @213793
     /* 213793 */   GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(213838), // Rule ID 1462 //
     /* 213798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 213806 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 213809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 213812 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 213815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213823 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213827 */     // (intrinsic_wo_chain:{ *:[v2i64] } 719:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 213827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv2i64),
     /* 213830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213832 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213834 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213836 */     GIR_RootConstrainSelectedInstOperands,
     /* 213837 */     // GIR_Coverage, 1462,
     /* 213837 */     GIR_EraseRootFromParent_Done,
     /* 213838 */   // Label 3994: @213838
     /* 213838 */   GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(213883), // Rule ID 1476 //
     /* 213843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 213851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 213854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 213857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 213860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213868 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213872 */     // (intrinsic_wo_chain:{ *:[v8i8] } 727:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 213872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i8),
     /* 213875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213877 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213879 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213881 */     GIR_RootConstrainSelectedInstOperands,
     /* 213882 */     // GIR_Coverage, 1476,
     /* 213882 */     GIR_EraseRootFromParent_Done,
     /* 213883 */   // Label 3995: @213883
     /* 213883 */   GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(213928), // Rule ID 1477 //
     /* 213888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 213896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 213899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 213902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 213905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213909 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213913 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213917 */     // (intrinsic_wo_chain:{ *:[v16i8] } 727:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 213917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv16i8),
     /* 213920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213924 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213926 */     GIR_RootConstrainSelectedInstOperands,
     /* 213927 */     // GIR_Coverage, 1477,
     /* 213927 */     GIR_EraseRootFromParent_Done,
     /* 213928 */   // Label 3996: @213928
     /* 213928 */   GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(213973), // Rule ID 1478 //
     /* 213933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 213941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 213944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 213947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 213950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213954 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213958 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 213962 */     // (intrinsic_wo_chain:{ *:[v4i16] } 727:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 213962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i16),
     /* 213965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 213967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 213969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 213971 */     GIR_RootConstrainSelectedInstOperands,
     /* 213972 */     // GIR_Coverage, 1478,
     /* 213972 */     GIR_EraseRootFromParent_Done,
     /* 213973 */   // Label 3997: @213973
     /* 213973 */   GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(214018), // Rule ID 1479 //
     /* 213978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 213981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 213986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 213989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 213992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 213995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 213999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214003 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214007 */     // (intrinsic_wo_chain:{ *:[v8i16] } 727:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 214007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv8i16),
     /* 214010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214012 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214014 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214016 */     GIR_RootConstrainSelectedInstOperands,
     /* 214017 */     // GIR_Coverage, 1479,
     /* 214017 */     GIR_EraseRootFromParent_Done,
     /* 214018 */   // Label 3998: @214018
     /* 214018 */   GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(214063), // Rule ID 1480 //
     /* 214023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 214031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 214034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 214037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 214040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214048 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214052 */     // (intrinsic_wo_chain:{ *:[v2i32] } 727:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 214052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i32),
     /* 214055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214061 */     GIR_RootConstrainSelectedInstOperands,
     /* 214062 */     // GIR_Coverage, 1480,
     /* 214062 */     GIR_EraseRootFromParent_Done,
     /* 214063 */   // Label 3999: @214063
     /* 214063 */   GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(214108), // Rule ID 1481 //
     /* 214068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 214076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 214079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 214082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 214085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214089 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214093 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214097 */     // (intrinsic_wo_chain:{ *:[v4i32] } 727:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 214097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv4i32),
     /* 214100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214106 */     GIR_RootConstrainSelectedInstOperands,
     /* 214107 */     // GIR_Coverage, 1481,
     /* 214107 */     GIR_EraseRootFromParent_Done,
     /* 214108 */   // Label 4000: @214108
     /* 214108 */   GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(214153), // Rule ID 1482 //
     /* 214113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 214121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 214124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 214127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 214130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214134 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214138 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214142 */     // (intrinsic_wo_chain:{ *:[v2i64] } 727:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 214142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv2i64),
     /* 214145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214149 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214151 */     GIR_RootConstrainSelectedInstOperands,
     /* 214152 */     // GIR_Coverage, 1482,
     /* 214152 */     GIR_EraseRootFromParent_Done,
     /* 214153 */   // Label 4001: @214153
     /* 214153 */   GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(214198), // Rule ID 1483 //
     /* 214158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 214169 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 214172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 214175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214179 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214183 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214187 */     // (intrinsic_wo_chain:{ *:[v8i8] } 728:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 214187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i8),
     /* 214190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214194 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214196 */     GIR_RootConstrainSelectedInstOperands,
     /* 214197 */     // GIR_Coverage, 1483,
     /* 214197 */     GIR_EraseRootFromParent_Done,
     /* 214198 */   // Label 4002: @214198
     /* 214198 */   GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(214243), // Rule ID 1484 //
     /* 214203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 214214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 214217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 214220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214228 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214232 */     // (intrinsic_wo_chain:{ *:[v16i8] } 728:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 214232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv16i8),
     /* 214235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214241 */     GIR_RootConstrainSelectedInstOperands,
     /* 214242 */     // GIR_Coverage, 1484,
     /* 214242 */     GIR_EraseRootFromParent_Done,
     /* 214243 */   // Label 4003: @214243
     /* 214243 */   GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(214288), // Rule ID 1485 //
     /* 214248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 214259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 214262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 214265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214273 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214277 */     // (intrinsic_wo_chain:{ *:[v4i16] } 728:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 214277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i16),
     /* 214280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214282 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214284 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214286 */     GIR_RootConstrainSelectedInstOperands,
     /* 214287 */     // GIR_Coverage, 1485,
     /* 214287 */     GIR_EraseRootFromParent_Done,
     /* 214288 */   // Label 4004: @214288
     /* 214288 */   GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(214333), // Rule ID 1486 //
     /* 214293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 214304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 214307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 214310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214318 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214322 */     // (intrinsic_wo_chain:{ *:[v8i16] } 728:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 214322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv8i16),
     /* 214325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214329 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214331 */     GIR_RootConstrainSelectedInstOperands,
     /* 214332 */     // GIR_Coverage, 1486,
     /* 214332 */     GIR_EraseRootFromParent_Done,
     /* 214333 */   // Label 4005: @214333
     /* 214333 */   GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(214378), // Rule ID 1487 //
     /* 214338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 214349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 214352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 214355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214359 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214363 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214367 */     // (intrinsic_wo_chain:{ *:[v2i32] } 728:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 214367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i32),
     /* 214370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214372 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214374 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214376 */     GIR_RootConstrainSelectedInstOperands,
     /* 214377 */     // GIR_Coverage, 1487,
     /* 214377 */     GIR_EraseRootFromParent_Done,
     /* 214378 */   // Label 4006: @214378
     /* 214378 */   GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(214423), // Rule ID 1488 //
     /* 214383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 214394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 214397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 214400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214404 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214408 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214412 */     // (intrinsic_wo_chain:{ *:[v4i32] } 728:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 214412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv4i32),
     /* 214415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214421 */     GIR_RootConstrainSelectedInstOperands,
     /* 214422 */     // GIR_Coverage, 1488,
     /* 214422 */     GIR_EraseRootFromParent_Done,
     /* 214423 */   // Label 4007: @214423
     /* 214423 */   GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(214468), // Rule ID 1489 //
     /* 214428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 214436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 214439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 214442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 214445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214453 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214457 */     // (intrinsic_wo_chain:{ *:[v2i64] } 728:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 214457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv2i64),
     /* 214460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214462 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214464 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214466 */     GIR_RootConstrainSelectedInstOperands,
     /* 214467 */     // GIR_Coverage, 1489,
     /* 214467 */     GIR_EraseRootFromParent_Done,
     /* 214468 */   // Label 4008: @214468
     /* 214468 */   GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(214513), // Rule ID 1515 //
     /* 214473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 214484 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 214487 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 214490 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214494 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214498 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214502 */     // (intrinsic_wo_chain:{ *:[v8i8] } 755:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UHSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 214502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i8),
     /* 214505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214509 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214511 */     GIR_RootConstrainSelectedInstOperands,
     /* 214512 */     // GIR_Coverage, 1515,
     /* 214512 */     GIR_EraseRootFromParent_Done,
     /* 214513 */   // Label 4009: @214513
     /* 214513 */   GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(214558), // Rule ID 1516 //
     /* 214518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 214529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 214532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 214535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214543 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214547 */     // (intrinsic_wo_chain:{ *:[v16i8] } 755:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UHSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 214547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv16i8),
     /* 214550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214554 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214556 */     GIR_RootConstrainSelectedInstOperands,
     /* 214557 */     // GIR_Coverage, 1516,
     /* 214557 */     GIR_EraseRootFromParent_Done,
     /* 214558 */   // Label 4010: @214558
     /* 214558 */   GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(214603), // Rule ID 1517 //
     /* 214563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 214574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 214577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 214580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214588 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214592 */     // (intrinsic_wo_chain:{ *:[v4i16] } 755:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UHSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 214592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i16),
     /* 214595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214601 */     GIR_RootConstrainSelectedInstOperands,
     /* 214602 */     // GIR_Coverage, 1517,
     /* 214602 */     GIR_EraseRootFromParent_Done,
     /* 214603 */   // Label 4011: @214603
     /* 214603 */   GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(214648), // Rule ID 1518 //
     /* 214608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 214619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 214622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 214625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214629 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214633 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214637 */     // (intrinsic_wo_chain:{ *:[v8i16] } 755:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UHSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 214637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv8i16),
     /* 214640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214642 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214644 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214646 */     GIR_RootConstrainSelectedInstOperands,
     /* 214647 */     // GIR_Coverage, 1518,
     /* 214647 */     GIR_EraseRootFromParent_Done,
     /* 214648 */   // Label 4012: @214648
     /* 214648 */   GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(214693), // Rule ID 1519 //
     /* 214653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 214664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 214667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 214670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214674 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214678 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214682 */     // (intrinsic_wo_chain:{ *:[v2i32] } 755:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UHSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 214682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv2i32),
     /* 214685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214689 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214691 */     GIR_RootConstrainSelectedInstOperands,
     /* 214692 */     // GIR_Coverage, 1519,
     /* 214692 */     GIR_EraseRootFromParent_Done,
     /* 214693 */   // Label 4013: @214693
     /* 214693 */   GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(214738), // Rule ID 1520 //
     /* 214698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uhsub),
     /* 214706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 214709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 214712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 214715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214719 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214723 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214727 */     // (intrinsic_wo_chain:{ *:[v4i32] } 755:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UHSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 214727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBv4i32),
     /* 214730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214736 */     GIR_RootConstrainSelectedInstOperands,
     /* 214737 */     // GIR_Coverage, 1520,
     /* 214737 */     GIR_EraseRootFromParent_Done,
     /* 214738 */   // Label 4014: @214738
     /* 214738 */   GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(214783), // Rule ID 1521 //
     /* 214743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 214754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 214757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 214760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214768 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214772 */     // (intrinsic_wo_chain:{ *:[v8i8] } 757:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMAXPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 214772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i8),
     /* 214775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214777 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214779 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214781 */     GIR_RootConstrainSelectedInstOperands,
     /* 214782 */     // GIR_Coverage, 1521,
     /* 214782 */     GIR_EraseRootFromParent_Done,
     /* 214783 */   // Label 4015: @214783
     /* 214783 */   GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(214828), // Rule ID 1522 //
     /* 214788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 214799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 214802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 214805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214817 */     // (intrinsic_wo_chain:{ *:[v16i8] } 757:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMAXPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 214817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv16i8),
     /* 214820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214826 */     GIR_RootConstrainSelectedInstOperands,
     /* 214827 */     // GIR_Coverage, 1522,
     /* 214827 */     GIR_EraseRootFromParent_Done,
     /* 214828 */   // Label 4016: @214828
     /* 214828 */   GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(214873), // Rule ID 1523 //
     /* 214833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 214844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 214847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 214850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214854 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214858 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214862 */     // (intrinsic_wo_chain:{ *:[v4i16] } 757:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMAXPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 214862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i16),
     /* 214865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214871 */     GIR_RootConstrainSelectedInstOperands,
     /* 214872 */     // GIR_Coverage, 1523,
     /* 214872 */     GIR_EraseRootFromParent_Done,
     /* 214873 */   // Label 4017: @214873
     /* 214873 */   GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(214918), // Rule ID 1524 //
     /* 214878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 214889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 214892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 214895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214903 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214907 */     // (intrinsic_wo_chain:{ *:[v8i16] } 757:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMAXPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 214907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv8i16),
     /* 214910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214916 */     GIR_RootConstrainSelectedInstOperands,
     /* 214917 */     // GIR_Coverage, 1524,
     /* 214917 */     GIR_EraseRootFromParent_Done,
     /* 214918 */   // Label 4018: @214918
     /* 214918 */   GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(214963), // Rule ID 1525 //
     /* 214923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 214934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 214937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 214940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214948 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 214952 */     // (intrinsic_wo_chain:{ *:[v2i32] } 757:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMAXPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 214952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 214955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 214957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 214959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 214961 */     GIR_RootConstrainSelectedInstOperands,
     /* 214962 */     // GIR_Coverage, 1525,
     /* 214962 */     GIR_EraseRootFromParent_Done,
     /* 214963 */   // Label 4019: @214963
     /* 214963 */   GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(215008), // Rule ID 1526 //
     /* 214968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 214971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxp),
     /* 214976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 214979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 214982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 214985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214989 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214993 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 214997 */     // (intrinsic_wo_chain:{ *:[v4i32] } 757:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMAXPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 214997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv4i32),
     /* 215000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215004 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215006 */     GIR_RootConstrainSelectedInstOperands,
     /* 215007 */     // GIR_Coverage, 1526,
     /* 215007 */     GIR_EraseRootFromParent_Done,
     /* 215008 */   // Label 4020: @215008
     /* 215008 */   GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(215053), // Rule ID 1533 //
     /* 215013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 215024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 215027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 215030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215034 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215038 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215042 */     // (intrinsic_wo_chain:{ *:[v8i8] } 760:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMINPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 215042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i8),
     /* 215045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215047 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215049 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215051 */     GIR_RootConstrainSelectedInstOperands,
     /* 215052 */     // GIR_Coverage, 1533,
     /* 215052 */     GIR_EraseRootFromParent_Done,
     /* 215053 */   // Label 4021: @215053
     /* 215053 */   GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(215098), // Rule ID 1534 //
     /* 215058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215069 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 215072 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 215075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215083 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215087 */     // (intrinsic_wo_chain:{ *:[v16i8] } 760:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMINPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 215087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv16i8),
     /* 215090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215092 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215094 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215096 */     GIR_RootConstrainSelectedInstOperands,
     /* 215097 */     // GIR_Coverage, 1534,
     /* 215097 */     GIR_EraseRootFromParent_Done,
     /* 215098 */   // Label 4022: @215098
     /* 215098 */   GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(215143), // Rule ID 1535 //
     /* 215103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 215114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 215117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 215120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215128 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215132 */     // (intrinsic_wo_chain:{ *:[v4i16] } 760:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMINPv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 215132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i16),
     /* 215135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215141 */     GIR_RootConstrainSelectedInstOperands,
     /* 215142 */     // GIR_Coverage, 1535,
     /* 215142 */     GIR_EraseRootFromParent_Done,
     /* 215143 */   // Label 4023: @215143
     /* 215143 */   GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(215188), // Rule ID 1536 //
     /* 215148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 215162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 215165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215173 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215177 */     // (intrinsic_wo_chain:{ *:[v8i16] } 760:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMINPv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 215177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv8i16),
     /* 215180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215186 */     GIR_RootConstrainSelectedInstOperands,
     /* 215187 */     // GIR_Coverage, 1536,
     /* 215187 */     GIR_EraseRootFromParent_Done,
     /* 215188 */   // Label 4024: @215188
     /* 215188 */   GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(215233), // Rule ID 1537 //
     /* 215193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 215204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 215207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 215210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215214 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215218 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215222 */     // (intrinsic_wo_chain:{ *:[v2i32] } 760:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMINPv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 215222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 215225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215227 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215231 */     GIR_RootConstrainSelectedInstOperands,
     /* 215232 */     // GIR_Coverage, 1537,
     /* 215232 */     GIR_EraseRootFromParent_Done,
     /* 215233 */   // Label 4025: @215233
     /* 215233 */   GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(215278), // Rule ID 1538 //
     /* 215238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminp),
     /* 215246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 215252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 215255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215263 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215267 */     // (intrinsic_wo_chain:{ *:[v4i32] } 760:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMINPv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 215267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINPv4i32),
     /* 215270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215274 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215276 */     GIR_RootConstrainSelectedInstOperands,
     /* 215277 */     // GIR_Coverage, 1538,
     /* 215277 */     GIR_EraseRootFromParent_Done,
     /* 215278 */   // Label 4026: @215278
     /* 215278 */   GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(215323), // Rule ID 1552 //
     /* 215283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 215294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 215297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 215300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215308 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215312 */     // (intrinsic_wo_chain:{ *:[v8i8] } 765:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQRSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 215312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i8),
     /* 215315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215321 */     GIR_RootConstrainSelectedInstOperands,
     /* 215322 */     // GIR_Coverage, 1552,
     /* 215322 */     GIR_EraseRootFromParent_Done,
     /* 215323 */   // Label 4027: @215323
     /* 215323 */   GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(215368), // Rule ID 1553 //
     /* 215328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215331 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215336 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 215342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 215345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215349 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215353 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215357 */     // (intrinsic_wo_chain:{ *:[v16i8] } 765:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQRSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 215357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv16i8),
     /* 215360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215366 */     GIR_RootConstrainSelectedInstOperands,
     /* 215367 */     // GIR_Coverage, 1553,
     /* 215367 */     GIR_EraseRootFromParent_Done,
     /* 215368 */   // Label 4028: @215368
     /* 215368 */   GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(215413), // Rule ID 1554 //
     /* 215373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 215384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 215387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 215390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215394 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215398 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215402 */     // (intrinsic_wo_chain:{ *:[v4i16] } 765:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQRSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 215402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i16),
     /* 215405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215409 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215411 */     GIR_RootConstrainSelectedInstOperands,
     /* 215412 */     // GIR_Coverage, 1554,
     /* 215412 */     GIR_EraseRootFromParent_Done,
     /* 215413 */   // Label 4029: @215413
     /* 215413 */   GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(215458), // Rule ID 1555 //
     /* 215418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 215432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 215435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215439 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215443 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215447 */     // (intrinsic_wo_chain:{ *:[v8i16] } 765:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQRSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 215447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv8i16),
     /* 215450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215454 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215456 */     GIR_RootConstrainSelectedInstOperands,
     /* 215457 */     // GIR_Coverage, 1555,
     /* 215457 */     GIR_EraseRootFromParent_Done,
     /* 215458 */   // Label 4030: @215458
     /* 215458 */   GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(215503), // Rule ID 1556 //
     /* 215463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 215474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 215477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 215480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215488 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215492 */     // (intrinsic_wo_chain:{ *:[v2i32] } 765:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQRSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 215492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i32),
     /* 215495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215501 */     GIR_RootConstrainSelectedInstOperands,
     /* 215502 */     // GIR_Coverage, 1556,
     /* 215502 */     GIR_EraseRootFromParent_Done,
     /* 215503 */   // Label 4031: @215503
     /* 215503 */   GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(215548), // Rule ID 1557 //
     /* 215508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 215522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 215525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215533 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215537 */     // (intrinsic_wo_chain:{ *:[v4i32] } 765:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQRSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 215537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv4i32),
     /* 215540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215542 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215544 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215546 */     GIR_RootConstrainSelectedInstOperands,
     /* 215547 */     // GIR_Coverage, 1557,
     /* 215547 */     GIR_EraseRootFromParent_Done,
     /* 215548 */   // Label 4032: @215548
     /* 215548 */   GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(215593), // Rule ID 1558 //
     /* 215553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 215561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 215567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 215570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215578 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215582 */     // (intrinsic_wo_chain:{ *:[v2i64] } 765:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQRSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 215582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv2i64),
     /* 215585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215587 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215589 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215591 */     GIR_RootConstrainSelectedInstOperands,
     /* 215592 */     // GIR_Coverage, 1558,
     /* 215592 */     GIR_EraseRootFromParent_Done,
     /* 215593 */   // Label 4033: @215593
     /* 215593 */   GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(215638), // Rule ID 1559 //
     /* 215598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 215609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 215612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 215615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215619 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215623 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215627 */     // (intrinsic_wo_chain:{ *:[v8i8] } 767:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 215627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i8),
     /* 215630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215636 */     GIR_RootConstrainSelectedInstOperands,
     /* 215637 */     // GIR_Coverage, 1559,
     /* 215637 */     GIR_EraseRootFromParent_Done,
     /* 215638 */   // Label 4034: @215638
     /* 215638 */   GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(215683), // Rule ID 1560 //
     /* 215643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 215657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 215660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215668 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215672 */     // (intrinsic_wo_chain:{ *:[v16i8] } 767:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 215672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv16i8),
     /* 215675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215679 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215681 */     GIR_RootConstrainSelectedInstOperands,
     /* 215682 */     // GIR_Coverage, 1560,
     /* 215682 */     GIR_EraseRootFromParent_Done,
     /* 215683 */   // Label 4035: @215683
     /* 215683 */   GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(215728), // Rule ID 1561 //
     /* 215688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 215699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 215702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 215705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215709 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215713 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215717 */     // (intrinsic_wo_chain:{ *:[v4i16] } 767:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 215717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i16),
     /* 215720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215722 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215724 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215726 */     GIR_RootConstrainSelectedInstOperands,
     /* 215727 */     // GIR_Coverage, 1561,
     /* 215727 */     GIR_EraseRootFromParent_Done,
     /* 215728 */   // Label 4036: @215728
     /* 215728 */   GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(215773), // Rule ID 1562 //
     /* 215733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 215744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 215747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 215750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215754 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215758 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215762 */     // (intrinsic_wo_chain:{ *:[v8i16] } 767:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 215762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv8i16),
     /* 215765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215769 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215771 */     GIR_RootConstrainSelectedInstOperands,
     /* 215772 */     // GIR_Coverage, 1562,
     /* 215772 */     GIR_EraseRootFromParent_Done,
     /* 215773 */   // Label 4037: @215773
     /* 215773 */   GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(215818), // Rule ID 1563 //
     /* 215778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 215789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 215792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 215795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215799 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215803 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215807 */     // (intrinsic_wo_chain:{ *:[v2i32] } 767:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 215807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i32),
     /* 215810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215814 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215816 */     GIR_RootConstrainSelectedInstOperands,
     /* 215817 */     // GIR_Coverage, 1563,
     /* 215817 */     GIR_EraseRootFromParent_Done,
     /* 215818 */   // Label 4038: @215818
     /* 215818 */   GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(215863), // Rule ID 1564 //
     /* 215823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 215834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 215837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 215840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215848 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215852 */     // (intrinsic_wo_chain:{ *:[v4i32] } 767:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 215852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv4i32),
     /* 215855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215859 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215861 */     GIR_RootConstrainSelectedInstOperands,
     /* 215862 */     // GIR_Coverage, 1564,
     /* 215862 */     GIR_EraseRootFromParent_Done,
     /* 215863 */   // Label 4039: @215863
     /* 215863 */   GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(215908), // Rule ID 1565 //
     /* 215868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215871 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 215876 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 215879 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 215882 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 215885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215889 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215893 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215897 */     // (intrinsic_wo_chain:{ *:[v2i64] } 767:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 215897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv2i64),
     /* 215900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215906 */     GIR_RootConstrainSelectedInstOperands,
     /* 215907 */     // GIR_Coverage, 1565,
     /* 215907 */     GIR_EraseRootFromParent_Done,
     /* 215908 */   // Label 4040: @215908
     /* 215908 */   GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(215953), // Rule ID 1579 //
     /* 215913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 215921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 215924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 215927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 215930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215934 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215938 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 215942 */     // (intrinsic_wo_chain:{ *:[v8i8] } 773:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (URSHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 215942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i8),
     /* 215945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215947 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215949 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215951 */     GIR_RootConstrainSelectedInstOperands,
     /* 215952 */     // GIR_Coverage, 1579,
     /* 215952 */     GIR_EraseRootFromParent_Done,
     /* 215953 */   // Label 4041: @215953
     /* 215953 */   GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(215998), // Rule ID 1580 //
     /* 215958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 215961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 215966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 215969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 215972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 215975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215983 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 215987 */     // (intrinsic_wo_chain:{ *:[v16i8] } 773:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (URSHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 215987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv16i8),
     /* 215990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 215992 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 215994 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 215996 */     GIR_RootConstrainSelectedInstOperands,
     /* 215997 */     // GIR_Coverage, 1580,
     /* 215997 */     GIR_EraseRootFromParent_Done,
     /* 215998 */   // Label 4042: @215998
     /* 215998 */   GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(216043), // Rule ID 1581 //
     /* 216003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216006 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 216011 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 216014 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 216017 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 216020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216024 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216028 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216032 */     // (intrinsic_wo_chain:{ *:[v4i16] } 773:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (URSHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 216032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i16),
     /* 216035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216037 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216039 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216041 */     GIR_RootConstrainSelectedInstOperands,
     /* 216042 */     // GIR_Coverage, 1581,
     /* 216042 */     GIR_EraseRootFromParent_Done,
     /* 216043 */   // Label 4043: @216043
     /* 216043 */   GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(216088), // Rule ID 1582 //
     /* 216048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 216056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 216059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 216062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 216065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216069 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216073 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216077 */     // (intrinsic_wo_chain:{ *:[v8i16] } 773:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (URSHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 216077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv8i16),
     /* 216080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216082 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216084 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216086 */     GIR_RootConstrainSelectedInstOperands,
     /* 216087 */     // GIR_Coverage, 1582,
     /* 216087 */     GIR_EraseRootFromParent_Done,
     /* 216088 */   // Label 4044: @216088
     /* 216088 */   GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(216133), // Rule ID 1583 //
     /* 216093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 216101 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 216104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 216107 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 216110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216114 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216118 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216122 */     // (intrinsic_wo_chain:{ *:[v2i32] } 773:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (URSHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 216122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i32),
     /* 216125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216127 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216129 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216131 */     GIR_RootConstrainSelectedInstOperands,
     /* 216132 */     // GIR_Coverage, 1583,
     /* 216132 */     GIR_EraseRootFromParent_Done,
     /* 216133 */   // Label 4045: @216133
     /* 216133 */   GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(216178), // Rule ID 1584 //
     /* 216138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 216146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 216149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 216152 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 216155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216159 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216163 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216167 */     // (intrinsic_wo_chain:{ *:[v4i32] } 773:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (URSHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 216167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv4i32),
     /* 216170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216176 */     GIR_RootConstrainSelectedInstOperands,
     /* 216177 */     // GIR_Coverage, 1584,
     /* 216177 */     GIR_EraseRootFromParent_Done,
     /* 216178 */   // Label 4046: @216178
     /* 216178 */   GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(216223), // Rule ID 1585 //
     /* 216183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 216191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 216194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 216197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 216200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216208 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216212 */     // (intrinsic_wo_chain:{ *:[v2i64] } 773:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (URSHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 216212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv2i64),
     /* 216215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216217 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216219 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216221 */     GIR_RootConstrainSelectedInstOperands,
     /* 216222 */     // GIR_Coverage, 1585,
     /* 216222 */     GIR_EraseRootFromParent_Done,
     /* 216223 */   // Label 4047: @216223
     /* 216223 */   GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(216268), // Rule ID 1586 //
     /* 216228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 216239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 216242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 216245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216249 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216253 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216257 */     // (intrinsic_wo_chain:{ *:[v8i8] } 776:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (USHLv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 216257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i8),
     /* 216260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216266 */     GIR_RootConstrainSelectedInstOperands,
     /* 216267 */     // GIR_Coverage, 1586,
     /* 216267 */     GIR_EraseRootFromParent_Done,
     /* 216268 */   // Label 4048: @216268
     /* 216268 */   GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(216313), // Rule ID 1587 //
     /* 216273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216276 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216281 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 216284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 216287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 216290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216298 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216302 */     // (intrinsic_wo_chain:{ *:[v16i8] } 776:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (USHLv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 216302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv16i8),
     /* 216305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216309 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216311 */     GIR_RootConstrainSelectedInstOperands,
     /* 216312 */     // GIR_Coverage, 1587,
     /* 216312 */     GIR_EraseRootFromParent_Done,
     /* 216313 */   // Label 4049: @216313
     /* 216313 */   GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(216358), // Rule ID 1588 //
     /* 216318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 216329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 216332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 216335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216343 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216347 */     // (intrinsic_wo_chain:{ *:[v4i16] } 776:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (USHLv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 216347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i16),
     /* 216350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216352 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216354 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216356 */     GIR_RootConstrainSelectedInstOperands,
     /* 216357 */     // GIR_Coverage, 1588,
     /* 216357 */     GIR_EraseRootFromParent_Done,
     /* 216358 */   // Label 4050: @216358
     /* 216358 */   GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(216403), // Rule ID 1589 //
     /* 216363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 216374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 216377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 216380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216388 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216392 */     // (intrinsic_wo_chain:{ *:[v8i16] } 776:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (USHLv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 216392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv8i16),
     /* 216395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216401 */     GIR_RootConstrainSelectedInstOperands,
     /* 216402 */     // GIR_Coverage, 1589,
     /* 216402 */     GIR_EraseRootFromParent_Done,
     /* 216403 */   // Label 4051: @216403
     /* 216403 */   GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(216448), // Rule ID 1590 //
     /* 216408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216411 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216416 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 216419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 216422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 216425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216429 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216433 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216437 */     // (intrinsic_wo_chain:{ *:[v2i32] } 776:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (USHLv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 216437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i32),
     /* 216440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216444 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216446 */     GIR_RootConstrainSelectedInstOperands,
     /* 216447 */     // GIR_Coverage, 1590,
     /* 216447 */     GIR_EraseRootFromParent_Done,
     /* 216448 */   // Label 4052: @216448
     /* 216448 */   GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(216493), // Rule ID 1591 //
     /* 216453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 216464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 216467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 216470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216474 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216478 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216482 */     // (intrinsic_wo_chain:{ *:[v4i32] } 776:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (USHLv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 216482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv4i32),
     /* 216485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216491 */     GIR_RootConstrainSelectedInstOperands,
     /* 216492 */     // GIR_Coverage, 1591,
     /* 216492 */     GIR_EraseRootFromParent_Done,
     /* 216493 */   // Label 4053: @216493
     /* 216493 */   GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(216538), // Rule ID 1592 //
     /* 216498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 216506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 216509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 216512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 216515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216519 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216523 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 216527 */     // (intrinsic_wo_chain:{ *:[v2i64] } 776:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (USHLv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 216527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv2i64),
     /* 216530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216536 */     GIR_RootConstrainSelectedInstOperands,
     /* 216537 */     // GIR_Coverage, 1592,
     /* 216537 */     GIR_EraseRootFromParent_Done,
     /* 216538 */   // Label 4054: @216538
     /* 216538 */   GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(216583), // Rule ID 1620 //
     /* 216543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 216551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 216554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 216557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 216560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216564 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216568 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216572 */     // (intrinsic_wo_chain:{ *:[f64] } 811:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FABD64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 216572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 216575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216579 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216581 */     GIR_RootConstrainSelectedInstOperands,
     /* 216582 */     // GIR_Coverage, 1620,
     /* 216582 */     GIR_EraseRootFromParent_Done,
     /* 216583 */   // Label 4055: @216583
     /* 216583 */   GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(216628), // Rule ID 1621 //
     /* 216588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 216596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 216599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 216602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 216605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216609 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216613 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216617 */     // (intrinsic_wo_chain:{ *:[f32] } 811:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FABD32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 216617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
     /* 216620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216624 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216626 */     GIR_RootConstrainSelectedInstOperands,
     /* 216627 */     // GIR_Coverage, 1621,
     /* 216627 */     GIR_EraseRootFromParent_Done,
     /* 216628 */   // Label 4056: @216628
     /* 216628 */   GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(216673), // Rule ID 1622 //
     /* 216633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 216636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 216641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 216644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 216647 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 216650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216654 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216658 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216662 */     // (intrinsic_wo_chain:{ *:[f16] } 811:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FABD16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 216662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
     /* 216665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216667 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216669 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216671 */     GIR_RootConstrainSelectedInstOperands,
     /* 216672 */     // GIR_Coverage, 1622,
     /* 216672 */     GIR_EraseRootFromParent_Done,
     /* 216673 */   // Label 4057: @216673
     /* 216673 */   GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(216718), // Rule ID 1623 //
     /* 216678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 216686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 216689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 216692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 216695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216699 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216703 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216707 */     // (intrinsic_wo_chain:{ *:[i64] } 601:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FACGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 216707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
     /* 216710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216716 */     GIR_RootConstrainSelectedInstOperands,
     /* 216717 */     // GIR_Coverage, 1623,
     /* 216717 */     GIR_EraseRootFromParent_Done,
     /* 216718 */   // Label 4058: @216718
     /* 216718 */   GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(216763), // Rule ID 1624 //
     /* 216723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216726 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 216731 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 216734 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 216737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 216740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216748 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216752 */     // (intrinsic_wo_chain:{ *:[i32] } 601:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FACGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 216752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE32),
     /* 216755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216759 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216761 */     GIR_RootConstrainSelectedInstOperands,
     /* 216762 */     // GIR_Coverage, 1624,
     /* 216762 */     GIR_EraseRootFromParent_Done,
     /* 216763 */   // Label 4059: @216763
     /* 216763 */   GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(216808), // Rule ID 1625 //
     /* 216768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 216776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 216779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 216782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 216785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216789 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216793 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216797 */     // (intrinsic_wo_chain:{ *:[i64] } 602:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FACGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 216797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
     /* 216800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216804 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216806 */     GIR_RootConstrainSelectedInstOperands,
     /* 216807 */     // GIR_Coverage, 1625,
     /* 216807 */     GIR_EraseRootFromParent_Done,
     /* 216808 */   // Label 4060: @216808
     /* 216808 */   GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(216853), // Rule ID 1626 //
     /* 216813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 216816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 216821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 216824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 216827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 216830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216834 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216838 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216842 */     // (intrinsic_wo_chain:{ *:[i32] } 602:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FACGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 216842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT32),
     /* 216845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216847 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216851 */     GIR_RootConstrainSelectedInstOperands,
     /* 216852 */     // GIR_Coverage, 1626,
     /* 216852 */     GIR_EraseRootFromParent_Done,
     /* 216853 */   // Label 4061: @216853
     /* 216853 */   GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(216898), // Rule ID 1633 //
     /* 216858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 216861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 216866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 216869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 216872 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 216875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 216887 */     // (intrinsic_wo_chain:{ *:[f64] } 635:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULX64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 216887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 216890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216896 */     GIR_RootConstrainSelectedInstOperands,
     /* 216897 */     // GIR_Coverage, 1633,
     /* 216897 */     GIR_EraseRootFromParent_Done,
     /* 216898 */   // Label 4062: @216898
     /* 216898 */   GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(216943), // Rule ID 1634 //
     /* 216903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 216906 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 216911 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 216914 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 216917 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 216920 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216924 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216928 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 216932 */     // (intrinsic_wo_chain:{ *:[f32] } 635:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULX32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 216932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX32),
     /* 216935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216939 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216941 */     GIR_RootConstrainSelectedInstOperands,
     /* 216942 */     // GIR_Coverage, 1634,
     /* 216942 */     GIR_EraseRootFromParent_Done,
     /* 216943 */   // Label 4063: @216943
     /* 216943 */   GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(216988), // Rule ID 1635 //
     /* 216948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 216951 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 216956 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 216959 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 216962 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 216965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216969 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216973 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 216977 */     // (intrinsic_wo_chain:{ *:[f16] } 635:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULX16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 216977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX16),
     /* 216980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 216982 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 216984 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 216986 */     GIR_RootConstrainSelectedInstOperands,
     /* 216987 */     // GIR_Coverage, 1635,
     /* 216987 */     GIR_EraseRootFromParent_Done,
     /* 216988 */   // Label 4064: @216988
     /* 216988 */   GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(217033), // Rule ID 1636 //
     /* 216993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 216996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 217001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217014 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217018 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217022 */     // (intrinsic_wo_chain:{ *:[f64] } 658:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FRECPS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 217022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
     /* 217025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217031 */     GIR_RootConstrainSelectedInstOperands,
     /* 217032 */     // GIR_Coverage, 1636,
     /* 217032 */     GIR_EraseRootFromParent_Done,
     /* 217033 */   // Label 4065: @217033
     /* 217033 */   GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(217078), // Rule ID 1637 //
     /* 217038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 217041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 217046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217063 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217067 */     // (intrinsic_wo_chain:{ *:[f32] } 658:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FRECPS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 217067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS32),
     /* 217070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217076 */     GIR_RootConstrainSelectedInstOperands,
     /* 217077 */     // GIR_Coverage, 1637,
     /* 217077 */     GIR_EraseRootFromParent_Done,
     /* 217078 */   // Label 4066: @217078
     /* 217078 */   GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(217123), // Rule ID 1638 //
     /* 217083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 217086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 217091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 217094 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 217097 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 217100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217108 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217112 */     // (intrinsic_wo_chain:{ *:[f16] } 658:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FRECPS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 217112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS16),
     /* 217115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217121 */     GIR_RootConstrainSelectedInstOperands,
     /* 217122 */     // GIR_Coverage, 1638,
     /* 217122 */     GIR_EraseRootFromParent_Done,
     /* 217123 */   // Label 4067: @217123
     /* 217123 */   GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(217168), // Rule ID 1639 //
     /* 217128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 217131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 217136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217149 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217157 */     // (intrinsic_wo_chain:{ *:[f64] } 665:{ *:[iPTR] }, FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FRSQRTS64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 217157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
     /* 217160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217166 */     GIR_RootConstrainSelectedInstOperands,
     /* 217167 */     // GIR_Coverage, 1639,
     /* 217167 */     GIR_EraseRootFromParent_Done,
     /* 217168 */   // Label 4068: @217168
     /* 217168 */   GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(217213), // Rule ID 1640 //
     /* 217173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 217176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 217181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217187 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217194 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217198 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217202 */     // (intrinsic_wo_chain:{ *:[f32] } 665:{ *:[iPTR] }, FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FRSQRTS32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 217202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS32),
     /* 217205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217209 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217211 */     GIR_RootConstrainSelectedInstOperands,
     /* 217212 */     // GIR_Coverage, 1640,
     /* 217212 */     GIR_EraseRootFromParent_Done,
     /* 217213 */   // Label 4069: @217213
     /* 217213 */   GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(217258), // Rule ID 1641 //
     /* 217218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 217221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 217226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
     /* 217229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 217232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 217235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217239 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217243 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 217247 */     // (intrinsic_wo_chain:{ *:[f16] } 665:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FRSQRTS16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 217247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS16),
     /* 217250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217254 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217256 */     GIR_RootConstrainSelectedInstOperands,
     /* 217257 */     // GIR_Coverage, 1641,
     /* 217257 */     GIR_EraseRootFromParent_Done,
     /* 217258 */   // Label 4070: @217258
     /* 217258 */   GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(217303), // Rule ID 1643 //
     /* 217263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmulh),
     /* 217271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217292 */     // (intrinsic_wo_chain:{ *:[i32] } 705:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 217292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULHv1i32),
     /* 217295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217297 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217301 */     GIR_RootConstrainSelectedInstOperands,
     /* 217302 */     // GIR_Coverage, 1643,
     /* 217302 */     GIR_EraseRootFromParent_Done,
     /* 217303 */   // Label 4071: @217303
     /* 217303 */   GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(217348), // Rule ID 1644 //
     /* 217308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217311 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmulh),
     /* 217316 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217329 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217333 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217337 */     // (intrinsic_wo_chain:{ *:[i32] } 713:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMULHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 217337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULHv1i32),
     /* 217340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217342 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217346 */     GIR_RootConstrainSelectedInstOperands,
     /* 217347 */     // GIR_Coverage, 1644,
     /* 217347 */     GIR_EraseRootFromParent_Done,
     /* 217348 */   // Label 4072: @217348
     /* 217348 */   GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(217393), // Rule ID 1645 //
     /* 217353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 217361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217374 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217378 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217382 */     // (intrinsic_wo_chain:{ *:[v1i64] } 716:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
     /* 217385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217387 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217389 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217391 */     GIR_RootConstrainSelectedInstOperands,
     /* 217392 */     // GIR_Coverage, 1645,
     /* 217392 */     GIR_EraseRootFromParent_Done,
     /* 217393 */   // Label 4073: @217393
     /* 217393 */   GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(217438), // Rule ID 1646 //
     /* 217398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 217406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217423 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217427 */     // (intrinsic_wo_chain:{ *:[v1i64] } 719:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
     /* 217430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217436 */     GIR_RootConstrainSelectedInstOperands,
     /* 217437 */     // GIR_Coverage, 1646,
     /* 217437 */     GIR_EraseRootFromParent_Done,
     /* 217438 */   // Label 4074: @217438
     /* 217438 */   GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(217483), // Rule ID 1648 //
     /* 217443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 217451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217464 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217468 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217472 */     // (intrinsic_wo_chain:{ *:[v1i64] } 727:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
     /* 217475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217481 */     GIR_RootConstrainSelectedInstOperands,
     /* 217482 */     // GIR_Coverage, 1648,
     /* 217482 */     GIR_EraseRootFromParent_Done,
     /* 217483 */   // Label 4075: @217483
     /* 217483 */   GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(217528), // Rule ID 1649 //
     /* 217488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217491 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 217496 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217499 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217502 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217509 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217513 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217517 */     // (intrinsic_wo_chain:{ *:[v1i64] } 728:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
     /* 217520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217526 */     GIR_RootConstrainSelectedInstOperands,
     /* 217527 */     // GIR_Coverage, 1649,
     /* 217527 */     GIR_EraseRootFromParent_Done,
     /* 217528 */   // Label 4076: @217528
     /* 217528 */   GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(217573), // Rule ID 1652 //
     /* 217533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 217541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217547 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217558 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217562 */     // (intrinsic_wo_chain:{ *:[v1i64] } 765:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQRSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
     /* 217565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217569 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217571 */     GIR_RootConstrainSelectedInstOperands,
     /* 217572 */     // GIR_Coverage, 1652,
     /* 217572 */     GIR_EraseRootFromParent_Done,
     /* 217573 */   // Label 4077: @217573
     /* 217573 */   GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(217618), // Rule ID 1653 //
     /* 217578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 217586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217599 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217603 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217607 */     // (intrinsic_wo_chain:{ *:[v1i64] } 767:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
     /* 217610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217616 */     GIR_RootConstrainSelectedInstOperands,
     /* 217617 */     // GIR_Coverage, 1653,
     /* 217617 */     GIR_EraseRootFromParent_Done,
     /* 217618 */   // Label 4078: @217618
     /* 217618 */   GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(217663), // Rule ID 1655 //
     /* 217623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 217631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217652 */     // (intrinsic_wo_chain:{ *:[v1i64] } 773:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (URSHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
     /* 217655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217657 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217661 */     GIR_RootConstrainSelectedInstOperands,
     /* 217662 */     // GIR_Coverage, 1655,
     /* 217662 */     GIR_EraseRootFromParent_Done,
     /* 217663 */   // Label 4079: @217663
     /* 217663 */   GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(217708), // Rule ID 1656 //
     /* 217668 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217671 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 217676 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217679 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217682 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217689 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217693 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217697 */     // (intrinsic_wo_chain:{ *:[v1i64] } 776:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (USHLv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 217697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
     /* 217700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217706 */     GIR_RootConstrainSelectedInstOperands,
     /* 217707 */     // GIR_Coverage, 1656,
     /* 217707 */     GIR_EraseRootFromParent_Done,
     /* 217708 */   // Label 4080: @217708
     /* 217708 */   GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(217753), // Rule ID 1707 //
     /* 217713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 217721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217730 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217734 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217738 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217742 */     // (intrinsic_wo_chain:{ *:[i64] } 740:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)  =>  (SUQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
     /* 217742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
     /* 217745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217751 */     GIR_RootConstrainSelectedInstOperands,
     /* 217752 */     // GIR_Coverage, 1707,
     /* 217752 */     GIR_EraseRootFromParent_Done,
     /* 217753 */   // Label 4081: @217753
     /* 217753 */   GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(217798), // Rule ID 1708 //
     /* 217758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 217766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217779 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217783 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217787 */     // (intrinsic_wo_chain:{ *:[i32] } 740:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)  =>  (SUQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
     /* 217787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i32),
     /* 217790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217796 */     GIR_RootConstrainSelectedInstOperands,
     /* 217797 */     // GIR_Coverage, 1708,
     /* 217797 */     GIR_EraseRootFromParent_Done,
     /* 217798 */   // Label 4082: @217798
     /* 217798 */   GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(217843), // Rule ID 1713 //
     /* 217803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 217811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 217814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 217817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 217820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217824 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217828 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217832 */     // (intrinsic_wo_chain:{ *:[i64] } 779:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)  =>  (USQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rd, FPR64:{ *:[i64] }:$Rn)
     /* 217832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
     /* 217835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217837 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217839 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217841 */     GIR_RootConstrainSelectedInstOperands,
     /* 217842 */     // GIR_Coverage, 1713,
     /* 217842 */     GIR_EraseRootFromParent_Done,
     /* 217843 */   // Label 4083: @217843
     /* 217843 */   GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(217888), // Rule ID 1714 //
     /* 217848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 217856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 217859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 217862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 217865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217869 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217873 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 217877 */     // (intrinsic_wo_chain:{ *:[i32] } 779:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)  =>  (USQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn)
     /* 217877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i32),
     /* 217880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 217882 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 217884 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 217886 */     GIR_RootConstrainSelectedInstOperands,
     /* 217887 */     // GIR_Coverage, 1714,
     /* 217887 */     GIR_EraseRootFromParent_Done,
     /* 217888 */   // Label 4084: @217888
     /* 217888 */   GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(217933), // Rule ID 1715 //
     /* 217893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 217901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 217904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 217907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 217910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217914 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217918 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217922 */     // (intrinsic_wo_chain:{ *:[v8i8] } 593:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 217922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
     /* 217925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217929 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217931 */     GIR_RootConstrainSelectedInstOperands,
     /* 217932 */     // GIR_Coverage, 1715,
     /* 217932 */     GIR_EraseRootFromParent_Done,
     /* 217933 */   // Label 4085: @217933
     /* 217933 */   GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(217978), // Rule ID 1716 //
     /* 217938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 217946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 217949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 217952 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 217955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 217959 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217963 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 217967 */     // (intrinsic_wo_chain:{ *:[v4i16] } 593:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 217967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
     /* 217970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 217972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 217974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 217976 */     GIR_RootConstrainSelectedInstOperands,
     /* 217977 */     // GIR_Coverage, 1716,
     /* 217977 */     GIR_EraseRootFromParent_Done,
     /* 217978 */   // Label 4086: @217978
     /* 217978 */   GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(218023), // Rule ID 1717 //
     /* 217983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 217986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_addhn),
     /* 217991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 217994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 217997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 218000 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218004 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218008 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218012 */     // (intrinsic_wo_chain:{ *:[v2i32] } 593:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 218012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
     /* 218015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218017 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218021 */     GIR_RootConstrainSelectedInstOperands,
     /* 218022 */     // GIR_Coverage, 1717,
     /* 218022 */     GIR_EraseRootFromParent_Done,
     /* 218023 */   // Label 4087: @218023
     /* 218023 */   GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(218068), // Rule ID 1718 //
     /* 218028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 218036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 218039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218049 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218053 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218057 */     // (intrinsic_wo_chain:{ *:[v8i8] } 739:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 218057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 218060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218064 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218066 */     GIR_RootConstrainSelectedInstOperands,
     /* 218067 */     // GIR_Coverage, 1718,
     /* 218067 */     GIR_EraseRootFromParent_Done,
     /* 218068 */   // Label 4088: @218068
     /* 218068 */   GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(218113), // Rule ID 1719 //
     /* 218073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 218081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218098 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218102 */     // (intrinsic_wo_chain:{ *:[v4i16] } 739:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 218102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 218105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218111 */     GIR_RootConstrainSelectedInstOperands,
     /* 218112 */     // GIR_Coverage, 1719,
     /* 218112 */     GIR_EraseRootFromParent_Done,
     /* 218113 */   // Label 4089: @218113
     /* 218113 */   GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(218158), // Rule ID 1720 //
     /* 218118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_subhn),
     /* 218126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 218129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 218132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 218135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218143 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218147 */     // (intrinsic_wo_chain:{ *:[v2i32] } 739:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 218147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 218150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218156 */     GIR_RootConstrainSelectedInstOperands,
     /* 218157 */     // GIR_Coverage, 1720,
     /* 218157 */     GIR_EraseRootFromParent_Done,
     /* 218158 */   // Label 4090: @218158
     /* 218158 */   GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(218203), // Rule ID 1721 //
     /* 218163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 218171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 218174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218177 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218184 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218188 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218192 */     // (intrinsic_wo_chain:{ *:[v8i8] } 681:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (RADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 218192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv8i16_v8i8),
     /* 218195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218199 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218201 */     GIR_RootConstrainSelectedInstOperands,
     /* 218202 */     // GIR_Coverage, 1721,
     /* 218202 */     GIR_EraseRootFromParent_Done,
     /* 218203 */   // Label 4091: @218203
     /* 218203 */   GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(218248), // Rule ID 1722 //
     /* 218208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218211 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 218216 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218219 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218222 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218233 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218237 */     // (intrinsic_wo_chain:{ *:[v4i16] } 681:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (RADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 218237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv4i32_v4i16),
     /* 218240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218242 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218244 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218246 */     GIR_RootConstrainSelectedInstOperands,
     /* 218247 */     // GIR_Coverage, 1722,
     /* 218247 */     GIR_EraseRootFromParent_Done,
     /* 218248 */   // Label 4092: @218248
     /* 218248 */   GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(218293), // Rule ID 1723 //
     /* 218253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_raddhn),
     /* 218261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 218264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 218267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 218270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218274 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218278 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218282 */     // (intrinsic_wo_chain:{ *:[v2i32] } 681:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (RADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 218282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNv2i64_v2i32),
     /* 218285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218287 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218289 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218291 */     GIR_RootConstrainSelectedInstOperands,
     /* 218292 */     // GIR_Coverage, 1723,
     /* 218292 */     GIR_EraseRootFromParent_Done,
     /* 218293 */   // Label 4093: @218293
     /* 218293 */   GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(218338), // Rule ID 1724 //
     /* 218298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 218306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 218309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218319 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218323 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218327 */     // (intrinsic_wo_chain:{ *:[v8i8] } 683:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (RSUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 218327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv8i16_v8i8),
     /* 218330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218334 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218336 */     GIR_RootConstrainSelectedInstOperands,
     /* 218337 */     // GIR_Coverage, 1724,
     /* 218337 */     GIR_EraseRootFromParent_Done,
     /* 218338 */   // Label 4094: @218338
     /* 218338 */   GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(218383), // Rule ID 1725 //
     /* 218343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 218351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218364 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218368 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218372 */     // (intrinsic_wo_chain:{ *:[v4i16] } 683:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (RSUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 218372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv4i32_v4i16),
     /* 218375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218381 */     GIR_RootConstrainSelectedInstOperands,
     /* 218382 */     // GIR_Coverage, 1725,
     /* 218382 */     GIR_EraseRootFromParent_Done,
     /* 218383 */   // Label 4095: @218383
     /* 218383 */   GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(218428), // Rule ID 1726 //
     /* 218388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_rsubhn),
     /* 218396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 218399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 218402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 218405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218413 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218417 */     // (intrinsic_wo_chain:{ *:[v2i32] } 683:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (RSUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 218417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNv2i64_v2i32),
     /* 218420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218426 */     GIR_RootConstrainSelectedInstOperands,
     /* 218427 */     // GIR_Coverage, 1726,
     /* 218427 */     GIR_EraseRootFromParent_Done,
     /* 218428 */   // Label 4096: @218428
     /* 218428 */   GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(218473), // Rule ID 1781 //
     /* 218433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 218441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218462 */     // (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQDMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 218462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv4i16_v4i32),
     /* 218465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218467 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218469 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218471 */     GIR_RootConstrainSelectedInstOperands,
     /* 218472 */     // GIR_Coverage, 1781,
     /* 218472 */     GIR_EraseRootFromParent_Done,
     /* 218473 */   // Label 4097: @218473
     /* 218473 */   GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(218518), // Rule ID 1783 //
     /* 218478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 218481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 218486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 218489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 218492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 218495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218507 */     // (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQDMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 218507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLv2i32_v2i64),
     /* 218510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218514 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218516 */     GIR_RootConstrainSelectedInstOperands,
     /* 218517 */     // GIR_Coverage, 1783,
     /* 218517 */     GIR_EraseRootFromParent_Done,
     /* 218518 */   // Label 4098: @218518
     /* 218518 */   GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(218563), // Rule ID 2334 //
     /* 218523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 218526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aese),
     /* 218531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 218534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 218537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 218540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218548 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218552 */     // (intrinsic_wo_chain:{ *:[v16i8] } 536:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (AESErr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 218552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESErr),
     /* 218555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218561 */     GIR_RootConstrainSelectedInstOperands,
     /* 218562 */     // GIR_Coverage, 2334,
     /* 218562 */     GIR_EraseRootFromParent_Done,
     /* 218563 */   // Label 4099: @218563
     /* 218563 */   GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(218608), // Rule ID 2335 //
     /* 218568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 218571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_aesd),
     /* 218576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 218579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 218582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 218585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218597 */     // (intrinsic_wo_chain:{ *:[v16i8] } 535:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)  =>  (AESDrr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn)
     /* 218597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESDrr),
     /* 218600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218604 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218606 */     GIR_RootConstrainSelectedInstOperands,
     /* 218607 */     // GIR_Coverage, 2335,
     /* 218607 */     GIR_EraseRootFromParent_Done,
     /* 218608 */   // Label 4100: @218608
     /* 218608 */   GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(218653), // Rule ID 2346 //
     /* 218613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 218616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su1),
     /* 218621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218634 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218638 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218642 */     // (intrinsic_wo_chain:{ *:[v4i32] } 549:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SHA1SU1rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 218642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU1rr),
     /* 218645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218647 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218651 */     GIR_RootConstrainSelectedInstOperands,
     /* 218652 */     // GIR_Coverage, 2346,
     /* 218652 */     GIR_EraseRootFromParent_Done,
     /* 218653 */   // Label 4101: @218653
     /* 218653 */   GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(218698), // Rule ID 2347 //
     /* 218658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 218661 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su0),
     /* 218666 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218669 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218672 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218679 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218683 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218687 */     // (intrinsic_wo_chain:{ *:[v4i32] } 552:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)  =>  (SHA256SU0rr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn)
     /* 218687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU0rr),
     /* 218690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 218692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 218694 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 218696 */     GIR_RootConstrainSelectedInstOperands,
     /* 218697 */     // GIR_Coverage, 2347,
     /* 218697 */     GIR_EraseRootFromParent_Done,
     /* 218698 */   // Label 4102: @218698
     /* 218698 */   GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(218743), // Rule ID 2370 //
     /* 218703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 218706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 218711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218720 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218724 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218728 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218732 */     // (intrinsic_wo_chain:{ *:[v4f16] } 656:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (FSCALEv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 218732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv4f16),
     /* 218735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218737 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218739 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218741 */     GIR_RootConstrainSelectedInstOperands,
     /* 218742 */     // GIR_Coverage, 2370,
     /* 218742 */     GIR_EraseRootFromParent_Done,
     /* 218743 */   // Label 4103: @218743
     /* 218743 */   GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(218788), // Rule ID 2371 //
     /* 218748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 218751 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 218756 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218759 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218762 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218769 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218773 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218777 */     // (intrinsic_wo_chain:{ *:[v8f16] } 656:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (FSCALEv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 218777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv8f16),
     /* 218780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218782 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218784 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218786 */     GIR_RootConstrainSelectedInstOperands,
     /* 218787 */     // GIR_Coverage, 2371,
     /* 218787 */     GIR_EraseRootFromParent_Done,
     /* 218788 */   // Label 4104: @218788
     /* 218788 */   GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(218833), // Rule ID 2372 //
     /* 218793 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 218796 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 218801 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 218804 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 218807 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 218810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218822 */     // (intrinsic_wo_chain:{ *:[v2f32] } 656:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (FSCALEv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 218822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv2f32),
     /* 218825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218831 */     GIR_RootConstrainSelectedInstOperands,
     /* 218832 */     // GIR_Coverage, 2372,
     /* 218832 */     GIR_EraseRootFromParent_Done,
     /* 218833 */   // Label 4105: @218833
     /* 218833 */   GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(218878), // Rule ID 2373 //
     /* 218838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 218841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 218846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 218849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 218852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 218855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218859 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218863 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218867 */     // (intrinsic_wo_chain:{ *:[v4f32] } 656:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (FSCALEv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 218867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv4f32),
     /* 218870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218874 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218876 */     GIR_RootConstrainSelectedInstOperands,
     /* 218877 */     // GIR_Coverage, 2373,
     /* 218877 */     GIR_EraseRootFromParent_Done,
     /* 218878 */   // Label 4106: @218878
     /* 218878 */   GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(218923), // Rule ID 2374 //
     /* 218883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 218886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fscale),
     /* 218891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 218894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 218897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 218900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218904 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218908 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218912 */     // (intrinsic_wo_chain:{ *:[v2f64] } 656:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (FSCALEv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 218912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALEv2f64),
     /* 218915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218917 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218921 */     GIR_RootConstrainSelectedInstOperands,
     /* 218922 */     // GIR_Coverage, 2374,
     /* 218922 */     GIR_EraseRootFromParent_Done,
     /* 218923 */   // Label 4107: @218923
     /* 218923 */   GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(218968), // Rule ID 2375 //
     /* 218928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 218931 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 218936 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 218939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 218942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 218945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218949 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218953 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 218957 */     // (intrinsic_wo_chain:{ *:[v4f16] } 605:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FAMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 218957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f16),
     /* 218960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 218962 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 218964 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 218966 */     GIR_RootConstrainSelectedInstOperands,
     /* 218967 */     // GIR_Coverage, 2375,
     /* 218967 */     GIR_EraseRootFromParent_Done,
     /* 218968 */   // Label 4108: @218968
     /* 218968 */   GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(219013), // Rule ID 2378 //
     /* 218973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 218976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 218981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 218984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 218987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 218990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 218998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219002 */     // (intrinsic_wo_chain:{ *:[v8f16] } 605:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FAMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 219002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv8f16),
     /* 219005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219011 */     GIR_RootConstrainSelectedInstOperands,
     /* 219012 */     // GIR_Coverage, 2378,
     /* 219012 */     GIR_EraseRootFromParent_Done,
     /* 219013 */   // Label 4109: @219013
     /* 219013 */   GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(219058), // Rule ID 2381 //
     /* 219018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 219026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 219029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 219032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 219035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219047 */     // (intrinsic_wo_chain:{ *:[v2f32] } 605:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FAMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 219047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f32),
     /* 219050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219056 */     GIR_RootConstrainSelectedInstOperands,
     /* 219057 */     // GIR_Coverage, 2381,
     /* 219057 */     GIR_EraseRootFromParent_Done,
     /* 219058 */   // Label 4110: @219058
     /* 219058 */   GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(219103), // Rule ID 2384 //
     /* 219063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 219071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 219074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 219077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 219080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219088 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219092 */     // (intrinsic_wo_chain:{ *:[v4f32] } 605:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FAMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 219092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f32),
     /* 219095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219097 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219099 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219101 */     GIR_RootConstrainSelectedInstOperands,
     /* 219102 */     // GIR_Coverage, 2384,
     /* 219102 */     GIR_EraseRootFromParent_Done,
     /* 219103 */   // Label 4111: @219103
     /* 219103 */   GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(219148), // Rule ID 2387 //
     /* 219108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famax),
     /* 219116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 219119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 219122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 219125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219133 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219137 */     // (intrinsic_wo_chain:{ *:[v2f64] } 605:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FAMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 219137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f64),
     /* 219140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219146 */     GIR_RootConstrainSelectedInstOperands,
     /* 219147 */     // GIR_Coverage, 2387,
     /* 219147 */     GIR_EraseRootFromParent_Done,
     /* 219148 */   // Label 4112: @219148
     /* 219148 */   GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(219193), // Rule ID 2390 //
     /* 219153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 219161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 219164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 219167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 219170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219178 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219182 */     // (intrinsic_wo_chain:{ *:[v4f16] } 606:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FAMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 219182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f16),
     /* 219185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219189 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219191 */     GIR_RootConstrainSelectedInstOperands,
     /* 219192 */     // GIR_Coverage, 2390,
     /* 219192 */     GIR_EraseRootFromParent_Done,
     /* 219193 */   // Label 4113: @219193
     /* 219193 */   GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(219238), // Rule ID 2393 //
     /* 219198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 219206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 219209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 219212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 219215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219223 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219227 */     // (intrinsic_wo_chain:{ *:[v8f16] } 606:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FAMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 219227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv8f16),
     /* 219230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219234 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219236 */     GIR_RootConstrainSelectedInstOperands,
     /* 219237 */     // GIR_Coverage, 2393,
     /* 219237 */     GIR_EraseRootFromParent_Done,
     /* 219238 */   // Label 4114: @219238
     /* 219238 */   GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(219283), // Rule ID 2396 //
     /* 219243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 219251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 219254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 219257 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 219260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219268 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219272 */     // (intrinsic_wo_chain:{ *:[v2f32] } 606:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FAMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 219272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f32),
     /* 219275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219277 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219279 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219281 */     GIR_RootConstrainSelectedInstOperands,
     /* 219282 */     // GIR_Coverage, 2396,
     /* 219282 */     GIR_EraseRootFromParent_Done,
     /* 219283 */   // Label 4115: @219283
     /* 219283 */   GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(219328), // Rule ID 2399 //
     /* 219288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 219296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 219299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 219302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 219305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219313 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219317 */     // (intrinsic_wo_chain:{ *:[v4f32] } 606:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FAMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 219317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f32),
     /* 219320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219326 */     GIR_RootConstrainSelectedInstOperands,
     /* 219327 */     // GIR_Coverage, 2399,
     /* 219327 */     GIR_EraseRootFromParent_Done,
     /* 219328 */   // Label 4116: @219328
     /* 219328 */   GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(219373), // Rule ID 2402 //
     /* 219333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 219336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_famin),
     /* 219341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 219344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 219347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 219350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219358 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 219362 */     // (intrinsic_wo_chain:{ *:[v2f64] } 606:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FAMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 219362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f64),
     /* 219365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219369 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219371 */     GIR_RootConstrainSelectedInstOperands,
     /* 219372 */     // GIR_Coverage, 2402,
     /* 219372 */     GIR_EraseRootFromParent_Done,
     /* 219373 */   // Label 4117: @219373
     /* 219373 */   GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(219418), // Rule ID 2457 //
     /* 219378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 219381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aese),
     /* 219386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 219389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 219392 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 219395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219403 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219407 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1286:{ *:[iPTR] }, ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)  =>  (AESE_ZZZ_B:{ *:[nxv16i8] } ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)
     /* 219407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESE_ZZZ_B),
     /* 219410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 219412 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 219414 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 219416 */     GIR_RootConstrainSelectedInstOperands,
     /* 219417 */     // GIR_Coverage, 2457,
     /* 219417 */     GIR_EraseRootFromParent_Done,
     /* 219418 */   // Label 4118: @219418
     /* 219418 */   GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(219463), // Rule ID 2458 //
     /* 219423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 219426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_aesd),
     /* 219431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 219434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 219437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 219440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219452 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1281:{ *:[iPTR] }, ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)  =>  (AESD_ZZZ_B:{ *:[nxv16i8] } ZPR8:{ *:[nxv16i8] }:$_Zdn, ZPR8:{ *:[nxv16i8] }:$Zm)
     /* 219452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AESD_ZZZ_B),
     /* 219455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 219457 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 219459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 219461 */     GIR_RootConstrainSelectedInstOperands,
     /* 219462 */     // GIR_Coverage, 2458,
     /* 219462 */     GIR_EraseRootFromParent_Done,
     /* 219463 */   // Label 4119: @219463
     /* 219463 */   GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(219508), // Rule ID 2459 //
     /* 219468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVESM4),
     /* 219471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4e),
     /* 219476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 219479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 219482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 219485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219489 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219493 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 219497 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1776:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$_Zdn, ZPR32:{ *:[nxv4i32] }:$Zm)  =>  (SM4E_ZZZ_S:{ *:[nxv4i32] } ZPR32:{ *:[nxv4i32] }:$_Zdn, ZPR32:{ *:[nxv4i32] }:$Zm)
     /* 219497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E_ZZZ_S),
     /* 219500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 219502 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Zdn
     /* 219504 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 219506 */     GIR_RootConstrainSelectedInstOperands,
     /* 219507 */     // GIR_Coverage, 2459,
     /* 219507 */     GIR_EraseRootFromParent_Done,
     /* 219508 */   // Label 4120: @219508
     /* 219508 */   GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(219553), // Rule ID 2537 //
     /* 219513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 219516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 219521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 219530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219534 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219538 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219542 */     // (intrinsic_wo_chain:{ *:[i64] } 704:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 219542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
     /* 219545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219551 */     GIR_RootConstrainSelectedInstOperands,
     /* 219552 */     // GIR_Coverage, 2537,
     /* 219552 */     GIR_EraseRootFromParent_Done,
     /* 219553 */   // Label 4121: @219553
     /* 219553 */   GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(219598), // Rule ID 2538 //
     /* 219558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 219561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqadd),
     /* 219566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 219575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 219579 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 219583 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 219587 */     // (intrinsic_wo_chain:{ *:[i32] } 704:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 219587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i32),
     /* 219590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219594 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219596 */     GIR_RootConstrainSelectedInstOperands,
     /* 219597 */     // GIR_Coverage, 2538,
     /* 219597 */     GIR_EraseRootFromParent_Done,
     /* 219598 */   // Label 4122: @219598
     /* 219598 */   GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(219643), // Rule ID 2544 //
     /* 219603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 219606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sisd_fabd),
     /* 219611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 219620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219628 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219632 */     // (intrinsic_wo_chain:{ *:[v1f64] } 811:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 219632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 219635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219641 */     GIR_RootConstrainSelectedInstOperands,
     /* 219642 */     // GIR_Coverage, 2544,
     /* 219642 */     GIR_EraseRootFromParent_Done,
     /* 219643 */   // Label 4123: @219643
     /* 219643 */   GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(219688), // Rule ID 2545 //
     /* 219648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 219651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 219656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 219665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219673 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219677 */     // (intrinsic_wo_chain:{ *:[v1i64] } 601:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FACGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 219677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE64),
     /* 219680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 219682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 219686 */     GIR_RootConstrainSelectedInstOperands,
     /* 219687 */     // GIR_Coverage, 2545,
     /* 219687 */     GIR_EraseRootFromParent_Done,
     /* 219688 */   // Label 4124: @219688
     /* 219688 */   GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(219733), // Rule ID 2550 //
     /* 219693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 219696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_suqadd),
     /* 219701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 219710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219718 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 219722 */     // (intrinsic_wo_chain:{ *:[v1i64] } 740:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)  =>  (SUQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
     /* 219722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADDv1i64),
     /* 219725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 219727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 219729 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 219731 */     GIR_RootConstrainSelectedInstOperands,
     /* 219732 */     // GIR_Coverage, 2550,
     /* 219732 */     GIR_EraseRootFromParent_Done,
     /* 219733 */   // Label 4125: @219733
     /* 219733 */   GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(219778), // Rule ID 2673 //
     /* 219738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 219746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219752 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 219755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219759 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219763 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219767 */     // (intrinsic_wo_chain:{ *:[i32] } 2082:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQINCP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 219767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_B),
     /* 219770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219776 */     GIR_RootConstrainSelectedInstOperands,
     /* 219777 */     // GIR_Coverage, 2673,
     /* 219777 */     GIR_EraseRootFromParent_Done,
     /* 219778 */   // Label 4126: @219778
     /* 219778 */   GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(219823), // Rule ID 2674 //
     /* 219783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 219791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 219800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219804 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219808 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219812 */     // (intrinsic_wo_chain:{ *:[i32] } 2082:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQINCP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 219812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_H),
     /* 219815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219819 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219821 */     GIR_RootConstrainSelectedInstOperands,
     /* 219822 */     // GIR_Coverage, 2674,
     /* 219822 */     GIR_EraseRootFromParent_Done,
     /* 219823 */   // Label 4127: @219823
     /* 219823 */   GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(219868), // Rule ID 2675 //
     /* 219828 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219831 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 219836 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 219845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219849 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219853 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219857 */     // (intrinsic_wo_chain:{ *:[i32] } 2082:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQINCP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 219857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_S),
     /* 219860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219862 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219866 */     GIR_RootConstrainSelectedInstOperands,
     /* 219867 */     // GIR_Coverage, 2675,
     /* 219867 */     GIR_EraseRootFromParent_Done,
     /* 219868 */   // Label 4128: @219868
     /* 219868 */   GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(219913), // Rule ID 2676 //
     /* 219873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n32),
     /* 219881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 219884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 219887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 219890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219894 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 219898 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219902 */     // (intrinsic_wo_chain:{ *:[i32] } 2082:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQINCP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 219902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_WP_D),
     /* 219905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219911 */     GIR_RootConstrainSelectedInstOperands,
     /* 219912 */     // GIR_Coverage, 2676,
     /* 219912 */     GIR_EraseRootFromParent_Done,
     /* 219913 */   // Label 4129: @219913
     /* 219913 */   GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(219958), // Rule ID 2677 //
     /* 219918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 219926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 219935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219943 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219947 */     // (intrinsic_wo_chain:{ *:[i64] } 1868:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (SQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 219947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_B),
     /* 219950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219952 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 219956 */     GIR_RootConstrainSelectedInstOperands,
     /* 219957 */     // GIR_Coverage, 2677,
     /* 219957 */     GIR_EraseRootFromParent_Done,
     /* 219958 */   // Label 4130: @219958
     /* 219958 */   GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(220003), // Rule ID 2678 //
     /* 219963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 219966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 219971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 219974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 219977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 219980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 219988 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 219992 */     // (intrinsic_wo_chain:{ *:[i64] } 1868:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (SQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 219992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_H),
     /* 219995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 219997 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 219999 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220001 */     GIR_RootConstrainSelectedInstOperands,
     /* 220002 */     // GIR_Coverage, 2678,
     /* 220002 */     GIR_EraseRootFromParent_Done,
     /* 220003 */   // Label 4131: @220003
     /* 220003 */   GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(220048), // Rule ID 2679 //
     /* 220008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220011 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 220016 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220019 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220022 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 220025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220029 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220033 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 220037 */     // (intrinsic_wo_chain:{ *:[i64] } 1868:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (SQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 220037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_S),
     /* 220040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 220044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220046 */     GIR_RootConstrainSelectedInstOperands,
     /* 220047 */     // GIR_Coverage, 2679,
     /* 220047 */     GIR_EraseRootFromParent_Done,
     /* 220048 */   // Label 4132: @220048
     /* 220048 */   GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(220093), // Rule ID 2680 //
     /* 220053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 220056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp_n64),
     /* 220061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 220070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220074 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220078 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 220082 */     // (intrinsic_wo_chain:{ *:[i64] } 1868:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (SQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 220082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_XP_D),
     /* 220085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 220087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 220089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220091 */     GIR_RootConstrainSelectedInstOperands,
     /* 220092 */     // GIR_Coverage, 2680,
     /* 220092 */     GIR_EraseRootFromParent_Done,
     /* 220093 */   // Label 4133: @220093
     /* 220093 */   GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(220138), // Rule ID 3904 //
     /* 220098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 220101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su0),
     /* 220106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 220109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 220112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 220115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220123 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220127 */     // (intrinsic_wo_chain:{ *:[v2i64] } 556:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512SU0:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 220127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU0),
     /* 220130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 220132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 220134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 220136 */     GIR_RootConstrainSelectedInstOperands,
     /* 220137 */     // GIR_Coverage, 3904,
     /* 220137 */     GIR_EraseRootFromParent_Done,
     /* 220138 */   // Label 4134: @220138
     /* 220138 */   GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(220183), // Rule ID 3936 //
     /* 220143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 220146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_rax1),
     /* 220151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 220154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 220157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 220160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220164 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220168 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220172 */     // (intrinsic_wo_chain:{ *:[v2i64] } 543:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (RAX1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 220172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1),
     /* 220175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 220177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 220179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 220181 */     GIR_RootConstrainSelectedInstOperands,
     /* 220182 */     // GIR_Coverage, 3936,
     /* 220182 */     GIR_EraseRootFromParent_Done,
     /* 220183 */   // Label 4135: @220183
     /* 220183 */   GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(220228), // Rule ID 3946 //
     /* 220188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 220191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4ekey),
     /* 220196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 220199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 220202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 220205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220213 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220217 */     // (intrinsic_wo_chain:{ *:[v4i32] } 566:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM4ENCKEY:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 220217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4ENCKEY),
     /* 220220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 220222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 220224 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 220226 */     GIR_RootConstrainSelectedInstOperands,
     /* 220227 */     // GIR_Coverage, 3946,
     /* 220227 */     GIR_EraseRootFromParent_Done,
     /* 220228 */   // Label 4136: @220228
     /* 220228 */   GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(220273), // Rule ID 3947 //
     /* 220233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 220236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm4e),
     /* 220241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 220244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 220247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 220250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220254 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220258 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220262 */     // (intrinsic_wo_chain:{ *:[v4i32] } 565:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM4E:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 220262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4E),
     /* 220265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 220267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 220269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 220271 */     GIR_RootConstrainSelectedInstOperands,
     /* 220272 */     // GIR_Coverage, 3947,
     /* 220272 */     GIR_EraseRootFromParent_Done,
     /* 220273 */   // Label 4137: @220273
     /* 220273 */   GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(220321), // Rule ID 3948 //
     /* 220278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 220281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 220286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 220289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 220292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 220295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220307 */     // (intrinsic_wo_chain:{ *:[v4f16] } 781:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
     /* 220307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
     /* 220310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220316 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 220319 */     GIR_RootConstrainSelectedInstOperands,
     /* 220320 */     // GIR_Coverage, 3948,
     /* 220320 */     GIR_EraseRootFromParent_Done,
     /* 220321 */   // Label 4138: @220321
     /* 220321 */   GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(220369), // Rule ID 3949 //
     /* 220326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 220329 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 220334 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 220337 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 220340 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 220343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220347 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220351 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220355 */     // (intrinsic_wo_chain:{ *:[v4f16] } 780:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
     /* 220355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f16),
     /* 220358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 220367 */     GIR_RootConstrainSelectedInstOperands,
     /* 220368 */     // GIR_Coverage, 3949,
     /* 220368 */     GIR_EraseRootFromParent_Done,
     /* 220369 */   // Label 4139: @220369
     /* 220369 */   GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(220417), // Rule ID 3950 //
     /* 220374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 220377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 220382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 220385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 220388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 220391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220399 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220403 */     // (intrinsic_wo_chain:{ *:[v8f16] } 781:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
     /* 220403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
     /* 220406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 220415 */     GIR_RootConstrainSelectedInstOperands,
     /* 220416 */     // GIR_Coverage, 3950,
     /* 220416 */     GIR_EraseRootFromParent_Done,
     /* 220417 */   // Label 4140: @220417
     /* 220417 */   GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(220465), // Rule ID 3951 //
     /* 220422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 220425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 220430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 220433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 220436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 220439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220451 */     // (intrinsic_wo_chain:{ *:[v8f16] } 780:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
     /* 220451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv8f16),
     /* 220454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 220463 */     GIR_RootConstrainSelectedInstOperands,
     /* 220464 */     // GIR_Coverage, 3951,
     /* 220464 */     GIR_EraseRootFromParent_Done,
     /* 220465 */   // Label 4141: @220465
     /* 220465 */   GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(220513), // Rule ID 3952 //
     /* 220470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 220478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 220481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 220484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 220487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220495 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220499 */     // (intrinsic_wo_chain:{ *:[v2f32] } 781:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
     /* 220499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
     /* 220502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220508 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 220511 */     GIR_RootConstrainSelectedInstOperands,
     /* 220512 */     // GIR_Coverage, 3952,
     /* 220512 */     GIR_EraseRootFromParent_Done,
     /* 220513 */   // Label 4142: @220513
     /* 220513 */   GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(220561), // Rule ID 3953 //
     /* 220518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 220526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 220529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 220532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 220535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220543 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220547 */     // (intrinsic_wo_chain:{ *:[v2f32] } 780:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
     /* 220547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f32),
     /* 220550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220554 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220556 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 220559 */     GIR_RootConstrainSelectedInstOperands,
     /* 220560 */     // GIR_Coverage, 3953,
     /* 220560 */     GIR_EraseRootFromParent_Done,
     /* 220561 */   // Label 4143: @220561
     /* 220561 */   GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(220609), // Rule ID 3954 //
     /* 220566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 220574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 220577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 220580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 220583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220591 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220595 */     // (intrinsic_wo_chain:{ *:[v4f32] } 781:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
     /* 220595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
     /* 220598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 220607 */     GIR_RootConstrainSelectedInstOperands,
     /* 220608 */     // GIR_Coverage, 3954,
     /* 220608 */     GIR_EraseRootFromParent_Done,
     /* 220609 */   // Label 4144: @220609
     /* 220609 */   GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(220657), // Rule ID 3955 //
     /* 220614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 220622 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 220625 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 220628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 220631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220635 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220639 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220643 */     // (intrinsic_wo_chain:{ *:[v4f32] } 780:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
     /* 220643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv4f32),
     /* 220646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 220655 */     GIR_RootConstrainSelectedInstOperands,
     /* 220656 */     // GIR_Coverage, 3955,
     /* 220656 */     GIR_EraseRootFromParent_Done,
     /* 220657 */   // Label 4145: @220657
     /* 220657 */   GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(220705), // Rule ID 3956 //
     /* 220662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot90),
     /* 220670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 220673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 220676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 220679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220687 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220691 */     // (intrinsic_wo_chain:{ *:[v2f64] } 781:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
     /* 220691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
     /* 220694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220698 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220700 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 220703 */     GIR_RootConstrainSelectedInstOperands,
     /* 220704 */     // GIR_Coverage, 3956,
     /* 220704 */     GIR_EraseRootFromParent_Done,
     /* 220705 */   // Label 4146: @220705
     /* 220705 */   GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(220753), // Rule ID 3957 //
     /* 220710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 220713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcadd_rot270),
     /* 220718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 220721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 220724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 220727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220735 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 220739 */     // (intrinsic_wo_chain:{ *:[v2f64] } 780:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
     /* 220739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCADDv2f64),
     /* 220742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 220751 */     GIR_RootConstrainSelectedInstOperands,
     /* 220752 */     // GIR_Coverage, 3957,
     /* 220752 */     GIR_EraseRootFromParent_Done,
     /* 220753 */   // Label 4147: @220753
     /* 220753 */   GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(220795), // Rule ID 4025 //
     /* 220758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
     /* 220763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 220772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220780 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220784 */     // (intrinsic_wo_chain:{ *:[i32] } 2225:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 220784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVWr),
     /* 220787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220791 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220793 */     GIR_RootConstrainSelectedInstOperands,
     /* 220794 */     // GIR_Coverage, 4025,
     /* 220794 */     GIR_EraseRootFromParent_Done,
     /* 220795 */   // Label 4148: @220795
     /* 220795 */   GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(220837), // Rule ID 4026 //
     /* 220800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_udiv),
     /* 220805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 220814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220822 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220826 */     // (intrinsic_wo_chain:{ *:[i64] } 2225:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 220826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVXr),
     /* 220829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220833 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220835 */     GIR_RootConstrainSelectedInstOperands,
     /* 220836 */     // GIR_Coverage, 4026,
     /* 220836 */     GIR_EraseRootFromParent_Done,
     /* 220837 */   // Label 4149: @220837
     /* 220837 */   GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(220879), // Rule ID 4027 //
     /* 220842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
     /* 220847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 220850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 220853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 220856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220864 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 220868 */     // (intrinsic_wo_chain:{ *:[i32] } 805:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SDIVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 220868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVWr),
     /* 220871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220877 */     GIR_RootConstrainSelectedInstOperands,
     /* 220878 */     // GIR_Coverage, 4027,
     /* 220878 */     GIR_EraseRootFromParent_Done,
     /* 220879 */   // Label 4150: @220879
     /* 220879 */   GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(220921), // Rule ID 4028 //
     /* 220884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sdiv),
     /* 220889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 220898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220906 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 220910 */     // (intrinsic_wo_chain:{ *:[i64] } 805:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SDIVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 220910 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVXr),
     /* 220913 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220915 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220917 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220919 */     GIR_RootConstrainSelectedInstOperands,
     /* 220920 */     // GIR_Coverage, 4028,
     /* 220920 */     GIR_EraseRootFromParent_Done,
     /* 220921 */   // Label 4151: @220921
     /* 220921 */   GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(220963), // Rule ID 5257 //
     /* 220926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fabd),
     /* 220931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 220940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220948 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220952 */     // (intrinsic_wo_chain:{ *:[v1f64] } 600:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FABD64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 220952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 220955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 220957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 220959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 220961 */     GIR_RootConstrainSelectedInstOperands,
     /* 220962 */     // GIR_Coverage, 5257,
     /* 220962 */     GIR_EraseRootFromParent_Done,
     /* 220963 */   // Label 4152: @220963
     /* 220963 */   GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(221008), // Rule ID 5261 //
     /* 220968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 220971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 220976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 220979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 220982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 220985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220989 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220993 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 220997 */     // (intrinsic_wo_chain:{ *:[v1i64] } 602:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FACGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 220997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT64),
     /* 221000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221004 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221006 */     GIR_RootConstrainSelectedInstOperands,
     /* 221007 */     // GIR_Coverage, 5261,
     /* 221007 */     GIR_EraseRootFromParent_Done,
     /* 221008 */   // Label 4153: @221008
     /* 221008 */   GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(221053), // Rule ID 5265 //
     /* 221013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmulx),
     /* 221021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221034 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221038 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221042 */     // (intrinsic_wo_chain:{ *:[v1f64] } 635:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMULX64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 221042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX64),
     /* 221045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221047 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221049 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221051 */     GIR_RootConstrainSelectedInstOperands,
     /* 221052 */     // GIR_Coverage, 5265,
     /* 221052 */     GIR_EraseRootFromParent_Done,
     /* 221053 */   // Label 4154: @221053
     /* 221053 */   GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(221098), // Rule ID 5266 //
     /* 221058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221061 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frecps),
     /* 221066 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221069 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221072 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221075 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221083 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221087 */     // (intrinsic_wo_chain:{ *:[v1f64] } 658:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FRECPS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 221087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRECPS64),
     /* 221090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221092 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221094 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221096 */     GIR_RootConstrainSelectedInstOperands,
     /* 221097 */     // GIR_Coverage, 5266,
     /* 221097 */     GIR_EraseRootFromParent_Done,
     /* 221098 */   // Label 4155: @221098
     /* 221098 */   GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(221143), // Rule ID 5267 //
     /* 221103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_frsqrts),
     /* 221111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221120 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221128 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221132 */     // (intrinsic_wo_chain:{ *:[v1f64] } 665:{ *:[iPTR] }, FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FRSQRTS64:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 221132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FRSQRTS64),
     /* 221135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221137 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221141 */     GIR_RootConstrainSelectedInstOperands,
     /* 221142 */     // GIR_Coverage, 5267,
     /* 221142 */     GIR_EraseRootFromParent_Done,
     /* 221143 */   // Label 4156: @221143
     /* 221143 */   GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(221188), // Rule ID 5269 //
     /* 221148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221151 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 221156 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221159 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221162 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221173 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221177 */     // (intrinsic_wo_chain:{ *:[i64] } 716:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i64),
     /* 221180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221186 */     GIR_RootConstrainSelectedInstOperands,
     /* 221187 */     // GIR_Coverage, 5269,
     /* 221187 */     GIR_EraseRootFromParent_Done,
     /* 221188 */   // Label 4157: @221188
     /* 221188 */   GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(221233), // Rule ID 5270 //
     /* 221193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrshl),
     /* 221201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221214 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221218 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221222 */     // (intrinsic_wo_chain:{ *:[i32] } 716:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHLv1i32),
     /* 221225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221227 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221229 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221231 */     GIR_RootConstrainSelectedInstOperands,
     /* 221232 */     // GIR_Coverage, 5270,
     /* 221232 */     GIR_EraseRootFromParent_Done,
     /* 221233 */   // Label 4158: @221233
     /* 221233 */   GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(221278), // Rule ID 5273 //
     /* 221238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 221246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221263 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221267 */     // (intrinsic_wo_chain:{ *:[i64] } 719:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i64),
     /* 221270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221274 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221276 */     GIR_RootConstrainSelectedInstOperands,
     /* 221277 */     // GIR_Coverage, 5273,
     /* 221277 */     GIR_EraseRootFromParent_Done,
     /* 221278 */   // Label 4159: @221278
     /* 221278 */   GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(221323), // Rule ID 5274 //
     /* 221283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqshl),
     /* 221291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221304 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221308 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221312 */     // (intrinsic_wo_chain:{ *:[i32] } 719:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLv1i32),
     /* 221315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221321 */     GIR_RootConstrainSelectedInstOperands,
     /* 221322 */     // GIR_Coverage, 5274,
     /* 221322 */     GIR_EraseRootFromParent_Done,
     /* 221323 */   // Label 4160: @221323
     /* 221323 */   GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(221368), // Rule ID 5277 //
     /* 221328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221331 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 221336 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221349 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221353 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221357 */     // (intrinsic_wo_chain:{ *:[i64] } 723:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
     /* 221360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221366 */     GIR_RootConstrainSelectedInstOperands,
     /* 221367 */     // GIR_Coverage, 5277,
     /* 221367 */     GIR_EraseRootFromParent_Done,
     /* 221368 */   // Label 4161: @221368
     /* 221368 */   GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(221413), // Rule ID 5278 //
     /* 221373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqsub),
     /* 221381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221394 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221398 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221402 */     // (intrinsic_wo_chain:{ *:[i32] } 723:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i32),
     /* 221405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221409 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221411 */     GIR_RootConstrainSelectedInstOperands,
     /* 221412 */     // GIR_Coverage, 5278,
     /* 221412 */     GIR_EraseRootFromParent_Done,
     /* 221413 */   // Label 4162: @221413
     /* 221413 */   GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(221458), // Rule ID 5281 //
     /* 221418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
     /* 221426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221439 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221443 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221447 */     // (intrinsic_wo_chain:{ *:[i64] } 764:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQADDv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
     /* 221450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221454 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221456 */     GIR_RootConstrainSelectedInstOperands,
     /* 221457 */     // GIR_Coverage, 5281,
     /* 221457 */     GIR_EraseRootFromParent_Done,
     /* 221458 */   // Label 4163: @221458
     /* 221458 */   GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(221503), // Rule ID 5282 //
     /* 221463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqadd),
     /* 221471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221488 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221492 */     // (intrinsic_wo_chain:{ *:[i32] } 764:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQADDv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i32),
     /* 221495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221501 */     GIR_RootConstrainSelectedInstOperands,
     /* 221502 */     // GIR_Coverage, 5282,
     /* 221502 */     GIR_EraseRootFromParent_Done,
     /* 221503 */   // Label 4164: @221503
     /* 221503 */   GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(221548), // Rule ID 5285 //
     /* 221508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 221516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221533 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221537 */     // (intrinsic_wo_chain:{ *:[i64] } 765:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i64),
     /* 221540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221542 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221544 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221546 */     GIR_RootConstrainSelectedInstOperands,
     /* 221547 */     // GIR_Coverage, 5285,
     /* 221547 */     GIR_EraseRootFromParent_Done,
     /* 221548 */   // Label 4165: @221548
     /* 221548 */   GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(221593), // Rule ID 5286 //
     /* 221553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqrshl),
     /* 221561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221578 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221582 */     // (intrinsic_wo_chain:{ *:[i32] } 765:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQRSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHLv1i32),
     /* 221585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221587 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221589 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221591 */     GIR_RootConstrainSelectedInstOperands,
     /* 221592 */     // GIR_Coverage, 5286,
     /* 221592 */     GIR_EraseRootFromParent_Done,
     /* 221593 */   // Label 4166: @221593
     /* 221593 */   GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(221638), // Rule ID 5289 //
     /* 221598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 221606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221619 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221623 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221627 */     // (intrinsic_wo_chain:{ *:[i64] } 767:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i64),
     /* 221630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221636 */     GIR_RootConstrainSelectedInstOperands,
     /* 221637 */     // GIR_Coverage, 5289,
     /* 221637 */     GIR_EraseRootFromParent_Done,
     /* 221638 */   // Label 4167: @221638
     /* 221638 */   GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(221683), // Rule ID 5290 //
     /* 221643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqshl),
     /* 221651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221668 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221672 */     // (intrinsic_wo_chain:{ *:[i32] } 767:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQSHLv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHLv1i32),
     /* 221675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221679 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221681 */     GIR_RootConstrainSelectedInstOperands,
     /* 221682 */     // GIR_Coverage, 5290,
     /* 221682 */     GIR_EraseRootFromParent_Done,
     /* 221683 */   // Label 4168: @221683
     /* 221683 */   GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(221728), // Rule ID 5293 //
     /* 221688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
     /* 221696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221709 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221713 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221717 */     // (intrinsic_wo_chain:{ *:[i64] } 769:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (UQSUBv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 221717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
     /* 221720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221722 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221724 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221726 */     GIR_RootConstrainSelectedInstOperands,
     /* 221727 */     // GIR_Coverage, 5293,
     /* 221727 */     GIR_EraseRootFromParent_Done,
     /* 221728 */   // Label 4169: @221728
     /* 221728 */   GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(221773), // Rule ID 5294 //
     /* 221733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221736 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uqsub),
     /* 221741 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221744 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 221747 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 221750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221754 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221758 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221762 */     // (intrinsic_wo_chain:{ *:[i32] } 769:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (UQSUBv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 221762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i32),
     /* 221765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 221767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221769 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 221771 */     GIR_RootConstrainSelectedInstOperands,
     /* 221772 */     // GIR_Coverage, 5294,
     /* 221772 */     GIR_EraseRootFromParent_Done,
     /* 221773 */   // Label 4170: @221773
     /* 221773 */   GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(221818), // Rule ID 5315 //
     /* 221778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 221781 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usqadd),
     /* 221786 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 221789 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 221792 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 221795 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221799 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221803 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221807 */     // (intrinsic_wo_chain:{ *:[v1i64] } 779:{ *:[iPTR] }, FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)  =>  (USQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn)
     /* 221807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADDv1i64),
     /* 221810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 221814 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221816 */     GIR_RootConstrainSelectedInstOperands,
     /* 221817 */     // GIR_Coverage, 5315,
     /* 221817 */     GIR_EraseRootFromParent_Done,
     /* 221818 */   // Label 4171: @221818
     /* 221818 */   GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(221860), // Rule ID 6183 //
     /* 221823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
     /* 221828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 221831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 221834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 221837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221841 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221845 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 221849 */     // (intrinsic_wo_chain:{ *:[v8i8] } 741:{ *:[iPTR] }, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)  =>  (TBLv8i8One:{ *:[v8i8] } VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
     /* 221849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv8i8One),
     /* 221852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 221854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 221856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ri
     /* 221858 */     GIR_RootConstrainSelectedInstOperands,
     /* 221859 */     // GIR_Coverage, 6183,
     /* 221859 */     GIR_EraseRootFromParent_Done,
     /* 221860 */   // Label 4172: @221860
     /* 221860 */   GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(221902), // Rule ID 6184 //
     /* 221865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbl1),
     /* 221870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 221873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 221876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 221879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221883 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221887 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 221891 */     // (intrinsic_wo_chain:{ *:[v16i8] } 741:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)  =>  (TBLv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
     /* 221891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLv16i8One),
     /* 221894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 221896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Ri
     /* 221898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 221900 */     GIR_RootConstrainSelectedInstOperands,
     /* 221901 */     // GIR_Coverage, 6184,
     /* 221901 */     GIR_EraseRootFromParent_Done,
     /* 221902 */   // Label 4173: @221902
     /* 221902 */   GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(221999), // Rule ID 6925 //
     /* 221907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facge),
     /* 221912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 221915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 221918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 221921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 221929 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 221933 */     // (intrinsic_wo_chain:{ *:[i32] } 601:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGE16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
     /* 221933 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 221936 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGE16),
     /* 221940 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 221945 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 221949 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 221953 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 221955 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 221958 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 221962 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 221967 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 221969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 221972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 221974 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 221977 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 221980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 221983 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221988 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 221993 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 221998 */     // GIR_Coverage, 6925,
     /* 221998 */     GIR_EraseRootFromParent_Done,
     /* 221999 */   // Label 4174: @221999
     /* 221999 */   GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(222096), // Rule ID 6926 //
     /* 222004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_facgt),
     /* 222009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 222015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 222018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222022 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 222026 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 222030 */     // (intrinsic_wo_chain:{ *:[i32] } 602:{ *:[iPTR] }, FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), (FACGT16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm), hsub:{ *:[i32] })
     /* 222030 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 222033 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FACGT16),
     /* 222037 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 222042 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 222046 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 222050 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 222052 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 222055 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 222059 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 222064 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 222066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 222069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 222071 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 222074 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 222077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 222080 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222085 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 222090 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 222095 */     // GIR_Coverage, 6926,
     /* 222095 */     GIR_EraseRootFromParent_Done,
     /* 222096 */   // Label 4175: @222096
     /* 222096 */   GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(222138), // Rule ID 7585 //
     /* 222101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sshl),
     /* 222106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 222115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222123 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222127 */     // (intrinsic_wo_chain:{ *:[i64] } 728:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 222127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLv1i64),
     /* 222130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 222132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 222136 */     GIR_RootConstrainSelectedInstOperands,
     /* 222137 */     // GIR_Coverage, 7585,
     /* 222137 */     GIR_EraseRootFromParent_Done,
     /* 222138 */   // Label 4176: @222138
     /* 222138 */   GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(222180), // Rule ID 7586 //
     /* 222143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ushl),
     /* 222148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 222157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222165 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222169 */     // (intrinsic_wo_chain:{ *:[i64] } 776:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (USHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 222169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLv1i64),
     /* 222172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 222174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 222178 */     GIR_RootConstrainSelectedInstOperands,
     /* 222179 */     // GIR_Coverage, 7586,
     /* 222179 */     GIR_EraseRootFromParent_Done,
     /* 222180 */   // Label 4177: @222180
     /* 222180 */   GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(222222), // Rule ID 7587 //
     /* 222185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_srshl),
     /* 222190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 222199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222211 */     // (intrinsic_wo_chain:{ *:[i64] } 727:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (SRSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 222211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHLv1i64),
     /* 222214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 222216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 222220 */     GIR_RootConstrainSelectedInstOperands,
     /* 222221 */     // GIR_Coverage, 7587,
     /* 222221 */     GIR_EraseRootFromParent_Done,
     /* 222222 */   // Label 4178: @222222
     /* 222222 */   GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(222264), // Rule ID 7588 //
     /* 222227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_urshl),
     /* 222232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 222241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222249 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 222253 */     // (intrinsic_wo_chain:{ *:[i64] } 773:{ *:[iPTR] }, FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)  =>  (URSHLv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i64] }:$Rm)
     /* 222253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHLv1i64),
     /* 222256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 222258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 222262 */     GIR_RootConstrainSelectedInstOperands,
     /* 222263 */     // GIR_Coverage, 7588,
     /* 222263 */     GIR_EraseRootFromParent_Done,
     /* 222264 */   // Label 4179: @222264
     /* 222264 */   GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(222312), // Rule ID 7628 //
     /* 222269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_blend),
     /* 222274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 222283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222287 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222291 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222295 */     // (intrinsic_wo_chain:{ *:[i64] } 306:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn)  =>  (BFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, 16:{ *:[i64] }, 15:{ *:[i64] })
     /* 222295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BFMXri),
     /* 222298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 222300 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 222302 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 222304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /* 222307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 222310 */     GIR_RootConstrainSelectedInstOperands,
     /* 222311 */     // GIR_Coverage, 7628,
     /* 222311 */     GIR_EraseRootFromParent_Done,
     /* 222312 */   // Label 4180: @222312
     /* 222312 */   GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(222357), // Rule ID 10767 //
     /* 222317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 222325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222331 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 222334 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222338 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222342 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222346 */     // (intrinsic_wo_chain:{ *:[i64] } 2083:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQINCP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_B),
     /* 222349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222351 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222353 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222355 */     GIR_RootConstrainSelectedInstOperands,
     /* 222356 */     // GIR_Coverage, 10767,
     /* 222356 */     GIR_EraseRootFromParent_Done,
     /* 222357 */   // Label 4181: @222357
     /* 222357 */   GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(222402), // Rule ID 10768 //
     /* 222362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222365 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 222370 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222373 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222376 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 222379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222383 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222387 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222391 */     // (intrinsic_wo_chain:{ *:[i64] } 2083:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQINCP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_H),
     /* 222394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222396 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222400 */     GIR_RootConstrainSelectedInstOperands,
     /* 222401 */     // GIR_Coverage, 10768,
     /* 222401 */     GIR_EraseRootFromParent_Done,
     /* 222402 */   // Label 4182: @222402
     /* 222402 */   GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(222447), // Rule ID 10769 //
     /* 222407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 222415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222421 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 222424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222428 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222432 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222436 */     // (intrinsic_wo_chain:{ *:[i64] } 2083:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQINCP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_S),
     /* 222439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222441 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222443 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222445 */     GIR_RootConstrainSelectedInstOperands,
     /* 222446 */     // GIR_Coverage, 10769,
     /* 222446 */     GIR_EraseRootFromParent_Done,
     /* 222447 */   // Label 4183: @222447
     /* 222447 */   GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(222492), // Rule ID 10770 //
     /* 222452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp_n64),
     /* 222460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 222469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222481 */     // (intrinsic_wo_chain:{ *:[i64] } 2083:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQINCP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_XP_D),
     /* 222484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222490 */     GIR_RootConstrainSelectedInstOperands,
     /* 222491 */     // GIR_Coverage, 10770,
     /* 222491 */     GIR_EraseRootFromParent_Done,
     /* 222492 */   // Label 4184: @222492
     /* 222492 */   GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(222537), // Rule ID 10779 //
     /* 222497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 222505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 222514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222518 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222522 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222526 */     // (intrinsic_wo_chain:{ *:[i64] } 1834:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (SQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_B),
     /* 222529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222531 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222535 */     GIR_RootConstrainSelectedInstOperands,
     /* 222536 */     // GIR_Coverage, 10779,
     /* 222536 */     GIR_EraseRootFromParent_Done,
     /* 222537 */   // Label 4185: @222537
     /* 222537 */   GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(222582), // Rule ID 10780 //
     /* 222542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 222550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 222559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222563 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222567 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222571 */     // (intrinsic_wo_chain:{ *:[i64] } 1834:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (SQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_H),
     /* 222574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222576 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222580 */     GIR_RootConstrainSelectedInstOperands,
     /* 222581 */     // GIR_Coverage, 10780,
     /* 222581 */     GIR_EraseRootFromParent_Done,
     /* 222582 */   // Label 4186: @222582
     /* 222582 */   GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(222627), // Rule ID 10781 //
     /* 222587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 222595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 222604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222608 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222612 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222616 */     // (intrinsic_wo_chain:{ *:[i64] } 1834:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (SQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_S),
     /* 222619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222621 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222625 */     GIR_RootConstrainSelectedInstOperands,
     /* 222626 */     // GIR_Coverage, 10781,
     /* 222626 */     GIR_EraseRootFromParent_Done,
     /* 222627 */   // Label 4187: @222627
     /* 222627 */   GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(222672), // Rule ID 10782 //
     /* 222632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp_n64),
     /* 222640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 222649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222657 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222661 */     // (intrinsic_wo_chain:{ *:[i64] } 1834:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (SQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_XP_D),
     /* 222664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222668 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222670 */     GIR_RootConstrainSelectedInstOperands,
     /* 222671 */     // GIR_Coverage, 10782,
     /* 222671 */     GIR_EraseRootFromParent_Done,
     /* 222672 */   // Label 4188: @222672
     /* 222672 */   GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(222717), // Rule ID 10783 //
     /* 222677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 222685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222691 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 222694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222702 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222706 */     // (intrinsic_wo_chain:{ *:[i32] } 2068:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQDECP_WP_B:{ *:[i32] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 222706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_B),
     /* 222709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222715 */     GIR_RootConstrainSelectedInstOperands,
     /* 222716 */     // GIR_Coverage, 10783,
     /* 222716 */     GIR_EraseRootFromParent_Done,
     /* 222717 */   // Label 4189: @222717
     /* 222717 */   GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(222762), // Rule ID 10784 //
     /* 222722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 222730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 222739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222747 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222751 */     // (intrinsic_wo_chain:{ *:[i32] } 2068:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQDECP_WP_H:{ *:[i32] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 222751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_H),
     /* 222754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222756 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222760 */     GIR_RootConstrainSelectedInstOperands,
     /* 222761 */     // GIR_Coverage, 10784,
     /* 222761 */     GIR_EraseRootFromParent_Done,
     /* 222762 */   // Label 4190: @222762
     /* 222762 */   GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(222807), // Rule ID 10785 //
     /* 222767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 222775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 222784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222792 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222796 */     // (intrinsic_wo_chain:{ *:[i32] } 2068:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQDECP_WP_S:{ *:[i32] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 222796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_S),
     /* 222799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222803 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222805 */     GIR_RootConstrainSelectedInstOperands,
     /* 222806 */     // GIR_Coverage, 10785,
     /* 222806 */     GIR_EraseRootFromParent_Done,
     /* 222807 */   // Label 4191: @222807
     /* 222807 */   GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(222852), // Rule ID 10786 //
     /* 222812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n32),
     /* 222820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 222823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 222826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 222829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 222837 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222841 */     // (intrinsic_wo_chain:{ *:[i32] } 2068:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQDECP_WP_D:{ *:[i32] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i32] }:$Rn)
     /* 222841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_WP_D),
     /* 222844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222848 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222850 */     GIR_RootConstrainSelectedInstOperands,
     /* 222851 */     // GIR_Coverage, 10786,
     /* 222851 */     GIR_EraseRootFromParent_Done,
     /* 222852 */   // Label 4192: @222852
     /* 222852 */   GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(222897), // Rule ID 10787 //
     /* 222857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 222865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 222874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222882 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222886 */     // (intrinsic_wo_chain:{ *:[i64] } 2069:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (UQDECP_XP_B:{ *:[i64] } PPRAny:{ *:[nxv16i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_B),
     /* 222889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222891 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222893 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222895 */     GIR_RootConstrainSelectedInstOperands,
     /* 222896 */     // GIR_Coverage, 10787,
     /* 222896 */     GIR_EraseRootFromParent_Done,
     /* 222897 */   // Label 4193: @222897
     /* 222897 */   GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(222942), // Rule ID 10788 //
     /* 222902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 222910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 222919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222927 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222931 */     // (intrinsic_wo_chain:{ *:[i64] } 2069:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv8i1] }:$Pg)  =>  (UQDECP_XP_H:{ *:[i64] } PPRAny:{ *:[nxv8i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_H),
     /* 222934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222940 */     GIR_RootConstrainSelectedInstOperands,
     /* 222941 */     // GIR_Coverage, 10788,
     /* 222941 */     GIR_EraseRootFromParent_Done,
     /* 222942 */   // Label 4194: @222942
     /* 222942 */   GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(222987), // Rule ID 10789 //
     /* 222947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 222955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 222958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 222961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 222964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222968 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 222972 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 222976 */     // (intrinsic_wo_chain:{ *:[i64] } 2069:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv4i1] }:$Pg)  =>  (UQDECP_XP_S:{ *:[i64] } PPRAny:{ *:[nxv4i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 222976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_S),
     /* 222979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 222981 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 222983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 222985 */     GIR_RootConstrainSelectedInstOperands,
     /* 222986 */     // GIR_Coverage, 10789,
     /* 222986 */     GIR_EraseRootFromParent_Done,
     /* 222987 */   // Label 4195: @222987
     /* 222987 */   GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(223032), // Rule ID 10790 //
     /* 222992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 222995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp_n64),
     /* 223000 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 223003 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 223006 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 223009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 223013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 223017 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223021 */     // (intrinsic_wo_chain:{ *:[i64] } 2069:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, PPRAny:{ *:[nxv2i1] }:$Pg)  =>  (UQDECP_XP_D:{ *:[i64] } PPRAny:{ *:[nxv2i1] }:$Pg, ?:{ *:[i64] }:$Rn)
     /* 223021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_XP_D),
     /* 223024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 223026 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pg
     /* 223028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 223030 */     GIR_RootConstrainSelectedInstOperands,
     /* 223031 */     // GIR_Coverage, 10790,
     /* 223031 */     GIR_EraseRootFromParent_Done,
     /* 223032 */   // Label 4196: @223032
     /* 223032 */   GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(223078), // Rule ID 126 //
     /* 223037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 223040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gmi),
     /* 223045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 223048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 223051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 223055 */     // MIs[0] Rn
     /* 223055 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 223059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 223063 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 223067 */     // (intrinsic_wo_chain:{ *:[i64] } 579:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (GMI:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 223067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GMI),
     /* 223070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 223072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 223074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 223076 */     GIR_RootConstrainSelectedInstOperands,
     /* 223077 */     // GIR_Coverage, 126,
     /* 223077 */     GIR_EraseRootFromParent_Done,
     /* 223078 */   // Label 4197: @223078
     /* 223078 */   GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(223125), // Rule ID 127 //
     /* 223083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 223086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_subp),
     /* 223091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 223094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 223098 */     // MIs[0] Rn
     /* 223098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 223102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 223106 */     // MIs[0] Rm
     /* 223106 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 223110 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 223114 */     // (intrinsic_wo_chain:{ *:[i64] } 1265:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (SUBP:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)
     /* 223114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBP),
     /* 223117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 223119 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 223121 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 223123 */     GIR_RootConstrainSelectedInstOperands,
     /* 223124 */     // GIR_Coverage, 127,
     /* 223124 */     GIR_EraseRootFromParent_Done,
     /* 223125 */   // Label 4198: @223125
     /* 223125 */   GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(223162), // Rule ID 2433 //
     /* 223130 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223133 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b16),
     /* 223138 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223141 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223144 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223151 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2211:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
     /* 223154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223160 */     GIR_RootConstrainSelectedInstOperands,
     /* 223161 */     // GIR_Coverage, 2433,
     /* 223161 */     GIR_EraseRootFromParent_Done,
     /* 223162 */   // Label 4199: @223162
     /* 223162 */   GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(223199), // Rule ID 2434 //
     /* 223167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b32),
     /* 223175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223188 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2212:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
     /* 223191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223195 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223197 */     GIR_RootConstrainSelectedInstOperands,
     /* 223198 */     // GIR_Coverage, 2434,
     /* 223198 */     GIR_EraseRootFromParent_Done,
     /* 223199 */   // Label 4200: @223199
     /* 223199 */   GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(223236), // Rule ID 2435 //
     /* 223204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1_b64),
     /* 223212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223225 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2213:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
     /* 223228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223230 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223232 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223234 */     GIR_RootConstrainSelectedInstOperands,
     /* 223235 */     // GIR_Coverage, 2435,
     /* 223235 */     GIR_EraseRootFromParent_Done,
     /* 223236 */   // Label 4201: @223236
     /* 223236 */   GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(223273), // Rule ID 2437 //
     /* 223241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b16),
     /* 223249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223262 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2216:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
     /* 223265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223271 */     GIR_RootConstrainSelectedInstOperands,
     /* 223272 */     // GIR_Coverage, 2437,
     /* 223272 */     GIR_EraseRootFromParent_Done,
     /* 223273 */   // Label 4202: @223273
     /* 223273 */   GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(223310), // Rule ID 2438 //
     /* 223278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b32),
     /* 223286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223299 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2217:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
     /* 223302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223308 */     GIR_RootConstrainSelectedInstOperands,
     /* 223309 */     // GIR_Coverage, 2438,
     /* 223309 */     GIR_EraseRootFromParent_Done,
     /* 223310 */   // Label 4203: @223310
     /* 223310 */   GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(223347), // Rule ID 2439 //
     /* 223315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223318 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2_b64),
     /* 223323 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223326 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223329 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223332 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223336 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2218:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
     /* 223339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223343 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223345 */     GIR_RootConstrainSelectedInstOperands,
     /* 223346 */     // GIR_Coverage, 2439,
     /* 223346 */     GIR_EraseRootFromParent_Done,
     /* 223347 */   // Label 4204: @223347
     /* 223347 */   GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(223384), // Rule ID 2441 //
     /* 223352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b16),
     /* 223360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223373 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2137:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 223376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223378 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223382 */     GIR_RootConstrainSelectedInstOperands,
     /* 223383 */     // GIR_Coverage, 2441,
     /* 223383 */     GIR_EraseRootFromParent_Done,
     /* 223384 */   // Label 4205: @223384
     /* 223384 */   GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(223421), // Rule ID 2442 //
     /* 223389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b32),
     /* 223397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223403 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223406 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223410 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2138:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 223413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223417 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223419 */     GIR_RootConstrainSelectedInstOperands,
     /* 223420 */     // GIR_Coverage, 2442,
     /* 223420 */     GIR_EraseRootFromParent_Done,
     /* 223421 */   // Label 4206: @223421
     /* 223421 */   GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(223458), // Rule ID 2443 //
     /* 223426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223429 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1_b64),
     /* 223434 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223437 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223440 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223447 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2139:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 223450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223454 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223456 */     GIR_RootConstrainSelectedInstOperands,
     /* 223457 */     // GIR_Coverage, 2443,
     /* 223457 */     GIR_EraseRootFromParent_Done,
     /* 223458 */   // Label 4207: @223458
     /* 223458 */   GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(223495), // Rule ID 2445 //
     /* 223463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b16),
     /* 223471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223484 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2142:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
     /* 223487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223489 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223491 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223493 */     GIR_RootConstrainSelectedInstOperands,
     /* 223494 */     // GIR_Coverage, 2445,
     /* 223494 */     GIR_EraseRootFromParent_Done,
     /* 223495 */   // Label 4208: @223495
     /* 223495 */   GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(223532), // Rule ID 2446 //
     /* 223500 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223503 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b32),
     /* 223508 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223521 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2143:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
     /* 223524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223528 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223530 */     GIR_RootConstrainSelectedInstOperands,
     /* 223531 */     // GIR_Coverage, 2446,
     /* 223531 */     GIR_EraseRootFromParent_Done,
     /* 223532 */   // Label 4209: @223532
     /* 223532 */   GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(223569), // Rule ID 2447 //
     /* 223537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2_b64),
     /* 223545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223558 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2144:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
     /* 223561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223563 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223567 */     GIR_RootConstrainSelectedInstOperands,
     /* 223568 */     // GIR_Coverage, 2447,
     /* 223568 */     GIR_EraseRootFromParent_Done,
     /* 223569 */   // Label 4210: @223569
     /* 223569 */   GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(223606), // Rule ID 2449 //
     /* 223574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b16),
     /* 223582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223595 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1977:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
     /* 223598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223604 */     GIR_RootConstrainSelectedInstOperands,
     /* 223605 */     // GIR_Coverage, 2449,
     /* 223605 */     GIR_EraseRootFromParent_Done,
     /* 223606 */   // Label 4211: @223606
     /* 223606 */   GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(223643), // Rule ID 2450 //
     /* 223611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b32),
     /* 223619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223632 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1978:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
     /* 223635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223641 */     GIR_RootConstrainSelectedInstOperands,
     /* 223642 */     // GIR_Coverage, 2450,
     /* 223642 */     GIR_EraseRootFromParent_Done,
     /* 223643 */   // Label 4212: @223643
     /* 223643 */   GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(223680), // Rule ID 2451 //
     /* 223648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1_b64),
     /* 223656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223669 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1979:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
     /* 223672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223676 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223678 */     GIR_RootConstrainSelectedInstOperands,
     /* 223679 */     // GIR_Coverage, 2451,
     /* 223679 */     GIR_EraseRootFromParent_Done,
     /* 223680 */   // Label 4213: @223680
     /* 223680 */   GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(223717), // Rule ID 2453 //
     /* 223685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b16),
     /* 223693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223706 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1982:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_H:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
     /* 223709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223713 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223715 */     GIR_RootConstrainSelectedInstOperands,
     /* 223716 */     // GIR_Coverage, 2453,
     /* 223716 */     GIR_EraseRootFromParent_Done,
     /* 223717 */   // Label 4214: @223717
     /* 223717 */   GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(223754), // Rule ID 2454 //
     /* 223722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b32),
     /* 223730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223743 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1983:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_S:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
     /* 223746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223748 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223750 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223752 */     GIR_RootConstrainSelectedInstOperands,
     /* 223753 */     // GIR_Coverage, 2454,
     /* 223753 */     GIR_EraseRootFromParent_Done,
     /* 223754 */   // Label 4215: @223754
     /* 223754 */   GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(223791), // Rule ID 2455 //
     /* 223759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2_b64),
     /* 223767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223780 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1984:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_D:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 223780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
     /* 223783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 223785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 223787 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 223789 */     GIR_RootConstrainSelectedInstOperands,
     /* 223790 */     // GIR_Coverage, 2455,
     /* 223790 */     GIR_EraseRootFromParent_Done,
     /* 223791 */   // Label 4216: @223791
     /* 223791 */   GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(223828), // Rule ID 2456 //
     /* 223796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 223799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histseg),
     /* 223804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 223807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 223810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 223813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 223817 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1596:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (HISTSEG_ZZZ:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)
     /* 223817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTSEG_ZZZ),
     /* 223820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 223822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 223824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 223826 */     GIR_RootConstrainSelectedInstOperands,
     /* 223827 */     // GIR_Coverage, 2456,
     /* 223827 */     GIR_EraseRootFromParent_Done,
     /* 223828 */   // Label 4217: @223828
     /* 223828 */   GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(223868), // Rule ID 2660 //
     /* 223833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pfirst),
     /* 223841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223854 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1676:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (PFIRST_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 223854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PFIRST_B),
     /* 223857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 223859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 223861 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 223863 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 223866 */     GIR_RootConstrainSelectedInstOperands,
     /* 223867 */     // GIR_Coverage, 2660,
     /* 223867 */     GIR_EraseRootFromParent_Done,
     /* 223868 */   // Label 4218: @223868
     /* 223868 */   GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(223908), // Rule ID 2661 //
     /* 223873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 223881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 223884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 223887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 223890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223894 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1686:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (PNEXT_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 223894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_B),
     /* 223897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 223899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 223901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 223903 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 223906 */     GIR_RootConstrainSelectedInstOperands,
     /* 223907 */     // GIR_Coverage, 2661,
     /* 223907 */     GIR_EraseRootFromParent_Done,
     /* 223908 */   // Label 4219: @223908
     /* 223908 */   GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(223948), // Rule ID 2662 //
     /* 223913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 223921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 223924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 223927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 223930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223934 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1686:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (PNEXT_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 223934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_H),
     /* 223937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 223939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 223941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 223943 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 223946 */     GIR_RootConstrainSelectedInstOperands,
     /* 223947 */     // GIR_Coverage, 2662,
     /* 223947 */     GIR_EraseRootFromParent_Done,
     /* 223948 */   // Label 4220: @223948
     /* 223948 */   GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(223988), // Rule ID 2663 //
     /* 223953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 223961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 223964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 223967 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 223970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 223974 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1686:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (PNEXT_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 223974 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_S),
     /* 223977 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 223979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 223981 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 223983 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 223986 */     GIR_RootConstrainSelectedInstOperands,
     /* 223987 */     // GIR_Coverage, 2663,
     /* 223987 */     GIR_EraseRootFromParent_Done,
     /* 223988 */   // Label 4221: @223988
     /* 223988 */   GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(224028), // Rule ID 2664 //
     /* 223993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 223996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pnext),
     /* 224001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 224004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 224010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 224014 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1686:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (PNEXT_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 224014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PNEXT_D),
     /* 224017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdn]
     /* 224019 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224021 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224023 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 224026 */     GIR_RootConstrainSelectedInstOperands,
     /* 224027 */     // GIR_Coverage, 2664,
     /* 224027 */     GIR_EraseRootFromParent_Done,
     /* 224028 */   // Label 4222: @224028
     /* 224028 */   GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(224065), // Rule ID 2681 //
     /* 224033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 224041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 224047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 224050 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224054 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1866:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 224054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_H),
     /* 224057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224061 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224063 */     GIR_RootConstrainSelectedInstOperands,
     /* 224064 */     // GIR_Coverage, 2681,
     /* 224064 */     GIR_EraseRootFromParent_Done,
     /* 224065 */   // Label 4223: @224065
     /* 224065 */   GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(224102), // Rule ID 2682 //
     /* 224070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 224078 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 224087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224091 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1866:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 224091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_S),
     /* 224094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224100 */     GIR_RootConstrainSelectedInstOperands,
     /* 224101 */     // GIR_Coverage, 2682,
     /* 224101 */     GIR_EraseRootFromParent_Done,
     /* 224102 */   // Label 4224: @224102
     /* 224102 */   GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(224139), // Rule ID 2683 //
     /* 224107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincp),
     /* 224115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 224121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 224124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224128 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1866:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 224128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCP_ZP_D),
     /* 224131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 224133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224135 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224137 */     GIR_RootConstrainSelectedInstOperands,
     /* 224138 */     // GIR_Coverage, 2683,
     /* 224138 */     GIR_EraseRootFromParent_Done,
     /* 224139 */   // Label 4225: @224139
     /* 224139 */   GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(224176), // Rule ID 2684 //
     /* 224144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 224152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 224155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 224158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 224161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 224165 */     // (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (CNTP_XPP_B:{ *:[i64] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 224165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_B),
     /* 224168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 224170 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224172 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224174 */     GIR_RootConstrainSelectedInstOperands,
     /* 224175 */     // GIR_Coverage, 2684,
     /* 224175 */     GIR_EraseRootFromParent_Done,
     /* 224176 */   // Label 4226: @224176
     /* 224176 */   GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(224213), // Rule ID 2685 //
     /* 224181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 224189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 224192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 224195 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 224198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 224202 */     // (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (CNTP_XPP_H:{ *:[i64] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 224202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_H),
     /* 224205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 224207 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224209 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224211 */     GIR_RootConstrainSelectedInstOperands,
     /* 224212 */     // GIR_Coverage, 2685,
     /* 224212 */     GIR_EraseRootFromParent_Done,
     /* 224213 */   // Label 4227: @224213
     /* 224213 */   GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(224250), // Rule ID 2686 //
     /* 224218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 224226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 224229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 224232 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 224235 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 224239 */     // (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (CNTP_XPP_S:{ *:[i64] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 224239 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_S),
     /* 224242 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 224244 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224246 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224248 */     GIR_RootConstrainSelectedInstOperands,
     /* 224249 */     // GIR_Coverage, 2686,
     /* 224249 */     GIR_EraseRootFromParent_Done,
     /* 224250 */   // Label 4228: @224250
     /* 224250 */   GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(224287), // Rule ID 2687 //
     /* 224255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 224258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cntp),
     /* 224263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 224266 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 224269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 224272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 224276 */     // (intrinsic_wo_chain:{ *:[i64] } 1366:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (CNTP_XPP_D:{ *:[i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 224276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNTP_XPP_D),
     /* 224279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 224281 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224283 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224285 */     GIR_RootConstrainSelectedInstOperands,
     /* 224286 */     // GIR_Coverage, 2687,
     /* 224286 */     GIR_EraseRootFromParent_Done,
     /* 224287 */   // Label 4229: @224287
     /* 224287 */   GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(224324), // Rule ID 2871 //
     /* 224292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 224295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 224300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224303 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 224306 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224313 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1593:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (FTSMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 224313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_H),
     /* 224316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224320 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224322 */     GIR_RootConstrainSelectedInstOperands,
     /* 224323 */     // GIR_Coverage, 2871,
     /* 224323 */     GIR_EraseRootFromParent_Done,
     /* 224324 */   // Label 4230: @224324
     /* 224324 */   GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(224361), // Rule ID 2872 //
     /* 224329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 224332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 224337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224346 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224350 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1593:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (FTSMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 224350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_S),
     /* 224353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224357 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224359 */     GIR_RootConstrainSelectedInstOperands,
     /* 224360 */     // GIR_Coverage, 2872,
     /* 224360 */     GIR_EraseRootFromParent_Done,
     /* 224361 */   // Label 4231: @224361
     /* 224361 */   GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(224398), // Rule ID 2873 //
     /* 224366 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 224369 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftsmul_x),
     /* 224374 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 224380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224387 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1593:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (FTSMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 224387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSMUL_ZZZ_D),
     /* 224390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224394 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224396 */     GIR_RootConstrainSelectedInstOperands,
     /* 224397 */     // GIR_Coverage, 2873,
     /* 224397 */     GIR_EraseRootFromParent_Done,
     /* 224398 */   // Label 4232: @224398
     /* 224398 */   GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(224435), // Rule ID 3065 //
     /* 224403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 224411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 224414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224424 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1848:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_B),
     /* 224427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224433 */     GIR_RootConstrainSelectedInstOperands,
     /* 224434 */     // GIR_Coverage, 3065,
     /* 224434 */     GIR_EraseRootFromParent_Done,
     /* 224435 */   // Label 4233: @224435
     /* 224435 */   GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(224472), // Rule ID 3066 //
     /* 224440 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 224448 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224451 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 224454 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224461 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1848:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 224461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_H),
     /* 224464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224466 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224468 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224470 */     GIR_RootConstrainSelectedInstOperands,
     /* 224471 */     // GIR_Coverage, 3066,
     /* 224471 */     GIR_EraseRootFromParent_Done,
     /* 224472 */   // Label 4234: @224472
     /* 224472 */   GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(224509), // Rule ID 3067 //
     /* 224477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 224485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224498 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1848:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 224498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_S),
     /* 224501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224503 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224507 */     GIR_RootConstrainSelectedInstOperands,
     /* 224508 */     // GIR_Coverage, 3067,
     /* 224508 */     GIR_EraseRootFromParent_Done,
     /* 224509 */   // Label 4235: @224509
     /* 224509 */   GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(224546), // Rule ID 3068 //
     /* 224514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh),
     /* 224522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 224528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224535 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1848:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 224535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZ_D),
     /* 224538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224544 */     GIR_RootConstrainSelectedInstOperands,
     /* 224545 */     // GIR_Coverage, 3068,
     /* 224545 */     GIR_EraseRootFromParent_Done,
     /* 224546 */   // Label 4236: @224546
     /* 224546 */   GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(224583), // Rule ID 3069 //
     /* 224551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224554 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmul),
     /* 224559 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 224562 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224565 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224572 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1682:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMUL_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMUL_ZZZ_B),
     /* 224575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224577 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224579 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224581 */     GIR_RootConstrainSelectedInstOperands,
     /* 224582 */     // GIR_Coverage, 3069,
     /* 224582 */     GIR_EraseRootFromParent_Done,
     /* 224583 */   // Label 4237: @224583
     /* 224583 */   GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(224620), // Rule ID 3091 //
     /* 224588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 224596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224605 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224609 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1740:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_H),
     /* 224612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224616 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224618 */     GIR_RootConstrainSelectedInstOperands,
     /* 224619 */     // GIR_Coverage, 3091,
     /* 224619 */     GIR_EraseRootFromParent_Done,
     /* 224620 */   // Label 4238: @224620
     /* 224620 */   GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(224657), // Rule ID 3092 //
     /* 224625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 224633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 224639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224646 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1740:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 224646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_S),
     /* 224649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224651 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224653 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224655 */     GIR_RootConstrainSelectedInstOperands,
     /* 224656 */     // GIR_Coverage, 3092,
     /* 224656 */     GIR_EraseRootFromParent_Done,
     /* 224657 */   // Label 4239: @224657
     /* 224657 */   GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(224694), // Rule ID 3093 //
     /* 224662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlb),
     /* 224670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224683 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1740:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 224683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLB_ZZZ_D),
     /* 224686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224688 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224690 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224692 */     GIR_RootConstrainSelectedInstOperands,
     /* 224693 */     // GIR_Coverage, 3093,
     /* 224693 */     GIR_EraseRootFromParent_Done,
     /* 224694 */   // Label 4240: @224694
     /* 224694 */   GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(224731), // Rule ID 3097 //
     /* 224699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 224702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 224707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 224713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224720 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1684:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (PMULLB_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 224720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_Q),
     /* 224723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224725 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224727 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224729 */     GIR_RootConstrainSelectedInstOperands,
     /* 224730 */     // GIR_Coverage, 3097,
     /* 224730 */     GIR_EraseRootFromParent_Done,
     /* 224731 */   // Label 4241: @224731
     /* 224731 */   GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(224768), // Rule ID 3098 //
     /* 224736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224739 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 224744 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 224747 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224750 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224753 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224757 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1684:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMULLB_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_H),
     /* 224760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224762 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224764 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224766 */     GIR_RootConstrainSelectedInstOperands,
     /* 224767 */     // GIR_Coverage, 3098,
     /* 224767 */     GIR_EraseRootFromParent_Done,
     /* 224768 */   // Label 4242: @224768
     /* 224768 */   GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(224805), // Rule ID 3099 //
     /* 224773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullb_pair),
     /* 224781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224794 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1684:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (PMULLB_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 224794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLB_ZZZ_D),
     /* 224797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224799 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224801 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224803 */     GIR_RootConstrainSelectedInstOperands,
     /* 224804 */     // GIR_Coverage, 3099,
     /* 224804 */     GIR_EraseRootFromParent_Done,
     /* 224805 */   // Label 4243: @224805
     /* 224805 */   GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(224842), // Rule ID 3100 //
     /* 224810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 224813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 224818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 224821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224831 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1304:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BEXT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_B),
     /* 224834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224836 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224838 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224840 */     GIR_RootConstrainSelectedInstOperands,
     /* 224841 */     // GIR_Coverage, 3100,
     /* 224841 */     GIR_EraseRootFromParent_Done,
     /* 224842 */   // Label 4244: @224842
     /* 224842 */   GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(224879), // Rule ID 3101 //
     /* 224847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 224850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 224855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 224861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 224864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224868 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1304:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BEXT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 224868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_H),
     /* 224871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224877 */     GIR_RootConstrainSelectedInstOperands,
     /* 224878 */     // GIR_Coverage, 3101,
     /* 224878 */     GIR_EraseRootFromParent_Done,
     /* 224879 */   // Label 4245: @224879
     /* 224879 */   GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(224916), // Rule ID 3102 //
     /* 224884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 224887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 224892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 224895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 224898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 224901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224905 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1304:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BEXT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 224905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_S),
     /* 224908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224912 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224914 */     GIR_RootConstrainSelectedInstOperands,
     /* 224915 */     // GIR_Coverage, 3102,
     /* 224915 */     GIR_EraseRootFromParent_Done,
     /* 224916 */   // Label 4246: @224916
     /* 224916 */   GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(224953), // Rule ID 3103 //
     /* 224921 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 224924 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bext_x),
     /* 224929 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 224932 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 224935 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 224938 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224942 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1304:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BEXT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 224942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BEXT_ZZZ_D),
     /* 224945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224947 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224949 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224951 */     GIR_RootConstrainSelectedInstOperands,
     /* 224952 */     // GIR_Coverage, 3103,
     /* 224952 */     GIR_EraseRootFromParent_Done,
     /* 224953 */   // Label 4247: @224953
     /* 224953 */   GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(224990), // Rule ID 3104 //
     /* 224958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 224966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 224969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 224972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 224975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 224979 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1741:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 224979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_H),
     /* 224982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 224984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 224986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 224988 */     GIR_RootConstrainSelectedInstOperands,
     /* 224989 */     // GIR_Coverage, 3104,
     /* 224989 */     GIR_EraseRootFromParent_Done,
     /* 224990 */   // Label 4248: @224990
     /* 224990 */   GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(225027), // Rule ID 3105 //
     /* 224995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 224998 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 225003 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225006 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 225009 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225016 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1741:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 225016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_S),
     /* 225019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225021 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225023 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225025 */     GIR_RootConstrainSelectedInstOperands,
     /* 225026 */     // GIR_Coverage, 3105,
     /* 225026 */     GIR_EraseRootFromParent_Done,
     /* 225027 */   // Label 4249: @225027
     /* 225027 */   GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(225064), // Rule ID 3106 //
     /* 225032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlbt),
     /* 225040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 225046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225053 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1741:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 225053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLBT_ZZZ_D),
     /* 225056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225058 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225060 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225062 */     GIR_RootConstrainSelectedInstOperands,
     /* 225063 */     // GIR_Coverage, 3106,
     /* 225063 */     GIR_EraseRootFromParent_Done,
     /* 225064 */   // Label 4250: @225064
     /* 225064 */   GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(225101), // Rule ID 3153 //
     /* 225069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 225077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 225080 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 225083 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225090 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1273:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 225090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_B),
     /* 225093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225099 */     GIR_RootConstrainSelectedInstOperands,
     /* 225100 */     // GIR_Coverage, 3153,
     /* 225100 */     GIR_EraseRootFromParent_Done,
     /* 225101 */   // Label 4251: @225101
     /* 225101 */   GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(225138), // Rule ID 3154 //
     /* 225106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 225114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 225120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225127 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1273:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 225127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_H),
     /* 225130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225136 */     GIR_RootConstrainSelectedInstOperands,
     /* 225137 */     // GIR_Coverage, 3154,
     /* 225137 */     GIR_EraseRootFromParent_Done,
     /* 225138 */   // Label 4252: @225138
     /* 225138 */   GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(225175), // Rule ID 3155 //
     /* 225143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnb),
     /* 225151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 225157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225164 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1273:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 225164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNB_ZZZ_S),
     /* 225167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225173 */     GIR_RootConstrainSelectedInstOperands,
     /* 225174 */     // GIR_Coverage, 3155,
     /* 225174 */     GIR_EraseRootFromParent_Done,
     /* 225175 */   // Label 4253: @225175
     /* 225175 */   GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(225212), // Rule ID 3162 //
     /* 225180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 225188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 225191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 225194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225201 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1907:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 225201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_B),
     /* 225204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225210 */     GIR_RootConstrainSelectedInstOperands,
     /* 225211 */     // GIR_Coverage, 3162,
     /* 225211 */     GIR_EraseRootFromParent_Done,
     /* 225212 */   // Label 4254: @225212
     /* 225212 */   GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(225249), // Rule ID 3163 //
     /* 225217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 225225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 225231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225238 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1907:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 225238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_H),
     /* 225241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225247 */     GIR_RootConstrainSelectedInstOperands,
     /* 225248 */     // GIR_Coverage, 3163,
     /* 225248 */     GIR_EraseRootFromParent_Done,
     /* 225249 */   // Label 4255: @225249
     /* 225249 */   GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(225286), // Rule ID 3164 //
     /* 225254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 225257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtnt),
     /* 225262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 225268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225275 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1907:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 225275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTNT_ZZ_S),
     /* 225278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225282 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225284 */     GIR_RootConstrainSelectedInstOperands,
     /* 225285 */     // GIR_Coverage, 3164,
     /* 225285 */     GIR_EraseRootFromParent_Done,
     /* 225286 */   // Label 4256: @225286
     /* 225286 */   GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(225326), // Rule ID 3272 //
     /* 225291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225294 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225299 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 225302 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 225305 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 225308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225312 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2192:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 225312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_B),
     /* 225315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225317 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225321 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225324 */     GIR_RootConstrainSelectedInstOperands,
     /* 225325 */     // GIR_Coverage, 3272,
     /* 225325 */     GIR_EraseRootFromParent_Done,
     /* 225326 */   // Label 4257: @225326
     /* 225326 */   GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(225366), // Rule ID 3273 //
     /* 225331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225334 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225339 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 225342 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 225345 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 225348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225352 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2192:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 225352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_H),
     /* 225355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225357 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225359 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225361 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225364 */     GIR_RootConstrainSelectedInstOperands,
     /* 225365 */     // GIR_Coverage, 3273,
     /* 225365 */     GIR_EraseRootFromParent_Done,
     /* 225366 */   // Label 4258: @225366
     /* 225366 */   GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(225406), // Rule ID 3274 //
     /* 225371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 225382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 225385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 225388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225392 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2192:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 225392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_S),
     /* 225395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225401 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225404 */     GIR_RootConstrainSelectedInstOperands,
     /* 225405 */     // GIR_Coverage, 3274,
     /* 225405 */     GIR_EraseRootFromParent_Done,
     /* 225406 */   // Label 4259: @225406
     /* 225406 */   GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(225446), // Rule ID 3275 //
     /* 225411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 225422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 225425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 225428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225432 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2192:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 225432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PWW_D),
     /* 225435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225441 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225444 */     GIR_RootConstrainSelectedInstOperands,
     /* 225445 */     // GIR_Coverage, 3275,
     /* 225445 */     GIR_EraseRootFromParent_Done,
     /* 225446 */   // Label 4260: @225446
     /* 225446 */   GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(225486), // Rule ID 3280 //
     /* 225451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 225462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 225465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 225468 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225472 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2192:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 225472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_B),
     /* 225475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225477 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225481 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225484 */     GIR_RootConstrainSelectedInstOperands,
     /* 225485 */     // GIR_Coverage, 3280,
     /* 225485 */     GIR_EraseRootFromParent_Done,
     /* 225486 */   // Label 4261: @225486
     /* 225486 */   GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(225526), // Rule ID 3281 //
     /* 225491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 225502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 225505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 225508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225512 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2192:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 225512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_H),
     /* 225515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225519 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225521 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225524 */     GIR_RootConstrainSelectedInstOperands,
     /* 225525 */     // GIR_Coverage, 3281,
     /* 225525 */     GIR_EraseRootFromParent_Done,
     /* 225526 */   // Label 4262: @225526
     /* 225526 */   GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(225566), // Rule ID 3282 //
     /* 225531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 225542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 225545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 225548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225552 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2192:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 225552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_S),
     /* 225555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225561 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225564 */     GIR_RootConstrainSelectedInstOperands,
     /* 225565 */     // GIR_Coverage, 3282,
     /* 225565 */     GIR_EraseRootFromParent_Done,
     /* 225566 */   // Label 4263: @225566
     /* 225566 */   GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(225606), // Rule ID 3283 //
     /* 225571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 225574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilelt),
     /* 225579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 225582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 225585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 225588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 225592 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2192:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 225592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELT_PXX_D),
     /* 225595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 225597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225601 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 225604 */     GIR_RootConstrainSelectedInstOperands,
     /* 225605 */     // GIR_Coverage, 3283,
     /* 225605 */     GIR_EraseRootFromParent_Done,
     /* 225606 */   // Label 4264: @225606
     /* 225606 */   GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(225643), // Rule ID 3452 //
     /* 225611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 225622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 225625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 225628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225632 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1387:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (EXPAND_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 225632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_B),
     /* 225635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225641 */     GIR_RootConstrainSelectedInstOperands,
     /* 225642 */     // GIR_Coverage, 3452,
     /* 225642 */     GIR_EraseRootFromParent_Done,
     /* 225643 */   // Label 4265: @225643
     /* 225643 */   GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(225680), // Rule ID 3453 //
     /* 225648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225669 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1387:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (EXPAND_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 225669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_H),
     /* 225672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225676 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225678 */     GIR_RootConstrainSelectedInstOperands,
     /* 225679 */     // GIR_Coverage, 3453,
     /* 225679 */     GIR_EraseRootFromParent_Done,
     /* 225680 */   // Label 4266: @225680
     /* 225680 */   GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(225717), // Rule ID 3454 //
     /* 225685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 225696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 225699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 225702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225706 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1387:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (EXPAND_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 225706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_H),
     /* 225709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225713 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225715 */     GIR_RootConstrainSelectedInstOperands,
     /* 225716 */     // GIR_Coverage, 3454,
     /* 225716 */     GIR_EraseRootFromParent_Done,
     /* 225717 */   // Label 4267: @225717
     /* 225717 */   GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(225754), // Rule ID 3455 //
     /* 225722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225743 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1387:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (EXPAND_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 225743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_S),
     /* 225746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225748 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225750 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225752 */     GIR_RootConstrainSelectedInstOperands,
     /* 225753 */     // GIR_Coverage, 3455,
     /* 225753 */     GIR_EraseRootFromParent_Done,
     /* 225754 */   // Label 4268: @225754
     /* 225754 */   GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(225791), // Rule ID 3456 //
     /* 225759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225780 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1387:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (EXPAND_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 225780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_S),
     /* 225783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225785 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225787 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225789 */     GIR_RootConstrainSelectedInstOperands,
     /* 225790 */     // GIR_Coverage, 3456,
     /* 225790 */     GIR_EraseRootFromParent_Done,
     /* 225791 */   // Label 4269: @225791
     /* 225791 */   GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(225828), // Rule ID 3457 //
     /* 225796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225799 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225804 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225807 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225810 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225813 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225817 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1387:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (EXPAND_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 225817 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_D),
     /* 225820 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225826 */     GIR_RootConstrainSelectedInstOperands,
     /* 225827 */     // GIR_Coverage, 3457,
     /* 225827 */     GIR_EraseRootFromParent_Done,
     /* 225828 */   // Label 4270: @225828
     /* 225828 */   GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(225865), // Rule ID 3458 //
     /* 225833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 225836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_expand),
     /* 225841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225850 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225854 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1387:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (EXPAND_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 225854 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXPAND_ZPZ_D),
     /* 225857 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225861 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225863 */     GIR_RootConstrainSelectedInstOperands,
     /* 225864 */     // GIR_Coverage, 3458,
     /* 225864 */     GIR_EraseRootFromParent_Done,
     /* 225865 */   // Label 4271: @225865
     /* 225865 */   GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(225902), // Rule ID 3479 //
     /* 225870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 225873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 225878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225891 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1372:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (COMPACT_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 225891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
     /* 225894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225900 */     GIR_RootConstrainSelectedInstOperands,
     /* 225901 */     // GIR_Coverage, 3479,
     /* 225901 */     GIR_EraseRootFromParent_Done,
     /* 225902 */   // Label 4272: @225902
     /* 225902 */   GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(225939), // Rule ID 3480 //
     /* 225907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 225910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 225915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 225918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 225921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 225924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225928 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1372:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (COMPACT_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 225928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_S),
     /* 225931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225937 */     GIR_RootConstrainSelectedInstOperands,
     /* 225938 */     // GIR_Coverage, 3480,
     /* 225938 */     GIR_EraseRootFromParent_Done,
     /* 225939 */   // Label 4273: @225939
     /* 225939 */   GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(225976), // Rule ID 3481 //
     /* 225944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 225947 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 225952 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225955 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225958 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 225965 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1372:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (COMPACT_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 225965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
     /* 225968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 225970 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 225972 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 225974 */     GIR_RootConstrainSelectedInstOperands,
     /* 225975 */     // GIR_Coverage, 3481,
     /* 225975 */     GIR_EraseRootFromParent_Done,
     /* 225976 */   // Label 4274: @225976
     /* 225976 */   GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(226013), // Rule ID 3482 //
     /* 225981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 225984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 225989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 225992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 225995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 225998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226002 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1372:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (COMPACT_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 226002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
     /* 226005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226009 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226011 */     GIR_RootConstrainSelectedInstOperands,
     /* 226012 */     // GIR_Coverage, 3482,
     /* 226012 */     GIR_EraseRootFromParent_Done,
     /* 226013 */   // Label 4275: @226013
     /* 226013 */   GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(226050), // Rule ID 3483 //
     /* 226018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p2),
     /* 226021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 226026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 226029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 226035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226039 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1372:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (COMPACT_ZPZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 226039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_D),
     /* 226042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226046 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226048 */     GIR_RootConstrainSelectedInstOperands,
     /* 226049 */     // GIR_Coverage, 3483,
     /* 226049 */     GIR_EraseRootFromParent_Done,
     /* 226050 */   // Label 4276: @226050
     /* 226050 */   GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(226087), // Rule ID 3484 //
     /* 226055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 226058 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 226063 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 226066 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 226069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 226072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226076 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1372:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (COMPACT_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 226076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_B),
     /* 226079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226083 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226085 */     GIR_RootConstrainSelectedInstOperands,
     /* 226086 */     // GIR_Coverage, 3484,
     /* 226086 */     GIR_EraseRootFromParent_Done,
     /* 226087 */   // Label 4277: @226087
     /* 226087 */   GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(226124), // Rule ID 3485 //
     /* 226092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 226095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 226100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226109 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226113 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1372:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (COMPACT_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 226113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_H),
     /* 226116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226118 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226120 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226122 */     GIR_RootConstrainSelectedInstOperands,
     /* 226123 */     // GIR_Coverage, 3485,
     /* 226123 */     GIR_EraseRootFromParent_Done,
     /* 226124 */   // Label 4278: @226124
     /* 226124 */   GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(226161), // Rule ID 3486 //
     /* 226129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE2p2_or_SME2p2),
     /* 226132 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_compact),
     /* 226137 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226140 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226143 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226146 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226150 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1372:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (COMPACT_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 226150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::COMPACT_ZPZ_H),
     /* 226153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226157 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226159 */     GIR_RootConstrainSelectedInstOperands,
     /* 226160 */     // GIR_Coverage, 3486,
     /* 226160 */     GIR_EraseRootFromParent_Done,
     /* 226161 */   // Label 4279: @226161
     /* 226161 */   GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(226198), // Rule ID 3508 //
     /* 226166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 226169 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 226174 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226177 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 226180 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226187 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1594:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (FTSSEL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 226187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_H),
     /* 226190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226194 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226196 */     GIR_RootConstrainSelectedInstOperands,
     /* 226197 */     // GIR_Coverage, 3508,
     /* 226197 */     GIR_EraseRootFromParent_Done,
     /* 226198 */   // Label 4280: @226198
     /* 226198 */   GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(226235), // Rule ID 3509 //
     /* 226203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 226206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 226211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 226217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226224 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1594:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (FTSSEL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 226224 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_S),
     /* 226227 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226229 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226231 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226233 */     GIR_RootConstrainSelectedInstOperands,
     /* 226234 */     // GIR_Coverage, 3509,
     /* 226234 */     GIR_EraseRootFromParent_Done,
     /* 226235 */   // Label 4281: @226235
     /* 226235 */   GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(226272), // Rule ID 3510 //
     /* 226240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 226243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftssel_x),
     /* 226248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 226254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226261 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1594:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (FTSSEL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 226261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTSSEL_ZZZ_D),
     /* 226264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226268 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226270 */     GIR_RootConstrainSelectedInstOperands,
     /* 226271 */     // GIR_Coverage, 3510,
     /* 226271 */     GIR_EraseRootFromParent_Done,
     /* 226272 */   // Label 4282: @226272
     /* 226272 */   GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(226309), // Rule ID 3532 //
     /* 226277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 226280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka_z),
     /* 226285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 226288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 226291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 226294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 226298 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1325:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (BRKA_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 226298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPzP),
     /* 226301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 226303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226307 */     GIR_RootConstrainSelectedInstOperands,
     /* 226308 */     // GIR_Coverage, 3532,
     /* 226308 */     GIR_EraseRootFromParent_Done,
     /* 226309 */   // Label 4283: @226309
     /* 226309 */   GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(226346), // Rule ID 3537 //
     /* 226314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVESM4),
     /* 226317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sm4ekey),
     /* 226322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 226328 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226335 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1777:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SM4EKEY_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 226335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM4EKEY_ZZZ_S),
     /* 226338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226340 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226342 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226344 */     GIR_RootConstrainSelectedInstOperands,
     /* 226345 */     // GIR_Coverage, 3537,
     /* 226345 */     GIR_EraseRootFromParent_Done,
     /* 226346 */   // Label 4284: @226346
     /* 226346 */   GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(226383), // Rule ID 3547 //
     /* 226351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 226362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 226365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 226368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226372 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2214:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 226372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226381 */     GIR_RootConstrainSelectedInstOperands,
     /* 226382 */     // GIR_Coverage, 3547,
     /* 226382 */     GIR_EraseRootFromParent_Done,
     /* 226383 */   // Label 4285: @226383
     /* 226383 */   GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(226420), // Rule ID 3548 //
     /* 226388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 226402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226409 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2214:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 226409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226418 */     GIR_RootConstrainSelectedInstOperands,
     /* 226419 */     // GIR_Coverage, 3548,
     /* 226419 */     GIR_EraseRootFromParent_Done,
     /* 226420 */   // Label 4286: @226420
     /* 226420 */   GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(226457), // Rule ID 3549 //
     /* 226425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226428 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226433 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 226439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226446 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2214:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 226446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226453 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226455 */     GIR_RootConstrainSelectedInstOperands,
     /* 226456 */     // GIR_Coverage, 3549,
     /* 226456 */     GIR_EraseRootFromParent_Done,
     /* 226457 */   // Label 4287: @226457
     /* 226457 */   GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(226494), // Rule ID 3550 //
     /* 226462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 226476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226483 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2214:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 226483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226490 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226492 */     GIR_RootConstrainSelectedInstOperands,
     /* 226493 */     // GIR_Coverage, 3550,
     /* 226493 */     GIR_EraseRootFromParent_Done,
     /* 226494 */   // Label 4288: @226494
     /* 226494 */   GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(226531), // Rule ID 3551 //
     /* 226499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 226513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226520 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2214:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 226520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226525 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226527 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226529 */     GIR_RootConstrainSelectedInstOperands,
     /* 226530 */     // GIR_Coverage, 3551,
     /* 226530 */     GIR_EraseRootFromParent_Done,
     /* 226531 */   // Label 4289: @226531
     /* 226531 */   GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(226568), // Rule ID 3552 //
     /* 226536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226539 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226544 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226547 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 226550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226553 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226557 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2214:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 226557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226562 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226564 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226566 */     GIR_RootConstrainSelectedInstOperands,
     /* 226567 */     // GIR_Coverage, 3552,
     /* 226567 */     GIR_EraseRootFromParent_Done,
     /* 226568 */   // Label 4290: @226568
     /* 226568 */   GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(226605), // Rule ID 3553 //
     /* 226573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 226576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip1q),
     /* 226581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 226587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226594 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2214:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 226594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_Q),
     /* 226597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226599 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226601 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226603 */     GIR_RootConstrainSelectedInstOperands,
     /* 226604 */     // GIR_Coverage, 3553,
     /* 226604 */     GIR_EraseRootFromParent_Done,
     /* 226605 */   // Label 4291: @226605
     /* 226605 */   GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(226642), // Rule ID 3609 //
     /* 226610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226613 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 226618 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 226621 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226624 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226631 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1399:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FADDQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 226631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_H),
     /* 226634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226640 */     GIR_RootConstrainSelectedInstOperands,
     /* 226641 */     // GIR_Coverage, 3609,
     /* 226641 */     GIR_EraseRootFromParent_Done,
     /* 226642 */   // Label 4292: @226642
     /* 226642 */   GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(226679), // Rule ID 3610 //
     /* 226647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 226655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 226658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 226661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226668 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1399:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FADDQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 226668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_S),
     /* 226671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226673 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226675 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226677 */     GIR_RootConstrainSelectedInstOperands,
     /* 226678 */     // GIR_Coverage, 3610,
     /* 226678 */     GIR_EraseRootFromParent_Done,
     /* 226679 */   // Label 4293: @226679
     /* 226679 */   GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(226716), // Rule ID 3611 //
     /* 226684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddqv),
     /* 226692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 226695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226705 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1399:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FADDQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 226705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDQV_D),
     /* 226708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226712 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226714 */     GIR_RootConstrainSelectedInstOperands,
     /* 226715 */     // GIR_Coverage, 3611,
     /* 226715 */     GIR_EraseRootFromParent_Done,
     /* 226716 */   // Label 4294: @226716
     /* 226716 */   GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(226753), // Rule ID 3641 //
     /* 226721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 226729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 226732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 226735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 226738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226742 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1669:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 226742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_B),
     /* 226745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226751 */     GIR_RootConstrainSelectedInstOperands,
     /* 226752 */     // GIR_Coverage, 3641,
     /* 226752 */     GIR_EraseRootFromParent_Done,
     /* 226753 */   // Label 4295: @226753
     /* 226753 */   GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(226790), // Rule ID 3642 //
     /* 226758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 226766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 226769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 226772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226779 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1669:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 226779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_H),
     /* 226782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226788 */     GIR_RootConstrainSelectedInstOperands,
     /* 226789 */     // GIR_Coverage, 3642,
     /* 226789 */     GIR_EraseRootFromParent_Done,
     /* 226790 */   // Label 4296: @226790
     /* 226790 */   GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(226827), // Rule ID 3643 //
     /* 226795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 226803 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 226806 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 226809 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226812 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226816 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1669:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 226816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_S),
     /* 226819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226821 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226823 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226825 */     GIR_RootConstrainSelectedInstOperands,
     /* 226826 */     // GIR_Coverage, 3643,
     /* 226826 */     GIR_EraseRootFromParent_Done,
     /* 226827 */   // Label 4297: @226827
     /* 226827 */   GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(226864), // Rule ID 3644 //
     /* 226832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orqv),
     /* 226840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 226843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 226846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 226853 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1669:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 226853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORQV_VPZ_D),
     /* 226856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 226858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226862 */     GIR_RootConstrainSelectedInstOperands,
     /* 226863 */     // GIR_Coverage, 3644,
     /* 226863 */     GIR_EraseRootFromParent_Done,
     /* 226864 */   // Label 4298: @226864
     /* 226864 */   GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(226901), // Rule ID 3645 //
     /* 226869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 226877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 226880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 226883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 226886 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226890 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2222:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 226890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_B),
     /* 226893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226895 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226897 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226899 */     GIR_RootConstrainSelectedInstOperands,
     /* 226900 */     // GIR_Coverage, 3645,
     /* 226900 */     GIR_EraseRootFromParent_Done,
     /* 226901 */   // Label 4299: @226901
     /* 226901 */   GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(226938), // Rule ID 3646 //
     /* 226906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226909 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 226914 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 226917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 226920 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 226923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226927 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2222:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 226927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
     /* 226930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226932 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226934 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226936 */     GIR_RootConstrainSelectedInstOperands,
     /* 226937 */     // GIR_Coverage, 3646,
     /* 226937 */     GIR_EraseRootFromParent_Done,
     /* 226938 */   // Label 4300: @226938
     /* 226938 */   GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(226975), // Rule ID 3647 //
     /* 226943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 226951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 226954 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 226957 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 226960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 226964 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2222:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 226964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
     /* 226967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 226969 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 226971 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 226973 */     GIR_RootConstrainSelectedInstOperands,
     /* 226974 */     // GIR_Coverage, 3647,
     /* 226974 */     GIR_EraseRootFromParent_Done,
     /* 226975 */   // Label 4301: @226975
     /* 226975 */   GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(227012), // Rule ID 3648 //
     /* 226980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 226983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 226988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 226991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 226994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 226997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227001 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2222:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
     /* 227004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227010 */     GIR_RootConstrainSelectedInstOperands,
     /* 227011 */     // GIR_Coverage, 3648,
     /* 227011 */     GIR_EraseRootFromParent_Done,
     /* 227012 */   // Label 4302: @227012
     /* 227012 */   GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(227049), // Rule ID 3649 //
     /* 227017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 227025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227038 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2222:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 227038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_H),
     /* 227041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227047 */     GIR_RootConstrainSelectedInstOperands,
     /* 227048 */     // GIR_Coverage, 3649,
     /* 227048 */     GIR_EraseRootFromParent_Done,
     /* 227049 */   // Label 4303: @227049
     /* 227049 */   GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(227086), // Rule ID 3650 //
     /* 227054 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227057 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 227062 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227075 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2222:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 227075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_S),
     /* 227078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227084 */     GIR_RootConstrainSelectedInstOperands,
     /* 227085 */     // GIR_Coverage, 3650,
     /* 227085 */     GIR_EraseRootFromParent_Done,
     /* 227086 */   // Label 4304: @227086
     /* 227086 */   GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(227123), // Rule ID 3651 //
     /* 227091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227094 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq1),
     /* 227099 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227102 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227105 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227108 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227112 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2222:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 227112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ1_ZZZ_D),
     /* 227115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227121 */     GIR_RootConstrainSelectedInstOperands,
     /* 227122 */     // GIR_Coverage, 3651,
     /* 227122 */     GIR_EraseRootFromParent_Done,
     /* 227123 */   // Label 4305: @227123
     /* 227123 */   GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(227160), // Rule ID 3652 //
     /* 227128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 227139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 227142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 227145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227149 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1973:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TBLQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 227149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_B),
     /* 227152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227156 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227158 */     GIR_RootConstrainSelectedInstOperands,
     /* 227159 */     // GIR_Coverage, 3652,
     /* 227159 */     GIR_EraseRootFromParent_Done,
     /* 227160 */   // Label 4306: @227160
     /* 227160 */   GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(227197), // Rule ID 3653 //
     /* 227165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227179 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227182 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227186 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1973:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TBLQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 227186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
     /* 227189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227191 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227193 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227195 */     GIR_RootConstrainSelectedInstOperands,
     /* 227196 */     // GIR_Coverage, 3653,
     /* 227196 */     GIR_EraseRootFromParent_Done,
     /* 227197 */   // Label 4307: @227197
     /* 227197 */   GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(227234), // Rule ID 3654 //
     /* 227202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227223 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1973:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TBLQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
     /* 227226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227232 */     GIR_RootConstrainSelectedInstOperands,
     /* 227233 */     // GIR_Coverage, 3654,
     /* 227233 */     GIR_EraseRootFromParent_Done,
     /* 227234 */   // Label 4308: @227234
     /* 227234 */   GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(227271), // Rule ID 3655 //
     /* 227239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227253 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227260 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1973:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TBLQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
     /* 227263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227265 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227267 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227269 */     GIR_RootConstrainSelectedInstOperands,
     /* 227270 */     // GIR_Coverage, 3655,
     /* 227270 */     GIR_EraseRootFromParent_Done,
     /* 227271 */   // Label 4309: @227271
     /* 227271 */   GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(227308), // Rule ID 3656 //
     /* 227276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 227287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 227290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 227293 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227297 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1973:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TBLQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 227297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_H),
     /* 227300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227306 */     GIR_RootConstrainSelectedInstOperands,
     /* 227307 */     // GIR_Coverage, 3656,
     /* 227307 */     GIR_EraseRootFromParent_Done,
     /* 227308 */   // Label 4310: @227308
     /* 227308 */   GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(227345), // Rule ID 3657 //
     /* 227313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227334 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1973:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TBLQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_S),
     /* 227337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227343 */     GIR_RootConstrainSelectedInstOperands,
     /* 227344 */     // GIR_Coverage, 3657,
     /* 227344 */     GIR_EraseRootFromParent_Done,
     /* 227345 */   // Label 4311: @227345
     /* 227345 */   GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(227382), // Rule ID 3658 //
     /* 227350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 227353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tblq),
     /* 227358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227371 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1973:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TBLQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBLQ_ZZZ_D),
     /* 227374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227378 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227380 */     GIR_RootConstrainSelectedInstOperands,
     /* 227381 */     // GIR_Coverage, 3658,
     /* 227381 */     GIR_EraseRootFromParent_Done,
     /* 227382 */   // Label 4312: @227382
     /* 227382 */   GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(227419), // Rule ID 9140 //
     /* 227387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb_z),
     /* 227395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 227398 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 227401 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 227404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227408 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1327:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (BRKB_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 227408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPzP),
     /* 227411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227415 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227417 */     GIR_RootConstrainSelectedInstOperands,
     /* 227418 */     // GIR_Coverage, 9140,
     /* 227418 */     GIR_EraseRootFromParent_Done,
     /* 227419 */   // Label 4313: @227419
     /* 227419 */   GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(227456), // Rule ID 9616 //
     /* 227424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227427 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
     /* 227432 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227445 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1277:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_0:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_0),
     /* 227448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227454 */     GIR_RootConstrainSelectedInstOperands,
     /* 227455 */     // GIR_Coverage, 9616,
     /* 227455 */     GIR_EraseRootFromParent_Done,
     /* 227456 */   // Label 4314: @227456
     /* 227456 */   GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(227493), // Rule ID 9617 //
     /* 227461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
     /* 227469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227475 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227478 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227482 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1279:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_1:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_1),
     /* 227485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227487 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227489 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227491 */     GIR_RootConstrainSelectedInstOperands,
     /* 227492 */     // GIR_Coverage, 9617,
     /* 227492 */     GIR_EraseRootFromParent_Done,
     /* 227493 */   // Label 4315: @227493
     /* 227493 */   GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(227530), // Rule ID 9618 //
     /* 227498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227501 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
     /* 227506 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227509 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227512 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227519 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1280:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_2:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_2),
     /* 227522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227528 */     GIR_RootConstrainSelectedInstOperands,
     /* 227529 */     // GIR_Coverage, 9618,
     /* 227529 */     GIR_EraseRootFromParent_Done,
     /* 227530 */   // Label 4316: @227530
     /* 227530 */   GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(227567), // Rule ID 9619 //
     /* 227535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227538 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
     /* 227543 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 227546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 227549 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 227552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227556 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1278:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADR_LSL_ZZZ_S_3:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 227556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_S_3),
     /* 227559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227561 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227563 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227565 */     GIR_RootConstrainSelectedInstOperands,
     /* 227566 */     // GIR_Coverage, 9619,
     /* 227566 */     GIR_EraseRootFromParent_Done,
     /* 227567 */   // Label 4317: @227567
     /* 227567 */   GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(227604), // Rule ID 9620 //
     /* 227572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrb),
     /* 227580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227593 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1277:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_0:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_0),
     /* 227596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227602 */     GIR_RootConstrainSelectedInstOperands,
     /* 227603 */     // GIR_Coverage, 9620,
     /* 227603 */     GIR_EraseRootFromParent_Done,
     /* 227604 */   // Label 4318: @227604
     /* 227604 */   GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(227641), // Rule ID 9621 //
     /* 227609 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227612 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrh),
     /* 227617 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227620 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227623 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227630 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1279:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_1:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_1),
     /* 227633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227637 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227639 */     GIR_RootConstrainSelectedInstOperands,
     /* 227640 */     // GIR_Coverage, 9621,
     /* 227640 */     GIR_EraseRootFromParent_Done,
     /* 227641 */   // Label 4319: @227641
     /* 227641 */   GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(227678), // Rule ID 9622 //
     /* 227646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrw),
     /* 227654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227667 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1280:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_2:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_2),
     /* 227670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227676 */     GIR_RootConstrainSelectedInstOperands,
     /* 227677 */     // GIR_Coverage, 9622,
     /* 227677 */     GIR_EraseRootFromParent_Done,
     /* 227678 */   // Label 4320: @227678
     /* 227678 */   GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(227715), // Rule ID 9623 //
     /* 227683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 227686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adrd),
     /* 227691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 227694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 227697 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 227700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 227704 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1278:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADR_LSL_ZZZ_D_3:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 227704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADR_LSL_ZZZ_D_3),
     /* 227707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 227709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227713 */     GIR_RootConstrainSelectedInstOperands,
     /* 227714 */     // GIR_Coverage, 9623,
     /* 227714 */     GIR_EraseRootFromParent_Done,
     /* 227715 */   // Label 4321: @227715
     /* 227715 */   GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(227755), // Rule ID 10633 //
     /* 227720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 227728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 227731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227734 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227741 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2174:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_B),
     /* 227744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227750 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227753 */     GIR_RootConstrainSelectedInstOperands,
     /* 227754 */     // GIR_Coverage, 10633,
     /* 227754 */     GIR_EraseRootFromParent_Done,
     /* 227755 */   // Label 4322: @227755
     /* 227755 */   GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(227795), // Rule ID 10634 //
     /* 227760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 227768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 227771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227781 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2174:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_H),
     /* 227784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227788 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227790 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227793 */     GIR_RootConstrainSelectedInstOperands,
     /* 227794 */     // GIR_Coverage, 10634,
     /* 227794 */     GIR_EraseRootFromParent_Done,
     /* 227795 */   // Label 4323: @227795
     /* 227795 */   GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(227835), // Rule ID 10635 //
     /* 227800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 227808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 227811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227821 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2174:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_S),
     /* 227824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227830 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227833 */     GIR_RootConstrainSelectedInstOperands,
     /* 227834 */     // GIR_Coverage, 10635,
     /* 227834 */     GIR_EraseRootFromParent_Done,
     /* 227835 */   // Label 4324: @227835
     /* 227835 */   GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(227875), // Rule ID 10636 //
     /* 227840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 227848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 227851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227861 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2174:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PWW_D),
     /* 227864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227868 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227870 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227873 */     GIR_RootConstrainSelectedInstOperands,
     /* 227874 */     // GIR_Coverage, 10636,
     /* 227874 */     GIR_EraseRootFromParent_Done,
     /* 227875 */   // Label 4325: @227875
     /* 227875 */   GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(227915), // Rule ID 10645 //
     /* 227880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 227888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 227891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227901 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2186:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_B),
     /* 227904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227906 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227910 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227913 */     GIR_RootConstrainSelectedInstOperands,
     /* 227914 */     // GIR_Coverage, 10645,
     /* 227914 */     GIR_EraseRootFromParent_Done,
     /* 227915 */   // Label 4326: @227915
     /* 227915 */   GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(227955), // Rule ID 10646 //
     /* 227920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 227928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 227931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227941 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2186:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_H),
     /* 227944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227950 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227953 */     GIR_RootConstrainSelectedInstOperands,
     /* 227954 */     // GIR_Coverage, 10646,
     /* 227954 */     GIR_EraseRootFromParent_Done,
     /* 227955 */   // Label 4327: @227955
     /* 227955 */   GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(227995), // Rule ID 10647 //
     /* 227960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 227963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 227968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 227971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 227974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 227977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 227981 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2186:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 227981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_S),
     /* 227984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 227986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 227988 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 227990 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 227993 */     GIR_RootConstrainSelectedInstOperands,
     /* 227994 */     // GIR_Coverage, 10647,
     /* 227994 */     GIR_EraseRootFromParent_Done,
     /* 227995 */   // Label 4328: @227995
     /* 227995 */   GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(228035), // Rule ID 10648 //
     /* 228000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 228008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 228011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 228014 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 228017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228021 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2186:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILELS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 228021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PWW_D),
     /* 228024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228030 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228033 */     GIR_RootConstrainSelectedInstOperands,
     /* 228034 */     // GIR_Coverage, 10648,
     /* 228034 */     GIR_EraseRootFromParent_Done,
     /* 228035 */   // Label 4329: @228035
     /* 228035 */   GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(228075), // Rule ID 10649 //
     /* 228040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 228048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 228051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228061 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2174:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_B),
     /* 228064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228070 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228073 */     GIR_RootConstrainSelectedInstOperands,
     /* 228074 */     // GIR_Coverage, 10649,
     /* 228074 */     GIR_EraseRootFromParent_Done,
     /* 228075 */   // Label 4330: @228075
     /* 228075 */   GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(228115), // Rule ID 10650 //
     /* 228080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 228088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 228091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228101 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2174:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_H),
     /* 228104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228108 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228110 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228113 */     GIR_RootConstrainSelectedInstOperands,
     /* 228114 */     // GIR_Coverage, 10650,
     /* 228114 */     GIR_EraseRootFromParent_Done,
     /* 228115 */   // Label 4331: @228115
     /* 228115 */   GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(228155), // Rule ID 10651 //
     /* 228120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 228128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 228131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228141 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2174:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_S),
     /* 228144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228148 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228150 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228153 */     GIR_RootConstrainSelectedInstOperands,
     /* 228154 */     // GIR_Coverage, 10651,
     /* 228154 */     GIR_EraseRootFromParent_Done,
     /* 228155 */   // Label 4332: @228155
     /* 228155 */   GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(228195), // Rule ID 10652 //
     /* 228160 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228163 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilele),
     /* 228168 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 228171 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228174 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228181 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2174:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELE_PXX_D),
     /* 228184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228190 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228193 */     GIR_RootConstrainSelectedInstOperands,
     /* 228194 */     // GIR_Coverage, 10652,
     /* 228194 */     GIR_EraseRootFromParent_Done,
     /* 228195 */   // Label 4333: @228195
     /* 228195 */   GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(228235), // Rule ID 10661 //
     /* 228200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228203 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 228208 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 228211 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228214 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228217 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228221 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2186:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
     /* 228224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228228 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228230 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228233 */     GIR_RootConstrainSelectedInstOperands,
     /* 228234 */     // GIR_Coverage, 10661,
     /* 228234 */     GIR_EraseRootFromParent_Done,
     /* 228235 */   // Label 4334: @228235
     /* 228235 */   GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(228275), // Rule ID 10662 //
     /* 228240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228243 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 228248 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 228251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228261 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2186:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 228264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228268 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228270 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228273 */     GIR_RootConstrainSelectedInstOperands,
     /* 228274 */     // GIR_Coverage, 10662,
     /* 228274 */     GIR_EraseRootFromParent_Done,
     /* 228275 */   // Label 4335: @228275
     /* 228275 */   GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(228315), // Rule ID 10663 //
     /* 228280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228283 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 228288 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 228291 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228294 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228301 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2186:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 228304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228308 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228310 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228313 */     GIR_RootConstrainSelectedInstOperands,
     /* 228314 */     // GIR_Coverage, 10663,
     /* 228314 */     GIR_EraseRootFromParent_Done,
     /* 228315 */   // Label 4336: @228315
     /* 228315 */   GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(228355), // Rule ID 10664 //
     /* 228320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilels),
     /* 228328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 228331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 228334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 228337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 228341 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2186:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILELS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 228341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 228344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 228346 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228348 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228350 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 228353 */     GIR_RootConstrainSelectedInstOperands,
     /* 228354 */     // GIR_Coverage, 10664,
     /* 228354 */     GIR_EraseRootFromParent_Done,
     /* 228355 */   // Label 4337: @228355
     /* 228355 */   GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(228392), // Rule ID 10823 //
     /* 228360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 228368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 228377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228381 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2081:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UQINCP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 228381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_H),
     /* 228384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228386 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228388 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228390 */     GIR_RootConstrainSelectedInstOperands,
     /* 228391 */     // GIR_Coverage, 10823,
     /* 228391 */     GIR_EraseRootFromParent_Done,
     /* 228392 */   // Label 4338: @228392
     /* 228392 */   GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(228429), // Rule ID 10824 //
     /* 228397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 228405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 228414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228418 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2081:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UQINCP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 228418 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_S),
     /* 228421 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228423 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228427 */     GIR_RootConstrainSelectedInstOperands,
     /* 228428 */     // GIR_Coverage, 10824,
     /* 228428 */     GIR_EraseRootFromParent_Done,
     /* 228429 */   // Label 4339: @228429
     /* 228429 */   GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(228466), // Rule ID 10825 //
     /* 228434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincp),
     /* 228442 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228445 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228448 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 228451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228455 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2081:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UQINCP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 228455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCP_ZP_D),
     /* 228458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228460 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228462 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228464 */     GIR_RootConstrainSelectedInstOperands,
     /* 228465 */     // GIR_Coverage, 10825,
     /* 228465 */     GIR_EraseRootFromParent_Done,
     /* 228466 */   // Label 4340: @228466
     /* 228466 */   GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(228503), // Rule ID 10826 //
     /* 228471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228474 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 228479 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 228488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228492 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1832:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (SQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 228492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_H),
     /* 228495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228501 */     GIR_RootConstrainSelectedInstOperands,
     /* 228502 */     // GIR_Coverage, 10826,
     /* 228502 */     GIR_EraseRootFromParent_Done,
     /* 228503 */   // Label 4341: @228503
     /* 228503 */   GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(228540), // Rule ID 10827 //
     /* 228508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 228516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 228525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228529 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1832:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (SQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 228529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_S),
     /* 228532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228538 */     GIR_RootConstrainSelectedInstOperands,
     /* 228539 */     // GIR_Coverage, 10827,
     /* 228539 */     GIR_EraseRootFromParent_Done,
     /* 228540 */   // Label 4342: @228540
     /* 228540 */   GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(228577), // Rule ID 10828 //
     /* 228545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecp),
     /* 228553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 228562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228566 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1832:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (SQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 228566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECP_ZP_D),
     /* 228569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228571 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228575 */     GIR_RootConstrainSelectedInstOperands,
     /* 228576 */     // GIR_Coverage, 10828,
     /* 228576 */     GIR_EraseRootFromParent_Done,
     /* 228577 */   // Label 4343: @228577
     /* 228577 */   GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(228614), // Rule ID 10829 //
     /* 228582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 228590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 228599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228603 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2067:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UQDECP_ZP_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 228603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_H),
     /* 228606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228612 */     GIR_RootConstrainSelectedInstOperands,
     /* 228613 */     // GIR_Coverage, 10829,
     /* 228613 */     GIR_EraseRootFromParent_Done,
     /* 228614 */   // Label 4344: @228614
     /* 228614 */   GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(228651), // Rule ID 10830 //
     /* 228619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 228627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 228636 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228640 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2067:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UQDECP_ZP_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 228640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_S),
     /* 228643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228645 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228647 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228649 */     GIR_RootConstrainSelectedInstOperands,
     /* 228650 */     // GIR_Coverage, 10830,
     /* 228650 */     GIR_EraseRootFromParent_Done,
     /* 228651 */   // Label 4345: @228651
     /* 228651 */   GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(228688), // Rule ID 10831 //
     /* 228656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 228659 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecp),
     /* 228664 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228667 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228670 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 228673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228677 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2067:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UQDECP_ZP_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 228677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECP_ZP_D),
     /* 228680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 228682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228686 */     GIR_RootConstrainSelectedInstOperands,
     /* 228687 */     // GIR_Coverage, 10831,
     /* 228687 */     GIR_EraseRootFromParent_Done,
     /* 228688 */   // Label 4346: @228688
     /* 228688 */   GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(228725), // Rule ID 12069 //
     /* 228693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228714 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2219:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 228714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228723 */     GIR_RootConstrainSelectedInstOperands,
     /* 228724 */     // GIR_Coverage, 12069,
     /* 228724 */     GIR_EraseRootFromParent_Done,
     /* 228725 */   // Label 4347: @228725
     /* 228725 */   GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(228762), // Rule ID 12070 //
     /* 228730 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228733 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228738 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228741 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228751 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2219:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 228751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228760 */     GIR_RootConstrainSelectedInstOperands,
     /* 228761 */     // GIR_Coverage, 12070,
     /* 228761 */     GIR_EraseRootFromParent_Done,
     /* 228762 */   // Label 4348: @228762
     /* 228762 */   GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(228799), // Rule ID 12071 //
     /* 228767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 228778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 228781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 228784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228788 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2219:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 228788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228797 */     GIR_RootConstrainSelectedInstOperands,
     /* 228798 */     // GIR_Coverage, 12071,
     /* 228798 */     GIR_EraseRootFromParent_Done,
     /* 228799 */   // Label 4349: @228799
     /* 228799 */   GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(228836), // Rule ID 12072 //
     /* 228804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228825 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2219:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 228825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228830 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228832 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228834 */     GIR_RootConstrainSelectedInstOperands,
     /* 228835 */     // GIR_Coverage, 12072,
     /* 228835 */     GIR_EraseRootFromParent_Done,
     /* 228836 */   // Label 4350: @228836
     /* 228836 */   GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(228873), // Rule ID 12073 //
     /* 228841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 228852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 228855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 228858 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228862 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2219:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 228862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228871 */     GIR_RootConstrainSelectedInstOperands,
     /* 228872 */     // GIR_Coverage, 12073,
     /* 228872 */     GIR_EraseRootFromParent_Done,
     /* 228873 */   // Label 4351: @228873
     /* 228873 */   GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(228910), // Rule ID 12074 //
     /* 228878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228899 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2219:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 228899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228908 */     GIR_RootConstrainSelectedInstOperands,
     /* 228909 */     // GIR_Coverage, 12074,
     /* 228909 */     GIR_EraseRootFromParent_Done,
     /* 228910 */   // Label 4352: @228910
     /* 228910 */   GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(228947), // Rule ID 12075 //
     /* 228915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zip2q),
     /* 228923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 228926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 228929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 228932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228936 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2219:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 228936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_Q),
     /* 228939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228945 */     GIR_RootConstrainSelectedInstOperands,
     /* 228946 */     // GIR_Coverage, 12075,
     /* 228946 */     GIR_EraseRootFromParent_Done,
     /* 228947 */   // Label 4353: @228947
     /* 228947 */   GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(228984), // Rule ID 12076 //
     /* 228952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 228960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 228963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 228966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 228969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 228973 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2140:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 228973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 228976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 228978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 228980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 228982 */     GIR_RootConstrainSelectedInstOperands,
     /* 228983 */     // GIR_Coverage, 12076,
     /* 228983 */     GIR_EraseRootFromParent_Done,
     /* 228984 */   // Label 4354: @228984
     /* 228984 */   GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(229021), // Rule ID 12077 //
     /* 228989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 228992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 228997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229010 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2140:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 229010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229019 */     GIR_RootConstrainSelectedInstOperands,
     /* 229020 */     // GIR_Coverage, 12077,
     /* 229020 */     GIR_EraseRootFromParent_Done,
     /* 229021 */   // Label 4355: @229021
     /* 229021 */   GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(229058), // Rule ID 12078 //
     /* 229026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 229034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229040 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229047 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2140:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 229047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229056 */     GIR_RootConstrainSelectedInstOperands,
     /* 229057 */     // GIR_Coverage, 12078,
     /* 229057 */     GIR_EraseRootFromParent_Done,
     /* 229058 */   // Label 4356: @229058
     /* 229058 */   GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(229095), // Rule ID 12079 //
     /* 229063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229066 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 229071 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229074 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229077 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229080 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229084 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2140:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 229084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229091 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229093 */     GIR_RootConstrainSelectedInstOperands,
     /* 229094 */     // GIR_Coverage, 12079,
     /* 229094 */     GIR_EraseRootFromParent_Done,
     /* 229095 */   // Label 4357: @229095
     /* 229095 */   GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(229132), // Rule ID 12080 //
     /* 229100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 229108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229121 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2140:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 229121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229130 */     GIR_RootConstrainSelectedInstOperands,
     /* 229131 */     // GIR_Coverage, 12080,
     /* 229131 */     GIR_EraseRootFromParent_Done,
     /* 229132 */   // Label 4358: @229132
     /* 229132 */   GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(229169), // Rule ID 12081 //
     /* 229137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 229145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229158 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2140:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 229158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229167 */     GIR_RootConstrainSelectedInstOperands,
     /* 229168 */     // GIR_Coverage, 12081,
     /* 229168 */     GIR_EraseRootFromParent_Done,
     /* 229169 */   // Label 4359: @229169
     /* 229169 */   GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(229206), // Rule ID 12082 //
     /* 229174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp1q),
     /* 229182 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229195 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2140:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 229195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_Q),
     /* 229198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229202 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229204 */     GIR_RootConstrainSelectedInstOperands,
     /* 229205 */     // GIR_Coverage, 12082,
     /* 229205 */     GIR_EraseRootFromParent_Done,
     /* 229206 */   // Label 4360: @229206
     /* 229206 */   GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(229243), // Rule ID 12083 //
     /* 229211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 229225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229232 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2145:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 229232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229239 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229241 */     GIR_RootConstrainSelectedInstOperands,
     /* 229242 */     // GIR_Coverage, 12083,
     /* 229242 */     GIR_EraseRootFromParent_Done,
     /* 229243 */   // Label 4361: @229243
     /* 229243 */   GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(229280), // Rule ID 12084 //
     /* 229248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229269 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2145:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 229269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229278 */     GIR_RootConstrainSelectedInstOperands,
     /* 229279 */     // GIR_Coverage, 12084,
     /* 229279 */     GIR_EraseRootFromParent_Done,
     /* 229280 */   // Label 4362: @229280
     /* 229280 */   GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(229317), // Rule ID 12085 //
     /* 229285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229299 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229302 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229306 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2145:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 229306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229311 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229313 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229315 */     GIR_RootConstrainSelectedInstOperands,
     /* 229316 */     // GIR_Coverage, 12085,
     /* 229316 */     GIR_EraseRootFromParent_Done,
     /* 229317 */   // Label 4363: @229317
     /* 229317 */   GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(229354), // Rule ID 12086 //
     /* 229322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229343 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2145:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 229343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229352 */     GIR_RootConstrainSelectedInstOperands,
     /* 229353 */     // GIR_Coverage, 12086,
     /* 229353 */     GIR_EraseRootFromParent_Done,
     /* 229354 */   // Label 4364: @229354
     /* 229354 */   GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(229391), // Rule ID 12087 //
     /* 229359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229380 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2145:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 229380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229385 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229387 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229389 */     GIR_RootConstrainSelectedInstOperands,
     /* 229390 */     // GIR_Coverage, 12087,
     /* 229390 */     GIR_EraseRootFromParent_Done,
     /* 229391 */   // Label 4365: @229391
     /* 229391 */   GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(229428), // Rule ID 12088 //
     /* 229396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229399 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229404 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229407 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229410 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229417 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2145:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 229417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229426 */     GIR_RootConstrainSelectedInstOperands,
     /* 229427 */     // GIR_Coverage, 12088,
     /* 229427 */     GIR_EraseRootFromParent_Done,
     /* 229428 */   // Label 4366: @229428
     /* 229428 */   GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(229465), // Rule ID 12089 //
     /* 229433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzp2q),
     /* 229441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229454 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2145:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 229454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_Q),
     /* 229457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229463 */     GIR_RootConstrainSelectedInstOperands,
     /* 229464 */     // GIR_Coverage, 12089,
     /* 229464 */     GIR_EraseRootFromParent_Done,
     /* 229465 */   // Label 4367: @229465
     /* 229465 */   GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(229502), // Rule ID 12090 //
     /* 229470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229473 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229478 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 229484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229491 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1980:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 229491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229498 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229500 */     GIR_RootConstrainSelectedInstOperands,
     /* 229501 */     // GIR_Coverage, 12090,
     /* 229501 */     GIR_EraseRootFromParent_Done,
     /* 229502 */   // Label 4368: @229502
     /* 229502 */   GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(229539), // Rule ID 12091 //
     /* 229507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229528 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1980:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 229528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229537 */     GIR_RootConstrainSelectedInstOperands,
     /* 229538 */     // GIR_Coverage, 12091,
     /* 229538 */     GIR_EraseRootFromParent_Done,
     /* 229539 */   // Label 4369: @229539
     /* 229539 */   GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(229576), // Rule ID 12092 //
     /* 229544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229565 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1980:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 229565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229574 */     GIR_RootConstrainSelectedInstOperands,
     /* 229575 */     // GIR_Coverage, 12092,
     /* 229575 */     GIR_EraseRootFromParent_Done,
     /* 229576 */   // Label 4370: @229576
     /* 229576 */   GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(229613), // Rule ID 12093 //
     /* 229581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229598 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229602 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1980:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 229602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229607 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229609 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229611 */     GIR_RootConstrainSelectedInstOperands,
     /* 229612 */     // GIR_Coverage, 12093,
     /* 229612 */     GIR_EraseRootFromParent_Done,
     /* 229613 */   // Label 4371: @229613
     /* 229613 */   GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(229650), // Rule ID 12094 //
     /* 229618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229639 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1980:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 229639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229648 */     GIR_RootConstrainSelectedInstOperands,
     /* 229649 */     // GIR_Coverage, 12094,
     /* 229649 */     GIR_EraseRootFromParent_Done,
     /* 229650 */   // Label 4372: @229650
     /* 229650 */   GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(229687), // Rule ID 12095 //
     /* 229655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229658 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229663 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229666 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229676 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1980:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 229676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229681 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229683 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229685 */     GIR_RootConstrainSelectedInstOperands,
     /* 229686 */     // GIR_Coverage, 12095,
     /* 229686 */     GIR_EraseRootFromParent_Done,
     /* 229687 */   // Label 4373: @229687
     /* 229687 */   GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(229724), // Rule ID 12096 //
     /* 229692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn1q),
     /* 229700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229713 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1980:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN1_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 229713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_Q),
     /* 229716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229722 */     GIR_RootConstrainSelectedInstOperands,
     /* 229723 */     // GIR_Coverage, 12096,
     /* 229723 */     GIR_EraseRootFromParent_Done,
     /* 229724 */   // Label 4374: @229724
     /* 229724 */   GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(229761), // Rule ID 12097 //
     /* 229729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 229743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 229746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229750 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1985:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 229750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229757 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229759 */     GIR_RootConstrainSelectedInstOperands,
     /* 229760 */     // GIR_Coverage, 12097,
     /* 229760 */     GIR_EraseRootFromParent_Done,
     /* 229761 */   // Label 4375: @229761
     /* 229761 */   GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(229798), // Rule ID 12098 //
     /* 229766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229787 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1985:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 229787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229796 */     GIR_RootConstrainSelectedInstOperands,
     /* 229797 */     // GIR_Coverage, 12098,
     /* 229797 */     GIR_EraseRootFromParent_Done,
     /* 229798 */   // Label 4376: @229798
     /* 229798 */   GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(229835), // Rule ID 12099 //
     /* 229803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 229814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 229817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 229820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229824 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1985:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 229824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229829 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229831 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229833 */     GIR_RootConstrainSelectedInstOperands,
     /* 229834 */     // GIR_Coverage, 12099,
     /* 229834 */     GIR_EraseRootFromParent_Done,
     /* 229835 */   // Label 4377: @229835
     /* 229835 */   GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(229872), // Rule ID 12100 //
     /* 229840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229843 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229848 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229851 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229854 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229857 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229861 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1985:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 229861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229868 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229870 */     GIR_RootConstrainSelectedInstOperands,
     /* 229871 */     // GIR_Coverage, 12100,
     /* 229871 */     GIR_EraseRootFromParent_Done,
     /* 229872 */   // Label 4378: @229872
     /* 229872 */   GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(229909), // Rule ID 12101 //
     /* 229877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 229888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 229891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 229894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229898 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1985:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 229898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229903 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229905 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229907 */     GIR_RootConstrainSelectedInstOperands,
     /* 229908 */     // GIR_Coverage, 12101,
     /* 229908 */     GIR_EraseRootFromParent_Done,
     /* 229909 */   // Label 4379: @229909
     /* 229909 */   GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(229946), // Rule ID 12102 //
     /* 229914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229931 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229935 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1985:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 229935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229940 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229944 */     GIR_RootConstrainSelectedInstOperands,
     /* 229945 */     // GIR_Coverage, 12102,
     /* 229945 */     GIR_EraseRootFromParent_Done,
     /* 229946 */   // Label 4380: @229946
     /* 229946 */   GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(229983), // Rule ID 12103 //
     /* 229951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE_or_SME),
     /* 229954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_trn2q),
     /* 229959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 229962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 229965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 229968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 229972 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1985:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN2_ZZZ_Q:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 229972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_Q),
     /* 229975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 229977 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 229979 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 229981 */     GIR_RootConstrainSelectedInstOperands,
     /* 229982 */     // GIR_Coverage, 12103,
     /* 229982 */     GIR_EraseRootFromParent_Done,
     /* 229983 */   // Label 4381: @229983
     /* 229983 */   GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(230020), // Rule ID 12123 //
     /* 229988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 229991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 229996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 229999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230009 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1879:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQRDMULH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_B),
     /* 230012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230016 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230018 */     GIR_RootConstrainSelectedInstOperands,
     /* 230019 */     // GIR_Coverage, 12123,
     /* 230019 */     GIR_EraseRootFromParent_Done,
     /* 230020 */   // Label 4382: @230020
     /* 230020 */   GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(230057), // Rule ID 12124 //
     /* 230025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 230033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230042 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230046 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1879:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQRDMULH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_H),
     /* 230049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230051 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230053 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230055 */     GIR_RootConstrainSelectedInstOperands,
     /* 230056 */     // GIR_Coverage, 12124,
     /* 230056 */     GIR_EraseRootFromParent_Done,
     /* 230057 */   // Label 4383: @230057
     /* 230057 */   GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(230094), // Rule ID 12125 //
     /* 230062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 230070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230083 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1879:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQRDMULH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_S),
     /* 230086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230092 */     GIR_RootConstrainSelectedInstOperands,
     /* 230093 */     // GIR_Coverage, 12125,
     /* 230093 */     GIR_EraseRootFromParent_Done,
     /* 230094 */   // Label 4384: @230094
     /* 230094 */   GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(230131), // Rule ID 12126 //
     /* 230099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh),
     /* 230107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 230113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 230116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230120 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1879:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQRDMULH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 230120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZ_D),
     /* 230123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230127 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230129 */     GIR_RootConstrainSelectedInstOperands,
     /* 230130 */     // GIR_Coverage, 12126,
     /* 230130 */     GIR_EraseRootFromParent_Done,
     /* 230131 */   // Label 4385: @230131
     /* 230131 */   GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(230168), // Rule ID 12440 //
     /* 230136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 230144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230150 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230157 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1742:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_H),
     /* 230160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230166 */     GIR_RootConstrainSelectedInstOperands,
     /* 230167 */     // GIR_Coverage, 12440,
     /* 230167 */     GIR_EraseRootFromParent_Done,
     /* 230168 */   // Label 4386: @230168
     /* 230168 */   GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(230205), // Rule ID 12441 //
     /* 230173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230176 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 230181 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230184 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230187 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230194 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1742:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_S),
     /* 230197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230199 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230201 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230203 */     GIR_RootConstrainSelectedInstOperands,
     /* 230204 */     // GIR_Coverage, 12441,
     /* 230204 */     GIR_EraseRootFromParent_Done,
     /* 230205 */   // Label 4387: @230205
     /* 230205 */   GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(230242), // Rule ID 12442 //
     /* 230210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230213 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saddlt),
     /* 230218 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230221 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230224 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230231 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1742:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLT_ZZZ_D),
     /* 230234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230240 */     GIR_RootConstrainSelectedInstOperands,
     /* 230241 */     // GIR_Coverage, 12442,
     /* 230241 */     GIR_EraseRootFromParent_Done,
     /* 230242 */   // Label 4388: @230242
     /* 230242 */   GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(230279), // Rule ID 12443 //
     /* 230247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 230255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230268 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1994:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UADDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_H),
     /* 230271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230273 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230275 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230277 */     GIR_RootConstrainSelectedInstOperands,
     /* 230278 */     // GIR_Coverage, 12443,
     /* 230278 */     GIR_EraseRootFromParent_Done,
     /* 230279 */   // Label 4389: @230279
     /* 230279 */   GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(230316), // Rule ID 12444 //
     /* 230284 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230287 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 230292 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230295 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230298 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230301 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230305 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1994:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UADDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_S),
     /* 230308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230310 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230312 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230314 */     GIR_RootConstrainSelectedInstOperands,
     /* 230315 */     // GIR_Coverage, 12444,
     /* 230315 */     GIR_EraseRootFromParent_Done,
     /* 230316 */   // Label 4390: @230316
     /* 230316 */   GIM_Try, /*On fail goto*//*Label 4391*/ GIMT_Encode4(230353), // Rule ID 12445 //
     /* 230321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlb),
     /* 230329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230335 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230342 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1994:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UADDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLB_ZZZ_D),
     /* 230345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230347 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230349 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230351 */     GIR_RootConstrainSelectedInstOperands,
     /* 230352 */     // GIR_Coverage, 12445,
     /* 230352 */     GIR_EraseRootFromParent_Done,
     /* 230353 */   // Label 4391: @230353
     /* 230353 */   GIM_Try, /*On fail goto*//*Label 4392*/ GIMT_Encode4(230390), // Rule ID 12446 //
     /* 230358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 230366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230379 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1995:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UADDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_H),
     /* 230382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230386 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230388 */     GIR_RootConstrainSelectedInstOperands,
     /* 230389 */     // GIR_Coverage, 12446,
     /* 230389 */     GIR_EraseRootFromParent_Done,
     /* 230390 */   // Label 4392: @230390
     /* 230390 */   GIM_Try, /*On fail goto*//*Label 4393*/ GIMT_Encode4(230427), // Rule ID 12447 //
     /* 230395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 230403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230406 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230409 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230416 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1995:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UADDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_S),
     /* 230419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230423 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230425 */     GIR_RootConstrainSelectedInstOperands,
     /* 230426 */     // GIR_Coverage, 12447,
     /* 230426 */     GIR_EraseRootFromParent_Done,
     /* 230427 */   // Label 4393: @230427
     /* 230427 */   GIM_Try, /*On fail goto*//*Label 4394*/ GIMT_Encode4(230464), // Rule ID 12448 //
     /* 230432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaddlt),
     /* 230440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230453 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1995:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UADDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLT_ZZZ_D),
     /* 230456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230460 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230462 */     GIR_RootConstrainSelectedInstOperands,
     /* 230463 */     // GIR_Coverage, 12448,
     /* 230463 */     GIR_EraseRootFromParent_Done,
     /* 230464 */   // Label 4394: @230464
     /* 230464 */   GIM_Try, /*On fail goto*//*Label 4395*/ GIMT_Encode4(230501), // Rule ID 12449 //
     /* 230469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 230477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230486 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230490 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1923:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_H),
     /* 230493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230497 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230499 */     GIR_RootConstrainSelectedInstOperands,
     /* 230500 */     // GIR_Coverage, 12449,
     /* 230500 */     GIR_EraseRootFromParent_Done,
     /* 230501 */   // Label 4395: @230501
     /* 230501 */   GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(230538), // Rule ID 12450 //
     /* 230506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230509 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 230514 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230517 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230520 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230527 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1923:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_S),
     /* 230530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230536 */     GIR_RootConstrainSelectedInstOperands,
     /* 230537 */     // GIR_Coverage, 12450,
     /* 230537 */     GIR_EraseRootFromParent_Done,
     /* 230538 */   // Label 4396: @230538
     /* 230538 */   GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(230575), // Rule ID 12451 //
     /* 230543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230546 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublb),
     /* 230551 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230554 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230557 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230560 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230564 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1923:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLB_ZZZ_D),
     /* 230567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230573 */     GIR_RootConstrainSelectedInstOperands,
     /* 230574 */     // GIR_Coverage, 12451,
     /* 230574 */     GIR_EraseRootFromParent_Done,
     /* 230575 */   // Label 4397: @230575
     /* 230575 */   GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(230612), // Rule ID 12452 //
     /* 230580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 230588 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230591 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230594 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230601 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1925:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_H),
     /* 230604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230610 */     GIR_RootConstrainSelectedInstOperands,
     /* 230611 */     // GIR_Coverage, 12452,
     /* 230611 */     GIR_EraseRootFromParent_Done,
     /* 230612 */   // Label 4398: @230612
     /* 230612 */   GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(230649), // Rule ID 12453 //
     /* 230617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 230625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230638 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1925:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230638 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_S),
     /* 230641 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230645 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230647 */     GIR_RootConstrainSelectedInstOperands,
     /* 230648 */     // GIR_Coverage, 12453,
     /* 230648 */     GIR_EraseRootFromParent_Done,
     /* 230649 */   // Label 4399: @230649
     /* 230649 */   GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(230686), // Rule ID 12454 //
     /* 230654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublt),
     /* 230662 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230665 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230668 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230675 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1925:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLT_ZZZ_D),
     /* 230678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230680 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230682 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230684 */     GIR_RootConstrainSelectedInstOperands,
     /* 230685 */     // GIR_Coverage, 12454,
     /* 230685 */     GIR_EraseRootFromParent_Done,
     /* 230686 */   // Label 4400: @230686
     /* 230686 */   GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(230723), // Rule ID 12455 //
     /* 230691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230694 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 230699 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230702 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230705 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230708 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230712 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2123:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230712 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_H),
     /* 230715 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230717 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230719 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230721 */     GIR_RootConstrainSelectedInstOperands,
     /* 230722 */     // GIR_Coverage, 12455,
     /* 230722 */     GIR_EraseRootFromParent_Done,
     /* 230723 */   // Label 4401: @230723
     /* 230723 */   GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(230760), // Rule ID 12456 //
     /* 230728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230731 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 230736 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230739 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230742 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230749 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2123:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_S),
     /* 230752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230754 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230756 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230758 */     GIR_RootConstrainSelectedInstOperands,
     /* 230759 */     // GIR_Coverage, 12456,
     /* 230759 */     GIR_EraseRootFromParent_Done,
     /* 230760 */   // Label 4402: @230760
     /* 230760 */   GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(230797), // Rule ID 12457 //
     /* 230765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublb),
     /* 230773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230786 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2123:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLB_ZZZ_D),
     /* 230789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230793 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230795 */     GIR_RootConstrainSelectedInstOperands,
     /* 230796 */     // GIR_Coverage, 12457,
     /* 230796 */     GIR_EraseRootFromParent_Done,
     /* 230797 */   // Label 4403: @230797
     /* 230797 */   GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(230834), // Rule ID 12458 //
     /* 230802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 230810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230823 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2124:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_H),
     /* 230826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230832 */     GIR_RootConstrainSelectedInstOperands,
     /* 230833 */     // GIR_Coverage, 12458,
     /* 230833 */     GIR_EraseRootFromParent_Done,
     /* 230834 */   // Label 4404: @230834
     /* 230834 */   GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(230871), // Rule ID 12459 //
     /* 230839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 230847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230860 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2124:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_S),
     /* 230863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230869 */     GIR_RootConstrainSelectedInstOperands,
     /* 230870 */     // GIR_Coverage, 12459,
     /* 230870 */     GIR_EraseRootFromParent_Done,
     /* 230871 */   // Label 4405: @230871
     /* 230871 */   GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(230908), // Rule ID 12460 //
     /* 230876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230879 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usublt),
     /* 230884 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230887 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 230890 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 230893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230897 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2124:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 230897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBLT_ZZZ_D),
     /* 230900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230906 */     GIR_RootConstrainSelectedInstOperands,
     /* 230907 */     // GIR_Coverage, 12460,
     /* 230907 */     GIR_EraseRootFromParent_Done,
     /* 230908 */   // Label 4406: @230908
     /* 230908 */   GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(230945), // Rule ID 12461 //
     /* 230913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 230921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 230924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 230927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 230930 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230934 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1737:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 230934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_H),
     /* 230937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230939 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230941 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230943 */     GIR_RootConstrainSelectedInstOperands,
     /* 230944 */     // GIR_Coverage, 12461,
     /* 230944 */     GIR_EraseRootFromParent_Done,
     /* 230945 */   // Label 4407: @230945
     /* 230945 */   GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(230982), // Rule ID 12462 //
     /* 230950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230953 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 230958 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 230961 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 230964 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 230967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 230971 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1737:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 230971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_S),
     /* 230974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 230976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 230978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 230980 */     GIR_RootConstrainSelectedInstOperands,
     /* 230981 */     // GIR_Coverage, 12462,
     /* 230981 */     GIR_EraseRootFromParent_Done,
     /* 230982 */   // Label 4408: @230982
     /* 230982 */   GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(231019), // Rule ID 12463 //
     /* 230987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 230990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlb),
     /* 230995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 230998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231001 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231008 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1737:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLB_ZZZ_D),
     /* 231011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231015 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231017 */     GIR_RootConstrainSelectedInstOperands,
     /* 231018 */     // GIR_Coverage, 12463,
     /* 231018 */     GIR_EraseRootFromParent_Done,
     /* 231019 */   // Label 4409: @231019
     /* 231019 */   GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(231056), // Rule ID 12464 //
     /* 231024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 231032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231045 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1738:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_H),
     /* 231048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231050 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231052 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231054 */     GIR_RootConstrainSelectedInstOperands,
     /* 231055 */     // GIR_Coverage, 12464,
     /* 231055 */     GIR_EraseRootFromParent_Done,
     /* 231056 */   // Label 4410: @231056
     /* 231056 */   GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(231093), // Rule ID 12465 //
     /* 231061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 231069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231082 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1738:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_S),
     /* 231085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231091 */     GIR_RootConstrainSelectedInstOperands,
     /* 231092 */     // GIR_Coverage, 12465,
     /* 231092 */     GIR_EraseRootFromParent_Done,
     /* 231093 */   // Label 4411: @231093
     /* 231093 */   GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(231130), // Rule ID 12466 //
     /* 231098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabdlt),
     /* 231106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231119 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1738:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLT_ZZZ_D),
     /* 231122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231124 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231128 */     GIR_RootConstrainSelectedInstOperands,
     /* 231129 */     // GIR_Coverage, 12466,
     /* 231129 */     GIR_EraseRootFromParent_Done,
     /* 231130 */   // Label 4412: @231130
     /* 231130 */   GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(231167), // Rule ID 12467 //
     /* 231135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 231143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231156 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1991:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UABDLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_H),
     /* 231159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231161 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231163 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231165 */     GIR_RootConstrainSelectedInstOperands,
     /* 231166 */     // GIR_Coverage, 12467,
     /* 231166 */     GIR_EraseRootFromParent_Done,
     /* 231167 */   // Label 4413: @231167
     /* 231167 */   GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(231204), // Rule ID 12468 //
     /* 231172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 231180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231193 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1991:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UABDLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_S),
     /* 231196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231200 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231202 */     GIR_RootConstrainSelectedInstOperands,
     /* 231203 */     // GIR_Coverage, 12468,
     /* 231203 */     GIR_EraseRootFromParent_Done,
     /* 231204 */   // Label 4414: @231204
     /* 231204 */   GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(231241), // Rule ID 12469 //
     /* 231209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlb),
     /* 231217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231226 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231230 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1991:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UABDLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLB_ZZZ_D),
     /* 231233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231237 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231239 */     GIR_RootConstrainSelectedInstOperands,
     /* 231240 */     // GIR_Coverage, 12469,
     /* 231240 */     GIR_EraseRootFromParent_Done,
     /* 231241 */   // Label 4415: @231241
     /* 231241 */   GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(231278), // Rule ID 12470 //
     /* 231246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231249 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 231254 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231257 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231260 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231267 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1992:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UABDLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_H),
     /* 231270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231274 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231276 */     GIR_RootConstrainSelectedInstOperands,
     /* 231277 */     // GIR_Coverage, 12470,
     /* 231277 */     GIR_EraseRootFromParent_Done,
     /* 231278 */   // Label 4416: @231278
     /* 231278 */   GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(231315), // Rule ID 12471 //
     /* 231283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 231291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231304 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1992:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UABDLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_S),
     /* 231307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231313 */     GIR_RootConstrainSelectedInstOperands,
     /* 231314 */     // GIR_Coverage, 12471,
     /* 231314 */     GIR_EraseRootFromParent_Done,
     /* 231315 */   // Label 4417: @231315
     /* 231315 */   GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(231352), // Rule ID 12472 //
     /* 231320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabdlt),
     /* 231328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231341 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1992:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UABDLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLT_ZZZ_D),
     /* 231344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231346 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231348 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231350 */     GIR_RootConstrainSelectedInstOperands,
     /* 231351 */     // GIR_Coverage, 12472,
     /* 231351 */     GIR_EraseRootFromParent_Done,
     /* 231352 */   // Label 4418: @231352
     /* 231352 */   GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(231389), // Rule ID 12482 //
     /* 231357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 231365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231378 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1927:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_H),
     /* 231381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231385 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231387 */     GIR_RootConstrainSelectedInstOperands,
     /* 231388 */     // GIR_Coverage, 12482,
     /* 231388 */     GIR_EraseRootFromParent_Done,
     /* 231389 */   // Label 4419: @231389
     /* 231389 */   GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(231426), // Rule ID 12483 //
     /* 231394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231397 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 231402 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231405 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231408 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231415 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1927:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_S),
     /* 231418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231420 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231422 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231424 */     GIR_RootConstrainSelectedInstOperands,
     /* 231425 */     // GIR_Coverage, 12483,
     /* 231425 */     GIR_EraseRootFromParent_Done,
     /* 231426 */   // Label 4420: @231426
     /* 231426 */   GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(231463), // Rule ID 12484 //
     /* 231431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwb),
     /* 231439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231452 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1927:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWB_ZZZ_D),
     /* 231455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231457 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231461 */     GIR_RootConstrainSelectedInstOperands,
     /* 231462 */     // GIR_Coverage, 12484,
     /* 231462 */     GIR_EraseRootFromParent_Done,
     /* 231463 */   // Label 4421: @231463
     /* 231463 */   GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(231500), // Rule ID 12485 //
     /* 231468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231471 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 231476 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231479 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231482 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231489 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1928:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_H),
     /* 231492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231498 */     GIR_RootConstrainSelectedInstOperands,
     /* 231499 */     // GIR_Coverage, 12485,
     /* 231499 */     GIR_EraseRootFromParent_Done,
     /* 231500 */   // Label 4422: @231500
     /* 231500 */   GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(231537), // Rule ID 12486 //
     /* 231505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 231513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231519 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231522 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231526 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1928:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_S),
     /* 231529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231533 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231535 */     GIR_RootConstrainSelectedInstOperands,
     /* 231536 */     // GIR_Coverage, 12486,
     /* 231536 */     GIR_EraseRootFromParent_Done,
     /* 231537 */   // Label 4423: @231537
     /* 231537 */   GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(231574), // Rule ID 12487 //
     /* 231542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubwt),
     /* 231550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231563 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1928:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBWT_ZZZ_D),
     /* 231566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231572 */     GIR_RootConstrainSelectedInstOperands,
     /* 231573 */     // GIR_Coverage, 12487,
     /* 231573 */     GIR_EraseRootFromParent_Done,
     /* 231574 */   // Label 4424: @231574
     /* 231574 */   GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(231611), // Rule ID 12488 //
     /* 231579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 231587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231600 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2125:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBWB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_H),
     /* 231603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231607 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231609 */     GIR_RootConstrainSelectedInstOperands,
     /* 231610 */     // GIR_Coverage, 12488,
     /* 231610 */     GIR_EraseRootFromParent_Done,
     /* 231611 */   // Label 4425: @231611
     /* 231611 */   GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(231648), // Rule ID 12489 //
     /* 231616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 231624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231637 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2125:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBWB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_S),
     /* 231640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231642 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231644 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231646 */     GIR_RootConstrainSelectedInstOperands,
     /* 231647 */     // GIR_Coverage, 12489,
     /* 231647 */     GIR_EraseRootFromParent_Done,
     /* 231648 */   // Label 4426: @231648
     /* 231648 */   GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(231685), // Rule ID 12490 //
     /* 231653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwb),
     /* 231661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231674 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2125:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBWB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWB_ZZZ_D),
     /* 231677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231681 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231683 */     GIR_RootConstrainSelectedInstOperands,
     /* 231684 */     // GIR_Coverage, 12490,
     /* 231684 */     GIR_EraseRootFromParent_Done,
     /* 231685 */   // Label 4427: @231685
     /* 231685 */   GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(231722), // Rule ID 12491 //
     /* 231690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 231698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231711 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2126:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (USUBWT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_H),
     /* 231714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231718 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231720 */     GIR_RootConstrainSelectedInstOperands,
     /* 231721 */     // GIR_Coverage, 12491,
     /* 231721 */     GIR_EraseRootFromParent_Done,
     /* 231722 */   // Label 4428: @231722
     /* 231722 */   GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(231759), // Rule ID 12492 //
     /* 231727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 231735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231748 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2126:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (USUBWT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_S),
     /* 231751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231757 */     GIR_RootConstrainSelectedInstOperands,
     /* 231758 */     // GIR_Coverage, 12492,
     /* 231758 */     GIR_EraseRootFromParent_Done,
     /* 231759 */   // Label 4429: @231759
     /* 231759 */   GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(231796), // Rule ID 12493 //
     /* 231764 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231767 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usubwt),
     /* 231772 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231775 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 231778 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231785 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2126:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (USUBWT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USUBWT_ZZZ_D),
     /* 231788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231790 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231792 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231794 */     GIR_RootConstrainSelectedInstOperands,
     /* 231795 */     // GIR_Coverage, 12493,
     /* 231795 */     GIR_EraseRootFromParent_Done,
     /* 231796 */   // Label 4430: @231796
     /* 231796 */   GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(231833), // Rule ID 12500 //
     /* 231801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 231809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231822 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1854:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_H),
     /* 231825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231831 */     GIR_RootConstrainSelectedInstOperands,
     /* 231832 */     // GIR_Coverage, 12500,
     /* 231832 */     GIR_EraseRootFromParent_Done,
     /* 231833 */   // Label 4431: @231833
     /* 231833 */   GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(231870), // Rule ID 12501 //
     /* 231838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 231846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231859 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1854:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_S),
     /* 231862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231866 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231868 */     GIR_RootConstrainSelectedInstOperands,
     /* 231869 */     // GIR_Coverage, 12501,
     /* 231869 */     GIR_EraseRootFromParent_Done,
     /* 231870 */   // Label 4432: @231870
     /* 231870 */   GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(231907), // Rule ID 12502 //
     /* 231875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231878 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb),
     /* 231883 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231886 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 231889 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 231892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231896 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1854:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 231896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZ_D),
     /* 231899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231903 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231905 */     GIR_RootConstrainSelectedInstOperands,
     /* 231906 */     // GIR_Coverage, 12502,
     /* 231906 */     GIR_EraseRootFromParent_Done,
     /* 231907 */   // Label 4433: @231907
     /* 231907 */   GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(231944), // Rule ID 12503 //
     /* 231912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 231920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 231923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 231926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 231929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231933 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1856:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQDMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 231933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_H),
     /* 231936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231942 */     GIR_RootConstrainSelectedInstOperands,
     /* 231943 */     // GIR_Coverage, 12503,
     /* 231943 */     GIR_EraseRootFromParent_Done,
     /* 231944 */   // Label 4434: @231944
     /* 231944 */   GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(231981), // Rule ID 12504 //
     /* 231949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 231957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 231960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 231963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 231966 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 231970 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1856:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQDMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 231970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_S),
     /* 231973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 231975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 231977 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 231979 */     GIR_RootConstrainSelectedInstOperands,
     /* 231980 */     // GIR_Coverage, 12504,
     /* 231980 */     GIR_EraseRootFromParent_Done,
     /* 231981 */   // Label 4435: @231981
     /* 231981 */   GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(232018), // Rule ID 12505 //
     /* 231986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 231989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt),
     /* 231994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 231997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232007 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1856:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQDMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZ_D),
     /* 232010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232012 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232014 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232016 */     GIR_RootConstrainSelectedInstOperands,
     /* 232017 */     // GIR_Coverage, 12505,
     /* 232017 */     GIR_EraseRootFromParent_Done,
     /* 232018 */   // Label 4436: @232018
     /* 232018 */   GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(232055), // Rule ID 12506 //
     /* 232023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 232031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 232040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232044 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1807:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_H),
     /* 232047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232049 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232051 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232053 */     GIR_RootConstrainSelectedInstOperands,
     /* 232054 */     // GIR_Coverage, 12506,
     /* 232054 */     GIR_EraseRootFromParent_Done,
     /* 232055 */   // Label 4437: @232055
     /* 232055 */   GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(232092), // Rule ID 12507 //
     /* 232060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232063 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 232068 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232071 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232074 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232081 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1807:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_S),
     /* 232084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232090 */     GIR_RootConstrainSelectedInstOperands,
     /* 232091 */     // GIR_Coverage, 12507,
     /* 232091 */     GIR_EraseRootFromParent_Done,
     /* 232092 */   // Label 4438: @232092
     /* 232092 */   GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(232129), // Rule ID 12508 //
     /* 232097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb),
     /* 232105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232118 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1807:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZ_D),
     /* 232121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232127 */     GIR_RootConstrainSelectedInstOperands,
     /* 232128 */     // GIR_Coverage, 12508,
     /* 232128 */     GIR_EraseRootFromParent_Done,
     /* 232129 */   // Label 4439: @232129
     /* 232129 */   GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(232166), // Rule ID 12509 //
     /* 232134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 232142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 232151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232155 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1809:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_H),
     /* 232158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232160 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232162 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232164 */     GIR_RootConstrainSelectedInstOperands,
     /* 232165 */     // GIR_Coverage, 12509,
     /* 232165 */     GIR_EraseRootFromParent_Done,
     /* 232166 */   // Label 4440: @232166
     /* 232166 */   GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(232203), // Rule ID 12510 //
     /* 232171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 232179 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232182 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232185 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232192 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1809:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_S),
     /* 232195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232199 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232201 */     GIR_RootConstrainSelectedInstOperands,
     /* 232202 */     // GIR_Coverage, 12510,
     /* 232202 */     GIR_EraseRootFromParent_Done,
     /* 232203 */   // Label 4441: @232203
     /* 232203 */   GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(232240), // Rule ID 12511 //
     /* 232208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232211 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt),
     /* 232216 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232219 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232222 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232229 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1809:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232229 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZ_D),
     /* 232232 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232234 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232238 */     GIR_RootConstrainSelectedInstOperands,
     /* 232239 */     // GIR_Coverage, 12511,
     /* 232239 */     GIR_EraseRootFromParent_Done,
     /* 232240 */   // Label 4442: @232240
     /* 232240 */   GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(232277), // Rule ID 12512 //
     /* 232245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 232253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 232262 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232266 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2049:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMULLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232266 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_H),
     /* 232269 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232271 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232273 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232275 */     GIR_RootConstrainSelectedInstOperands,
     /* 232276 */     // GIR_Coverage, 12512,
     /* 232276 */     GIR_EraseRootFromParent_Done,
     /* 232277 */   // Label 4443: @232277
     /* 232277 */   GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(232314), // Rule ID 12513 //
     /* 232282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232285 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 232290 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232303 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2049:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMULLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_S),
     /* 232306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232312 */     GIR_RootConstrainSelectedInstOperands,
     /* 232313 */     // GIR_Coverage, 12513,
     /* 232313 */     GIR_EraseRootFromParent_Done,
     /* 232314 */   // Label 4444: @232314
     /* 232314 */   GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(232351), // Rule ID 12514 //
     /* 232319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232322 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb),
     /* 232327 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232330 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232333 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232340 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2049:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMULLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZ_D),
     /* 232343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232349 */     GIR_RootConstrainSelectedInstOperands,
     /* 232350 */     // GIR_Coverage, 12514,
     /* 232350 */     GIR_EraseRootFromParent_Done,
     /* 232351 */   // Label 4445: @232351
     /* 232351 */   GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(232388), // Rule ID 12515 //
     /* 232356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 232364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 232373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232377 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2051:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMULLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_H),
     /* 232380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232386 */     GIR_RootConstrainSelectedInstOperands,
     /* 232387 */     // GIR_Coverage, 12515,
     /* 232387 */     GIR_EraseRootFromParent_Done,
     /* 232388 */   // Label 4446: @232388
     /* 232388 */   GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(232425), // Rule ID 12516 //
     /* 232393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 232401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232407 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232414 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2051:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMULLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_S),
     /* 232417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232419 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232421 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232423 */     GIR_RootConstrainSelectedInstOperands,
     /* 232424 */     // GIR_Coverage, 12516,
     /* 232424 */     GIR_EraseRootFromParent_Done,
     /* 232425 */   // Label 4447: @232425
     /* 232425 */   GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(232462), // Rule ID 12517 //
     /* 232430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt),
     /* 232438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 232441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232451 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2051:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMULLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZ_D),
     /* 232454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232460 */     GIR_RootConstrainSelectedInstOperands,
     /* 232461 */     // GIR_Coverage, 12517,
     /* 232461 */     GIR_EraseRootFromParent_Done,
     /* 232462 */   // Label 4448: @232462
     /* 232462 */   GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(232499), // Rule ID 12518 //
     /* 232467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232470 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 232475 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232478 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232481 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 232484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232488 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1685:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (PMULLT_ZZZ_H:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 232488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_H),
     /* 232491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232497 */     GIR_RootConstrainSelectedInstOperands,
     /* 232498 */     // GIR_Coverage, 12518,
     /* 232498 */     GIR_EraseRootFromParent_Done,
     /* 232499 */   // Label 4449: @232499
     /* 232499 */   GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(232536), // Rule ID 12519 //
     /* 232504 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232507 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 232512 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232515 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232518 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232521 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232525 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1685:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (PMULLT_ZZZ_D:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232525 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_D),
     /* 232528 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232530 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232532 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232534 */     GIR_RootConstrainSelectedInstOperands,
     /* 232535 */     // GIR_Coverage, 12519,
     /* 232535 */     GIR_EraseRootFromParent_Done,
     /* 232536 */   // Label 4450: @232536
     /* 232536 */   GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(232573), // Rule ID 12620 //
     /* 232541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 232549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232555 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232562 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1715:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (RADDHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232562 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_B),
     /* 232565 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232569 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232571 */     GIR_RootConstrainSelectedInstOperands,
     /* 232572 */     // GIR_Coverage, 12620,
     /* 232572 */     GIR_EraseRootFromParent_Done,
     /* 232573 */   // Label 4451: @232573
     /* 232573 */   GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(232610), // Rule ID 12621 //
     /* 232578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 232586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232599 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1715:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (RADDHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_H),
     /* 232602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232606 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232608 */     GIR_RootConstrainSelectedInstOperands,
     /* 232609 */     // GIR_Coverage, 12621,
     /* 232609 */     GIR_EraseRootFromParent_Done,
     /* 232610 */   // Label 4452: @232610
     /* 232610 */   GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(232647), // Rule ID 12622 //
     /* 232615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232618 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnb),
     /* 232623 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232626 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232629 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 232632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232636 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1715:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RADDHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNB_ZZZ_S),
     /* 232639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232641 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232643 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232645 */     GIR_RootConstrainSelectedInstOperands,
     /* 232646 */     // GIR_Coverage, 12622,
     /* 232646 */     GIR_EraseRootFromParent_Done,
     /* 232647 */   // Label 4453: @232647
     /* 232647 */   GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(232684), // Rule ID 12623 //
     /* 232652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 232660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232673 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1959:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_B),
     /* 232676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232678 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232682 */     GIR_RootConstrainSelectedInstOperands,
     /* 232683 */     // GIR_Coverage, 12623,
     /* 232683 */     GIR_EraseRootFromParent_Done,
     /* 232684 */   // Label 4454: @232684
     /* 232684 */   GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(232721), // Rule ID 12624 //
     /* 232689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 232697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232706 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232710 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1959:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_H),
     /* 232713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232717 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232719 */     GIR_RootConstrainSelectedInstOperands,
     /* 232720 */     // GIR_Coverage, 12624,
     /* 232720 */     GIR_EraseRootFromParent_Done,
     /* 232721 */   // Label 4455: @232721
     /* 232721 */   GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(232758), // Rule ID 12625 //
     /* 232726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnb),
     /* 232734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 232743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232747 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1959:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNB_ZZZ_S),
     /* 232750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232754 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232756 */     GIR_RootConstrainSelectedInstOperands,
     /* 232757 */     // GIR_Coverage, 12625,
     /* 232757 */     GIR_EraseRootFromParent_Done,
     /* 232758 */   // Label 4456: @232758
     /* 232758 */   GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(232795), // Rule ID 12626 //
     /* 232763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 232771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232784 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1730:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (RSUBHNB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_B),
     /* 232787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232791 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232793 */     GIR_RootConstrainSelectedInstOperands,
     /* 232794 */     // GIR_Coverage, 12626,
     /* 232794 */     GIR_EraseRootFromParent_Done,
     /* 232795 */   // Label 4457: @232795
     /* 232795 */   GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(232832), // Rule ID 12627 //
     /* 232800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232803 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 232808 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232811 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232814 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232821 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1730:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (RSUBHNB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_H),
     /* 232824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232830 */     GIR_RootConstrainSelectedInstOperands,
     /* 232831 */     // GIR_Coverage, 12627,
     /* 232831 */     GIR_EraseRootFromParent_Done,
     /* 232832 */   // Label 4458: @232832
     /* 232832 */   GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(232869), // Rule ID 12628 //
     /* 232837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnb),
     /* 232845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 232851 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 232854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232858 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1730:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RSUBHNB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNB_ZZZ_S),
     /* 232861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232865 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232867 */     GIR_RootConstrainSelectedInstOperands,
     /* 232868 */     // GIR_Coverage, 12628,
     /* 232868 */     GIR_EraseRootFromParent_Done,
     /* 232869 */   // Label 4459: @232869
     /* 232869 */   GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(232906), // Rule ID 12644 //
     /* 232874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232877 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 232882 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232885 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232888 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 232891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232895 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2104:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQXTNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 232895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_B),
     /* 232898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232904 */     GIR_RootConstrainSelectedInstOperands,
     /* 232905 */     // GIR_Coverage, 12644,
     /* 232905 */     GIR_EraseRootFromParent_Done,
     /* 232906 */   // Label 4460: @232906
     /* 232906 */   GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(232943), // Rule ID 12645 //
     /* 232911 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232914 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 232919 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 232922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 232925 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 232928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232932 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2104:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQXTNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 232932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_H),
     /* 232935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232939 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232941 */     GIR_RootConstrainSelectedInstOperands,
     /* 232942 */     // GIR_Coverage, 12645,
     /* 232942 */     GIR_EraseRootFromParent_Done,
     /* 232943 */   // Label 4461: @232943
     /* 232943 */   GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(232980), // Rule ID 12646 //
     /* 232948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232951 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqxtnt),
     /* 232956 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 232959 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 232962 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 232965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 232969 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2104:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQXTNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 232969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQXTNT_ZZ_S),
     /* 232972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 232974 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 232976 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 232978 */     GIR_RootConstrainSelectedInstOperands,
     /* 232979 */     // GIR_Coverage, 12646,
     /* 232979 */     GIR_EraseRootFromParent_Done,
     /* 232980 */   // Label 4462: @232980
     /* 232980 */   GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(233017), // Rule ID 12647 //
     /* 232985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 232988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 232993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 232996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 232999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 233002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233006 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1909:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQXTUNT_ZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 233006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_B),
     /* 233009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233013 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233015 */     GIR_RootConstrainSelectedInstOperands,
     /* 233016 */     // GIR_Coverage, 12647,
     /* 233016 */     GIR_EraseRootFromParent_Done,
     /* 233017 */   // Label 4463: @233017
     /* 233017 */   GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(233054), // Rule ID 12648 //
     /* 233022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 233030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 233033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 233036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 233039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233043 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1909:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQXTUNT_ZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 233043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_H),
     /* 233046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233050 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233052 */     GIR_RootConstrainSelectedInstOperands,
     /* 233053 */     // GIR_Coverage, 12648,
     /* 233053 */     GIR_EraseRootFromParent_Done,
     /* 233054 */   // Label 4464: @233054
     /* 233054 */   GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(233091), // Rule ID 12649 //
     /* 233059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqxtunt),
     /* 233067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 233070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 233073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 233076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233080 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1909:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQXTUNT_ZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 233080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNT_ZZ_S),
     /* 233083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233089 */     GIR_RootConstrainSelectedInstOperands,
     /* 233090 */     // GIR_Coverage, 12649,
     /* 233090 */     GIR_EraseRootFromParent_Done,
     /* 233091 */   // Label 4465: @233091
     /* 233091 */   GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(233128), // Rule ID 12665 //
     /* 233096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233099 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 233104 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 233107 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 233110 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 233113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233117 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1924:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 233117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_H),
     /* 233120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233126 */     GIR_RootConstrainSelectedInstOperands,
     /* 233127 */     // GIR_Coverage, 12665,
     /* 233127 */     GIR_EraseRootFromParent_Done,
     /* 233128 */   // Label 4466: @233128
     /* 233128 */   GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(233165), // Rule ID 12666 //
     /* 233133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 233141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 233144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 233147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 233150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233154 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1924:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 233154 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_S),
     /* 233157 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233159 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233161 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233163 */     GIR_RootConstrainSelectedInstOperands,
     /* 233164 */     // GIR_Coverage, 12666,
     /* 233164 */     GIR_EraseRootFromParent_Done,
     /* 233165 */   // Label 4467: @233165
     /* 233165 */   GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(233202), // Rule ID 12667 //
     /* 233170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssublbt),
     /* 233178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 233181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 233184 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 233187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233191 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1924:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 233191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLBT_ZZZ_D),
     /* 233194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233198 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233200 */     GIR_RootConstrainSelectedInstOperands,
     /* 233201 */     // GIR_Coverage, 12667,
     /* 233201 */     GIR_EraseRootFromParent_Done,
     /* 233202 */   // Label 4468: @233202
     /* 233202 */   GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(233239), // Rule ID 12668 //
     /* 233207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 233215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 233218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 233221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 233224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233228 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1926:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SSUBLTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 233228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_H),
     /* 233231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233237 */     GIR_RootConstrainSelectedInstOperands,
     /* 233238 */     // GIR_Coverage, 12668,
     /* 233238 */     GIR_EraseRootFromParent_Done,
     /* 233239 */   // Label 4469: @233239
     /* 233239 */   GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(233276), // Rule ID 12669 //
     /* 233244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233247 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 233252 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 233255 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 233258 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 233261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233265 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1926:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SSUBLTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 233265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_S),
     /* 233268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233274 */     GIR_RootConstrainSelectedInstOperands,
     /* 233275 */     // GIR_Coverage, 12669,
     /* 233275 */     GIR_EraseRootFromParent_Done,
     /* 233276 */   // Label 4470: @233276
     /* 233276 */   GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(233313), // Rule ID 12670 //
     /* 233281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssubltb),
     /* 233289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 233292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 233295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 233298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 233302 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1926:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SSUBLTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 233302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSUBLTB_ZZZ_D),
     /* 233305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 233307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233309 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233311 */     GIR_RootConstrainSelectedInstOperands,
     /* 233312 */     // GIR_Coverage, 12670,
     /* 233312 */     GIR_EraseRootFromParent_Done,
     /* 233313 */   // Label 4471: @233313
     /* 233313 */   GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(233353), // Rule ID 12905 //
     /* 233318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 233326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 233329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233339 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2150:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_B),
     /* 233342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233346 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233348 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233351 */     GIR_RootConstrainSelectedInstOperands,
     /* 233352 */     // GIR_Coverage, 12905,
     /* 233352 */     GIR_EraseRootFromParent_Done,
     /* 233353 */   // Label 4472: @233353
     /* 233353 */   GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(233393), // Rule ID 12906 //
     /* 233358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 233366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 233369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233379 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2150:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_H),
     /* 233382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233386 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233388 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233391 */     GIR_RootConstrainSelectedInstOperands,
     /* 233392 */     // GIR_Coverage, 12906,
     /* 233392 */     GIR_EraseRootFromParent_Done,
     /* 233393 */   // Label 4473: @233393
     /* 233393 */   GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(233433), // Rule ID 12907 //
     /* 233398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 233406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 233409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233419 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2150:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_S),
     /* 233422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233426 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233428 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233431 */     GIR_RootConstrainSelectedInstOperands,
     /* 233432 */     // GIR_Coverage, 12907,
     /* 233432 */     GIR_EraseRootFromParent_Done,
     /* 233433 */   // Label 4474: @233433
     /* 233433 */   GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(233473), // Rule ID 12908 //
     /* 233438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 233446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 233449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233459 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2150:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGE_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PWW_D),
     /* 233462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233468 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233471 */     GIR_RootConstrainSelectedInstOperands,
     /* 233472 */     // GIR_Coverage, 12908,
     /* 233472 */     GIR_EraseRootFromParent_Done,
     /* 233473 */   // Label 4475: @233473
     /* 233473 */   GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(233513), // Rule ID 12909 //
     /* 233478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 233486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 233489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233499 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2156:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_B),
     /* 233502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233508 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233511 */     GIR_RootConstrainSelectedInstOperands,
     /* 233512 */     // GIR_Coverage, 12909,
     /* 233512 */     GIR_EraseRootFromParent_Done,
     /* 233513 */   // Label 4476: @233513
     /* 233513 */   GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(233553), // Rule ID 12910 //
     /* 233518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 233526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 233529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233539 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2156:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_H),
     /* 233542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233548 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233551 */     GIR_RootConstrainSelectedInstOperands,
     /* 233552 */     // GIR_Coverage, 12910,
     /* 233552 */     GIR_EraseRootFromParent_Done,
     /* 233553 */   // Label 4477: @233553
     /* 233553 */   GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(233593), // Rule ID 12911 //
     /* 233558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 233566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 233569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233579 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2156:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_S),
     /* 233582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233588 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233591 */     GIR_RootConstrainSelectedInstOperands,
     /* 233592 */     // GIR_Coverage, 12911,
     /* 233592 */     GIR_EraseRootFromParent_Done,
     /* 233593 */   // Label 4478: @233593
     /* 233593 */   GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(233633), // Rule ID 12912 //
     /* 233598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 233606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 233609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233619 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2156:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEGT_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PWW_D),
     /* 233622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233624 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233626 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233628 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233631 */     GIR_RootConstrainSelectedInstOperands,
     /* 233632 */     // GIR_Coverage, 12912,
     /* 233632 */     GIR_EraseRootFromParent_Done,
     /* 233633 */   // Label 4479: @233633
     /* 233633 */   GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(233673), // Rule ID 12917 //
     /* 233638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 233646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 233649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233659 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2168:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_B),
     /* 233662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233668 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233671 */     GIR_RootConstrainSelectedInstOperands,
     /* 233672 */     // GIR_Coverage, 12917,
     /* 233672 */     GIR_EraseRootFromParent_Done,
     /* 233673 */   // Label 4480: @233673
     /* 233673 */   GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(233713), // Rule ID 12918 //
     /* 233678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233681 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 233686 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 233689 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233692 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233699 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2168:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_H),
     /* 233702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233704 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233706 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233708 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233711 */     GIR_RootConstrainSelectedInstOperands,
     /* 233712 */     // GIR_Coverage, 12918,
     /* 233712 */     GIR_EraseRootFromParent_Done,
     /* 233713 */   // Label 4481: @233713
     /* 233713 */   GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(233753), // Rule ID 12919 //
     /* 233718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 233726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 233729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233739 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2168:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_S),
     /* 233742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233748 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233751 */     GIR_RootConstrainSelectedInstOperands,
     /* 233752 */     // GIR_Coverage, 12919,
     /* 233752 */     GIR_EraseRootFromParent_Done,
     /* 233753 */   // Label 4482: @233753
     /* 233753 */   GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(233793), // Rule ID 12920 //
     /* 233758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 233766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 233769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233779 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2168:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHS_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PWW_D),
     /* 233782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233788 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233791 */     GIR_RootConstrainSelectedInstOperands,
     /* 233792 */     // GIR_Coverage, 12920,
     /* 233792 */     GIR_EraseRootFromParent_Done,
     /* 233793 */   // Label 4483: @233793
     /* 233793 */   GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(233833), // Rule ID 12921 //
     /* 233798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 233806 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 233809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233812 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233819 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2162:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_B),
     /* 233822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233824 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233826 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233828 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233831 */     GIR_RootConstrainSelectedInstOperands,
     /* 233832 */     // GIR_Coverage, 12921,
     /* 233832 */     GIR_EraseRootFromParent_Done,
     /* 233833 */   // Label 4484: @233833
     /* 233833 */   GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(233873), // Rule ID 12922 //
     /* 233838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233841 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 233846 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 233849 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233852 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233855 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233859 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2162:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_H),
     /* 233862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233866 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233868 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233871 */     GIR_RootConstrainSelectedInstOperands,
     /* 233872 */     // GIR_Coverage, 12922,
     /* 233872 */     GIR_EraseRootFromParent_Done,
     /* 233873 */   // Label 4485: @233873
     /* 233873 */   GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(233913), // Rule ID 12923 //
     /* 233878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 233886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 233889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233899 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2162:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_S),
     /* 233902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233908 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233911 */     GIR_RootConstrainSelectedInstOperands,
     /* 233912 */     // GIR_Coverage, 12923,
     /* 233912 */     GIR_EraseRootFromParent_Done,
     /* 233913 */   // Label 4486: @233913
     /* 233913 */   GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(233953), // Rule ID 12924 //
     /* 233918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 233926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 233929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 233932 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 233935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233939 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2162:{ *:[iPTR] }, i32:{ *:[i32] }:$Op1, i32:{ *:[i32] }:$Op2)  =>  (WHILEHI_PWW_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i32] }:$Op1, ?:{ *:[i32] }:$Op2)
     /* 233939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PWW_D),
     /* 233942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233948 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233951 */     GIR_RootConstrainSelectedInstOperands,
     /* 233952 */     // GIR_Coverage, 12924,
     /* 233952 */     GIR_EraseRootFromParent_Done,
     /* 233953 */   // Label 4487: @233953
     /* 233953 */   GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(233993), // Rule ID 12929 //
     /* 233958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 233961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 233966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 233969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 233972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 233975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 233979 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2150:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 233979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_B),
     /* 233982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 233984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 233986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 233988 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 233991 */     GIR_RootConstrainSelectedInstOperands,
     /* 233992 */     // GIR_Coverage, 12929,
     /* 233992 */     GIR_EraseRootFromParent_Done,
     /* 233993 */   // Label 4488: @233993
     /* 233993 */   GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(234033), // Rule ID 12930 //
     /* 233998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234001 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 234006 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 234009 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234012 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234015 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234019 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2150:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_H),
     /* 234022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234024 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234026 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234028 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234031 */     GIR_RootConstrainSelectedInstOperands,
     /* 234032 */     // GIR_Coverage, 12930,
     /* 234032 */     GIR_EraseRootFromParent_Done,
     /* 234033 */   // Label 4489: @234033
     /* 234033 */   GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(234073), // Rule ID 12931 //
     /* 234038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 234046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 234049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234059 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2150:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_S),
     /* 234062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234068 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234071 */     GIR_RootConstrainSelectedInstOperands,
     /* 234072 */     // GIR_Coverage, 12931,
     /* 234072 */     GIR_EraseRootFromParent_Done,
     /* 234073 */   // Label 4490: @234073
     /* 234073 */   GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(234113), // Rule ID 12932 //
     /* 234078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilege),
     /* 234086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 234089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234099 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2150:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGE_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGE_PXX_D),
     /* 234102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234106 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234108 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234111 */     GIR_RootConstrainSelectedInstOperands,
     /* 234112 */     // GIR_Coverage, 12932,
     /* 234112 */     GIR_EraseRootFromParent_Done,
     /* 234113 */   // Label 4491: @234113
     /* 234113 */   GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(234153), // Rule ID 12933 //
     /* 234118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234121 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 234126 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234139 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2156:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_B),
     /* 234142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234148 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234151 */     GIR_RootConstrainSelectedInstOperands,
     /* 234152 */     // GIR_Coverage, 12933,
     /* 234152 */     GIR_EraseRootFromParent_Done,
     /* 234153 */   // Label 4492: @234153
     /* 234153 */   GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(234193), // Rule ID 12934 //
     /* 234158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 234166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 234169 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234175 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234179 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2156:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_H),
     /* 234182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234184 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234186 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234188 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234191 */     GIR_RootConstrainSelectedInstOperands,
     /* 234192 */     // GIR_Coverage, 12934,
     /* 234192 */     GIR_EraseRootFromParent_Done,
     /* 234193 */   // Label 4493: @234193
     /* 234193 */   GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(234233), // Rule ID 12935 //
     /* 234198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 234206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 234209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234219 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2156:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_S),
     /* 234222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234226 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234228 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234231 */     GIR_RootConstrainSelectedInstOperands,
     /* 234232 */     // GIR_Coverage, 12935,
     /* 234232 */     GIR_EraseRootFromParent_Done,
     /* 234233 */   // Label 4494: @234233
     /* 234233 */   GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(234273), // Rule ID 12936 //
     /* 234238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilegt),
     /* 234246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 234249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234259 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2156:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEGT_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEGT_PXX_D),
     /* 234262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234268 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234271 */     GIR_RootConstrainSelectedInstOperands,
     /* 234272 */     // GIR_Coverage, 12936,
     /* 234272 */     GIR_EraseRootFromParent_Done,
     /* 234273 */   // Label 4495: @234273
     /* 234273 */   GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(234313), // Rule ID 12941 //
     /* 234278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 234286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234292 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234299 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2168:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_B),
     /* 234302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234308 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234311 */     GIR_RootConstrainSelectedInstOperands,
     /* 234312 */     // GIR_Coverage, 12941,
     /* 234312 */     GIR_EraseRootFromParent_Done,
     /* 234313 */   // Label 4496: @234313
     /* 234313 */   GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(234353), // Rule ID 12942 //
     /* 234318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 234326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 234329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234335 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234339 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2168:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_H),
     /* 234342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234344 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234346 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234348 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234351 */     GIR_RootConstrainSelectedInstOperands,
     /* 234352 */     // GIR_Coverage, 12942,
     /* 234352 */     GIR_EraseRootFromParent_Done,
     /* 234353 */   // Label 4497: @234353
     /* 234353 */   GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(234393), // Rule ID 12943 //
     /* 234358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 234366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 234369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234379 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2168:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_S),
     /* 234382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234386 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234388 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234391 */     GIR_RootConstrainSelectedInstOperands,
     /* 234392 */     // GIR_Coverage, 12943,
     /* 234392 */     GIR_EraseRootFromParent_Done,
     /* 234393 */   // Label 4498: @234393
     /* 234393 */   GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(234433), // Rule ID 12944 //
     /* 234398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234401 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehs),
     /* 234406 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 234409 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234412 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234419 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2168:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHS_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHS_PXX_D),
     /* 234422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234426 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234428 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234431 */     GIR_RootConstrainSelectedInstOperands,
     /* 234432 */     // GIR_Coverage, 12944,
     /* 234432 */     GIR_EraseRootFromParent_Done,
     /* 234433 */   // Label 4499: @234433
     /* 234433 */   GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(234473), // Rule ID 12945 //
     /* 234438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 234446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 234449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234459 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 2162:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_B),
     /* 234462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234468 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234471 */     GIR_RootConstrainSelectedInstOperands,
     /* 234472 */     // GIR_Coverage, 12945,
     /* 234472 */     GIR_EraseRootFromParent_Done,
     /* 234473 */   // Label 4500: @234473
     /* 234473 */   GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(234513), // Rule ID 12946 //
     /* 234478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 234486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 234489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234499 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 2162:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_H),
     /* 234502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234508 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234511 */     GIR_RootConstrainSelectedInstOperands,
     /* 234512 */     // GIR_Coverage, 12946,
     /* 234512 */     GIR_EraseRootFromParent_Done,
     /* 234513 */   // Label 4501: @234513
     /* 234513 */   GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(234553), // Rule ID 12947 //
     /* 234518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 234526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 234529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234539 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 2162:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_S),
     /* 234542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234548 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234551 */     GIR_RootConstrainSelectedInstOperands,
     /* 234552 */     // GIR_Coverage, 12947,
     /* 234552 */     GIR_EraseRootFromParent_Done,
     /* 234553 */   // Label 4502: @234553
     /* 234553 */   GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(234593), // Rule ID 12948 //
     /* 234558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 234561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_whilehi),
     /* 234566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 234569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 234572 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 234575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 234579 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 2162:{ *:[iPTR] }, i64:{ *:[i64] }:$Op1, i64:{ *:[i64] }:$Op2)  =>  (WHILEHI_PXX_D:{ *:[nxv2i1] }:{ *:[i32] } ?:{ *:[i64] }:$Op1, ?:{ *:[i64] }:$Op2)
     /* 234579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WHILEHI_PXX_D),
     /* 234582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 234584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234588 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 234591 */     GIR_RootConstrainSelectedInstOperands,
     /* 234592 */     // GIR_Coverage, 12948,
     /* 234592 */     GIR_EraseRootFromParent_Done,
     /* 234593 */   // Label 4503: @234593
     /* 234593 */   GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(234630), // Rule ID 12958 //
     /* 234598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_AES_HasSVEAES),
     /* 234601 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmullt_pair),
     /* 234606 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 234609 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 234612 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 234615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234619 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1685:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (PMULLT_ZZZ_Q:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 234619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLT_ZZZ_Q),
     /* 234622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234624 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234626 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234628 */     GIR_RootConstrainSelectedInstOperands,
     /* 234629 */     // GIR_Coverage, 12958,
     /* 234629 */     GIR_EraseRootFromParent_Done,
     /* 234630 */   // Label 4504: @234630
     /* 234630 */   GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(234667), // Rule ID 12959 //
     /* 234635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SME2p1_HasSVESHA3),
     /* 234638 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rax1),
     /* 234643 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 234646 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 234649 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 234652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234656 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1717:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (RAX1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 234656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RAX1_ZZZ_D),
     /* 234659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234663 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234665 */     GIR_RootConstrainSelectedInstOperands,
     /* 234666 */     // GIR_Coverage, 12959,
     /* 234666 */     GIR_EraseRootFromParent_Done,
     /* 234667 */   // Label 4505: @234667
     /* 234667 */   GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(234704), // Rule ID 12960 //
     /* 234672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 234680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 234683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 234686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 234689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234693 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1303:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BDEP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 234693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_B),
     /* 234696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234698 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234702 */     GIR_RootConstrainSelectedInstOperands,
     /* 234703 */     // GIR_Coverage, 12960,
     /* 234703 */     GIR_EraseRootFromParent_Done,
     /* 234704 */   // Label 4506: @234704
     /* 234704 */   GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(234741), // Rule ID 12961 //
     /* 234709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 234717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 234720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 234723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 234726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234730 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1303:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BDEP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 234730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_H),
     /* 234733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234735 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234737 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234739 */     GIR_RootConstrainSelectedInstOperands,
     /* 234740 */     // GIR_Coverage, 12961,
     /* 234740 */     GIR_EraseRootFromParent_Done,
     /* 234741 */   // Label 4507: @234741
     /* 234741 */   GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(234778), // Rule ID 12962 //
     /* 234746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 234754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 234757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 234760 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 234763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234767 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1303:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BDEP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 234767 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_S),
     /* 234770 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234772 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234774 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234776 */     GIR_RootConstrainSelectedInstOperands,
     /* 234777 */     // GIR_Coverage, 12962,
     /* 234777 */     GIR_EraseRootFromParent_Done,
     /* 234778 */   // Label 4508: @234778
     /* 234778 */   GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(234815), // Rule ID 12963 //
     /* 234783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bdep_x),
     /* 234791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 234794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 234797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 234800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234804 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1303:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BDEP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 234804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BDEP_ZZZ_D),
     /* 234807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234809 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234811 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234813 */     GIR_RootConstrainSelectedInstOperands,
     /* 234814 */     // GIR_Coverage, 12963,
     /* 234814 */     GIR_EraseRootFromParent_Done,
     /* 234815 */   // Label 4509: @234815
     /* 234815 */   GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(234852), // Rule ID 12964 //
     /* 234820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 234828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 234831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 234834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 234837 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234841 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1320:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BGRP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 234841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_B),
     /* 234844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234846 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234850 */     GIR_RootConstrainSelectedInstOperands,
     /* 234851 */     // GIR_Coverage, 12964,
     /* 234851 */     GIR_EraseRootFromParent_Done,
     /* 234852 */   // Label 4510: @234852
     /* 234852 */   GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(234889), // Rule ID 12965 //
     /* 234857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 234865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 234868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 234871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 234874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234878 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1320:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BGRP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 234878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_H),
     /* 234881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234887 */     GIR_RootConstrainSelectedInstOperands,
     /* 234888 */     // GIR_Coverage, 12965,
     /* 234888 */     GIR_EraseRootFromParent_Done,
     /* 234889 */   // Label 4511: @234889
     /* 234889 */   GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(234926), // Rule ID 12966 //
     /* 234894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 234902 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 234905 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 234908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 234911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234915 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1320:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BGRP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 234915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_S),
     /* 234918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234924 */     GIR_RootConstrainSelectedInstOperands,
     /* 234925 */     // GIR_Coverage, 12966,
     /* 234925 */     GIR_EraseRootFromParent_Done,
     /* 234926 */   // Label 4512: @234926
     /* 234926 */   GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(234963), // Rule ID 12967 //
     /* 234931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNonStreamingSVE_or_SSVE_BitPerm_HasSVEBitPerm),
     /* 234934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bgrp_x),
     /* 234939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 234942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 234945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 234948 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 234952 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1320:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BGRP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 234952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BGRP_ZZZ_D),
     /* 234955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 234957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234961 */     GIR_RootConstrainSelectedInstOperands,
     /* 234962 */     // GIR_Coverage, 12967,
     /* 234962 */     GIR_EraseRootFromParent_Done,
     /* 234963 */   // Label 4513: @234963
     /* 234963 */   GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(235000), // Rule ID 13083 //
     /* 234968 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 234971 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 234976 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 234979 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 234982 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 234985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 234989 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1475:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMAXNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 234989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_H),
     /* 234992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 234994 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 234996 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 234998 */     GIR_RootConstrainSelectedInstOperands,
     /* 234999 */     // GIR_Coverage, 13083,
     /* 234999 */     GIR_EraseRootFromParent_Done,
     /* 235000 */   // Label 4514: @235000
     /* 235000 */   GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(235037), // Rule ID 13084 //
     /* 235005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 235013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235026 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1475:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMAXNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 235026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_S),
     /* 235029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235031 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235033 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235035 */     GIR_RootConstrainSelectedInstOperands,
     /* 235036 */     // GIR_Coverage, 13084,
     /* 235036 */     GIR_EraseRootFromParent_Done,
     /* 235037 */   // Label 4515: @235037
     /* 235037 */   GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(235074), // Rule ID 13085 //
     /* 235042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235045 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmqv),
     /* 235050 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235063 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1475:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMAXNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 235063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMQV_D),
     /* 235066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235072 */     GIR_RootConstrainSelectedInstOperands,
     /* 235073 */     // GIR_Coverage, 13085,
     /* 235073 */     GIR_EraseRootFromParent_Done,
     /* 235074 */   // Label 4516: @235074
     /* 235074 */   GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(235111), // Rule ID 13086 //
     /* 235079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 235087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235093 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235100 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1493:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMINNMQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 235100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_H),
     /* 235103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235109 */     GIR_RootConstrainSelectedInstOperands,
     /* 235110 */     // GIR_Coverage, 13086,
     /* 235110 */     GIR_EraseRootFromParent_Done,
     /* 235111 */   // Label 4517: @235111
     /* 235111 */   GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(235148), // Rule ID 13087 //
     /* 235116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235119 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 235124 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235127 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235130 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235137 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1493:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMINNMQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 235137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_S),
     /* 235140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235146 */     GIR_RootConstrainSelectedInstOperands,
     /* 235147 */     // GIR_Coverage, 13087,
     /* 235147 */     GIR_EraseRootFromParent_Done,
     /* 235148 */   // Label 4518: @235148
     /* 235148 */   GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(235185), // Rule ID 13088 //
     /* 235153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmqv),
     /* 235161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235170 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235174 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1493:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMINNMQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 235174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMQV_D),
     /* 235177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235179 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235181 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235183 */     GIR_RootConstrainSelectedInstOperands,
     /* 235184 */     // GIR_Coverage, 13088,
     /* 235184 */     GIR_EraseRootFromParent_Done,
     /* 235185 */   // Label 4519: @235185
     /* 235185 */   GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(235222), // Rule ID 13089 //
     /* 235190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 235198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235211 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1478:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMAXQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 235211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_H),
     /* 235214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235220 */     GIR_RootConstrainSelectedInstOperands,
     /* 235221 */     // GIR_Coverage, 13089,
     /* 235221 */     GIR_EraseRootFromParent_Done,
     /* 235222 */   // Label 4520: @235222
     /* 235222 */   GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(235259), // Rule ID 13090 //
     /* 235227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 235235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235248 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1478:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMAXQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 235248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_S),
     /* 235251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235257 */     GIR_RootConstrainSelectedInstOperands,
     /* 235258 */     // GIR_Coverage, 13090,
     /* 235258 */     GIR_EraseRootFromParent_Done,
     /* 235259 */   // Label 4521: @235259
     /* 235259 */   GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(235296), // Rule ID 13091 //
     /* 235264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxqv),
     /* 235272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235285 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1478:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMAXQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 235285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXQV_D),
     /* 235288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235290 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235292 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235294 */     GIR_RootConstrainSelectedInstOperands,
     /* 235295 */     // GIR_Coverage, 13091,
     /* 235295 */     GIR_EraseRootFromParent_Done,
     /* 235296 */   // Label 4522: @235296
     /* 235296 */   GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(235333), // Rule ID 13092 //
     /* 235301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235304 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 235309 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235312 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235315 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235318 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235322 */     // (intrinsic_wo_chain:{ *:[v8f16] } 1496:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMINQV_H:{ *:[v8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 235322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_H),
     /* 235325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235329 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235331 */     GIR_RootConstrainSelectedInstOperands,
     /* 235332 */     // GIR_Coverage, 13092,
     /* 235332 */     GIR_EraseRootFromParent_Done,
     /* 235333 */   // Label 4523: @235333
     /* 235333 */   GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(235370), // Rule ID 13093 //
     /* 235338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 235346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235359 */     // (intrinsic_wo_chain:{ *:[v4f32] } 1496:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMINQV_S:{ *:[v4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 235359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_S),
     /* 235362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235364 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235366 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235368 */     GIR_RootConstrainSelectedInstOperands,
     /* 235369 */     // GIR_Coverage, 13093,
     /* 235369 */     GIR_EraseRootFromParent_Done,
     /* 235370 */   // Label 4524: @235370
     /* 235370 */   GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(235407), // Rule ID 13094 //
     /* 235375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminqv),
     /* 235383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235396 */     // (intrinsic_wo_chain:{ *:[v2f64] } 1496:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMINQV_D:{ *:[v2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 235396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINQV_D),
     /* 235399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235401 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235403 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235405 */     GIR_RootConstrainSelectedInstOperands,
     /* 235406 */     // GIR_Coverage, 13094,
     /* 235406 */     GIR_EraseRootFromParent_Done,
     /* 235407 */   // Label 4525: @235407
     /* 235407 */   GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(235444), // Rule ID 13095 //
     /* 235412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 235420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 235426 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 235429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235433 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1384:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (EORQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 235433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_B),
     /* 235436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235442 */     GIR_RootConstrainSelectedInstOperands,
     /* 235443 */     // GIR_Coverage, 13095,
     /* 235443 */     GIR_EraseRootFromParent_Done,
     /* 235444 */   // Label 4526: @235444
     /* 235444 */   GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(235481), // Rule ID 13096 //
     /* 235449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 235457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235466 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235470 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1384:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (EORQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 235470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_H),
     /* 235473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235475 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235477 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235479 */     GIR_RootConstrainSelectedInstOperands,
     /* 235480 */     // GIR_Coverage, 13096,
     /* 235480 */     GIR_EraseRootFromParent_Done,
     /* 235481 */   // Label 4527: @235481
     /* 235481 */   GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(235518), // Rule ID 13097 //
     /* 235486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 235494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235500 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235507 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1384:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (EORQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 235507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_S),
     /* 235510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235512 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235514 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235516 */     GIR_RootConstrainSelectedInstOperands,
     /* 235517 */     // GIR_Coverage, 13097,
     /* 235517 */     GIR_EraseRootFromParent_Done,
     /* 235518 */   // Label 4528: @235518
     /* 235518 */   GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(235555), // Rule ID 13098 //
     /* 235523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorqv),
     /* 235531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235544 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1384:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (EORQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 235544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORQV_VPZ_D),
     /* 235547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235549 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235551 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235553 */     GIR_RootConstrainSelectedInstOperands,
     /* 235554 */     // GIR_Coverage, 13098,
     /* 235554 */     GIR_EraseRootFromParent_Done,
     /* 235555 */   // Label 4529: @235555
     /* 235555 */   GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(235592), // Rule ID 13099 //
     /* 235560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 235568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 235574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 235577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235581 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1296:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ANDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 235581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_B),
     /* 235584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235586 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235588 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235590 */     GIR_RootConstrainSelectedInstOperands,
     /* 235591 */     // GIR_Coverage, 13099,
     /* 235591 */     GIR_EraseRootFromParent_Done,
     /* 235592 */   // Label 4530: @235592
     /* 235592 */   GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(235629), // Rule ID 13100 //
     /* 235597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235600 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 235605 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235608 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235611 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235614 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235618 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1296:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ANDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 235618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_H),
     /* 235621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235625 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235627 */     GIR_RootConstrainSelectedInstOperands,
     /* 235628 */     // GIR_Coverage, 13100,
     /* 235628 */     GIR_EraseRootFromParent_Done,
     /* 235629 */   // Label 4531: @235629
     /* 235629 */   GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(235666), // Rule ID 13101 //
     /* 235634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 235642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235648 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235655 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1296:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ANDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 235655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_S),
     /* 235658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235664 */     GIR_RootConstrainSelectedInstOperands,
     /* 235665 */     // GIR_Coverage, 13101,
     /* 235665 */     GIR_EraseRootFromParent_Done,
     /* 235666 */   // Label 4532: @235666
     /* 235666 */   GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(235703), // Rule ID 13102 //
     /* 235671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_andqv),
     /* 235679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235692 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1296:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ANDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 235692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ANDQV_VPZ_D),
     /* 235695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235697 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235699 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235701 */     GIR_RootConstrainSelectedInstOperands,
     /* 235702 */     // GIR_Coverage, 13102,
     /* 235702 */     GIR_EraseRootFromParent_Done,
     /* 235703 */   // Label 4533: @235703
     /* 235703 */   GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(235740), // Rule ID 13103 //
     /* 235708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 235716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 235722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 235725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235729 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1276:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ADDQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 235729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_B),
     /* 235732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235734 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235736 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235738 */     GIR_RootConstrainSelectedInstOperands,
     /* 235739 */     // GIR_Coverage, 13103,
     /* 235739 */     GIR_EraseRootFromParent_Done,
     /* 235740 */   // Label 4534: @235740
     /* 235740 */   GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(235777), // Rule ID 13104 //
     /* 235745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 235753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235766 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1276:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ADDQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 235766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_H),
     /* 235769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235775 */     GIR_RootConstrainSelectedInstOperands,
     /* 235776 */     // GIR_Coverage, 13104,
     /* 235776 */     GIR_EraseRootFromParent_Done,
     /* 235777 */   // Label 4535: @235777
     /* 235777 */   GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(235814), // Rule ID 13105 //
     /* 235782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 235790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235796 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235803 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1276:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ADDQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 235803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_S),
     /* 235806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235812 */     GIR_RootConstrainSelectedInstOperands,
     /* 235813 */     // GIR_Coverage, 13105,
     /* 235813 */     GIR_EraseRootFromParent_Done,
     /* 235814 */   // Label 4536: @235814
     /* 235814 */   GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(235851), // Rule ID 13106 //
     /* 235819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addqv),
     /* 235827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235840 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1276:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ADDQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 235840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDQV_VPZ_D),
     /* 235843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235847 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235849 */     GIR_RootConstrainSelectedInstOperands,
     /* 235850 */     // GIR_Coverage, 13106,
     /* 235850 */     GIR_EraseRootFromParent_Done,
     /* 235851 */   // Label 4537: @235851
     /* 235851 */   GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(235888), // Rule ID 13107 //
     /* 235856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235859 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 235864 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 235867 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 235870 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 235873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235877 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1785:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 235877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_B),
     /* 235880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235882 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235884 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235886 */     GIR_RootConstrainSelectedInstOperands,
     /* 235887 */     // GIR_Coverage, 13107,
     /* 235887 */     GIR_EraseRootFromParent_Done,
     /* 235888 */   // Label 4538: @235888
     /* 235888 */   GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(235925), // Rule ID 13108 //
     /* 235893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 235901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 235904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 235907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 235910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235914 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1785:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 235914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_H),
     /* 235917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235919 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235921 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235923 */     GIR_RootConstrainSelectedInstOperands,
     /* 235924 */     // GIR_Coverage, 13108,
     /* 235924 */     GIR_EraseRootFromParent_Done,
     /* 235925 */   // Label 4539: @235925
     /* 235925 */   GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(235962), // Rule ID 13109 //
     /* 235930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235933 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 235938 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 235941 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 235944 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 235947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235951 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1785:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 235951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_S),
     /* 235954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235958 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235960 */     GIR_RootConstrainSelectedInstOperands,
     /* 235961 */     // GIR_Coverage, 13109,
     /* 235961 */     GIR_EraseRootFromParent_Done,
     /* 235962 */   // Label 4540: @235962
     /* 235962 */   GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(235999), // Rule ID 13110 //
     /* 235967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 235970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxqv),
     /* 235975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 235978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 235981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 235984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 235988 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1785:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 235988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXQV_VPZ_D),
     /* 235991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 235993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 235995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 235997 */     GIR_RootConstrainSelectedInstOperands,
     /* 235998 */     // GIR_Coverage, 13110,
     /* 235998 */     GIR_EraseRootFromParent_Done,
     /* 235999 */   // Label 4541: @235999
     /* 235999 */   GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(236036), // Rule ID 13111 //
     /* 236004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236007 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 236012 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 236015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 236018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236025 */     // (intrinsic_wo_chain:{ *:[v16i8] } 2027:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMAXQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_B),
     /* 236028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236032 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236034 */     GIR_RootConstrainSelectedInstOperands,
     /* 236035 */     // GIR_Coverage, 13111,
     /* 236035 */     GIR_EraseRootFromParent_Done,
     /* 236036 */   // Label 4542: @236036
     /* 236036 */   GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(236073), // Rule ID 13112 //
     /* 236041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 236049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 236055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236062 */     // (intrinsic_wo_chain:{ *:[v8i16] } 2027:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMAXQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 236062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_H),
     /* 236065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236067 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236071 */     GIR_RootConstrainSelectedInstOperands,
     /* 236072 */     // GIR_Coverage, 13112,
     /* 236072 */     GIR_EraseRootFromParent_Done,
     /* 236073 */   // Label 4543: @236073
     /* 236073 */   GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(236110), // Rule ID 13113 //
     /* 236078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236081 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 236086 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236089 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 236092 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236099 */     // (intrinsic_wo_chain:{ *:[v4i32] } 2027:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMAXQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 236099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_S),
     /* 236102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236106 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236108 */     GIR_RootConstrainSelectedInstOperands,
     /* 236109 */     // GIR_Coverage, 13113,
     /* 236109 */     GIR_EraseRootFromParent_Done,
     /* 236110 */   // Label 4544: @236110
     /* 236110 */   GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(236147), // Rule ID 13114 //
     /* 236115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxqv),
     /* 236123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 236129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236136 */     // (intrinsic_wo_chain:{ *:[v2i64] } 2027:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UMAXQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 236136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXQV_VPZ_D),
     /* 236139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236145 */     GIR_RootConstrainSelectedInstOperands,
     /* 236146 */     // GIR_Coverage, 13114,
     /* 236146 */     GIR_EraseRootFromParent_Done,
     /* 236147 */   // Label 4545: @236147
     /* 236147 */   GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(236184), // Rule ID 13115 //
     /* 236152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 236160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 236163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 236166 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236173 */     // (intrinsic_wo_chain:{ *:[v16i8] } 1794:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_B),
     /* 236176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236182 */     GIR_RootConstrainSelectedInstOperands,
     /* 236183 */     // GIR_Coverage, 13115,
     /* 236183 */     GIR_EraseRootFromParent_Done,
     /* 236184 */   // Label 4546: @236184
     /* 236184 */   GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(236221), // Rule ID 13116 //
     /* 236189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 236197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 236203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236210 */     // (intrinsic_wo_chain:{ *:[v8i16] } 1794:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 236210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_H),
     /* 236213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236217 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236219 */     GIR_RootConstrainSelectedInstOperands,
     /* 236220 */     // GIR_Coverage, 13116,
     /* 236220 */     GIR_EraseRootFromParent_Done,
     /* 236221 */   // Label 4547: @236221
     /* 236221 */   GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(236258), // Rule ID 13117 //
     /* 236226 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236229 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 236234 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236237 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 236240 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236247 */     // (intrinsic_wo_chain:{ *:[v4i32] } 1794:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 236247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_S),
     /* 236250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236254 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236256 */     GIR_RootConstrainSelectedInstOperands,
     /* 236257 */     // GIR_Coverage, 13117,
     /* 236257 */     GIR_EraseRootFromParent_Done,
     /* 236258 */   // Label 4548: @236258
     /* 236258 */   GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(236295), // Rule ID 13118 //
     /* 236263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminqv),
     /* 236271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 236277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236284 */     // (intrinsic_wo_chain:{ *:[v2i64] } 1794:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 236284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINQV_VPZ_D),
     /* 236287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236289 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236291 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236293 */     GIR_RootConstrainSelectedInstOperands,
     /* 236294 */     // GIR_Coverage, 13118,
     /* 236294 */     GIR_EraseRootFromParent_Done,
     /* 236295 */   // Label 4549: @236295
     /* 236295 */   GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(236332), // Rule ID 13119 //
     /* 236300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 236308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 236311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 236314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236321 */     // (intrinsic_wo_chain:{ *:[v16i8] } 2036:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UMINQV_VPZ_B:{ *:[v16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_B),
     /* 236324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236326 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236328 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236330 */     GIR_RootConstrainSelectedInstOperands,
     /* 236331 */     // GIR_Coverage, 13119,
     /* 236331 */     GIR_EraseRootFromParent_Done,
     /* 236332 */   // Label 4550: @236332
     /* 236332 */   GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(236369), // Rule ID 13120 //
     /* 236337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 236345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 236348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 236351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236358 */     // (intrinsic_wo_chain:{ *:[v8i16] } 2036:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UMINQV_VPZ_H:{ *:[v8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 236358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_H),
     /* 236361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236367 */     GIR_RootConstrainSelectedInstOperands,
     /* 236368 */     // GIR_Coverage, 13120,
     /* 236368 */     GIR_EraseRootFromParent_Done,
     /* 236369 */   // Label 4551: @236369
     /* 236369 */   GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(236406), // Rule ID 13121 //
     /* 236374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 236382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 236385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 236388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236395 */     // (intrinsic_wo_chain:{ *:[v4i32] } 2036:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UMINQV_VPZ_S:{ *:[v4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 236395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_S),
     /* 236398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236402 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236404 */     GIR_RootConstrainSelectedInstOperands,
     /* 236405 */     // GIR_Coverage, 13121,
     /* 236405 */     GIR_EraseRootFromParent_Done,
     /* 236406 */   // Label 4552: @236406
     /* 236406 */   GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(236443), // Rule ID 13122 //
     /* 236411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminqv),
     /* 236419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 236422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 236425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 236432 */     // (intrinsic_wo_chain:{ *:[v2i64] } 2036:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UMINQV_VPZ_D:{ *:[v2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 236432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINQV_VPZ_D),
     /* 236435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 236437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236441 */     GIR_RootConstrainSelectedInstOperands,
     /* 236442 */     // GIR_Coverage, 13122,
     /* 236442 */     GIR_EraseRootFromParent_Done,
     /* 236443 */   // Label 4553: @236443
     /* 236443 */   GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(236480), // Rule ID 13123 //
     /* 236448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 236459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 236462 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236469 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2223:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_B),
     /* 236472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236476 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236478 */     GIR_RootConstrainSelectedInstOperands,
     /* 236479 */     // GIR_Coverage, 13123,
     /* 236479 */     GIR_EraseRootFromParent_Done,
     /* 236480 */   // Label 4554: @236480
     /* 236480 */   GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(236517), // Rule ID 13124 //
     /* 236485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 236496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 236499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236502 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236506 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2223:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 236506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
     /* 236509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236513 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236515 */     GIR_RootConstrainSelectedInstOperands,
     /* 236516 */     // GIR_Coverage, 13124,
     /* 236516 */     GIR_EraseRootFromParent_Done,
     /* 236517 */   // Label 4555: @236517
     /* 236517 */   GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(236554), // Rule ID 13125 //
     /* 236522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 236533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 236536 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236543 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2223:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 236543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
     /* 236546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236552 */     GIR_RootConstrainSelectedInstOperands,
     /* 236553 */     // GIR_Coverage, 13125,
     /* 236553 */     GIR_EraseRootFromParent_Done,
     /* 236554 */   // Label 4556: @236554
     /* 236554 */   GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(236591), // Rule ID 13126 //
     /* 236559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 236570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 236573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236580 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2223:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 236580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
     /* 236583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236587 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236589 */     GIR_RootConstrainSelectedInstOperands,
     /* 236590 */     // GIR_Coverage, 13126,
     /* 236590 */     GIR_EraseRootFromParent_Done,
     /* 236591 */   // Label 4557: @236591
     /* 236591 */   GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(236628), // Rule ID 13127 //
     /* 236596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236599 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236604 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 236607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 236610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236617 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2223:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 236617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_H),
     /* 236620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236624 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236626 */     GIR_RootConstrainSelectedInstOperands,
     /* 236627 */     // GIR_Coverage, 13127,
     /* 236627 */     GIR_EraseRootFromParent_Done,
     /* 236628 */   // Label 4558: @236628
     /* 236628 */   GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(236665), // Rule ID 13128 //
     /* 236633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 236644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 236647 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236654 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2223:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 236654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_S),
     /* 236657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236659 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236661 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236663 */     GIR_RootConstrainSelectedInstOperands,
     /* 236664 */     // GIR_Coverage, 13128,
     /* 236664 */     GIR_EraseRootFromParent_Done,
     /* 236665 */   // Label 4559: @236665
     /* 236665 */   GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(236702), // Rule ID 13129 //
     /* 236670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_zipq2),
     /* 236678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 236681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 236684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236691 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2223:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 236691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIPQ2_ZZZ_D),
     /* 236694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236698 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236700 */     GIR_RootConstrainSelectedInstOperands,
     /* 236701 */     // GIR_Coverage, 13129,
     /* 236701 */     GIR_EraseRootFromParent_Done,
     /* 236702 */   // Label 4560: @236702
     /* 236702 */   GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(236739), // Rule ID 13130 //
     /* 236707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 236718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 236721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236728 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2148:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZPQ1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_B),
     /* 236731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236733 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236735 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236737 */     GIR_RootConstrainSelectedInstOperands,
     /* 236738 */     // GIR_Coverage, 13130,
     /* 236738 */     GIR_EraseRootFromParent_Done,
     /* 236739 */   // Label 4561: @236739
     /* 236739 */   GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(236776), // Rule ID 13131 //
     /* 236744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236747 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236752 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 236755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 236758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236765 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2148:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZPQ1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 236765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
     /* 236768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236774 */     GIR_RootConstrainSelectedInstOperands,
     /* 236775 */     // GIR_Coverage, 13131,
     /* 236775 */     GIR_EraseRootFromParent_Done,
     /* 236776 */   // Label 4562: @236776
     /* 236776 */   GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(236813), // Rule ID 13132 //
     /* 236781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 236792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 236795 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236798 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236802 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2148:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZPQ1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 236802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
     /* 236805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236809 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236811 */     GIR_RootConstrainSelectedInstOperands,
     /* 236812 */     // GIR_Coverage, 13132,
     /* 236812 */     GIR_EraseRootFromParent_Done,
     /* 236813 */   // Label 4563: @236813
     /* 236813 */   GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(236850), // Rule ID 13133 //
     /* 236818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 236829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 236832 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236839 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2148:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZPQ1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 236839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
     /* 236842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236844 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236848 */     GIR_RootConstrainSelectedInstOperands,
     /* 236849 */     // GIR_Coverage, 13133,
     /* 236849 */     GIR_EraseRootFromParent_Done,
     /* 236850 */   // Label 4564: @236850
     /* 236850 */   GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(236887), // Rule ID 13134 //
     /* 236855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 236866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 236869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 236872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236876 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2148:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZPQ1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 236876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_H),
     /* 236879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236881 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236883 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236885 */     GIR_RootConstrainSelectedInstOperands,
     /* 236886 */     // GIR_Coverage, 13134,
     /* 236886 */     GIR_EraseRootFromParent_Done,
     /* 236887 */   // Label 4565: @236887
     /* 236887 */   GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(236924), // Rule ID 13135 //
     /* 236892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 236903 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 236906 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 236909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236913 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2148:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZPQ1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 236913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_S),
     /* 236916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236922 */     GIR_RootConstrainSelectedInstOperands,
     /* 236923 */     // GIR_Coverage, 13135,
     /* 236923 */     GIR_EraseRootFromParent_Done,
     /* 236924 */   // Label 4566: @236924
     /* 236924 */   GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(236961), // Rule ID 13136 //
     /* 236929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236932 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq1),
     /* 236937 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 236940 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 236943 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 236946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236950 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2148:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZPQ1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 236950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ1_ZZZ_D),
     /* 236953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236959 */     GIR_RootConstrainSelectedInstOperands,
     /* 236960 */     // GIR_Coverage, 13136,
     /* 236960 */     GIR_EraseRootFromParent_Done,
     /* 236961 */   // Label 4567: @236961
     /* 236961 */   GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(236998), // Rule ID 13137 //
     /* 236966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 236969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 236974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 236977 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 236980 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 236983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 236987 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2149:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZPQ2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 236987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_B),
     /* 236990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 236992 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 236994 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 236996 */     GIR_RootConstrainSelectedInstOperands,
     /* 236997 */     // GIR_Coverage, 13137,
     /* 236997 */     GIR_EraseRootFromParent_Done,
     /* 236998 */   // Label 4568: @236998
     /* 236998 */   GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(237035), // Rule ID 13138 //
     /* 237003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237006 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237011 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237014 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 237017 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237024 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2149:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZPQ2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 237024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
     /* 237027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237029 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237031 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237033 */     GIR_RootConstrainSelectedInstOperands,
     /* 237034 */     // GIR_Coverage, 13138,
     /* 237034 */     GIR_EraseRootFromParent_Done,
     /* 237035 */   // Label 4569: @237035
     /* 237035 */   GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(237072), // Rule ID 13139 //
     /* 237040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237061 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2149:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZPQ2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 237061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
     /* 237064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237070 */     GIR_RootConstrainSelectedInstOperands,
     /* 237071 */     // GIR_Coverage, 13139,
     /* 237071 */     GIR_EraseRootFromParent_Done,
     /* 237072 */   // Label 4570: @237072
     /* 237072 */   GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(237109), // Rule ID 13140 //
     /* 237077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 237091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237098 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2149:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZPQ2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 237098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
     /* 237101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237103 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237105 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237107 */     GIR_RootConstrainSelectedInstOperands,
     /* 237108 */     // GIR_Coverage, 13140,
     /* 237108 */     GIR_EraseRootFromParent_Done,
     /* 237109 */   // Label 4571: @237109
     /* 237109 */   GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(237146), // Rule ID 13141 //
     /* 237114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 237125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 237128 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 237131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237135 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2149:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZPQ2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 237135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_H),
     /* 237138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237144 */     GIR_RootConstrainSelectedInstOperands,
     /* 237145 */     // GIR_Coverage, 13141,
     /* 237145 */     GIR_EraseRootFromParent_Done,
     /* 237146 */   // Label 4572: @237146
     /* 237146 */   GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(237183), // Rule ID 13142 //
     /* 237151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 237162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 237165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 237168 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237172 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2149:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZPQ2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 237172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_S),
     /* 237175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237179 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237181 */     GIR_RootConstrainSelectedInstOperands,
     /* 237182 */     // GIR_Coverage, 13142,
     /* 237182 */     GIR_EraseRootFromParent_Done,
     /* 237183 */   // Label 4573: @237183
     /* 237183 */   GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(237220), // Rule ID 13143 //
     /* 237188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 237191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uzpq2),
     /* 237196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 237199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 237202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 237205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 237209 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2149:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZPQ2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 237209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZPQ2_ZZZ_D),
     /* 237212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 237214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237218 */     GIR_RootConstrainSelectedInstOperands,
     /* 237219 */     // GIR_Coverage, 13143,
     /* 237219 */     GIR_EraseRootFromParent_Done,
     /* 237220 */   // Label 4574: @237220
     /* 237220 */   GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(237257), // Rule ID 13514 //
     /* 237225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_firstp),
     /* 237233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 237239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 237242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237246 */     // (intrinsic_wo_chain:{ *:[i64] } 1459:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (FIRSTP_XPP_B:{ *:[i64] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 237246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FIRSTP_XPP_B),
     /* 237249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237251 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237253 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237255 */     GIR_RootConstrainSelectedInstOperands,
     /* 237256 */     // GIR_Coverage, 13514,
     /* 237256 */     GIR_EraseRootFromParent_Done,
     /* 237257 */   // Label 4575: @237257
     /* 237257 */   GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(237294), // Rule ID 13515 //
     /* 237262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_firstp),
     /* 237270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 237276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 237279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237283 */     // (intrinsic_wo_chain:{ *:[i64] } 1459:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (FIRSTP_XPP_H:{ *:[i64] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 237283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FIRSTP_XPP_H),
     /* 237286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237292 */     GIR_RootConstrainSelectedInstOperands,
     /* 237293 */     // GIR_Coverage, 13515,
     /* 237293 */     GIR_EraseRootFromParent_Done,
     /* 237294 */   // Label 4576: @237294
     /* 237294 */   GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(237331), // Rule ID 13516 //
     /* 237299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_firstp),
     /* 237307 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 237313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 237316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237320 */     // (intrinsic_wo_chain:{ *:[i64] } 1459:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (FIRSTP_XPP_S:{ *:[i64] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 237320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FIRSTP_XPP_S),
     /* 237323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237327 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237329 */     GIR_RootConstrainSelectedInstOperands,
     /* 237330 */     // GIR_Coverage, 13516,
     /* 237330 */     GIR_EraseRootFromParent_Done,
     /* 237331 */   // Label 4577: @237331
     /* 237331 */   GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(237368), // Rule ID 13517 //
     /* 237336 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237339 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_firstp),
     /* 237344 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237347 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 237350 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 237353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237357 */     // (intrinsic_wo_chain:{ *:[i64] } 1459:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (FIRSTP_XPP_D:{ *:[i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 237357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FIRSTP_XPP_D),
     /* 237360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237366 */     GIR_RootConstrainSelectedInstOperands,
     /* 237367 */     // GIR_Coverage, 13517,
     /* 237367 */     GIR_EraseRootFromParent_Done,
     /* 237368 */   // Label 4578: @237368
     /* 237368 */   GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(237405), // Rule ID 13518 //
     /* 237373 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237376 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lastp),
     /* 237381 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237384 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 237387 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 237390 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237394 */     // (intrinsic_wo_chain:{ *:[i64] } 1601:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2)  =>  (LASTP_XPP_B:{ *:[i64] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2)
     /* 237394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTP_XPP_B),
     /* 237397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237401 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237403 */     GIR_RootConstrainSelectedInstOperands,
     /* 237404 */     // GIR_Coverage, 13518,
     /* 237404 */     GIR_EraseRootFromParent_Done,
     /* 237405 */   // Label 4579: @237405
     /* 237405 */   GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(237442), // Rule ID 13519 //
     /* 237410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lastp),
     /* 237418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 237424 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 237427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237431 */     // (intrinsic_wo_chain:{ *:[i64] } 1601:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (LASTP_XPP_H:{ *:[i64] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 237431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTP_XPP_H),
     /* 237434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237436 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237438 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237440 */     GIR_RootConstrainSelectedInstOperands,
     /* 237441 */     // GIR_Coverage, 13519,
     /* 237441 */     GIR_EraseRootFromParent_Done,
     /* 237442 */   // Label 4580: @237442
     /* 237442 */   GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(237479), // Rule ID 13520 //
     /* 237447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lastp),
     /* 237455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 237461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 237464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237468 */     // (intrinsic_wo_chain:{ *:[i64] } 1601:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (LASTP_XPP_S:{ *:[i64] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 237468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTP_XPP_S),
     /* 237471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237477 */     GIR_RootConstrainSelectedInstOperands,
     /* 237478 */     // GIR_Coverage, 13520,
     /* 237478 */     GIR_EraseRootFromParent_Done,
     /* 237479 */   // Label 4581: @237479
     /* 237479 */   GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(237516), // Rule ID 13521 //
     /* 237484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 237487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lastp),
     /* 237492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 237495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 237498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 237501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 237505 */     // (intrinsic_wo_chain:{ *:[i64] } 1601:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (LASTP_XPP_D:{ *:[i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 237505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTP_XPP_D),
     /* 237508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 237510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 237512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 237514 */     GIR_RootConstrainSelectedInstOperands,
     /* 237515 */     // GIR_Coverage, 13521,
     /* 237515 */     GIR_EraseRootFromParent_Done,
     /* 237516 */   // Label 4582: @237516
     /* 237516 */   GIM_Reject,
     /* 237517 */ // Label 3695: @237517
     /* 237517 */ GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(281867),
     /* 237522 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /* 237525 */   GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(237638), // Rule ID 2100 //
     /* 237530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 237533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 237538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 237541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 237544 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 237547 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 237550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237558 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 237566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 237570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 237574 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 237578 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 237582 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 237586 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 237590 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 237595 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 237599 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 237603 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 237607 */     // MIs[3] Operand 1
     /* 237607 */     // No operand predicates
     /* 237607 */     // MIs[1] Operand 2
     /* 237607 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 237618 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 237620 */     // (intrinsic_wo_chain:{ *:[v4i16] } 711:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 237620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16_indexed),
     /* 237623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 237629 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 237633 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 237636 */     GIR_RootConstrainSelectedInstOperands,
     /* 237637 */     // GIR_Coverage, 2100,
     /* 237637 */     GIR_EraseRootFromParent_Done,
     /* 237638 */   // Label 4584: @237638
     /* 237638 */   GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(237751), // Rule ID 2107 //
     /* 237643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 237646 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 237651 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 237654 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 237657 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 237660 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 237663 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237667 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237671 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 237679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 237683 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 237687 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 237691 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 237695 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 237699 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 237703 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 237708 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 237712 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 237716 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 237720 */     // MIs[3] Operand 1
     /* 237720 */     // No operand predicates
     /* 237720 */     // MIs[1] Operand 2
     /* 237720 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 237731 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 237733 */     // (intrinsic_wo_chain:{ *:[v4i16] } 712:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 237733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16_indexed),
     /* 237736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237738 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237740 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 237742 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 237746 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 237749 */     GIR_RootConstrainSelectedInstOperands,
     /* 237750 */     // GIR_Coverage, 2107,
     /* 237750 */     GIR_EraseRootFromParent_Done,
     /* 237751 */   // Label 4585: @237751
     /* 237751 */   GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(237864), // Rule ID 2103 //
     /* 237756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 237759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 237764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 237767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 237770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 237773 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 237776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237784 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 237792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 237796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 237800 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 237804 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 237808 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 237812 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 237816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237821 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 237825 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 237829 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 237833 */     // MIs[3] Operand 1
     /* 237833 */     // No operand predicates
     /* 237833 */     // MIs[1] Operand 2
     /* 237833 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 237844 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 237846 */     // (intrinsic_wo_chain:{ *:[v2i32] } 711:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 237846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32_indexed),
     /* 237849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237851 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237853 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 237855 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 237859 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 237862 */     GIR_RootConstrainSelectedInstOperands,
     /* 237863 */     // GIR_Coverage, 2103,
     /* 237863 */     GIR_EraseRootFromParent_Done,
     /* 237864 */   // Label 4586: @237864
     /* 237864 */   GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(237977), // Rule ID 2110 //
     /* 237869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 237872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 237877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 237880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 237883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 237886 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 237889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 237901 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 237905 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 237909 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 237913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 237917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 237921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 237925 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 237929 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 237934 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 237938 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 237942 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 237946 */     // MIs[3] Operand 1
     /* 237946 */     // No operand predicates
     /* 237946 */     // MIs[1] Operand 2
     /* 237946 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 237957 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 237959 */     // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 237959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32_indexed),
     /* 237962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 237964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 237966 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 237968 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 237972 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 237975 */     GIR_RootConstrainSelectedInstOperands,
     /* 237976 */     // GIR_Coverage, 2110,
     /* 237976 */     GIR_EraseRootFromParent_Done,
     /* 237977 */   // Label 4587: @237977
     /* 237977 */   GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(238082), // Rule ID 3962 //
     /* 237982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 237985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 237990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 237993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 237996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 237999 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 238002 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238006 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238010 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238014 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238018 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238022 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 238026 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238030 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238034 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238038 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238042 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238047 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238051 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238055 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 238059 */     // MIs[3] Operand 1
     /* 238059 */     // No operand predicates
     /* 238059 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238061 */     // (intrinsic_wo_chain:{ *:[v4f16] } 782:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 238061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 238064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238066 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238068 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238070 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238077 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 238080 */     GIR_RootConstrainSelectedInstOperands,
     /* 238081 */     // GIR_Coverage, 3962,
     /* 238081 */     GIR_EraseRootFromParent_Done,
     /* 238082 */   // Label 4588: @238082
     /* 238082 */   GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(238187), // Rule ID 3963 //
     /* 238087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 238095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 238098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 238101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 238104 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 238107 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238115 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 238131 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238135 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238139 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238143 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238147 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238152 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238156 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238160 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 238164 */     // MIs[3] Operand 1
     /* 238164 */     // No operand predicates
     /* 238164 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238166 */     // (intrinsic_wo_chain:{ *:[v4f16] } 785:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 238166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 238169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238173 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238179 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 238185 */     GIR_RootConstrainSelectedInstOperands,
     /* 238186 */     // GIR_Coverage, 3963,
     /* 238186 */     GIR_EraseRootFromParent_Done,
     /* 238187 */   // Label 4589: @238187
     /* 238187 */   GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(238292), // Rule ID 3964 //
     /* 238192 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238195 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 238200 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 238203 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 238206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 238209 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 238212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238216 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238220 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 238236 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238240 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238244 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238248 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238252 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238257 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238261 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238265 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 238269 */     // MIs[3] Operand 1
     /* 238269 */     // No operand predicates
     /* 238269 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238271 */     // (intrinsic_wo_chain:{ *:[v4f16] } 783:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 238271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 238274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238276 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238278 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238284 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238287 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 238290 */     GIR_RootConstrainSelectedInstOperands,
     /* 238291 */     // GIR_Coverage, 3964,
     /* 238291 */     GIR_EraseRootFromParent_Done,
     /* 238292 */   // Label 4590: @238292
     /* 238292 */   GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(238397), // Rule ID 3965 //
     /* 238297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 238305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 238308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 238311 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 238314 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 238317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 238329 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238333 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238337 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 238341 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238345 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238349 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238353 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238357 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238362 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238366 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238370 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 238374 */     // MIs[3] Operand 1
     /* 238374 */     // No operand predicates
     /* 238374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238376 */     // (intrinsic_wo_chain:{ *:[v4f16] } 784:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (bitconvert:{ *:[v4f16] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f16_indexed:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 238376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16_indexed),
     /* 238379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238381 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238383 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238389 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238392 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 238395 */     GIR_RootConstrainSelectedInstOperands,
     /* 238396 */     // GIR_Coverage, 3965,
     /* 238396 */     GIR_EraseRootFromParent_Done,
     /* 238397 */   // Label 4591: @238397
     /* 238397 */   GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(238502), // Rule ID 3970 //
     /* 238402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 238410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 238413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 238416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 238419 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 238422 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238426 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238430 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238442 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238446 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238450 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238454 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238458 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238462 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238467 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238471 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238475 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 238479 */     // MIs[3] Operand 1
     /* 238479 */     // No operand predicates
     /* 238479 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238481 */     // (intrinsic_wo_chain:{ *:[v8f16] } 782:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 238481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 238484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238490 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238494 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238497 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 238500 */     GIR_RootConstrainSelectedInstOperands,
     /* 238501 */     // GIR_Coverage, 3970,
     /* 238501 */     GIR_EraseRootFromParent_Done,
     /* 238502 */   // Label 4592: @238502
     /* 238502 */   GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(238607), // Rule ID 3971 //
     /* 238507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 238515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 238518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 238521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 238524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 238527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238535 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238551 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238555 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238559 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238563 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238567 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238572 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238576 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238580 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 238584 */     // MIs[3] Operand 1
     /* 238584 */     // No operand predicates
     /* 238584 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238586 */     // (intrinsic_wo_chain:{ *:[v8f16] } 785:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 238586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 238589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238595 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238599 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 238605 */     GIR_RootConstrainSelectedInstOperands,
     /* 238606 */     // GIR_Coverage, 3971,
     /* 238606 */     GIR_EraseRootFromParent_Done,
     /* 238607 */   // Label 4593: @238607
     /* 238607 */   GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(238712), // Rule ID 3972 //
     /* 238612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 238620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 238623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 238626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 238629 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 238632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238636 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238640 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238644 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238648 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238652 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238656 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238660 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238664 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238668 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238672 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238677 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238681 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238685 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 238689 */     // MIs[3] Operand 1
     /* 238689 */     // No operand predicates
     /* 238689 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238691 */     // (intrinsic_wo_chain:{ *:[v8f16] } 783:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 238691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 238694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238696 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238698 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238704 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 238710 */     GIR_RootConstrainSelectedInstOperands,
     /* 238711 */     // GIR_Coverage, 3972,
     /* 238711 */     GIR_EraseRootFromParent_Done,
     /* 238712 */   // Label 4594: @238712
     /* 238712 */   GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(238817), // Rule ID 3973 //
     /* 238717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 238720 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 238725 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 238728 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 238731 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 238734 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 238737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238741 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238745 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238753 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238757 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 238769 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 238773 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238777 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238782 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238786 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238790 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 238794 */     // MIs[3] Operand 1
     /* 238794 */     // No operand predicates
     /* 238794 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238796 */     // (intrinsic_wo_chain:{ *:[v8f16] } 784:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (bitconvert:{ *:[v8f16] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (FCMLAv8f16_indexed:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 238796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16_indexed),
     /* 238799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238801 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238803 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238809 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 238815 */     GIR_RootConstrainSelectedInstOperands,
     /* 238816 */     // GIR_Coverage, 3973,
     /* 238816 */     GIR_EraseRootFromParent_Done,
     /* 238817 */   // Label 4595: @238817
     /* 238817 */   GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(238922), // Rule ID 3986 //
     /* 238822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 238825 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 238830 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 238833 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 238836 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 238839 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 238842 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238850 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 238866 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238870 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 238874 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 238878 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238882 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238887 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238891 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 238895 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 238899 */     // MIs[3] Operand 1
     /* 238899 */     // No operand predicates
     /* 238899 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 238901 */     // (intrinsic_wo_chain:{ *:[v4f32] } 782:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 0:{ *:[i32] })
     /* 238901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 238904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 238906 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 238908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 238910 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 238914 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 238917 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 238920 */     GIR_RootConstrainSelectedInstOperands,
     /* 238921 */     // GIR_Coverage, 3986,
     /* 238921 */     GIR_EraseRootFromParent_Done,
     /* 238922 */   // Label 4596: @238922
     /* 238922 */   GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(239027), // Rule ID 3987 //
     /* 238927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 238930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 238935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 238938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 238941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 238944 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 238947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238955 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 238963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 238967 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 238971 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 238975 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 238979 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 238983 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 238987 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 238992 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 238996 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 239000 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 239004 */     // MIs[3] Operand 1
     /* 239004 */     // No operand predicates
     /* 239004 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 239006 */     // (intrinsic_wo_chain:{ *:[v4f32] } 785:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 1:{ *:[i32] })
     /* 239006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 239009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 239011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 239013 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 239015 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 239019 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 239022 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 239025 */     GIR_RootConstrainSelectedInstOperands,
     /* 239026 */     // GIR_Coverage, 3987,
     /* 239026 */     GIR_EraseRootFromParent_Done,
     /* 239027 */   // Label 4597: @239027
     /* 239027 */   GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(239132), // Rule ID 3988 //
     /* 239032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 239035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 239040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 239043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 239046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 239049 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 239052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239056 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239060 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 239068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 239072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 239076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 239080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 239084 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 239088 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 239092 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239097 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 239101 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 239105 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 239109 */     // MIs[3] Operand 1
     /* 239109 */     // No operand predicates
     /* 239109 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 239111 */     // (intrinsic_wo_chain:{ *:[v4f32] } 783:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 2:{ *:[i32] })
     /* 239111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 239114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 239116 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 239118 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 239120 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 239124 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 239127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 239130 */     GIR_RootConstrainSelectedInstOperands,
     /* 239131 */     // GIR_Coverage, 3988,
     /* 239131 */     GIR_EraseRootFromParent_Done,
     /* 239132 */   // Label 4598: @239132
     /* 239132 */   GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(239237), // Rule ID 3989 //
     /* 239137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 239140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 239145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 239148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 239151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 239154 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 239157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239165 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 239173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 239177 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 239181 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 239185 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 239189 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 239193 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 239197 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 239202 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 239206 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 239210 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 239214 */     // MIs[3] Operand 1
     /* 239214 */     // No operand predicates
     /* 239214 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 239216 */     // (intrinsic_wo_chain:{ *:[v4f32] } 784:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (bitconvert:{ *:[v4f32] } (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)))  =>  (FCMLAv4f32_indexed:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, 3:{ *:[i32] })
     /* 239216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32_indexed),
     /* 239219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 239221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 239223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 239225 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 239229 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 239232 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 239235 */     GIR_RootConstrainSelectedInstOperands,
     /* 239236 */     // GIR_Coverage, 3989,
     /* 239236 */     GIR_EraseRootFromParent_Done,
     /* 239237 */   // Label 4599: @239237
     /* 239237 */   GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(239293), // Rule ID 2691 //
     /* 239242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch),
     /* 239250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 239253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 239256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 239264 */     // MIs[0] pattern
     /* 239264 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239267 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239272 */     // MIs[0] imm4
     /* 239272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239275 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239280 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1863:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_ZPiI),
     /* 239283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 239285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 239287 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239289 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239291 */     GIR_RootConstrainSelectedInstOperands,
     /* 239292 */     // GIR_Coverage, 2691,
     /* 239292 */     GIR_EraseRootFromParent_Done,
     /* 239293 */   // Label 4600: @239293
     /* 239293 */   GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(239349), // Rule ID 2700 //
     /* 239298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n32),
     /* 239306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 239309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 239312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239316 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239320 */     // MIs[0] pattern
     /* 239320 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239323 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239328 */     // MIs[0] imm4
     /* 239328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239331 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239336 */     // (intrinsic_wo_chain:{ *:[i32] } 2073:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_WPiI),
     /* 239339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239343 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239345 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239347 */     GIR_RootConstrainSelectedInstOperands,
     /* 239348 */     // GIR_Coverage, 2700,
     /* 239348 */     GIR_EraseRootFromParent_Done,
     /* 239349 */   // Label 4601: @239349
     /* 239349 */   GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(239405), // Rule ID 2701 //
     /* 239354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincb_n64),
     /* 239362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239376 */     // MIs[0] pattern
     /* 239376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239379 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239384 */     // MIs[0] imm4
     /* 239384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239387 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239392 */     // (intrinsic_wo_chain:{ *:[i64] } 1859:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCB_XPiI),
     /* 239395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239397 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239399 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239401 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239403 */     GIR_RootConstrainSelectedInstOperands,
     /* 239404 */     // GIR_Coverage, 2701,
     /* 239404 */     GIR_EraseRootFromParent_Done,
     /* 239405 */   // Label 4602: @239405
     /* 239405 */   GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(239461), // Rule ID 10722 //
     /* 239410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n32),
     /* 239418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 239421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 239424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239428 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239432 */     // MIs[0] pattern
     /* 239432 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239435 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239440 */     // MIs[0] imm4
     /* 239440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239443 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239448 */     // (intrinsic_wo_chain:{ *:[i32] } 2059:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECB_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_WPiI),
     /* 239451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239455 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239457 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239459 */     GIR_RootConstrainSelectedInstOperands,
     /* 239460 */     // GIR_Coverage, 10722,
     /* 239460 */     GIR_EraseRootFromParent_Done,
     /* 239461 */   // Label 4603: @239461
     /* 239461 */   GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(239517), // Rule ID 10723 //
     /* 239466 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239469 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincb_n64),
     /* 239474 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239477 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239484 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239488 */     // MIs[0] pattern
     /* 239488 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239491 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239496 */     // MIs[0] imm4
     /* 239496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239499 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239504 */     // (intrinsic_wo_chain:{ *:[i64] } 2074:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239504 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCB_XPiI),
     /* 239507 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239509 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239511 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239513 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239515 */     GIR_RootConstrainSelectedInstOperands,
     /* 239516 */     // GIR_Coverage, 10723,
     /* 239516 */     GIR_EraseRootFromParent_Done,
     /* 239517 */   // Label 4604: @239517
     /* 239517 */   GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(239573), // Rule ID 10724 //
     /* 239522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecb_n64),
     /* 239530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239544 */     // MIs[0] pattern
     /* 239544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239547 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239552 */     // MIs[0] imm4
     /* 239552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239555 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239560 */     // (intrinsic_wo_chain:{ *:[i64] } 1825:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECB_XPiI),
     /* 239563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239567 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239569 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239571 */     GIR_RootConstrainSelectedInstOperands,
     /* 239572 */     // GIR_Coverage, 10724,
     /* 239572 */     GIR_EraseRootFromParent_Done,
     /* 239573 */   // Label 4605: @239573
     /* 239573 */   GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(239629), // Rule ID 10725 //
     /* 239578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecb_n64),
     /* 239586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239600 */     // MIs[0] pattern
     /* 239600 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239603 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239608 */     // MIs[0] imm4
     /* 239608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239611 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239616 */     // (intrinsic_wo_chain:{ *:[i64] } 2060:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECB_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECB_XPiI),
     /* 239619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239621 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239623 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239625 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239627 */     GIR_RootConstrainSelectedInstOperands,
     /* 239628 */     // GIR_Coverage, 10725,
     /* 239628 */     GIR_EraseRootFromParent_Done,
     /* 239629 */   // Label 4606: @239629
     /* 239629 */   GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(239685), // Rule ID 10728 //
     /* 239634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239637 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n32),
     /* 239642 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 239645 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 239648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239652 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239656 */     // MIs[0] pattern
     /* 239656 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239659 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239664 */     // MIs[0] imm4
     /* 239664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239667 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239672 */     // (intrinsic_wo_chain:{ *:[i32] } 2079:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_WPiI),
     /* 239675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239679 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239681 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239683 */     GIR_RootConstrainSelectedInstOperands,
     /* 239684 */     // GIR_Coverage, 10728,
     /* 239684 */     GIR_EraseRootFromParent_Done,
     /* 239685 */   // Label 4607: @239685
     /* 239685 */   GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(239741), // Rule ID 10731 //
     /* 239690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n32),
     /* 239698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 239701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 239704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239712 */     // MIs[0] pattern
     /* 239712 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239715 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239720 */     // MIs[0] imm4
     /* 239720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239723 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239728 */     // (intrinsic_wo_chain:{ *:[i32] } 2065:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_WPiI),
     /* 239731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239733 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239735 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239737 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239739 */     GIR_RootConstrainSelectedInstOperands,
     /* 239740 */     // GIR_Coverage, 10731,
     /* 239740 */     GIR_EraseRootFromParent_Done,
     /* 239741 */   // Label 4608: @239741
     /* 239741 */   GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(239797), // Rule ID 10732 //
     /* 239746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqinch_n64),
     /* 239754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239768 */     // MIs[0] pattern
     /* 239768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239776 */     // MIs[0] imm4
     /* 239776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239779 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239784 */     // (intrinsic_wo_chain:{ *:[i64] } 1865:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCH_XPiI),
     /* 239787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239791 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239793 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239795 */     GIR_RootConstrainSelectedInstOperands,
     /* 239796 */     // GIR_Coverage, 10732,
     /* 239796 */     GIR_EraseRootFromParent_Done,
     /* 239797 */   // Label 4609: @239797
     /* 239797 */   GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(239853), // Rule ID 10733 //
     /* 239802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch_n64),
     /* 239810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239824 */     // MIs[0] pattern
     /* 239824 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239827 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239832 */     // MIs[0] imm4
     /* 239832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239835 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239840 */     // (intrinsic_wo_chain:{ *:[i64] } 2080:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_XPiI),
     /* 239843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239847 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239849 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239851 */     GIR_RootConstrainSelectedInstOperands,
     /* 239852 */     // GIR_Coverage, 10733,
     /* 239852 */     GIR_EraseRootFromParent_Done,
     /* 239853 */   // Label 4610: @239853
     /* 239853 */   GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(239909), // Rule ID 10734 //
     /* 239858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239861 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech_n64),
     /* 239866 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239869 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239876 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239880 */     // MIs[0] pattern
     /* 239880 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239883 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239888 */     // MIs[0] imm4
     /* 239888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239891 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239896 */     // (intrinsic_wo_chain:{ *:[i64] } 1831:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239896 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_XPiI),
     /* 239899 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239903 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239905 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239907 */     GIR_RootConstrainSelectedInstOperands,
     /* 239908 */     // GIR_Coverage, 10734,
     /* 239908 */     GIR_EraseRootFromParent_Done,
     /* 239909 */   // Label 4611: @239909
     /* 239909 */   GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(239965), // Rule ID 10735 //
     /* 239914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech_n64),
     /* 239922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 239925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 239928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239932 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 239936 */     // MIs[0] pattern
     /* 239936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239939 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 239944 */     // MIs[0] imm4
     /* 239944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 239947 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 239952 */     // (intrinsic_wo_chain:{ *:[i64] } 2066:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 239952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_XPiI),
     /* 239955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 239957 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 239959 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 239961 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 239963 */     GIR_RootConstrainSelectedInstOperands,
     /* 239964 */     // GIR_Coverage, 10735,
     /* 239964 */     GIR_EraseRootFromParent_Done,
     /* 239965 */   // Label 4612: @239965
     /* 239965 */   GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(240021), // Rule ID 10738 //
     /* 239970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 239973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n32),
     /* 239978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 239981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 239984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 239992 */     // MIs[0] pattern
     /* 239992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 239995 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240000 */     // MIs[0] imm4
     /* 240000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240003 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240008 */     // (intrinsic_wo_chain:{ *:[i32] } 2085:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_WPiI),
     /* 240011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240015 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240017 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240019 */     GIR_RootConstrainSelectedInstOperands,
     /* 240020 */     // GIR_Coverage, 10738,
     /* 240020 */     GIR_EraseRootFromParent_Done,
     /* 240021 */   // Label 4613: @240021
     /* 240021 */   GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(240077), // Rule ID 10741 //
     /* 240026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n32),
     /* 240034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 240037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 240040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240048 */     // MIs[0] pattern
     /* 240048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240051 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240056 */     // MIs[0] imm4
     /* 240056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240059 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240064 */     // (intrinsic_wo_chain:{ *:[i32] } 2071:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_WPiI),
     /* 240067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240069 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240071 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240073 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240075 */     GIR_RootConstrainSelectedInstOperands,
     /* 240076 */     // GIR_Coverage, 10741,
     /* 240076 */     GIR_EraseRootFromParent_Done,
     /* 240077 */   // Label 4614: @240077
     /* 240077 */   GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(240133), // Rule ID 10742 //
     /* 240082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw_n64),
     /* 240090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240104 */     // MIs[0] pattern
     /* 240104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240107 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240112 */     // MIs[0] imm4
     /* 240112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240115 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240120 */     // (intrinsic_wo_chain:{ *:[i64] } 1871:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_XPiI),
     /* 240123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240127 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240129 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240131 */     GIR_RootConstrainSelectedInstOperands,
     /* 240132 */     // GIR_Coverage, 10742,
     /* 240132 */     GIR_EraseRootFromParent_Done,
     /* 240133 */   // Label 4615: @240133
     /* 240133 */   GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(240189), // Rule ID 10743 //
     /* 240138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw_n64),
     /* 240146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240160 */     // MIs[0] pattern
     /* 240160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240163 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240168 */     // MIs[0] imm4
     /* 240168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240171 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240176 */     // (intrinsic_wo_chain:{ *:[i64] } 2086:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_XPiI),
     /* 240179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240183 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240185 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240187 */     GIR_RootConstrainSelectedInstOperands,
     /* 240188 */     // GIR_Coverage, 10743,
     /* 240188 */     GIR_EraseRootFromParent_Done,
     /* 240189 */   // Label 4616: @240189
     /* 240189 */   GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(240245), // Rule ID 10744 //
     /* 240194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw_n64),
     /* 240202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240216 */     // MIs[0] pattern
     /* 240216 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240219 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240224 */     // MIs[0] imm4
     /* 240224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240227 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240232 */     // (intrinsic_wo_chain:{ *:[i64] } 1837:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_XPiI),
     /* 240235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240237 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240239 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240241 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240243 */     GIR_RootConstrainSelectedInstOperands,
     /* 240244 */     // GIR_Coverage, 10744,
     /* 240244 */     GIR_EraseRootFromParent_Done,
     /* 240245 */   // Label 4617: @240245
     /* 240245 */   GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(240301), // Rule ID 10745 //
     /* 240250 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240253 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw_n64),
     /* 240258 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240261 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240268 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240272 */     // MIs[0] pattern
     /* 240272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240275 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240280 */     // MIs[0] imm4
     /* 240280 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240283 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240288 */     // (intrinsic_wo_chain:{ *:[i64] } 2072:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_XPiI),
     /* 240291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240295 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240297 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240299 */     GIR_RootConstrainSelectedInstOperands,
     /* 240300 */     // GIR_Coverage, 10745,
     /* 240300 */     GIR_EraseRootFromParent_Done,
     /* 240301 */   // Label 4618: @240301
     /* 240301 */   GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(240357), // Rule ID 10748 //
     /* 240306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n32),
     /* 240314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 240317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 240320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240328 */     // MIs[0] pattern
     /* 240328 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240331 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240336 */     // MIs[0] imm4
     /* 240336 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240339 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240344 */     // (intrinsic_wo_chain:{ *:[i32] } 2076:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_WPiI),
     /* 240347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240351 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240353 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240355 */     GIR_RootConstrainSelectedInstOperands,
     /* 240356 */     // GIR_Coverage, 10748,
     /* 240356 */     GIR_EraseRootFromParent_Done,
     /* 240357 */   // Label 4619: @240357
     /* 240357 */   GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(240413), // Rule ID 10751 //
     /* 240362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240365 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n32),
     /* 240370 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 240373 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 240376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 240384 */     // MIs[0] pattern
     /* 240384 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240387 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240392 */     // MIs[0] imm4
     /* 240392 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240395 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240400 */     // (intrinsic_wo_chain:{ *:[i32] } 2062:{ *:[iPTR] }, GPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_WPiI:{ *:[i32] } ?:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_WPiI),
     /* 240403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240407 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240409 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240411 */     GIR_RootConstrainSelectedInstOperands,
     /* 240412 */     // GIR_Coverage, 10751,
     /* 240412 */     GIR_EraseRootFromParent_Done,
     /* 240413 */   // Label 4620: @240413
     /* 240413 */   GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(240469), // Rule ID 10752 //
     /* 240418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd_n64),
     /* 240426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240432 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240436 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240440 */     // MIs[0] pattern
     /* 240440 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240443 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240448 */     // MIs[0] imm4
     /* 240448 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240451 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240456 */     // (intrinsic_wo_chain:{ *:[i64] } 1862:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_XPiI),
     /* 240459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240461 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240463 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240465 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240467 */     GIR_RootConstrainSelectedInstOperands,
     /* 240468 */     // GIR_Coverage, 10752,
     /* 240468 */     GIR_EraseRootFromParent_Done,
     /* 240469 */   // Label 4621: @240469
     /* 240469 */   GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(240525), // Rule ID 10753 //
     /* 240474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd_n64),
     /* 240482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240496 */     // MIs[0] pattern
     /* 240496 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240499 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240504 */     // MIs[0] imm4
     /* 240504 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240507 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240512 */     // (intrinsic_wo_chain:{ *:[i64] } 2077:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_XPiI),
     /* 240515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240519 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240521 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240523 */     GIR_RootConstrainSelectedInstOperands,
     /* 240524 */     // GIR_Coverage, 10753,
     /* 240524 */     GIR_EraseRootFromParent_Done,
     /* 240525 */   // Label 4622: @240525
     /* 240525 */   GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(240581), // Rule ID 10754 //
     /* 240530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd_n64),
     /* 240538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240552 */     // MIs[0] pattern
     /* 240552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240555 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240560 */     // MIs[0] imm4
     /* 240560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240563 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240568 */     // (intrinsic_wo_chain:{ *:[i64] } 1828:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_XPiI),
     /* 240571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240575 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240577 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240579 */     GIR_RootConstrainSelectedInstOperands,
     /* 240580 */     // GIR_Coverage, 10754,
     /* 240580 */     GIR_EraseRootFromParent_Done,
     /* 240581 */   // Label 4623: @240581
     /* 240581 */   GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(240637), // Rule ID 10755 //
     /* 240586 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240589 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd_n64),
     /* 240594 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 240597 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 240600 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240604 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 240608 */     // MIs[0] pattern
     /* 240608 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240611 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240616 */     // MIs[0] imm4
     /* 240616 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240619 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240624 */     // (intrinsic_wo_chain:{ *:[i64] } 2063:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_XPiI:{ *:[i64] } ?:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_XPiI),
     /* 240627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
     /* 240629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 240631 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240633 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240635 */     GIR_RootConstrainSelectedInstOperands,
     /* 240636 */     // GIR_Coverage, 10755,
     /* 240636 */     GIR_EraseRootFromParent_Done,
     /* 240637 */   // Label 4624: @240637
     /* 240637 */   GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(240693), // Rule ID 10756 //
     /* 240642 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240645 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqinch),
     /* 240650 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240653 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 240656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240660 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240664 */     // MIs[0] pattern
     /* 240664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240667 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240672 */     // MIs[0] imm4
     /* 240672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240675 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240680 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2078:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCH_ZPiI),
     /* 240683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240687 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240689 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240691 */     GIR_RootConstrainSelectedInstOperands,
     /* 240692 */     // GIR_Coverage, 10756,
     /* 240692 */     GIR_EraseRootFromParent_Done,
     /* 240693 */   // Label 4625: @240693
     /* 240693 */   GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(240749), // Rule ID 10757 //
     /* 240698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdech),
     /* 240706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 240712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240716 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240720 */     // MIs[0] pattern
     /* 240720 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240723 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240728 */     // MIs[0] imm4
     /* 240728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240731 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240736 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1829:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECH_ZPiI),
     /* 240739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240743 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240745 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240747 */     GIR_RootConstrainSelectedInstOperands,
     /* 240748 */     // GIR_Coverage, 10757,
     /* 240748 */     GIR_EraseRootFromParent_Done,
     /* 240749 */   // Label 4626: @240749
     /* 240749 */   GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(240805), // Rule ID 10758 //
     /* 240754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdech),
     /* 240762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 240765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 240768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240772 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240776 */     // MIs[0] pattern
     /* 240776 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240779 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240784 */     // MIs[0] imm4
     /* 240784 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240787 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240792 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2064:{ *:[iPTR] }, ZPR16:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECH_ZPiI:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240792 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECH_ZPiI),
     /* 240795 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240797 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240799 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240801 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240803 */     GIR_RootConstrainSelectedInstOperands,
     /* 240804 */     // GIR_Coverage, 10758,
     /* 240804 */     GIR_EraseRootFromParent_Done,
     /* 240805 */   // Label 4627: @240805
     /* 240805 */   GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(240861), // Rule ID 10759 //
     /* 240810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincw),
     /* 240818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240832 */     // MIs[0] pattern
     /* 240832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240835 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240840 */     // MIs[0] imm4
     /* 240840 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240843 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240848 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1869:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCW_ZPiI),
     /* 240851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240853 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240855 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240857 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240859 */     GIR_RootConstrainSelectedInstOperands,
     /* 240860 */     // GIR_Coverage, 10759,
     /* 240860 */     GIR_EraseRootFromParent_Done,
     /* 240861 */   // Label 4628: @240861
     /* 240861 */   GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(240917), // Rule ID 10760 //
     /* 240866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240869 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincw),
     /* 240874 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240877 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240884 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240888 */     // MIs[0] pattern
     /* 240888 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240891 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240896 */     // MIs[0] imm4
     /* 240896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240899 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240904 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2084:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCW_ZPiI),
     /* 240907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240911 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240913 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240915 */     GIR_RootConstrainSelectedInstOperands,
     /* 240916 */     // GIR_Coverage, 10760,
     /* 240916 */     GIR_EraseRootFromParent_Done,
     /* 240917 */   // Label 4629: @240917
     /* 240917 */   GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(240973), // Rule ID 10761 //
     /* 240922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240925 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecw),
     /* 240930 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240933 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240936 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240944 */     // MIs[0] pattern
     /* 240944 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 240947 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 240952 */     // MIs[0] imm4
     /* 240952 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 240955 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 240960 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1835:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 240960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECW_ZPiI),
     /* 240963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 240965 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 240967 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 240969 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 240971 */     GIR_RootConstrainSelectedInstOperands,
     /* 240972 */     // GIR_Coverage, 10761,
     /* 240972 */     GIR_EraseRootFromParent_Done,
     /* 240973 */   // Label 4630: @240973
     /* 240973 */   GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(241029), // Rule ID 10762 //
     /* 240978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 240981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecw),
     /* 240986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 240989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 240992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 240996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241000 */     // MIs[0] pattern
     /* 241000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 241003 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 241008 */     // MIs[0] imm4
     /* 241008 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 241011 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 241016 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2070:{ *:[iPTR] }, ZPR32:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECW_ZPiI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 241016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECW_ZPiI),
     /* 241019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241021 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 241023 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 241025 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 241027 */     GIR_RootConstrainSelectedInstOperands,
     /* 241028 */     // GIR_Coverage, 10762,
     /* 241028 */     GIR_EraseRootFromParent_Done,
     /* 241029 */   // Label 4631: @241029
     /* 241029 */   GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(241085), // Rule ID 10763 //
     /* 241034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqincd),
     /* 241042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241052 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241056 */     // MIs[0] pattern
     /* 241056 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 241059 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 241064 */     // MIs[0] imm4
     /* 241064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 241067 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 241072 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1860:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 241072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQINCD_ZPiI),
     /* 241075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 241079 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 241081 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 241083 */     GIR_RootConstrainSelectedInstOperands,
     /* 241084 */     // GIR_Coverage, 10763,
     /* 241084 */     GIR_EraseRootFromParent_Done,
     /* 241085 */   // Label 4632: @241085
     /* 241085 */   GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(241141), // Rule ID 10764 //
     /* 241090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241093 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqincd),
     /* 241098 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241101 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241112 */     // MIs[0] pattern
     /* 241112 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 241115 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 241120 */     // MIs[0] imm4
     /* 241120 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 241123 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 241128 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2075:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQINCD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 241128 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQINCD_ZPiI),
     /* 241131 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241133 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 241135 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 241137 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 241139 */     GIR_RootConstrainSelectedInstOperands,
     /* 241140 */     // GIR_Coverage, 10764,
     /* 241140 */     GIR_EraseRootFromParent_Done,
     /* 241141 */   // Label 4633: @241141
     /* 241141 */   GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(241197), // Rule ID 10765 //
     /* 241146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241149 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdecd),
     /* 241154 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241157 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241164 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241168 */     // MIs[0] pattern
     /* 241168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 241171 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 241176 */     // MIs[0] imm4
     /* 241176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 241179 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 241184 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1826:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (SQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 241184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDECD_ZPiI),
     /* 241187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241189 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 241191 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 241193 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 241195 */     GIR_RootConstrainSelectedInstOperands,
     /* 241196 */     // GIR_Coverage, 10765,
     /* 241196 */     GIR_EraseRootFromParent_Done,
     /* 241197 */   // Label 4634: @241197
     /* 241197 */   GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(241253), // Rule ID 10766 //
     /* 241202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 241205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqdecd),
     /* 241210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 241213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 241216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241220 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 241224 */     // MIs[0] pattern
     /* 241224 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 241227 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_pred_enum),
     /* 241232 */     // MIs[0] imm4
     /* 241232 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 241235 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_incdec_imm),
     /* 241240 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2061:{ *:[iPTR] }, ZPR64:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)  =>  (UQDECD_ZPiI:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Zn, (timm:{ *:[i32] })<<P:Predicate_sve_pred_enum>>:$pattern, (timm:{ *:[i32] })<<P:Predicate_sve_incdec_imm>>:$imm4)
     /* 241240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQDECD_ZPiI),
     /* 241243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 241245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 241247 */     GIR_RootToRootCopy, /*OpIdx*/3, // pattern
     /* 241249 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm4
     /* 241251 */     GIR_RootConstrainSelectedInstOperands,
     /* 241252 */     // GIR_Coverage, 10766,
     /* 241252 */     GIR_EraseRootFromParent_Done,
     /* 241253 */   // Label 4635: @241253
     /* 241253 */   GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(241343), // Rule ID 47 //
     /* 241258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 241266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 241269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 241272 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 241275 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 241278 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241286 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241298 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241302 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241306 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241311 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241315 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241319 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241323 */     // MIs[2] Operand 1
     /* 241323 */     // No operand predicates
     /* 241323 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241325 */     // (intrinsic_wo_chain:{ *:[v2f32] } 630:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLALlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev4f16),
     /* 241328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241334 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241338 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241341 */     GIR_RootConstrainSelectedInstOperands,
     /* 241342 */     // GIR_Coverage, 47,
     /* 241342 */     GIR_EraseRootFromParent_Done,
     /* 241343 */   // Label 4636: @241343
     /* 241343 */   GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(241433), // Rule ID 48 //
     /* 241348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 241356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 241359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 241362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 241365 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 241368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241376 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241388 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241392 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241396 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241401 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241405 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241409 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241413 */     // MIs[2] Operand 1
     /* 241413 */     // No operand predicates
     /* 241413 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241415 */     // (intrinsic_wo_chain:{ *:[v4f32] } 630:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLALlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALlanev8f16),
     /* 241418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241420 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241422 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241424 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241428 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241431 */     GIR_RootConstrainSelectedInstOperands,
     /* 241432 */     // GIR_Coverage, 48,
     /* 241432 */     GIR_EraseRootFromParent_Done,
     /* 241433 */   // Label 4637: @241433
     /* 241433 */   GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(241523), // Rule ID 49 //
     /* 241438 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241441 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 241446 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 241449 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 241452 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 241455 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 241458 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241466 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241474 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241478 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241482 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241486 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241491 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241495 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241499 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241503 */     // MIs[2] Operand 1
     /* 241503 */     // No operand predicates
     /* 241503 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241505 */     // (intrinsic_wo_chain:{ *:[v2f32] } 632:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSLlanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev4f16),
     /* 241508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241514 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241518 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241521 */     GIR_RootConstrainSelectedInstOperands,
     /* 241522 */     // GIR_Coverage, 49,
     /* 241522 */     GIR_EraseRootFromParent_Done,
     /* 241523 */   // Label 4638: @241523
     /* 241523 */   GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(241613), // Rule ID 50 //
     /* 241528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241531 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 241536 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 241539 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 241542 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 241545 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 241548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241552 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241556 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241568 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241572 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241589 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241593 */     // MIs[2] Operand 1
     /* 241593 */     // No operand predicates
     /* 241593 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241595 */     // (intrinsic_wo_chain:{ *:[v4f32] } 632:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSLlanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLlanev8f16),
     /* 241598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241604 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241608 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241611 */     GIR_RootConstrainSelectedInstOperands,
     /* 241612 */     // GIR_Coverage, 50,
     /* 241612 */     GIR_EraseRootFromParent_Done,
     /* 241613 */   // Label 4639: @241613
     /* 241613 */   GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(241703), // Rule ID 51 //
     /* 241618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 241626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 241629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 241632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 241635 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 241638 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241642 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241646 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241658 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241662 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241666 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241671 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241675 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241679 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241683 */     // MIs[2] Operand 1
     /* 241683 */     // No operand predicates
     /* 241683 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241685 */     // (intrinsic_wo_chain:{ *:[v2f32] } 631:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLAL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev4f16),
     /* 241688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241694 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241698 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241701 */     GIR_RootConstrainSelectedInstOperands,
     /* 241702 */     // GIR_Coverage, 51,
     /* 241702 */     GIR_EraseRootFromParent_Done,
     /* 241703 */   // Label 4640: @241703
     /* 241703 */   GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(241793), // Rule ID 52 //
     /* 241708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241711 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 241716 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 241719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 241722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 241725 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 241728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241736 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241740 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241744 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241748 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241752 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241756 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241769 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241773 */     // MIs[2] Operand 1
     /* 241773 */     // No operand predicates
     /* 241773 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241775 */     // (intrinsic_wo_chain:{ *:[v4f32] } 631:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLAL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2lanev8f16),
     /* 241778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241782 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241784 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241788 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241791 */     GIR_RootConstrainSelectedInstOperands,
     /* 241792 */     // GIR_Coverage, 52,
     /* 241792 */     GIR_EraseRootFromParent_Done,
     /* 241793 */   // Label 4641: @241793
     /* 241793 */   GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(241883), // Rule ID 53 //
     /* 241798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 241806 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 241809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 241812 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 241815 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 241818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241822 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241826 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 241830 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241834 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241838 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241842 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241846 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241851 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241855 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241859 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241863 */     // MIs[2] Operand 1
     /* 241863 */     // No operand predicates
     /* 241863 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241865 */     // (intrinsic_wo_chain:{ *:[v2f32] } 633:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSL2lanev4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev4f16),
     /* 241868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241874 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241878 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241881 */     GIR_RootConstrainSelectedInstOperands,
     /* 241882 */     // GIR_Coverage, 53,
     /* 241882 */     GIR_EraseRootFromParent_Done,
     /* 241883 */   // Label 4642: @241883
     /* 241883 */   GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(241973), // Rule ID 54 //
     /* 241888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 241891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 241896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 241899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 241902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 241905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 241908 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241912 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241916 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 241920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 241924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 241928 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 241932 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 241936 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 241941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 241945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 241949 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 241953 */     // MIs[2] Operand 1
     /* 241953 */     // No operand predicates
     /* 241953 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 241955 */     // (intrinsic_wo_chain:{ *:[v4f32] } 633:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMLSL2lanev8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 241955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2lanev8f16),
     /* 241958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 241960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 241962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 241964 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 241968 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 241971 */     GIR_RootConstrainSelectedInstOperands,
     /* 241972 */     // GIR_Coverage, 54,
     /* 241972 */     GIR_EraseRootFromParent_Done,
     /* 241973 */   // Label 4643: @241973
     /* 241973 */   GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(242063), // Rule ID 2101 //
     /* 241978 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 241981 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 241986 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 241989 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 241992 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 241995 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 241998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242006 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 242018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 242022 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242026 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 242031 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242035 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242039 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 242043 */     // MIs[2] Operand 1
     /* 242043 */     // No operand predicates
     /* 242043 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242045 */     // (intrinsic_wo_chain:{ *:[v4i16] } 711:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLAHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16_indexed),
     /* 242048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242050 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242052 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242054 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242058 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242061 */     GIR_RootConstrainSelectedInstOperands,
     /* 242062 */     // GIR_Coverage, 2101,
     /* 242062 */     GIR_EraseRootFromParent_Done,
     /* 242063 */   // Label 4644: @242063
     /* 242063 */   GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(242153), // Rule ID 2102 //
     /* 242068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 242076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 242079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 242082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 242085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 242088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 242108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 242112 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242116 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 242121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242129 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 242133 */     // MIs[2] Operand 1
     /* 242133 */     // No operand predicates
     /* 242133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242135 */     // (intrinsic_wo_chain:{ *:[v8i16] } 711:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLAHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16_indexed),
     /* 242138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242148 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242151 */     GIR_RootConstrainSelectedInstOperands,
     /* 242152 */     // GIR_Coverage, 2102,
     /* 242152 */     GIR_EraseRootFromParent_Done,
     /* 242153 */   // Label 4645: @242153
     /* 242153 */   GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(242243), // Rule ID 2108 //
     /* 242158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242161 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 242166 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 242169 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 242172 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 242175 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 242178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242182 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242186 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 242198 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 242202 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242206 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 242211 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242215 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242219 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 242223 */     // MIs[2] Operand 1
     /* 242223 */     // No operand predicates
     /* 242223 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242225 */     // (intrinsic_wo_chain:{ *:[v4i16] } 712:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLSHv4i16_indexed:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16_indexed),
     /* 242228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242230 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242232 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242234 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242238 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242241 */     GIR_RootConstrainSelectedInstOperands,
     /* 242242 */     // GIR_Coverage, 2108,
     /* 242242 */     GIR_EraseRootFromParent_Done,
     /* 242243 */   // Label 4646: @242243
     /* 242243 */   GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(242333), // Rule ID 2109 //
     /* 242248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 242256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 242259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 242262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 242265 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 242268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242272 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242276 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 242288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 242292 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 242301 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242305 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242309 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 242313 */     // MIs[2] Operand 1
     /* 242313 */     // No operand predicates
     /* 242313 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242315 */     // (intrinsic_wo_chain:{ *:[v8i16] } 712:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SQRDMLSHv8i16_indexed:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16_indexed),
     /* 242318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242320 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242322 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242324 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242328 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242331 */     GIR_RootConstrainSelectedInstOperands,
     /* 242332 */     // GIR_Coverage, 2109,
     /* 242332 */     GIR_EraseRootFromParent_Done,
     /* 242333 */   // Label 4647: @242333
     /* 242333 */   GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(242423), // Rule ID 2104 //
     /* 242338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 242346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 242349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 242352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 242355 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 242358 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242362 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242366 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 242378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242391 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242395 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242399 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242403 */     // MIs[2] Operand 1
     /* 242403 */     // No operand predicates
     /* 242403 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242405 */     // (intrinsic_wo_chain:{ *:[v2i32] } 711:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32_indexed),
     /* 242408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242410 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242412 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242414 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242418 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242421 */     GIR_RootConstrainSelectedInstOperands,
     /* 242422 */     // GIR_Coverage, 2104,
     /* 242422 */     GIR_EraseRootFromParent_Done,
     /* 242423 */   // Label 4648: @242423
     /* 242423 */   GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(242513), // Rule ID 2105 //
     /* 242428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242431 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 242436 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 242439 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 242442 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 242445 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 242448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242456 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242460 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242464 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 242468 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242472 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242476 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242489 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242493 */     // MIs[2] Operand 1
     /* 242493 */     // No operand predicates
     /* 242493 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242495 */     // (intrinsic_wo_chain:{ *:[v4i32] } 711:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32_indexed),
     /* 242498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242502 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242504 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242508 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242511 */     GIR_RootConstrainSelectedInstOperands,
     /* 242512 */     // GIR_Coverage, 2105,
     /* 242512 */     GIR_EraseRootFromParent_Done,
     /* 242513 */   // Label 4649: @242513
     /* 242513 */   GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(242603), // Rule ID 2111 //
     /* 242518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242521 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 242526 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 242529 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 242532 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 242535 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 242538 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242542 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242546 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 242550 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242554 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 242558 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242562 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242566 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242579 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242583 */     // MIs[2] Operand 1
     /* 242583 */     // No operand predicates
     /* 242583 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242585 */     // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv2i32_indexed:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32_indexed),
     /* 242588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242590 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242592 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242598 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242601 */     GIR_RootConstrainSelectedInstOperands,
     /* 242602 */     // GIR_Coverage, 2111,
     /* 242602 */     GIR_EraseRootFromParent_Done,
     /* 242603 */   // Label 4650: @242603
     /* 242603 */   GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(242693), // Rule ID 2112 //
     /* 242608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242611 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 242616 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 242619 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 242622 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 242625 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 242628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242636 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 242648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242652 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242656 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242661 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242665 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242669 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242673 */     // MIs[2] Operand 1
     /* 242673 */     // No operand predicates
     /* 242673 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242675 */     // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv4i32_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32_indexed),
     /* 242678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242680 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242682 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242688 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242691 */     GIR_RootConstrainSelectedInstOperands,
     /* 242692 */     // GIR_Coverage, 2112,
     /* 242692 */     GIR_EraseRootFromParent_Done,
     /* 242693 */   // Label 4651: @242693
     /* 242693 */   GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(242783), // Rule ID 2106 //
     /* 242698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 242706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 242709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 242712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 242715 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 242718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242722 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242726 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 242738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242742 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242746 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242751 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242755 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242759 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242763 */     // MIs[2] Operand 1
     /* 242763 */     // No operand predicates
     /* 242763 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242765 */     // (intrinsic_wo_chain:{ *:[i32] } 711:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLAHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32_indexed),
     /* 242768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242778 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242781 */     GIR_RootConstrainSelectedInstOperands,
     /* 242782 */     // GIR_Coverage, 2106,
     /* 242782 */     GIR_EraseRootFromParent_Done,
     /* 242783 */   // Label 4652: @242783
     /* 242783 */   GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(242873), // Rule ID 2113 //
     /* 242788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 242791 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 242796 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 242799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 242802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 242805 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 242808 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242812 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242816 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 242820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 242828 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 242832 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 242836 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 242841 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 242845 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 242849 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 242853 */     // MIs[2] Operand 1
     /* 242853 */     // No operand predicates
     /* 242853 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242855 */     // (intrinsic_wo_chain:{ *:[i32] } 712:{ *:[iPTR] }, FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SQRDMLSHv1i32_indexed:{ *:[i32] } FPR32Op:{ *:[i32] }:$Rd, FPR32Op:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 242855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32_indexed),
     /* 242858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 242860 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 242862 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 242864 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 242868 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 242871 */     GIR_RootConstrainSelectedInstOperands,
     /* 242872 */     // GIR_Coverage, 2113,
     /* 242872 */     GIR_EraseRootFromParent_Done,
     /* 242873 */   // Label 4653: @242873
     /* 242873 */   GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(242950), // Rule ID 2826 //
     /* 242878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242881 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 242886 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242889 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242892 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242895 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242902 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 242906 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242910 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242914 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 242918 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 242922 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 242926 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 242930 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 242934 */     // MIs[2] Operand 1
     /* 242934 */     // No operand predicates
     /* 242934 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 242936 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 242936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_H),
     /* 242939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 242941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 242943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 242945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 242948 */     GIR_RootConstrainSelectedInstOperands,
     /* 242949 */     // GIR_Coverage, 2826,
     /* 242949 */     GIR_EraseRootFromParent_Done,
     /* 242950 */   // Label 4654: @242950
     /* 242950 */   GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(243027), // Rule ID 2827 //
     /* 242955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 242958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 242963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 242966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 242969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 242972 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 242975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 242983 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 242987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 242991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 242995 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 242999 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243003 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243007 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243011 */     // MIs[2] Operand 1
     /* 243011 */     // No operand predicates
     /* 243011 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243013 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 243013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_H),
     /* 243016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243022 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243025 */     GIR_RootConstrainSelectedInstOperands,
     /* 243026 */     // GIR_Coverage, 2827,
     /* 243026 */     GIR_EraseRootFromParent_Done,
     /* 243027 */   // Label 4655: @243027
     /* 243027 */   GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(243104), // Rule ID 2828 //
     /* 243032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 243040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243049 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243052 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243056 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243060 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 243076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243084 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243088 */     // MIs[2] Operand 1
     /* 243088 */     // No operand predicates
     /* 243088 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243090 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 243090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_S),
     /* 243093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243099 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243102 */     GIR_RootConstrainSelectedInstOperands,
     /* 243103 */     // GIR_Coverage, 2828,
     /* 243103 */     GIR_EraseRootFromParent_Done,
     /* 243104 */   // Label 4656: @243104
     /* 243104 */   GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(243181), // Rule ID 2829 //
     /* 243109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 243117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243126 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243133 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243137 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243141 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243145 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243149 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 243153 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243157 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243161 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243165 */     // MIs[2] Operand 1
     /* 243165 */     // No operand predicates
     /* 243165 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243167 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 243167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_S),
     /* 243170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243179 */     GIR_RootConstrainSelectedInstOperands,
     /* 243180 */     // GIR_Coverage, 2829,
     /* 243180 */     GIR_EraseRootFromParent_Done,
     /* 243181 */   // Label 4657: @243181
     /* 243181 */   GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(243258), // Rule ID 2830 //
     /* 243186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243189 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 243194 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243197 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243200 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243203 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243214 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 243230 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243234 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243238 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243242 */     // MIs[2] Operand 1
     /* 243242 */     // No operand predicates
     /* 243242 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243244 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FADD_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 243244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_D),
     /* 243247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243256 */     GIR_RootConstrainSelectedInstOperands,
     /* 243257 */     // GIR_Coverage, 2830,
     /* 243257 */     GIR_EraseRootFromParent_Done,
     /* 243258 */   // Label 4658: @243258
     /* 243258 */   GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(243335), // Rule ID 2831 //
     /* 243263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 243271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243280 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243287 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243291 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243295 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243299 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243303 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 243307 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243311 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243315 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243319 */     // MIs[2] Operand 1
     /* 243319 */     // No operand predicates
     /* 243319 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243321 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1395:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FADD_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 243321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmI_D),
     /* 243324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243326 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243328 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243333 */     GIR_RootConstrainSelectedInstOperands,
     /* 243334 */     // GIR_Coverage, 2831,
     /* 243334 */     GIR_EraseRootFromParent_Done,
     /* 243335 */   // Label 4659: @243335
     /* 243335 */   GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(243412), // Rule ID 8540 //
     /* 243340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243364 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243368 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 243384 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243388 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243392 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243396 */     // MIs[2] Operand 1
     /* 243396 */     // No operand predicates
     /* 243396 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243398 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 243398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_H),
     /* 243401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243407 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243410 */     GIR_RootConstrainSelectedInstOperands,
     /* 243411 */     // GIR_Coverage, 8540,
     /* 243411 */     GIR_EraseRootFromParent_Done,
     /* 243412 */   // Label 4660: @243412
     /* 243412 */   GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(243489), // Rule ID 8541 //
     /* 243417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243420 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243425 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243428 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243434 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243441 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243445 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243453 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243457 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 243461 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243465 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243469 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243473 */     // MIs[2] Operand 1
     /* 243473 */     // No operand predicates
     /* 243473 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243475 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 243475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_H),
     /* 243478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243484 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243487 */     GIR_RootConstrainSelectedInstOperands,
     /* 243488 */     // GIR_Coverage, 8541,
     /* 243488 */     GIR_EraseRootFromParent_Done,
     /* 243489 */   // Label 4661: @243489
     /* 243489 */   GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(243566), // Rule ID 8542 //
     /* 243494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243511 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243518 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243522 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243534 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 243538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243546 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243550 */     // MIs[2] Operand 1
     /* 243550 */     // No operand predicates
     /* 243550 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243552 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 243552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_S),
     /* 243555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243561 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243564 */     GIR_RootConstrainSelectedInstOperands,
     /* 243565 */     // GIR_Coverage, 8542,
     /* 243565 */     GIR_EraseRootFromParent_Done,
     /* 243566 */   // Label 4662: @243566
     /* 243566 */   GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(243643), // Rule ID 8543 //
     /* 243571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243588 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243599 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 243615 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243619 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243623 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243627 */     // MIs[2] Operand 1
     /* 243627 */     // No operand predicates
     /* 243627 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243629 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 243629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_S),
     /* 243632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243636 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243638 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243641 */     GIR_RootConstrainSelectedInstOperands,
     /* 243642 */     // GIR_Coverage, 8543,
     /* 243642 */     GIR_EraseRootFromParent_Done,
     /* 243643 */   // Label 4663: @243643
     /* 243643 */   GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(243720), // Rule ID 8544 //
     /* 243648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243651 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243656 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243665 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243672 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243676 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243680 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243684 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243688 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 243692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243700 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243704 */     // MIs[2] Operand 1
     /* 243704 */     // No operand predicates
     /* 243704 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243706 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FSUB_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 243706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_D),
     /* 243709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243713 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243715 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243718 */     GIR_RootConstrainSelectedInstOperands,
     /* 243719 */     // GIR_Coverage, 8544,
     /* 243719 */     GIR_EraseRootFromParent_Done,
     /* 243720 */   // Label 4664: @243720
     /* 243720 */   GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(243797), // Rule ID 8545 //
     /* 243725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 243733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 243736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 243739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 243742 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 243745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243749 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243753 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243757 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243761 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243765 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 243769 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243773 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243777 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 243781 */     // MIs[2] Operand 1
     /* 243781 */     // No operand predicates
     /* 243781 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243783 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1589:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FSUB_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 243783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmI_D),
     /* 243786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243790 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243792 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243795 */     GIR_RootConstrainSelectedInstOperands,
     /* 243796 */     // GIR_Coverage, 8545,
     /* 243796 */     GIR_EraseRootFromParent_Done,
     /* 243797 */   // Label 4665: @243797
     /* 243797 */   GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(243874), // Rule ID 8546 //
     /* 243802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 243810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243819 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243826 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243830 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243842 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 243846 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243850 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243854 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 243858 */     // MIs[2] Operand 1
     /* 243858 */     // No operand predicates
     /* 243858 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243860 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 243860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_H),
     /* 243863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 243872 */     GIR_RootConstrainSelectedInstOperands,
     /* 243873 */     // GIR_Coverage, 8546,
     /* 243873 */     GIR_EraseRootFromParent_Done,
     /* 243874 */   // Label 4666: @243874
     /* 243874 */   GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(243951), // Rule ID 8547 //
     /* 243879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243882 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 243887 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 243890 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 243893 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 243896 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 243899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243907 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 243923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 243927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 243931 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 243935 */     // MIs[2] Operand 1
     /* 243935 */     // No operand predicates
     /* 243935 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 243937 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 243937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_H),
     /* 243940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 243942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 243944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 243946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 243949 */     GIR_RootConstrainSelectedInstOperands,
     /* 243950 */     // GIR_Coverage, 8547,
     /* 243950 */     GIR_EraseRootFromParent_Done,
     /* 243951 */   // Label 4667: @243951
     /* 243951 */   GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(244028), // Rule ID 8548 //
     /* 243956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 243959 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 243964 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 243967 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 243970 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 243973 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 243976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243980 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 243984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 243988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 243992 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 243996 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 244000 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244004 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244008 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 244012 */     // MIs[2] Operand 1
     /* 244012 */     // No operand predicates
     /* 244012 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244014 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 244014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_S),
     /* 244017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244019 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244021 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244023 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244026 */     GIR_RootConstrainSelectedInstOperands,
     /* 244027 */     // GIR_Coverage, 8548,
     /* 244027 */     GIR_EraseRootFromParent_Done,
     /* 244028 */   // Label 4668: @244028
     /* 244028 */   GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(244105), // Rule ID 8549 //
     /* 244033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 244041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244050 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244057 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244061 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244073 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 244077 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244081 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244085 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 244089 */     // MIs[2] Operand 1
     /* 244089 */     // No operand predicates
     /* 244089 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244091 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 244091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_S),
     /* 244094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244100 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244103 */     GIR_RootConstrainSelectedInstOperands,
     /* 244104 */     // GIR_Coverage, 8549,
     /* 244104 */     GIR_EraseRootFromParent_Done,
     /* 244105 */   // Label 4669: @244105
     /* 244105 */   GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(244182), // Rule ID 8550 //
     /* 244110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244113 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 244118 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244121 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244124 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244127 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244134 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244138 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244142 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244146 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244150 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 244154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244162 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 244166 */     // MIs[2] Operand 1
     /* 244166 */     // No operand predicates
     /* 244166 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244168 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FMUL_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 244168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_D),
     /* 244171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244173 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244175 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244180 */     GIR_RootConstrainSelectedInstOperands,
     /* 244181 */     // GIR_Coverage, 8550,
     /* 244181 */     GIR_EraseRootFromParent_Done,
     /* 244182 */   // Label 4670: @244182
     /* 244182 */   GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(244259), // Rule ID 8551 //
     /* 244187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul),
     /* 244195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244204 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244211 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244215 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244227 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 244231 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244235 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244239 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_two),
     /* 244243 */     // MIs[2] Operand 1
     /* 244243 */     // No operand predicates
     /* 244243 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244245 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1514:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_two>>))  =>  (FMUL_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 244245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZPmI_D),
     /* 244248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244257 */     GIR_RootConstrainSelectedInstOperands,
     /* 244258 */     // GIR_Coverage, 8551,
     /* 244258 */     GIR_EraseRootFromParent_Done,
     /* 244259 */   // Label 4671: @244259
     /* 244259 */   GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(244336), // Rule ID 8552 //
     /* 244264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244281 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244292 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244304 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 244308 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244312 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244316 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 244320 */     // MIs[2] Operand 1
     /* 244320 */     // No operand predicates
     /* 244320 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244322 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 244322 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_H),
     /* 244325 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244327 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244329 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244331 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244334 */     GIR_RootConstrainSelectedInstOperands,
     /* 244335 */     // GIR_Coverage, 8552,
     /* 244335 */     GIR_EraseRootFromParent_Done,
     /* 244336 */   // Label 4672: @244336
     /* 244336 */   GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(244413), // Rule ID 8553 //
     /* 244341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244344 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244349 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244352 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244355 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244358 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244369 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244381 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 244385 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244389 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244393 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 244397 */     // MIs[2] Operand 1
     /* 244397 */     // No operand predicates
     /* 244397 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244399 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 244399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_H),
     /* 244402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244411 */     GIR_RootConstrainSelectedInstOperands,
     /* 244412 */     // GIR_Coverage, 8553,
     /* 244412 */     GIR_EraseRootFromParent_Done,
     /* 244413 */   // Label 4673: @244413
     /* 244413 */   GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(244490), // Rule ID 8554 //
     /* 244418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 244462 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244466 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244470 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 244474 */     // MIs[2] Operand 1
     /* 244474 */     // No operand predicates
     /* 244474 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244476 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 244476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_S),
     /* 244479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244481 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244483 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244485 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244488 */     GIR_RootConstrainSelectedInstOperands,
     /* 244489 */     // GIR_Coverage, 8554,
     /* 244489 */     GIR_EraseRootFromParent_Done,
     /* 244490 */   // Label 4674: @244490
     /* 244490 */   GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(244567), // Rule ID 8555 //
     /* 244495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244503 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244506 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244509 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244512 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244519 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244523 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 244539 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244543 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244547 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 244551 */     // MIs[2] Operand 1
     /* 244551 */     // No operand predicates
     /* 244551 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244553 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 244553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_S),
     /* 244556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244562 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244565 */     GIR_RootConstrainSelectedInstOperands,
     /* 244566 */     // GIR_Coverage, 8555,
     /* 244566 */     GIR_EraseRootFromParent_Done,
     /* 244567 */   // Label 4675: @244567
     /* 244567 */   GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(244644), // Rule ID 8556 //
     /* 244572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244589 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244600 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244608 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244612 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 244616 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244620 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244624 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_half),
     /* 244628 */     // MIs[2] Operand 1
     /* 244628 */     // No operand predicates
     /* 244628 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244630 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_half>>))  =>  (FSUBR_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 244630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_D),
     /* 244633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244637 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244642 */     GIR_RootConstrainSelectedInstOperands,
     /* 244643 */     // GIR_Coverage, 8556,
     /* 244643 */     GIR_EraseRootFromParent_Done,
     /* 244644 */   // Label 4676: @244644
     /* 244644 */   GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(244721), // Rule ID 8557 //
     /* 244649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 244657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 244660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 244663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 244666 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 244669 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244673 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244677 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244689 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 244693 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244697 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244701 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 244705 */     // MIs[2] Operand 1
     /* 244705 */     // No operand predicates
     /* 244705 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244707 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1591:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FSUBR_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 244707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmI_D),
     /* 244710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244716 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244719 */     GIR_RootConstrainSelectedInstOperands,
     /* 244720 */     // GIR_Coverage, 8557,
     /* 244720 */     GIR_EraseRootFromParent_Done,
     /* 244721 */   // Label 4677: @244721
     /* 244721 */   GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(244798), // Rule ID 8558 //
     /* 244726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 244734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244743 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244754 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 244770 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244774 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244778 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 244782 */     // MIs[2] Operand 1
     /* 244782 */     // No operand predicates
     /* 244782 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244784 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 244784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_H),
     /* 244787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244791 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244796 */     GIR_RootConstrainSelectedInstOperands,
     /* 244797 */     // GIR_Coverage, 8558,
     /* 244797 */     GIR_EraseRootFromParent_Done,
     /* 244798 */   // Label 4678: @244798
     /* 244798 */   GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(244875), // Rule ID 8559 //
     /* 244803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244806 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 244811 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 244814 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 244817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 244820 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 244823 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244827 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244831 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 244847 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244851 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244855 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 244859 */     // MIs[2] Operand 1
     /* 244859 */     // No operand predicates
     /* 244859 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244861 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 244861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_H),
     /* 244864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244866 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244868 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 244873 */     GIR_RootConstrainSelectedInstOperands,
     /* 244874 */     // GIR_Coverage, 8559,
     /* 244874 */     GIR_EraseRootFromParent_Done,
     /* 244875 */   // Label 4679: @244875
     /* 244875 */   GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(244952), // Rule ID 8560 //
     /* 244880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 244888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244904 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244908 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244912 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244916 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244920 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 244924 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 244928 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 244932 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 244936 */     // MIs[2] Operand 1
     /* 244936 */     // No operand predicates
     /* 244936 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 244938 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 244938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_S),
     /* 244941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 244943 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 244945 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 244947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 244950 */     GIR_RootConstrainSelectedInstOperands,
     /* 244951 */     // GIR_Coverage, 8560,
     /* 244951 */     GIR_EraseRootFromParent_Done,
     /* 244952 */   // Label 4680: @244952
     /* 244952 */   GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(245029), // Rule ID 8561 //
     /* 244957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 244960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 244965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 244968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 244971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 244974 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 244977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244981 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 244985 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 244989 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 244993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 244997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 245001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245009 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245013 */     // MIs[2] Operand 1
     /* 245013 */     // No operand predicates
     /* 245013 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245015 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 245015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_S),
     /* 245018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245020 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245022 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245024 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245027 */     GIR_RootConstrainSelectedInstOperands,
     /* 245028 */     // GIR_Coverage, 8561,
     /* 245028 */     GIR_EraseRootFromParent_Done,
     /* 245029 */   // Label 4681: @245029
     /* 245029 */   GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(245106), // Rule ID 8562 //
     /* 245034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 245042 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 245045 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245048 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 245051 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 245054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245062 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245074 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 245078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245086 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245090 */     // MIs[2] Operand 1
     /* 245090 */     // No operand predicates
     /* 245090 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245092 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMAXNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 245092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_D),
     /* 245095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245097 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245099 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245104 */     GIR_RootConstrainSelectedInstOperands,
     /* 245105 */     // GIR_Coverage, 8562,
     /* 245105 */     GIR_EraseRootFromParent_Done,
     /* 245106 */   // Label 4682: @245106
     /* 245106 */   GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(245183), // Rule ID 8563 //
     /* 245111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnm),
     /* 245119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 245122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 245128 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 245131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245139 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245143 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245147 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245151 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 245155 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245159 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245163 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245167 */     // MIs[2] Operand 1
     /* 245167 */     // No operand predicates
     /* 245167 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245169 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1468:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMAXNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 245169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNM_ZPmI_D),
     /* 245172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245178 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245181 */     GIR_RootConstrainSelectedInstOperands,
     /* 245182 */     // GIR_Coverage, 8563,
     /* 245182 */     GIR_EraseRootFromParent_Done,
     /* 245183 */   // Label 4683: @245183
     /* 245183 */   GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(245260), // Rule ID 8564 //
     /* 245188 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245191 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245196 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 245199 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245202 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 245205 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 245208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245212 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245216 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245220 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245224 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245228 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 245232 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245236 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245240 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245244 */     // MIs[2] Operand 1
     /* 245244 */     // No operand predicates
     /* 245244 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245246 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 245246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_H),
     /* 245249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245251 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245253 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245255 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245258 */     GIR_RootConstrainSelectedInstOperands,
     /* 245259 */     // GIR_Coverage, 8564,
     /* 245259 */     GIR_EraseRootFromParent_Done,
     /* 245260 */   // Label 4684: @245260
     /* 245260 */   GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(245337), // Rule ID 8565 //
     /* 245265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245268 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245273 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 245276 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245279 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 245282 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 245285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245297 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245301 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245305 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 245309 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245313 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245317 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245321 */     // MIs[2] Operand 1
     /* 245321 */     // No operand predicates
     /* 245321 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245323 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 245323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_H),
     /* 245326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245328 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245330 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245335 */     GIR_RootConstrainSelectedInstOperands,
     /* 245336 */     // GIR_Coverage, 8565,
     /* 245336 */     GIR_EraseRootFromParent_Done,
     /* 245337 */   // Label 4685: @245337
     /* 245337 */   GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(245414), // Rule ID 8566 //
     /* 245342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 245353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 245359 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 245362 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245370 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 245386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245394 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245398 */     // MIs[2] Operand 1
     /* 245398 */     // No operand predicates
     /* 245398 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245400 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 245400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_S),
     /* 245403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245407 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245412 */     GIR_RootConstrainSelectedInstOperands,
     /* 245413 */     // GIR_Coverage, 8566,
     /* 245413 */     GIR_EraseRootFromParent_Done,
     /* 245414 */   // Label 4686: @245414
     /* 245414 */   GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(245491), // Rule ID 8567 //
     /* 245419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245422 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245427 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 245430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 245436 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 245439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245451 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245455 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245459 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 245463 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245467 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245471 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245475 */     // MIs[2] Operand 1
     /* 245475 */     // No operand predicates
     /* 245475 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245477 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 245477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_S),
     /* 245480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245482 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245489 */     GIR_RootConstrainSelectedInstOperands,
     /* 245490 */     // GIR_Coverage, 8567,
     /* 245490 */     GIR_EraseRootFromParent_Done,
     /* 245491 */   // Label 4687: @245491
     /* 245491 */   GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(245568), // Rule ID 8568 //
     /* 245496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245499 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245504 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 245507 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245510 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 245513 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 245516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245524 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245528 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245532 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245536 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 245540 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245544 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245548 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245552 */     // MIs[2] Operand 1
     /* 245552 */     // No operand predicates
     /* 245552 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245554 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMINNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 245554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_D),
     /* 245557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245561 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245566 */     GIR_RootConstrainSelectedInstOperands,
     /* 245567 */     // GIR_Coverage, 8568,
     /* 245567 */     GIR_EraseRootFromParent_Done,
     /* 245568 */   // Label 4688: @245568
     /* 245568 */   GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(245645), // Rule ID 8569 //
     /* 245573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnm),
     /* 245581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 245584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 245590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 245593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245597 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245601 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 245617 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245621 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245625 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245629 */     // MIs[2] Operand 1
     /* 245629 */     // No operand predicates
     /* 245629 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245631 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1486:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMINNM_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 245631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNM_ZPmI_D),
     /* 245634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245643 */     GIR_RootConstrainSelectedInstOperands,
     /* 245644 */     // GIR_Coverage, 8569,
     /* 245644 */     GIR_EraseRootFromParent_Done,
     /* 245645 */   // Label 4689: @245645
     /* 245645 */   GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(245722), // Rule ID 8570 //
     /* 245650 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245653 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 245658 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 245661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 245667 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 245670 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245674 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245678 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245682 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245686 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245690 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 245694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245702 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245706 */     // MIs[2] Operand 1
     /* 245706 */     // No operand predicates
     /* 245706 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245708 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 245708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_H),
     /* 245711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245715 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245717 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245720 */     GIR_RootConstrainSelectedInstOperands,
     /* 245721 */     // GIR_Coverage, 8570,
     /* 245721 */     GIR_EraseRootFromParent_Done,
     /* 245722 */   // Label 4690: @245722
     /* 245722 */   GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(245799), // Rule ID 8571 //
     /* 245727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 245735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 245738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 245741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 245744 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 245747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245751 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245755 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245763 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245767 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 245771 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245775 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245779 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245783 */     // MIs[2] Operand 1
     /* 245783 */     // No operand predicates
     /* 245783 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245785 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 245785 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_H),
     /* 245788 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245790 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245792 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245794 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245797 */     GIR_RootConstrainSelectedInstOperands,
     /* 245798 */     // GIR_Coverage, 8571,
     /* 245798 */     GIR_EraseRootFromParent_Done,
     /* 245799 */   // Label 4691: @245799
     /* 245799 */   GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(245876), // Rule ID 8572 //
     /* 245804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245807 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 245812 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 245815 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245818 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 245821 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 245824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245832 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 245848 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245852 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245856 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 245860 */     // MIs[2] Operand 1
     /* 245860 */     // No operand predicates
     /* 245860 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245862 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 245862 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_S),
     /* 245865 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245867 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245871 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 245874 */     GIR_RootConstrainSelectedInstOperands,
     /* 245875 */     // GIR_Coverage, 8572,
     /* 245875 */     GIR_EraseRootFromParent_Done,
     /* 245876 */   // Label 4692: @245876
     /* 245876 */   GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(245953), // Rule ID 8573 //
     /* 245881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 245889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 245892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 245895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 245898 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 245901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245909 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245921 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 245925 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 245929 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 245933 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 245937 */     // MIs[2] Operand 1
     /* 245937 */     // No operand predicates
     /* 245937 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 245939 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 245939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_S),
     /* 245942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 245944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 245946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 245948 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 245951 */     GIR_RootConstrainSelectedInstOperands,
     /* 245952 */     // GIR_Coverage, 8573,
     /* 245952 */     GIR_EraseRootFromParent_Done,
     /* 245953 */   // Label 4693: @245953
     /* 245953 */   GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(246030), // Rule ID 8574 //
     /* 245958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 245961 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 245966 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 245969 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 245972 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 245975 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 245978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 245986 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 245990 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 245994 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 245998 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 246002 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246006 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246010 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 246014 */     // MIs[2] Operand 1
     /* 246014 */     // No operand predicates
     /* 246014 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246016 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMAX_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 246016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_D),
     /* 246019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246021 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246023 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 246028 */     GIR_RootConstrainSelectedInstOperands,
     /* 246029 */     // GIR_Coverage, 8574,
     /* 246029 */     GIR_EraseRootFromParent_Done,
     /* 246030 */   // Label 4694: @246030
     /* 246030 */   GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(246107), // Rule ID 8575 //
     /* 246035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmax),
     /* 246043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246052 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246063 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246067 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246071 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246075 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 246079 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246083 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246087 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 246091 */     // MIs[2] Operand 1
     /* 246091 */     // No operand predicates
     /* 246091 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246093 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1462:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMAX_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 246093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAX_ZPmI_D),
     /* 246096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246098 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246102 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 246105 */     GIR_RootConstrainSelectedInstOperands,
     /* 246106 */     // GIR_Coverage, 8575,
     /* 246106 */     GIR_EraseRootFromParent_Done,
     /* 246107 */   // Label 4695: @246107
     /* 246107 */   GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(246184), // Rule ID 8576 //
     /* 246112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246129 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 246132 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246136 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246140 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 246156 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246160 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246164 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 246168 */     // MIs[2] Operand 1
     /* 246168 */     // No operand predicates
     /* 246168 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246170 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 0:{ *:[i32] })
     /* 246170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_H),
     /* 246173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246177 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246179 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 246182 */     GIR_RootConstrainSelectedInstOperands,
     /* 246183 */     // GIR_Coverage, 8576,
     /* 246183 */     GIR_EraseRootFromParent_Done,
     /* 246184 */   // Label 4696: @246184
     /* 246184 */   GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(246261), // Rule ID 8577 //
     /* 246189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246192 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246197 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246200 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 246203 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246206 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 246209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246213 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246217 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 246233 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246237 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246241 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 246245 */     // MIs[2] Operand 1
     /* 246245 */     // No operand predicates
     /* 246245 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246247 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$Pg, ZPR:{ *:[nxv8f16] }:$Zs1, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Pg, ?:{ *:[nxv8f16] }:$Zs1, 1:{ *:[i32] })
     /* 246247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_H),
     /* 246250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246252 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246254 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246256 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 246259 */     GIR_RootConstrainSelectedInstOperands,
     /* 246260 */     // GIR_Coverage, 8577,
     /* 246260 */     GIR_EraseRootFromParent_Done,
     /* 246261 */   // Label 4697: @246261
     /* 246261 */   GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(246338), // Rule ID 8578 //
     /* 246266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246269 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246274 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246277 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246280 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246283 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 246286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246290 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246298 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246302 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246306 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 246310 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246314 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246318 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 246322 */     // MIs[2] Operand 1
     /* 246322 */     // No operand predicates
     /* 246322 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246324 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 0:{ *:[i32] })
     /* 246324 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_S),
     /* 246327 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246329 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246331 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246333 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 246336 */     GIR_RootConstrainSelectedInstOperands,
     /* 246337 */     // GIR_Coverage, 8578,
     /* 246337 */     GIR_EraseRootFromParent_Done,
     /* 246338 */   // Label 4698: @246338
     /* 246338 */   GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(246415), // Rule ID 8579 //
     /* 246343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 246357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246360 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 246363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246371 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246375 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246379 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246383 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 246387 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246391 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246395 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 246399 */     // MIs[2] Operand 1
     /* 246399 */     // No operand predicates
     /* 246399 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246401 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR:{ *:[nxv4f32] }:$Zs1, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Pg, ?:{ *:[nxv4f32] }:$Zs1, 1:{ *:[i32] })
     /* 246401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_S),
     /* 246404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246408 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 246413 */     GIR_RootConstrainSelectedInstOperands,
     /* 246414 */     // GIR_Coverage, 8579,
     /* 246414 */     GIR_EraseRootFromParent_Done,
     /* 246415 */   // Label 4699: @246415
     /* 246415 */   GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(246492), // Rule ID 8580 //
     /* 246420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246431 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246434 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246437 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 246464 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246468 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246472 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 246476 */     // MIs[2] Operand 1
     /* 246476 */     // No operand predicates
     /* 246476 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246478 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>))  =>  (FMIN_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 0:{ *:[i32] })
     /* 246478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_D),
     /* 246481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246483 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246485 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 246490 */     GIR_RootConstrainSelectedInstOperands,
     /* 246491 */     // GIR_Coverage, 8580,
     /* 246491 */     GIR_EraseRootFromParent_Done,
     /* 246492 */   // Label 4700: @246492
     /* 246492 */   GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(246569), // Rule ID 8581 //
     /* 246497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmin),
     /* 246505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 246511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246514 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 246517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246521 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 246525 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 246533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 246537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 246541 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 246545 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 246549 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_one),
     /* 246553 */     // MIs[2] Operand 1
     /* 246553 */     // No operand predicates
     /* 246553 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 246555 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1480:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR:{ *:[nxv2f64] }:$Zs1, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_one>>))  =>  (FMIN_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Pg, ?:{ *:[nxv2f64] }:$Zs1, 1:{ *:[i32] })
     /* 246555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMIN_ZPmI_D),
     /* 246558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 246562 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zs1
     /* 246564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 246567 */     GIR_RootConstrainSelectedInstOperands,
     /* 246568 */     // GIR_Coverage, 8581,
     /* 246568 */     GIR_EraseRootFromParent_Done,
     /* 246569 */   // Label 4701: @246569
     /* 246569 */   GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(246624), // Rule ID 2844 //
     /* 246574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 246577 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 246582 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246585 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 246588 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246599 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246603 */     // MIs[0] imm
     /* 246603 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246606 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 246611 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1592:{ *:[iPTR] }, ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_H:{ *:[nxv8f16] } ZPR16:{ *:[nxv8f16] }:$Zn, ZPR16:{ *:[nxv8f16] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 246611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_H),
     /* 246614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246616 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 246618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 246620 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 246622 */     GIR_RootConstrainSelectedInstOperands,
     /* 246623 */     // GIR_Coverage, 2844,
     /* 246623 */     GIR_EraseRootFromParent_Done,
     /* 246624 */   // Label 4702: @246624
     /* 246624 */   GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(246679), // Rule ID 2845 //
     /* 246629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 246632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 246637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 246643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 246646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246654 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246658 */     // MIs[0] imm
     /* 246658 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246661 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 246666 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1592:{ *:[iPTR] }, ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_S:{ *:[nxv4f32] } ZPR32:{ *:[nxv4f32] }:$Zn, ZPR32:{ *:[nxv4f32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 246666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_S),
     /* 246669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246671 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 246673 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 246675 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 246677 */     GIR_RootConstrainSelectedInstOperands,
     /* 246678 */     // GIR_Coverage, 2845,
     /* 246678 */     GIR_EraseRootFromParent_Done,
     /* 246679 */   // Label 4703: @246679
     /* 246679 */   GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(246734), // Rule ID 2846 //
     /* 246684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 246687 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ftmad_x),
     /* 246692 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 246698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 246701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246709 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246713 */     // MIs[0] imm
     /* 246713 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246716 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 246721 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1592:{ *:[iPTR] }, ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)  =>  (FTMAD_ZZI_D:{ *:[nxv2f64] } ZPR64:{ *:[nxv2f64] }:$Zn, ZPR64:{ *:[nxv2f64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$imm)
     /* 246721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FTMAD_ZZI_D),
     /* 246724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 246726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 246728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 246730 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 246732 */     GIR_RootConstrainSelectedInstOperands,
     /* 246733 */     // GIR_Coverage, 2846,
     /* 246733 */     GIR_EraseRootFromParent_Done,
     /* 246734 */   // Label 4704: @246734
     /* 246734 */   GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(246789), // Rule ID 3634 //
     /* 246739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 246742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 246747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 246753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 246756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246764 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246768 */     // MIs[0] Idx
     /* 246768 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246771 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_1),
     /* 246776 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1680:{ *:[iPTR] }, ZPRAny:{ *:[nxv8i16] }:$Zd, PPR16:{ *:[nxv8i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx)  =>  (PMOV_ZIP_H:{ *:[nxv8i16] } ZPRAny:{ *:[nxv8i16] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_1>>:$Idx, PPR16:{ *:[nxv8i1] }:$Pn)
     /* 246776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_H),
     /* 246779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 246781 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 246783 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 246785 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 246787 */     GIR_RootConstrainSelectedInstOperands,
     /* 246788 */     // GIR_Coverage, 3634,
     /* 246788 */     GIR_EraseRootFromParent_Done,
     /* 246789 */   // Label 4705: @246789
     /* 246789 */   GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(246844), // Rule ID 3635 //
     /* 246794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 246797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 246802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 246805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 246808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 246811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246819 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246823 */     // MIs[0] Idx
     /* 246823 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246826 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_3),
     /* 246831 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1680:{ *:[iPTR] }, ZPRAny:{ *:[nxv4i32] }:$Zd, PPR32:{ *:[nxv4i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx)  =>  (PMOV_ZIP_S:{ *:[nxv4i32] } ZPRAny:{ *:[nxv4i32] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_3>>:$Idx, PPR32:{ *:[nxv4i1] }:$Pn)
     /* 246831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_S),
     /* 246834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 246836 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 246838 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 246840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 246842 */     GIR_RootConstrainSelectedInstOperands,
     /* 246843 */     // GIR_Coverage, 3635,
     /* 246843 */     GIR_EraseRootFromParent_Done,
     /* 246844 */   // Label 4706: @246844
     /* 246844 */   GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(246899), // Rule ID 3636 //
     /* 246849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 246852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_pmov_to_vector_lane_merging),
     /* 246857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 246860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 246863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 246866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 246878 */     // MIs[0] Idx
     /* 246878 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246881 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_1_7),
     /* 246886 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1680:{ *:[iPTR] }, ZPRAny:{ *:[nxv2i64] }:$Zd, PPR64:{ *:[nxv2i1] }:$Pn, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx)  =>  (PMOV_ZIP_D:{ *:[nxv2i64] } ZPRAny:{ *:[nxv2i64] }:$Zd, (timm:{ *:[i32] })<<P:Predicate_timm32_1_7>>:$Idx, PPR64:{ *:[nxv2i1] }:$Pn)
     /* 246886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMOV_ZIP_D),
     /* 246889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 246891 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zd
     /* 246893 */     GIR_RootToRootCopy, /*OpIdx*/4, // Idx
     /* 246895 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pn
     /* 246897 */     GIR_RootConstrainSelectedInstOperands,
     /* 246898 */     // GIR_Coverage, 3636,
     /* 246898 */     GIR_EraseRootFromParent_Done,
     /* 246899 */   // Label 4707: @246899
     /* 246899 */   GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(246954), // Rule ID 3937 //
     /* 246904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 246907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_xar),
     /* 246912 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 246915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 246918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 246921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 246925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 246929 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 246933 */     // MIs[0] imm
     /* 246933 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246936 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm0_63),
     /* 246941 */     // (intrinsic_wo_chain:{ *:[v2i64] } 567:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm)  =>  (XAR:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_timm0_63>>:$imm)
     /* 246941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR),
     /* 246944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 246946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 246948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 246950 */     GIR_RootToRootCopy, /*OpIdx*/4, // imm
     /* 246952 */     GIR_RootConstrainSelectedInstOperands,
     /* 246953 */     // GIR_Coverage, 3937,
     /* 246953 */     GIR_EraseRootFromParent_Done,
     /* 246954 */   // Label 4708: @246954
     /* 246954 */   GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(247001), // Rule ID 2907 //
     /* 246959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 246962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 246967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 246970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 246973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 246976 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 246980 */     // MIs[0] idx
     /* 246980 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 246983 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 246988 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1515:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 246988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 246991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 246993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 246995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 246997 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 246999 */     GIR_RootConstrainSelectedInstOperands,
     /* 247000 */     // GIR_Coverage, 2907,
     /* 247000 */     GIR_EraseRootFromParent_Done,
     /* 247001 */   // Label 4709: @247001
     /* 247001 */   GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(247048), // Rule ID 2911 //
     /* 247006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247009 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 247014 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247017 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247020 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247023 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247027 */     // MIs[0] idx
     /* 247027 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247030 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 247035 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1515:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 247035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 247038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247040 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247044 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 247046 */     GIR_RootConstrainSelectedInstOperands,
     /* 247047 */     // GIR_Coverage, 2911,
     /* 247047 */     GIR_EraseRootFromParent_Done,
     /* 247048 */   // Label 4710: @247048
     /* 247048 */   GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(247095), // Rule ID 2915 //
     /* 247053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 247056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmul_lane),
     /* 247061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 247067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247074 */     // MIs[0] idx
     /* 247074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247077 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 247082 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1515:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 247082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 247085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247091 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 247093 */     GIR_RootConstrainSelectedInstOperands,
     /* 247094 */     // GIR_Coverage, 2915,
     /* 247094 */     GIR_EraseRootFromParent_Done,
     /* 247095 */   // Label 4711: @247095
     /* 247095 */   GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(247142), // Rule ID 3070 //
     /* 247100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247103 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 247108 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247111 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247114 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247117 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247121 */     // MIs[0] Op3
     /* 247121 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247124 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 247129 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1660:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (MUL_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 247129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_H),
     /* 247132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247136 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247138 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247140 */     GIR_RootConstrainSelectedInstOperands,
     /* 247141 */     // GIR_Coverage, 3070,
     /* 247141 */     GIR_EraseRootFromParent_Done,
     /* 247142 */   // Label 4712: @247142
     /* 247142 */   GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(247189), // Rule ID 3071 //
     /* 247147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247150 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 247155 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247158 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247161 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247168 */     // MIs[0] Op3
     /* 247168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247171 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 247176 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1660:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (MUL_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 247176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_S),
     /* 247179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247183 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247185 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247187 */     GIR_RootConstrainSelectedInstOperands,
     /* 247188 */     // GIR_Coverage, 3071,
     /* 247188 */     GIR_EraseRootFromParent_Done,
     /* 247189 */   // Label 4713: @247189
     /* 247189 */   GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(247236), // Rule ID 3072 //
     /* 247194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mul_lane),
     /* 247202 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 247208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247215 */     // MIs[0] Op3
     /* 247215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247218 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 247223 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1660:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (MUL_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 247223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MUL_ZZZI_D),
     /* 247226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247232 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247234 */     GIR_RootConstrainSelectedInstOperands,
     /* 247235 */     // GIR_Coverage, 3072,
     /* 247235 */     GIR_EraseRootFromParent_Done,
     /* 247236 */   // Label 4714: @247236
     /* 247236 */   GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(247283), // Rule ID 3073 //
     /* 247241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
     /* 247249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247262 */     // MIs[0] Op3
     /* 247262 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247265 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 247270 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1808:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 247270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_S),
     /* 247273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247279 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247281 */     GIR_RootConstrainSelectedInstOperands,
     /* 247282 */     // GIR_Coverage, 3073,
     /* 247282 */     GIR_EraseRootFromParent_Done,
     /* 247283 */   // Label 4715: @247283
     /* 247283 */   GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(247330), // Rule ID 3074 //
     /* 247288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullb_lane),
     /* 247296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247309 */     // MIs[0] Op3
     /* 247309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247312 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 247317 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1808:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 247317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLB_ZZZI_D),
     /* 247320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247326 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247328 */     GIR_RootConstrainSelectedInstOperands,
     /* 247329 */     // GIR_Coverage, 3074,
     /* 247329 */     GIR_EraseRootFromParent_Done,
     /* 247330 */   // Label 4716: @247330
     /* 247330 */   GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(247377), // Rule ID 3122 //
     /* 247335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 247343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247346 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 247349 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247356 */     // MIs[0] Op3
     /* 247356 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247359 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 247364 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1922:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 247364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_B),
     /* 247367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 247369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247371 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247373 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247375 */     GIR_RootConstrainSelectedInstOperands,
     /* 247376 */     // GIR_Coverage, 3122,
     /* 247376 */     GIR_EraseRootFromParent_Done,
     /* 247377 */   // Label 4717: @247377
     /* 247377 */   GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(247424), // Rule ID 3124 //
     /* 247382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 247390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247403 */     // MIs[0] Op3
     /* 247403 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247406 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 247411 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1922:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 247411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_H),
     /* 247414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 247416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247420 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247422 */     GIR_RootConstrainSelectedInstOperands,
     /* 247423 */     // GIR_Coverage, 3124,
     /* 247423 */     GIR_EraseRootFromParent_Done,
     /* 247424 */   // Label 4718: @247424
     /* 247424 */   GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(247471), // Rule ID 3126 //
     /* 247429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 247437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247450 */     // MIs[0] Op3
     /* 247450 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247453 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 247458 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1922:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 247458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_S),
     /* 247461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 247463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247465 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247467 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247469 */     GIR_RootConstrainSelectedInstOperands,
     /* 247470 */     // GIR_Coverage, 3126,
     /* 247470 */     GIR_EraseRootFromParent_Done,
     /* 247471 */   // Label 4719: @247471
     /* 247471 */   GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(247518), // Rule ID 3128 //
     /* 247476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ssra),
     /* 247484 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 247490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247497 */     // MIs[0] Op3
     /* 247497 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247500 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 247505 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1922:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (SSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 247505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSRA_ZZI_D),
     /* 247508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 247510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247514 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247516 */     GIR_RootConstrainSelectedInstOperands,
     /* 247517 */     // GIR_Coverage, 3128,
     /* 247517 */     GIR_EraseRootFromParent_Done,
     /* 247518 */   // Label 4720: @247518
     /* 247518 */   GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(247565), // Rule ID 3150 //
     /* 247523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 247531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 247537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247544 */     // MIs[0] Op3
     /* 247544 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247547 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 247552 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1901:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SQSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 247552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_B),
     /* 247555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247561 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247563 */     GIR_RootConstrainSelectedInstOperands,
     /* 247564 */     // GIR_Coverage, 3150,
     /* 247564 */     GIR_EraseRootFromParent_Done,
     /* 247565 */   // Label 4721: @247565
     /* 247565 */   GIM_Try, /*On fail goto*//*Label 4722*/ GIMT_Encode4(247612), // Rule ID 3151 //
     /* 247570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247573 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 247578 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247581 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247584 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247587 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247591 */     // MIs[0] Op3
     /* 247591 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247594 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 247599 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1901:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SQSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 247599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_H),
     /* 247602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247606 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247608 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247610 */     GIR_RootConstrainSelectedInstOperands,
     /* 247611 */     // GIR_Coverage, 3151,
     /* 247611 */     GIR_EraseRootFromParent_Done,
     /* 247612 */   // Label 4722: @247612
     /* 247612 */   GIM_Try, /*On fail goto*//*Label 4723*/ GIMT_Encode4(247659), // Rule ID 3152 //
     /* 247617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrunt),
     /* 247625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247638 */     // MIs[0] Op3
     /* 247638 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247641 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 247646 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1901:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SQSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 247646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNT_ZZI_S),
     /* 247649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247651 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247653 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247655 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247657 */     GIR_RootConstrainSelectedInstOperands,
     /* 247658 */     // GIR_Coverage, 3152,
     /* 247658 */     GIR_EraseRootFromParent_Done,
     /* 247659 */   // Label 4723: @247659
     /* 247659 */   GIM_Try, /*On fail goto*//*Label 4724*/ GIMT_Encode4(247706), // Rule ID 3225 //
     /* 247664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 247672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 247678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247685 */     // MIs[0] Op3
     /* 247685 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247688 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 247693 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2207:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (XAR_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 247693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_B),
     /* 247696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247698 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247702 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247704 */     GIR_RootConstrainSelectedInstOperands,
     /* 247705 */     // GIR_Coverage, 3225,
     /* 247705 */     GIR_EraseRootFromParent_Done,
     /* 247706 */   // Label 4724: @247706
     /* 247706 */   GIM_Try, /*On fail goto*//*Label 4725*/ GIMT_Encode4(247753), // Rule ID 3226 //
     /* 247711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247714 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 247719 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 247728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247732 */     // MIs[0] Op3
     /* 247732 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247735 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 247740 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2207:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (XAR_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 247740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_H),
     /* 247743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247747 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247749 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247751 */     GIR_RootConstrainSelectedInstOperands,
     /* 247752 */     // GIR_Coverage, 3226,
     /* 247752 */     GIR_EraseRootFromParent_Done,
     /* 247753 */   // Label 4725: @247753
     /* 247753 */   GIM_Try, /*On fail goto*//*Label 4726*/ GIMT_Encode4(247800), // Rule ID 3227 //
     /* 247758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247761 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 247766 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 247769 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 247772 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 247775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247779 */     // MIs[0] Op3
     /* 247779 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247782 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 247787 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2207:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (XAR_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 247787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_S),
     /* 247790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247796 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247798 */     GIR_RootConstrainSelectedInstOperands,
     /* 247799 */     // GIR_Coverage, 3227,
     /* 247799 */     GIR_EraseRootFromParent_Done,
     /* 247800 */   // Label 4726: @247800
     /* 247800 */   GIM_Try, /*On fail goto*//*Label 4727*/ GIMT_Encode4(247847), // Rule ID 3228 //
     /* 247805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 247808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_xar),
     /* 247813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 247816 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 247819 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 247822 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247826 */     // MIs[0] Op3
     /* 247826 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247829 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 247834 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2207:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (XAR_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 247834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XAR_ZZZI_D),
     /* 247837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247845 */     GIR_RootConstrainSelectedInstOperands,
     /* 247846 */     // GIR_Coverage, 3228,
     /* 247846 */     GIR_EraseRootFromParent_Done,
     /* 247847 */   // Label 4727: @247847
     /* 247847 */   GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(247894), // Rule ID 3619 //
     /* 247852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 247855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_extq),
     /* 247860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 247866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247873 */     // MIs[0] Op3
     /* 247873 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247876 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_15),
     /* 247881 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1389:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)  =>  (EXTQ_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_15>>:$Op3)
     /* 247881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTQ_ZZI),
     /* 247884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 247886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247890 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247892 */     GIR_RootConstrainSelectedInstOperands,
     /* 247893 */     // GIR_Coverage, 3619,
     /* 247893 */     GIR_EraseRootFromParent_Done,
     /* 247894 */   // Label 4728: @247894
     /* 247894 */   GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(247941), // Rule ID 3668 //
     /* 247899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 247902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 247907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 247910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 247913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247916 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247920 */     // MIs[0] Op3
     /* 247920 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247923 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 247928 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1647:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI2_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 247928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_B),
     /* 247931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247937 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247939 */     GIR_RootConstrainSelectedInstOperands,
     /* 247940 */     // GIR_Coverage, 3668,
     /* 247940 */     GIR_EraseRootFromParent_Done,
     /* 247941 */   // Label 4729: @247941
     /* 247941 */   GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(247988), // Rule ID 3669 //
     /* 247946 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 247949 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 247954 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 247957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 247960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 247963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 247967 */     // MIs[0] Op3
     /* 247967 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 247970 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 247975 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1647:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)  =>  (LUTI2_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)
     /* 247975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_H),
     /* 247978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 247980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 247982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 247984 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 247986 */     GIR_RootConstrainSelectedInstOperands,
     /* 247987 */     // GIR_Coverage, 3669,
     /* 247987 */     GIR_EraseRootFromParent_Done,
     /* 247988 */   // Label 4730: @247988
     /* 247988 */   GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(248035), // Rule ID 3670 //
     /* 247993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 247996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti2_lane),
     /* 248001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248014 */     // MIs[0] Op3
     /* 248014 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248017 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 248022 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1647:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)  =>  (LUTI2_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$Op3)
     /* 248022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI2_ZZZI_H),
     /* 248025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248031 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248033 */     GIR_RootConstrainSelectedInstOperands,
     /* 248034 */     // GIR_Coverage, 3670,
     /* 248034 */     GIR_EraseRootFromParent_Done,
     /* 248035 */   // Label 4731: @248035
     /* 248035 */   GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(248082), // Rule ID 3671 //
     /* 248040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 248043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 248048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 248051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 248054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248057 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248061 */     // MIs[0] Op3
     /* 248061 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248064 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 248069 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1648:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Op3)  =>  (LUTI4_ZZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$Op3)
     /* 248069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_B),
     /* 248072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248074 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248076 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248078 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248080 */     GIR_RootConstrainSelectedInstOperands,
     /* 248081 */     // GIR_Coverage, 3671,
     /* 248081 */     GIR_EraseRootFromParent_Done,
     /* 248082 */   // Label 4732: @248082
     /* 248082 */   GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(248129), // Rule ID 3672 //
     /* 248087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 248090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 248095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248108 */     // MIs[0] Op3
     /* 248108 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248111 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 248116 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1648:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI4_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 248116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_H),
     /* 248119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248125 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248127 */     GIR_RootConstrainSelectedInstOperands,
     /* 248128 */     // GIR_Coverage, 3672,
     /* 248128 */     GIR_EraseRootFromParent_Done,
     /* 248129 */   // Label 4733: @248129
     /* 248129 */   GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(248176), // Rule ID 3673 //
     /* 248134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT_HasNonStreamingSVE2_or_SME2),
     /* 248137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_luti4_lane),
     /* 248142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248148 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248155 */     // MIs[0] Op3
     /* 248155 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248158 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 248163 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1648:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)  =>  (LUTI4_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$Op3)
     /* 248163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUTI4_ZZZI_H),
     /* 248166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248172 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248174 */     GIR_RootConstrainSelectedInstOperands,
     /* 248175 */     // GIR_Coverage, 3673,
     /* 248175 */     GIR_EraseRootFromParent_Done,
     /* 248176 */   // Label 4734: @248176
     /* 248176 */   GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(248223), // Rule ID 12117 //
     /* 248181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248184 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 248189 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248195 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248202 */     // MIs[0] Op3
     /* 248202 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248205 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248210 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1849:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_H),
     /* 248213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248217 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248219 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248221 */     GIR_RootConstrainSelectedInstOperands,
     /* 248222 */     // GIR_Coverage, 12117,
     /* 248222 */     GIR_EraseRootFromParent_Done,
     /* 248223 */   // Label 4735: @248223
     /* 248223 */   GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(248270), // Rule ID 12118 //
     /* 248228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248231 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 248236 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248249 */     // MIs[0] Op3
     /* 248249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248252 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248257 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1849:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_S),
     /* 248260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248266 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248268 */     GIR_RootConstrainSelectedInstOperands,
     /* 248269 */     // GIR_Coverage, 12118,
     /* 248269 */     GIR_EraseRootFromParent_Done,
     /* 248270 */   // Label 4736: @248270
     /* 248270 */   GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(248317), // Rule ID 12119 //
     /* 248275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmulh_lane),
     /* 248283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 248292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248296 */     // MIs[0] Op3
     /* 248296 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248299 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 248304 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1849:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (SQDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 248304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULH_ZZZI_D),
     /* 248307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248313 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248315 */     GIR_RootConstrainSelectedInstOperands,
     /* 248316 */     // GIR_Coverage, 12119,
     /* 248316 */     GIR_EraseRootFromParent_Done,
     /* 248317 */   // Label 4737: @248317
     /* 248317 */   GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(248364), // Rule ID 12120 //
     /* 248322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 248330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248343 */     // MIs[0] Op3
     /* 248343 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248346 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248351 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1880:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_H),
     /* 248354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248356 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248360 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248362 */     GIR_RootConstrainSelectedInstOperands,
     /* 248363 */     // GIR_Coverage, 12120,
     /* 248363 */     GIR_EraseRootFromParent_Done,
     /* 248364 */   // Label 4738: @248364
     /* 248364 */   GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(248411), // Rule ID 12121 //
     /* 248369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 248377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248390 */     // MIs[0] Op3
     /* 248390 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248393 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248398 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1880:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_S),
     /* 248401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248407 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248409 */     GIR_RootConstrainSelectedInstOperands,
     /* 248410 */     // GIR_Coverage, 12121,
     /* 248410 */     GIR_EraseRootFromParent_Done,
     /* 248411 */   // Label 4739: @248411
     /* 248411 */   GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(248458), // Rule ID 12122 //
     /* 248416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248419 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmulh_lane),
     /* 248424 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248427 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 248430 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 248433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248437 */     // MIs[0] Op3
     /* 248437 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248440 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 248445 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1880:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)  =>  (SQRDMULH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op3)
     /* 248445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMULH_ZZZI_D),
     /* 248448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248454 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248456 */     GIR_RootConstrainSelectedInstOperands,
     /* 248457 */     // GIR_Coverage, 12122,
     /* 248457 */     GIR_EraseRootFromParent_Done,
     /* 248458 */   // Label 4740: @248458
     /* 248458 */   GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(248505), // Rule ID 12145 //
     /* 248463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
     /* 248471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248480 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248484 */     // MIs[0] Op3
     /* 248484 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248487 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248492 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1810:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_S),
     /* 248495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248501 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248503 */     GIR_RootConstrainSelectedInstOperands,
     /* 248504 */     // GIR_Coverage, 12145,
     /* 248504 */     GIR_EraseRootFromParent_Done,
     /* 248505 */   // Label 4741: @248505
     /* 248505 */   GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(248552), // Rule ID 12146 //
     /* 248510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smullt_lane),
     /* 248518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248531 */     // MIs[0] Op3
     /* 248531 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248534 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248539 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1810:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLT_ZZZI_D),
     /* 248542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248548 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248550 */     GIR_RootConstrainSelectedInstOperands,
     /* 248551 */     // GIR_Coverage, 12146,
     /* 248551 */     GIR_EraseRootFromParent_Done,
     /* 248552 */   // Label 4742: @248552
     /* 248552 */   GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(248599), // Rule ID 12147 //
     /* 248557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
     /* 248565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248571 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248578 */     // MIs[0] Op3
     /* 248578 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248581 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248586 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2050:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (UMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_S),
     /* 248589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248595 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248597 */     GIR_RootConstrainSelectedInstOperands,
     /* 248598 */     // GIR_Coverage, 12147,
     /* 248598 */     GIR_EraseRootFromParent_Done,
     /* 248599 */   // Label 4743: @248599
     /* 248599 */   GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(248646), // Rule ID 12148 //
     /* 248604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248607 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullb_lane),
     /* 248612 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248615 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248618 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248625 */     // MIs[0] Op3
     /* 248625 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248628 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248633 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2050:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (UMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLB_ZZZI_D),
     /* 248636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248638 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248642 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248644 */     GIR_RootConstrainSelectedInstOperands,
     /* 248645 */     // GIR_Coverage, 12148,
     /* 248645 */     GIR_EraseRootFromParent_Done,
     /* 248646 */   // Label 4744: @248646
     /* 248646 */   GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(248693), // Rule ID 12149 //
     /* 248651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248654 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
     /* 248659 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248668 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248672 */     // MIs[0] Op3
     /* 248672 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248675 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248680 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2052:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (UMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_S),
     /* 248683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248687 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248689 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248691 */     GIR_RootConstrainSelectedInstOperands,
     /* 248692 */     // GIR_Coverage, 12149,
     /* 248692 */     GIR_EraseRootFromParent_Done,
     /* 248693 */   // Label 4745: @248693
     /* 248693 */   GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(248740), // Rule ID 12150 //
     /* 248698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umullt_lane),
     /* 248706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248719 */     // MIs[0] Op3
     /* 248719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248722 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248727 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2052:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (UMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLT_ZZZI_D),
     /* 248730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248736 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248738 */     GIR_RootConstrainSelectedInstOperands,
     /* 248739 */     // GIR_Coverage, 12150,
     /* 248739 */     GIR_EraseRootFromParent_Done,
     /* 248740 */   // Label 4746: @248740
     /* 248740 */   GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(248787), // Rule ID 12151 //
     /* 248745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
     /* 248753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248766 */     // MIs[0] Op3
     /* 248766 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248769 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248774 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1855:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_S),
     /* 248777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248779 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248781 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248783 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248785 */     GIR_RootConstrainSelectedInstOperands,
     /* 248786 */     // GIR_Coverage, 12151,
     /* 248786 */     GIR_EraseRootFromParent_Done,
     /* 248787 */   // Label 4747: @248787
     /* 248787 */   GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(248834), // Rule ID 12152 //
     /* 248792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullb_lane),
     /* 248800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248813 */     // MIs[0] Op3
     /* 248813 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248816 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248821 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1855:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLB_ZZZI_D),
     /* 248824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248830 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248832 */     GIR_RootConstrainSelectedInstOperands,
     /* 248833 */     // GIR_Coverage, 12152,
     /* 248833 */     GIR_EraseRootFromParent_Done,
     /* 248834 */   // Label 4748: @248834
     /* 248834 */   GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(248881), // Rule ID 12153 //
     /* 248839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
     /* 248847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 248850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 248853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248860 */     // MIs[0] Op3
     /* 248860 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248863 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 248868 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1857:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)  =>  (SQDMULLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op3)
     /* 248868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_S),
     /* 248871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248877 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248879 */     GIR_RootConstrainSelectedInstOperands,
     /* 248880 */     // GIR_Coverage, 12153,
     /* 248880 */     GIR_EraseRootFromParent_Done,
     /* 248881 */   // Label 4749: @248881
     /* 248881 */   GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(248928), // Rule ID 12154 //
     /* 248886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248889 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmullt_lane),
     /* 248894 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 248897 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 248900 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 248903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248907 */     // MIs[0] Op3
     /* 248907 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248910 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 248915 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1857:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)  =>  (SQDMULLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op3)
     /* 248915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMULLT_ZZZI_D),
     /* 248918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 248920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248924 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248926 */     GIR_RootConstrainSelectedInstOperands,
     /* 248927 */     // GIR_Coverage, 12154,
     /* 248927 */     GIR_EraseRootFromParent_Done,
     /* 248928 */   // Label 4750: @248928
     /* 248928 */   GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(248975), // Rule ID 12416 //
     /* 248933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 248941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 248944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 248947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 248950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 248954 */     // MIs[0] Op3
     /* 248954 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 248957 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 248962 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1918:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SRSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 248962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_B),
     /* 248965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 248967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 248969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 248971 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 248973 */     GIR_RootConstrainSelectedInstOperands,
     /* 248974 */     // GIR_Coverage, 12416,
     /* 248974 */     GIR_EraseRootFromParent_Done,
     /* 248975 */   // Label 4751: @248975
     /* 248975 */   GIM_Try, /*On fail goto*//*Label 4752*/ GIMT_Encode4(249022), // Rule ID 12417 //
     /* 248980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 248983 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 248988 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 248991 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 248994 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 248997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249001 */     // MIs[0] Op3
     /* 249001 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249004 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 249009 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1918:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SRSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 249009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_H),
     /* 249012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249016 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249018 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249020 */     GIR_RootConstrainSelectedInstOperands,
     /* 249021 */     // GIR_Coverage, 12417,
     /* 249021 */     GIR_EraseRootFromParent_Done,
     /* 249022 */   // Label 4752: @249022
     /* 249022 */   GIM_Try, /*On fail goto*//*Label 4753*/ GIMT_Encode4(249069), // Rule ID 12418 //
     /* 249027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 249035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 249041 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249048 */     // MIs[0] Op3
     /* 249048 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249051 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 249056 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1918:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SRSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 249056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_S),
     /* 249059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249063 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249065 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249067 */     GIR_RootConstrainSelectedInstOperands,
     /* 249068 */     // GIR_Coverage, 12418,
     /* 249068 */     GIR_EraseRootFromParent_Done,
     /* 249069 */   // Label 4753: @249069
     /* 249069 */   GIM_Try, /*On fail goto*//*Label 4754*/ GIMT_Encode4(249116), // Rule ID 12419 //
     /* 249074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshr),
     /* 249082 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249085 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 249088 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249095 */     // MIs[0] Op3
     /* 249095 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249098 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 249103 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1918:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (SRSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 249103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHR_ZPmI_D),
     /* 249106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249110 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249112 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249114 */     GIR_RootConstrainSelectedInstOperands,
     /* 249115 */     // GIR_Coverage, 12419,
     /* 249115 */     GIR_EraseRootFromParent_Done,
     /* 249116 */   // Label 4754: @249116
     /* 249116 */   GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(249163), // Rule ID 12420 //
     /* 249121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 249129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 249135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249142 */     // MIs[0] Op3
     /* 249142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249145 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 249150 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2113:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (URSHR_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 249150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_B),
     /* 249153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249157 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249159 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249161 */     GIR_RootConstrainSelectedInstOperands,
     /* 249162 */     // GIR_Coverage, 12420,
     /* 249162 */     GIR_EraseRootFromParent_Done,
     /* 249163 */   // Label 4755: @249163
     /* 249163 */   GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(249210), // Rule ID 12422 //
     /* 249168 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249171 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 249176 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249179 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 249182 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249189 */     // MIs[0] Op3
     /* 249189 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249192 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 249197 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2113:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (URSHR_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 249197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_H),
     /* 249200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249202 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249204 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249206 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249208 */     GIR_RootConstrainSelectedInstOperands,
     /* 249209 */     // GIR_Coverage, 12422,
     /* 249209 */     GIR_EraseRootFromParent_Done,
     /* 249210 */   // Label 4756: @249210
     /* 249210 */   GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(249257), // Rule ID 12424 //
     /* 249215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 249223 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249226 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 249229 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249236 */     // MIs[0] Op3
     /* 249236 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249239 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 249244 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2113:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (URSHR_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 249244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_S),
     /* 249247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249249 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249253 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249255 */     GIR_RootConstrainSelectedInstOperands,
     /* 249256 */     // GIR_Coverage, 12424,
     /* 249256 */     GIR_EraseRootFromParent_Done,
     /* 249257 */   // Label 4757: @249257
     /* 249257 */   GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(249304), // Rule ID 12426 //
     /* 249262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshr),
     /* 249270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 249276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249283 */     // MIs[0] Op3
     /* 249283 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249286 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 249291 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2113:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (URSHR_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 249291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHR_ZPmI_D),
     /* 249294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249300 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249302 */     GIR_RootConstrainSelectedInstOperands,
     /* 249303 */     // GIR_Coverage, 12426,
     /* 249303 */     GIR_EraseRootFromParent_Done,
     /* 249304 */   // Label 4758: @249304
     /* 249304 */   GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(249351), // Rule ID 12428 //
     /* 249309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 249317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 249323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249330 */     // MIs[0] Op3
     /* 249330 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249333 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 249338 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1897:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op3)  =>  (SQSHLU_ZPmI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op3)
     /* 249338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_B),
     /* 249341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249347 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249349 */     GIR_RootConstrainSelectedInstOperands,
     /* 249350 */     // GIR_Coverage, 12428,
     /* 249350 */     GIR_EraseRootFromParent_Done,
     /* 249351 */   // Label 4759: @249351
     /* 249351 */   GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(249398), // Rule ID 12429 //
     /* 249356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249359 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 249364 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249367 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 249370 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249377 */     // MIs[0] Op3
     /* 249377 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249380 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 249385 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1897:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op3)  =>  (SQSHLU_ZPmI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op3)
     /* 249385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_H),
     /* 249388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249392 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249394 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249396 */     GIR_RootConstrainSelectedInstOperands,
     /* 249397 */     // GIR_Coverage, 12429,
     /* 249397 */     GIR_EraseRootFromParent_Done,
     /* 249398 */   // Label 4760: @249398
     /* 249398 */   GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(249445), // Rule ID 12430 //
     /* 249403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 249411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 249417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249424 */     // MIs[0] Op3
     /* 249424 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249427 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 249432 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1897:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op3)  =>  (SQSHLU_ZPmI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op3)
     /* 249432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_S),
     /* 249435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249441 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249443 */     GIR_RootConstrainSelectedInstOperands,
     /* 249444 */     // GIR_Coverage, 12430,
     /* 249444 */     GIR_EraseRootFromParent_Done,
     /* 249445 */   // Label 4761: @249445
     /* 249445 */   GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(249492), // Rule ID 12431 //
     /* 249450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshlu),
     /* 249458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 249464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249471 */     // MIs[0] Op3
     /* 249471 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249474 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 249479 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1897:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$Op3)  =>  (SQSHLU_ZPmI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$Op3)
     /* 249479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHLU_ZPmI_D),
     /* 249482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 249484 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249488 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249490 */     GIR_RootConstrainSelectedInstOperands,
     /* 249491 */     // GIR_Coverage, 12431,
     /* 249491 */     GIR_EraseRootFromParent_Done,
     /* 249492 */   // Label 4762: @249492
     /* 249492 */   GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(249539), // Rule ID 12520 //
     /* 249497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 249505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 249511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249518 */     // MIs[0] Op3
     /* 249518 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249521 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 249526 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2122:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (USRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 249526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_B),
     /* 249529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249531 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249533 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249535 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249537 */     GIR_RootConstrainSelectedInstOperands,
     /* 249538 */     // GIR_Coverage, 12520,
     /* 249538 */     GIR_EraseRootFromParent_Done,
     /* 249539 */   // Label 4763: @249539
     /* 249539 */   GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(249586), // Rule ID 12522 //
     /* 249544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249547 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 249552 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249555 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249558 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249565 */     // MIs[0] Op3
     /* 249565 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249568 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 249573 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2122:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (USRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 249573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_H),
     /* 249576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249580 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249582 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249584 */     GIR_RootConstrainSelectedInstOperands,
     /* 249585 */     // GIR_Coverage, 12522,
     /* 249585 */     GIR_EraseRootFromParent_Done,
     /* 249586 */   // Label 4764: @249586
     /* 249586 */   GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(249633), // Rule ID 12524 //
     /* 249591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 249599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249612 */     // MIs[0] Op3
     /* 249612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249615 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 249620 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2122:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (USRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 249620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_S),
     /* 249623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249629 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249631 */     GIR_RootConstrainSelectedInstOperands,
     /* 249632 */     // GIR_Coverage, 12524,
     /* 249632 */     GIR_EraseRootFromParent_Done,
     /* 249633 */   // Label 4765: @249633
     /* 249633 */   GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(249680), // Rule ID 12526 //
     /* 249638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usra),
     /* 249646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249652 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249659 */     // MIs[0] Op3
     /* 249659 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249662 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 249667 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2122:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (USRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 249667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USRA_ZZI_D),
     /* 249670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249672 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249676 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249678 */     GIR_RootConstrainSelectedInstOperands,
     /* 249679 */     // GIR_Coverage, 12526,
     /* 249679 */     GIR_EraseRootFromParent_Done,
     /* 249680 */   // Label 4766: @249680
     /* 249680 */   GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(249727), // Rule ID 12528 //
     /* 249685 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249688 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 249693 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249696 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 249699 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249706 */     // MIs[0] Op3
     /* 249706 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249709 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 249714 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1919:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SRSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 249714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_B),
     /* 249717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249723 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249725 */     GIR_RootConstrainSelectedInstOperands,
     /* 249726 */     // GIR_Coverage, 12528,
     /* 249726 */     GIR_EraseRootFromParent_Done,
     /* 249727 */   // Label 4767: @249727
     /* 249727 */   GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(249774), // Rule ID 12529 //
     /* 249732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 249740 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249753 */     // MIs[0] Op3
     /* 249753 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249756 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 249761 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1919:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SRSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 249761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_H),
     /* 249764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249768 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249770 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249772 */     GIR_RootConstrainSelectedInstOperands,
     /* 249773 */     // GIR_Coverage, 12529,
     /* 249773 */     GIR_EraseRootFromParent_Done,
     /* 249774 */   // Label 4768: @249774
     /* 249774 */   GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(249821), // Rule ID 12530 //
     /* 249779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 249787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249800 */     // MIs[0] Op3
     /* 249800 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249803 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 249808 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1919:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SRSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 249808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_S),
     /* 249811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249813 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249815 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249817 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249819 */     GIR_RootConstrainSelectedInstOperands,
     /* 249820 */     // GIR_Coverage, 12530,
     /* 249820 */     GIR_EraseRootFromParent_Done,
     /* 249821 */   // Label 4769: @249821
     /* 249821 */   GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(249868), // Rule ID 12531 //
     /* 249826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249829 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srsra),
     /* 249834 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 249837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 249840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 249843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249847 */     // MIs[0] Op3
     /* 249847 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249850 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 249855 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1919:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (SRSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 249855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSRA_ZZI_D),
     /* 249858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249860 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249862 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249864 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249866 */     GIR_RootConstrainSelectedInstOperands,
     /* 249867 */     // GIR_Coverage, 12531,
     /* 249867 */     GIR_EraseRootFromParent_Done,
     /* 249868 */   // Label 4770: @249868
     /* 249868 */   GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(249915), // Rule ID 12536 //
     /* 249873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 249881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 249884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 249887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 249890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249894 */     // MIs[0] Op3
     /* 249894 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249897 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 249902 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2115:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (URSRA_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 249902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_B),
     /* 249905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249907 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249909 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249911 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249913 */     GIR_RootConstrainSelectedInstOperands,
     /* 249914 */     // GIR_Coverage, 12536,
     /* 249914 */     GIR_EraseRootFromParent_Done,
     /* 249915 */   // Label 4771: @249915
     /* 249915 */   GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(249962), // Rule ID 12537 //
     /* 249920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249923 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 249928 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 249931 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 249934 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 249937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249941 */     // MIs[0] Op3
     /* 249941 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249944 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 249949 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2115:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (URSRA_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 249949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_H),
     /* 249952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 249954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 249956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 249958 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 249960 */     GIR_RootConstrainSelectedInstOperands,
     /* 249961 */     // GIR_Coverage, 12537,
     /* 249961 */     GIR_EraseRootFromParent_Done,
     /* 249962 */   // Label 4772: @249962
     /* 249962 */   GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(250009), // Rule ID 12538 //
     /* 249967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 249970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 249975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 249978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 249981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 249984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 249988 */     // MIs[0] Op3
     /* 249988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 249991 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 249996 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2115:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (URSRA_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 249996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_S),
     /* 249999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250003 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250005 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250007 */     GIR_RootConstrainSelectedInstOperands,
     /* 250008 */     // GIR_Coverage, 12538,
     /* 250008 */     GIR_EraseRootFromParent_Done,
     /* 250009 */   // Label 4773: @250009
     /* 250009 */   GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(250056), // Rule ID 12539 //
     /* 250014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursra),
     /* 250022 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 250025 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 250028 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250035 */     // MIs[0] Op3
     /* 250035 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250038 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 250043 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2115:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (URSRA_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 250043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSRA_ZZI_D),
     /* 250046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 250048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250050 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250052 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250054 */     GIR_RootConstrainSelectedInstOperands,
     /* 250055 */     // GIR_Coverage, 12539,
     /* 250055 */     GIR_EraseRootFromParent_Done,
     /* 250056 */   // Label 4774: @250056
     /* 250056 */   GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(250103), // Rule ID 12599 //
     /* 250061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 250069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250082 */     // MIs[0] Op3
     /* 250082 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250085 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250090 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1894:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SQRSHRUNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_B),
     /* 250093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250095 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250099 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250101 */     GIR_RootConstrainSelectedInstOperands,
     /* 250102 */     // GIR_Coverage, 12599,
     /* 250102 */     GIR_EraseRootFromParent_Done,
     /* 250103 */   // Label 4775: @250103
     /* 250103 */   GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(250150), // Rule ID 12600 //
     /* 250108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250111 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 250116 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250119 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250129 */     // MIs[0] Op3
     /* 250129 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250132 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250137 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1894:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SQRSHRUNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_H),
     /* 250140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250146 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250148 */     GIR_RootConstrainSelectedInstOperands,
     /* 250149 */     // GIR_Coverage, 12600,
     /* 250149 */     GIR_EraseRootFromParent_Done,
     /* 250150 */   // Label 4776: @250150
     /* 250150 */   GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(250197), // Rule ID 12601 //
     /* 250155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrunt),
     /* 250163 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250166 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250169 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250176 */     // MIs[0] Op3
     /* 250176 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250179 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250184 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1894:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SQRSHRUNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNT_ZZI_S),
     /* 250187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250189 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250191 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250193 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250195 */     GIR_RootConstrainSelectedInstOperands,
     /* 250196 */     // GIR_Coverage, 12601,
     /* 250196 */     GIR_EraseRootFromParent_Done,
     /* 250197 */   // Label 4777: @250197
     /* 250197 */   GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(250244), // Rule ID 12602 //
     /* 250202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 250210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250223 */     // MIs[0] Op3
     /* 250223 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250226 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250231 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1771:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_B),
     /* 250234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250240 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250242 */     GIR_RootConstrainSelectedInstOperands,
     /* 250243 */     // GIR_Coverage, 12602,
     /* 250243 */     GIR_EraseRootFromParent_Done,
     /* 250244 */   // Label 4778: @250244
     /* 250244 */   GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(250291), // Rule ID 12603 //
     /* 250249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 250257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250270 */     // MIs[0] Op3
     /* 250270 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250273 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250278 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1771:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_H),
     /* 250281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250283 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250285 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250287 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250289 */     GIR_RootConstrainSelectedInstOperands,
     /* 250290 */     // GIR_Coverage, 12603,
     /* 250290 */     GIR_EraseRootFromParent_Done,
     /* 250291 */   // Label 4779: @250291
     /* 250291 */   GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(250338), // Rule ID 12604 //
     /* 250296 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shrnt),
     /* 250304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250317 */     // MIs[0] Op3
     /* 250317 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250320 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250325 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1771:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNT_ZZI_S),
     /* 250328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250334 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250336 */     GIR_RootConstrainSelectedInstOperands,
     /* 250337 */     // GIR_Coverage, 12604,
     /* 250337 */     GIR_EraseRootFromParent_Done,
     /* 250338 */   // Label 4780: @250338
     /* 250338 */   GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(250385), // Rule ID 12605 //
     /* 250343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 250351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250364 */     // MIs[0] Op3
     /* 250364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250367 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250372 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1729:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (RSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_B),
     /* 250375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250381 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250383 */     GIR_RootConstrainSelectedInstOperands,
     /* 250384 */     // GIR_Coverage, 12605,
     /* 250384 */     GIR_EraseRootFromParent_Done,
     /* 250385 */   // Label 4781: @250385
     /* 250385 */   GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(250432), // Rule ID 12606 //
     /* 250390 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250393 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 250398 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250411 */     // MIs[0] Op3
     /* 250411 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250414 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250419 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1729:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (RSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_H),
     /* 250422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250426 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250428 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250430 */     GIR_RootConstrainSelectedInstOperands,
     /* 250431 */     // GIR_Coverage, 12606,
     /* 250431 */     GIR_EraseRootFromParent_Done,
     /* 250432 */   // Label 4782: @250432
     /* 250432 */   GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(250479), // Rule ID 12607 //
     /* 250437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rshrnt),
     /* 250445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250458 */     // MIs[0] Op3
     /* 250458 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250461 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250466 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1729:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (RSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSHRNT_ZZI_S),
     /* 250469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250473 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250475 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250477 */     GIR_RootConstrainSelectedInstOperands,
     /* 250478 */     // GIR_Coverage, 12607,
     /* 250478 */     GIR_EraseRootFromParent_Done,
     /* 250479 */   // Label 4783: @250479
     /* 250479 */   GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(250526), // Rule ID 12608 //
     /* 250484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 250492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250505 */     // MIs[0] Op3
     /* 250505 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250508 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250513 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1899:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_B),
     /* 250516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250522 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250524 */     GIR_RootConstrainSelectedInstOperands,
     /* 250525 */     // GIR_Coverage, 12608,
     /* 250525 */     GIR_EraseRootFromParent_Done,
     /* 250526 */   // Label 4784: @250526
     /* 250526 */   GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(250573), // Rule ID 12609 //
     /* 250531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 250539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250552 */     // MIs[0] Op3
     /* 250552 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250555 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250560 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1899:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_H),
     /* 250563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250567 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250569 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250571 */     GIR_RootConstrainSelectedInstOperands,
     /* 250572 */     // GIR_Coverage, 12609,
     /* 250572 */     GIR_EraseRootFromParent_Done,
     /* 250573 */   // Label 4785: @250573
     /* 250573 */   GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(250620), // Rule ID 12610 //
     /* 250578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250581 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshrnt),
     /* 250586 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250589 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250592 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250599 */     // MIs[0] Op3
     /* 250599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250602 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250607 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1899:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNT_ZZI_S),
     /* 250610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250612 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250616 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250618 */     GIR_RootConstrainSelectedInstOperands,
     /* 250619 */     // GIR_Coverage, 12610,
     /* 250619 */     GIR_EraseRootFromParent_Done,
     /* 250620 */   // Label 4786: @250620
     /* 250620 */   GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(250667), // Rule ID 12611 //
     /* 250625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 250633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250639 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250646 */     // MIs[0] Op3
     /* 250646 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250649 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250654 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1888:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_B),
     /* 250657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250659 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250661 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250663 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250665 */     GIR_RootConstrainSelectedInstOperands,
     /* 250666 */     // GIR_Coverage, 12611,
     /* 250666 */     GIR_EraseRootFromParent_Done,
     /* 250667 */   // Label 4787: @250667
     /* 250667 */   GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(250714), // Rule ID 12612 //
     /* 250672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 250680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250693 */     // MIs[0] Op3
     /* 250693 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250696 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250701 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1888:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_H),
     /* 250704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250706 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250708 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250710 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250712 */     GIR_RootConstrainSelectedInstOperands,
     /* 250713 */     // GIR_Coverage, 12612,
     /* 250713 */     GIR_EraseRootFromParent_Done,
     /* 250714 */   // Label 4788: @250714
     /* 250714 */   GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(250761), // Rule ID 12613 //
     /* 250719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshrnt),
     /* 250727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250740 */     // MIs[0] Op3
     /* 250740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250743 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250748 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1888:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNT_ZZI_S),
     /* 250751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250757 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250759 */     GIR_RootConstrainSelectedInstOperands,
     /* 250760 */     // GIR_Coverage, 12613,
     /* 250760 */     GIR_EraseRootFromParent_Done,
     /* 250761 */   // Label 4789: @250761
     /* 250761 */   GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(250808), // Rule ID 12614 //
     /* 250766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 250774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250787 */     // MIs[0] Op3
     /* 250787 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250790 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250795 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2098:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (UQSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_B),
     /* 250798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250802 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250804 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250806 */     GIR_RootConstrainSelectedInstOperands,
     /* 250807 */     // GIR_Coverage, 12614,
     /* 250807 */     GIR_EraseRootFromParent_Done,
     /* 250808 */   // Label 4790: @250808
     /* 250808 */   GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(250855), // Rule ID 12615 //
     /* 250813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 250821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250834 */     // MIs[0] Op3
     /* 250834 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250837 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250842 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2098:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (UQSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_H),
     /* 250845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250847 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250851 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250853 */     GIR_RootConstrainSelectedInstOperands,
     /* 250854 */     // GIR_Coverage, 12615,
     /* 250854 */     GIR_EraseRootFromParent_Done,
     /* 250855 */   // Label 4791: @250855
     /* 250855 */   GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(250902), // Rule ID 12616 //
     /* 250860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshrnt),
     /* 250868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 250871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 250874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 250877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250881 */     // MIs[0] Op3
     /* 250881 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250884 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 250889 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2098:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (UQSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 250889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNT_ZZI_S),
     /* 250892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250898 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250900 */     GIR_RootConstrainSelectedInstOperands,
     /* 250901 */     // GIR_Coverage, 12616,
     /* 250901 */     GIR_EraseRootFromParent_Done,
     /* 250902 */   // Label 4792: @250902
     /* 250902 */   GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(250949), // Rule ID 12617 //
     /* 250907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 250915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 250918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 250921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 250924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250928 */     // MIs[0] Op3
     /* 250928 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250931 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 250936 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2094:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (UQRSHRNT_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 250936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_B),
     /* 250939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250941 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250945 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250947 */     GIR_RootConstrainSelectedInstOperands,
     /* 250948 */     // GIR_Coverage, 12617,
     /* 250948 */     GIR_EraseRootFromParent_Done,
     /* 250949 */   // Label 4793: @250949
     /* 250949 */   GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(250996), // Rule ID 12618 //
     /* 250954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 250957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 250962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 250965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 250968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 250971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 250975 */     // MIs[0] Op3
     /* 250975 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 250978 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 250983 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2094:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (UQRSHRNT_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 250983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_H),
     /* 250986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 250988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 250990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 250992 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 250994 */     GIR_RootConstrainSelectedInstOperands,
     /* 250995 */     // GIR_Coverage, 12618,
     /* 250995 */     GIR_EraseRootFromParent_Done,
     /* 250996 */   // Label 4794: @250996
     /* 250996 */   GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(251043), // Rule ID 12619 //
     /* 251001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshrnt),
     /* 251009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 251018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251022 */     // MIs[0] Op3
     /* 251022 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 251025 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 251030 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2094:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (UQRSHRNT_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 251030 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNT_ZZI_S),
     /* 251033 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251035 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 251037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 251039 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 251041 */     GIR_RootConstrainSelectedInstOperands,
     /* 251042 */     // GIR_Coverage, 12619,
     /* 251042 */     GIR_EraseRootFromParent_Done,
     /* 251043 */   // Label 4795: @251043
     /* 251043 */   GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(251110), // Rule ID 2643 //
     /* 251048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251051 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
     /* 251056 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251059 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251062 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 251065 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251068 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251072 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251076 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251080 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251082 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2105:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (URECPE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 251082 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251085 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251089 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251094 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S_UNDEF),
     /* 251099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251101 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251106 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251108 */     GIR_RootConstrainSelectedInstOperands,
     /* 251109 */     // GIR_Coverage, 2643,
     /* 251109 */     GIR_EraseRootFromParent_Done,
     /* 251110 */   // Label 4796: @251110
     /* 251110 */   GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(251177), // Rule ID 8379 //
     /* 251115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 251123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 251129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 251132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251147 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251149 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1341:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CLS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 251149 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251152 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251156 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251161 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B_UNDEF),
     /* 251166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251168 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251175 */     GIR_RootConstrainSelectedInstOperands,
     /* 251176 */     // GIR_Coverage, 8379,
     /* 251176 */     GIR_EraseRootFromParent_Done,
     /* 251177 */   // Label 4797: @251177
     /* 251177 */   GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(251244), // Rule ID 8381 //
     /* 251182 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251185 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 251190 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 251196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 251199 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251202 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251214 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251216 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1341:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CLS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 251216 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251219 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251223 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251228 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H_UNDEF),
     /* 251233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251235 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251240 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251242 */     GIR_RootConstrainSelectedInstOperands,
     /* 251243 */     // GIR_Coverage, 8381,
     /* 251243 */     GIR_EraseRootFromParent_Done,
     /* 251244 */   // Label 4798: @251244
     /* 251244 */   GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(251311), // Rule ID 8383 //
     /* 251249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 251257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 251266 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251273 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251277 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251281 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251283 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1341:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CLS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 251283 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251286 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251290 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251295 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S_UNDEF),
     /* 251300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251302 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251307 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251309 */     GIR_RootConstrainSelectedInstOperands,
     /* 251310 */     // GIR_Coverage, 8383,
     /* 251310 */     GIR_EraseRootFromParent_Done,
     /* 251311 */   // Label 4799: @251311
     /* 251311 */   GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(251378), // Rule ID 8385 //
     /* 251316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251319 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 251324 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251327 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 251330 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 251333 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251336 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251348 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251350 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1341:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CLS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 251350 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251353 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251357 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251362 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D_UNDEF),
     /* 251367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251369 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251372 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251374 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251376 */     GIR_RootConstrainSelectedInstOperands,
     /* 251377 */     // GIR_Coverage, 8385,
     /* 251377 */     GIR_EraseRootFromParent_Done,
     /* 251378 */   // Label 4800: @251378
     /* 251378 */   GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(251445), // Rule ID 8415 //
     /* 251383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 251391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 251397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 251400 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251407 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251411 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251415 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251417 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1361:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CNOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 251417 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251420 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251424 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251429 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B_UNDEF),
     /* 251434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251436 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251441 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251443 */     GIR_RootConstrainSelectedInstOperands,
     /* 251444 */     // GIR_Coverage, 8415,
     /* 251444 */     GIR_EraseRootFromParent_Done,
     /* 251445 */   // Label 4801: @251445
     /* 251445 */   GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(251512), // Rule ID 8417 //
     /* 251450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 251458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 251464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 251467 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251474 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251478 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251482 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251484 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1361:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CNOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 251484 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251487 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251491 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251496 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H_UNDEF),
     /* 251501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251503 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251508 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251510 */     GIR_RootConstrainSelectedInstOperands,
     /* 251511 */     // GIR_Coverage, 8417,
     /* 251511 */     GIR_EraseRootFromParent_Done,
     /* 251512 */   // Label 4802: @251512
     /* 251512 */   GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(251579), // Rule ID 8419 //
     /* 251517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 251525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251528 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251531 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 251534 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251549 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251551 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1361:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CNOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 251551 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251554 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251558 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251563 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S_UNDEF),
     /* 251568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251570 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251575 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251577 */     GIR_RootConstrainSelectedInstOperands,
     /* 251578 */     // GIR_Coverage, 8419,
     /* 251578 */     GIR_EraseRootFromParent_Done,
     /* 251579 */   // Label 4803: @251579
     /* 251579 */   GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(251646), // Rule ID 8421 //
     /* 251584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251587 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 251592 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251595 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 251598 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 251601 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251608 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251612 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251616 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251618 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1361:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CNOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 251618 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251621 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251625 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251630 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D_UNDEF),
     /* 251635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251637 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251642 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251644 */     GIR_RootConstrainSelectedInstOperands,
     /* 251645 */     // GIR_Coverage, 8421,
     /* 251645 */     GIR_EraseRootFromParent_Done,
     /* 251646 */   // Label 4804: @251646
     /* 251646 */   GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(251713), // Rule ID 8427 //
     /* 251651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251654 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 251659 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 251665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 251668 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 251671 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251683 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251685 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1667:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (NOT_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 251685 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251688 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251692 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251697 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B_UNDEF),
     /* 251702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251704 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251707 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251709 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251711 */     GIR_RootConstrainSelectedInstOperands,
     /* 251712 */     // GIR_Coverage, 8427,
     /* 251712 */     GIR_EraseRootFromParent_Done,
     /* 251713 */   // Label 4805: @251713
     /* 251713 */   GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(251780), // Rule ID 8429 //
     /* 251718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251721 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 251726 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 251729 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 251732 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 251735 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 251738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251746 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251752 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1667:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (NOT_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 251752 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251755 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251759 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251764 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H_UNDEF),
     /* 251769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251771 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251774 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251776 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251778 */     GIR_RootConstrainSelectedInstOperands,
     /* 251779 */     // GIR_Coverage, 8429,
     /* 251779 */     GIR_EraseRootFromParent_Done,
     /* 251780 */   // Label 4806: @251780
     /* 251780 */   GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(251847), // Rule ID 8431 //
     /* 251785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251788 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 251793 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251796 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251799 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 251802 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251809 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251813 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251817 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251819 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1667:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (NOT_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 251819 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251822 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251826 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251831 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S_UNDEF),
     /* 251836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251838 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251845 */     GIR_RootConstrainSelectedInstOperands,
     /* 251846 */     // GIR_Coverage, 8431,
     /* 251846 */     GIR_EraseRootFromParent_Done,
     /* 251847 */   // Label 4807: @251847
     /* 251847 */   GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(251914), // Rule ID 8433 //
     /* 251852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 251855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 251860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 251863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 251866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 251869 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 251872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251876 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251880 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251884 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251886 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1667:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (NOT_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 251886 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251889 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251893 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251898 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D_UNDEF),
     /* 251903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251905 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251908 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251910 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251912 */     GIR_RootConstrainSelectedInstOperands,
     /* 251913 */     // GIR_Coverage, 8433,
     /* 251913 */     GIR_EraseRootFromParent_Done,
     /* 251914 */   // Label 4808: @251914
     /* 251914 */   GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(251981), // Rule ID 12294 //
     /* 251919 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251922 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
     /* 251927 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 251930 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 251933 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 251936 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 251939 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 251943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 251947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 251951 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 251953 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2114:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (URSQRTE_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 251953 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 251956 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 251960 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 251965 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 251967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S_UNDEF),
     /* 251970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 251972 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 251975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 251977 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 251979 */     GIR_RootConstrainSelectedInstOperands,
     /* 251980 */     // GIR_Coverage, 12294,
     /* 251980 */     GIR_EraseRootFromParent_Done,
     /* 251981 */   // Label 4809: @251981
     /* 251981 */   GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(252048), // Rule ID 12296 //
     /* 251986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 251989 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 251994 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 251997 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 252000 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 252003 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252018 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252020 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1812:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQABS_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 252020 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252023 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252027 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252032 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B_UNDEF),
     /* 252037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252039 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252044 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252046 */     GIR_RootConstrainSelectedInstOperands,
     /* 252047 */     // GIR_Coverage, 12296,
     /* 252047 */     GIR_EraseRootFromParent_Done,
     /* 252048 */   // Label 4810: @252048
     /* 252048 */   GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(252115), // Rule ID 12298 //
     /* 252053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 252061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 252067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 252070 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252081 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252087 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1812:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQABS_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 252087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252099 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H_UNDEF),
     /* 252104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252106 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252109 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252111 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252113 */     GIR_RootConstrainSelectedInstOperands,
     /* 252114 */     // GIR_Coverage, 12298,
     /* 252114 */     GIR_EraseRootFromParent_Done,
     /* 252115 */   // Label 4811: @252115
     /* 252115 */   GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(252182), // Rule ID 12300 //
     /* 252120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 252128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 252134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 252137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252152 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252154 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1812:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQABS_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 252154 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252157 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252161 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252166 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S_UNDEF),
     /* 252171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252173 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252178 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252180 */     GIR_RootConstrainSelectedInstOperands,
     /* 252181 */     // GIR_Coverage, 12300,
     /* 252181 */     GIR_EraseRootFromParent_Done,
     /* 252182 */   // Label 4812: @252182
     /* 252182 */   GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(252249), // Rule ID 12302 //
     /* 252187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 252195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 252201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 252204 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252215 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252219 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252221 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1812:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQABS_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 252221 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252224 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252228 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252233 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D_UNDEF),
     /* 252238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252243 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252245 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252247 */     GIR_RootConstrainSelectedInstOperands,
     /* 252248 */     // GIR_Coverage, 12302,
     /* 252248 */     GIR_EraseRootFromParent_Done,
     /* 252249 */   // Label 4813: @252249
     /* 252249 */   GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(252316), // Rule ID 12308 //
     /* 252254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 252262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 252265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 252268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 252271 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 252274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252282 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252286 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252288 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1872:{ *:[iPTR] }, (undef:{ *:[nxv16i8] }), nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQNEG_ZPmZ_B_UNDEF:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 252288 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252291 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252295 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252300 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B_UNDEF),
     /* 252305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252307 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252312 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252314 */     GIR_RootConstrainSelectedInstOperands,
     /* 252315 */     // GIR_Coverage, 12308,
     /* 252315 */     GIR_EraseRootFromParent_Done,
     /* 252316 */   // Label 4814: @252316
     /* 252316 */   GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(252383), // Rule ID 12310 //
     /* 252321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 252329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 252332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 252335 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 252338 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 252341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252345 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252349 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252353 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252355 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1872:{ *:[iPTR] }, (undef:{ *:[nxv8i16] }), nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQNEG_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 252355 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252358 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252362 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252367 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H_UNDEF),
     /* 252372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252374 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252377 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252379 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252381 */     GIR_RootConstrainSelectedInstOperands,
     /* 252382 */     // GIR_Coverage, 12310,
     /* 252382 */     GIR_EraseRootFromParent_Done,
     /* 252383 */   // Label 4815: @252383
     /* 252383 */   GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(252450), // Rule ID 12312 //
     /* 252388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 252396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 252399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 252402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 252405 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 252408 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252412 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252416 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252420 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252422 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1872:{ *:[iPTR] }, (undef:{ *:[nxv4i32] }), nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQNEG_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 252422 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252425 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252429 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252434 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S_UNDEF),
     /* 252439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252441 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252444 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252446 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252448 */     GIR_RootConstrainSelectedInstOperands,
     /* 252449 */     // GIR_Coverage, 12312,
     /* 252449 */     GIR_EraseRootFromParent_Done,
     /* 252450 */   // Label 4816: @252450
     /* 252450 */   GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(252517), // Rule ID 12314 //
     /* 252455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 252458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 252463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 252466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 252469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 252472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 252475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 252479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 252483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 252487 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 252489 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1872:{ *:[iPTR] }, (undef:{ *:[nxv2i64] }), nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQNEG_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 252489 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 252492 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 252496 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 252501 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 252503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D_UNDEF),
     /* 252506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 252508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 252511 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 252513 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 252515 */     GIR_RootConstrainSelectedInstOperands,
     /* 252516 */     // GIR_Coverage, 12314,
     /* 252516 */     GIR_EraseRootFromParent_Done,
     /* 252517 */   // Label 4817: @252517
     /* 252517 */   GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(252576), // Rule ID 3994 //
     /* 252522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPAuth),
     /* 252525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::ptrauth_sign),
     /* 252530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 252533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 252536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64,
     /* 252539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 252543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 252547 */     // MIs[0] Key
     /* 252547 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 252550 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 252554 */     // (intrinsic_wo_chain:{ *:[i64] } 308:{ *:[iPTR] }, GPR64:{ *:[i64] }:$Val, (timm:{ *:[i32] }):$Key, GPR64noip:{ *:[i64] }:$AddrDisc)  =>  (PAC:{ *:[i64] }:{ *:[i64] } GPR64:{ *:[i64] }:$Val, ?:{ *:[i32] }:$Key, 0:{ *:[i64] }, GPR64noip:{ *:[i64] }:$AddrDisc)
     /* 252554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PAC),
     /* 252557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[SignedVal]
     /* 252559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Val
     /* 252561 */     GIR_RootToRootCopy, /*OpIdx*/3, // Key
     /* 252563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 252566 */     GIR_RootToRootCopy, /*OpIdx*/4, // AddrDisc
     /* 252568 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 252571 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 252574 */     GIR_RootConstrainSelectedInstOperands,
     /* 252575 */     // GIR_Coverage, 3994,
     /* 252575 */     GIR_EraseRootFromParent_Done,
     /* 252576 */   // Label 4818: @252576
     /* 252576 */   GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(252630), // Rule ID 30 //
     /* 252581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 252584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smmla),
     /* 252589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 252592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 252595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 252598 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 252601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252605 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252609 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252613 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252617 */     // (intrinsic_wo_chain:{ *:[v4i32] } 701:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 252617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA),
     /* 252620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252624 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252626 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252628 */     GIR_RootConstrainSelectedInstOperands,
     /* 252629 */     // GIR_Coverage, 30,
     /* 252629 */     GIR_EraseRootFromParent_Done,
     /* 252630 */   // Label 4819: @252630
     /* 252630 */   GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(252684), // Rule ID 31 //
     /* 252635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 252638 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_ummla),
     /* 252643 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 252646 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 252649 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 252652 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 252655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252659 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252663 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252667 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252671 */     // (intrinsic_wo_chain:{ *:[v4i32] } 762:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 252671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA),
     /* 252674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252678 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252680 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252682 */     GIR_RootConstrainSelectedInstOperands,
     /* 252683 */     // GIR_Coverage, 31,
     /* 252683 */     GIR_EraseRootFromParent_Done,
     /* 252684 */   // Label 4820: @252684
     /* 252684 */   GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(252738), // Rule ID 32 //
     /* 252689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 252692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_usmmla),
     /* 252697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 252700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 252703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 252706 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 252709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252721 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252725 */     // (intrinsic_wo_chain:{ *:[v4i32] } 778:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (USMMLA:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 252725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA),
     /* 252728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252730 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252732 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252734 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252736 */     GIR_RootConstrainSelectedInstOperands,
     /* 252737 */     // GIR_Coverage, 32,
     /* 252737 */     GIR_EraseRootFromParent_Done,
     /* 252738 */   // Label 4821: @252738
     /* 252738 */   GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(252792), // Rule ID 39 //
     /* 252743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 252746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 252751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 252754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 252757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 252760 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 252763 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252767 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252771 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252775 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252779 */     // (intrinsic_wo_chain:{ *:[v2f32] } 630:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLALv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 252779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv4f16),
     /* 252782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252788 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252790 */     GIR_RootConstrainSelectedInstOperands,
     /* 252791 */     // GIR_Coverage, 39,
     /* 252791 */     GIR_EraseRootFromParent_Done,
     /* 252792 */   // Label 4822: @252792
     /* 252792 */   GIM_Try, /*On fail goto*//*Label 4823*/ GIMT_Encode4(252846), // Rule ID 40 //
     /* 252797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 252800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal),
     /* 252805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 252808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 252811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 252814 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 252817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252821 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252825 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252829 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252833 */     // (intrinsic_wo_chain:{ *:[v4f32] } 630:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLALv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 252833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALv8f16),
     /* 252836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252842 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252844 */     GIR_RootConstrainSelectedInstOperands,
     /* 252845 */     // GIR_Coverage, 40,
     /* 252845 */     GIR_EraseRootFromParent_Done,
     /* 252846 */   // Label 4823: @252846
     /* 252846 */   GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(252900), // Rule ID 41 //
     /* 252851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 252854 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 252859 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 252862 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 252865 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 252868 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 252871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252879 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252883 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252887 */     // (intrinsic_wo_chain:{ *:[v2f32] } 632:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLSLv4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 252887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv4f16),
     /* 252890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252896 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252898 */     GIR_RootConstrainSelectedInstOperands,
     /* 252899 */     // GIR_Coverage, 41,
     /* 252899 */     GIR_EraseRootFromParent_Done,
     /* 252900 */   // Label 4824: @252900
     /* 252900 */   GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(252954), // Rule ID 42 //
     /* 252905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 252908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl),
     /* 252913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 252916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 252919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 252922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 252925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252937 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 252941 */     // (intrinsic_wo_chain:{ *:[v4f32] } 632:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLSLv8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 252941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLv8f16),
     /* 252944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 252946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 252948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 252950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 252952 */     GIR_RootConstrainSelectedInstOperands,
     /* 252953 */     // GIR_Coverage, 42,
     /* 252953 */     GIR_EraseRootFromParent_Done,
     /* 252954 */   // Label 4825: @252954
     /* 252954 */   GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(253008), // Rule ID 43 //
     /* 252959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 252962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 252967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 252970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 252973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 252976 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 252979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252983 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252987 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252991 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 252995 */     // (intrinsic_wo_chain:{ *:[v2f32] } 631:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLAL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 252995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v4f16),
     /* 252998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253000 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253002 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253004 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253006 */     GIR_RootConstrainSelectedInstOperands,
     /* 253007 */     // GIR_Coverage, 43,
     /* 253007 */     GIR_EraseRootFromParent_Done,
     /* 253008 */   // Label 4826: @253008
     /* 253008 */   GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(253062), // Rule ID 44 //
     /* 253013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 253016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlal2),
     /* 253021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 253030 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 253033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253037 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253041 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253045 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253049 */     // (intrinsic_wo_chain:{ *:[v4f32] } 631:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLAL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 253049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAL2v8f16),
     /* 253052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253056 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253058 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253060 */     GIR_RootConstrainSelectedInstOperands,
     /* 253061 */     // GIR_Coverage, 44,
     /* 253061 */     GIR_EraseRootFromParent_Done,
     /* 253062 */   // Label 4827: @253062
     /* 253062 */   GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(253116), // Rule ID 45 //
     /* 253067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 253070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 253075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 253078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 253081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 253084 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 253087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253091 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253095 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253099 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253103 */     // (intrinsic_wo_chain:{ *:[v2f32] } 633:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMLSL2v4f16:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 253103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v4f16),
     /* 253106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253108 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253110 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253112 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253114 */     GIR_RootConstrainSelectedInstOperands,
     /* 253115 */     // GIR_Coverage, 45,
     /* 253115 */     GIR_EraseRootFromParent_Done,
     /* 253116 */   // Label 4828: @253116
     /* 253116 */   GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(253170), // Rule ID 46 //
     /* 253121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16FML_HasNEON),
     /* 253124 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmlsl2),
     /* 253129 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253132 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253135 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 253138 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 253141 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253153 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253157 */     // (intrinsic_wo_chain:{ *:[v4f32] } 633:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMLSL2v8f16:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 253157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSL2v8f16),
     /* 253160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253166 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253168 */     GIR_RootConstrainSelectedInstOperands,
     /* 253169 */     // GIR_Coverage, 46,
     /* 253169 */     GIR_EraseRootFromParent_Done,
     /* 253170 */   // Label 4829: @253170
     /* 253170 */   GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(253224), // Rule ID 1593 //
     /* 253175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 253183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 253186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 253189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 253192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 253195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253199 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253203 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253207 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253211 */     // (intrinsic_wo_chain:{ *:[v4i16] } 711:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMLAHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 253211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i16),
     /* 253214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253220 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253222 */     GIR_RootConstrainSelectedInstOperands,
     /* 253223 */     // GIR_Coverage, 1593,
     /* 253223 */     GIR_EraseRootFromParent_Done,
     /* 253224 */   // Label 4830: @253224
     /* 253224 */   GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(253278), // Rule ID 1594 //
     /* 253229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 253237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 253240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 253243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 253246 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 253249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253257 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253261 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253265 */     // (intrinsic_wo_chain:{ *:[v8i16] } 711:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMLAHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 253265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv8i16),
     /* 253268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253274 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253276 */     GIR_RootConstrainSelectedInstOperands,
     /* 253277 */     // GIR_Coverage, 1594,
     /* 253277 */     GIR_EraseRootFromParent_Done,
     /* 253278 */   // Label 4831: @253278
     /* 253278 */   GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(253332), // Rule ID 1595 //
     /* 253283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 253291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 253294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 253297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 253300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 253303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253307 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253311 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253315 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253319 */     // (intrinsic_wo_chain:{ *:[v2i32] } 711:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMLAHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 253319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv2i32),
     /* 253322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253328 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253330 */     GIR_RootConstrainSelectedInstOperands,
     /* 253331 */     // GIR_Coverage, 1595,
     /* 253331 */     GIR_EraseRootFromParent_Done,
     /* 253332 */   // Label 4832: @253332
     /* 253332 */   GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(253386), // Rule ID 1596 //
     /* 253337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 253345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253354 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253361 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253365 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253369 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253373 */     // (intrinsic_wo_chain:{ *:[v4i32] } 711:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMLAHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv4i32),
     /* 253376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253378 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253382 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253384 */     GIR_RootConstrainSelectedInstOperands,
     /* 253385 */     // GIR_Coverage, 1596,
     /* 253385 */     GIR_EraseRootFromParent_Done,
     /* 253386 */   // Label 4833: @253386
     /* 253386 */   GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(253440), // Rule ID 1597 //
     /* 253391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253394 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 253399 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 253402 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 253405 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 253408 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 253411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253423 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253427 */     // (intrinsic_wo_chain:{ *:[v4i16] } 712:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQRDMLSHv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 253427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i16),
     /* 253430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253436 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253438 */     GIR_RootConstrainSelectedInstOperands,
     /* 253439 */     // GIR_Coverage, 1597,
     /* 253439 */     GIR_EraseRootFromParent_Done,
     /* 253440 */   // Label 4834: @253440
     /* 253440 */   GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(253494), // Rule ID 1598 //
     /* 253445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 253453 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 253456 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 253459 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 253462 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 253465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253469 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253473 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253477 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253481 */     // (intrinsic_wo_chain:{ *:[v8i16] } 712:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQRDMLSHv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 253481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv8i16),
     /* 253484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253488 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253490 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253492 */     GIR_RootConstrainSelectedInstOperands,
     /* 253493 */     // GIR_Coverage, 1598,
     /* 253493 */     GIR_EraseRootFromParent_Done,
     /* 253494 */   // Label 4835: @253494
     /* 253494 */   GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(253548), // Rule ID 1599 //
     /* 253499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253502 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 253507 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 253510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 253513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 253516 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 253519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253527 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253531 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 253535 */     // (intrinsic_wo_chain:{ *:[v2i32] } 712:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQRDMLSHv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 253535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv2i32),
     /* 253538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253544 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253546 */     GIR_RootConstrainSelectedInstOperands,
     /* 253547 */     // GIR_Coverage, 1599,
     /* 253547 */     GIR_EraseRootFromParent_Done,
     /* 253548 */   // Label 4836: @253548
     /* 253548 */   GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(253602), // Rule ID 1600 //
     /* 253553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRDM),
     /* 253556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 253561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253570 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253581 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253585 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253589 */     // (intrinsic_wo_chain:{ *:[v4i32] } 712:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQRDMLSHv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv4i32),
     /* 253592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253594 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253596 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253598 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253600 */     GIR_RootConstrainSelectedInstOperands,
     /* 253601 */     // GIR_Coverage, 1600,
     /* 253601 */     GIR_EraseRootFromParent_Done,
     /* 253602 */   // Label 4837: @253602
     /* 253602 */   GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(253656), // Rule ID 2338 //
     /* 253607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1c),
     /* 253615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253621 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 253624 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253631 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253635 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 253639 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253643 */     // (intrinsic_wo_chain:{ *:[v4i32] } 544:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Crrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Crrr),
     /* 253646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253652 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253654 */     GIR_RootConstrainSelectedInstOperands,
     /* 253655 */     // GIR_Coverage, 2338,
     /* 253655 */     GIR_EraseRootFromParent_Done,
     /* 253656 */   // Label 4838: @253656
     /* 253656 */   GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(253710), // Rule ID 2339 //
     /* 253661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1p),
     /* 253669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 253678 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253685 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253689 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 253693 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253697 */     // (intrinsic_wo_chain:{ *:[v4i32] } 547:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Prrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Prrr),
     /* 253700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253706 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253708 */     GIR_RootConstrainSelectedInstOperands,
     /* 253709 */     // GIR_Coverage, 2339,
     /* 253709 */     GIR_EraseRootFromParent_Done,
     /* 253710 */   // Label 4839: @253710
     /* 253710 */   GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(253764), // Rule ID 2340 //
     /* 253715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1m),
     /* 253723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 253732 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253739 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253743 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 253747 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253751 */     // (intrinsic_wo_chain:{ *:[v4i32] } 546:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1Mrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1Mrrr),
     /* 253754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253756 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253760 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253762 */     GIR_RootConstrainSelectedInstOperands,
     /* 253763 */     // GIR_Coverage, 2340,
     /* 253763 */     GIR_EraseRootFromParent_Done,
     /* 253764 */   // Label 4840: @253764
     /* 253764 */   GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(253818), // Rule ID 2341 //
     /* 253769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253772 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha1su0),
     /* 253777 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253786 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253801 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253805 */     // (intrinsic_wo_chain:{ *:[v4i32] } 548:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA1SU0rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA1SU0rrr),
     /* 253808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253810 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253812 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253814 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253816 */     GIR_RootConstrainSelectedInstOperands,
     /* 253817 */     // GIR_Coverage, 2341,
     /* 253817 */     GIR_EraseRootFromParent_Done,
     /* 253818 */   // Label 4841: @253818
     /* 253818 */   GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(253872), // Rule ID 2342 //
     /* 253823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h),
     /* 253831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253840 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253847 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253851 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253855 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253859 */     // (intrinsic_wo_chain:{ *:[v4i32] } 550:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256Hrrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256Hrrr),
     /* 253862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253866 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253868 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253870 */     GIR_RootConstrainSelectedInstOperands,
     /* 253871 */     // GIR_Coverage, 2342,
     /* 253871 */     GIR_EraseRootFromParent_Done,
     /* 253872 */   // Label 4842: @253872
     /* 253872 */   GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(253926), // Rule ID 2343 //
     /* 253877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253880 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256h2),
     /* 253885 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253894 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253897 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253901 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253905 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253909 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253913 */     // (intrinsic_wo_chain:{ *:[v4i32] } 551:{ *:[iPTR] }, FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256H2rrr:{ *:[v4i32] } FPR128:{ *:[v4i32] }:$Rd, FPR128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256H2rrr),
     /* 253916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253922 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253924 */     GIR_RootConstrainSelectedInstOperands,
     /* 253925 */     // GIR_Coverage, 2343,
     /* 253925 */     GIR_EraseRootFromParent_Done,
     /* 253926 */   // Label 4843: @253926
     /* 253926 */   GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(253980), // Rule ID 2344 //
     /* 253931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2),
     /* 253934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha256su1),
     /* 253939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 253942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 253945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 253948 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 253951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253959 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253963 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 253967 */     // (intrinsic_wo_chain:{ *:[v4i32] } 553:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SHA256SU1rrr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 253967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA256SU1rrr),
     /* 253970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 253972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 253974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 253976 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 253978 */     GIR_RootConstrainSelectedInstOperands,
     /* 253979 */     // GIR_Coverage, 2344,
     /* 253979 */     GIR_EraseRootFromParent_Done,
     /* 253980 */   // Label 4844: @253980
     /* 253980 */   GIM_Try, /*On fail goto*//*Label 4845*/ GIMT_Encode4(254034), // Rule ID 2415 //
     /* 253985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF8F16MM_HasNEON),
     /* 253988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmmla),
     /* 253993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 253996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 253999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 254002 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 254005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254009 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254013 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254017 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254021 */     // (intrinsic_wo_chain:{ *:[v8f16] } 634:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 254021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLAv8f16),
     /* 254024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 254026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 254028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 254030 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 254032 */     GIR_RootConstrainSelectedInstOperands,
     /* 254033 */     // GIR_Coverage, 2415,
     /* 254033 */     GIR_EraseRootFromParent_Done,
     /* 254034 */   // Label 4845: @254034
     /* 254034 */   GIM_Try, /*On fail goto*//*Label 4846*/ GIMT_Encode4(254088), // Rule ID 2416 //
     /* 254039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF8F32MM_HasNEON),
     /* 254042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fmmla),
     /* 254047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 254050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 254053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 254056 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 254059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254071 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254075 */     // (intrinsic_wo_chain:{ *:[v4f32] } 634:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 254075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLAv4f32),
     /* 254078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 254080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 254082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 254084 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 254086 */     GIR_RootConstrainSelectedInstOperands,
     /* 254087 */     // GIR_Coverage, 2416,
     /* 254087 */     GIR_EraseRootFromParent_Done,
     /* 254088 */   // Label 4846: @254088
     /* 254088 */   GIM_Try, /*On fail goto*//*Label 4847*/ GIMT_Encode4(254142), // Rule ID 2542 //
     /* 254093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
     /* 254096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlah),
     /* 254101 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 254104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 254107 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 254110 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 254113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 254117 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 254121 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 254125 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 254129 */     // (intrinsic_wo_chain:{ *:[i32] } 711:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMLAHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 254129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAHv1i32),
     /* 254132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 254134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 254136 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 254138 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 254140 */     GIR_RootConstrainSelectedInstOperands,
     /* 254141 */     // GIR_Coverage, 2542,
     /* 254141 */     GIR_EraseRootFromParent_Done,
     /* 254142 */   // Label 4847: @254142
     /* 254142 */   GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(254199), // Rule ID 3723 //
     /* 254147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 254150 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 254155 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 254158 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254161 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 254164 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 254167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 254171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254175 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254179 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 254183 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1704:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR8:{ *:[nxv16i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_B:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 254183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_B),
     /* 254186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 254188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 254190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 254192 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 254194 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 254197 */     GIR_RootConstrainSelectedInstOperands,
     /* 254198 */     // GIR_Coverage, 3723,
     /* 254198 */     GIR_EraseRootFromParent_Done,
     /* 254199 */   // Label 4848: @254199
     /* 254199 */   GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(254256), // Rule ID 3724 //
     /* 254204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 254207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 254212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 254215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 254221 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 254224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 254228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254232 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254236 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 254240 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1704:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR16:{ *:[nxv8i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_H:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 254240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_H),
     /* 254243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 254245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 254247 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 254249 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 254251 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 254254 */     GIR_RootConstrainSelectedInstOperands,
     /* 254255 */     // GIR_Coverage, 3724,
     /* 254255 */     GIR_EraseRootFromParent_Done,
     /* 254256 */   // Label 4849: @254256
     /* 254256 */   GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(254313), // Rule ID 3725 //
     /* 254261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 254264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 254269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 254272 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254275 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 254278 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 254281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 254285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254289 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254293 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 254297 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1704:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR32:{ *:[nxv4i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_S:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 254297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_S),
     /* 254300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 254302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 254304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 254306 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 254308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 254311 */     GIR_RootConstrainSelectedInstOperands,
     /* 254312 */     // GIR_Coverage, 3725,
     /* 254312 */     GIR_EraseRootFromParent_Done,
     /* 254313 */   // Label 4850: @254313
     /* 254313 */   GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(254370), // Rule ID 3726 //
     /* 254318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 254321 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_psel),
     /* 254326 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 254329 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 254332 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 254335 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 254338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 254342 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254346 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 254350 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::MatrixIndexGPR32_12_15RegClassID),
     /* 254354 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1704:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pn, PPR64:{ *:[nxv2i1] }:$Pm, MatrixIndexGPR32Op12_15:{ *:[i32] }:$idx)  =>  (PSEL_PPPRI_D:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[i32] }:$idx, 0:{ *:[i32] })
     /* 254354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PSEL_PPPRI_D),
     /* 254357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 254359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 254361 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 254363 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 254365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 254368 */     GIR_RootConstrainSelectedInstOperands,
     /* 254369 */     // GIR_Coverage, 3726,
     /* 254369 */     GIR_EraseRootFromParent_Done,
     /* 254370 */   // Label 4851: @254370
     /* 254370 */   GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(254424), // Rule ID 3905 //
     /* 254375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h),
     /* 254383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 254386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 254389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 254392 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 254395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254399 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254403 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254407 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254411 */     // (intrinsic_wo_chain:{ *:[v2i64] } 554:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512H:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 254411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H),
     /* 254414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 254416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254420 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254422 */     GIR_RootConstrainSelectedInstOperands,
     /* 254423 */     // GIR_Coverage, 3905,
     /* 254423 */     GIR_EraseRootFromParent_Done,
     /* 254424 */   // Label 4852: @254424
     /* 254424 */   GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(254478), // Rule ID 3906 //
     /* 254429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512h2),
     /* 254437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 254440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 254443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 254446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 254449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254457 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254461 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254465 */     // (intrinsic_wo_chain:{ *:[v2i64] } 555:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512H2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 254465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512H2),
     /* 254468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 254470 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254472 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254474 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254476 */     GIR_RootConstrainSelectedInstOperands,
     /* 254477 */     // GIR_Coverage, 3906,
     /* 254477 */     GIR_EraseRootFromParent_Done,
     /* 254478 */   // Label 4853: @254478
     /* 254478 */   GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(254532), // Rule ID 3907 //
     /* 254483 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254486 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sha512su1),
     /* 254491 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 254494 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 254497 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 254500 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 254503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254507 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254511 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254515 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254519 */     // (intrinsic_wo_chain:{ *:[v2i64] } 557:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (SHA512SU1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 254519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHA512SU1),
     /* 254522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 254524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254528 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254530 */     GIR_RootConstrainSelectedInstOperands,
     /* 254531 */     // GIR_Coverage, 3907,
     /* 254531 */     GIR_EraseRootFromParent_Done,
     /* 254532 */   // Label 4854: @254532
     /* 254532 */   GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(254586), // Rule ID 3908 //
     /* 254537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 254545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 254548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 254551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 254554 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 254557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254561 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254565 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254569 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254573 */     // (intrinsic_wo_chain:{ *:[v16i8] } 542:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 254573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 254576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254580 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254582 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254584 */     GIR_RootConstrainSelectedInstOperands,
     /* 254585 */     // GIR_Coverage, 3908,
     /* 254585 */     GIR_EraseRootFromParent_Done,
     /* 254586 */   // Label 4855: @254586
     /* 254586 */   GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(254640), // Rule ID 3909 //
     /* 254591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 254599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 254602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 254605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 254608 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 254611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254619 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254623 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254627 */     // (intrinsic_wo_chain:{ *:[v8i16] } 542:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 254627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 254630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254636 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254638 */     GIR_RootConstrainSelectedInstOperands,
     /* 254639 */     // GIR_Coverage, 3909,
     /* 254639 */     GIR_EraseRootFromParent_Done,
     /* 254640 */   // Label 4856: @254640
     /* 254640 */   GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(254694), // Rule ID 3910 //
     /* 254645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 254653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 254656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 254659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 254662 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 254665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254673 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254677 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254681 */     // (intrinsic_wo_chain:{ *:[v4i32] } 542:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 254681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 254684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254690 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254692 */     GIR_RootConstrainSelectedInstOperands,
     /* 254693 */     // GIR_Coverage, 3910,
     /* 254693 */     GIR_EraseRootFromParent_Done,
     /* 254694 */   // Label 4857: @254694
     /* 254694 */   GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(254748), // Rule ID 3911 //
     /* 254699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3u),
     /* 254707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 254710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 254713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 254716 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 254719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254727 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254731 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254735 */     // (intrinsic_wo_chain:{ *:[v2i64] } 542:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 254735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 254738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254742 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254744 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254746 */     GIR_RootConstrainSelectedInstOperands,
     /* 254747 */     // GIR_Coverage, 3911,
     /* 254747 */     GIR_EraseRootFromParent_Done,
     /* 254748 */   // Label 4858: @254748
     /* 254748 */   GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(254802), // Rule ID 3924 //
     /* 254753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254756 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 254761 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 254764 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 254767 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 254770 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 254773 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254777 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254781 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254785 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254789 */     // (intrinsic_wo_chain:{ *:[v16i8] } 540:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 254789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 254792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254794 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254796 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254798 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254800 */     GIR_RootConstrainSelectedInstOperands,
     /* 254801 */     // GIR_Coverage, 3924,
     /* 254801 */     GIR_EraseRootFromParent_Done,
     /* 254802 */   // Label 4859: @254802
     /* 254802 */   GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(254856), // Rule ID 3925 //
     /* 254807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 254815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 254818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 254821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 254824 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 254827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254831 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254835 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254839 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254843 */     // (intrinsic_wo_chain:{ *:[v8i16] } 540:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 254843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 254846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254848 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254850 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254852 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254854 */     GIR_RootConstrainSelectedInstOperands,
     /* 254855 */     // GIR_Coverage, 3925,
     /* 254855 */     GIR_EraseRootFromParent_Done,
     /* 254856 */   // Label 4860: @254856
     /* 254856 */   GIM_Try, /*On fail goto*//*Label 4861*/ GIMT_Encode4(254910), // Rule ID 3926 //
     /* 254861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 254869 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 254872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 254875 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 254878 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 254881 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254889 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254893 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254897 */     // (intrinsic_wo_chain:{ *:[v4i32] } 540:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 254897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 254900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254906 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254908 */     GIR_RootConstrainSelectedInstOperands,
     /* 254909 */     // GIR_Coverage, 3926,
     /* 254909 */     GIR_EraseRootFromParent_Done,
     /* 254910 */   // Label 4861: @254910
     /* 254910 */   GIM_Try, /*On fail goto*//*Label 4862*/ GIMT_Encode4(254964), // Rule ID 3927 //
     /* 254915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxu),
     /* 254923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 254926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 254929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 254932 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 254935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254943 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254947 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254951 */     // (intrinsic_wo_chain:{ *:[v2i64] } 540:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 254951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 254954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 254956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 254958 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 254960 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 254962 */     GIR_RootConstrainSelectedInstOperands,
     /* 254963 */     // GIR_Coverage, 3927,
     /* 254963 */     GIR_EraseRootFromParent_Done,
     /* 254964 */   // Label 4862: @254964
     /* 254964 */   GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(255018), // Rule ID 3928 //
     /* 254969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 254972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 254977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 254980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 254983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 254986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 254989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 254997 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255001 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255005 */     // (intrinsic_wo_chain:{ *:[v16i8] } 541:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (EOR3:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 255005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 255008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255010 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255012 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255014 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255016 */     GIR_RootConstrainSelectedInstOperands,
     /* 255017 */     // GIR_Coverage, 3928,
     /* 255017 */     GIR_EraseRootFromParent_Done,
     /* 255018 */   // Label 4863: @255018
     /* 255018 */   GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(255072), // Rule ID 3929 //
     /* 255023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 255031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255040 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255047 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255051 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255055 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255059 */     // (intrinsic_wo_chain:{ *:[v8i16] } 541:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (EOR3:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 255059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 255062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255068 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255070 */     GIR_RootConstrainSelectedInstOperands,
     /* 255071 */     // GIR_Coverage, 3929,
     /* 255071 */     GIR_EraseRootFromParent_Done,
     /* 255072 */   // Label 4864: @255072
     /* 255072 */   GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(255126), // Rule ID 3930 //
     /* 255077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 255085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 255088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 255091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 255094 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 255097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255101 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255105 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255109 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255113 */     // (intrinsic_wo_chain:{ *:[v4i32] } 541:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (EOR3:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 255113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 255116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255118 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255120 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255122 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255124 */     GIR_RootConstrainSelectedInstOperands,
     /* 255125 */     // GIR_Coverage, 3930,
     /* 255125 */     GIR_EraseRootFromParent_Done,
     /* 255126 */   // Label 4865: @255126
     /* 255126 */   GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(255180), // Rule ID 3931 //
     /* 255131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255134 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_eor3s),
     /* 255139 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 255142 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 255145 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 255148 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 255151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255155 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255159 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255163 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255167 */     // (intrinsic_wo_chain:{ *:[v2i64] } 541:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (EOR3:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 255167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3),
     /* 255170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255176 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255178 */     GIR_RootConstrainSelectedInstOperands,
     /* 255179 */     // GIR_Coverage, 3931,
     /* 255179 */     GIR_EraseRootFromParent_Done,
     /* 255180 */   // Label 4866: @255180
     /* 255180 */   GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(255234), // Rule ID 3932 //
     /* 255185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 255193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 255196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 255199 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 255202 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 255205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255213 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255217 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255221 */     // (intrinsic_wo_chain:{ *:[v16i8] } 539:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)  =>  (BCAX:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, V128:{ *:[v16i8] }:$Vn, V128:{ *:[v16i8] }:$Vm)
     /* 255221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 255224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255226 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255228 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255230 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255232 */     GIR_RootConstrainSelectedInstOperands,
     /* 255233 */     // GIR_Coverage, 3932,
     /* 255233 */     GIR_EraseRootFromParent_Done,
     /* 255234 */   // Label 4867: @255234
     /* 255234 */   GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(255288), // Rule ID 3933 //
     /* 255239 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255242 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 255247 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255250 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255253 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255256 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255263 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255267 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255271 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255275 */     // (intrinsic_wo_chain:{ *:[v8i16] } 539:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)  =>  (BCAX:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, V128:{ *:[v8i16] }:$Vn, V128:{ *:[v8i16] }:$Vm)
     /* 255275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 255278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255282 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255284 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255286 */     GIR_RootConstrainSelectedInstOperands,
     /* 255287 */     // GIR_Coverage, 3933,
     /* 255287 */     GIR_EraseRootFromParent_Done,
     /* 255288 */   // Label 4868: @255288
     /* 255288 */   GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(255342), // Rule ID 3934 //
     /* 255293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 255301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 255304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 255307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 255310 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 255313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255317 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255321 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255325 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255329 */     // (intrinsic_wo_chain:{ *:[v4i32] } 539:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (BCAX:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 255329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 255332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255338 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255340 */     GIR_RootConstrainSelectedInstOperands,
     /* 255341 */     // GIR_Coverage, 3934,
     /* 255341 */     GIR_EraseRootFromParent_Done,
     /* 255342 */   // Label 4869: @255342
     /* 255342 */   GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(255396), // Rule ID 3935 //
     /* 255347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA3),
     /* 255350 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_bcaxs),
     /* 255355 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 255358 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 255361 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 255364 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 255367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255371 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255375 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255379 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255383 */     // (intrinsic_wo_chain:{ *:[v2i64] } 539:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)  =>  (BCAX:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm)
     /* 255383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX),
     /* 255386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255392 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255394 */     GIR_RootConstrainSelectedInstOperands,
     /* 255395 */     // GIR_Coverage, 3935,
     /* 255395 */     GIR_EraseRootFromParent_Done,
     /* 255396 */   // Label 4870: @255396
     /* 255396 */   GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(255450), // Rule ID 3939 //
     /* 255401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 255404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3ss1),
     /* 255409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 255412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 255415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 255418 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 255421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255429 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255433 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255437 */     // (intrinsic_wo_chain:{ *:[v4i32] } 560:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)  =>  (SM3SS1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, V128:{ *:[v4i32] }:$Va)
     /* 255437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3SS1),
     /* 255440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 255442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vn
     /* 255444 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vm
     /* 255446 */     GIR_RootToRootCopy, /*OpIdx*/4, // Va
     /* 255448 */     GIR_RootConstrainSelectedInstOperands,
     /* 255449 */     // GIR_Coverage, 3939,
     /* 255449 */     GIR_EraseRootFromParent_Done,
     /* 255450 */   // Label 4871: @255450
     /* 255450 */   GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(255504), // Rule ID 3940 //
     /* 255455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 255458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw1),
     /* 255463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 255466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 255469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 255472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 255475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255483 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255487 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255491 */     // (intrinsic_wo_chain:{ *:[v4i32] } 558:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM3PARTW1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 255491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW1),
     /* 255494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 255496 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255498 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255500 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255502 */     GIR_RootConstrainSelectedInstOperands,
     /* 255503 */     // GIR_Coverage, 3940,
     /* 255503 */     GIR_EraseRootFromParent_Done,
     /* 255504 */   // Label 4872: @255504
     /* 255504 */   GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(255558), // Rule ID 3941 //
     /* 255509 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 255512 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3partw2),
     /* 255517 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 255520 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 255523 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 255526 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 255529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255537 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255541 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255545 */     // (intrinsic_wo_chain:{ *:[v4i32] } 559:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)  =>  (SM3PARTW2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm)
     /* 255545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3PARTW2),
     /* 255548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 255550 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 255552 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 255554 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 255556 */     GIR_RootConstrainSelectedInstOperands,
     /* 255557 */     // GIR_Coverage, 3941,
     /* 255557 */     GIR_EraseRootFromParent_Done,
     /* 255558 */   // Label 4873: @255558
     /* 255558 */   GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(255615), // Rule ID 3958 //
     /* 255563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 255571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 255574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 255577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 255580 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 255583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255591 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255595 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255599 */     // (intrinsic_wo_chain:{ *:[v4f16] } 782:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
     /* 255599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 255602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255606 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255608 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255610 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 255613 */     GIR_RootConstrainSelectedInstOperands,
     /* 255614 */     // GIR_Coverage, 3958,
     /* 255614 */     GIR_EraseRootFromParent_Done,
     /* 255615 */   // Label 4874: @255615
     /* 255615 */   GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(255672), // Rule ID 3959 //
     /* 255620 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255623 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 255628 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 255631 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 255634 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 255637 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 255640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255644 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255652 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255656 */     // (intrinsic_wo_chain:{ *:[v4f16] } 785:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
     /* 255656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 255659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255663 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255665 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255667 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 255670 */     GIR_RootConstrainSelectedInstOperands,
     /* 255671 */     // GIR_Coverage, 3959,
     /* 255671 */     GIR_EraseRootFromParent_Done,
     /* 255672 */   // Label 4875: @255672
     /* 255672 */   GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(255729), // Rule ID 3960 //
     /* 255677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 255685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 255688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 255691 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 255694 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 255697 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255701 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255705 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255709 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255713 */     // (intrinsic_wo_chain:{ *:[v4f16] } 783:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 2:{ *:[i32] })
     /* 255713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 255716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255722 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 255727 */     GIR_RootConstrainSelectedInstOperands,
     /* 255728 */     // GIR_Coverage, 3960,
     /* 255728 */     GIR_EraseRootFromParent_Done,
     /* 255729 */   // Label 4876: @255729
     /* 255729 */   GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(255786), // Rule ID 3961 //
     /* 255734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 255742 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 255745 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 255748 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 255751 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
     /* 255754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255758 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255762 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255766 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 255770 */     // (intrinsic_wo_chain:{ *:[v4f16] } 784:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMLAv4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v4f16] }:$Rn, ?:{ *:[v4f16] }:$Rm, 3:{ *:[i32] })
     /* 255770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f16),
     /* 255773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255777 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255779 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 255784 */     GIR_RootConstrainSelectedInstOperands,
     /* 255785 */     // GIR_Coverage, 3961,
     /* 255785 */     GIR_EraseRootFromParent_Done,
     /* 255786 */   // Label 4877: @255786
     /* 255786 */   GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(255843), // Rule ID 3966 //
     /* 255791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 255799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255815 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255819 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255823 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255827 */     // (intrinsic_wo_chain:{ *:[v8f16] } 782:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
     /* 255827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 255830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255832 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255834 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255836 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 255841 */     GIR_RootConstrainSelectedInstOperands,
     /* 255842 */     // GIR_Coverage, 3966,
     /* 255842 */     GIR_EraseRootFromParent_Done,
     /* 255843 */   // Label 4878: @255843
     /* 255843 */   GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(255900), // Rule ID 3967 //
     /* 255848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255851 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 255856 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255865 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255872 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255876 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255880 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255884 */     // (intrinsic_wo_chain:{ *:[v8f16] } 785:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
     /* 255884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 255887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255891 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255893 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255895 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 255898 */     GIR_RootConstrainSelectedInstOperands,
     /* 255899 */     // GIR_Coverage, 3967,
     /* 255899 */     GIR_EraseRootFromParent_Done,
     /* 255900 */   // Label 4879: @255900
     /* 255900 */   GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(255957), // Rule ID 3968 //
     /* 255905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 255913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255937 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255941 */     // (intrinsic_wo_chain:{ *:[v8f16] } 783:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 2:{ *:[i32] })
     /* 255941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 255944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 255946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 255948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 255950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 255952 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 255955 */     GIR_RootConstrainSelectedInstOperands,
     /* 255956 */     // GIR_Coverage, 3968,
     /* 255956 */     GIR_EraseRootFromParent_Done,
     /* 255957 */   // Label 4880: @255957
     /* 255957 */   GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(256014), // Rule ID 3969 //
     /* 255962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasFullFP16_HasNEON),
     /* 255965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 255970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 255973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 255976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 255979 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 255982 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255986 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255990 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255994 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 255998 */     // (intrinsic_wo_chain:{ *:[v8f16] } 784:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMLAv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm, 3:{ *:[i32] })
     /* 255998 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv8f16),
     /* 256001 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256003 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256005 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256007 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256009 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 256012 */     GIR_RootConstrainSelectedInstOperands,
     /* 256013 */     // GIR_Coverage, 3969,
     /* 256013 */     GIR_EraseRootFromParent_Done,
     /* 256014 */   // Label 4881: @256014
     /* 256014 */   GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(256071), // Rule ID 3974 //
     /* 256019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 256027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 256030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 256033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 256036 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 256039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256047 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256051 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256055 */     // (intrinsic_wo_chain:{ *:[v2f32] } 782:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
     /* 256055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 256058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256064 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256066 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 256069 */     GIR_RootConstrainSelectedInstOperands,
     /* 256070 */     // GIR_Coverage, 3974,
     /* 256070 */     GIR_EraseRootFromParent_Done,
     /* 256071 */   // Label 4882: @256071
     /* 256071 */   GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(256128), // Rule ID 3975 //
     /* 256076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 256084 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 256087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 256090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 256093 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 256096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256108 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256112 */     // (intrinsic_wo_chain:{ *:[v2f32] } 785:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
     /* 256112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 256115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256121 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 256126 */     GIR_RootConstrainSelectedInstOperands,
     /* 256127 */     // GIR_Coverage, 3975,
     /* 256127 */     GIR_EraseRootFromParent_Done,
     /* 256128 */   // Label 4883: @256128
     /* 256128 */   GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(256185), // Rule ID 3976 //
     /* 256133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 256141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 256144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 256147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 256150 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 256153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256157 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256161 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256165 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256169 */     // (intrinsic_wo_chain:{ *:[v2f32] } 783:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 2:{ *:[i32] })
     /* 256169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 256172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256178 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 256183 */     GIR_RootConstrainSelectedInstOperands,
     /* 256184 */     // GIR_Coverage, 3976,
     /* 256184 */     GIR_EraseRootFromParent_Done,
     /* 256185 */   // Label 4884: @256185
     /* 256185 */   GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(256242), // Rule ID 3977 //
     /* 256190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 256198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 256201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 256204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 256207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
     /* 256210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256214 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256218 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256222 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256226 */     // (intrinsic_wo_chain:{ *:[v2f32] } 784:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMLAv2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v2f32] }:$Rn, ?:{ *:[v2f32] }:$Rm, 3:{ *:[i32] })
     /* 256226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f32),
     /* 256229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256231 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256233 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256235 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256237 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 256240 */     GIR_RootConstrainSelectedInstOperands,
     /* 256241 */     // GIR_Coverage, 3977,
     /* 256241 */     GIR_EraseRootFromParent_Done,
     /* 256242 */   // Label 4885: @256242
     /* 256242 */   GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(256299), // Rule ID 3978 //
     /* 256247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 256255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 256258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 256261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 256264 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 256267 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256275 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256279 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256283 */     // (intrinsic_wo_chain:{ *:[v4f32] } 782:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
     /* 256283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 256286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256292 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 256297 */     GIR_RootConstrainSelectedInstOperands,
     /* 256298 */     // GIR_Coverage, 3978,
     /* 256298 */     GIR_EraseRootFromParent_Done,
     /* 256299 */   // Label 4886: @256299
     /* 256299 */   GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(256356), // Rule ID 3979 //
     /* 256304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256307 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 256312 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 256315 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 256318 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 256321 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 256324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256336 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256340 */     // (intrinsic_wo_chain:{ *:[v4f32] } 785:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
     /* 256340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 256343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256347 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256349 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 256354 */     GIR_RootConstrainSelectedInstOperands,
     /* 256355 */     // GIR_Coverage, 3979,
     /* 256355 */     GIR_EraseRootFromParent_Done,
     /* 256356 */   // Label 4887: @256356
     /* 256356 */   GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(256413), // Rule ID 3980 //
     /* 256361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 256369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 256372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 256375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 256378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 256381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256389 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256393 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256397 */     // (intrinsic_wo_chain:{ *:[v4f32] } 783:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 2:{ *:[i32] })
     /* 256397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 256400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256402 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256404 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256406 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 256411 */     GIR_RootConstrainSelectedInstOperands,
     /* 256412 */     // GIR_Coverage, 3980,
     /* 256412 */     GIR_EraseRootFromParent_Done,
     /* 256413 */   // Label 4888: @256413
     /* 256413 */   GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(256470), // Rule ID 3981 //
     /* 256418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 256426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 256429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 256432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 256435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 256438 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256450 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256454 */     // (intrinsic_wo_chain:{ *:[v4f32] } 784:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMLAv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm, 3:{ *:[i32] })
     /* 256454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv4f32),
     /* 256457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256463 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256465 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 256468 */     GIR_RootConstrainSelectedInstOperands,
     /* 256469 */     // GIR_Coverage, 3981,
     /* 256469 */     GIR_EraseRootFromParent_Done,
     /* 256470 */   // Label 4889: @256470
     /* 256470 */   GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(256527), // Rule ID 3982 //
     /* 256475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256478 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot0),
     /* 256483 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 256486 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 256489 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 256492 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 256495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256507 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256511 */     // (intrinsic_wo_chain:{ *:[v2f64] } 782:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 0:{ *:[i32] })
     /* 256511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 256514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256520 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 256525 */     GIR_RootConstrainSelectedInstOperands,
     /* 256526 */     // GIR_Coverage, 3982,
     /* 256526 */     GIR_EraseRootFromParent_Done,
     /* 256527 */   // Label 4890: @256527
     /* 256527 */   GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(256584), // Rule ID 3983 //
     /* 256532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot90),
     /* 256540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 256543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 256546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 256549 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 256552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256556 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256560 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256564 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256568 */     // (intrinsic_wo_chain:{ *:[v2f64] } 785:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 1:{ *:[i32] })
     /* 256568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 256571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256577 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 256582 */     GIR_RootConstrainSelectedInstOperands,
     /* 256583 */     // GIR_Coverage, 3983,
     /* 256583 */     GIR_EraseRootFromParent_Done,
     /* 256584 */   // Label 4891: @256584
     /* 256584 */   GIM_Try, /*On fail goto*//*Label 4892*/ GIMT_Encode4(256641), // Rule ID 3984 //
     /* 256589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot180),
     /* 256597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 256600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 256603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 256606 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 256609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256617 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256621 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256625 */     // (intrinsic_wo_chain:{ *:[v2f64] } 783:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 2:{ *:[i32] })
     /* 256625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 256628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256630 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256632 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256634 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
     /* 256639 */     GIR_RootConstrainSelectedInstOperands,
     /* 256640 */     // GIR_Coverage, 3984,
     /* 256640 */     GIR_EraseRootFromParent_Done,
     /* 256641 */   // Label 4892: @256641
     /* 256641 */   GIM_Try, /*On fail goto*//*Label 4893*/ GIMT_Encode4(256698), // Rule ID 3985 //
     /* 256646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasComplxNum_HasNEON),
     /* 256649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcmla_rot270),
     /* 256654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 256657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 256660 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 256663 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 256666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256670 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256674 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256678 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256682 */     // (intrinsic_wo_chain:{ *:[v2f64] } 784:{ *:[iPTR] }, V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMLAv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rd, ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm, 3:{ *:[i32] })
     /* 256682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLAv2f64),
     /* 256685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256689 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256691 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256693 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 256696 */     GIR_RootConstrainSelectedInstOperands,
     /* 256697 */     // GIR_Coverage, 3985,
     /* 256697 */     GIR_EraseRootFromParent_Done,
     /* 256698 */   // Label 4893: @256698
     /* 256698 */   GIM_Try, /*On fail goto*//*Label 4894*/ GIMT_Encode4(256752), // Rule ID 5297 //
     /* 256703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasRDM),
     /* 256706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqrdmlsh),
     /* 256711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 256714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 256717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 256720 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 256723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 256727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 256731 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 256735 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 256739 */     // (intrinsic_wo_chain:{ *:[i32] } 712:{ *:[iPTR] }, FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)  =>  (SQRDMLSHv1i32:{ *:[i32] } FPR32:{ *:[i32] }:$Rd, FPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }:$Rm)
     /* 256739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSHv1i32),
     /* 256742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256748 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 256750 */     GIR_RootConstrainSelectedInstOperands,
     /* 256751 */     // GIR_Coverage, 5297,
     /* 256751 */     GIR_EraseRootFromParent_Done,
     /* 256752 */   // Label 4894: @256752
     /* 256752 */   GIM_Try, /*On fail goto*//*Label 4895*/ GIMT_Encode4(256803), // Rule ID 6185 //
     /* 256757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
     /* 256762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 256765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 256768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 256771 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 256774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256778 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256782 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256786 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 256790 */     // (intrinsic_wo_chain:{ *:[v8i8] } 745:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)  =>  (TBXv8i8One:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, VecListOne128:{ *:[v16i8] }:$Rn, V64:{ *:[v8i8] }:$Ri)
     /* 256790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv8i8One),
     /* 256793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256795 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256797 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 256799 */     GIR_RootToRootCopy, /*OpIdx*/4, // Ri
     /* 256801 */     GIR_RootConstrainSelectedInstOperands,
     /* 256802 */     // GIR_Coverage, 6185,
     /* 256802 */     GIR_EraseRootFromParent_Done,
     /* 256803 */   // Label 4895: @256803
     /* 256803 */   GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(256854), // Rule ID 6186 //
     /* 256808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_tbx1),
     /* 256813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 256816 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 256819 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 256822 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 256825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256829 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256833 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256837 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 256841 */     // (intrinsic_wo_chain:{ *:[v16i8] } 745:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)  =>  (TBXv16i8One:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Ri, V128:{ *:[v16i8] }:$Rn)
     /* 256841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXv16i8One),
     /* 256844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 256846 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 256848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ri
     /* 256850 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rn
     /* 256852 */     GIR_RootConstrainSelectedInstOperands,
     /* 256853 */     // GIR_Coverage, 6186,
     /* 256853 */     GIR_EraseRootFromParent_Done,
     /* 256854 */   // Label 4896: @256854
     /* 256854 */   GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(256896), // Rule ID 2738 //
     /* 256859 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256862 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 256867 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 256870 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 256873 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 256876 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 256879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256883 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1974:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (TBX_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 256883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_B),
     /* 256886 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256890 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256892 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256894 */     GIR_RootConstrainSelectedInstOperands,
     /* 256895 */     // GIR_Coverage, 2738,
     /* 256895 */     GIR_EraseRootFromParent_Done,
     /* 256896 */   // Label 4897: @256896
     /* 256896 */   GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(256938), // Rule ID 2739 //
     /* 256901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 256909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 256912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 256915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 256918 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 256921 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256925 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1974:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBX_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 256925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
     /* 256928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256930 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256932 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256934 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256936 */     GIR_RootConstrainSelectedInstOperands,
     /* 256937 */     // GIR_Coverage, 2739,
     /* 256937 */     GIR_EraseRootFromParent_Done,
     /* 256938 */   // Label 4898: @256938
     /* 256938 */   GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(256980), // Rule ID 2740 //
     /* 256943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 256951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 256954 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 256957 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 256960 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 256963 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 256967 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1974:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBX_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 256967 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
     /* 256970 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 256972 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 256974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 256976 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 256978 */     GIR_RootConstrainSelectedInstOperands,
     /* 256979 */     // GIR_Coverage, 2740,
     /* 256979 */     GIR_EraseRootFromParent_Done,
     /* 256980 */   // Label 4899: @256980
     /* 256980 */   GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(257022), // Rule ID 2741 //
     /* 256985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 256988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 256993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 256996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 256999 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257002 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257005 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257009 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1974:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBX_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 257009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
     /* 257012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257016 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257018 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257020 */     GIR_RootConstrainSelectedInstOperands,
     /* 257021 */     // GIR_Coverage, 2741,
     /* 257021 */     GIR_EraseRootFromParent_Done,
     /* 257022 */   // Label 4900: @257022
     /* 257022 */   GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(257064), // Rule ID 2742 //
     /* 257027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 257035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 257041 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257044 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257051 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1974:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBX_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 257051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_H),
     /* 257054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257056 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257058 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257060 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257062 */     GIR_RootConstrainSelectedInstOperands,
     /* 257063 */     // GIR_Coverage, 2742,
     /* 257063 */     GIR_EraseRootFromParent_Done,
     /* 257064 */   // Label 4901: @257064
     /* 257064 */   GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(257106), // Rule ID 2743 //
     /* 257069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 257077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257080 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257083 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257086 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257093 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1974:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBX_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 257093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_S),
     /* 257096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257098 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257102 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257104 */     GIR_RootConstrainSelectedInstOperands,
     /* 257105 */     // GIR_Coverage, 2743,
     /* 257105 */     GIR_EraseRootFromParent_Done,
     /* 257106 */   // Label 4902: @257106
     /* 257106 */   GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(257148), // Rule ID 2744 //
     /* 257111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbx),
     /* 257119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 257125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257128 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257135 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1974:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBX_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 257135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBX_ZZZ_D),
     /* 257138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257144 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257146 */     GIR_RootConstrainSelectedInstOperands,
     /* 257147 */     // GIR_Coverage, 2744,
     /* 257147 */     GIR_EraseRootFromParent_Done,
     /* 257148 */   // Label 4903: @257148
     /* 257148 */   GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(257190), // Rule ID 2783 //
     /* 257153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 257161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 257164 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 257167 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 257170 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 257173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 257177 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1295:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 257177 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 257180 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257182 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257184 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257186 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257188 */     GIR_RootConstrainSelectedInstOperands,
     /* 257189 */     // GIR_Coverage, 2783,
     /* 257189 */     GIR_EraseRootFromParent_Done,
     /* 257190 */   // Label 4904: @257190
     /* 257190 */   GIM_Try, /*On fail goto*//*Label 4905*/ GIMT_Encode4(257232), // Rule ID 2784 //
     /* 257195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 257203 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 257206 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257209 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 257212 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 257215 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 257219 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1295:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 257219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 257222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257224 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257226 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257228 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257230 */     GIR_RootConstrainSelectedInstOperands,
     /* 257231 */     // GIR_Coverage, 2784,
     /* 257231 */     GIR_EraseRootFromParent_Done,
     /* 257232 */   // Label 4905: @257232
     /* 257232 */   GIM_Try, /*On fail goto*//*Label 4906*/ GIMT_Encode4(257274), // Rule ID 2785 //
     /* 257237 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257240 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 257245 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 257248 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257251 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 257254 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 257257 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 257261 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1295:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 257261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 257264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257266 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257268 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257270 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257272 */     GIR_RootConstrainSelectedInstOperands,
     /* 257273 */     // GIR_Coverage, 2785,
     /* 257273 */     GIR_EraseRootFromParent_Done,
     /* 257274 */   // Label 4906: @257274
     /* 257274 */   GIM_Try, /*On fail goto*//*Label 4907*/ GIMT_Encode4(257316), // Rule ID 2786 //
     /* 257279 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257282 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 257287 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 257290 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257293 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 257296 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 257299 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 257303 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1295:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 257303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 257306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257308 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257310 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257312 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257314 */     GIR_RootConstrainSelectedInstOperands,
     /* 257315 */     // GIR_Coverage, 2786,
     /* 257315 */     GIR_EraseRootFromParent_Done,
     /* 257316 */   // Label 4907: @257316
     /* 257316 */   GIM_Try, /*On fail goto*//*Label 4908*/ GIMT_Encode4(257358), // Rule ID 2787 //
     /* 257321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257324 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_and_z),
     /* 257329 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 257332 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 257335 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 257338 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 257341 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 257345 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1295:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (AND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 257345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::AND_PPzPP),
     /* 257348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 257350 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257352 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257354 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257356 */     GIR_RootConstrainSelectedInstOperands,
     /* 257357 */     // GIR_Coverage, 2787,
     /* 257357 */     GIR_EraseRootFromParent_Done,
     /* 257358 */   // Label 4908: @257358
     /* 257358 */   GIM_Try, /*On fail goto*//*Label 4909*/ GIMT_Encode4(257400), // Rule ID 2832 //
     /* 257363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 257371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257380 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257387 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1395:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FADD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_H),
     /* 257390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257394 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257396 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257398 */     GIR_RootConstrainSelectedInstOperands,
     /* 257399 */     // GIR_Coverage, 2832,
     /* 257399 */     GIR_EraseRootFromParent_Done,
     /* 257400 */   // Label 4909: @257400
     /* 257400 */   GIM_Try, /*On fail goto*//*Label 4910*/ GIMT_Encode4(257442), // Rule ID 2834 //
     /* 257405 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257408 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 257413 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257416 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257419 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257422 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257425 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257429 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1395:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FADD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_S),
     /* 257432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257434 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257436 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257438 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257440 */     GIR_RootConstrainSelectedInstOperands,
     /* 257441 */     // GIR_Coverage, 2834,
     /* 257441 */     GIR_EraseRootFromParent_Done,
     /* 257442 */   // Label 4910: @257442
     /* 257442 */   GIM_Try, /*On fail goto*//*Label 4911*/ GIMT_Encode4(257484), // Rule ID 2836 //
     /* 257447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fadd),
     /* 257455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257464 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257471 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1395:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FADD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZPmZ_D),
     /* 257474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257476 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257478 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257480 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257482 */     GIR_RootConstrainSelectedInstOperands,
     /* 257483 */     // GIR_Coverage, 2836,
     /* 257483 */     GIR_EraseRootFromParent_Done,
     /* 257484 */   // Label 4911: @257484
     /* 257484 */   GIM_Try, /*On fail goto*//*Label 4912*/ GIMT_Encode4(257526), // Rule ID 2838 //
     /* 257489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 257497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257506 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257513 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1583:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (FSCALE_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 257513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_H),
     /* 257516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257522 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257524 */     GIR_RootConstrainSelectedInstOperands,
     /* 257525 */     // GIR_Coverage, 2838,
     /* 257525 */     GIR_EraseRootFromParent_Done,
     /* 257526 */   // Label 4912: @257526
     /* 257526 */   GIM_Try, /*On fail goto*//*Label 4913*/ GIMT_Encode4(257568), // Rule ID 2839 //
     /* 257531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 257539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257548 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257555 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1583:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (FSCALE_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 257555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_S),
     /* 257558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257562 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257564 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257566 */     GIR_RootConstrainSelectedInstOperands,
     /* 257567 */     // GIR_Coverage, 2839,
     /* 257567 */     GIR_EraseRootFromParent_Done,
     /* 257568 */   // Label 4913: @257568
     /* 257568 */   GIM_Try, /*On fail goto*//*Label 4914*/ GIMT_Encode4(257610), // Rule ID 2840 //
     /* 257573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 257576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fscale),
     /* 257581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 257587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 257590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257597 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1583:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (FSCALE_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 257597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSCALE_ZPmZ_D),
     /* 257600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257604 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257606 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257608 */     GIR_RootConstrainSelectedInstOperands,
     /* 257609 */     // GIR_Coverage, 2840,
     /* 257609 */     GIR_EraseRootFromParent_Done,
     /* 257610 */   // Label 4914: @257610
     /* 257610 */   GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(257652), // Rule ID 2924 //
     /* 257615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257618 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f16f32),
     /* 257623 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257626 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 257629 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 257632 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257639 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1431:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTNT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_StoH),
     /* 257642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257648 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257650 */     GIR_RootConstrainSelectedInstOperands,
     /* 257651 */     // GIR_Coverage, 2924,
     /* 257651 */     GIR_EraseRootFromParent_Done,
     /* 257652 */   // Label 4915: @257652
     /* 257652 */   GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(257694), // Rule ID 2925 //
     /* 257657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_f32f64),
     /* 257665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 257674 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257681 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1432:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPmZ_DtoS),
     /* 257684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257690 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257692 */     GIR_RootConstrainSelectedInstOperands,
     /* 257693 */     // GIR_Coverage, 2925,
     /* 257693 */     GIR_EraseRootFromParent_Done,
     /* 257694 */   // Label 4916: @257694
     /* 257694 */   GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(257736), // Rule ID 2926 //
     /* 257699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f32f16),
     /* 257707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 257716 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257723 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1427:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTLT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_HtoS),
     /* 257726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257732 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257734 */     GIR_RootConstrainSelectedInstOperands,
     /* 257735 */     // GIR_Coverage, 2926,
     /* 257735 */     GIR_EraseRootFromParent_Done,
     /* 257736 */   // Label 4917: @257736
     /* 257736 */   GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(257778), // Rule ID 2927 //
     /* 257741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtlt_f64f32),
     /* 257749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 257752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 257755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 257758 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257765 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1428:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTLT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLT_ZPmZ_StoD),
     /* 257768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257774 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257776 */     GIR_RootConstrainSelectedInstOperands,
     /* 257777 */     // GIR_Coverage, 2927,
     /* 257777 */     GIR_EraseRootFromParent_Done,
     /* 257778 */   // Label 4918: @257778
     /* 257778 */   GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(257820), // Rule ID 2928 //
     /* 257783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtxnt_f32f64),
     /* 257791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 257800 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257807 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1437:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTXNT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNT_ZPmZ_DtoS),
     /* 257810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257814 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257816 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257818 */     GIR_RootConstrainSelectedInstOperands,
     /* 257819 */     // GIR_Coverage, 2928,
     /* 257819 */     GIR_EraseRootFromParent_Done,
     /* 257820 */   // Label 4919: @257820
     /* 257820 */   GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(257862), // Rule ID 2929 //
     /* 257825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 257828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_z_f16f32),
     /* 257833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 257839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 257842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257849 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1434:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTNT_ZPzZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPzZ_StoH),
     /* 257852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257858 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257860 */     GIR_RootConstrainSelectedInstOperands,
     /* 257861 */     // GIR_Coverage, 2929,
     /* 257861 */     GIR_EraseRootFromParent_Done,
     /* 257862 */   // Label 4920: @257862
     /* 257862 */   GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(257904), // Rule ID 2930 //
     /* 257867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 257870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtnt_z_f32f64),
     /* 257875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 257881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 257884 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 257887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257891 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1435:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTNT_ZPzZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 257891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNT_ZPzZ_DtoS),
     /* 257894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 257896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257900 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257902 */     GIR_RootConstrainSelectedInstOperands,
     /* 257903 */     // GIR_Coverage, 2930,
     /* 257903 */     GIR_EraseRootFromParent_Done,
     /* 257904 */   // Label 4921: @257904
     /* 257904 */   GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(257946), // Rule ID 2931 //
     /* 257909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257912 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 257917 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 257920 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 257923 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 257926 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 257929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257933 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1398:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FADDP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 257933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_H),
     /* 257936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257942 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257944 */     GIR_RootConstrainSelectedInstOperands,
     /* 257945 */     // GIR_Coverage, 2931,
     /* 257945 */     GIR_EraseRootFromParent_Done,
     /* 257946 */   // Label 4922: @257946
     /* 257946 */   GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(257988), // Rule ID 2932 //
     /* 257951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 257959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 257962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 257965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 257968 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 257971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 257975 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1398:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FADDP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 257975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_S),
     /* 257978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 257980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 257982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 257984 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 257986 */     GIR_RootConstrainSelectedInstOperands,
     /* 257987 */     // GIR_Coverage, 2932,
     /* 257987 */     GIR_EraseRootFromParent_Done,
     /* 257988 */   // Label 4923: @257988
     /* 257988 */   GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(258030), // Rule ID 2933 //
     /* 257993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 257996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_faddp),
     /* 258001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258010 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258017 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1398:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FADDP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 258017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDP_ZPmZZ_D),
     /* 258020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258024 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258026 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258028 */     GIR_RootConstrainSelectedInstOperands,
     /* 258029 */     // GIR_Coverage, 2933,
     /* 258029 */     GIR_EraseRootFromParent_Done,
     /* 258030 */   // Label 4924: @258030
     /* 258030 */   GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(258072), // Rule ID 2944 //
     /* 258035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 258038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f16),
     /* 258043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 258052 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258059 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1420:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVT_ZPmZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoS),
     /* 258062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258068 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258070 */     GIR_RootConstrainSelectedInstOperands,
     /* 258071 */     // GIR_Coverage, 2944,
     /* 258071 */     GIR_EraseRootFromParent_Done,
     /* 258072 */   // Label 4925: @258072
     /* 258072 */   GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(258114), // Rule ID 2946 //
     /* 258077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 258080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f32),
     /* 258085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 258094 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258101 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1418:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVT_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 258101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoH),
     /* 258104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258108 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258110 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258112 */     GIR_RootConstrainSelectedInstOperands,
     /* 258113 */     // GIR_Coverage, 2946,
     /* 258113 */     GIR_EraseRootFromParent_Done,
     /* 258114 */   // Label 4926: @258114
     /* 258114 */   GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(258156), // Rule ID 2954 //
     /* 258119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 258127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 258136 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258143 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1460:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FLOGB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 258143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_H),
     /* 258146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258150 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258152 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258154 */     GIR_RootConstrainSelectedInstOperands,
     /* 258155 */     // GIR_Coverage, 2954,
     /* 258155 */     GIR_EraseRootFromParent_Done,
     /* 258156 */   // Label 4927: @258156
     /* 258156 */   GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(258198), // Rule ID 2955 //
     /* 258161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 258169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 258178 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258185 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1460:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FLOGB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 258185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_S),
     /* 258188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258194 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258196 */     GIR_RootConstrainSelectedInstOperands,
     /* 258197 */     // GIR_Coverage, 2955,
     /* 258197 */     GIR_EraseRootFromParent_Done,
     /* 258198 */   // Label 4928: @258198
     /* 258198 */   GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(258240), // Rule ID 2956 //
     /* 258203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_flogb),
     /* 258211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 258220 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258227 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1460:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FLOGB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 258227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FLOGB_ZPmZ_D),
     /* 258230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258234 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258236 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258238 */     GIR_RootConstrainSelectedInstOperands,
     /* 258239 */     // GIR_Coverage, 2956,
     /* 258239 */     GIR_EraseRootFromParent_Done,
     /* 258240 */   // Label 4929: @258240
     /* 258240 */   GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(258282), // Rule ID 2960 //
     /* 258245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtx_f32f64),
     /* 258253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 258262 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258269 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1436:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTX_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 258269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTX_ZPmZ_DtoS),
     /* 258272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 258274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258278 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258280 */     GIR_RootConstrainSelectedInstOperands,
     /* 258281 */     // GIR_Coverage, 2960,
     /* 258281 */     GIR_EraseRootFromParent_Done,
     /* 258282 */   // Label 4930: @258282
     /* 258282 */   GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(258324), // Rule ID 3008 //
     /* 258287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 258290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
     /* 258295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258301 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258304 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258311 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1758:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_S),
     /* 258314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258316 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258318 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258320 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258322 */     GIR_RootConstrainSelectedInstOperands,
     /* 258323 */     // GIR_Coverage, 3008,
     /* 258323 */     GIR_EraseRootFromParent_Done,
     /* 258324 */   // Label 4931: @258324
     /* 258324 */   GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(258366), // Rule ID 3009 //
     /* 258329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 258332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdiv),
     /* 258337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258346 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258353 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1758:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIV_ZPmZ_D),
     /* 258356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258360 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258362 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258364 */     GIR_RootConstrainSelectedInstOperands,
     /* 258365 */     // GIR_Coverage, 3009,
     /* 258365 */     GIR_EraseRootFromParent_Done,
     /* 258366 */   // Label 4932: @258366
     /* 258366 */   GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(258408), // Rule ID 3038 //
     /* 258371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 258379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 258382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 258385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 258388 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258395 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1875:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRDMLAH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_B),
     /* 258398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258402 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258404 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258406 */     GIR_RootConstrainSelectedInstOperands,
     /* 258407 */     // GIR_Coverage, 3038,
     /* 258407 */     GIR_EraseRootFromParent_Done,
     /* 258408 */   // Label 4933: @258408
     /* 258408 */   GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(258450), // Rule ID 3039 //
     /* 258413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 258421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258430 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258433 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258437 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1875:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRDMLAH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_H),
     /* 258440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258442 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258444 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258446 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258448 */     GIR_RootConstrainSelectedInstOperands,
     /* 258449 */     // GIR_Coverage, 3039,
     /* 258449 */     GIR_EraseRootFromParent_Done,
     /* 258450 */   // Label 4934: @258450
     /* 258450 */   GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(258492), // Rule ID 3040 //
     /* 258455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 258463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258479 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1875:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRDMLAH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_S),
     /* 258482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258484 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258488 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258490 */     GIR_RootConstrainSelectedInstOperands,
     /* 258491 */     // GIR_Coverage, 3040,
     /* 258491 */     GIR_EraseRootFromParent_Done,
     /* 258492 */   // Label 4935: @258492
     /* 258492 */   GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(258534), // Rule ID 3041 //
     /* 258497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah),
     /* 258505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258514 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258521 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1875:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRDMLAH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZ_D),
     /* 258524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258528 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258530 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258532 */     GIR_RootConstrainSelectedInstOperands,
     /* 258533 */     // GIR_Coverage, 3041,
     /* 258533 */     GIR_EraseRootFromParent_Done,
     /* 258534 */   // Label 4936: @258534
     /* 258534 */   GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(258576), // Rule ID 3042 //
     /* 258539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 258547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 258553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 258556 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258563 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1796:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_H),
     /* 258566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258572 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258574 */     GIR_RootConstrainSelectedInstOperands,
     /* 258575 */     // GIR_Coverage, 3042,
     /* 258575 */     GIR_EraseRootFromParent_Done,
     /* 258576 */   // Label 4937: @258576
     /* 258576 */   GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(258618), // Rule ID 3043 //
     /* 258581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 258589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258598 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258605 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1796:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_S),
     /* 258608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258610 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258612 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258614 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258616 */     GIR_RootConstrainSelectedInstOperands,
     /* 258617 */     // GIR_Coverage, 3043,
     /* 258617 */     GIR_EraseRootFromParent_Done,
     /* 258618 */   // Label 4938: @258618
     /* 258618 */   GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(258660), // Rule ID 3044 //
     /* 258623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb),
     /* 258631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 258637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258647 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1796:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZ_D),
     /* 258650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258656 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258658 */     GIR_RootConstrainSelectedInstOperands,
     /* 258659 */     // GIR_Coverage, 3044,
     /* 258659 */     GIR_EraseRootFromParent_Done,
     /* 258660 */   // Label 4939: @258660
     /* 258660 */   GIM_Try, /*On fail goto*//*Label 4940*/ GIMT_Encode4(258702), // Rule ID 3052 //
     /* 258665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 258668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_x2),
     /* 258673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258676 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 258679 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258682 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258689 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1764:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_HtoS),
     /* 258692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258696 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258698 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258700 */     GIR_RootConstrainSelectedInstOperands,
     /* 258701 */     // GIR_Coverage, 3052,
     /* 258701 */     GIR_EraseRootFromParent_Done,
     /* 258702 */   // Label 4940: @258702
     /* 258702 */   GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(258744), // Rule ID 3075 //
     /* 258707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 258715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 258718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 258721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 258724 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258731 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1769:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_B),
     /* 258734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258740 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258742 */     GIR_RootConstrainSelectedInstOperands,
     /* 258743 */     // GIR_Coverage, 3075,
     /* 258743 */     GIR_EraseRootFromParent_Done,
     /* 258744 */   // Label 4941: @258744
     /* 258744 */   GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(258786), // Rule ID 3077 //
     /* 258749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 258757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 258763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258766 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258773 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1769:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_H),
     /* 258776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258778 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258780 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258782 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258784 */     GIR_RootConstrainSelectedInstOperands,
     /* 258785 */     // GIR_Coverage, 3077,
     /* 258785 */     GIR_EraseRootFromParent_Done,
     /* 258786 */   // Label 4942: @258786
     /* 258786 */   GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(258828), // Rule ID 3079 //
     /* 258791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 258799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258815 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1769:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_S),
     /* 258818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258822 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258824 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258826 */     GIR_RootConstrainSelectedInstOperands,
     /* 258827 */     // GIR_Coverage, 3079,
     /* 258827 */     GIR_EraseRootFromParent_Done,
     /* 258828 */   // Label 4943: @258828
     /* 258828 */   GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(258870), // Rule ID 3081 //
     /* 258833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shadd),
     /* 258841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 258853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258857 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1769:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 258857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHADD_ZPmZ_D),
     /* 258860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 258862 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258864 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258866 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258868 */     GIR_RootConstrainSelectedInstOperands,
     /* 258869 */     // GIR_Coverage, 3081,
     /* 258869 */     GIR_EraseRootFromParent_Done,
     /* 258870 */   // Label 4944: @258870
     /* 258870 */   GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(258912), // Rule ID 3083 //
     /* 258875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258878 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 258883 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 258886 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 258889 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 258892 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 258895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258899 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1739:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 258899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_H),
     /* 258902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258908 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258910 */     GIR_RootConstrainSelectedInstOperands,
     /* 258911 */     // GIR_Coverage, 3083,
     /* 258911 */     GIR_EraseRootFromParent_Done,
     /* 258912 */   // Label 4945: @258912
     /* 258912 */   GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(258954), // Rule ID 3084 //
     /* 258917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 258925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 258928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 258931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 258934 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 258937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258941 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1739:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 258941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_S),
     /* 258944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258952 */     GIR_RootConstrainSelectedInstOperands,
     /* 258953 */     // GIR_Coverage, 3084,
     /* 258953 */     GIR_EraseRootFromParent_Done,
     /* 258954 */   // Label 4946: @258954
     /* 258954 */   GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(258996), // Rule ID 3085 //
     /* 258959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 258962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sadalp),
     /* 258967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 258970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 258973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 258976 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 258979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 258983 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1739:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 258983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADALP_ZPmZ_D),
     /* 258986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 258988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 258990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 258992 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 258994 */     GIR_RootConstrainSelectedInstOperands,
     /* 258995 */     // GIR_Coverage, 3085,
     /* 258995 */     GIR_EraseRootFromParent_Done,
     /* 258996 */   // Label 4947: @258996
     /* 258996 */   GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(259038), // Rule ID 3086 //
     /* 259001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urecpe),
     /* 259009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 259018 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259025 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2105:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URECPE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URECPE_ZPmZ_S),
     /* 259028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259032 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259034 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259036 */     GIR_RootConstrainSelectedInstOperands,
     /* 259037 */     // GIR_Coverage, 3086,
     /* 259037 */     GIR_EraseRootFromParent_Done,
     /* 259038 */   // Label 4948: @259038
     /* 259038 */   GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(259080), // Rule ID 3087 //
     /* 259043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 259051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 259054 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 259057 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 259060 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 259063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259067 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1812:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQABS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 259067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_B),
     /* 259070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259076 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259078 */     GIR_RootConstrainSelectedInstOperands,
     /* 259079 */     // GIR_Coverage, 3087,
     /* 259079 */     GIR_EraseRootFromParent_Done,
     /* 259080 */   // Label 4949: @259080
     /* 259080 */   GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(259122), // Rule ID 3088 //
     /* 259085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 259093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259099 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 259102 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259109 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1812:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQABS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 259109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_H),
     /* 259112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259116 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259118 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259120 */     GIR_RootConstrainSelectedInstOperands,
     /* 259121 */     // GIR_Coverage, 3088,
     /* 259121 */     GIR_EraseRootFromParent_Done,
     /* 259122 */   // Label 4950: @259122
     /* 259122 */   GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(259164), // Rule ID 3089 //
     /* 259127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 259135 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 259144 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259151 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1812:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQABS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_S),
     /* 259154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259160 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259162 */     GIR_RootConstrainSelectedInstOperands,
     /* 259163 */     // GIR_Coverage, 3089,
     /* 259163 */     GIR_EraseRootFromParent_Done,
     /* 259164 */   // Label 4951: @259164
     /* 259164 */   GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(259206), // Rule ID 3090 //
     /* 259169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqabs),
     /* 259177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 259183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 259186 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259193 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1812:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQABS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 259193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQABS_ZPmZ_D),
     /* 259196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259200 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259202 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259204 */     GIR_RootConstrainSelectedInstOperands,
     /* 259205 */     // GIR_Coverage, 3090,
     /* 259205 */     GIR_EraseRootFromParent_Done,
     /* 259206 */   // Label 4952: @259206
     /* 259206 */   GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(259248), // Rule ID 3107 //
     /* 259211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 259219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 259222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 259225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 259228 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 259231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259235 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1383:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EORBT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 259235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_B),
     /* 259238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259242 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259244 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259246 */     GIR_RootConstrainSelectedInstOperands,
     /* 259247 */     // GIR_Coverage, 3107,
     /* 259247 */     GIR_EraseRootFromParent_Done,
     /* 259248 */   // Label 4953: @259248
     /* 259248 */   GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(259290), // Rule ID 3108 //
     /* 259253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 259261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 259270 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259277 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1383:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EORBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 259277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_H),
     /* 259280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259282 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259284 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259286 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259288 */     GIR_RootConstrainSelectedInstOperands,
     /* 259289 */     // GIR_Coverage, 3108,
     /* 259289 */     GIR_EraseRootFromParent_Done,
     /* 259290 */   // Label 4954: @259290
     /* 259290 */   GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(259332), // Rule ID 3109 //
     /* 259295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259298 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 259303 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259306 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259309 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259312 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259319 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1383:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EORBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_S),
     /* 259322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259328 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259330 */     GIR_RootConstrainSelectedInstOperands,
     /* 259331 */     // GIR_Coverage, 3109,
     /* 259331 */     GIR_EraseRootFromParent_Done,
     /* 259332 */   // Label 4955: @259332
     /* 259332 */   GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(259374), // Rule ID 3110 //
     /* 259337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eorbt),
     /* 259345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 259351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259354 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259361 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1383:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EORBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 259361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORBT_ZZZ_D),
     /* 259364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259368 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259370 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259372 */     GIR_RootConstrainSelectedInstOperands,
     /* 259373 */     // GIR_Coverage, 3110,
     /* 259373 */     GIR_EraseRootFromParent_Done,
     /* 259374 */   // Label 4956: @259374
     /* 259374 */   GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(259416), // Rule ID 3134 //
     /* 259379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 259387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 259390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 259393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 259396 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 259399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259403 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1732:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 259403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_B),
     /* 259406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259412 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259414 */     GIR_RootConstrainSelectedInstOperands,
     /* 259415 */     // GIR_Coverage, 3134,
     /* 259415 */     GIR_EraseRootFromParent_Done,
     /* 259416 */   // Label 4957: @259416
     /* 259416 */   GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(259458), // Rule ID 3136 //
     /* 259421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 259429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259435 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 259438 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259445 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1732:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 259445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_H),
     /* 259448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259454 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259456 */     GIR_RootConstrainSelectedInstOperands,
     /* 259457 */     // GIR_Coverage, 3136,
     /* 259457 */     GIR_EraseRootFromParent_Done,
     /* 259458 */   // Label 4958: @259458
     /* 259458 */   GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(259500), // Rule ID 3138 //
     /* 259463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 259471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259480 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259487 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1732:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_S),
     /* 259490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259492 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259494 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259496 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259498 */     GIR_RootConstrainSelectedInstOperands,
     /* 259499 */     // GIR_Coverage, 3138,
     /* 259499 */     GIR_EraseRootFromParent_Done,
     /* 259500 */   // Label 4959: @259500
     /* 259500 */   GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(259542), // Rule ID 3140 //
     /* 259505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_saba),
     /* 259513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 259519 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259522 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259529 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1732:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 259529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABA_ZZZ_D),
     /* 259532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259538 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259540 */     GIR_RootConstrainSelectedInstOperands,
     /* 259541 */     // GIR_Coverage, 3140,
     /* 259541 */     GIR_EraseRootFromParent_Done,
     /* 259542 */   // Label 4960: @259542
     /* 259542 */   GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(259584), // Rule ID 3142 //
     /* 259547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259550 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 259555 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259558 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259561 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 259564 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 259567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259571 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1733:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 259571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_H),
     /* 259574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259578 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259580 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259582 */     GIR_RootConstrainSelectedInstOperands,
     /* 259583 */     // GIR_Coverage, 3142,
     /* 259583 */     GIR_EraseRootFromParent_Done,
     /* 259584 */   // Label 4961: @259584
     /* 259584 */   GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(259626), // Rule ID 3143 //
     /* 259589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 259597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 259606 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259613 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1733:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 259613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_S),
     /* 259616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259622 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259624 */     GIR_RootConstrainSelectedInstOperands,
     /* 259625 */     // GIR_Coverage, 3143,
     /* 259625 */     GIR_EraseRootFromParent_Done,
     /* 259626 */   // Label 4962: @259626
     /* 259626 */   GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(259668), // Rule ID 3144 //
     /* 259631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalb),
     /* 259639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 259645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259648 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259655 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1733:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALB_ZZZ_D),
     /* 259658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259664 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259666 */     GIR_RootConstrainSelectedInstOperands,
     /* 259667 */     // GIR_Coverage, 3144,
     /* 259667 */     GIR_EraseRootFromParent_Done,
     /* 259668 */   // Label 4963: @259668
     /* 259668 */   GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(259710), // Rule ID 3145 //
     /* 259673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
     /* 259681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259690 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259697 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1267:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_S),
     /* 259700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259706 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259708 */     GIR_RootConstrainSelectedInstOperands,
     /* 259709 */     // GIR_Coverage, 3145,
     /* 259709 */     GIR_EraseRootFromParent_Done,
     /* 259710 */   // Label 4964: @259710
     /* 259710 */   GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(259752), // Rule ID 3146 //
     /* 259715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclb),
     /* 259723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 259726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 259729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259732 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259739 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1267:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 259739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLB_ZZZ_D),
     /* 259742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 259744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259748 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259750 */     GIR_RootConstrainSelectedInstOperands,
     /* 259751 */     // GIR_Coverage, 3146,
     /* 259751 */     GIR_EraseRootFromParent_Done,
     /* 259752 */   // Label 4965: @259752
     /* 259752 */   GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(259794), // Rule ID 3156 //
     /* 259757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 259765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 259768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 259771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 259774 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259781 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1274:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 259781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_B),
     /* 259784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259788 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259790 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259792 */     GIR_RootConstrainSelectedInstOperands,
     /* 259793 */     // GIR_Coverage, 3156,
     /* 259793 */     GIR_EraseRootFromParent_Done,
     /* 259794 */   // Label 4966: @259794
     /* 259794 */   GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(259836), // Rule ID 3157 //
     /* 259799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 259807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259810 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 259816 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259823 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1274:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 259823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_H),
     /* 259826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259832 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259834 */     GIR_RootConstrainSelectedInstOperands,
     /* 259835 */     // GIR_Coverage, 3157,
     /* 259835 */     GIR_EraseRootFromParent_Done,
     /* 259836 */   // Label 4967: @259836
     /* 259836 */   GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(259878), // Rule ID 3158 //
     /* 259841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 259844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addhnt),
     /* 259849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 259858 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 259861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259865 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1274:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 259865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNT_ZZZ_S),
     /* 259868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 259872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 259874 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 259876 */     GIR_RootConstrainSelectedInstOperands,
     /* 259877 */     // GIR_Coverage, 3158,
     /* 259877 */     GIR_EraseRootFromParent_Done,
     /* 259878 */   // Label 4968: @259878
     /* 259878 */   GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(259920), // Rule ID 3175 //
     /* 259883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 259886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 259891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 259894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 259897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 259900 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 259903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259907 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1341:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CLS_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 259907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_B),
     /* 259910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 259914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 259916 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 259918 */     GIR_RootConstrainSelectedInstOperands,
     /* 259919 */     // GIR_Coverage, 3175,
     /* 259919 */     GIR_EraseRootFromParent_Done,
     /* 259920 */   // Label 4969: @259920
     /* 259920 */   GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(259962), // Rule ID 3176 //
     /* 259925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 259928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 259933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 259936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 259939 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 259942 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 259945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259949 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1341:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CLS_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 259949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_H),
     /* 259952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 259956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 259958 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 259960 */     GIR_RootConstrainSelectedInstOperands,
     /* 259961 */     // GIR_Coverage, 3176,
     /* 259961 */     GIR_EraseRootFromParent_Done,
     /* 259962 */   // Label 4970: @259962
     /* 259962 */   GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(260004), // Rule ID 3177 //
     /* 259967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 259970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 259975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 259978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 259981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 259984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 259987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 259991 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1341:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CLS_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 259991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_S),
     /* 259994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 259996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 259998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 260000 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 260002 */     GIR_RootConstrainSelectedInstOperands,
     /* 260003 */     // GIR_Coverage, 3177,
     /* 260003 */     GIR_EraseRootFromParent_Done,
     /* 260004 */   // Label 4971: @260004
     /* 260004 */   GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(260046), // Rule ID 3178 //
     /* 260009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cls),
     /* 260017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 260020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 260023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 260026 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260033 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1341:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CLS_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 260033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLS_ZPmZ_D),
     /* 260036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 260038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 260040 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 260042 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 260044 */     GIR_RootConstrainSelectedInstOperands,
     /* 260045 */     // GIR_Coverage, 3178,
     /* 260045 */     GIR_EraseRootFromParent_Done,
     /* 260046 */   // Label 4972: @260046
     /* 260046 */   GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(260088), // Rule ID 3213 //
     /* 260051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 260054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 260059 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260062 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 260065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260068 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 260071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260075 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1382:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 260075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 260078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260084 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260086 */     GIR_RootConstrainSelectedInstOperands,
     /* 260087 */     // GIR_Coverage, 3213,
     /* 260087 */     GIR_EraseRootFromParent_Done,
     /* 260088 */   // Label 4973: @260088
     /* 260088 */   GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(260130), // Rule ID 3215 //
     /* 260093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 260096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 260101 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 260107 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260110 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260117 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1382:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 260117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 260120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260126 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260128 */     GIR_RootConstrainSelectedInstOperands,
     /* 260129 */     // GIR_Coverage, 3215,
     /* 260129 */     GIR_EraseRootFromParent_Done,
     /* 260130 */   // Label 4974: @260130
     /* 260130 */   GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(260172), // Rule ID 3217 //
     /* 260135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 260138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 260143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 260146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 260149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 260155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260159 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1382:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 260159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 260162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260164 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260168 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260170 */     GIR_RootConstrainSelectedInstOperands,
     /* 260171 */     // GIR_Coverage, 3217,
     /* 260171 */     GIR_EraseRootFromParent_Done,
     /* 260172 */   // Label 4975: @260172
     /* 260172 */   GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(260214), // Rule ID 3219 //
     /* 260177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 260180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor3),
     /* 260185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 260188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 260191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 260194 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260201 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1382:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EOR3_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR3_ZZZZ),
     /* 260204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260210 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260212 */     GIR_RootConstrainSelectedInstOperands,
     /* 260213 */     // GIR_Coverage, 3219,
     /* 260213 */     GIR_EraseRootFromParent_Done,
     /* 260214 */   // Label 4976: @260214
     /* 260214 */   GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(260259), // Rule ID 3262 //
     /* 260219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 260227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 260230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260233 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260236 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260243 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1346:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_B),
     /* 260246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260250 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260252 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260254 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260257 */     GIR_RootConstrainSelectedInstOperands,
     /* 260258 */     // GIR_Coverage, 3262,
     /* 260258 */     GIR_EraseRootFromParent_Done,
     /* 260259 */   // Label 4977: @260259
     /* 260259 */   GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(260304), // Rule ID 3263 //
     /* 260264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260267 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 260272 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 260275 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260278 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260281 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260288 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1346:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_H),
     /* 260291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260297 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260299 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260302 */     GIR_RootConstrainSelectedInstOperands,
     /* 260303 */     // GIR_Coverage, 3263,
     /* 260303 */     GIR_EraseRootFromParent_Done,
     /* 260304 */   // Label 4978: @260304
     /* 260304 */   GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(260349), // Rule ID 3264 //
     /* 260309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpeq_wide),
     /* 260317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 260320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260333 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1346:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPEQ_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_WIDE_PPzZZ_S),
     /* 260336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260342 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260344 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260347 */     GIR_RootConstrainSelectedInstOperands,
     /* 260348 */     // GIR_Coverage, 3264,
     /* 260348 */     GIR_EraseRootFromParent_Done,
     /* 260349 */   // Label 4979: @260349
     /* 260349 */   GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(260394), // Rule ID 3265 //
     /* 260354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 260362 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 260365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260371 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260378 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1348:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_B),
     /* 260381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260385 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260387 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260389 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260392 */     GIR_RootConstrainSelectedInstOperands,
     /* 260393 */     // GIR_Coverage, 3265,
     /* 260393 */     GIR_EraseRootFromParent_Done,
     /* 260394 */   // Label 4980: @260394
     /* 260394 */   GIM_Try, /*On fail goto*//*Label 4981*/ GIMT_Encode4(260439), // Rule ID 3266 //
     /* 260399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260402 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 260407 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 260410 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260413 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260416 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260423 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1348:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_H),
     /* 260426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260428 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260430 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260432 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260434 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260437 */     GIR_RootConstrainSelectedInstOperands,
     /* 260438 */     // GIR_Coverage, 3266,
     /* 260438 */     GIR_EraseRootFromParent_Done,
     /* 260439 */   // Label 4981: @260439
     /* 260439 */   GIM_Try, /*On fail goto*//*Label 4982*/ GIMT_Encode4(260484), // Rule ID 3267 //
     /* 260444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpge_wide),
     /* 260452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 260455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260461 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260468 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1348:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260468 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGE_WIDE_PPzZZ_S),
     /* 260471 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260473 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260477 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260479 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 260482 */     GIR_RootConstrainSelectedInstOperands,
     /* 260483 */     // GIR_Coverage, 3267,
     /* 260483 */     GIR_EraseRootFromParent_Done,
     /* 260484 */   // Label 4982: @260484
     /* 260484 */   GIM_Try, /*On fail goto*//*Label 4983*/ GIMT_Encode4(260526), // Rule ID 3322 //
     /* 260489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 260497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 260500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260506 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260513 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1393:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FACGE_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 260513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_H),
     /* 260516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260518 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260522 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260524 */     GIR_RootConstrainSelectedInstOperands,
     /* 260525 */     // GIR_Coverage, 3322,
     /* 260525 */     GIR_EraseRootFromParent_Done,
     /* 260526 */   // Label 4983: @260526
     /* 260526 */   GIM_Try, /*On fail goto*//*Label 4984*/ GIMT_Encode4(260568), // Rule ID 3323 //
     /* 260531 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260534 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 260539 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 260542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260548 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 260551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260555 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1393:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FACGE_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 260555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_S),
     /* 260558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260560 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260562 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260564 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260566 */     GIR_RootConstrainSelectedInstOperands,
     /* 260567 */     // GIR_Coverage, 3323,
     /* 260567 */     GIR_EraseRootFromParent_Done,
     /* 260568 */   // Label 4984: @260568
     /* 260568 */   GIM_Try, /*On fail goto*//*Label 4985*/ GIMT_Encode4(260610), // Rule ID 3324 //
     /* 260573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facge),
     /* 260581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 260584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 260587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 260590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 260597 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1393:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FACGE_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 260597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGE_PPzZZ_D),
     /* 260600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 260602 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260604 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260606 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260608 */     GIR_RootConstrainSelectedInstOperands,
     /* 260609 */     // GIR_Coverage, 3324,
     /* 260609 */     GIR_EraseRootFromParent_Done,
     /* 260610 */   // Label 4985: @260610
     /* 260610 */   GIM_Try, /*On fail goto*//*Label 4986*/ GIMT_Encode4(260652), // Rule ID 3376 //
     /* 260615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260618 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 260623 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260626 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260629 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260632 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 260635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260639 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1298:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (ASR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 260639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_B),
     /* 260642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260644 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260646 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260648 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260650 */     GIR_RootConstrainSelectedInstOperands,
     /* 260651 */     // GIR_Coverage, 3376,
     /* 260651 */     GIR_EraseRootFromParent_Done,
     /* 260652 */   // Label 4986: @260652
     /* 260652 */   GIM_Try, /*On fail goto*//*Label 4987*/ GIMT_Encode4(260694), // Rule ID 3377 //
     /* 260657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 260665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260674 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260677 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260681 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1298:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ASR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 260681 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_H),
     /* 260684 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260690 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260692 */     GIR_RootConstrainSelectedInstOperands,
     /* 260693 */     // GIR_Coverage, 3377,
     /* 260693 */     GIR_EraseRootFromParent_Done,
     /* 260694 */   // Label 4987: @260694
     /* 260694 */   GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(260736), // Rule ID 3378 //
     /* 260699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260702 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 260707 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 260710 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260713 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260716 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 260719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260723 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1298:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ASR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 260723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_S),
     /* 260726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260732 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260734 */     GIR_RootConstrainSelectedInstOperands,
     /* 260735 */     // GIR_Coverage, 3378,
     /* 260735 */     GIR_EraseRootFromParent_Done,
     /* 260736 */   // Label 4988: @260736
     /* 260736 */   GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(260778), // Rule ID 3379 //
     /* 260741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr),
     /* 260749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 260752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 260755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 260758 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260761 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260765 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1298:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_ZPmZ_D),
     /* 260768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260770 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260772 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260774 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260776 */     GIR_RootConstrainSelectedInstOperands,
     /* 260777 */     // GIR_Coverage, 3379,
     /* 260777 */     GIR_EraseRootFromParent_Done,
     /* 260778 */   // Label 4989: @260778
     /* 260778 */   GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(260820), // Rule ID 3388 //
     /* 260783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 260791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260800 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260803 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260807 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1300:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_B),
     /* 260810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260814 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260816 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260818 */     GIR_RootConstrainSelectedInstOperands,
     /* 260819 */     // GIR_Coverage, 3388,
     /* 260819 */     GIR_EraseRootFromParent_Done,
     /* 260820 */   // Label 4990: @260820
     /* 260820 */   GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(260862), // Rule ID 3389 //
     /* 260825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 260833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260849 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1300:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_H),
     /* 260852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260858 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260860 */     GIR_RootConstrainSelectedInstOperands,
     /* 260861 */     // GIR_Coverage, 3389,
     /* 260861 */     GIR_EraseRootFromParent_Done,
     /* 260862 */   // Label 4991: @260862
     /* 260862 */   GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(260904), // Rule ID 3390 //
     /* 260867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_asr_wide),
     /* 260875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 260878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 260881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 260884 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 260887 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260891 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1300:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ASR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 260891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASR_WIDE_ZPmZ_S),
     /* 260894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260896 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260900 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260902 */     GIR_RootConstrainSelectedInstOperands,
     /* 260903 */     // GIR_Coverage, 3390,
     /* 260903 */     GIR_EraseRootFromParent_Done,
     /* 260904 */   // Label 4992: @260904
     /* 260904 */   GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(260946), // Rule ID 3429 //
     /* 260909 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260912 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 260917 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 260920 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 260923 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 260926 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 260929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260933 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1337:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (CLASTA_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 260933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_B),
     /* 260936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260942 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260944 */     GIR_RootConstrainSelectedInstOperands,
     /* 260945 */     // GIR_Coverage, 3429,
     /* 260945 */     GIR_EraseRootFromParent_Done,
     /* 260946 */   // Label 4993: @260946
     /* 260946 */   GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(260988), // Rule ID 3430 //
     /* 260951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 260959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 260962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 260965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 260968 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 260971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 260975 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1337:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (CLASTA_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 260975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
     /* 260978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 260980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 260982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 260984 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 260986 */     GIR_RootConstrainSelectedInstOperands,
     /* 260987 */     // GIR_Coverage, 3430,
     /* 260987 */     GIR_EraseRootFromParent_Done,
     /* 260988 */   // Label 4994: @260988
     /* 260988 */   GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(261030), // Rule ID 3431 //
     /* 260993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 260996 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 261001 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261004 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 261007 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261010 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261013 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261017 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1337:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (CLASTA_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 261017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
     /* 261020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261024 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261026 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261028 */     GIR_RootConstrainSelectedInstOperands,
     /* 261029 */     // GIR_Coverage, 3431,
     /* 261029 */     GIR_EraseRootFromParent_Done,
     /* 261030 */   // Label 4995: @261030
     /* 261030 */   GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(261072), // Rule ID 3432 //
     /* 261035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 261043 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261046 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 261049 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261052 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261055 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261059 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1337:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CLASTA_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 261059 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
     /* 261062 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261064 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261068 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261070 */     GIR_RootConstrainSelectedInstOperands,
     /* 261071 */     // GIR_Coverage, 3432,
     /* 261071 */     GIR_EraseRootFromParent_Done,
     /* 261072 */   // Label 4996: @261072
     /* 261072 */   GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(261114), // Rule ID 3433 //
     /* 261077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 261085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 261091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261094 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261101 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1337:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (CLASTA_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 261101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_H),
     /* 261104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261106 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261108 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261110 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261112 */     GIR_RootConstrainSelectedInstOperands,
     /* 261113 */     // GIR_Coverage, 3433,
     /* 261113 */     GIR_EraseRootFromParent_Done,
     /* 261114 */   // Label 4997: @261114
     /* 261114 */   GIM_Try, /*On fail goto*//*Label 4998*/ GIMT_Encode4(261156), // Rule ID 3434 //
     /* 261119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 261127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 261133 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261136 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261143 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1337:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (CLASTA_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 261143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_S),
     /* 261146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261148 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261150 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261152 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261154 */     GIR_RootConstrainSelectedInstOperands,
     /* 261155 */     // GIR_Coverage, 3434,
     /* 261155 */     GIR_EraseRootFromParent_Done,
     /* 261156 */   // Label 4998: @261156
     /* 261156 */   GIM_Try, /*On fail goto*//*Label 4999*/ GIMT_Encode4(261198), // Rule ID 3435 //
     /* 261161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clasta),
     /* 261169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 261175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261178 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261181 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261185 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1337:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (CLASTA_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 261185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTA_ZPZ_D),
     /* 261188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261194 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261196 */     GIR_RootConstrainSelectedInstOperands,
     /* 261197 */     // GIR_Coverage, 3435,
     /* 261197 */     GIR_EraseRootFromParent_Done,
     /* 261198 */   // Label 4999: @261198
     /* 261198 */   GIM_Try, /*On fail goto*//*Label 5000*/ GIMT_Encode4(261240), // Rule ID 3529 //
     /* 261203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261206 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpa_z),
     /* 261211 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 261214 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 261217 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 261220 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 261223 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 261227 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1329:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKPA_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 261227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPA_PPzPP),
     /* 261230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 261232 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261234 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261236 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261238 */     GIR_RootConstrainSelectedInstOperands,
     /* 261239 */     // GIR_Coverage, 3529,
     /* 261239 */     GIR_EraseRootFromParent_Done,
     /* 261240 */   // Label 5000: @261240
     /* 261240 */   GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(261282), // Rule ID 3530 //
     /* 261245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkn_z),
     /* 261253 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 261256 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 261259 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 261262 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 261265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 261269 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1328:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKN_PPzP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 261269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKN_PPzP),
     /* 261272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pdm]
     /* 261274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261278 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261280 */     GIR_RootConstrainSelectedInstOperands,
     /* 261281 */     // GIR_Coverage, 3530,
     /* 261281 */     GIR_EraseRootFromParent_Done,
     /* 261282 */   // Label 5001: @261282
     /* 261282 */   GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(261324), // Rule ID 3531 //
     /* 261287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brka),
     /* 261295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 261298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 261301 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 261304 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 261307 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 261311 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1324:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKA_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 261311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKA_PPmP),
     /* 261314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 261316 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261318 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261320 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261322 */     GIR_RootConstrainSelectedInstOperands,
     /* 261323 */     // GIR_Coverage, 3531,
     /* 261323 */     GIR_EraseRootFromParent_Done,
     /* 261324 */   // Label 5002: @261324
     /* 261324 */   GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(261369), // Rule ID 3533 //
     /* 261329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 261332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
     /* 261337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 261340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 261343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 261346 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 261349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 261353 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1651:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (MATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 261353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_B),
     /* 261356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 261358 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261360 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261362 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261364 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 261367 */     GIR_RootConstrainSelectedInstOperands,
     /* 261368 */     // GIR_Coverage, 3533,
     /* 261368 */     GIR_EraseRootFromParent_Done,
     /* 261369 */   // Label 5003: @261369
     /* 261369 */   GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(261414), // Rule ID 3534 //
     /* 261374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 261377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_match),
     /* 261382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 261385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 261388 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261391 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 261398 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1651:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (MATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 261398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MATCH_PPzZZ_H),
     /* 261401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 261403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261407 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261409 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 261412 */     GIR_RootConstrainSelectedInstOperands,
     /* 261413 */     // GIR_Coverage, 3534,
     /* 261413 */     GIR_EraseRootFromParent_Done,
     /* 261414 */   // Label 5004: @261414
     /* 261414 */   GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(261456), // Rule ID 3535 //
     /* 261419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 261422 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
     /* 261427 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 261433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261436 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261443 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1595:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (HISTCNT_ZPzZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 261443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_S),
     /* 261446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261452 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261454 */     GIR_RootConstrainSelectedInstOperands,
     /* 261455 */     // GIR_Coverage, 3535,
     /* 261455 */     GIR_EraseRootFromParent_Done,
     /* 261456 */   // Label 5005: @261456
     /* 261456 */   GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(261498), // Rule ID 3536 //
     /* 261461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 261464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_histcnt),
     /* 261469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 261475 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261478 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261485 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1595:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (HISTCNT_ZPzZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 261485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HISTCNT_ZPzZZ_D),
     /* 261488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261492 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261494 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261496 */     GIR_RootConstrainSelectedInstOperands,
     /* 261497 */     // GIR_Coverage, 3536,
     /* 261497 */     GIR_EraseRootFromParent_Done,
     /* 261498 */   // Label 5006: @261498
     /* 261498 */   GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(261540), // Rule ID 3540 //
     /* 261503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p2_or_SME2p2),
     /* 261506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtxnt_z_f32f64),
     /* 261511 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261514 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 261520 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261527 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1438:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTXNT_ZPzZ_StoD:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 261527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNT_ZPzZ_StoD),
     /* 261530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261536 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261538 */     GIR_RootConstrainSelectedInstOperands,
     /* 261539 */     // GIR_Coverage, 3540,
     /* 261539 */     GIR_EraseRootFromParent_Done,
     /* 261540 */   // Label 5007: @261540
     /* 261540 */   GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(261582), // Rule ID 3541 //
     /* 261545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 261548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smmla),
     /* 261553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 261562 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 261565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261569 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1804:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 261569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMMLA_ZZZ),
     /* 261572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 261574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261576 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261578 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261580 */     GIR_RootConstrainSelectedInstOperands,
     /* 261581 */     // GIR_Coverage, 3541,
     /* 261581 */     GIR_EraseRootFromParent_Done,
     /* 261582 */   // Label 5008: @261582
     /* 261582 */   GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(261624), // Rule ID 3582 //
     /* 261587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 261590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 261595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 261601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261604 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261611 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1406:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCLAMP_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 261611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_H),
     /* 261614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261616 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261620 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261622 */     GIR_RootConstrainSelectedInstOperands,
     /* 261623 */     // GIR_Coverage, 3582,
     /* 261623 */     GIR_EraseRootFromParent_Done,
     /* 261624 */   // Label 5009: @261624
     /* 261624 */   GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(261666), // Rule ID 3584 //
     /* 261629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 261632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 261637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261646 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261653 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1406:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCLAMP_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 261653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_S),
     /* 261656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261662 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261664 */     GIR_RootConstrainSelectedInstOperands,
     /* 261665 */     // GIR_Coverage, 3584,
     /* 261665 */     GIR_EraseRootFromParent_Done,
     /* 261666 */   // Label 5010: @261666
     /* 261666 */   GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(261708), // Rule ID 3586 //
     /* 261671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 261674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fclamp),
     /* 261679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 261685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261688 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261695 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1406:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCLAMP_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 261695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCLAMP_ZZZ_D),
     /* 261698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261702 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261704 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261706 */     GIR_RootConstrainSelectedInstOperands,
     /* 261707 */     // GIR_Coverage, 3586,
     /* 261707 */     GIR_EraseRootFromParent_Done,
     /* 261708 */   // Label 5011: @261708
     /* 261708 */   GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(261750), // Rule ID 3715 //
     /* 261713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 261716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 261721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 261724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 261727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 261730 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 261733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261737 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1748:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 261737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_B),
     /* 261740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261746 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261748 */     GIR_RootConstrainSelectedInstOperands,
     /* 261749 */     // GIR_Coverage, 3715,
     /* 261749 */     GIR_EraseRootFromParent_Done,
     /* 261750 */   // Label 5012: @261750
     /* 261750 */   GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(261792), // Rule ID 3717 //
     /* 261755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 261758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 261763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 261769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261772 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261779 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1748:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 261779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_H),
     /* 261782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261788 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261790 */     GIR_RootConstrainSelectedInstOperands,
     /* 261791 */     // GIR_Coverage, 3717,
     /* 261791 */     GIR_EraseRootFromParent_Done,
     /* 261792 */   // Label 5013: @261792
     /* 261792 */   GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(261834), // Rule ID 3719 //
     /* 261797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 261800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 261805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 261811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261814 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261821 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1748:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 261821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_S),
     /* 261824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261830 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261832 */     GIR_RootConstrainSelectedInstOperands,
     /* 261833 */     // GIR_Coverage, 3719,
     /* 261833 */     GIR_EraseRootFromParent_Done,
     /* 261834 */   // Label 5014: @261834
     /* 261834 */   GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(261876), // Rule ID 3721 //
     /* 261839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 261842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sclamp),
     /* 261847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 261850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 261853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 261856 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 261859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261863 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1748:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 261863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCLAMP_ZZZ_D),
     /* 261866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 261868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261870 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261872 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261874 */     GIR_RootConstrainSelectedInstOperands,
     /* 261875 */     // GIR_Coverage, 3721,
     /* 261875 */     GIR_EraseRootFromParent_Done,
     /* 261876 */   // Label 5015: @261876
     /* 261876 */   GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(261918), // Rule ID 8158 //
     /* 261881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 261889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 261892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 261895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 261898 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 261901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261905 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1961:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 261905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_B),
     /* 261908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261912 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261914 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261916 */     GIR_RootConstrainSelectedInstOperands,
     /* 261917 */     // GIR_Coverage, 8158,
     /* 261917 */     GIR_EraseRootFromParent_Done,
     /* 261918 */   // Label 5016: @261918
     /* 261918 */   GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(261960), // Rule ID 8160 //
     /* 261923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 261931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 261934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 261937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 261940 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 261943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261947 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1961:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 261947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_H),
     /* 261950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261956 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 261958 */     GIR_RootConstrainSelectedInstOperands,
     /* 261959 */     // GIR_Coverage, 8160,
     /* 261959 */     GIR_EraseRootFromParent_Done,
     /* 261960 */   // Label 5017: @261960
     /* 261960 */   GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(262002), // Rule ID 8162 //
     /* 261965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 261968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 261973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 261976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 261979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 261982 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 261985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 261989 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1961:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 261989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_S),
     /* 261992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 261994 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 261996 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 261998 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262000 */     GIR_RootConstrainSelectedInstOperands,
     /* 262001 */     // GIR_Coverage, 8162,
     /* 262001 */     GIR_EraseRootFromParent_Done,
     /* 262002 */   // Label 5018: @262002
     /* 262002 */   GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(262044), // Rule ID 8164 //
     /* 262007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subr),
     /* 262015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262024 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262031 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1961:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_D),
     /* 262034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262040 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262042 */     GIR_RootConstrainSelectedInstOperands,
     /* 262043 */     // GIR_Coverage, 8164,
     /* 262043 */     GIR_EraseRootFromParent_Done,
     /* 262044 */   // Label 5019: @262044
     /* 262044 */   GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(262086), // Rule ID 8182 //
     /* 262049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 262057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 262060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 262063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262066 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262073 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1321:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (BIC_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 262073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_B),
     /* 262076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262082 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262084 */     GIR_RootConstrainSelectedInstOperands,
     /* 262085 */     // GIR_Coverage, 8182,
     /* 262085 */     GIR_EraseRootFromParent_Done,
     /* 262086 */   // Label 5020: @262086
     /* 262086 */   GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(262128), // Rule ID 8183 //
     /* 262091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262094 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 262099 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262102 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 262105 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262108 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262115 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1321:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (BIC_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 262115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_H),
     /* 262118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262120 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262122 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262124 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262126 */     GIR_RootConstrainSelectedInstOperands,
     /* 262127 */     // GIR_Coverage, 8183,
     /* 262127 */     GIR_EraseRootFromParent_Done,
     /* 262128 */   // Label 5021: @262128
     /* 262128 */   GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(262170), // Rule ID 8184 //
     /* 262133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 262141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262150 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262157 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1321:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (BIC_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_S),
     /* 262160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262166 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262168 */     GIR_RootConstrainSelectedInstOperands,
     /* 262169 */     // GIR_Coverage, 8184,
     /* 262169 */     GIR_EraseRootFromParent_Done,
     /* 262170 */   // Label 5022: @262170
     /* 262170 */   GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(262212), // Rule ID 8185 //
     /* 262175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic),
     /* 262183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262199 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1321:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (BIC_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_ZPmZ_D),
     /* 262202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262206 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262208 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262210 */     GIR_RootConstrainSelectedInstOperands,
     /* 262211 */     // GIR_Coverage, 8185,
     /* 262211 */     GIR_EraseRootFromParent_Done,
     /* 262212 */   // Label 5023: @262212
     /* 262212 */   GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(262254), // Rule ID 8301 //
     /* 262217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 262225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 262228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 262231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262234 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262241 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1805:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 262241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_B),
     /* 262244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262248 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262250 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262252 */     GIR_RootConstrainSelectedInstOperands,
     /* 262253 */     // GIR_Coverage, 8301,
     /* 262253 */     GIR_EraseRootFromParent_Done,
     /* 262254 */   // Label 5024: @262254
     /* 262254 */   GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(262296), // Rule ID 8302 //
     /* 262259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 262267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 262273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262276 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262283 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1805:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 262283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_H),
     /* 262286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262292 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262294 */     GIR_RootConstrainSelectedInstOperands,
     /* 262295 */     // GIR_Coverage, 8302,
     /* 262295 */     GIR_EraseRootFromParent_Done,
     /* 262296 */   // Label 5025: @262296
     /* 262296 */   GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(262338), // Rule ID 8303 //
     /* 262301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262304 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 262309 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262312 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262315 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262318 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262325 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1805:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_S),
     /* 262328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262334 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262336 */     GIR_RootConstrainSelectedInstOperands,
     /* 262337 */     // GIR_Coverage, 8303,
     /* 262337 */     GIR_EraseRootFromParent_Done,
     /* 262338 */   // Label 5026: @262338
     /* 262338 */   GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(262380), // Rule ID 8304 //
     /* 262343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smulh),
     /* 262351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262360 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262367 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1805:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULH_ZPmZ_D),
     /* 262370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262372 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262374 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262376 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262378 */     GIR_RootConstrainSelectedInstOperands,
     /* 262379 */     // GIR_Coverage, 8304,
     /* 262379 */     GIR_EraseRootFromParent_Done,
     /* 262380 */   // Label 5027: @262380
     /* 262380 */   GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(262422), // Rule ID 8305 //
     /* 262385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 262393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 262396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 262399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 262402 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262409 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2047:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMULH_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 262409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_B),
     /* 262412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262418 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262420 */     GIR_RootConstrainSelectedInstOperands,
     /* 262421 */     // GIR_Coverage, 8305,
     /* 262421 */     GIR_EraseRootFromParent_Done,
     /* 262422 */   // Label 5028: @262422
     /* 262422 */   GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(262464), // Rule ID 8306 //
     /* 262427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262430 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 262435 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 262441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 262444 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262451 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2047:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMULH_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 262451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_H),
     /* 262454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262460 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262462 */     GIR_RootConstrainSelectedInstOperands,
     /* 262463 */     // GIR_Coverage, 8306,
     /* 262463 */     GIR_EraseRootFromParent_Done,
     /* 262464 */   // Label 5029: @262464
     /* 262464 */   GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(262506), // Rule ID 8307 //
     /* 262469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 262477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262486 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262493 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2047:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMULH_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_S),
     /* 262496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262500 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262502 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262504 */     GIR_RootConstrainSelectedInstOperands,
     /* 262505 */     // GIR_Coverage, 8307,
     /* 262505 */     GIR_EraseRootFromParent_Done,
     /* 262506 */   // Label 5030: @262506
     /* 262506 */   GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(262548), // Rule ID 8308 //
     /* 262511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umulh),
     /* 262519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262528 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262535 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2047:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMULH_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULH_ZPmZ_D),
     /* 262538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262544 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262546 */     GIR_RootConstrainSelectedInstOperands,
     /* 262547 */     // GIR_Coverage, 8308,
     /* 262547 */     GIR_EraseRootFromParent_Done,
     /* 262548 */   // Label 5031: @262548
     /* 262548 */   GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(262590), // Rule ID 8317 //
     /* 262553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
     /* 262561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262570 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262577 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2009:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UDIV_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_S),
     /* 262580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262582 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262584 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262586 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262588 */     GIR_RootConstrainSelectedInstOperands,
     /* 262589 */     // GIR_Coverage, 8317,
     /* 262589 */     GIR_EraseRootFromParent_Done,
     /* 262590 */   // Label 5032: @262590
     /* 262590 */   GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(262632), // Rule ID 8318 //
     /* 262595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udiv),
     /* 262603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262612 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262619 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2009:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UDIV_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIV_ZPmZ_D),
     /* 262622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262624 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262626 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262628 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262630 */     GIR_RootConstrainSelectedInstOperands,
     /* 262631 */     // GIR_Coverage, 8318,
     /* 262631 */     GIR_EraseRootFromParent_Done,
     /* 262632 */   // Label 5033: @262632
     /* 262632 */   GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(262674), // Rule ID 8319 //
     /* 262637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
     /* 262645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262648 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262651 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262654 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262661 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1760:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_S),
     /* 262664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262668 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262670 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262672 */     GIR_RootConstrainSelectedInstOperands,
     /* 262673 */     // GIR_Coverage, 8319,
     /* 262673 */     GIR_EraseRootFromParent_Done,
     /* 262674 */   // Label 5034: @262674
     /* 262674 */   GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(262716), // Rule ID 8320 //
     /* 262679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdivr),
     /* 262687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262693 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262696 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262703 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1760:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDIVR_ZPmZ_D),
     /* 262706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262710 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262712 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262714 */     GIR_RootConstrainSelectedInstOperands,
     /* 262715 */     // GIR_Coverage, 8320,
     /* 262715 */     GIR_EraseRootFromParent_Done,
     /* 262716 */   // Label 5035: @262716
     /* 262716 */   GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(262758), // Rule ID 8321 //
     /* 262721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
     /* 262729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 262735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 262738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262745 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2011:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UDIVR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 262745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_S),
     /* 262748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262752 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262754 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262756 */     GIR_RootConstrainSelectedInstOperands,
     /* 262757 */     // GIR_Coverage, 8321,
     /* 262757 */     GIR_EraseRootFromParent_Done,
     /* 262758 */   // Label 5036: @262758
     /* 262758 */   GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(262800), // Rule ID 8322 //
     /* 262763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udivr),
     /* 262771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 262777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 262780 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262787 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2011:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UDIVR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 262787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDIVR_ZPmZ_D),
     /* 262790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 262792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 262794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 262796 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 262798 */     GIR_RootConstrainSelectedInstOperands,
     /* 262799 */     // GIR_Coverage, 8322,
     /* 262799 */     GIR_EraseRootFromParent_Done,
     /* 262800 */   // Label 5037: @262800
     /* 262800 */   GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(262842), // Rule ID 8411 //
     /* 262805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 262813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 262816 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 262819 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 262822 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262829 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1361:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (CNOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 262829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_B),
     /* 262832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 262834 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 262836 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 262838 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 262840 */     GIR_RootConstrainSelectedInstOperands,
     /* 262841 */     // GIR_Coverage, 8411,
     /* 262841 */     GIR_EraseRootFromParent_Done,
     /* 262842 */   // Label 5038: @262842
     /* 262842 */   GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(262884), // Rule ID 8412 //
     /* 262847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 262855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 262858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 262861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 262864 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 262867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262871 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1361:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (CNOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 262871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_H),
     /* 262874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 262876 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 262878 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 262880 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 262882 */     GIR_RootConstrainSelectedInstOperands,
     /* 262883 */     // GIR_Coverage, 8412,
     /* 262883 */     GIR_EraseRootFromParent_Done,
     /* 262884 */   // Label 5039: @262884
     /* 262884 */   GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(262926), // Rule ID 8413 //
     /* 262889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 262897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 262900 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 262903 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 262906 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 262909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262913 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1361:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (CNOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 262913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_S),
     /* 262916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 262918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 262920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 262922 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 262924 */     GIR_RootConstrainSelectedInstOperands,
     /* 262925 */     // GIR_Coverage, 8413,
     /* 262925 */     GIR_EraseRootFromParent_Done,
     /* 262926 */   // Label 5040: @262926
     /* 262926 */   GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(262968), // Rule ID 8414 //
     /* 262931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cnot),
     /* 262939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 262942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 262945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 262948 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 262951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262955 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1361:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (CNOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 262955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CNOT_ZPmZ_D),
     /* 262958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 262960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 262962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 262964 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 262966 */     GIR_RootConstrainSelectedInstOperands,
     /* 262967 */     // GIR_Coverage, 8414,
     /* 262967 */     GIR_EraseRootFromParent_Done,
     /* 262968 */   // Label 5041: @262968
     /* 262968 */   GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(263010), // Rule ID 8423 //
     /* 262973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 262976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 262981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 262984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 262987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 262990 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 262993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 262997 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1667:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (NOT_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 262997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_B),
     /* 263000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 263002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 263004 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 263006 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 263008 */     GIR_RootConstrainSelectedInstOperands,
     /* 263009 */     // GIR_Coverage, 8423,
     /* 263009 */     GIR_EraseRootFromParent_Done,
     /* 263010 */   // Label 5042: @263010
     /* 263010 */   GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(263052), // Rule ID 8424 //
     /* 263015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 263023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 263029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 263032 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263039 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1667:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (NOT_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 263039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_H),
     /* 263042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 263044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 263046 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 263048 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 263050 */     GIR_RootConstrainSelectedInstOperands,
     /* 263051 */     // GIR_Coverage, 8424,
     /* 263051 */     GIR_EraseRootFromParent_Done,
     /* 263052 */   // Label 5043: @263052
     /* 263052 */   GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(263094), // Rule ID 8425 //
     /* 263057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 263065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 263071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 263074 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263081 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1667:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (NOT_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 263081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_S),
     /* 263084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 263086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 263088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 263090 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 263092 */     GIR_RootConstrainSelectedInstOperands,
     /* 263093 */     // GIR_Coverage, 8425,
     /* 263093 */     GIR_EraseRootFromParent_Done,
     /* 263094 */   // Label 5044: @263094
     /* 263094 */   GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(263136), // Rule ID 8426 //
     /* 263099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_not),
     /* 263107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 263113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 263116 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263123 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1667:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (NOT_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 263123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOT_ZPmZ_D),
     /* 263126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 263128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op3
     /* 263130 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op1
     /* 263132 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op2
     /* 263134 */     GIR_RootConstrainSelectedInstOperands,
     /* 263135 */     // GIR_Coverage, 8426,
     /* 263135 */     GIR_EraseRootFromParent_Done,
     /* 263136 */   // Label 5045: @263136
     /* 263136 */   GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(263178), // Rule ID 8505 //
     /* 263141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 263149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 263152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 263155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 263158 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 263161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263165 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1735:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 263165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_B),
     /* 263168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263170 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263172 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263174 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263176 */     GIR_RootConstrainSelectedInstOperands,
     /* 263177 */     // GIR_Coverage, 8505,
     /* 263177 */     GIR_EraseRootFromParent_Done,
     /* 263178 */   // Label 5046: @263178
     /* 263178 */   GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(263220), // Rule ID 8506 //
     /* 263183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 263191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263200 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263207 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1735:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 263207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_H),
     /* 263210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263214 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263216 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263218 */     GIR_RootConstrainSelectedInstOperands,
     /* 263219 */     // GIR_Coverage, 8506,
     /* 263219 */     GIR_EraseRootFromParent_Done,
     /* 263220 */   // Label 5047: @263220
     /* 263220 */   GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(263262), // Rule ID 8507 //
     /* 263225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 263233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263242 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263249 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1735:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 263249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_S),
     /* 263252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263258 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263260 */     GIR_RootConstrainSelectedInstOperands,
     /* 263261 */     // GIR_Coverage, 8507,
     /* 263261 */     GIR_EraseRootFromParent_Done,
     /* 263262 */   // Label 5048: @263262
     /* 263262 */   GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(263304), // Rule ID 8508 //
     /* 263267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabd),
     /* 263275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263284 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263291 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1735:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 263291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABD_ZPmZ_D),
     /* 263294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263300 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263302 */     GIR_RootConstrainSelectedInstOperands,
     /* 263303 */     // GIR_Coverage, 8508,
     /* 263303 */     GIR_EraseRootFromParent_Done,
     /* 263304 */   // Label 5049: @263304
     /* 263304 */   GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(263346), // Rule ID 8509 //
     /* 263309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 263317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 263320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 263323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 263326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 263329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263333 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1989:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 263333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_B),
     /* 263336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263342 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263344 */     GIR_RootConstrainSelectedInstOperands,
     /* 263345 */     // GIR_Coverage, 8509,
     /* 263345 */     GIR_EraseRootFromParent_Done,
     /* 263346 */   // Label 5050: @263346
     /* 263346 */   GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(263388), // Rule ID 8510 //
     /* 263351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 263359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263375 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1989:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 263375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_H),
     /* 263378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263380 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263382 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263384 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263386 */     GIR_RootConstrainSelectedInstOperands,
     /* 263387 */     // GIR_Coverage, 8510,
     /* 263387 */     GIR_EraseRootFromParent_Done,
     /* 263388 */   // Label 5051: @263388
     /* 263388 */   GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(263430), // Rule ID 8511 //
     /* 263393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 263401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263407 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263410 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263417 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1989:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 263417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_S),
     /* 263420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263426 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263428 */     GIR_RootConstrainSelectedInstOperands,
     /* 263429 */     // GIR_Coverage, 8511,
     /* 263429 */     GIR_EraseRootFromParent_Done,
     /* 263430 */   // Label 5052: @263430
     /* 263430 */   GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(263472), // Rule ID 8512 //
     /* 263435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabd),
     /* 263443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263452 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263459 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1989:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UABD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 263459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABD_ZPmZ_D),
     /* 263462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263468 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263470 */     GIR_RootConstrainSelectedInstOperands,
     /* 263471 */     // GIR_Coverage, 8512,
     /* 263471 */     GIR_EraseRootFromParent_Done,
     /* 263472 */   // Label 5053: @263472
     /* 263472 */   GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(263514), // Rule ID 8708 //
     /* 263477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 263485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263494 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263501 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1589:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FSUB_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 263501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_H),
     /* 263504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263508 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263510 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263512 */     GIR_RootConstrainSelectedInstOperands,
     /* 263513 */     // GIR_Coverage, 8708,
     /* 263513 */     GIR_EraseRootFromParent_Done,
     /* 263514 */   // Label 5054: @263514
     /* 263514 */   GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(263556), // Rule ID 8710 //
     /* 263519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 263527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263543 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1589:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FSUB_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 263543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_S),
     /* 263546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263552 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263554 */     GIR_RootConstrainSelectedInstOperands,
     /* 263555 */     // GIR_Coverage, 8710,
     /* 263555 */     GIR_EraseRootFromParent_Done,
     /* 263556 */   // Label 5055: @263556
     /* 263556 */   GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(263598), // Rule ID 8712 //
     /* 263561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263564 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsub),
     /* 263569 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263572 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263575 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263578 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263585 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1589:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FSUB_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 263585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZPmZ_D),
     /* 263588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263590 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263592 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263594 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263596 */     GIR_RootConstrainSelectedInstOperands,
     /* 263597 */     // GIR_Coverage, 8712,
     /* 263597 */     GIR_EraseRootFromParent_Done,
     /* 263598 */   // Label 5056: @263598
     /* 263598 */   GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(263640), // Rule ID 8720 //
     /* 263603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 263611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263620 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263627 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1591:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FSUBR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 263627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_H),
     /* 263630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263636 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263638 */     GIR_RootConstrainSelectedInstOperands,
     /* 263639 */     // GIR_Coverage, 8720,
     /* 263639 */     GIR_EraseRootFromParent_Done,
     /* 263640 */   // Label 5057: @263640
     /* 263640 */   GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(263682), // Rule ID 8722 //
     /* 263645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 263653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263662 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263669 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1591:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FSUBR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 263669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_S),
     /* 263672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263676 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263678 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263680 */     GIR_RootConstrainSelectedInstOperands,
     /* 263681 */     // GIR_Coverage, 8722,
     /* 263681 */     GIR_EraseRootFromParent_Done,
     /* 263682 */   // Label 5058: @263682
     /* 263682 */   GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(263724), // Rule ID 8724 //
     /* 263687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fsubr),
     /* 263695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263704 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263711 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1591:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FSUBR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 263711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FSUBR_ZPmZ_D),
     /* 263714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263718 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263720 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263722 */     GIR_RootConstrainSelectedInstOperands,
     /* 263723 */     // GIR_Coverage, 8724,
     /* 263723 */     GIR_EraseRootFromParent_Done,
     /* 263724 */   // Label 5059: @263724
     /* 263724 */   GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(263766), // Rule ID 8762 //
     /* 263729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 263737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263746 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263753 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1390:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FABD_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 263753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_H),
     /* 263756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263762 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263764 */     GIR_RootConstrainSelectedInstOperands,
     /* 263765 */     // GIR_Coverage, 8762,
     /* 263765 */     GIR_EraseRootFromParent_Done,
     /* 263766 */   // Label 5060: @263766
     /* 263766 */   GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(263808), // Rule ID 8763 //
     /* 263771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 263779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263788 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263795 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1390:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FABD_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 263795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_S),
     /* 263798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263802 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263804 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263806 */     GIR_RootConstrainSelectedInstOperands,
     /* 263807 */     // GIR_Coverage, 8763,
     /* 263807 */     GIR_EraseRootFromParent_Done,
     /* 263808 */   // Label 5061: @263808
     /* 263808 */   GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(263850), // Rule ID 8764 //
     /* 263813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd),
     /* 263821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263830 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263837 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1390:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FABD_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 263837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPmZ_D),
     /* 263840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263844 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263846 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263848 */     GIR_RootConstrainSelectedInstOperands,
     /* 263849 */     // GIR_Coverage, 8764,
     /* 263849 */     GIR_EraseRootFromParent_Done,
     /* 263850 */   // Label 5062: @263850
     /* 263850 */   GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(263892), // Rule ID 8765 //
     /* 263855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 263863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263872 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 263875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263879 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1521:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMULX_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 263879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_H),
     /* 263882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263886 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263888 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263890 */     GIR_RootConstrainSelectedInstOperands,
     /* 263891 */     // GIR_Coverage, 8765,
     /* 263891 */     GIR_EraseRootFromParent_Done,
     /* 263892 */   // Label 5063: @263892
     /* 263892 */   GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(263934), // Rule ID 8766 //
     /* 263897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 263905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 263908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 263911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 263914 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 263917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263921 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1521:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMULX_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 263921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_S),
     /* 263924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263926 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263928 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263930 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263932 */     GIR_RootConstrainSelectedInstOperands,
     /* 263933 */     // GIR_Coverage, 8766,
     /* 263933 */     GIR_EraseRootFromParent_Done,
     /* 263934 */   // Label 5064: @263934
     /* 263934 */   GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(263976), // Rule ID 8767 //
     /* 263939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263942 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx),
     /* 263947 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 263950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 263953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 263956 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 263959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 263963 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1521:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMULX_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 263963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPmZ_D),
     /* 263966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 263968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 263970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 263972 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 263974 */     GIR_RootConstrainSelectedInstOperands,
     /* 263975 */     // GIR_Coverage, 8767,
     /* 263975 */     GIR_EraseRootFromParent_Done,
     /* 263976 */   // Label 5065: @263976
     /* 263976 */   GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(264018), // Rule ID 8768 //
     /* 263981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 263984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 263989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 263992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 263995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 263998 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264005 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1455:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDIVR_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 264005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_H),
     /* 264008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264010 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264012 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264014 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264016 */     GIR_RootConstrainSelectedInstOperands,
     /* 264017 */     // GIR_Coverage, 8768,
     /* 264017 */     GIR_EraseRootFromParent_Done,
     /* 264018 */   // Label 5066: @264018
     /* 264018 */   GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(264060), // Rule ID 8769 //
     /* 264023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 264031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264040 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264047 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1455:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FDIVR_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 264047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_S),
     /* 264050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264056 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264058 */     GIR_RootConstrainSelectedInstOperands,
     /* 264059 */     // GIR_Coverage, 8769,
     /* 264059 */     GIR_EraseRootFromParent_Done,
     /* 264060 */   // Label 5067: @264060
     /* 264060 */   GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(264102), // Rule ID 8770 //
     /* 264065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdivr),
     /* 264073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264079 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264082 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264089 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1455:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FDIVR_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 264089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIVR_ZPmZ_D),
     /* 264092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264098 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264100 */     GIR_RootConstrainSelectedInstOperands,
     /* 264101 */     // GIR_Coverage, 8770,
     /* 264101 */     GIR_EraseRootFromParent_Done,
     /* 264102 */   // Label 5068: @264102
     /* 264102 */   GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(264144), // Rule ID 8771 //
     /* 264107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 264115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264124 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264131 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1453:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDIV_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 264131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_H),
     /* 264134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264138 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264140 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264142 */     GIR_RootConstrainSelectedInstOperands,
     /* 264143 */     // GIR_Coverage, 8771,
     /* 264143 */     GIR_EraseRootFromParent_Done,
     /* 264144 */   // Label 5069: @264144
     /* 264144 */   GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(264186), // Rule ID 8772 //
     /* 264149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 264157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264166 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264173 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1453:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FDIV_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 264173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_S),
     /* 264176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264182 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264184 */     GIR_RootConstrainSelectedInstOperands,
     /* 264185 */     // GIR_Coverage, 8772,
     /* 264185 */     GIR_EraseRootFromParent_Done,
     /* 264186 */   // Label 5070: @264186
     /* 264186 */   GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(264228), // Rule ID 8773 //
     /* 264191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264194 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdiv),
     /* 264199 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264208 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264215 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1453:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FDIV_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 264215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDIV_ZPmZ_D),
     /* 264218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 264220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264222 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264224 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264226 */     GIR_RootConstrainSelectedInstOperands,
     /* 264227 */     // GIR_Coverage, 8773,
     /* 264227 */     GIR_EraseRootFromParent_Done,
     /* 264228 */   // Label 5071: @264228
     /* 264228 */   GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(264270), // Rule ID 8810 //
     /* 264233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264250 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264257 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1391:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 264257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 264260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264266 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264268 */     GIR_RootConstrainSelectedInstOperands,
     /* 264269 */     // GIR_Coverage, 8810,
     /* 264269 */     GIR_EraseRootFromParent_Done,
     /* 264270 */   // Label 5072: @264270
     /* 264270 */   GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(264312), // Rule ID 8812 //
     /* 264275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 264286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 264292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 264295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264299 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1391:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 264299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 264302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264308 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264310 */     GIR_RootConstrainSelectedInstOperands,
     /* 264311 */     // GIR_Coverage, 8812,
     /* 264311 */     GIR_EraseRootFromParent_Done,
     /* 264312 */   // Label 5073: @264312
     /* 264312 */   GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(264354), // Rule ID 8814 //
     /* 264317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 264328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264331 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 264334 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 264337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264341 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1391:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FABD_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 264341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_H_UNDEF),
     /* 264344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264346 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264348 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264350 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264352 */     GIR_RootConstrainSelectedInstOperands,
     /* 264353 */     // GIR_Coverage, 8814,
     /* 264353 */     GIR_EraseRootFromParent_Done,
     /* 264354 */   // Label 5074: @264354
     /* 264354 */   GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(264396), // Rule ID 8816 //
     /* 264359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264376 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264383 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1391:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FABD_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 264383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
     /* 264386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264392 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264394 */     GIR_RootConstrainSelectedInstOperands,
     /* 264395 */     // GIR_Coverage, 8816,
     /* 264395 */     GIR_EraseRootFromParent_Done,
     /* 264396 */   // Label 5075: @264396
     /* 264396 */   GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(264438), // Rule ID 8818 //
     /* 264401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 264412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 264418 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 264421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264425 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1391:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FABD_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 264425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_S_UNDEF),
     /* 264428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264430 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264432 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264434 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264436 */     GIR_RootConstrainSelectedInstOperands,
     /* 264437 */     // GIR_Coverage, 8818,
     /* 264437 */     GIR_EraseRootFromParent_Done,
     /* 264438 */   // Label 5076: @264438
     /* 264438 */   GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(264480), // Rule ID 8820 //
     /* 264443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fabd_u),
     /* 264451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264460 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264467 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1391:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FABD_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 264467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD_ZPZZ_D_UNDEF),
     /* 264470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264474 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264476 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264478 */     GIR_RootConstrainSelectedInstOperands,
     /* 264479 */     // GIR_Coverage, 8820,
     /* 264479 */     GIR_EraseRootFromParent_Done,
     /* 264480 */   // Label 5077: @264480
     /* 264480 */   GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(264522), // Rule ID 8822 //
     /* 264485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 264496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 264502 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 264505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264509 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1522:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 264509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 264512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264518 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264520 */     GIR_RootConstrainSelectedInstOperands,
     /* 264521 */     // GIR_Coverage, 8822,
     /* 264521 */     GIR_EraseRootFromParent_Done,
     /* 264522 */   // Label 5078: @264522
     /* 264522 */   GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(264564), // Rule ID 8823 //
     /* 264527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 264538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 264544 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 264547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264551 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1522:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 264551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 264554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264558 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264560 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264562 */     GIR_RootConstrainSelectedInstOperands,
     /* 264563 */     // GIR_Coverage, 8823,
     /* 264563 */     GIR_EraseRootFromParent_Done,
     /* 264564 */   // Label 5079: @264564
     /* 264564 */   GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(264606), // Rule ID 8824 //
     /* 264569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 264580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 264586 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 264589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264593 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1522:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FMULX_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 264593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_H_UNDEF),
     /* 264596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264602 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264604 */     GIR_RootConstrainSelectedInstOperands,
     /* 264605 */     // GIR_Coverage, 8824,
     /* 264605 */     GIR_EraseRootFromParent_Done,
     /* 264606 */   // Label 5080: @264606
     /* 264606 */   GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(264648), // Rule ID 8825 //
     /* 264611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 264622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 264628 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 264631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264635 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1522:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMULX_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 264635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
     /* 264638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264642 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264644 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264646 */     GIR_RootConstrainSelectedInstOperands,
     /* 264647 */     // GIR_Coverage, 8825,
     /* 264647 */     GIR_EraseRootFromParent_Done,
     /* 264648 */   // Label 5081: @264648
     /* 264648 */   GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(264690), // Rule ID 8826 //
     /* 264653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 264664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 264670 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 264673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264677 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1522:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FMULX_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 264677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_S_UNDEF),
     /* 264680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264686 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264688 */     GIR_RootConstrainSelectedInstOperands,
     /* 264689 */     // GIR_Coverage, 8826,
     /* 264689 */     GIR_EraseRootFromParent_Done,
     /* 264690 */   // Label 5082: @264690
     /* 264690 */   GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(264732), // Rule ID 8827 //
     /* 264695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264698 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmulx_u),
     /* 264703 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 264706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264709 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 264712 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 264715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 264719 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1522:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMULX_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 264719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULX_ZPZZ_D_UNDEF),
     /* 264722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 264724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264726 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264728 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264730 */     GIR_RootConstrainSelectedInstOperands,
     /* 264731 */     // GIR_Coverage, 8827,
     /* 264731 */     GIR_EraseRootFromParent_Done,
     /* 264732 */   // Label 5083: @264732
     /* 264732 */   GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(264774), // Rule ID 9139 //
     /* 264737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkpb_z),
     /* 264745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 264748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 264751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 264754 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 264757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 264761 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1330:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKPB_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 264761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKPB_PPzPP),
     /* 264764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264768 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264770 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264772 */     GIR_RootConstrainSelectedInstOperands,
     /* 264773 */     // GIR_Coverage, 9139,
     /* 264773 */     GIR_EraseRootFromParent_Done,
     /* 264774 */   // Label 5084: @264774
     /* 264774 */   GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(264816), // Rule ID 9141 //
     /* 264779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_brkb),
     /* 264787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 264790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 264793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 264796 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 264799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 264803 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1326:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BRKB_PPmP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 264803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRKB_PPmP),
     /* 264806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264812 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264814 */     GIR_RootConstrainSelectedInstOperands,
     /* 264815 */     // GIR_Coverage, 9141,
     /* 264815 */     GIR_EraseRootFromParent_Done,
     /* 264816 */   // Label 5085: @264816
     /* 264816 */   GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(264858), // Rule ID 9142 //
     /* 264821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264824 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 264829 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 264832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 264835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 264838 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 264841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 264845 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1323:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 264845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 264848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264852 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264854 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264856 */     GIR_RootConstrainSelectedInstOperands,
     /* 264857 */     // GIR_Coverage, 9142,
     /* 264857 */     GIR_EraseRootFromParent_Done,
     /* 264858 */   // Label 5086: @264858
     /* 264858 */   GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(264900), // Rule ID 9143 //
     /* 264863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 264871 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 264874 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 264877 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 264880 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 264883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 264887 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1323:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 264887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 264890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264896 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264898 */     GIR_RootConstrainSelectedInstOperands,
     /* 264899 */     // GIR_Coverage, 9143,
     /* 264899 */     GIR_EraseRootFromParent_Done,
     /* 264900 */   // Label 5087: @264900
     /* 264900 */   GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(264942), // Rule ID 9144 //
     /* 264905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 264913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 264916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 264919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 264922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 264925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 264929 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1323:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 264929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 264932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264938 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264940 */     GIR_RootConstrainSelectedInstOperands,
     /* 264941 */     // GIR_Coverage, 9144,
     /* 264941 */     GIR_EraseRootFromParent_Done,
     /* 264942 */   // Label 5088: @264942
     /* 264942 */   GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(264984), // Rule ID 9145 //
     /* 264947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 264955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 264958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 264961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 264964 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 264967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 264971 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1323:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 264971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 264974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 264976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 264978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 264980 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 264982 */     GIR_RootConstrainSelectedInstOperands,
     /* 264983 */     // GIR_Coverage, 9145,
     /* 264983 */     GIR_EraseRootFromParent_Done,
     /* 264984 */   // Label 5089: @264984
     /* 264984 */   GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(265026), // Rule ID 9146 //
     /* 264989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 264992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bic_z),
     /* 264997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 265000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 265003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 265006 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 265009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265013 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1323:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (BIC_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 265013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BIC_PPzPP),
     /* 265016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265022 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265024 */     GIR_RootConstrainSelectedInstOperands,
     /* 265025 */     // GIR_Coverage, 9146,
     /* 265025 */     GIR_EraseRootFromParent_Done,
     /* 265026 */   // Label 5090: @265026
     /* 265026 */   GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(265068), // Rule ID 9167 //
     /* 265031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 265039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 265042 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265045 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 265048 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 265051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265055 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1381:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 265055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 265058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265064 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265066 */     GIR_RootConstrainSelectedInstOperands,
     /* 265067 */     // GIR_Coverage, 9167,
     /* 265067 */     GIR_EraseRootFromParent_Done,
     /* 265068 */   // Label 5091: @265068
     /* 265068 */   GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(265110), // Rule ID 9168 //
     /* 265073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 265081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 265084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 265090 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 265093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265097 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1381:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 265097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 265100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265106 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265108 */     GIR_RootConstrainSelectedInstOperands,
     /* 265109 */     // GIR_Coverage, 9168,
     /* 265109 */     GIR_EraseRootFromParent_Done,
     /* 265110 */   // Label 5092: @265110
     /* 265110 */   GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(265152), // Rule ID 9169 //
     /* 265115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 265123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 265126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 265132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 265135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265139 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1381:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 265139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 265142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265148 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265150 */     GIR_RootConstrainSelectedInstOperands,
     /* 265151 */     // GIR_Coverage, 9169,
     /* 265151 */     GIR_EraseRootFromParent_Done,
     /* 265152 */   // Label 5093: @265152
     /* 265152 */   GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(265194), // Rule ID 9170 //
     /* 265157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 265165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 265168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 265174 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 265177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265181 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1381:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 265181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 265184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265190 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265192 */     GIR_RootConstrainSelectedInstOperands,
     /* 265193 */     // GIR_Coverage, 9170,
     /* 265193 */     GIR_EraseRootFromParent_Done,
     /* 265194 */   // Label 5094: @265194
     /* 265194 */   GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(265236), // Rule ID 9171 //
     /* 265199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eor_z),
     /* 265207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 265210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 265213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 265216 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 265219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265223 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1381:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (EOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 265223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EOR_PPzPP),
     /* 265226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265232 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265234 */     GIR_RootConstrainSelectedInstOperands,
     /* 265235 */     // GIR_Coverage, 9171,
     /* 265235 */     GIR_EraseRootFromParent_Done,
     /* 265236 */   // Label 5095: @265236
     /* 265236 */   GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(265278), // Rule ID 9187 //
     /* 265241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 265249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 265252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 265258 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 265261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265265 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1672:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 265265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 265268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265274 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265276 */     GIR_RootConstrainSelectedInstOperands,
     /* 265277 */     // GIR_Coverage, 9187,
     /* 265277 */     GIR_EraseRootFromParent_Done,
     /* 265278 */   // Label 5096: @265278
     /* 265278 */   GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(265320), // Rule ID 9188 //
     /* 265283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 265291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 265294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 265300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 265303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265307 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1672:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 265307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 265310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265316 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265318 */     GIR_RootConstrainSelectedInstOperands,
     /* 265319 */     // GIR_Coverage, 9188,
     /* 265319 */     GIR_EraseRootFromParent_Done,
     /* 265320 */   // Label 5097: @265320
     /* 265320 */   GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(265362), // Rule ID 9189 //
     /* 265325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 265333 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 265336 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265339 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 265342 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 265345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265349 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1672:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 265349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 265352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265354 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265356 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265358 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265360 */     GIR_RootConstrainSelectedInstOperands,
     /* 265361 */     // GIR_Coverage, 9189,
     /* 265361 */     GIR_EraseRootFromParent_Done,
     /* 265362 */   // Label 5098: @265362
     /* 265362 */   GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(265404), // Rule ID 9190 //
     /* 265367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 265375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 265378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265381 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 265384 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 265387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265391 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1672:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 265391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 265394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265400 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265402 */     GIR_RootConstrainSelectedInstOperands,
     /* 265403 */     // GIR_Coverage, 9190,
     /* 265403 */     GIR_EraseRootFromParent_Done,
     /* 265404 */   // Label 5099: @265404
     /* 265404 */   GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(265446), // Rule ID 9191 //
     /* 265409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orr_z),
     /* 265417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 265420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 265423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 265426 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 265429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265433 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1672:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (ORR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 265433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORR_PPzPP),
     /* 265436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265442 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265444 */     GIR_RootConstrainSelectedInstOperands,
     /* 265445 */     // GIR_Coverage, 9191,
     /* 265445 */     GIR_EraseRootFromParent_Done,
     /* 265446 */   // Label 5100: @265446
     /* 265446 */   GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(265488), // Rule ID 9192 //
     /* 265451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 265459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 265462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 265468 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 265471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265475 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1668:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 265475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 265478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265484 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265486 */     GIR_RootConstrainSelectedInstOperands,
     /* 265487 */     // GIR_Coverage, 9192,
     /* 265487 */     GIR_EraseRootFromParent_Done,
     /* 265488 */   // Label 5101: @265488
     /* 265488 */   GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(265530), // Rule ID 9193 //
     /* 265493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 265501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 265504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 265510 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 265513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265517 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1668:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 265517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 265520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265526 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265528 */     GIR_RootConstrainSelectedInstOperands,
     /* 265529 */     // GIR_Coverage, 9193,
     /* 265529 */     GIR_EraseRootFromParent_Done,
     /* 265530 */   // Label 5102: @265530
     /* 265530 */   GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(265572), // Rule ID 9194 //
     /* 265535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265538 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 265543 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 265546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265549 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 265552 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 265555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265559 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1668:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 265559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 265562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265568 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265570 */     GIR_RootConstrainSelectedInstOperands,
     /* 265571 */     // GIR_Coverage, 9194,
     /* 265571 */     GIR_EraseRootFromParent_Done,
     /* 265572 */   // Label 5103: @265572
     /* 265572 */   GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(265614), // Rule ID 9195 //
     /* 265577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 265585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 265588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 265594 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 265597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265601 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1668:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 265601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 265604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265610 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265612 */     GIR_RootConstrainSelectedInstOperands,
     /* 265613 */     // GIR_Coverage, 9195,
     /* 265613 */     GIR_EraseRootFromParent_Done,
     /* 265614 */   // Label 5104: @265614
     /* 265614 */   GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(265656), // Rule ID 9196 //
     /* 265619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_orn_z),
     /* 265627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 265630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 265633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 265636 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 265639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265643 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1668:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (ORN_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 265643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ORN_PPzPP),
     /* 265646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265652 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265654 */     GIR_RootConstrainSelectedInstOperands,
     /* 265655 */     // GIR_Coverage, 9196,
     /* 265655 */     GIR_EraseRootFromParent_Done,
     /* 265656 */   // Label 5105: @265656
     /* 265656 */   GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(265698), // Rule ID 9197 //
     /* 265661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 265669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 265672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 265678 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 265681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265685 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1666:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 265685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 265688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265694 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265696 */     GIR_RootConstrainSelectedInstOperands,
     /* 265697 */     // GIR_Coverage, 9197,
     /* 265697 */     GIR_EraseRootFromParent_Done,
     /* 265698 */   // Label 5106: @265698
     /* 265698 */   GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(265740), // Rule ID 9198 //
     /* 265703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 265711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 265714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 265720 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 265723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265727 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1666:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 265727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 265730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265736 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265738 */     GIR_RootConstrainSelectedInstOperands,
     /* 265739 */     // GIR_Coverage, 9198,
     /* 265739 */     GIR_EraseRootFromParent_Done,
     /* 265740 */   // Label 5107: @265740
     /* 265740 */   GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(265782), // Rule ID 9199 //
     /* 265745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 265753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 265756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 265762 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 265765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265769 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1666:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 265769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 265772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265778 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265780 */     GIR_RootConstrainSelectedInstOperands,
     /* 265781 */     // GIR_Coverage, 9199,
     /* 265781 */     GIR_EraseRootFromParent_Done,
     /* 265782 */   // Label 5108: @265782
     /* 265782 */   GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(265824), // Rule ID 9200 //
     /* 265787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 265795 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 265798 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 265801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 265804 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 265807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265811 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1666:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 265811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 265814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265820 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265822 */     GIR_RootConstrainSelectedInstOperands,
     /* 265823 */     // GIR_Coverage, 9200,
     /* 265823 */     GIR_EraseRootFromParent_Done,
     /* 265824 */   // Label 5109: @265824
     /* 265824 */   GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(265866), // Rule ID 9201 //
     /* 265829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nor_z),
     /* 265837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 265840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 265843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 265846 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 265849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265853 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1666:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (NOR_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 265853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NOR_PPzPP),
     /* 265856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265862 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265864 */     GIR_RootConstrainSelectedInstOperands,
     /* 265865 */     // GIR_Coverage, 9201,
     /* 265865 */     GIR_EraseRootFromParent_Done,
     /* 265866 */   // Label 5110: @265866
     /* 265866 */   GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(265908), // Rule ID 9202 //
     /* 265871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 265879 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 265882 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 265885 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 265888 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s1,
     /* 265891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265895 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1662:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 265895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 265898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265904 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265906 */     GIR_RootConstrainSelectedInstOperands,
     /* 265907 */     // GIR_Coverage, 9202,
     /* 265907 */     GIR_EraseRootFromParent_Done,
     /* 265908 */   // Label 5111: @265908
     /* 265908 */   GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(265950), // Rule ID 9203 //
     /* 265913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 265921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 265924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 265927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 265930 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s1,
     /* 265933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265937 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1662:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 265937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 265940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265946 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265948 */     GIR_RootConstrainSelectedInstOperands,
     /* 265949 */     // GIR_Coverage, 9203,
     /* 265949 */     GIR_EraseRootFromParent_Done,
     /* 265950 */   // Label 5112: @265950
     /* 265950 */   GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(265992), // Rule ID 9204 //
     /* 265955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 265958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 265963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 265966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 265969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 265972 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s1,
     /* 265975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 265979 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1662:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 265979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 265982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 265984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 265986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 265988 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 265990 */     GIR_RootConstrainSelectedInstOperands,
     /* 265991 */     // GIR_Coverage, 9204,
     /* 265991 */     GIR_EraseRootFromParent_Done,
     /* 265992 */   // Label 5113: @265992
     /* 265992 */   GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(266034), // Rule ID 9205 //
     /* 265997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 266005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 266008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 266014 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s1,
     /* 266017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 266021 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1662:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 266021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 266024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266030 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266032 */     GIR_RootConstrainSelectedInstOperands,
     /* 266033 */     // GIR_Coverage, 9205,
     /* 266033 */     GIR_EraseRootFromParent_Done,
     /* 266034 */   // Label 5114: @266034
     /* 266034 */   GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(266076), // Rule ID 9206 //
     /* 266039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nand_z),
     /* 266047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv1s1,
     /* 266050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 266053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 266056 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv1s1,
     /* 266059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 266063 */     // (intrinsic_wo_chain:{ *:[nxv1i1] } 1662:{ *:[iPTR] }, nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (NAND_PPzPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 266063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NAND_PPzPP),
     /* 266066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266072 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266074 */     GIR_RootConstrainSelectedInstOperands,
     /* 266075 */     // GIR_Coverage, 9206,
     /* 266075 */     GIR_EraseRootFromParent_Done,
     /* 266076 */   // Label 5115: @266076
     /* 266076 */   GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(266118), // Rule ID 9214 //
     /* 266081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 266092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266098 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 266101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266105 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1339:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (CLASTB_ZPZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 266105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_B),
     /* 266108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266114 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266116 */     GIR_RootConstrainSelectedInstOperands,
     /* 266117 */     // GIR_Coverage, 9214,
     /* 266117 */     GIR_EraseRootFromParent_Done,
     /* 266118 */   // Label 5116: @266118
     /* 266118 */   GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(266160), // Rule ID 9215 //
     /* 266123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266140 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266147 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1339:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (CLASTB_ZPZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 266147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
     /* 266150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266156 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266158 */     GIR_RootConstrainSelectedInstOperands,
     /* 266159 */     // GIR_Coverage, 9215,
     /* 266159 */     GIR_EraseRootFromParent_Done,
     /* 266160 */   // Label 5117: @266160
     /* 266160 */   GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(266202), // Rule ID 9216 //
     /* 266165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266179 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266182 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266189 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1339:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (CLASTB_ZPZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 266189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
     /* 266192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266198 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266200 */     GIR_RootConstrainSelectedInstOperands,
     /* 266201 */     // GIR_Coverage, 9216,
     /* 266201 */     GIR_EraseRootFromParent_Done,
     /* 266202 */   // Label 5118: @266202
     /* 266202 */   GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(266244), // Rule ID 9217 //
     /* 266207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266224 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266231 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1339:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CLASTB_ZPZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
     /* 266234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266240 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266242 */     GIR_RootConstrainSelectedInstOperands,
     /* 266243 */     // GIR_Coverage, 9217,
     /* 266243 */     GIR_EraseRootFromParent_Done,
     /* 266244 */   // Label 5119: @266244
     /* 266244 */   GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(266286), // Rule ID 9218 //
     /* 266249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 266260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266266 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 266269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266273 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1339:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (CLASTB_ZPZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 266273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_H),
     /* 266276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266282 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266284 */     GIR_RootConstrainSelectedInstOperands,
     /* 266285 */     // GIR_Coverage, 9218,
     /* 266285 */     GIR_EraseRootFromParent_Done,
     /* 266286 */   // Label 5120: @266286
     /* 266286 */   GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(266328), // Rule ID 9219 //
     /* 266291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266294 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266299 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 266302 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266305 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266308 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 266311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266315 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1339:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (CLASTB_ZPZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 266315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_S),
     /* 266318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266320 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266322 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266324 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266326 */     GIR_RootConstrainSelectedInstOperands,
     /* 266327 */     // GIR_Coverage, 9219,
     /* 266327 */     GIR_EraseRootFromParent_Done,
     /* 266328 */   // Label 5121: @266328
     /* 266328 */   GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(266370), // Rule ID 9220 //
     /* 266333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_clastb),
     /* 266341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 266344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 266347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 266350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 266357 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1339:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (CLASTB_ZPZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 266357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLASTB_ZPZ_D),
     /* 266360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 266362 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266364 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266366 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266368 */     GIR_RootConstrainSelectedInstOperands,
     /* 266369 */     // GIR_Coverage, 9220,
     /* 266369 */     GIR_EraseRootFromParent_Done,
     /* 266370 */   // Label 5122: @266370
     /* 266370 */   GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(266415), // Rule ID 9926 //
     /* 266375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 266383 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 266386 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266389 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266392 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266395 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266399 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1360:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_B),
     /* 266402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266404 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266406 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266408 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266410 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266413 */     GIR_RootConstrainSelectedInstOperands,
     /* 266414 */     // GIR_Coverage, 9926,
     /* 266414 */     GIR_EraseRootFromParent_Done,
     /* 266415 */   // Label 5123: @266415
     /* 266415 */   GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(266460), // Rule ID 9927 //
     /* 266420 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266423 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 266428 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 266431 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266434 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266437 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266440 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266444 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1360:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_H),
     /* 266447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266449 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266451 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266453 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266455 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266458 */     GIR_RootConstrainSelectedInstOperands,
     /* 266459 */     // GIR_Coverage, 9927,
     /* 266459 */     GIR_EraseRootFromParent_Done,
     /* 266460 */   // Label 5124: @266460
     /* 266460 */   GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(266505), // Rule ID 9928 //
     /* 266465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpne_wide),
     /* 266473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 266476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266489 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1360:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPNE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPNE_WIDE_PPzZZ_S),
     /* 266492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266498 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266500 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266503 */     GIR_RootConstrainSelectedInstOperands,
     /* 266504 */     // GIR_Coverage, 9928,
     /* 266504 */     GIR_EraseRootFromParent_Done,
     /* 266505 */   // Label 5125: @266505
     /* 266505 */   GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(266550), // Rule ID 9929 //
     /* 266510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266513 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 266518 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 266521 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266524 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266527 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266530 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266534 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1350:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_B),
     /* 266537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266539 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266541 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266543 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266545 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266548 */     GIR_RootConstrainSelectedInstOperands,
     /* 266549 */     // GIR_Coverage, 9929,
     /* 266549 */     GIR_EraseRootFromParent_Done,
     /* 266550 */   // Label 5126: @266550
     /* 266550 */   GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(266595), // Rule ID 9930 //
     /* 266555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 266563 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 266566 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266569 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266572 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266579 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1350:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_H),
     /* 266582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266588 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266590 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266593 */     GIR_RootConstrainSelectedInstOperands,
     /* 266594 */     // GIR_Coverage, 9930,
     /* 266594 */     GIR_EraseRootFromParent_Done,
     /* 266595 */   // Label 5127: @266595
     /* 266595 */   GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(266640), // Rule ID 9931 //
     /* 266600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpgt_wide),
     /* 266608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 266611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266624 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1350:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPGT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPGT_WIDE_PPzZZ_S),
     /* 266627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266629 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266631 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266633 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266635 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266638 */     GIR_RootConstrainSelectedInstOperands,
     /* 266639 */     // GIR_Coverage, 9931,
     /* 266639 */     GIR_EraseRootFromParent_Done,
     /* 266640 */   // Label 5128: @266640
     /* 266640 */   GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(266685), // Rule ID 9932 //
     /* 266645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 266653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 266656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266662 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266669 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1358:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_B),
     /* 266672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266676 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266678 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266680 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266683 */     GIR_RootConstrainSelectedInstOperands,
     /* 266684 */     // GIR_Coverage, 9932,
     /* 266684 */     GIR_EraseRootFromParent_Done,
     /* 266685 */   // Label 5129: @266685
     /* 266685 */   GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(266730), // Rule ID 9933 //
     /* 266690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266693 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 266698 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 266701 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266704 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266707 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266714 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1358:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_H),
     /* 266717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266719 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266721 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266723 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266725 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266728 */     GIR_RootConstrainSelectedInstOperands,
     /* 266729 */     // GIR_Coverage, 9933,
     /* 266729 */     GIR_EraseRootFromParent_Done,
     /* 266730 */   // Label 5130: @266730
     /* 266730 */   GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(266775), // Rule ID 9934 //
     /* 266735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266738 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplt_wide),
     /* 266743 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 266746 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266752 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266759 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1358:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLT_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLT_WIDE_PPzZZ_S),
     /* 266762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266764 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266768 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266770 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266773 */     GIR_RootConstrainSelectedInstOperands,
     /* 266774 */     // GIR_Coverage, 9934,
     /* 266774 */     GIR_EraseRootFromParent_Done,
     /* 266775 */   // Label 5131: @266775
     /* 266775 */   GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(266820), // Rule ID 9935 //
     /* 266780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 266788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 266791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266797 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266804 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1355:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_B),
     /* 266807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266809 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266811 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266813 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266815 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266818 */     GIR_RootConstrainSelectedInstOperands,
     /* 266819 */     // GIR_Coverage, 9935,
     /* 266819 */     GIR_EraseRootFromParent_Done,
     /* 266820 */   // Label 5132: @266820
     /* 266820 */   GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(266865), // Rule ID 9936 //
     /* 266825 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 266833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 266836 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266839 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266842 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266845 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266849 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1355:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_H),
     /* 266852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266854 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266856 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266858 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266860 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266863 */     GIR_RootConstrainSelectedInstOperands,
     /* 266864 */     // GIR_Coverage, 9936,
     /* 266864 */     GIR_EraseRootFromParent_Done,
     /* 266865 */   // Label 5133: @266865
     /* 266865 */   GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(266910), // Rule ID 9937 //
     /* 266870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266873 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmple_wide),
     /* 266878 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 266881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 266884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 266887 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266894 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1355:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLE_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLE_WIDE_PPzZZ_S),
     /* 266897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266903 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266905 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266908 */     GIR_RootConstrainSelectedInstOperands,
     /* 266909 */     // GIR_Coverage, 9937,
     /* 266909 */     GIR_EraseRootFromParent_Done,
     /* 266910 */   // Label 5134: @266910
     /* 266910 */   GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(266955), // Rule ID 9938 //
     /* 266915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 266923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 266926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 266929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 266932 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266939 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1354:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_B),
     /* 266942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266948 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266950 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266953 */     GIR_RootConstrainSelectedInstOperands,
     /* 266954 */     // GIR_Coverage, 9938,
     /* 266954 */     GIR_EraseRootFromParent_Done,
     /* 266955 */   // Label 5135: @266955
     /* 266955 */   GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(267000), // Rule ID 9939 //
     /* 266960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 266963 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 266968 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 266971 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 266974 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 266977 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 266980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 266984 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1354:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 266984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_H),
     /* 266987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 266989 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 266991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 266993 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 266995 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 266998 */     GIR_RootConstrainSelectedInstOperands,
     /* 266999 */     // GIR_Coverage, 9939,
     /* 266999 */     GIR_EraseRootFromParent_Done,
     /* 267000 */   // Label 5136: @267000
     /* 267000 */   GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(267045), // Rule ID 9940 //
     /* 267005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphs_wide),
     /* 267013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 267016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267022 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267029 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1354:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHS_WIDE_PPzZZ_S),
     /* 267032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267036 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267038 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267040 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267043 */     GIR_RootConstrainSelectedInstOperands,
     /* 267044 */     // GIR_Coverage, 9940,
     /* 267044 */     GIR_EraseRootFromParent_Done,
     /* 267045 */   // Label 5137: @267045
     /* 267045 */   GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(267090), // Rule ID 9941 //
     /* 267050 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267053 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 267058 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 267061 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267064 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267067 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267070 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267074 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1352:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_B),
     /* 267077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267079 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267081 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267083 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267085 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267088 */     GIR_RootConstrainSelectedInstOperands,
     /* 267089 */     // GIR_Coverage, 9941,
     /* 267089 */     GIR_EraseRootFromParent_Done,
     /* 267090 */   // Label 5138: @267090
     /* 267090 */   GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(267135), // Rule ID 9942 //
     /* 267095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267098 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 267103 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 267106 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267109 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267112 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267119 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1352:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_H),
     /* 267122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267124 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267128 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267130 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267133 */     GIR_RootConstrainSelectedInstOperands,
     /* 267134 */     // GIR_Coverage, 9942,
     /* 267134 */     GIR_EraseRootFromParent_Done,
     /* 267135 */   // Label 5139: @267135
     /* 267135 */   GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(267180), // Rule ID 9943 //
     /* 267140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267143 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmphi_wide),
     /* 267148 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 267151 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267154 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267157 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267164 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1352:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPHI_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPHI_WIDE_PPzZZ_S),
     /* 267167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267175 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267178 */     GIR_RootConstrainSelectedInstOperands,
     /* 267179 */     // GIR_Coverage, 9943,
     /* 267179 */     GIR_EraseRootFromParent_Done,
     /* 267180 */   // Label 5140: @267180
     /* 267180 */   GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(267225), // Rule ID 9944 //
     /* 267185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 267193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 267196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267199 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267202 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267209 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1356:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_B),
     /* 267212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267218 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267220 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267223 */     GIR_RootConstrainSelectedInstOperands,
     /* 267224 */     // GIR_Coverage, 9944,
     /* 267224 */     GIR_EraseRootFromParent_Done,
     /* 267225 */   // Label 5141: @267225
     /* 267225 */   GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(267270), // Rule ID 9945 //
     /* 267230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 267238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 267241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267254 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1356:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_H),
     /* 267257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267259 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267261 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267263 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267265 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267268 */     GIR_RootConstrainSelectedInstOperands,
     /* 267269 */     // GIR_Coverage, 9945,
     /* 267269 */     GIR_EraseRootFromParent_Done,
     /* 267270 */   // Label 5142: @267270
     /* 267270 */   GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(267315), // Rule ID 9946 //
     /* 267275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmplo_wide),
     /* 267283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 267286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267299 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1356:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLO_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLO_WIDE_PPzZZ_S),
     /* 267302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267308 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267310 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267313 */     GIR_RootConstrainSelectedInstOperands,
     /* 267314 */     // GIR_Coverage, 9946,
     /* 267314 */     GIR_EraseRootFromParent_Done,
     /* 267315 */   // Label 5143: @267315
     /* 267315 */   GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(267360), // Rule ID 9947 //
     /* 267320 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267323 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 267328 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 267331 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267334 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267337 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267344 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1357:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267344 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_B),
     /* 267347 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267349 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267351 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267353 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267355 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267358 */     GIR_RootConstrainSelectedInstOperands,
     /* 267359 */     // GIR_Coverage, 9947,
     /* 267359 */     GIR_EraseRootFromParent_Done,
     /* 267360 */   // Label 5144: @267360
     /* 267360 */   GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(267405), // Rule ID 9948 //
     /* 267365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267368 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 267373 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 267376 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267379 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267382 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267385 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267389 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1357:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_H),
     /* 267392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267394 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267396 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267398 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267400 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267403 */     GIR_RootConstrainSelectedInstOperands,
     /* 267404 */     // GIR_Coverage, 9948,
     /* 267404 */     GIR_EraseRootFromParent_Done,
     /* 267405 */   // Label 5145: @267405
     /* 267405 */   GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(267450), // Rule ID 9949 //
     /* 267410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_cmpls_wide),
     /* 267418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 267421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267424 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267427 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267430 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267434 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1357:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (CMPLS_WIDE_PPzZZ_S:{ *:[nxv4i1] }:{ *:[i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267434 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMPLS_WIDE_PPzZZ_S),
     /* 267437 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267439 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267441 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267443 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267445 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 267448 */     GIR_RootConstrainSelectedInstOperands,
     /* 267449 */     // GIR_Coverage, 9949,
     /* 267449 */     GIR_EraseRootFromParent_Done,
     /* 267450 */   // Label 5146: @267450
     /* 267450 */   GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(267492), // Rule ID 10346 //
     /* 267455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267458 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 267463 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 267466 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267469 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267472 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 267475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267479 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1394:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FACGT_PPzZZ_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 267479 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_H),
     /* 267482 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267484 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267488 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267490 */     GIR_RootConstrainSelectedInstOperands,
     /* 267491 */     // GIR_Coverage, 10346,
     /* 267491 */     GIR_EraseRootFromParent_Done,
     /* 267492 */   // Label 5147: @267492
     /* 267492 */   GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(267534), // Rule ID 10347 //
     /* 267497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 267505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s1,
     /* 267508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267514 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267521 */     // (intrinsic_wo_chain:{ *:[nxv4i1] } 1394:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FACGT_PPzZZ_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 267521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_S),
     /* 267524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267528 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267530 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267532 */     GIR_RootConstrainSelectedInstOperands,
     /* 267533 */     // GIR_Coverage, 10347,
     /* 267533 */     GIR_EraseRootFromParent_Done,
     /* 267534 */   // Label 5148: @267534
     /* 267534 */   GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(267576), // Rule ID 10348 //
     /* 267539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267542 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_facgt),
     /* 267547 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s1,
     /* 267550 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267553 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267556 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 267563 */     // (intrinsic_wo_chain:{ *:[nxv2i1] } 1394:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FACGT_PPzZZ_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 267563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGT_PPzZZ_D),
     /* 267566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 267568 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267570 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267572 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267574 */     GIR_RootConstrainSelectedInstOperands,
     /* 267575 */     // GIR_Coverage, 10348,
     /* 267575 */     GIR_EraseRootFromParent_Done,
     /* 267576 */   // Label 5149: @267576
     /* 267576 */   GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(267618), // Rule ID 10886 //
     /* 267581 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267584 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 267589 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 267592 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267595 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267598 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 267601 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267605 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1644:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (LSR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 267605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_B),
     /* 267608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267610 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267612 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267614 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267616 */     GIR_RootConstrainSelectedInstOperands,
     /* 267617 */     // GIR_Coverage, 10886,
     /* 267617 */     GIR_EraseRootFromParent_Done,
     /* 267618 */   // Label 5150: @267618
     /* 267618 */   GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(267660), // Rule ID 10887 //
     /* 267623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 267631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 267634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 267643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267647 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1644:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (LSR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 267647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_H),
     /* 267650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267656 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267658 */     GIR_RootConstrainSelectedInstOperands,
     /* 267659 */     // GIR_Coverage, 10887,
     /* 267659 */     GIR_EraseRootFromParent_Done,
     /* 267660 */   // Label 5151: @267660
     /* 267660 */   GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(267702), // Rule ID 10888 //
     /* 267665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267668 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 267673 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 267676 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267679 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267682 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267685 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267689 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1644:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (LSR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 267689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_S),
     /* 267692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267694 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267696 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267698 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267700 */     GIR_RootConstrainSelectedInstOperands,
     /* 267701 */     // GIR_Coverage, 10888,
     /* 267701 */     GIR_EraseRootFromParent_Done,
     /* 267702 */   // Label 5152: @267702
     /* 267702 */   GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(267744), // Rule ID 10889 //
     /* 267707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr),
     /* 267715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 267718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267724 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267731 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1644:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_ZPmZ_D),
     /* 267734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267736 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267738 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267740 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267742 */     GIR_RootConstrainSelectedInstOperands,
     /* 267743 */     // GIR_Coverage, 10889,
     /* 267743 */     GIR_EraseRootFromParent_Done,
     /* 267744 */   // Label 5153: @267744
     /* 267744 */   GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(267786), // Rule ID 10890 //
     /* 267749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 267757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 267760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267766 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 267769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267773 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1641:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (LSL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 267773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_B),
     /* 267776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267778 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267780 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267782 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267784 */     GIR_RootConstrainSelectedInstOperands,
     /* 267785 */     // GIR_Coverage, 10890,
     /* 267785 */     GIR_EraseRootFromParent_Done,
     /* 267786 */   // Label 5154: @267786
     /* 267786 */   GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(267828), // Rule ID 10891 //
     /* 267791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267794 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 267799 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 267802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 267811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267815 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1641:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (LSL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 267815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_H),
     /* 267818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267820 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267822 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267824 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267826 */     GIR_RootConstrainSelectedInstOperands,
     /* 267827 */     // GIR_Coverage, 10891,
     /* 267827 */     GIR_EraseRootFromParent_Done,
     /* 267828 */   // Label 5155: @267828
     /* 267828 */   GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(267870), // Rule ID 10892 //
     /* 267833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 267841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 267844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 267847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 267850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 267853 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267857 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1641:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (LSL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 267857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_S),
     /* 267860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267862 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267864 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267866 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267868 */     GIR_RootConstrainSelectedInstOperands,
     /* 267869 */     // GIR_Coverage, 10892,
     /* 267869 */     GIR_EraseRootFromParent_Done,
     /* 267870 */   // Label 5156: @267870
     /* 267870 */   GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(267912), // Rule ID 10893 //
     /* 267875 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267878 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl),
     /* 267883 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 267886 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 267889 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 267892 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267895 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267899 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1641:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_ZPmZ_D),
     /* 267902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267904 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267908 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267910 */     GIR_RootConstrainSelectedInstOperands,
     /* 267911 */     // GIR_Coverage, 10893,
     /* 267911 */     GIR_EraseRootFromParent_Done,
     /* 267912 */   // Label 5157: @267912
     /* 267912 */   GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(267954), // Rule ID 10906 //
     /* 267917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 267925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 267928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 267931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 267934 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267941 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1646:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_B),
     /* 267944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267952 */     GIR_RootConstrainSelectedInstOperands,
     /* 267953 */     // GIR_Coverage, 10906,
     /* 267953 */     GIR_EraseRootFromParent_Done,
     /* 267954 */   // Label 5158: @267954
     /* 267954 */   GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(267996), // Rule ID 10907 //
     /* 267959 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 267962 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 267967 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 267970 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 267973 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 267976 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 267979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 267983 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1646:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 267983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_H),
     /* 267986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 267988 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 267990 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 267992 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 267994 */     GIR_RootConstrainSelectedInstOperands,
     /* 267995 */     // GIR_Coverage, 10907,
     /* 267995 */     GIR_EraseRootFromParent_Done,
     /* 267996 */   // Label 5159: @267996
     /* 267996 */   GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(268038), // Rule ID 10908 //
     /* 268001 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268004 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsr_wide),
     /* 268009 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268012 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 268015 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 268018 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268025 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1646:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSR_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSR_WIDE_ZPmZ_S),
     /* 268028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 268030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268032 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268034 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268036 */     GIR_RootConstrainSelectedInstOperands,
     /* 268037 */     // GIR_Coverage, 10908,
     /* 268037 */     GIR_EraseRootFromParent_Done,
     /* 268038 */   // Label 5160: @268038
     /* 268038 */   GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(268080), // Rule ID 10909 //
     /* 268043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268046 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 268051 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 268054 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 268057 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 268060 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268063 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268067 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1643:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_B),
     /* 268070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 268072 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268076 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268078 */     GIR_RootConstrainSelectedInstOperands,
     /* 268079 */     // GIR_Coverage, 10909,
     /* 268079 */     GIR_EraseRootFromParent_Done,
     /* 268080 */   // Label 5161: @268080
     /* 268080 */   GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(268122), // Rule ID 10910 //
     /* 268085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 268093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 268099 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 268102 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268109 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1643:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_H),
     /* 268112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 268114 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268116 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268118 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268120 */     GIR_RootConstrainSelectedInstOperands,
     /* 268121 */     // GIR_Coverage, 10910,
     /* 268121 */     GIR_EraseRootFromParent_Done,
     /* 268122 */   // Label 5162: @268122
     /* 268122 */   GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(268164), // Rule ID 10911 //
     /* 268127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_lsl_wide),
     /* 268135 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 268141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 268144 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268147 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268151 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1643:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (LSL_WIDE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSL_WIDE_ZPmZ_S),
     /* 268154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 268156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268158 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268160 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268162 */     GIR_RootConstrainSelectedInstOperands,
     /* 268163 */     // GIR_Coverage, 10911,
     /* 268163 */     GIR_EraseRootFromParent_Done,
     /* 268164 */   // Label 5163: @268164
     /* 268164 */   GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(268206), // Rule ID 10938 //
     /* 268169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f16f64),
     /* 268177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 268183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268186 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268193 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1419:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVT_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 268193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoH),
     /* 268196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268198 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268200 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268202 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268204 */     GIR_RootConstrainSelectedInstOperands,
     /* 268205 */     // GIR_Coverage, 10938,
     /* 268205 */     GIR_EraseRootFromParent_Done,
     /* 268206 */   // Label 5164: @268206
     /* 268206 */   GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(268248), // Rule ID 10942 //
     /* 268211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f16),
     /* 268219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268225 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268228 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 268231 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268235 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1422:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVT_ZPmZ_HtoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 268235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_HtoD),
     /* 268238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268242 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268244 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268246 */     GIR_RootConstrainSelectedInstOperands,
     /* 268247 */     // GIR_Coverage, 10942,
     /* 268247 */     GIR_EraseRootFromParent_Done,
     /* 268248 */   // Label 5165: @268248
     /* 268248 */   GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(268290), // Rule ID 10946 //
     /* 268253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f32f64),
     /* 268261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268270 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268273 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268277 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1421:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVT_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 268277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_DtoS),
     /* 268280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268282 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268284 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268286 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268288 */     GIR_RootConstrainSelectedInstOperands,
     /* 268289 */     // GIR_Coverage, 10946,
     /* 268289 */     GIR_EraseRootFromParent_Done,
     /* 268290 */   // Label 5166: @268290
     /* 268290 */   GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(268332), // Rule ID 10950 //
     /* 268295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268298 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvt_f64f32),
     /* 268303 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268306 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268309 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268312 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268319 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1423:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVT_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 268319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVT_ZPmZ_StoD),
     /* 268322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268328 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268330 */     GIR_RootConstrainSelectedInstOperands,
     /* 268331 */     // GIR_Coverage, 10950,
     /* 268331 */     GIR_EraseRootFromParent_Done,
     /* 268332 */   // Label 5167: @268332
     /* 268332 */   GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(268374), // Rule ID 10954 //
     /* 268337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f64i32),
     /* 268345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268354 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268361 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1755:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 268361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoD),
     /* 268364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268368 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268370 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268372 */     GIR_RootConstrainSelectedInstOperands,
     /* 268373 */     // GIR_Coverage, 10954,
     /* 268373 */     GIR_EraseRootFromParent_Done,
     /* 268374 */   // Label 5168: @268374
     /* 268374 */   GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(268416), // Rule ID 10955 //
     /* 268379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268382 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f64i32),
     /* 268387 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268390 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268393 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268396 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268399 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268403 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 2006:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCVTF_ZPmZ_StoD:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 268403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoD),
     /* 268406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268412 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268414 */     GIR_RootConstrainSelectedInstOperands,
     /* 268415 */     // GIR_Coverage, 10955,
     /* 268415 */     GIR_EraseRootFromParent_Done,
     /* 268416 */   // Label 5169: @268416
     /* 268416 */   GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(268458), // Rule ID 10956 //
     /* 268421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268424 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i32),
     /* 268429 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268432 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 268435 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 268438 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268445 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2003:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 268445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_StoH),
     /* 268448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268454 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268456 */     GIR_RootConstrainSelectedInstOperands,
     /* 268457 */     // GIR_Coverage, 10956,
     /* 268457 */     GIR_EraseRootFromParent_Done,
     /* 268458 */   // Label 5170: @268458
     /* 268458 */   GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(268500), // Rule ID 10960 //
     /* 268463 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f32i64),
     /* 268471 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268474 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268477 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268480 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268487 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1754:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoS),
     /* 268490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268492 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268494 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268496 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268498 */     GIR_RootConstrainSelectedInstOperands,
     /* 268499 */     // GIR_Coverage, 10960,
     /* 268499 */     GIR_EraseRootFromParent_Done,
     /* 268500 */   // Label 5171: @268500
     /* 268500 */   GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(268542), // Rule ID 10964 //
     /* 268505 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268508 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i32),
     /* 268513 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268516 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 268519 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 268522 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268525 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268529 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1752:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SCVTF_ZPmZ_StoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 268529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_StoH),
     /* 268532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268536 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268538 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268540 */     GIR_RootConstrainSelectedInstOperands,
     /* 268541 */     // GIR_Coverage, 10964,
     /* 268541 */     GIR_EraseRootFromParent_Done,
     /* 268542 */   // Label 5172: @268542
     /* 268542 */   GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(268584), // Rule ID 10968 //
     /* 268547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268550 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_scvtf_f16i64),
     /* 268555 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268558 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 268561 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268564 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268571 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1753:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTF_ZPmZ_DtoH),
     /* 268574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268576 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268578 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268580 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268582 */     GIR_RootConstrainSelectedInstOperands,
     /* 268583 */     // GIR_Coverage, 10968,
     /* 268583 */     GIR_EraseRootFromParent_Done,
     /* 268584 */   // Label 5173: @268584
     /* 268584 */   GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(268626), // Rule ID 10972 //
     /* 268589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f32i64),
     /* 268597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268606 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268613 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 2005:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCVTF_ZPmZ_DtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoS),
     /* 268616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268618 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268622 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268624 */     GIR_RootConstrainSelectedInstOperands,
     /* 268625 */     // GIR_Coverage, 10972,
     /* 268625 */     GIR_EraseRootFromParent_Done,
     /* 268626 */   // Label 5174: @268626
     /* 268626 */   GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(268668), // Rule ID 10976 //
     /* 268631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ucvtf_f16i64),
     /* 268639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 268642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 268645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268648 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268651 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268655 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 2004:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCVTF_ZPmZ_DtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 268655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTF_ZPmZ_DtoH),
     /* 268658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268664 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268666 */     GIR_RootConstrainSelectedInstOperands,
     /* 268667 */     // GIR_Coverage, 10976,
     /* 268667 */     GIR_EraseRootFromParent_Done,
     /* 268668 */   // Label 5175: @268668
     /* 268668 */   GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(268710), // Rule ID 10986 //
     /* 268673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268676 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f64),
     /* 268681 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268684 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268687 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268690 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268693 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268697 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1441:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTZS_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 268697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_DtoS),
     /* 268700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268702 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268706 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268708 */     GIR_RootConstrainSelectedInstOperands,
     /* 268709 */     // GIR_Coverage, 10986,
     /* 268709 */     GIR_EraseRootFromParent_Done,
     /* 268710 */   // Label 5176: @268710
     /* 268710 */   GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(268752), // Rule ID 10987 //
     /* 268715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f64),
     /* 268723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268732 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 268735 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268739 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1448:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FCVTZU_ZPmZ_DtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 268739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_DtoS),
     /* 268742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268748 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268750 */     GIR_RootConstrainSelectedInstOperands,
     /* 268751 */     // GIR_Coverage, 10987,
     /* 268751 */     GIR_EraseRootFromParent_Done,
     /* 268752 */   // Label 5177: @268752
     /* 268752 */   GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(268794), // Rule ID 10988 //
     /* 268757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f32),
     /* 268765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268774 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268781 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1443:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTZS_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 268781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_StoD),
     /* 268784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268786 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268788 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268790 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268792 */     GIR_RootConstrainSelectedInstOperands,
     /* 268793 */     // GIR_Coverage, 10988,
     /* 268793 */     GIR_EraseRootFromParent_Done,
     /* 268794 */   // Label 5178: @268794
     /* 268794 */   GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(268836), // Rule ID 10992 //
     /* 268799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i32f16),
     /* 268807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268810 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 268816 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 268819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268823 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1440:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZS_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 268823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoS),
     /* 268826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268828 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268830 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268832 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268834 */     GIR_RootConstrainSelectedInstOperands,
     /* 268835 */     // GIR_Coverage, 10992,
     /* 268835 */     GIR_EraseRootFromParent_Done,
     /* 268836 */   // Label 5179: @268836
     /* 268836 */   GIM_Try, /*On fail goto*//*Label 5180*/ GIMT_Encode4(268878), // Rule ID 10996 //
     /* 268841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzs_i64f16),
     /* 268849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268858 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 268861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268865 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1442:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZS_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 268865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZS_ZPmZ_HtoD),
     /* 268868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268870 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268874 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268876 */     GIR_RootConstrainSelectedInstOperands,
     /* 268877 */     // GIR_Coverage, 10996,
     /* 268877 */     GIR_EraseRootFromParent_Done,
     /* 268878 */   // Label 5180: @268878
     /* 268878 */   GIM_Try, /*On fail goto*//*Label 5181*/ GIMT_Encode4(268920), // Rule ID 11000 //
     /* 268883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i32f16),
     /* 268891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 268894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 268897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 268900 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 268903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268907 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1447:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZU_ZPmZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 268907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoS),
     /* 268910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268916 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268918 */     GIR_RootConstrainSelectedInstOperands,
     /* 268919 */     // GIR_Coverage, 11000,
     /* 268919 */     GIR_EraseRootFromParent_Done,
     /* 268920 */   // Label 5181: @268920
     /* 268920 */   GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(268962), // Rule ID 11004 //
     /* 268925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268928 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f16),
     /* 268933 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268939 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268942 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 268945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268949 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1449:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FCVTZU_ZPmZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 268949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_HtoD),
     /* 268952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268954 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268956 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 268958 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 268960 */     GIR_RootConstrainSelectedInstOperands,
     /* 268961 */     // GIR_Coverage, 11004,
     /* 268961 */     GIR_EraseRootFromParent_Done,
     /* 268962 */   // Label 5182: @268962
     /* 268962 */   GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(269004), // Rule ID 11008 //
     /* 268967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 268970 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fcvtzu_i64f32),
     /* 268975 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 268978 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 268981 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 268984 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 268987 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 268991 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1450:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FCVTZU_ZPmZ_StoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 268991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZU_ZPmZ_StoD),
     /* 268994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 268996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 268998 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269000 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269002 */     GIR_RootConstrainSelectedInstOperands,
     /* 269003 */     // GIR_Coverage, 11008,
     /* 269003 */     GIR_EraseRootFromParent_Done,
     /* 269004 */   // Label 5183: @269004
     /* 269004 */   GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(269046), // Rule ID 12053 //
     /* 269009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 269012 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ummla),
     /* 269017 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269026 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269029 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269033 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2046:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMMLA_ZZZ),
     /* 269036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269038 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269040 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269042 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269044 */     GIR_RootConstrainSelectedInstOperands,
     /* 269045 */     // GIR_Coverage, 12053,
     /* 269045 */     GIR_EraseRootFromParent_Done,
     /* 269046 */   // Label 5184: @269046
     /* 269046 */   GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(269088), // Rule ID 12054 //
     /* 269051 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE),
     /* 269054 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usmmla),
     /* 269059 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269062 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269065 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269068 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269075 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2120:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (USMMLA_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMMLA_ZZZ),
     /* 269078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269084 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269086 */     GIR_RootConstrainSelectedInstOperands,
     /* 269087 */     // GIR_Coverage, 12054,
     /* 269087 */     GIR_EraseRootFromParent_Done,
     /* 269088 */   // Label 5185: @269088
     /* 269088 */   GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(269130), // Rule ID 12057 //
     /* 269093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP32_HasSVE),
     /* 269096 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
     /* 269101 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269107 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269110 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269113 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269117 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1512:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMMLA_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 269117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_S),
     /* 269120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269126 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269128 */     GIR_RootConstrainSelectedInstOperands,
     /* 269129 */     // GIR_Coverage, 12057,
     /* 269129 */     GIR_EraseRootFromParent_Done,
     /* 269130 */   // Label 5186: @269130
     /* 269130 */   GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(269172), // Rule ID 12058 //
     /* 269135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_F16F32MM),
     /* 269138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
     /* 269143 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269146 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269149 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269152 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269155 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269159 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1512:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLLA_ZZZ_HtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 269159 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLLA_ZZZ_HtoS),
     /* 269162 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269164 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269168 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269170 */     GIR_RootConstrainSelectedInstOperands,
     /* 269171 */     // GIR_Coverage, 12058,
     /* 269171 */     GIR_EraseRootFromParent_Done,
     /* 269172 */   // Label 5187: @269172
     /* 269172 */   GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(269214), // Rule ID 12059 //
     /* 269177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulFP64_HasSVE),
     /* 269180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmmla),
     /* 269185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 269194 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 269197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269201 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1512:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMMLA_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 269201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_D),
     /* 269204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269210 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269212 */     GIR_RootConstrainSelectedInstOperands,
     /* 269213 */     // GIR_Coverage, 12059,
     /* 269213 */     GIR_EraseRootFromParent_Done,
     /* 269214 */   // Label 5188: @269214
     /* 269214 */   GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(269256), // Rule ID 12113 //
     /* 269219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269222 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 269227 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 269230 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 269233 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269236 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269243 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1877:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRDMLSH_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_B),
     /* 269246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269250 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269252 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269254 */     GIR_RootConstrainSelectedInstOperands,
     /* 269255 */     // GIR_Coverage, 12113,
     /* 269255 */     GIR_EraseRootFromParent_Done,
     /* 269256 */   // Label 5189: @269256
     /* 269256 */   GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(269298), // Rule ID 12114 //
     /* 269261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269264 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 269269 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269272 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269275 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269278 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269285 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1877:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRDMLSH_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_H),
     /* 269288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269290 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269292 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269294 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269296 */     GIR_RootConstrainSelectedInstOperands,
     /* 269297 */     // GIR_Coverage, 12114,
     /* 269297 */     GIR_EraseRootFromParent_Done,
     /* 269298 */   // Label 5190: @269298
     /* 269298 */   GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(269340), // Rule ID 12115 //
     /* 269303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 269311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269320 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269327 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1877:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRDMLSH_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_S),
     /* 269330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269332 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269334 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269336 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269338 */     GIR_RootConstrainSelectedInstOperands,
     /* 269339 */     // GIR_Coverage, 12115,
     /* 269339 */     GIR_EraseRootFromParent_Done,
     /* 269340 */   // Label 5191: @269340
     /* 269340 */   GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(269382), // Rule ID 12116 //
     /* 269345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269348 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh),
     /* 269353 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269356 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269359 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 269362 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 269365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269369 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1877:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRDMLSH_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 269369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZ_D),
     /* 269372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269378 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269380 */     GIR_RootConstrainSelectedInstOperands,
     /* 269381 */     // GIR_Coverage, 12116,
     /* 269381 */     GIR_EraseRootFromParent_Done,
     /* 269382 */   // Label 5192: @269382
     /* 269382 */   GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(269424), // Rule ID 12169 //
     /* 269387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 269395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269398 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269401 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269404 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269411 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1798:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_H),
     /* 269414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269420 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269422 */     GIR_RootConstrainSelectedInstOperands,
     /* 269423 */     // GIR_Coverage, 12169,
     /* 269423 */     GIR_EraseRootFromParent_Done,
     /* 269424 */   // Label 5193: @269424
     /* 269424 */   GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(269466), // Rule ID 12170 //
     /* 269429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 269437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269446 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269453 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1798:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_S),
     /* 269456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269458 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269460 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269462 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269464 */     GIR_RootConstrainSelectedInstOperands,
     /* 269465 */     // GIR_Coverage, 12170,
     /* 269465 */     GIR_EraseRootFromParent_Done,
     /* 269466 */   // Label 5194: @269466
     /* 269466 */   GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(269508), // Rule ID 12171 //
     /* 269471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269474 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt),
     /* 269479 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269488 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269495 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1798:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZ_D),
     /* 269498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269500 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269502 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269504 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269506 */     GIR_RootConstrainSelectedInstOperands,
     /* 269507 */     // GIR_Coverage, 12171,
     /* 269507 */     GIR_EraseRootFromParent_Done,
     /* 269508 */   // Label 5195: @269508
     /* 269508 */   GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(269550), // Rule ID 12172 //
     /* 269513 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269516 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 269521 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269524 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269527 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269530 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269533 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269537 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2038:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_H),
     /* 269540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269542 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269544 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269546 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269548 */     GIR_RootConstrainSelectedInstOperands,
     /* 269549 */     // GIR_Coverage, 12172,
     /* 269549 */     GIR_EraseRootFromParent_Done,
     /* 269550 */   // Label 5196: @269550
     /* 269550 */   GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(269592), // Rule ID 12173 //
     /* 269555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 269563 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269566 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269569 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269572 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269575 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269579 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2038:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_S),
     /* 269582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269586 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269588 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269590 */     GIR_RootConstrainSelectedInstOperands,
     /* 269591 */     // GIR_Coverage, 12173,
     /* 269591 */     GIR_EraseRootFromParent_Done,
     /* 269592 */   // Label 5197: @269592
     /* 269592 */   GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(269634), // Rule ID 12174 //
     /* 269597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269600 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb),
     /* 269605 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269608 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269611 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269614 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269621 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2038:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZ_D),
     /* 269624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269626 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269630 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269632 */     GIR_RootConstrainSelectedInstOperands,
     /* 269633 */     // GIR_Coverage, 12174,
     /* 269633 */     GIR_EraseRootFromParent_Done,
     /* 269634 */   // Label 5198: @269634
     /* 269634 */   GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(269676), // Rule ID 12175 //
     /* 269639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 269647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269656 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269659 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269663 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2040:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_H),
     /* 269666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269668 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269670 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269672 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269674 */     GIR_RootConstrainSelectedInstOperands,
     /* 269675 */     // GIR_Coverage, 12175,
     /* 269675 */     GIR_EraseRootFromParent_Done,
     /* 269676 */   // Label 5199: @269676
     /* 269676 */   GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(269718), // Rule ID 12176 //
     /* 269681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269684 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 269689 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269692 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269695 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269698 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269705 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2040:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_S),
     /* 269708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269710 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269712 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269714 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269716 */     GIR_RootConstrainSelectedInstOperands,
     /* 269717 */     // GIR_Coverage, 12176,
     /* 269717 */     GIR_EraseRootFromParent_Done,
     /* 269718 */   // Label 5200: @269718
     /* 269718 */   GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(269760), // Rule ID 12177 //
     /* 269723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269726 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt),
     /* 269731 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269734 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269737 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269740 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269743 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269747 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2040:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZ_D),
     /* 269750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269754 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269756 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269758 */     GIR_RootConstrainSelectedInstOperands,
     /* 269759 */     // GIR_Coverage, 12177,
     /* 269759 */     GIR_EraseRootFromParent_Done,
     /* 269760 */   // Label 5201: @269760
     /* 269760 */   GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(269802), // Rule ID 12178 //
     /* 269765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269768 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 269773 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269776 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269779 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269782 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269785 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269789 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1800:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_H),
     /* 269792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269794 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269796 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269798 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269800 */     GIR_RootConstrainSelectedInstOperands,
     /* 269801 */     // GIR_Coverage, 12178,
     /* 269801 */     GIR_EraseRootFromParent_Done,
     /* 269802 */   // Label 5202: @269802
     /* 269802 */   GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(269844), // Rule ID 12179 //
     /* 269807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 269815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269824 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269831 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1800:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_S),
     /* 269834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269836 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269838 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269840 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269842 */     GIR_RootConstrainSelectedInstOperands,
     /* 269843 */     // GIR_Coverage, 12179,
     /* 269843 */     GIR_EraseRootFromParent_Done,
     /* 269844 */   // Label 5203: @269844
     /* 269844 */   GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(269886), // Rule ID 12180 //
     /* 269849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb),
     /* 269857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269866 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269873 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1800:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZ_D),
     /* 269876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269878 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269880 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269882 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269884 */     GIR_RootConstrainSelectedInstOperands,
     /* 269885 */     // GIR_Coverage, 12180,
     /* 269885 */     GIR_EraseRootFromParent_Done,
     /* 269886 */   // Label 5204: @269886
     /* 269886 */   GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(269928), // Rule ID 12181 //
     /* 269891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269894 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 269899 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 269902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 269905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 269908 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 269911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269915 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1802:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 269915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_H),
     /* 269918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269924 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269926 */     GIR_RootConstrainSelectedInstOperands,
     /* 269927 */     // GIR_Coverage, 12181,
     /* 269927 */     GIR_EraseRootFromParent_Done,
     /* 269928 */   // Label 5205: @269928
     /* 269928 */   GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(269970), // Rule ID 12182 //
     /* 269933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269936 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 269941 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 269944 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 269947 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 269950 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 269953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269957 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1802:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 269957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_S),
     /* 269960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 269962 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 269964 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 269966 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 269968 */     GIR_RootConstrainSelectedInstOperands,
     /* 269969 */     // GIR_Coverage, 12182,
     /* 269969 */     GIR_EraseRootFromParent_Done,
     /* 269970 */   // Label 5206: @269970
     /* 269970 */   GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(270012), // Rule ID 12183 //
     /* 269975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 269978 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt),
     /* 269983 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 269986 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 269989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 269992 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 269995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 269999 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1802:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 269999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZ_D),
     /* 270002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270004 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270006 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270008 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270010 */     GIR_RootConstrainSelectedInstOperands,
     /* 270011 */     // GIR_Coverage, 12183,
     /* 270011 */     GIR_EraseRootFromParent_Done,
     /* 270012 */   // Label 5207: @270012
     /* 270012 */   GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(270054), // Rule ID 12184 //
     /* 270017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 270025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270034 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270037 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270041 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2042:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_H),
     /* 270044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270046 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270048 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270050 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270052 */     GIR_RootConstrainSelectedInstOperands,
     /* 270053 */     // GIR_Coverage, 12184,
     /* 270053 */     GIR_EraseRootFromParent_Done,
     /* 270054 */   // Label 5208: @270054
     /* 270054 */   GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(270096), // Rule ID 12185 //
     /* 270059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 270067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270076 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270083 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2042:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_S),
     /* 270086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270088 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270090 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270092 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270094 */     GIR_RootConstrainSelectedInstOperands,
     /* 270095 */     // GIR_Coverage, 12185,
     /* 270095 */     GIR_EraseRootFromParent_Done,
     /* 270096 */   // Label 5209: @270096
     /* 270096 */   GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(270138), // Rule ID 12186 //
     /* 270101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270104 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb),
     /* 270109 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270112 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270115 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270118 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270125 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2042:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270125 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZ_D),
     /* 270128 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270130 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270132 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270134 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270136 */     GIR_RootConstrainSelectedInstOperands,
     /* 270137 */     // GIR_Coverage, 12186,
     /* 270137 */     GIR_EraseRootFromParent_Done,
     /* 270138 */   // Label 5210: @270138
     /* 270138 */   GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(270180), // Rule ID 12187 //
     /* 270143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270146 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 270151 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270160 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270163 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270167 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2044:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_H),
     /* 270170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270172 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270174 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270176 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270178 */     GIR_RootConstrainSelectedInstOperands,
     /* 270179 */     // GIR_Coverage, 12187,
     /* 270179 */     GIR_EraseRootFromParent_Done,
     /* 270180 */   // Label 5211: @270180
     /* 270180 */   GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(270222), // Rule ID 12188 //
     /* 270185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270188 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 270193 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270196 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270199 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270202 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270205 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270209 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2044:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_S),
     /* 270212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270218 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270220 */     GIR_RootConstrainSelectedInstOperands,
     /* 270221 */     // GIR_Coverage, 12188,
     /* 270221 */     GIR_EraseRootFromParent_Done,
     /* 270222 */   // Label 5212: @270222
     /* 270222 */   GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(270264), // Rule ID 12189 //
     /* 270227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270230 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt),
     /* 270235 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270238 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270241 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270244 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270247 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270251 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2044:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZ_D),
     /* 270254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270256 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270258 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270260 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270262 */     GIR_RootConstrainSelectedInstOperands,
     /* 270263 */     // GIR_Coverage, 12189,
     /* 270263 */     GIR_EraseRootFromParent_Done,
     /* 270264 */   // Label 5213: @270264
     /* 270264 */   GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(270306), // Rule ID 12204 //
     /* 270269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270272 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 270277 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270280 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270283 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270286 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270289 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270293 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1838:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_H),
     /* 270296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270298 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270300 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270302 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270304 */     GIR_RootConstrainSelectedInstOperands,
     /* 270305 */     // GIR_Coverage, 12204,
     /* 270305 */     GIR_EraseRootFromParent_Done,
     /* 270306 */   // Label 5214: @270306
     /* 270306 */   GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(270348), // Rule ID 12205 //
     /* 270311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 270319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270328 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270331 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270335 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1838:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_S),
     /* 270338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270340 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270342 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270344 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270346 */     GIR_RootConstrainSelectedInstOperands,
     /* 270347 */     // GIR_Coverage, 12205,
     /* 270347 */     GIR_EraseRootFromParent_Done,
     /* 270348 */   // Label 5215: @270348
     /* 270348 */   GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(270390), // Rule ID 12206 //
     /* 270353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270356 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb),
     /* 270361 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270364 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270367 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270370 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270377 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1838:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZ_D),
     /* 270380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270386 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270388 */     GIR_RootConstrainSelectedInstOperands,
     /* 270389 */     // GIR_Coverage, 12206,
     /* 270389 */     GIR_EraseRootFromParent_Done,
     /* 270390 */   // Label 5216: @270390
     /* 270390 */   GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(270432), // Rule ID 12207 //
     /* 270395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 270403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270406 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270409 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270412 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270415 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270419 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1841:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_H),
     /* 270422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270424 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270426 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270428 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270430 */     GIR_RootConstrainSelectedInstOperands,
     /* 270431 */     // GIR_Coverage, 12207,
     /* 270431 */     GIR_EraseRootFromParent_Done,
     /* 270432 */   // Label 5217: @270432
     /* 270432 */   GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(270474), // Rule ID 12208 //
     /* 270437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 270445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270454 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270461 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1841:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_S),
     /* 270464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270466 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270468 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270470 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270472 */     GIR_RootConstrainSelectedInstOperands,
     /* 270473 */     // GIR_Coverage, 12208,
     /* 270473 */     GIR_EraseRootFromParent_Done,
     /* 270474 */   // Label 5218: @270474
     /* 270474 */   GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(270516), // Rule ID 12209 //
     /* 270479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270482 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt),
     /* 270487 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270490 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270493 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270496 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270503 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1841:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZ_D),
     /* 270506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270508 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270510 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270512 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270514 */     GIR_RootConstrainSelectedInstOperands,
     /* 270515 */     // GIR_Coverage, 12209,
     /* 270515 */     GIR_EraseRootFromParent_Done,
     /* 270516 */   // Label 5219: @270516
     /* 270516 */   GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(270558), // Rule ID 12210 //
     /* 270521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270524 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 270529 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270532 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270535 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270538 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270541 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270545 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1843:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270545 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_H),
     /* 270548 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270550 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270552 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270554 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270556 */     GIR_RootConstrainSelectedInstOperands,
     /* 270557 */     // GIR_Coverage, 12210,
     /* 270557 */     GIR_EraseRootFromParent_Done,
     /* 270558 */   // Label 5220: @270558
     /* 270558 */   GIM_Try, /*On fail goto*//*Label 5221*/ GIMT_Encode4(270600), // Rule ID 12211 //
     /* 270563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270566 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 270571 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270574 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270577 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270580 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270587 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1843:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_S),
     /* 270590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270592 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270594 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270596 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270598 */     GIR_RootConstrainSelectedInstOperands,
     /* 270599 */     // GIR_Coverage, 12211,
     /* 270599 */     GIR_EraseRootFromParent_Done,
     /* 270600 */   // Label 5221: @270600
     /* 270600 */   GIM_Try, /*On fail goto*//*Label 5222*/ GIMT_Encode4(270642), // Rule ID 12212 //
     /* 270605 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270608 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb),
     /* 270613 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270616 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270619 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270622 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270625 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270629 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1843:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZ_D),
     /* 270632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270636 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270638 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270640 */     GIR_RootConstrainSelectedInstOperands,
     /* 270641 */     // GIR_Coverage, 12212,
     /* 270641 */     GIR_EraseRootFromParent_Done,
     /* 270642 */   // Label 5222: @270642
     /* 270642 */   GIM_Try, /*On fail goto*//*Label 5223*/ GIMT_Encode4(270684), // Rule ID 12213 //
     /* 270647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 270655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270664 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270671 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1846:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_H),
     /* 270674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270678 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270680 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270682 */     GIR_RootConstrainSelectedInstOperands,
     /* 270683 */     // GIR_Coverage, 12213,
     /* 270683 */     GIR_EraseRootFromParent_Done,
     /* 270684 */   // Label 5223: @270684
     /* 270684 */   GIM_Try, /*On fail goto*//*Label 5224*/ GIMT_Encode4(270726), // Rule ID 12214 //
     /* 270689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 270697 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270703 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270706 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270713 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1846:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_S),
     /* 270716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270718 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270720 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270722 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270724 */     GIR_RootConstrainSelectedInstOperands,
     /* 270725 */     // GIR_Coverage, 12214,
     /* 270725 */     GIR_EraseRootFromParent_Done,
     /* 270726 */   // Label 5224: @270726
     /* 270726 */   GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(270768), // Rule ID 12215 //
     /* 270731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270734 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt),
     /* 270739 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270742 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270745 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270748 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270751 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270755 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1846:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZ_D),
     /* 270758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270760 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270762 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270764 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270766 */     GIR_RootConstrainSelectedInstOperands,
     /* 270767 */     // GIR_Coverage, 12215,
     /* 270767 */     GIR_EraseRootFromParent_Done,
     /* 270768 */   // Label 5225: @270768
     /* 270768 */   GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(270810), // Rule ID 12216 //
     /* 270773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 270781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270790 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270797 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1840:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLALBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_H),
     /* 270800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270802 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270804 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270806 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270808 */     GIR_RootConstrainSelectedInstOperands,
     /* 270809 */     // GIR_Coverage, 12216,
     /* 270809 */     GIR_EraseRootFromParent_Done,
     /* 270810 */   // Label 5226: @270810
     /* 270810 */   GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(270852), // Rule ID 12217 //
     /* 270815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 270823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270829 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270832 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270839 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1840:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLALBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_S),
     /* 270842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270844 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270846 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270848 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270850 */     GIR_RootConstrainSelectedInstOperands,
     /* 270851 */     // GIR_Coverage, 12217,
     /* 270851 */     GIR_EraseRootFromParent_Done,
     /* 270852 */   // Label 5227: @270852
     /* 270852 */   GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(270894), // Rule ID 12218 //
     /* 270857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalbt),
     /* 270865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 270874 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 270877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270881 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1840:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLALBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 270881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALBT_ZZZ_D),
     /* 270884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270890 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270892 */     GIR_RootConstrainSelectedInstOperands,
     /* 270893 */     // GIR_Coverage, 12218,
     /* 270893 */     GIR_EraseRootFromParent_Done,
     /* 270894 */   // Label 5228: @270894
     /* 270894 */   GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(270936), // Rule ID 12219 //
     /* 270899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270902 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 270907 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 270910 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 270913 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 270916 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 270919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270923 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1845:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQDMLSLBT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 270923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_H),
     /* 270926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270928 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270930 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270932 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270934 */     GIR_RootConstrainSelectedInstOperands,
     /* 270935 */     // GIR_Coverage, 12219,
     /* 270935 */     GIR_EraseRootFromParent_Done,
     /* 270936 */   // Label 5229: @270936
     /* 270936 */   GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(270978), // Rule ID 12220 //
     /* 270941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270944 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 270949 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 270952 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 270955 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 270958 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 270961 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 270965 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1845:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQDMLSLBT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 270965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_S),
     /* 270968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 270970 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 270972 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 270974 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 270976 */     GIR_RootConstrainSelectedInstOperands,
     /* 270977 */     // GIR_Coverage, 12220,
     /* 270977 */     GIR_EraseRootFromParent_Done,
     /* 270978 */   // Label 5230: @270978
     /* 270978 */   GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(271020), // Rule ID 12221 //
     /* 270983 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 270986 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslbt),
     /* 270991 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 270994 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 270997 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271000 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271003 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271007 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1845:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQDMLSLBT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLBT_ZZZ_D),
     /* 271010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 271012 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271014 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271016 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271018 */     GIR_RootConstrainSelectedInstOperands,
     /* 271019 */     // GIR_Coverage, 12221,
     /* 271019 */     GIR_EraseRootFromParent_Done,
     /* 271020 */   // Label 5231: @271020
     /* 271020 */   GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(271062), // Rule ID 12222 //
     /* 271025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 271033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271042 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271049 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2016:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_B),
     /* 271052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271056 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271058 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271060 */     GIR_RootConstrainSelectedInstOperands,
     /* 271061 */     // GIR_Coverage, 12222,
     /* 271061 */     GIR_EraseRootFromParent_Done,
     /* 271062 */   // Label 5232: @271062
     /* 271062 */   GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(271104), // Rule ID 12224 //
     /* 271067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 271075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271084 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271091 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2016:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_H),
     /* 271094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271098 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271100 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271102 */     GIR_RootConstrainSelectedInstOperands,
     /* 271103 */     // GIR_Coverage, 12224,
     /* 271103 */     GIR_EraseRootFromParent_Done,
     /* 271104 */   // Label 5233: @271104
     /* 271104 */   GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(271146), // Rule ID 12226 //
     /* 271109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 271117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271126 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271133 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2016:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_S),
     /* 271136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271138 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271140 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271142 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271144 */     GIR_RootConstrainSelectedInstOperands,
     /* 271145 */     // GIR_Coverage, 12226,
     /* 271145 */     GIR_EraseRootFromParent_Done,
     /* 271146 */   // Label 5234: @271146
     /* 271146 */   GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(271188), // Rule ID 12228 //
     /* 271151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271154 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhadd),
     /* 271159 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 271162 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 271165 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271168 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 271171 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271175 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2016:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 271175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHADD_ZPmZ_D),
     /* 271178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271182 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271184 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271186 */     GIR_RootConstrainSelectedInstOperands,
     /* 271187 */     // GIR_Coverage, 12228,
     /* 271187 */     GIR_EraseRootFromParent_Done,
     /* 271188 */   // Label 5235: @271188
     /* 271188 */   GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(271230), // Rule ID 12230 //
     /* 271193 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271196 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 271201 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271204 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271207 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271210 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271213 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271217 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1772:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_B),
     /* 271220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271224 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271226 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271228 */     GIR_RootConstrainSelectedInstOperands,
     /* 271229 */     // GIR_Coverage, 12230,
     /* 271229 */     GIR_EraseRootFromParent_Done,
     /* 271230 */   // Label 5236: @271230
     /* 271230 */   GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(271272), // Rule ID 12231 //
     /* 271235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 271243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271252 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271259 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1772:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_H),
     /* 271262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271268 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271270 */     GIR_RootConstrainSelectedInstOperands,
     /* 271271 */     // GIR_Coverage, 12231,
     /* 271271 */     GIR_EraseRootFromParent_Done,
     /* 271272 */   // Label 5237: @271272
     /* 271272 */   GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(271314), // Rule ID 12232 //
     /* 271277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 271285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271294 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271301 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1772:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_S),
     /* 271304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271308 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271310 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271312 */     GIR_RootConstrainSelectedInstOperands,
     /* 271313 */     // GIR_Coverage, 12232,
     /* 271313 */     GIR_EraseRootFromParent_Done,
     /* 271314 */   // Label 5238: @271314
     /* 271314 */   GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(271356), // Rule ID 12233 //
     /* 271319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271322 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub),
     /* 271327 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 271330 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 271333 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271336 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 271339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271343 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1772:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 271343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPmZ_D),
     /* 271346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271348 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271350 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271352 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271354 */     GIR_RootConstrainSelectedInstOperands,
     /* 271355 */     // GIR_Coverage, 12233,
     /* 271355 */     GIR_EraseRootFromParent_Done,
     /* 271356 */   // Label 5239: @271356
     /* 271356 */   GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(271398), // Rule ID 12234 //
     /* 271361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271364 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 271369 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271372 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271375 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271378 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271381 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271385 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2017:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_B),
     /* 271388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271392 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271394 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271396 */     GIR_RootConstrainSelectedInstOperands,
     /* 271397 */     // GIR_Coverage, 12234,
     /* 271397 */     GIR_EraseRootFromParent_Done,
     /* 271398 */   // Label 5240: @271398
     /* 271398 */   GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(271440), // Rule ID 12235 //
     /* 271403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 271411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271420 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271423 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271427 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2017:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_H),
     /* 271430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271436 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271438 */     GIR_RootConstrainSelectedInstOperands,
     /* 271439 */     // GIR_Coverage, 12235,
     /* 271439 */     GIR_EraseRootFromParent_Done,
     /* 271440 */   // Label 5241: @271440
     /* 271440 */   GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(271482), // Rule ID 12236 //
     /* 271445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271448 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 271453 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271456 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271459 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271462 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271465 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271469 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2017:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_S),
     /* 271472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271474 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271476 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271478 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271480 */     GIR_RootConstrainSelectedInstOperands,
     /* 271481 */     // GIR_Coverage, 12236,
     /* 271481 */     GIR_EraseRootFromParent_Done,
     /* 271482 */   // Label 5242: @271482
     /* 271482 */   GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(271524), // Rule ID 12237 //
     /* 271487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub),
     /* 271495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 271498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 271501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271504 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 271507 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271511 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2017:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 271511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPmZ_D),
     /* 271514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271516 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271520 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271522 */     GIR_RootConstrainSelectedInstOperands,
     /* 271523 */     // GIR_Coverage, 12237,
     /* 271523 */     GIR_EraseRootFromParent_Done,
     /* 271524 */   // Label 5243: @271524
     /* 271524 */   GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(271566), // Rule ID 12238 //
     /* 271529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 271537 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271543 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271546 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271553 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1910:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SRHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_B),
     /* 271556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271562 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271564 */     GIR_RootConstrainSelectedInstOperands,
     /* 271565 */     // GIR_Coverage, 12238,
     /* 271565 */     GIR_EraseRootFromParent_Done,
     /* 271566 */   // Label 5244: @271566
     /* 271566 */   GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(271608), // Rule ID 12240 //
     /* 271571 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271574 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 271579 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271588 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271591 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271595 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1910:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SRHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_H),
     /* 271598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271604 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271606 */     GIR_RootConstrainSelectedInstOperands,
     /* 271607 */     // GIR_Coverage, 12240,
     /* 271607 */     GIR_EraseRootFromParent_Done,
     /* 271608 */   // Label 5245: @271608
     /* 271608 */   GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(271650), // Rule ID 12242 //
     /* 271613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271616 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 271621 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271630 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271637 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1910:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SRHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271637 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_S),
     /* 271640 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271642 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271644 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271646 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271648 */     GIR_RootConstrainSelectedInstOperands,
     /* 271649 */     // GIR_Coverage, 12242,
     /* 271649 */     GIR_EraseRootFromParent_Done,
     /* 271650 */   // Label 5246: @271650
     /* 271650 */   GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(271692), // Rule ID 12244 //
     /* 271655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271658 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srhadd),
     /* 271663 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 271666 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 271669 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271672 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 271675 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271679 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1910:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SRHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 271679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRHADD_ZPmZ_D),
     /* 271682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271684 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271686 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271688 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271690 */     GIR_RootConstrainSelectedInstOperands,
     /* 271691 */     // GIR_Coverage, 12244,
     /* 271691 */     GIR_EraseRootFromParent_Done,
     /* 271692 */   // Label 5247: @271692
     /* 271692 */   GIM_Try, /*On fail goto*//*Label 5248*/ GIMT_Encode4(271734), // Rule ID 12246 //
     /* 271697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 271705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271714 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271717 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271721 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2106:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (URHADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_B),
     /* 271724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271726 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271728 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271730 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271732 */     GIR_RootConstrainSelectedInstOperands,
     /* 271733 */     // GIR_Coverage, 12246,
     /* 271733 */     GIR_EraseRootFromParent_Done,
     /* 271734 */   // Label 5248: @271734
     /* 271734 */   GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(271776), // Rule ID 12248 //
     /* 271739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 271747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271763 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2106:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (URHADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_H),
     /* 271766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271768 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271770 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271772 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271774 */     GIR_RootConstrainSelectedInstOperands,
     /* 271775 */     // GIR_Coverage, 12248,
     /* 271775 */     GIR_EraseRootFromParent_Done,
     /* 271776 */   // Label 5249: @271776
     /* 271776 */   GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(271818), // Rule ID 12250 //
     /* 271781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271784 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 271789 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271792 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271795 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271798 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271805 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2106:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URHADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_S),
     /* 271808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271810 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271812 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271814 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271816 */     GIR_RootConstrainSelectedInstOperands,
     /* 271817 */     // GIR_Coverage, 12250,
     /* 271817 */     GIR_EraseRootFromParent_Done,
     /* 271818 */   // Label 5250: @271818
     /* 271818 */   GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(271860), // Rule ID 12252 //
     /* 271823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urhadd),
     /* 271831 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 271834 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 271837 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 271840 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 271843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271847 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2106:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (URHADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 271847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URHADD_ZPmZ_D),
     /* 271850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271854 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271856 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271858 */     GIR_RootConstrainSelectedInstOperands,
     /* 271859 */     // GIR_Coverage, 12252,
     /* 271859 */     GIR_EraseRootFromParent_Done,
     /* 271860 */   // Label 5251: @271860
     /* 271860 */   GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(271902), // Rule ID 12254 //
     /* 271865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 271873 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 271876 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 271879 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 271882 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 271885 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271889 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1774:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 271889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_B),
     /* 271892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271894 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271896 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271898 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271900 */     GIR_RootConstrainSelectedInstOperands,
     /* 271901 */     // GIR_Coverage, 12254,
     /* 271901 */     GIR_EraseRootFromParent_Done,
     /* 271902 */   // Label 5252: @271902
     /* 271902 */   GIM_Try, /*On fail goto*//*Label 5253*/ GIMT_Encode4(271944), // Rule ID 12255 //
     /* 271907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 271915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 271918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 271921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 271924 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 271927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271931 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1774:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 271931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_H),
     /* 271934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271936 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271938 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271940 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271942 */     GIR_RootConstrainSelectedInstOperands,
     /* 271943 */     // GIR_Coverage, 12255,
     /* 271943 */     GIR_EraseRootFromParent_Done,
     /* 271944 */   // Label 5253: @271944
     /* 271944 */   GIM_Try, /*On fail goto*//*Label 5254*/ GIMT_Encode4(271986), // Rule ID 12256 //
     /* 271949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 271957 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 271960 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 271963 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 271966 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 271969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 271973 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1774:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 271973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_S),
     /* 271976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 271978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 271980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 271982 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 271984 */     GIR_RootConstrainSelectedInstOperands,
     /* 271985 */     // GIR_Coverage, 12256,
     /* 271985 */     GIR_EraseRootFromParent_Done,
     /* 271986 */   // Label 5254: @271986
     /* 271986 */   GIM_Try, /*On fail goto*//*Label 5255*/ GIMT_Encode4(272028), // Rule ID 12257 //
     /* 271991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 271994 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsubr),
     /* 271999 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272002 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272005 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272008 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272015 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1774:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUBR_ZPmZ_D),
     /* 272018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272020 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272022 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272024 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272026 */     GIR_RootConstrainSelectedInstOperands,
     /* 272027 */     // GIR_Coverage, 12257,
     /* 272027 */     GIR_EraseRootFromParent_Done,
     /* 272028 */   // Label 5255: @272028
     /* 272028 */   GIM_Try, /*On fail goto*//*Label 5256*/ GIMT_Encode4(272070), // Rule ID 12258 //
     /* 272033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 272041 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 272044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 272047 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 272050 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272053 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272057 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2019:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_B),
     /* 272060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272064 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272066 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272068 */     GIR_RootConstrainSelectedInstOperands,
     /* 272069 */     // GIR_Coverage, 12258,
     /* 272069 */     GIR_EraseRootFromParent_Done,
     /* 272070 */   // Label 5256: @272070
     /* 272070 */   GIM_Try, /*On fail goto*//*Label 5257*/ GIMT_Encode4(272112), // Rule ID 12259 //
     /* 272075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 272083 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272086 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272089 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272092 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272095 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272099 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2019:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_H),
     /* 272102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272106 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272108 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272110 */     GIR_RootConstrainSelectedInstOperands,
     /* 272111 */     // GIR_Coverage, 12259,
     /* 272111 */     GIR_EraseRootFromParent_Done,
     /* 272112 */   // Label 5257: @272112
     /* 272112 */   GIM_Try, /*On fail goto*//*Label 5258*/ GIMT_Encode4(272154), // Rule ID 12260 //
     /* 272117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 272125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272134 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272141 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2019:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_S),
     /* 272144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272146 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272148 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272150 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272152 */     GIR_RootConstrainSelectedInstOperands,
     /* 272153 */     // GIR_Coverage, 12260,
     /* 272153 */     GIR_EraseRootFromParent_Done,
     /* 272154 */   // Label 5258: @272154
     /* 272154 */   GIM_Try, /*On fail goto*//*Label 5259*/ GIMT_Encode4(272196), // Rule ID 12261 //
     /* 272159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsubr),
     /* 272167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272176 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272183 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2019:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUBR_ZPmZ_D),
     /* 272186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272192 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272194 */     GIR_RootConstrainSelectedInstOperands,
     /* 272195 */     // GIR_Coverage, 12261,
     /* 272195 */     GIR_EraseRootFromParent_Done,
     /* 272196 */   // Label 5259: @272196
     /* 272196 */   GIM_Try, /*On fail goto*//*Label 5260*/ GIMT_Encode4(272238), // Rule ID 12262 //
     /* 272201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub_u),
     /* 272209 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 272212 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 272215 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 272218 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272225 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1773:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SHSUB_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272225 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPZZ_B_UNDEF),
     /* 272228 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272230 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272232 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272234 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272236 */     GIR_RootConstrainSelectedInstOperands,
     /* 272237 */     // GIR_Coverage, 12262,
     /* 272237 */     GIR_EraseRootFromParent_Done,
     /* 272238 */   // Label 5260: @272238
     /* 272238 */   GIM_Try, /*On fail goto*//*Label 5261*/ GIMT_Encode4(272280), // Rule ID 12263 //
     /* 272243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub_u),
     /* 272251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272257 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272260 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272263 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272267 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1773:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SHSUB_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPZZ_H_UNDEF),
     /* 272270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272272 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272274 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272276 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272278 */     GIR_RootConstrainSelectedInstOperands,
     /* 272279 */     // GIR_Coverage, 12263,
     /* 272279 */     GIR_EraseRootFromParent_Done,
     /* 272280 */   // Label 5261: @272280
     /* 272280 */   GIM_Try, /*On fail goto*//*Label 5262*/ GIMT_Encode4(272322), // Rule ID 12264 //
     /* 272285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub_u),
     /* 272293 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272296 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272299 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272302 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272309 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1773:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SHSUB_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPZZ_S_UNDEF),
     /* 272312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272314 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272316 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272318 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272320 */     GIR_RootConstrainSelectedInstOperands,
     /* 272321 */     // GIR_Coverage, 12264,
     /* 272321 */     GIR_EraseRootFromParent_Done,
     /* 272322 */   // Label 5262: @272322
     /* 272322 */   GIM_Try, /*On fail goto*//*Label 5263*/ GIMT_Encode4(272364), // Rule ID 12265 //
     /* 272327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272330 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_shsub_u),
     /* 272335 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272338 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272341 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272344 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272351 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1773:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SHSUB_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHSUB_ZPZZ_D_UNDEF),
     /* 272354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272356 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272360 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272362 */     GIR_RootConstrainSelectedInstOperands,
     /* 272363 */     // GIR_Coverage, 12265,
     /* 272363 */     GIR_EraseRootFromParent_Done,
     /* 272364 */   // Label 5263: @272364
     /* 272364 */   GIM_Try, /*On fail goto*//*Label 5264*/ GIMT_Encode4(272406), // Rule ID 12266 //
     /* 272369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub_u),
     /* 272377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 272380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 272383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 272386 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272393 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2018:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UHSUB_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPZZ_B_UNDEF),
     /* 272396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272400 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272402 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272404 */     GIR_RootConstrainSelectedInstOperands,
     /* 272405 */     // GIR_Coverage, 12266,
     /* 272405 */     GIR_EraseRootFromParent_Done,
     /* 272406 */   // Label 5264: @272406
     /* 272406 */   GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(272448), // Rule ID 12267 //
     /* 272411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub_u),
     /* 272419 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272428 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272435 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2018:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UHSUB_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPZZ_H_UNDEF),
     /* 272438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272442 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272444 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272446 */     GIR_RootConstrainSelectedInstOperands,
     /* 272447 */     // GIR_Coverage, 12267,
     /* 272447 */     GIR_EraseRootFromParent_Done,
     /* 272448 */   // Label 5265: @272448
     /* 272448 */   GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(272490), // Rule ID 12268 //
     /* 272453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub_u),
     /* 272461 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272464 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272467 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272470 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272477 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2018:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UHSUB_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272477 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPZZ_S_UNDEF),
     /* 272480 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272482 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272484 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272486 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272488 */     GIR_RootConstrainSelectedInstOperands,
     /* 272489 */     // GIR_Coverage, 12268,
     /* 272489 */     GIR_EraseRootFromParent_Done,
     /* 272490 */   // Label 5266: @272490
     /* 272490 */   GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(272532), // Rule ID 12269 //
     /* 272495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uhsub_u),
     /* 272503 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272506 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272509 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272512 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272519 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2018:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UHSUB_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UHSUB_ZPZZ_D_UNDEF),
     /* 272522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 272524 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272528 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272530 */     GIR_RootConstrainSelectedInstOperands,
     /* 272531 */     // GIR_Coverage, 12269,
     /* 272531 */     GIR_EraseRootFromParent_Done,
     /* 272532 */   // Label 5267: @272532
     /* 272532 */   GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(272574), // Rule ID 12270 //
     /* 272537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 272545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272554 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272561 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1993:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UADALP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_H),
     /* 272564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 272566 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272568 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272570 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272572 */     GIR_RootConstrainSelectedInstOperands,
     /* 272573 */     // GIR_Coverage, 12270,
     /* 272573 */     GIR_EraseRootFromParent_Done,
     /* 272574 */   // Label 5268: @272574
     /* 272574 */   GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(272616), // Rule ID 12271 //
     /* 272579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 272587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272593 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272596 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272603 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1993:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UADALP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_S),
     /* 272606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 272608 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272612 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272614 */     GIR_RootConstrainSelectedInstOperands,
     /* 272615 */     // GIR_Coverage, 12271,
     /* 272615 */     GIR_EraseRootFromParent_Done,
     /* 272616 */   // Label 5269: @272616
     /* 272616 */   GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(272658), // Rule ID 12272 //
     /* 272621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uadalp),
     /* 272629 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272632 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272635 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272638 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272641 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272645 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1993:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UADALP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADALP_ZPmZ_D),
     /* 272648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 272650 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272652 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272654 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272656 */     GIR_RootConstrainSelectedInstOperands,
     /* 272657 */     // GIR_Coverage, 12272,
     /* 272657 */     GIR_EraseRootFromParent_Done,
     /* 272658 */   // Label 5270: @272658
     /* 272658 */   GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(272700), // Rule ID 12273 //
     /* 272663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 272671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 272674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 272677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 272680 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272683 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272687 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1275:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (ADDP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_B),
     /* 272690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272692 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272694 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272696 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272698 */     GIR_RootConstrainSelectedInstOperands,
     /* 272699 */     // GIR_Coverage, 12273,
     /* 272699 */     GIR_EraseRootFromParent_Done,
     /* 272700 */   // Label 5271: @272700
     /* 272700 */   GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(272742), // Rule ID 12274 //
     /* 272705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 272713 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272716 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272719 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272722 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272729 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1275:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (ADDP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272729 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_H),
     /* 272732 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272734 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272736 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272738 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272740 */     GIR_RootConstrainSelectedInstOperands,
     /* 272741 */     // GIR_Coverage, 12274,
     /* 272741 */     GIR_EraseRootFromParent_Done,
     /* 272742 */   // Label 5272: @272742
     /* 272742 */   GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(272784), // Rule ID 12275 //
     /* 272747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 272755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272764 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272767 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272771 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1275:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADDP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_S),
     /* 272774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272778 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272780 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272782 */     GIR_RootConstrainSelectedInstOperands,
     /* 272783 */     // GIR_Coverage, 12275,
     /* 272783 */     GIR_EraseRootFromParent_Done,
     /* 272784 */   // Label 5273: @272784
     /* 272784 */   GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(272826), // Rule ID 12276 //
     /* 272789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_addp),
     /* 272797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272806 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272813 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1275:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADDP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDP_ZPmZ_D),
     /* 272816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272822 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272824 */     GIR_RootConstrainSelectedInstOperands,
     /* 272825 */     // GIR_Coverage, 12276,
     /* 272825 */     GIR_EraseRootFromParent_Done,
     /* 272826 */   // Label 5274: @272826
     /* 272826 */   GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(272868), // Rule ID 12277 //
     /* 272831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 272839 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 272842 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 272845 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 272848 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 272851 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272855 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1784:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 272855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_B),
     /* 272858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272860 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272862 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272864 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272866 */     GIR_RootConstrainSelectedInstOperands,
     /* 272867 */     // GIR_Coverage, 12277,
     /* 272867 */     GIR_EraseRootFromParent_Done,
     /* 272868 */   // Label 5275: @272868
     /* 272868 */   GIM_Try, /*On fail goto*//*Label 5276*/ GIMT_Encode4(272910), // Rule ID 12278 //
     /* 272873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 272881 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 272884 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 272887 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 272890 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 272893 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272897 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1784:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 272897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_H),
     /* 272900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272902 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272904 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272906 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272908 */     GIR_RootConstrainSelectedInstOperands,
     /* 272909 */     // GIR_Coverage, 12278,
     /* 272909 */     GIR_EraseRootFromParent_Done,
     /* 272910 */   // Label 5276: @272910
     /* 272910 */   GIM_Try, /*On fail goto*//*Label 5277*/ GIMT_Encode4(272952), // Rule ID 12279 //
     /* 272915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 272923 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 272926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 272929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 272932 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 272935 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272939 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1784:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 272939 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_S),
     /* 272942 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272944 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272946 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272948 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272950 */     GIR_RootConstrainSelectedInstOperands,
     /* 272951 */     // GIR_Coverage, 12279,
     /* 272951 */     GIR_EraseRootFromParent_Done,
     /* 272952 */   // Label 5277: @272952
     /* 272952 */   GIM_Try, /*On fail goto*//*Label 5278*/ GIMT_Encode4(272994), // Rule ID 12280 //
     /* 272957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 272960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smaxp),
     /* 272965 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 272968 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 272971 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 272974 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 272977 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 272981 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1784:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 272981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXP_ZPmZ_D),
     /* 272984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 272986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 272988 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 272990 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 272992 */     GIR_RootConstrainSelectedInstOperands,
     /* 272993 */     // GIR_Coverage, 12280,
     /* 272993 */     GIR_EraseRootFromParent_Done,
     /* 272994 */   // Label 5278: @272994
     /* 272994 */   GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(273036), // Rule ID 12281 //
     /* 272999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 273007 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273010 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 273013 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 273016 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273019 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273023 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2026:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMAXP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_B),
     /* 273026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273028 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273030 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273032 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273034 */     GIR_RootConstrainSelectedInstOperands,
     /* 273035 */     // GIR_Coverage, 12281,
     /* 273035 */     GIR_EraseRootFromParent_Done,
     /* 273036 */   // Label 5279: @273036
     /* 273036 */   GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(273078), // Rule ID 12282 //
     /* 273041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 273049 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273052 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 273055 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 273058 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273061 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273065 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2026:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMAXP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_H),
     /* 273068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273070 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273072 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273074 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273076 */     GIR_RootConstrainSelectedInstOperands,
     /* 273077 */     // GIR_Coverage, 12282,
     /* 273077 */     GIR_EraseRootFromParent_Done,
     /* 273078 */   // Label 5280: @273078
     /* 273078 */   GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(273120), // Rule ID 12283 //
     /* 273083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 273091 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273094 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273097 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273100 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273107 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2026:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMAXP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273107 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_S),
     /* 273110 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273112 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273114 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273116 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273118 */     GIR_RootConstrainSelectedInstOperands,
     /* 273119 */     // GIR_Coverage, 12283,
     /* 273119 */     GIR_EraseRootFromParent_Done,
     /* 273120 */   // Label 5281: @273120
     /* 273120 */   GIM_Try, /*On fail goto*//*Label 5282*/ GIMT_Encode4(273162), // Rule ID 12284 //
     /* 273125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273128 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umaxp),
     /* 273133 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273139 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 273142 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273149 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2026:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMAXP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 273149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXP_ZPmZ_D),
     /* 273152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273156 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273158 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273160 */     GIR_RootConstrainSelectedInstOperands,
     /* 273161 */     // GIR_Coverage, 12284,
     /* 273161 */     GIR_EraseRootFromParent_Done,
     /* 273162 */   // Label 5282: @273162
     /* 273162 */   GIM_Try, /*On fail goto*//*Label 5283*/ GIMT_Encode4(273204), // Rule ID 12285 //
     /* 273167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 273175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 273181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 273184 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273191 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1793:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_B),
     /* 273194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273198 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273200 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273202 */     GIR_RootConstrainSelectedInstOperands,
     /* 273203 */     // GIR_Coverage, 12285,
     /* 273203 */     GIR_EraseRootFromParent_Done,
     /* 273204 */   // Label 5283: @273204
     /* 273204 */   GIM_Try, /*On fail goto*//*Label 5284*/ GIMT_Encode4(273246), // Rule ID 12286 //
     /* 273209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 273217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 273223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 273226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273233 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1793:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_H),
     /* 273236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273242 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273244 */     GIR_RootConstrainSelectedInstOperands,
     /* 273245 */     // GIR_Coverage, 12286,
     /* 273245 */     GIR_EraseRootFromParent_Done,
     /* 273246 */   // Label 5284: @273246
     /* 273246 */   GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(273288), // Rule ID 12287 //
     /* 273251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273254 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 273259 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273265 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273268 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273275 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1793:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_S),
     /* 273278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273280 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273282 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273284 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273286 */     GIR_RootConstrainSelectedInstOperands,
     /* 273287 */     // GIR_Coverage, 12287,
     /* 273287 */     GIR_EraseRootFromParent_Done,
     /* 273288 */   // Label 5285: @273288
     /* 273288 */   GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(273330), // Rule ID 12288 //
     /* 273293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sminp),
     /* 273301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 273310 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273317 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1793:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 273317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINP_ZPmZ_D),
     /* 273320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273326 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273328 */     GIR_RootConstrainSelectedInstOperands,
     /* 273329 */     // GIR_Coverage, 12288,
     /* 273329 */     GIR_EraseRootFromParent_Done,
     /* 273330 */   // Label 5286: @273330
     /* 273330 */   GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(273372), // Rule ID 12289 //
     /* 273335 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273338 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 273343 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273346 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 273349 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 273352 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273359 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2035:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UMINP_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_B),
     /* 273362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273364 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273366 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273368 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273370 */     GIR_RootConstrainSelectedInstOperands,
     /* 273371 */     // GIR_Coverage, 12289,
     /* 273371 */     GIR_EraseRootFromParent_Done,
     /* 273372 */   // Label 5287: @273372
     /* 273372 */   GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(273414), // Rule ID 12290 //
     /* 273377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 273385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 273391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 273394 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273401 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2035:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UMINP_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_H),
     /* 273404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273406 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273408 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273410 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273412 */     GIR_RootConstrainSelectedInstOperands,
     /* 273413 */     // GIR_Coverage, 12290,
     /* 273413 */     GIR_EraseRootFromParent_Done,
     /* 273414 */   // Label 5288: @273414
     /* 273414 */   GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(273456), // Rule ID 12291 //
     /* 273419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273422 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 273427 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273436 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273443 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2035:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UMINP_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_S),
     /* 273446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273448 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273452 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273454 */     GIR_RootConstrainSelectedInstOperands,
     /* 273455 */     // GIR_Coverage, 12291,
     /* 273455 */     GIR_EraseRootFromParent_Done,
     /* 273456 */   // Label 5289: @273456
     /* 273456 */   GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(273498), // Rule ID 12292 //
     /* 273461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273464 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uminp),
     /* 273469 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273472 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273475 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 273478 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273481 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273485 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2035:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UMINP_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 273485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINP_ZPmZ_D),
     /* 273488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273492 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273494 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273496 */     GIR_RootConstrainSelectedInstOperands,
     /* 273497 */     // GIR_Coverage, 12292,
     /* 273497 */     GIR_EraseRootFromParent_Done,
     /* 273498 */   // Label 5290: @273498
     /* 273498 */   GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(273540), // Rule ID 12293 //
     /* 273503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273506 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ursqrte),
     /* 273511 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273514 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 273517 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 273520 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273523 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273527 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2114:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URSQRTE_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSQRTE_ZPmZ_S),
     /* 273530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 273532 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273536 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273538 */     GIR_RootConstrainSelectedInstOperands,
     /* 273539 */     // GIR_Coverage, 12293,
     /* 273539 */     GIR_EraseRootFromParent_Done,
     /* 273540 */   // Label 5291: @273540
     /* 273540 */   GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(273582), // Rule ID 12304 //
     /* 273545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 273553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 273559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 273562 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273569 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1872:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQNEG_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_B),
     /* 273572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 273574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273576 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273578 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273580 */     GIR_RootConstrainSelectedInstOperands,
     /* 273581 */     // GIR_Coverage, 12304,
     /* 273581 */     GIR_EraseRootFromParent_Done,
     /* 273582 */   // Label 5292: @273582
     /* 273582 */   GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(273624), // Rule ID 12305 //
     /* 273587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 273595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 273601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 273604 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273611 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1872:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQNEG_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_H),
     /* 273614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 273616 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273620 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273622 */     GIR_RootConstrainSelectedInstOperands,
     /* 273623 */     // GIR_Coverage, 12305,
     /* 273623 */     GIR_EraseRootFromParent_Done,
     /* 273624 */   // Label 5293: @273624
     /* 273624 */   GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(273666), // Rule ID 12306 //
     /* 273629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273632 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 273637 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 273643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 273646 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273653 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1872:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQNEG_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_S),
     /* 273656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 273658 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273662 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273664 */     GIR_RootConstrainSelectedInstOperands,
     /* 273665 */     // GIR_Coverage, 12306,
     /* 273665 */     GIR_EraseRootFromParent_Done,
     /* 273666 */   // Label 5294: @273666
     /* 273666 */   GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(273708), // Rule ID 12307 //
     /* 273671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqneg),
     /* 273679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 273685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 273688 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273695 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1872:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQNEG_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 273695 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQNEG_ZPmZ_D),
     /* 273698 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 273700 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273702 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273704 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273706 */     GIR_RootConstrainSelectedInstOperands,
     /* 273707 */     // GIR_Coverage, 12307,
     /* 273707 */     GIR_EraseRootFromParent_Done,
     /* 273708 */   // Label 5295: @273708
     /* 273708 */   GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(273750), // Rule ID 12316 //
     /* 273713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 273721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 273727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 273730 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273733 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273737 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1813:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_B),
     /* 273740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273742 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273744 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273746 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273748 */     GIR_RootConstrainSelectedInstOperands,
     /* 273749 */     // GIR_Coverage, 12316,
     /* 273749 */     GIR_EraseRootFromParent_Done,
     /* 273750 */   // Label 5296: @273750
     /* 273750 */   GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(273792), // Rule ID 12317 //
     /* 273755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273758 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 273763 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273766 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 273769 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 273772 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273779 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1813:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_H),
     /* 273782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273784 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273786 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273788 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273790 */     GIR_RootConstrainSelectedInstOperands,
     /* 273791 */     // GIR_Coverage, 12317,
     /* 273791 */     GIR_EraseRootFromParent_Done,
     /* 273792 */   // Label 5297: @273792
     /* 273792 */   GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(273834), // Rule ID 12318 //
     /* 273797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 273805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273814 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273821 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1813:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_S),
     /* 273824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273830 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273832 */     GIR_RootConstrainSelectedInstOperands,
     /* 273833 */     // GIR_Coverage, 12318,
     /* 273833 */     GIR_EraseRootFromParent_Done,
     /* 273834 */   // Label 5298: @273834
     /* 273834 */   GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(273876), // Rule ID 12319 //
     /* 273839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqadd),
     /* 273847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 273850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 273853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 273856 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 273859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273863 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1813:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 273863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZPmZ_D),
     /* 273866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273868 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273870 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273872 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273874 */     GIR_RootConstrainSelectedInstOperands,
     /* 273875 */     // GIR_Coverage, 12319,
     /* 273875 */     GIR_EraseRootFromParent_Done,
     /* 273876 */   // Label 5299: @273876
     /* 273876 */   GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(273918), // Rule ID 12320 //
     /* 273881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273884 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 273889 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 273892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 273895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 273898 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 273901 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273905 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2053:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 273905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_B),
     /* 273908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273912 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273914 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273916 */     GIR_RootConstrainSelectedInstOperands,
     /* 273917 */     // GIR_Coverage, 12320,
     /* 273917 */     GIR_EraseRootFromParent_Done,
     /* 273918 */   // Label 5300: @273918
     /* 273918 */   GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(273960), // Rule ID 12321 //
     /* 273923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 273931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 273934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 273937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 273940 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 273943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273947 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2053:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 273947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_H),
     /* 273950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273952 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273956 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 273958 */     GIR_RootConstrainSelectedInstOperands,
     /* 273959 */     // GIR_Coverage, 12321,
     /* 273959 */     GIR_EraseRootFromParent_Done,
     /* 273960 */   // Label 5301: @273960
     /* 273960 */   GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(274002), // Rule ID 12322 //
     /* 273965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 273968 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 273973 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 273976 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 273979 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 273982 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 273985 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 273989 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2053:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 273989 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_S),
     /* 273992 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 273994 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 273996 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 273998 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274000 */     GIR_RootConstrainSelectedInstOperands,
     /* 274001 */     // GIR_Coverage, 12322,
     /* 274001 */     GIR_EraseRootFromParent_Done,
     /* 274002 */   // Label 5302: @274002
     /* 274002 */   GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(274044), // Rule ID 12323 //
     /* 274007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqadd),
     /* 274015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274024 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274027 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274031 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2053:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZPmZ_D),
     /* 274034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274036 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274038 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274040 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274042 */     GIR_RootConstrainSelectedInstOperands,
     /* 274043 */     // GIR_Coverage, 12323,
     /* 274043 */     GIR_EraseRootFromParent_Done,
     /* 274044 */   // Label 5303: @274044
     /* 274044 */   GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(274086), // Rule ID 12324 //
     /* 274049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 274057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274066 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274073 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1902:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_B),
     /* 274076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274082 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274084 */     GIR_RootConstrainSelectedInstOperands,
     /* 274085 */     // GIR_Coverage, 12324,
     /* 274085 */     GIR_EraseRootFromParent_Done,
     /* 274086 */   // Label 5304: @274086
     /* 274086 */   GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(274128), // Rule ID 12325 //
     /* 274091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274094 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 274099 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274102 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274105 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274108 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274115 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1902:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_H),
     /* 274118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274120 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274122 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274124 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274126 */     GIR_RootConstrainSelectedInstOperands,
     /* 274127 */     // GIR_Coverage, 12325,
     /* 274127 */     GIR_EraseRootFromParent_Done,
     /* 274128 */   // Label 5305: @274128
     /* 274128 */   GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(274170), // Rule ID 12326 //
     /* 274133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274136 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 274141 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274144 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274147 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274150 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274153 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274157 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1902:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_S),
     /* 274160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274164 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274166 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274168 */     GIR_RootConstrainSelectedInstOperands,
     /* 274169 */     // GIR_Coverage, 12326,
     /* 274169 */     GIR_EraseRootFromParent_Done,
     /* 274170 */   // Label 5306: @274170
     /* 274170 */   GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(274212), // Rule ID 12327 //
     /* 274175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274178 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsub),
     /* 274183 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274186 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274189 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274192 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274195 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274199 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1902:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZPmZ_D),
     /* 274202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274206 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274208 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274210 */     GIR_RootConstrainSelectedInstOperands,
     /* 274211 */     // GIR_Coverage, 12327,
     /* 274211 */     GIR_EraseRootFromParent_Done,
     /* 274212 */   // Label 5307: @274212
     /* 274212 */   GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(274254), // Rule ID 12328 //
     /* 274217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 274225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274234 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274237 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274241 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2099:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSUB_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_B),
     /* 274244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274246 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274248 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274250 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274252 */     GIR_RootConstrainSelectedInstOperands,
     /* 274253 */     // GIR_Coverage, 12328,
     /* 274253 */     GIR_EraseRootFromParent_Done,
     /* 274254 */   // Label 5308: @274254
     /* 274254 */   GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(274296), // Rule ID 12329 //
     /* 274259 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274262 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 274267 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274270 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274273 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274276 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274283 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2099:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSUB_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_H),
     /* 274286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274292 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274294 */     GIR_RootConstrainSelectedInstOperands,
     /* 274295 */     // GIR_Coverage, 12329,
     /* 274295 */     GIR_EraseRootFromParent_Done,
     /* 274296 */   // Label 5309: @274296
     /* 274296 */   GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(274338), // Rule ID 12330 //
     /* 274301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274304 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 274309 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274312 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274315 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274318 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274325 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2099:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSUB_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_S),
     /* 274328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274334 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274336 */     GIR_RootConstrainSelectedInstOperands,
     /* 274337 */     // GIR_Coverage, 12330,
     /* 274337 */     GIR_EraseRootFromParent_Done,
     /* 274338 */   // Label 5310: @274338
     /* 274338 */   GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(274380), // Rule ID 12331 //
     /* 274343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274346 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsub),
     /* 274351 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274354 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274357 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274360 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274367 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2099:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSUB_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZPmZ_D),
     /* 274370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274372 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274374 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274376 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274378 */     GIR_RootConstrainSelectedInstOperands,
     /* 274379 */     // GIR_Coverage, 12331,
     /* 274379 */     GIR_EraseRootFromParent_Done,
     /* 274380 */   // Label 5311: @274380
     /* 274380 */   GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(274422), // Rule ID 12332 //
     /* 274385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 274393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274402 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274409 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1967:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SUQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_B),
     /* 274412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274418 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274420 */     GIR_RootConstrainSelectedInstOperands,
     /* 274421 */     // GIR_Coverage, 12332,
     /* 274421 */     GIR_EraseRootFromParent_Done,
     /* 274422 */   // Label 5312: @274422
     /* 274422 */   GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(274464), // Rule ID 12333 //
     /* 274427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274430 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 274435 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274444 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274447 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274451 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1967:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_H),
     /* 274454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274460 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274462 */     GIR_RootConstrainSelectedInstOperands,
     /* 274463 */     // GIR_Coverage, 12333,
     /* 274463 */     GIR_EraseRootFromParent_Done,
     /* 274464 */   // Label 5313: @274464
     /* 274464 */   GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(274506), // Rule ID 12334 //
     /* 274469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 274477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274483 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274486 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274489 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274493 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1967:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_S),
     /* 274496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274498 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274500 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274502 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274504 */     GIR_RootConstrainSelectedInstOperands,
     /* 274505 */     // GIR_Coverage, 12334,
     /* 274505 */     GIR_EraseRootFromParent_Done,
     /* 274506 */   // Label 5314: @274506
     /* 274506 */   GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(274548), // Rule ID 12335 //
     /* 274511 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274514 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_suqadd),
     /* 274519 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274522 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274525 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274528 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274535 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1967:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUQADD_ZPmZ_D),
     /* 274538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274544 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274546 */     GIR_RootConstrainSelectedInstOperands,
     /* 274547 */     // GIR_Coverage, 12335,
     /* 274547 */     GIR_EraseRootFromParent_Done,
     /* 274548 */   // Label 5315: @274548
     /* 274548 */   GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(274590), // Rule ID 12336 //
     /* 274553 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274556 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 274561 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274570 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274573 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274577 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2121:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (USQADD_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_B),
     /* 274580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274582 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274584 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274586 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274588 */     GIR_RootConstrainSelectedInstOperands,
     /* 274589 */     // GIR_Coverage, 12336,
     /* 274589 */     GIR_EraseRootFromParent_Done,
     /* 274590 */   // Label 5316: @274590
     /* 274590 */   GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(274632), // Rule ID 12337 //
     /* 274595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274598 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 274603 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274612 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274615 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274619 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2121:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (USQADD_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274619 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_H),
     /* 274622 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274624 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274626 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274628 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274630 */     GIR_RootConstrainSelectedInstOperands,
     /* 274631 */     // GIR_Coverage, 12337,
     /* 274631 */     GIR_EraseRootFromParent_Done,
     /* 274632 */   // Label 5317: @274632
     /* 274632 */   GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(274674), // Rule ID 12338 //
     /* 274637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 274645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274648 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274651 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274654 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274657 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274661 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2121:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (USQADD_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_S),
     /* 274664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274668 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274670 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274672 */     GIR_RootConstrainSelectedInstOperands,
     /* 274673 */     // GIR_Coverage, 12338,
     /* 274673 */     GIR_EraseRootFromParent_Done,
     /* 274674 */   // Label 5318: @274674
     /* 274674 */   GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(274716), // Rule ID 12339 //
     /* 274679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usqadd),
     /* 274687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274693 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274696 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274703 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2121:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (USQADD_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USQADD_ZPmZ_D),
     /* 274706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274708 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274710 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274712 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274714 */     GIR_RootConstrainSelectedInstOperands,
     /* 274715 */     // GIR_Coverage, 12339,
     /* 274715 */     GIR_EraseRootFromParent_Done,
     /* 274716 */   // Label 5319: @274716
     /* 274716 */   GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(274758), // Rule ID 12340 //
     /* 274721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274724 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 274729 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274738 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274741 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274745 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1905:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_B),
     /* 274748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274752 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274754 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274756 */     GIR_RootConstrainSelectedInstOperands,
     /* 274757 */     // GIR_Coverage, 12340,
     /* 274757 */     GIR_EraseRootFromParent_Done,
     /* 274758 */   // Label 5320: @274758
     /* 274758 */   GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(274800), // Rule ID 12341 //
     /* 274763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 274771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274780 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274787 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1905:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_H),
     /* 274790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274796 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274798 */     GIR_RootConstrainSelectedInstOperands,
     /* 274799 */     // GIR_Coverage, 12341,
     /* 274799 */     GIR_EraseRootFromParent_Done,
     /* 274800 */   // Label 5321: @274800
     /* 274800 */   GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(274842), // Rule ID 12342 //
     /* 274805 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274808 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 274813 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274816 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274819 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274822 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274825 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274829 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1905:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_S),
     /* 274832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274834 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274836 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274838 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274840 */     GIR_RootConstrainSelectedInstOperands,
     /* 274841 */     // GIR_Coverage, 12342,
     /* 274841 */     GIR_EraseRootFromParent_Done,
     /* 274842 */   // Label 5322: @274842
     /* 274842 */   GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(274884), // Rule ID 12343 //
     /* 274847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqsubr),
     /* 274855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 274858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 274861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 274864 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 274867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274871 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1905:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 274871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSUBR_ZPmZ_D),
     /* 274874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274876 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274878 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274880 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274882 */     GIR_RootConstrainSelectedInstOperands,
     /* 274883 */     // GIR_Coverage, 12343,
     /* 274883 */     GIR_EraseRootFromParent_Done,
     /* 274884 */   // Label 5323: @274884
     /* 274884 */   GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(274926), // Rule ID 12344 //
     /* 274889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 274897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 274900 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 274903 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 274906 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 274909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274913 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2102:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 274913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_B),
     /* 274916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274920 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274922 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274924 */     GIR_RootConstrainSelectedInstOperands,
     /* 274925 */     // GIR_Coverage, 12344,
     /* 274925 */     GIR_EraseRootFromParent_Done,
     /* 274926 */   // Label 5324: @274926
     /* 274926 */   GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(274968), // Rule ID 12345 //
     /* 274931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274934 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 274939 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 274942 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 274945 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 274948 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 274951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274955 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2102:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 274955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_H),
     /* 274958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 274960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 274962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 274964 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 274966 */     GIR_RootConstrainSelectedInstOperands,
     /* 274967 */     // GIR_Coverage, 12345,
     /* 274967 */     GIR_EraseRootFromParent_Done,
     /* 274968 */   // Label 5325: @274968
     /* 274968 */   GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(275010), // Rule ID 12346 //
     /* 274973 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 274976 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 274981 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 274984 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 274987 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 274990 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 274993 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 274997 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2102:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 274997 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_S),
     /* 275000 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275002 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275004 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275006 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275008 */     GIR_RootConstrainSelectedInstOperands,
     /* 275009 */     // GIR_Coverage, 12346,
     /* 275009 */     GIR_EraseRootFromParent_Done,
     /* 275010 */   // Label 5326: @275010
     /* 275010 */   GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(275052), // Rule ID 12347 //
     /* 275015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275018 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqsubr),
     /* 275023 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275032 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275039 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2102:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSUBR_ZPmZ_D),
     /* 275042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275046 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275048 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275050 */     GIR_RootConstrainSelectedInstOperands,
     /* 275051 */     // GIR_Coverage, 12347,
     /* 275051 */     GIR_EraseRootFromParent_Done,
     /* 275052 */   // Label 5327: @275052
     /* 275052 */   GIM_Try, /*On fail goto*//*Label 5328*/ GIMT_Encode4(275094), // Rule ID 12348 //
     /* 275057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 275065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275074 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275081 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1912:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_B),
     /* 275084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275086 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275090 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275092 */     GIR_RootConstrainSelectedInstOperands,
     /* 275093 */     // GIR_Coverage, 12348,
     /* 275093 */     GIR_EraseRootFromParent_Done,
     /* 275094 */   // Label 5328: @275094
     /* 275094 */   GIM_Try, /*On fail goto*//*Label 5329*/ GIMT_Encode4(275136), // Rule ID 12349 //
     /* 275099 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275102 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 275107 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275110 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275113 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275116 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275119 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275123 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1912:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_H),
     /* 275126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275128 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275130 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275132 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275134 */     GIR_RootConstrainSelectedInstOperands,
     /* 275135 */     // GIR_Coverage, 12349,
     /* 275135 */     GIR_EraseRootFromParent_Done,
     /* 275136 */   // Label 5329: @275136
     /* 275136 */   GIM_Try, /*On fail goto*//*Label 5330*/ GIMT_Encode4(275178), // Rule ID 12350 //
     /* 275141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275144 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 275149 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275152 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275155 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275158 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 275161 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275165 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1912:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 275165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_S),
     /* 275168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275170 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275172 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275174 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275176 */     GIR_RootConstrainSelectedInstOperands,
     /* 275177 */     // GIR_Coverage, 12350,
     /* 275177 */     GIR_EraseRootFromParent_Done,
     /* 275178 */   // Label 5330: @275178
     /* 275178 */   GIM_Try, /*On fail goto*//*Label 5331*/ GIMT_Encode4(275220), // Rule ID 12351 //
     /* 275183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl),
     /* 275191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275200 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275203 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275207 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1912:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275207 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPmZ_D),
     /* 275210 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275212 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275214 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275216 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275218 */     GIR_RootConstrainSelectedInstOperands,
     /* 275219 */     // GIR_Coverage, 12351,
     /* 275219 */     GIR_EraseRootFromParent_Done,
     /* 275220 */   // Label 5331: @275220
     /* 275220 */   GIM_Try, /*On fail goto*//*Label 5332*/ GIMT_Encode4(275262), // Rule ID 12352 //
     /* 275225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275228 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 275233 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275242 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275249 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2107:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (URSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_B),
     /* 275252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275258 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275260 */     GIR_RootConstrainSelectedInstOperands,
     /* 275261 */     // GIR_Coverage, 12352,
     /* 275261 */     GIR_EraseRootFromParent_Done,
     /* 275262 */   // Label 5332: @275262
     /* 275262 */   GIM_Try, /*On fail goto*//*Label 5333*/ GIMT_Encode4(275304), // Rule ID 12353 //
     /* 275267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 275275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275284 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275287 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275291 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2107:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (URSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_H),
     /* 275294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275296 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275300 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275302 */     GIR_RootConstrainSelectedInstOperands,
     /* 275303 */     // GIR_Coverage, 12353,
     /* 275303 */     GIR_EraseRootFromParent_Done,
     /* 275304 */   // Label 5333: @275304
     /* 275304 */   GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(275346), // Rule ID 12354 //
     /* 275309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275312 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 275317 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275320 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275323 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275326 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 275329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275333 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2107:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 275333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_S),
     /* 275336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275338 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275340 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275342 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275344 */     GIR_RootConstrainSelectedInstOperands,
     /* 275345 */     // GIR_Coverage, 12354,
     /* 275345 */     GIR_EraseRootFromParent_Done,
     /* 275346 */   // Label 5334: @275346
     /* 275346 */   GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(275388), // Rule ID 12355 //
     /* 275351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275354 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl),
     /* 275359 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275375 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2107:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (URSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPmZ_D),
     /* 275378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275380 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275382 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275384 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275386 */     GIR_RootConstrainSelectedInstOperands,
     /* 275387 */     // GIR_Coverage, 12355,
     /* 275387 */     GIR_EraseRootFromParent_Done,
     /* 275388 */   // Label 5335: @275388
     /* 275388 */   GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(275430), // Rule ID 12356 //
     /* 275393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 275401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275407 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275410 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275417 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1895:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_B),
     /* 275420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275422 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275424 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275426 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275428 */     GIR_RootConstrainSelectedInstOperands,
     /* 275429 */     // GIR_Coverage, 12356,
     /* 275429 */     GIR_EraseRootFromParent_Done,
     /* 275430 */   // Label 5336: @275430
     /* 275430 */   GIM_Try, /*On fail goto*//*Label 5337*/ GIMT_Encode4(275472), // Rule ID 12357 //
     /* 275435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 275443 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275452 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275459 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1895:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_H),
     /* 275462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275464 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275468 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275470 */     GIR_RootConstrainSelectedInstOperands,
     /* 275471 */     // GIR_Coverage, 12357,
     /* 275471 */     GIR_EraseRootFromParent_Done,
     /* 275472 */   // Label 5337: @275472
     /* 275472 */   GIM_Try, /*On fail goto*//*Label 5338*/ GIMT_Encode4(275514), // Rule ID 12358 //
     /* 275477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 275485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275494 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 275497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275501 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1895:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 275501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_S),
     /* 275504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275508 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275510 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275512 */     GIR_RootConstrainSelectedInstOperands,
     /* 275513 */     // GIR_Coverage, 12358,
     /* 275513 */     GIR_EraseRootFromParent_Done,
     /* 275514 */   // Label 5338: @275514
     /* 275514 */   GIM_Try, /*On fail goto*//*Label 5339*/ GIMT_Encode4(275556), // Rule ID 12359 //
     /* 275519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl),
     /* 275527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275543 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1895:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPmZ_D),
     /* 275546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275552 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275554 */     GIR_RootConstrainSelectedInstOperands,
     /* 275555 */     // GIR_Coverage, 12359,
     /* 275555 */     GIR_EraseRootFromParent_Done,
     /* 275556 */   // Label 5339: @275556
     /* 275556 */   GIM_Try, /*On fail goto*//*Label 5340*/ GIMT_Encode4(275598), // Rule ID 12360 //
     /* 275561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275564 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 275569 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275572 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275575 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275578 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275581 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275585 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2095:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_B),
     /* 275588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275590 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275592 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275594 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275596 */     GIR_RootConstrainSelectedInstOperands,
     /* 275597 */     // GIR_Coverage, 12360,
     /* 275597 */     GIR_EraseRootFromParent_Done,
     /* 275598 */   // Label 5340: @275598
     /* 275598 */   GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(275640), // Rule ID 12361 //
     /* 275603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 275611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275620 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275627 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2095:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_H),
     /* 275630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275636 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275638 */     GIR_RootConstrainSelectedInstOperands,
     /* 275639 */     // GIR_Coverage, 12361,
     /* 275639 */     GIR_EraseRootFromParent_Done,
     /* 275640 */   // Label 5341: @275640
     /* 275640 */   GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(275682), // Rule ID 12362 //
     /* 275645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 275653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275662 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 275665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275669 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2095:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 275669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_S),
     /* 275672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275674 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275676 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275678 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275680 */     GIR_RootConstrainSelectedInstOperands,
     /* 275681 */     // GIR_Coverage, 12362,
     /* 275681 */     GIR_EraseRootFromParent_Done,
     /* 275682 */   // Label 5342: @275682
     /* 275682 */   GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(275724), // Rule ID 12363 //
     /* 275687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275690 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl),
     /* 275695 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275704 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275711 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2095:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPmZ_D),
     /* 275714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275716 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275718 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275720 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275722 */     GIR_RootConstrainSelectedInstOperands,
     /* 275723 */     // GIR_Coverage, 12363,
     /* 275723 */     GIR_EraseRootFromParent_Done,
     /* 275724 */   // Label 5343: @275724
     /* 275724 */   GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(275766), // Rule ID 12364 //
     /* 275729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275732 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 275737 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275740 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275743 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275746 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275753 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1881:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_B),
     /* 275756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275762 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275764 */     GIR_RootConstrainSelectedInstOperands,
     /* 275765 */     // GIR_Coverage, 12364,
     /* 275765 */     GIR_EraseRootFromParent_Done,
     /* 275766 */   // Label 5344: @275766
     /* 275766 */   GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(275808), // Rule ID 12365 //
     /* 275771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275774 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 275779 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275788 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275795 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1881:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275795 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_H),
     /* 275798 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275800 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275802 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275804 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275806 */     GIR_RootConstrainSelectedInstOperands,
     /* 275807 */     // GIR_Coverage, 12365,
     /* 275807 */     GIR_EraseRootFromParent_Done,
     /* 275808 */   // Label 5345: @275808
     /* 275808 */   GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(275850), // Rule ID 12366 //
     /* 275813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275816 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 275821 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275824 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275827 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275830 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 275833 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275837 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1881:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 275837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_S),
     /* 275840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275842 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275844 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275846 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275848 */     GIR_RootConstrainSelectedInstOperands,
     /* 275849 */     // GIR_Coverage, 12366,
     /* 275849 */     GIR_EraseRootFromParent_Done,
     /* 275850 */   // Label 5346: @275850
     /* 275850 */   GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(275892), // Rule ID 12367 //
     /* 275855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl),
     /* 275863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 275866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 275869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 275872 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 275875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275879 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1881:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 275879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPmZ_D),
     /* 275882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275884 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275886 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275888 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275890 */     GIR_RootConstrainSelectedInstOperands,
     /* 275891 */     // GIR_Coverage, 12367,
     /* 275891 */     GIR_EraseRootFromParent_Done,
     /* 275892 */   // Label 5347: @275892
     /* 275892 */   GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(275934), // Rule ID 12368 //
     /* 275897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 275905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 275908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 275911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 275914 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 275917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275921 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2087:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQRSHL_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 275921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_B),
     /* 275924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275926 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275928 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275930 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275932 */     GIR_RootConstrainSelectedInstOperands,
     /* 275933 */     // GIR_Coverage, 12368,
     /* 275933 */     GIR_EraseRootFromParent_Done,
     /* 275934 */   // Label 5348: @275934
     /* 275934 */   GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(275976), // Rule ID 12369 //
     /* 275939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275942 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 275947 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 275950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 275953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 275956 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 275959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 275963 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2087:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQRSHL_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 275963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_H),
     /* 275966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 275968 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 275970 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 275972 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 275974 */     GIR_RootConstrainSelectedInstOperands,
     /* 275975 */     // GIR_Coverage, 12369,
     /* 275975 */     GIR_EraseRootFromParent_Done,
     /* 275976 */   // Label 5349: @275976
     /* 275976 */   GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(276018), // Rule ID 12370 //
     /* 275981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 275984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 275989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 275992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 275995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 275998 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276001 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276005 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2087:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQRSHL_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_S),
     /* 276008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 276010 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276012 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276014 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276016 */     GIR_RootConstrainSelectedInstOperands,
     /* 276017 */     // GIR_Coverage, 12370,
     /* 276017 */     GIR_EraseRootFromParent_Done,
     /* 276018 */   // Label 5350: @276018
     /* 276018 */   GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(276060), // Rule ID 12371 //
     /* 276023 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276026 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl),
     /* 276031 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276034 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276037 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276040 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276047 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2087:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQRSHL_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPmZ_D),
     /* 276050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 276052 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276054 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276056 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276058 */     GIR_RootConstrainSelectedInstOperands,
     /* 276059 */     // GIR_Coverage, 12371,
     /* 276059 */     GIR_EraseRootFromParent_Done,
     /* 276060 */   // Label 5351: @276060
     /* 276060 */   GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(276102), // Rule ID 12372 //
     /* 276065 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276068 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl_u),
     /* 276073 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276076 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276079 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276082 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276089 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1915:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SRSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPZZ_B_UNDEF),
     /* 276092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276098 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276100 */     GIR_RootConstrainSelectedInstOperands,
     /* 276101 */     // GIR_Coverage, 12372,
     /* 276101 */     GIR_EraseRootFromParent_Done,
     /* 276102 */   // Label 5352: @276102
     /* 276102 */   GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(276144), // Rule ID 12373 //
     /* 276107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl_u),
     /* 276115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276124 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276127 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276131 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1915:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SRSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276131 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPZZ_H_UNDEF),
     /* 276134 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276138 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276140 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276142 */     GIR_RootConstrainSelectedInstOperands,
     /* 276143 */     // GIR_Coverage, 12373,
     /* 276143 */     GIR_EraseRootFromParent_Done,
     /* 276144 */   // Label 5353: @276144
     /* 276144 */   GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(276186), // Rule ID 12374 //
     /* 276149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl_u),
     /* 276157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 276166 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276173 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1915:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SRSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPZZ_S_UNDEF),
     /* 276176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276178 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276180 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276182 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276184 */     GIR_RootConstrainSelectedInstOperands,
     /* 276185 */     // GIR_Coverage, 12374,
     /* 276185 */     GIR_EraseRootFromParent_Done,
     /* 276186 */   // Label 5354: @276186
     /* 276186 */   GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(276228), // Rule ID 12375 //
     /* 276191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276194 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_srshl_u),
     /* 276199 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276208 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276215 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1915:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SRSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SRSHL_ZPZZ_D_UNDEF),
     /* 276218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276220 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276222 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276224 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276226 */     GIR_RootConstrainSelectedInstOperands,
     /* 276227 */     // GIR_Coverage, 12375,
     /* 276227 */     GIR_EraseRootFromParent_Done,
     /* 276228 */   // Label 5355: @276228
     /* 276228 */   GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(276270), // Rule ID 12376 //
     /* 276233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276236 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl_u),
     /* 276241 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276244 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276247 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276250 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276257 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2110:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (URSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPZZ_B_UNDEF),
     /* 276260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276266 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276268 */     GIR_RootConstrainSelectedInstOperands,
     /* 276269 */     // GIR_Coverage, 12376,
     /* 276269 */     GIR_EraseRootFromParent_Done,
     /* 276270 */   // Label 5356: @276270
     /* 276270 */   GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(276312), // Rule ID 12377 //
     /* 276275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl_u),
     /* 276283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276299 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2110:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (URSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPZZ_H_UNDEF),
     /* 276302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276304 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276308 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276310 */     GIR_RootConstrainSelectedInstOperands,
     /* 276311 */     // GIR_Coverage, 12377,
     /* 276311 */     GIR_EraseRootFromParent_Done,
     /* 276312 */   // Label 5357: @276312
     /* 276312 */   GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(276354), // Rule ID 12378 //
     /* 276317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276320 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl_u),
     /* 276325 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276328 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276331 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 276334 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276337 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276341 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2110:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (URSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPZZ_S_UNDEF),
     /* 276344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276346 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276348 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276350 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276352 */     GIR_RootConstrainSelectedInstOperands,
     /* 276353 */     // GIR_Coverage, 12378,
     /* 276353 */     GIR_EraseRootFromParent_Done,
     /* 276354 */   // Label 5358: @276354
     /* 276354 */   GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(276396), // Rule ID 12379 //
     /* 276359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_urshl_u),
     /* 276367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276376 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276379 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276383 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2110:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (URSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::URSHL_ZPZZ_D_UNDEF),
     /* 276386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276388 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276392 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276394 */     GIR_RootConstrainSelectedInstOperands,
     /* 276395 */     // GIR_Coverage, 12379,
     /* 276395 */     GIR_EraseRootFromParent_Done,
     /* 276396 */   // Label 5359: @276396
     /* 276396 */   GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(276438), // Rule ID 12380 //
     /* 276401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276404 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl_u),
     /* 276409 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276412 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276415 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276418 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276421 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276425 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1896:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPZZ_B_UNDEF),
     /* 276428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276430 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276432 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276434 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276436 */     GIR_RootConstrainSelectedInstOperands,
     /* 276437 */     // GIR_Coverage, 12380,
     /* 276437 */     GIR_EraseRootFromParent_Done,
     /* 276438 */   // Label 5360: @276438
     /* 276438 */   GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(276480), // Rule ID 12381 //
     /* 276443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276446 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl_u),
     /* 276451 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276454 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276457 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276460 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276463 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276467 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1896:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPZZ_H_UNDEF),
     /* 276470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276472 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276474 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276476 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276478 */     GIR_RootConstrainSelectedInstOperands,
     /* 276479 */     // GIR_Coverage, 12381,
     /* 276479 */     GIR_EraseRootFromParent_Done,
     /* 276480 */   // Label 5361: @276480
     /* 276480 */   GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(276522), // Rule ID 12382 //
     /* 276485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276488 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl_u),
     /* 276493 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276496 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276499 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 276502 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276505 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276509 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1896:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPZZ_S_UNDEF),
     /* 276512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276518 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276520 */     GIR_RootConstrainSelectedInstOperands,
     /* 276521 */     // GIR_Coverage, 12382,
     /* 276521 */     GIR_EraseRootFromParent_Done,
     /* 276522 */   // Label 5362: @276522
     /* 276522 */   GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(276564), // Rule ID 12383 //
     /* 276527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqshl_u),
     /* 276535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276544 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276551 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1896:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHL_ZPZZ_D_UNDEF),
     /* 276554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276556 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276558 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276560 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276562 */     GIR_RootConstrainSelectedInstOperands,
     /* 276563 */     // GIR_Coverage, 12383,
     /* 276563 */     GIR_EraseRootFromParent_Done,
     /* 276564 */   // Label 5363: @276564
     /* 276564 */   GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(276606), // Rule ID 12384 //
     /* 276569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276572 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl_u),
     /* 276577 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276580 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276583 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276586 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276593 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2096:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPZZ_B_UNDEF),
     /* 276596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276602 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276604 */     GIR_RootConstrainSelectedInstOperands,
     /* 276605 */     // GIR_Coverage, 12384,
     /* 276605 */     GIR_EraseRootFromParent_Done,
     /* 276606 */   // Label 5364: @276606
     /* 276606 */   GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(276648), // Rule ID 12385 //
     /* 276611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl_u),
     /* 276619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276628 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276635 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2096:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPZZ_H_UNDEF),
     /* 276638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276640 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276642 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276644 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276646 */     GIR_RootConstrainSelectedInstOperands,
     /* 276647 */     // GIR_Coverage, 12385,
     /* 276647 */     GIR_EraseRootFromParent_Done,
     /* 276648 */   // Label 5365: @276648
     /* 276648 */   GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(276690), // Rule ID 12386 //
     /* 276653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl_u),
     /* 276661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 276670 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276677 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2096:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276677 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPZZ_S_UNDEF),
     /* 276680 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276682 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276686 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276688 */     GIR_RootConstrainSelectedInstOperands,
     /* 276689 */     // GIR_Coverage, 12386,
     /* 276689 */     GIR_EraseRootFromParent_Done,
     /* 276690 */   // Label 5366: @276690
     /* 276690 */   GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(276732), // Rule ID 12387 //
     /* 276695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276698 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqshl_u),
     /* 276703 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276709 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276712 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276719 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2096:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHL_ZPZZ_D_UNDEF),
     /* 276722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276726 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276728 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276730 */     GIR_RootConstrainSelectedInstOperands,
     /* 276731 */     // GIR_Coverage, 12387,
     /* 276731 */     GIR_EraseRootFromParent_Done,
     /* 276732 */   // Label 5367: @276732
     /* 276732 */   GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(276774), // Rule ID 12388 //
     /* 276737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl_u),
     /* 276745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276754 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276757 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276761 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1882:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SQRSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPZZ_B_UNDEF),
     /* 276764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276766 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276768 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276770 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276772 */     GIR_RootConstrainSelectedInstOperands,
     /* 276773 */     // GIR_Coverage, 12388,
     /* 276773 */     GIR_EraseRootFromParent_Done,
     /* 276774 */   // Label 5368: @276774
     /* 276774 */   GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(276816), // Rule ID 12389 //
     /* 276779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276782 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl_u),
     /* 276787 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276790 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276793 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276796 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276803 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1882:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SQRSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276803 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPZZ_H_UNDEF),
     /* 276806 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276808 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276812 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276814 */     GIR_RootConstrainSelectedInstOperands,
     /* 276815 */     // GIR_Coverage, 12389,
     /* 276815 */     GIR_EraseRootFromParent_Done,
     /* 276816 */   // Label 5369: @276816
     /* 276816 */   GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(276858), // Rule ID 12390 //
     /* 276821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276824 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl_u),
     /* 276829 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 276832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 276835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 276838 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 276841 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276845 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1882:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SQRSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 276845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPZZ_S_UNDEF),
     /* 276848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276852 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276854 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276856 */     GIR_RootConstrainSelectedInstOperands,
     /* 276857 */     // GIR_Coverage, 12390,
     /* 276857 */     GIR_EraseRootFromParent_Done,
     /* 276858 */   // Label 5370: @276858
     /* 276858 */   GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(276900), // Rule ID 12391 //
     /* 276863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276866 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrshl_u),
     /* 276871 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 276874 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 276877 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 276880 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 276883 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276887 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1882:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SQRSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 276887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHL_ZPZZ_D_UNDEF),
     /* 276890 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276896 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276898 */     GIR_RootConstrainSelectedInstOperands,
     /* 276899 */     // GIR_Coverage, 12391,
     /* 276899 */     GIR_EraseRootFromParent_Done,
     /* 276900 */   // Label 5371: @276900
     /* 276900 */   GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(276942), // Rule ID 12392 //
     /* 276905 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276908 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl_u),
     /* 276913 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 276916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 276919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 276922 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 276925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276929 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 2088:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UQRSHL_ZPZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 276929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPZZ_B_UNDEF),
     /* 276932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276938 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276940 */     GIR_RootConstrainSelectedInstOperands,
     /* 276941 */     // GIR_Coverage, 12392,
     /* 276941 */     GIR_EraseRootFromParent_Done,
     /* 276942 */   // Label 5372: @276942
     /* 276942 */   GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(276984), // Rule ID 12393 //
     /* 276947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl_u),
     /* 276955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 276958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 276961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 276964 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 276967 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 276971 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 2088:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UQRSHL_ZPZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 276971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPZZ_H_UNDEF),
     /* 276974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 276976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 276978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 276980 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 276982 */     GIR_RootConstrainSelectedInstOperands,
     /* 276983 */     // GIR_Coverage, 12393,
     /* 276983 */     GIR_EraseRootFromParent_Done,
     /* 276984 */   // Label 5373: @276984
     /* 276984 */   GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(277026), // Rule ID 12394 //
     /* 276989 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 276992 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl_u),
     /* 276997 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277000 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 277003 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277006 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277013 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2088:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UQRSHL_ZPZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPZZ_S_UNDEF),
     /* 277016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 277018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277022 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277024 */     GIR_RootConstrainSelectedInstOperands,
     /* 277025 */     // GIR_Coverage, 12394,
     /* 277025 */     GIR_EraseRootFromParent_Done,
     /* 277026 */   // Label 5374: @277026
     /* 277026 */   GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(277068), // Rule ID 12395 //
     /* 277031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uqrshl_u),
     /* 277039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277042 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 277045 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277048 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277055 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2088:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UQRSHL_ZPZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHL_ZPZZ_D_UNDEF),
     /* 277058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 277060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277064 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277066 */     GIR_RootConstrainSelectedInstOperands,
     /* 277067 */     // GIR_Coverage, 12395,
     /* 277067 */     GIR_EraseRootFromParent_Done,
     /* 277068 */   // Label 5375: @277068
     /* 277068 */   GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(277110), // Rule ID 12552 //
     /* 277073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 277081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 277084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 277087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 277090 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277097 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1986:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABA_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 277097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_B),
     /* 277100 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277106 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277108 */     GIR_RootConstrainSelectedInstOperands,
     /* 277109 */     // GIR_Coverage, 12552,
     /* 277109 */     GIR_EraseRootFromParent_Done,
     /* 277110 */   // Label 5376: @277110
     /* 277110 */   GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(277152), // Rule ID 12554 //
     /* 277115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 277123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 277126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 277129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 277132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277139 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1986:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABA_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 277139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_H),
     /* 277142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277148 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277150 */     GIR_RootConstrainSelectedInstOperands,
     /* 277151 */     // GIR_Coverage, 12554,
     /* 277151 */     GIR_EraseRootFromParent_Done,
     /* 277152 */   // Label 5377: @277152
     /* 277152 */   GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(277194), // Rule ID 12556 //
     /* 277157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 277165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277174 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277181 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1986:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABA_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_S),
     /* 277184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277190 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277192 */     GIR_RootConstrainSelectedInstOperands,
     /* 277193 */     // GIR_Coverage, 12556,
     /* 277193 */     GIR_EraseRootFromParent_Done,
     /* 277194 */   // Label 5378: @277194
     /* 277194 */   GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(277236), // Rule ID 12558 //
     /* 277199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277202 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uaba),
     /* 277207 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277210 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277213 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277216 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277223 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1986:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UABA_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABA_ZZZ_D),
     /* 277226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277232 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277234 */     GIR_RootConstrainSelectedInstOperands,
     /* 277235 */     // GIR_Coverage, 12558,
     /* 277235 */     GIR_EraseRootFromParent_Done,
     /* 277236 */   // Label 5379: @277236
     /* 277236 */   GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(277278), // Rule ID 12560 //
     /* 277241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 277249 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 277252 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 277255 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 277258 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277265 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1734:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 277265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_H),
     /* 277268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277274 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277276 */     GIR_RootConstrainSelectedInstOperands,
     /* 277277 */     // GIR_Coverage, 12560,
     /* 277277 */     GIR_EraseRootFromParent_Done,
     /* 277278 */   // Label 5380: @277278
     /* 277278 */   GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(277320), // Rule ID 12561 //
     /* 277283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277286 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 277291 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277294 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277297 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 277300 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277303 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277307 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1734:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 277307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_S),
     /* 277310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277316 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277318 */     GIR_RootConstrainSelectedInstOperands,
     /* 277319 */     // GIR_Coverage, 12561,
     /* 277319 */     GIR_EraseRootFromParent_Done,
     /* 277320 */   // Label 5381: @277320
     /* 277320 */   GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(277362), // Rule ID 12562 //
     /* 277325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277328 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sabalt),
     /* 277333 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277336 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277339 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277342 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277349 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1734:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABALT_ZZZ_D),
     /* 277352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277354 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277356 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277358 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277360 */     GIR_RootConstrainSelectedInstOperands,
     /* 277361 */     // GIR_Coverage, 12562,
     /* 277361 */     GIR_EraseRootFromParent_Done,
     /* 277362 */   // Label 5382: @277362
     /* 277362 */   GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(277404), // Rule ID 12563 //
     /* 277367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 277375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 277378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 277381 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 277384 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277391 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1987:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABALB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 277391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_H),
     /* 277394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277400 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277402 */     GIR_RootConstrainSelectedInstOperands,
     /* 277403 */     // GIR_Coverage, 12563,
     /* 277403 */     GIR_EraseRootFromParent_Done,
     /* 277404 */   // Label 5383: @277404
     /* 277404 */   GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(277446), // Rule ID 12564 //
     /* 277409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 277417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 277426 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277433 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1987:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABALB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 277433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_S),
     /* 277436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277442 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277444 */     GIR_RootConstrainSelectedInstOperands,
     /* 277445 */     // GIR_Coverage, 12564,
     /* 277445 */     GIR_EraseRootFromParent_Done,
     /* 277446 */   // Label 5384: @277446
     /* 277446 */   GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(277488), // Rule ID 12565 //
     /* 277451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277454 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalb),
     /* 277459 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277462 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277465 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277468 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277471 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277475 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1987:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABALB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALB_ZZZ_D),
     /* 277478 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277484 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277486 */     GIR_RootConstrainSelectedInstOperands,
     /* 277487 */     // GIR_Coverage, 12565,
     /* 277487 */     GIR_EraseRootFromParent_Done,
     /* 277488 */   // Label 5385: @277488
     /* 277488 */   GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(277530), // Rule ID 12566 //
     /* 277493 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 277501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 277504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 277507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 277510 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 277513 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277517 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1988:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UABALT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 277517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_H),
     /* 277520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277526 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277528 */     GIR_RootConstrainSelectedInstOperands,
     /* 277529 */     // GIR_Coverage, 12566,
     /* 277529 */     GIR_EraseRootFromParent_Done,
     /* 277530 */   // Label 5386: @277530
     /* 277530 */   GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(277572), // Rule ID 12567 //
     /* 277535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277538 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 277543 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277549 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 277552 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277555 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277559 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1988:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UABALT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 277559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_S),
     /* 277562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277568 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277570 */     GIR_RootConstrainSelectedInstOperands,
     /* 277571 */     // GIR_Coverage, 12567,
     /* 277571 */     GIR_EraseRootFromParent_Done,
     /* 277572 */   // Label 5387: @277572
     /* 277572 */   GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(277614), // Rule ID 12568 //
     /* 277577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uabalt),
     /* 277585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277594 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277597 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277601 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1988:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UABALT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABALT_ZZZ_D),
     /* 277604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277610 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277612 */     GIR_RootConstrainSelectedInstOperands,
     /* 277613 */     // GIR_Coverage, 12568,
     /* 277613 */     GIR_EraseRootFromParent_Done,
     /* 277614 */   // Label 5388: @277614
     /* 277614 */   GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(277656), // Rule ID 12569 //
     /* 277619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
     /* 277627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277636 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277643 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1268:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (ADCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_S),
     /* 277646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277652 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277654 */     GIR_RootConstrainSelectedInstOperands,
     /* 277655 */     // GIR_Coverage, 12569,
     /* 277655 */     GIR_EraseRootFromParent_Done,
     /* 277656 */   // Label 5389: @277656
     /* 277656 */   GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(277698), // Rule ID 12570 //
     /* 277661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277664 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_adclt),
     /* 277669 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277672 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277675 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277678 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277685 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1268:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (ADCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADCLT_ZZZ_D),
     /* 277688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277694 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277696 */     GIR_RootConstrainSelectedInstOperands,
     /* 277697 */     // GIR_Coverage, 12570,
     /* 277697 */     GIR_EraseRootFromParent_Done,
     /* 277698 */   // Label 5390: @277698
     /* 277698 */   GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(277740), // Rule ID 12571 //
     /* 277703 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277706 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
     /* 277711 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277714 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277717 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277720 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277727 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1746:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SBCLB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_S),
     /* 277730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277736 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277738 */     GIR_RootConstrainSelectedInstOperands,
     /* 277739 */     // GIR_Coverage, 12571,
     /* 277739 */     GIR_EraseRootFromParent_Done,
     /* 277740 */   // Label 5391: @277740
     /* 277740 */   GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(277782), // Rule ID 12572 //
     /* 277745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclb),
     /* 277753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277762 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277769 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1746:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SBCLB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLB_ZZZ_D),
     /* 277772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277778 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277780 */     GIR_RootConstrainSelectedInstOperands,
     /* 277781 */     // GIR_Coverage, 12572,
     /* 277781 */     GIR_EraseRootFromParent_Done,
     /* 277782 */   // Label 5392: @277782
     /* 277782 */   GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(277824), // Rule ID 12573 //
     /* 277787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277790 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
     /* 277795 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277798 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277801 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277804 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277807 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277811 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1747:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SBCLT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_S),
     /* 277814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277820 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277822 */     GIR_RootConstrainSelectedInstOperands,
     /* 277823 */     // GIR_Coverage, 12573,
     /* 277823 */     GIR_EraseRootFromParent_Done,
     /* 277824 */   // Label 5393: @277824
     /* 277824 */   GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(277866), // Rule ID 12574 //
     /* 277829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277832 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sbclt),
     /* 277837 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 277840 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 277843 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277846 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277853 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1747:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SBCLT_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBCLT_ZZZ_D),
     /* 277856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 277858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277862 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277864 */     GIR_RootConstrainSelectedInstOperands,
     /* 277865 */     // GIR_Coverage, 12574,
     /* 277865 */     GIR_EraseRootFromParent_Done,
     /* 277866 */   // Label 5394: @277866
     /* 277866 */   GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(277908), // Rule ID 12629 //
     /* 277871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 277879 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 277882 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 277885 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 277888 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 277891 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277895 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1716:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (RADDHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 277895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_B),
     /* 277898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 277900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277904 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277906 */     GIR_RootConstrainSelectedInstOperands,
     /* 277907 */     // GIR_Coverage, 12629,
     /* 277907 */     GIR_EraseRootFromParent_Done,
     /* 277908 */   // Label 5395: @277908
     /* 277908 */   GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(277950), // Rule ID 12630 //
     /* 277913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277916 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 277921 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 277924 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 277927 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 277930 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 277933 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277937 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1716:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (RADDHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 277937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_H),
     /* 277940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 277942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277946 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277948 */     GIR_RootConstrainSelectedInstOperands,
     /* 277949 */     // GIR_Coverage, 12630,
     /* 277949 */     GIR_EraseRootFromParent_Done,
     /* 277950 */   // Label 5396: @277950
     /* 277950 */   GIM_Try, /*On fail goto*//*Label 5397*/ GIMT_Encode4(277992), // Rule ID 12631 //
     /* 277955 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 277958 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_raddhnt),
     /* 277963 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 277966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 277969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 277972 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 277975 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 277979 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1716:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (RADDHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 277979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RADDHNT_ZZZ_S),
     /* 277982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 277984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 277986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 277988 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 277990 */     GIR_RootConstrainSelectedInstOperands,
     /* 277991 */     // GIR_Coverage, 12631,
     /* 277991 */     GIR_EraseRootFromParent_Done,
     /* 277992 */   // Label 5397: @277992
     /* 277992 */   GIM_Try, /*On fail goto*//*Label 5398*/ GIMT_Encode4(278034), // Rule ID 12632 //
     /* 277997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 278005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 278008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 278011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278014 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278021 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1960:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 278021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_B),
     /* 278024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278030 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278032 */     GIR_RootConstrainSelectedInstOperands,
     /* 278033 */     // GIR_Coverage, 12632,
     /* 278033 */     GIR_EraseRootFromParent_Done,
     /* 278034 */   // Label 5398: @278034
     /* 278034 */   GIM_Try, /*On fail goto*//*Label 5399*/ GIMT_Encode4(278076), // Rule ID 12633 //
     /* 278039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278042 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 278047 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278050 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 278053 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278056 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278063 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1960:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 278063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_H),
     /* 278066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278072 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278074 */     GIR_RootConstrainSelectedInstOperands,
     /* 278075 */     // GIR_Coverage, 12633,
     /* 278075 */     GIR_EraseRootFromParent_Done,
     /* 278076 */   // Label 5399: @278076
     /* 278076 */   GIM_Try, /*On fail goto*//*Label 5400*/ GIMT_Encode4(278118), // Rule ID 12634 //
     /* 278081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278084 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_subhnt),
     /* 278089 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278092 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 278095 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278098 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278105 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1960:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 278105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNT_ZZZ_S),
     /* 278108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278114 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278116 */     GIR_RootConstrainSelectedInstOperands,
     /* 278117 */     // GIR_Coverage, 12634,
     /* 278117 */     GIR_EraseRootFromParent_Done,
     /* 278118 */   // Label 5400: @278118
     /* 278118 */   GIM_Try, /*On fail goto*//*Label 5401*/ GIMT_Encode4(278160), // Rule ID 12635 //
     /* 278123 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278126 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 278131 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 278134 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 278137 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278140 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278143 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278147 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1731:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (RSUBHNT_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 278147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_B),
     /* 278150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278152 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278156 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278158 */     GIR_RootConstrainSelectedInstOperands,
     /* 278159 */     // GIR_Coverage, 12635,
     /* 278159 */     GIR_EraseRootFromParent_Done,
     /* 278160 */   // Label 5401: @278160
     /* 278160 */   GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(278202), // Rule ID 12636 //
     /* 278165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 278173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 278179 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278182 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278189 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1731:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (RSUBHNT_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 278189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_H),
     /* 278192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278198 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278200 */     GIR_RootConstrainSelectedInstOperands,
     /* 278201 */     // GIR_Coverage, 12636,
     /* 278201 */     GIR_EraseRootFromParent_Done,
     /* 278202 */   // Label 5402: @278202
     /* 278202 */   GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(278244), // Rule ID 12637 //
     /* 278207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rsubhnt),
     /* 278215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 278221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278224 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278231 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1731:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (RSUBHNT_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 278231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RSUBHNT_ZZZ_S),
     /* 278234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278236 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278238 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278240 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278242 */     GIR_RootConstrainSelectedInstOperands,
     /* 278243 */     // GIR_Coverage, 12637,
     /* 278243 */     GIR_EraseRootFromParent_Done,
     /* 278244 */   // Label 5403: @278244
     /* 278244 */   GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(278289), // Rule ID 12650 //
     /* 278249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 278252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
     /* 278257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 278260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 278263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278266 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 278273 */     // (intrinsic_wo_chain:{ *:[nxv16i1] } 1665:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (NMATCH_PPzZZ_B:{ *:[nxv16i1] }:{ *:[i32] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 278273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_B),
     /* 278276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 278278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278280 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278282 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278284 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 278287 */     GIR_RootConstrainSelectedInstOperands,
     /* 278288 */     // GIR_Coverage, 12650,
     /* 278288 */     GIR_EraseRootFromParent_Done,
     /* 278289 */   // Label 5404: @278289
     /* 278289 */   GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(278334), // Rule ID 12651 //
     /* 278294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2),
     /* 278297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_nmatch),
     /* 278302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s1,
     /* 278305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278311 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 278318 */     // (intrinsic_wo_chain:{ *:[nxv8i1] } 1665:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (NMATCH_PPzZZ_H:{ *:[nxv8i1] }:{ *:[i32] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 278318 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::NMATCH_PPzZZ_H),
     /* 278321 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 278323 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278325 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278327 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278329 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 278332 */     GIR_RootConstrainSelectedInstOperands,
     /* 278333 */     // GIR_Coverage, 12651,
     /* 278333 */     GIR_EraseRootFromParent_Done,
     /* 278334 */   // Label 5405: @278334
     /* 278334 */   GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(278376), // Rule ID 12652 //
     /* 278339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 278347 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 278350 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 278353 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 278356 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 278359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278363 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1385:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (EORTB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 278363 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_B),
     /* 278366 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278368 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278370 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278372 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278374 */     GIR_RootConstrainSelectedInstOperands,
     /* 278375 */     // GIR_Coverage, 12652,
     /* 278375 */     GIR_EraseRootFromParent_Done,
     /* 278376 */   // Label 5406: @278376
     /* 278376 */   GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(278418), // Rule ID 12653 //
     /* 278381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278384 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 278389 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278392 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 278395 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278398 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278405 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1385:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (EORTB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 278405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_H),
     /* 278408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278410 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278412 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278414 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278416 */     GIR_RootConstrainSelectedInstOperands,
     /* 278417 */     // GIR_Coverage, 12653,
     /* 278417 */     GIR_EraseRootFromParent_Done,
     /* 278418 */   // Label 5407: @278418
     /* 278418 */   GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(278460), // Rule ID 12654 //
     /* 278423 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278426 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 278431 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278434 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 278437 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278440 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278443 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278447 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1385:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (EORTB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 278447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_S),
     /* 278450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278452 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278454 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278456 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278458 */     GIR_RootConstrainSelectedInstOperands,
     /* 278459 */     // GIR_Coverage, 12654,
     /* 278459 */     GIR_EraseRootFromParent_Done,
     /* 278460 */   // Label 5408: @278460
     /* 278460 */   GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(278502), // Rule ID 12655 //
     /* 278465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_eortb),
     /* 278473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 278476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 278479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278489 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1385:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (EORTB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 278489 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORTB_ZZZ_D),
     /* 278492 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 278494 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278496 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278498 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278500 */     GIR_RootConstrainSelectedInstOperands,
     /* 278501 */     // GIR_Coverage, 12655,
     /* 278501 */     GIR_EraseRootFromParent_Done,
     /* 278502 */   // Label 5409: @278502
     /* 278502 */   GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(278544), // Rule ID 12671 //
     /* 278507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 278515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278531 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1474:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMAXNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 278531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_H),
     /* 278534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278538 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278540 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278542 */     GIR_RootConstrainSelectedInstOperands,
     /* 278543 */     // GIR_Coverage, 12671,
     /* 278543 */     GIR_EraseRootFromParent_Done,
     /* 278544 */   // Label 5410: @278544
     /* 278544 */   GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(278586), // Rule ID 12672 //
     /* 278549 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278552 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 278557 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 278563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278566 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278573 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1474:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMAXNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 278573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_S),
     /* 278576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278578 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278580 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278582 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278584 */     GIR_RootConstrainSelectedInstOperands,
     /* 278585 */     // GIR_Coverage, 12672,
     /* 278585 */     GIR_EraseRootFromParent_Done,
     /* 278586 */   // Label 5411: @278586
     /* 278586 */   GIM_Try, /*On fail goto*//*Label 5412*/ GIMT_Encode4(278628), // Rule ID 12673 //
     /* 278591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278594 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxnmp),
     /* 278599 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 278602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 278605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278608 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278611 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278615 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1474:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMAXNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 278615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMP_ZPmZZ_D),
     /* 278618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278620 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278622 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278624 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278626 */     GIR_RootConstrainSelectedInstOperands,
     /* 278627 */     // GIR_Coverage, 12673,
     /* 278627 */     GIR_EraseRootFromParent_Done,
     /* 278628 */   // Label 5412: @278628
     /* 278628 */   GIM_Try, /*On fail goto*//*Label 5413*/ GIMT_Encode4(278670), // Rule ID 12674 //
     /* 278633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278636 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 278641 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278644 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278647 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278650 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278653 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278657 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1492:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMINNMP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 278657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_H),
     /* 278660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278666 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278668 */     GIR_RootConstrainSelectedInstOperands,
     /* 278669 */     // GIR_Coverage, 12674,
     /* 278669 */     GIR_EraseRootFromParent_Done,
     /* 278670 */   // Label 5413: @278670
     /* 278670 */   GIM_Try, /*On fail goto*//*Label 5414*/ GIMT_Encode4(278712), // Rule ID 12675 //
     /* 278675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 278683 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278686 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 278689 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278692 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278695 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278699 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1492:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMINNMP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 278699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_S),
     /* 278702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278704 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278706 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278708 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278710 */     GIR_RootConstrainSelectedInstOperands,
     /* 278711 */     // GIR_Coverage, 12675,
     /* 278711 */     GIR_EraseRootFromParent_Done,
     /* 278712 */   // Label 5414: @278712
     /* 278712 */   GIM_Try, /*On fail goto*//*Label 5415*/ GIMT_Encode4(278754), // Rule ID 12676 //
     /* 278717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278720 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminnmp),
     /* 278725 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 278728 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 278731 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278734 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278737 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278741 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1492:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMINNMP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 278741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMP_ZPmZZ_D),
     /* 278744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278746 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278750 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278752 */     GIR_RootConstrainSelectedInstOperands,
     /* 278753 */     // GIR_Coverage, 12676,
     /* 278753 */     GIR_EraseRootFromParent_Done,
     /* 278754 */   // Label 5415: @278754
     /* 278754 */   GIM_Try, /*On fail goto*//*Label 5416*/ GIMT_Encode4(278796), // Rule ID 12677 //
     /* 278759 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278762 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 278767 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278770 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278773 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278776 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278783 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1477:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMAXP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 278783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_H),
     /* 278786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278788 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278790 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278792 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278794 */     GIR_RootConstrainSelectedInstOperands,
     /* 278795 */     // GIR_Coverage, 12677,
     /* 278795 */     GIR_EraseRootFromParent_Done,
     /* 278796 */   // Label 5416: @278796
     /* 278796 */   GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(278838), // Rule ID 12678 //
     /* 278801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 278809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 278815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278818 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278821 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278825 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1477:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMAXP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 278825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_S),
     /* 278828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278830 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278832 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278834 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278836 */     GIR_RootConstrainSelectedInstOperands,
     /* 278837 */     // GIR_Coverage, 12678,
     /* 278837 */     GIR_EraseRootFromParent_Done,
     /* 278838 */   // Label 5417: @278838
     /* 278838 */   GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(278880), // Rule ID 12679 //
     /* 278843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmaxp),
     /* 278851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 278854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 278857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278860 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278867 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1477:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMAXP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 278867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAXP_ZPmZZ_D),
     /* 278870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278872 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278874 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278876 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278878 */     GIR_RootConstrainSelectedInstOperands,
     /* 278879 */     // GIR_Coverage, 12679,
     /* 278879 */     GIR_EraseRootFromParent_Done,
     /* 278880 */   // Label 5418: @278880
     /* 278880 */   GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(278922), // Rule ID 12680 //
     /* 278885 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278888 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 278893 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 278896 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 278899 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 278902 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 278905 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278909 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1495:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMINP_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 278909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_H),
     /* 278912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278914 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278916 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278918 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278920 */     GIR_RootConstrainSelectedInstOperands,
     /* 278921 */     // GIR_Coverage, 12680,
     /* 278921 */     GIR_EraseRootFromParent_Done,
     /* 278922 */   // Label 5419: @278922
     /* 278922 */   GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(278964), // Rule ID 12681 //
     /* 278927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 278935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 278938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 278941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 278944 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 278947 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278951 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1495:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FMINP_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 278951 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_S),
     /* 278954 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278956 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 278958 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 278960 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 278962 */     GIR_RootConstrainSelectedInstOperands,
     /* 278963 */     // GIR_Coverage, 12681,
     /* 278963 */     GIR_EraseRootFromParent_Done,
     /* 278964 */   // Label 5420: @278964
     /* 278964 */   GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(279006), // Rule ID 12682 //
     /* 278969 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 278972 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fminp),
     /* 278977 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 278980 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 278983 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 278986 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 278989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 278993 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1495:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FMINP_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 278993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINP_ZPmZZ_D),
     /* 278996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 278998 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279002 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279004 */     GIR_RootConstrainSelectedInstOperands,
     /* 279005 */     // GIR_Coverage, 12682,
     /* 279005 */     GIR_EraseRootFromParent_Done,
     /* 279006 */   // Label 5421: @279006
     /* 279006 */   GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(279048), // Rule ID 12687 //
     /* 279011 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279014 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb),
     /* 279019 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279028 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279035 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1501:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLALB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZ_SHH),
     /* 279038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279040 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279044 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279046 */     GIR_RootConstrainSelectedInstOperands,
     /* 279047 */     // GIR_Coverage, 12687,
     /* 279047 */     GIR_EraseRootFromParent_Done,
     /* 279048 */   // Label 5422: @279048
     /* 279048 */   GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(279090), // Rule ID 12688 //
     /* 279053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt),
     /* 279061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279064 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279067 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279070 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279073 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279077 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1503:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLALT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279077 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZ_SHH),
     /* 279080 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279082 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279084 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279086 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279088 */     GIR_RootConstrainSelectedInstOperands,
     /* 279089 */     // GIR_Coverage, 12688,
     /* 279089 */     GIR_EraseRootFromParent_Done,
     /* 279090 */   // Label 5423: @279090
     /* 279090 */   GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(279132), // Rule ID 12689 //
     /* 279095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279098 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb),
     /* 279103 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279106 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279109 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279112 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279119 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1508:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLSLB_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZ_SHH),
     /* 279122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279124 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279128 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279130 */     GIR_RootConstrainSelectedInstOperands,
     /* 279131 */     // GIR_Coverage, 12689,
     /* 279131 */     GIR_EraseRootFromParent_Done,
     /* 279132 */   // Label 5424: @279132
     /* 279132 */   GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(279174), // Rule ID 12690 //
     /* 279137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt),
     /* 279145 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279148 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279151 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279154 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279157 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279161 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1510:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FMLSLT_ZZZ_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZ_SHH),
     /* 279164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279166 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279168 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279170 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279172 */     GIR_RootConstrainSelectedInstOperands,
     /* 279173 */     // GIR_Coverage, 12690,
     /* 279173 */     GIR_EraseRootFromParent_Done,
     /* 279174 */   // Label 5425: @279174
     /* 279174 */   GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(279216), // Rule ID 12703 //
     /* 279179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279182 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 279187 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 279190 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 279193 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279196 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279203 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1302:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 279203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 279206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279208 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279210 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279212 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279214 */     GIR_RootConstrainSelectedInstOperands,
     /* 279215 */     // GIR_Coverage, 12703,
     /* 279215 */     GIR_EraseRootFromParent_Done,
     /* 279216 */   // Label 5426: @279216
     /* 279216 */   GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(279258), // Rule ID 12705 //
     /* 279221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 279229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279232 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 279235 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279238 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279245 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1302:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 279245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 279248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279250 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279254 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279256 */     GIR_RootConstrainSelectedInstOperands,
     /* 279257 */     // GIR_Coverage, 12705,
     /* 279257 */     GIR_EraseRootFromParent_Done,
     /* 279258 */   // Label 5427: @279258
     /* 279258 */   GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(279300), // Rule ID 12707 //
     /* 279263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 279271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 279280 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 279283 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279287 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1302:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 279287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 279290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279292 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279296 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279298 */     GIR_RootConstrainSelectedInstOperands,
     /* 279299 */     // GIR_Coverage, 12707,
     /* 279299 */     GIR_EraseRootFromParent_Done,
     /* 279300 */   // Label 5428: @279300
     /* 279300 */   GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(279342), // Rule ID 12709 //
     /* 279305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 279308 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_bcax),
     /* 279313 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 279316 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 279319 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 279322 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 279325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279329 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1302:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (BCAX_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 279329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BCAX_ZZZZ),
     /* 279332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279338 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279340 */     GIR_RootConstrainSelectedInstOperands,
     /* 279341 */     // GIR_Coverage, 12709,
     /* 279341 */     GIR_EraseRootFromParent_Done,
     /* 279342 */   // Label 5429: @279342
     /* 279342 */   GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(279384), // Rule ID 12968 //
     /* 279347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 279350 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 279355 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 279358 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 279361 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279364 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279371 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1999:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UCLAMP_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 279371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_B),
     /* 279374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279378 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279380 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279382 */     GIR_RootConstrainSelectedInstOperands,
     /* 279383 */     // GIR_Coverage, 12968,
     /* 279383 */     GIR_EraseRootFromParent_Done,
     /* 279384 */   // Label 5430: @279384
     /* 279384 */   GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(279426), // Rule ID 12970 //
     /* 279389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 279392 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 279397 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279400 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 279403 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279406 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279413 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1999:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UCLAMP_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 279413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_H),
     /* 279416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279422 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279424 */     GIR_RootConstrainSelectedInstOperands,
     /* 279425 */     // GIR_Coverage, 12970,
     /* 279425 */     GIR_EraseRootFromParent_Done,
     /* 279426 */   // Label 5431: @279426
     /* 279426 */   GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(279468), // Rule ID 12972 //
     /* 279431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 279434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 279439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 279448 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 279451 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279455 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1999:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (UCLAMP_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 279455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_S),
     /* 279458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279460 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279462 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279464 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279466 */     GIR_RootConstrainSelectedInstOperands,
     /* 279467 */     // GIR_Coverage, 12972,
     /* 279467 */     GIR_EraseRootFromParent_Done,
     /* 279468 */   // Label 5432: @279468
     /* 279468 */   GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(279510), // Rule ID 12974 //
     /* 279473 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME),
     /* 279476 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_uclamp),
     /* 279481 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 279484 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 279487 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 279490 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 279493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279497 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1999:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (UCLAMP_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 279497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCLAMP_ZZZ_D),
     /* 279500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279502 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279504 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279506 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279508 */     GIR_RootConstrainSelectedInstOperands,
     /* 279509 */     // GIR_Coverage, 12974,
     /* 279509 */     GIR_EraseRootFromParent_Done,
     /* 279510 */   // Label 5433: @279510
     /* 279510 */   GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(279552), // Rule ID 12976 //
     /* 279515 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 279518 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_x2),
     /* 279523 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279526 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279529 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279532 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279539 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1457:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FDOT_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_S),
     /* 279542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279548 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279550 */     GIR_RootConstrainSelectedInstOperands,
     /* 279551 */     // GIR_Coverage, 12976,
     /* 279551 */     GIR_EraseRootFromParent_Done,
     /* 279552 */   // Label 5434: @279552
     /* 279552 */   GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(279594), // Rule ID 12979 //
     /* 279557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 279560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_x2),
     /* 279565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279571 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279574 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279577 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279581 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2015:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UDOT_ZZZ_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 279581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_HtoS),
     /* 279584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 279586 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279588 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279590 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279592 */     GIR_RootConstrainSelectedInstOperands,
     /* 279593 */     // GIR_Coverage, 12979,
     /* 279593 */     GIR_EraseRootFromParent_Done,
     /* 279594 */   // Label 5435: @279594
     /* 279594 */   GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(279636), // Rule ID 13144 //
     /* 279599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 279610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 279613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 279616 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 279619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279623 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1975:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (TBXQ_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 279623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_B),
     /* 279626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279628 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279632 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279634 */     GIR_RootConstrainSelectedInstOperands,
     /* 279635 */     // GIR_Coverage, 13144,
     /* 279635 */     GIR_EraseRootFromParent_Done,
     /* 279636 */   // Label 5436: @279636
     /* 279636 */   GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(279678), // Rule ID 13145 //
     /* 279641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 279655 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279658 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279665 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1975:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBXQ_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 279665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
     /* 279668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279672 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279674 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279676 */     GIR_RootConstrainSelectedInstOperands,
     /* 279677 */     // GIR_Coverage, 13145,
     /* 279677 */     GIR_EraseRootFromParent_Done,
     /* 279678 */   // Label 5437: @279678
     /* 279678 */   GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(279720), // Rule ID 13146 //
     /* 279683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279686 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279691 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279694 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279697 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 279700 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 279703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279707 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1975:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBXQ_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 279707 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
     /* 279710 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279712 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279716 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279718 */     GIR_RootConstrainSelectedInstOperands,
     /* 279719 */     // GIR_Coverage, 13146,
     /* 279719 */     GIR_EraseRootFromParent_Done,
     /* 279720 */   // Label 5438: @279720
     /* 279720 */   GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(279762), // Rule ID 13147 //
     /* 279725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279728 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279733 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 279736 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 279739 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 279742 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 279745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279749 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1975:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBXQ_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 279749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
     /* 279752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279754 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279756 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279758 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279760 */     GIR_RootConstrainSelectedInstOperands,
     /* 279761 */     // GIR_Coverage, 13147,
     /* 279761 */     GIR_EraseRootFromParent_Done,
     /* 279762 */   // Label 5439: @279762
     /* 279762 */   GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(279804), // Rule ID 13148 //
     /* 279767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 279781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279784 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279787 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279791 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1975:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (TBXQ_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 279791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_H),
     /* 279794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279796 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279798 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279800 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279802 */     GIR_RootConstrainSelectedInstOperands,
     /* 279803 */     // GIR_Coverage, 13148,
     /* 279803 */     GIR_EraseRootFromParent_Done,
     /* 279804 */   // Label 5440: @279804
     /* 279804 */   GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(279846), // Rule ID 13149 //
     /* 279809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279812 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279817 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279820 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 279823 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 279826 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 279829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279833 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1975:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (TBXQ_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 279833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_S),
     /* 279836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279842 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279844 */     GIR_RootConstrainSelectedInstOperands,
     /* 279845 */     // GIR_Coverage, 13149,
     /* 279845 */     GIR_EraseRootFromParent_Done,
     /* 279846 */   // Label 5441: @279846
     /* 279846 */   GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(279888), // Rule ID 13150 //
     /* 279851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2p1),
     /* 279854 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_tbxq),
     /* 279859 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 279862 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 279865 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 279868 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 279871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279875 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1975:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (TBXQ_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 279875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::TBXQ_ZZZ_D),
     /* 279878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 279880 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279882 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279884 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279886 */     GIR_RootConstrainSelectedInstOperands,
     /* 279887 */     // GIR_Coverage, 13150,
     /* 279887 */     GIR_EraseRootFromParent_Done,
     /* 279888 */   // Label 5442: @279888
     /* 279888 */   GIM_Try, /*On fail goto*//*Label 5443*/ GIMT_Encode4(279930), // Rule ID 13560 //
     /* 279893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 279896 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 279901 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 279904 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 279907 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 279910 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 279913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279917 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1403:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMIN_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 279917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_H),
     /* 279920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279922 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279924 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279926 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279928 */     GIR_RootConstrainSelectedInstOperands,
     /* 279929 */     // GIR_Coverage, 13560,
     /* 279929 */     GIR_EraseRootFromParent_Done,
     /* 279930 */   // Label 5443: @279930
     /* 279930 */   GIM_Try, /*On fail goto*//*Label 5444*/ GIMT_Encode4(279972), // Rule ID 13561 //
     /* 279935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 279938 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 279943 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 279946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 279949 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 279952 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 279955 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 279959 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1403:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMIN_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 279959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_S),
     /* 279962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 279964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 279966 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 279968 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 279970 */     GIR_RootConstrainSelectedInstOperands,
     /* 279971 */     // GIR_Coverage, 13561,
     /* 279971 */     GIR_EraseRootFromParent_Done,
     /* 279972 */   // Label 5444: @279972
     /* 279972 */   GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(280014), // Rule ID 13562 //
     /* 279977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 279980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin),
     /* 279985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 279988 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 279991 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 279994 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 279997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280001 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1403:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMIN_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 280001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPmZ_D),
     /* 280004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 280006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280010 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280012 */     GIR_RootConstrainSelectedInstOperands,
     /* 280013 */     // GIR_Coverage, 13562,
     /* 280013 */     GIR_EraseRootFromParent_Done,
     /* 280014 */   // Label 5445: @280014
     /* 280014 */   GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(280056), // Rule ID 13563 //
     /* 280019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280022 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 280027 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 280030 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 280033 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 280036 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 280039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280043 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1401:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMAX_ZPmZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 280043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_H),
     /* 280046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 280048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280050 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280052 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280054 */     GIR_RootConstrainSelectedInstOperands,
     /* 280055 */     // GIR_Coverage, 13563,
     /* 280055 */     GIR_EraseRootFromParent_Done,
     /* 280056 */   // Label 5446: @280056
     /* 280056 */   GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(280098), // Rule ID 13564 //
     /* 280061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280064 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 280069 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 280072 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 280075 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 280078 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 280081 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280085 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1401:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMAX_ZPmZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 280085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_S),
     /* 280088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 280090 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280092 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280094 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280096 */     GIR_RootConstrainSelectedInstOperands,
     /* 280097 */     // GIR_Coverage, 13564,
     /* 280097 */     GIR_EraseRootFromParent_Done,
     /* 280098 */   // Label 5447: @280098
     /* 280098 */   GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(280140), // Rule ID 13565 //
     /* 280103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280106 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax),
     /* 280111 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 280114 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280117 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 280120 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 280123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280127 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1401:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMAX_ZPmZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 280127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPmZ_D),
     /* 280130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 280132 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280136 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280138 */     GIR_RootConstrainSelectedInstOperands,
     /* 280139 */     // GIR_Coverage, 13565,
     /* 280139 */     GIR_EraseRootFromParent_Done,
     /* 280140 */   // Label 5448: @280140
     /* 280140 */   GIM_Try, /*On fail goto*//*Label 5449*/ GIMT_Encode4(280182), // Rule ID 13566 //
     /* 280145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280148 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280153 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 280156 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 280159 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 280162 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 280165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280169 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1402:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 280169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 280172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280178 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280180 */     GIR_RootConstrainSelectedInstOperands,
     /* 280181 */     // GIR_Coverage, 13566,
     /* 280181 */     GIR_EraseRootFromParent_Done,
     /* 280182 */   // Label 5449: @280182
     /* 280182 */   GIM_Try, /*On fail goto*//*Label 5450*/ GIMT_Encode4(280224), // Rule ID 13569 //
     /* 280187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 280198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 280201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 280204 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 280207 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280211 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1402:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 280211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 280214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280220 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280222 */     GIR_RootConstrainSelectedInstOperands,
     /* 280223 */     // GIR_Coverage, 13569,
     /* 280223 */     GIR_EraseRootFromParent_Done,
     /* 280224 */   // Label 5450: @280224
     /* 280224 */   GIM_Try, /*On fail goto*//*Label 5451*/ GIMT_Encode4(280266), // Rule ID 13572 //
     /* 280229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 280240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 280246 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 280249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280253 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1402:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FAMAX_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 280253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_H_UNDEF),
     /* 280256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280258 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280260 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280262 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280264 */     GIR_RootConstrainSelectedInstOperands,
     /* 280265 */     // GIR_Coverage, 13572,
     /* 280265 */     GIR_EraseRootFromParent_Done,
     /* 280266 */   // Label 5451: @280266
     /* 280266 */   GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(280308), // Rule ID 13575 //
     /* 280271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 280282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 280285 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 280288 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 280291 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280295 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1402:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMAX_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 280295 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_S_UNDEF),
     /* 280298 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280300 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280302 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280304 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280306 */     GIR_RootConstrainSelectedInstOperands,
     /* 280307 */     // GIR_Coverage, 13575,
     /* 280307 */     GIR_EraseRootFromParent_Done,
     /* 280308 */   // Label 5452: @280308
     /* 280308 */   GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(280350), // Rule ID 13578 //
     /* 280313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280316 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280321 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 280324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 280330 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 280333 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280337 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1402:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FAMAX_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 280337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_S_UNDEF),
     /* 280340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280342 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280344 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280346 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280348 */     GIR_RootConstrainSelectedInstOperands,
     /* 280349 */     // GIR_Coverage, 13578,
     /* 280349 */     GIR_EraseRootFromParent_Done,
     /* 280350 */   // Label 5453: @280350
     /* 280350 */   GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(280392), // Rule ID 13581 //
     /* 280355 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280358 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famax_u),
     /* 280363 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 280366 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280369 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 280372 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 280375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280379 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1402:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMAX_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 280379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAX_ZPZZ_D_UNDEF),
     /* 280382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280384 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280386 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280388 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280390 */     GIR_RootConstrainSelectedInstOperands,
     /* 280391 */     // GIR_Coverage, 13581,
     /* 280391 */     GIR_EraseRootFromParent_Done,
     /* 280392 */   // Label 5454: @280392
     /* 280392 */   GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(280434), // Rule ID 13584 //
     /* 280397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 280408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 280411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 280414 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 280417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280421 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1404:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 280421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 280424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280426 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280428 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280430 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280432 */     GIR_RootConstrainSelectedInstOperands,
     /* 280433 */     // GIR_Coverage, 13584,
     /* 280433 */     GIR_EraseRootFromParent_Done,
     /* 280434 */   // Label 5455: @280434
     /* 280434 */   GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(280476), // Rule ID 13587 //
     /* 280439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 280450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 280453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 280456 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 280459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280463 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1404:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 280463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 280466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280470 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280472 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280474 */     GIR_RootConstrainSelectedInstOperands,
     /* 280475 */     // GIR_Coverage, 13587,
     /* 280475 */     GIR_EraseRootFromParent_Done,
     /* 280476 */   // Label 5456: @280476
     /* 280476 */   GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(280518), // Rule ID 13590 //
     /* 280481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280484 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280489 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 280492 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280495 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 280498 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 280501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280505 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1404:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (FAMIN_ZPZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 280505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_H_UNDEF),
     /* 280508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280514 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280516 */     GIR_RootConstrainSelectedInstOperands,
     /* 280517 */     // GIR_Coverage, 13590,
     /* 280517 */     GIR_EraseRootFromParent_Done,
     /* 280518 */   // Label 5457: @280518
     /* 280518 */   GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(280560), // Rule ID 13593 //
     /* 280523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 280534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 280537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 280540 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 280543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280547 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1404:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (FAMIN_ZPZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 280547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_S_UNDEF),
     /* 280550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280552 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280554 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280556 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280558 */     GIR_RootConstrainSelectedInstOperands,
     /* 280559 */     // GIR_Coverage, 13593,
     /* 280559 */     GIR_EraseRootFromParent_Done,
     /* 280560 */   // Label 5458: @280560
     /* 280560 */   GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(280602), // Rule ID 13596 //
     /* 280565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 280576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 280582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 280585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280589 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1404:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (FAMIN_ZPZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 280589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_S_UNDEF),
     /* 280592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280594 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280596 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280598 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280600 */     GIR_RootConstrainSelectedInstOperands,
     /* 280601 */     // GIR_Coverage, 13596,
     /* 280601 */     GIR_EraseRootFromParent_Done,
     /* 280602 */   // Label 5459: @280602
     /* 280602 */   GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(280644), // Rule ID 13599 //
     /* 280607 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNonStreamingSVE2_or_SME2),
     /* 280610 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_famin_u),
     /* 280615 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 280618 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 280621 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 280624 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 280627 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 280631 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1404:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (FAMIN_ZPZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 280631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMIN_ZPZZ_D_UNDEF),
     /* 280634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 280636 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 280638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 280640 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 280642 */     GIR_RootConstrainSelectedInstOperands,
     /* 280643 */     // GIR_Coverage, 13599,
     /* 280643 */     GIR_EraseRootFromParent_Done,
     /* 280644 */   // Label 5460: @280644
     /* 280644 */   GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(280787), // Rule ID 6187 //
     /* 280649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 280652 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 280657 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 280660 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 280663 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 280666 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280670 */     // MIs[0] idx
     /* 280670 */     // No operand predicates
     /* 280670 */     // (intrinsic_wo_chain:{ *:[v16i8] } 793:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 280670 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 280673 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 280677 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 280684 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 280687 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 280691 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280696 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 280699 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 280703 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 280706 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280711 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280716 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280721 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 280724 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 280728 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280733 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 280735 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 280738 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 280742 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280747 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 280750 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 280754 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 280757 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280762 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280767 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280772 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 280775 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280777 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 280780 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 280783 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 280785 */     GIR_RootConstrainSelectedInstOperands,
     /* 280786 */     // GIR_Coverage, 6187,
     /* 280786 */     GIR_EraseRootFromParent_Done,
     /* 280787 */   // Label 5461: @280787
     /* 280787 */   GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(280878), // Rule ID 6188 //
     /* 280792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 280795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 280800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 280803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 280806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 280809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280813 */     // MIs[0] idx
     /* 280813 */     // No operand predicates
     /* 280813 */     // (intrinsic_wo_chain:{ *:[v16i8] } 794:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 280813 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 280816 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 280820 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 280827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 280830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 280834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280839 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 280842 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 280846 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 280849 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280854 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280859 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 280867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280869 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 280872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 280874 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 280876 */     GIR_RootConstrainSelectedInstOperands,
     /* 280877 */     // GIR_Coverage, 6188,
     /* 280877 */     GIR_EraseRootFromParent_Done,
     /* 280878 */   // Label 5462: @280878
     /* 280878 */   GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(280969), // Rule ID 6189 //
     /* 280883 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 280886 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 280891 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 280894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 280897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 280900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280904 */     // MIs[0] idx
     /* 280904 */     // No operand predicates
     /* 280904 */     // (intrinsic_wo_chain:{ *:[v16i8] } 793:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 280904 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 280907 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 280911 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280916 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 280918 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 280921 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 280925 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 280930 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 280933 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 280937 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 280940 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280945 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280950 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 280955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 280958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 280960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 280962 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 280965 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 280967 */     GIR_RootConstrainSelectedInstOperands,
     /* 280968 */     // GIR_Coverage, 6189,
     /* 280968 */     GIR_EraseRootFromParent_Done,
     /* 280969 */   // Label 5463: @280969
     /* 280969 */   GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(281008), // Rule ID 6190 //
     /* 280974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 280977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 280982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 280985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 280988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 280991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 280995 */     // MIs[0] idx
     /* 280995 */     // No operand predicates
     /* 280995 */     // (intrinsic_wo_chain:{ *:[v16i8] } 794:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_B:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 280995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_B),
     /* 280998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281000 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281002 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281004 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281006 */     GIR_RootConstrainSelectedInstOperands,
     /* 281007 */     // GIR_Coverage, 6190,
     /* 281007 */     GIR_EraseRootFromParent_Done,
     /* 281008 */   // Label 5464: @281008
     /* 281008 */   GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(281151), // Rule ID 6191 //
     /* 281013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281016 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 281021 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 281027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 281030 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281034 */     // MIs[0] idx
     /* 281034 */     // No operand predicates
     /* 281034 */     // (intrinsic_wo_chain:{ *:[v8i16] } 793:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281034 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 281037 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281041 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281046 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 281048 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 281051 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281055 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281060 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 281063 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 281067 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 281070 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281075 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281080 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281085 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281088 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281092 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281099 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281102 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281106 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281111 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281114 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 281118 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281121 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281126 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281131 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281141 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281144 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 281147 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281149 */     GIR_RootConstrainSelectedInstOperands,
     /* 281150 */     // GIR_Coverage, 6191,
     /* 281150 */     GIR_EraseRootFromParent_Done,
     /* 281151 */   // Label 5465: @281151
     /* 281151 */   GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(281242), // Rule ID 6192 //
     /* 281156 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281159 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 281164 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 281170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 281173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281177 */     // MIs[0] idx
     /* 281177 */     // No operand predicates
     /* 281177 */     // (intrinsic_wo_chain:{ *:[v8i16] } 794:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281177 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281180 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281184 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281189 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281191 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281194 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281198 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281203 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281206 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 281210 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281213 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281218 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281223 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281233 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281238 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281240 */     GIR_RootConstrainSelectedInstOperands,
     /* 281241 */     // GIR_Coverage, 6192,
     /* 281241 */     GIR_EraseRootFromParent_Done,
     /* 281242 */   // Label 5466: @281242
     /* 281242 */   GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(281333), // Rule ID 6193 //
     /* 281247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 281255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 281261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 281264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281268 */     // MIs[0] idx
     /* 281268 */     // No operand predicates
     /* 281268 */     // (intrinsic_wo_chain:{ *:[v8i16] } 793:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281268 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281271 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281275 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281280 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281282 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281285 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281289 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281294 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281297 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 281301 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281304 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281309 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281314 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281319 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281322 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281324 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281326 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281329 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281331 */     GIR_RootConstrainSelectedInstOperands,
     /* 281332 */     // GIR_Coverage, 6193,
     /* 281332 */     GIR_EraseRootFromParent_Done,
     /* 281333 */   // Label 5467: @281333
     /* 281333 */   GIM_Try, /*On fail goto*//*Label 5468*/ GIMT_Encode4(281372), // Rule ID 6194 //
     /* 281338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 281346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 281352 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 281355 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281359 */     // MIs[0] idx
     /* 281359 */     // No operand predicates
     /* 281359 */     // (intrinsic_wo_chain:{ *:[v8i16] } 794:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281364 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281366 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281368 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281370 */     GIR_RootConstrainSelectedInstOperands,
     /* 281371 */     // GIR_Coverage, 6194,
     /* 281371 */     GIR_EraseRootFromParent_Done,
     /* 281372 */   // Label 5468: @281372
     /* 281372 */   GIM_Try, /*On fail goto*//*Label 5469*/ GIMT_Encode4(281515), // Rule ID 6195 //
     /* 281377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 281385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 281391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 281394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281398 */     // MIs[0] idx
     /* 281398 */     // No operand predicates
     /* 281398 */     // (intrinsic_wo_chain:{ *:[v8f16] } 793:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281398 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 281401 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281405 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281410 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 281412 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 281415 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281419 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281424 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 281427 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 281431 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 281434 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281439 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281444 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281449 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281452 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281456 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281461 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281463 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281466 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281470 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281475 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281478 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 281482 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281485 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281490 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281495 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281505 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 281511 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281513 */     GIR_RootConstrainSelectedInstOperands,
     /* 281514 */     // GIR_Coverage, 6195,
     /* 281514 */     GIR_EraseRootFromParent_Done,
     /* 281515 */   // Label 5469: @281515
     /* 281515 */   GIM_Try, /*On fail goto*//*Label 5470*/ GIMT_Encode4(281606), // Rule ID 6196 //
     /* 281520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281523 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 281528 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281531 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 281534 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 281537 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281541 */     // MIs[0] idx
     /* 281541 */     // No operand predicates
     /* 281541 */     // (intrinsic_wo_chain:{ *:[v8f16] } 794:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281541 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281544 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281548 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281553 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281555 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281558 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281562 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281567 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281570 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 281574 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281577 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281582 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281587 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281600 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281602 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281604 */     GIR_RootConstrainSelectedInstOperands,
     /* 281605 */     // GIR_Coverage, 6196,
     /* 281605 */     GIR_EraseRootFromParent_Done,
     /* 281606 */   // Label 5470: @281606
     /* 281606 */   GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(281697), // Rule ID 6197 //
     /* 281611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_lane),
     /* 281619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 281625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 281628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281632 */     // MIs[0] idx
     /* 281632 */     // No operand predicates
     /* 281632 */     // (intrinsic_wo_chain:{ *:[v8f16] } 793:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281632 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281635 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281639 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281644 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281646 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281649 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281653 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281658 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281661 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 281665 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281668 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281673 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281678 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281688 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281690 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281693 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281695 */     GIR_RootConstrainSelectedInstOperands,
     /* 281696 */     // GIR_Coverage, 6197,
     /* 281696 */     GIR_EraseRootFromParent_Done,
     /* 281697 */   // Label 5471: @281697
     /* 281697 */   GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(281736), // Rule ID 6198 //
     /* 281702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti2_laneq),
     /* 281710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 281713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 281716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 281719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281723 */     // MIs[0] idx
     /* 281723 */     // No operand predicates
     /* 281723 */     // (intrinsic_wo_chain:{ *:[v8f16] } 794:{ *:[iPTR] }, v8f16:{ *:[v8f16] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT2_H:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 281723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT2_H),
     /* 281726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281728 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281730 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281732 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281734 */     GIR_RootConstrainSelectedInstOperands,
     /* 281735 */     // GIR_Coverage, 6198,
     /* 281735 */     GIR_EraseRootFromParent_Done,
     /* 281736 */   // Label 5472: @281736
     /* 281736 */   GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(281775), // Rule ID 6199 //
     /* 281741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281744 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti4q_laneq),
     /* 281749 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 281752 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 281755 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 281758 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281762 */     // MIs[0] idx
     /* 281762 */     // No operand predicates
     /* 281762 */     // (intrinsic_wo_chain:{ *:[v16i8] } 797:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v16i8:{ *:[v16i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT4_B:{ *:[v16i8] } VecListOne16b:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 281762 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT4_B),
     /* 281765 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281767 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281769 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 281771 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281773 */     GIR_RootConstrainSelectedInstOperands,
     /* 281774 */     // GIR_Coverage, 6199,
     /* 281774 */     GIR_EraseRootFromParent_Done,
     /* 281775 */   // Label 5473: @281775
     /* 281775 */   GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(281866), // Rule ID 6200 //
     /* 281780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLUT),
     /* 281783 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vluti4q_lane),
     /* 281788 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 281791 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 281794 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 281797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281801 */     // MIs[0] idx
     /* 281801 */     // No operand predicates
     /* 281801 */     // (intrinsic_wo_chain:{ *:[v16i8] } 795:{ *:[iPTR] }, v16i8:{ *:[v16i8] }:$Rn, v8i8:{ *:[v8i8] }:$Rm, i32:{ *:[i32] }:$idx)  =>  (LUT4_B:{ *:[v16i8] } VecListOne16b:{ *:[v16i8] }:$Rn, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), V64:{ *:[v8i8] }:$Rm, dsub:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 281801 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 281804 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 281808 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281813 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 281815 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 281818 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 281822 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 281827 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 281830 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Rm
     /* 281834 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 281837 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281842 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 281847 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 281852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LUT4_B),
     /* 281855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 281857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 281859 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 281862 */     GIR_RootToRootCopy, /*OpIdx*/4, // idx
     /* 281864 */     GIR_RootConstrainSelectedInstOperands,
     /* 281865 */     // GIR_Coverage, 6200,
     /* 281865 */     GIR_EraseRootFromParent_Done,
     /* 281866 */   // Label 5474: @281866
     /* 281866 */   GIM_Reject,
     /* 281867 */ // Label 4583: @281867
     /* 281867 */ GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(288978),
     /* 281872 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /* 281875 */   GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(281922), // Rule ID 3030 //
     /* 281880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 281883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 281888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 281891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 281894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 281897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 281900 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 281903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 281907 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1654:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLA_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 281907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_B_UNDEF),
     /* 281910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 281912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 281914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 281916 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 281918 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 281920 */     GIR_RootConstrainSelectedInstOperands,
     /* 281921 */     // GIR_Coverage, 3030,
     /* 281921 */     GIR_EraseRootFromParent_Done,
     /* 281922 */   // Label 5476: @281922
     /* 281922 */   GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(281969), // Rule ID 3032 //
     /* 281927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 281930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 281935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 281938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 281941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 281944 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 281947 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 281950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 281954 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1654:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLA_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 281954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_H_UNDEF),
     /* 281957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 281959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 281961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 281963 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 281965 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 281967 */     GIR_RootConstrainSelectedInstOperands,
     /* 281968 */     // GIR_Coverage, 3032,
     /* 281968 */     GIR_EraseRootFromParent_Done,
     /* 281969 */   // Label 5477: @281969
     /* 281969 */   GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(282016), // Rule ID 3034 //
     /* 281974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 281977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 281982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 281985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 281988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 281991 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 281994 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 281997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282001 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1654:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLA_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 282001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_S_UNDEF),
     /* 282004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282010 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282012 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282014 */     GIR_RootConstrainSelectedInstOperands,
     /* 282015 */     // GIR_Coverage, 3034,
     /* 282015 */     GIR_EraseRootFromParent_Done,
     /* 282016 */   // Label 5478: @282016
     /* 282016 */   GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(282063), // Rule ID 3036 //
     /* 282021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_u),
     /* 282029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 282032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 282035 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 282038 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 282041 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 282044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282048 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1654:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLA_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 282048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPZZZ_D_UNDEF),
     /* 282051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282057 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282059 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282061 */     GIR_RootConstrainSelectedInstOperands,
     /* 282062 */     // GIR_Coverage, 3036,
     /* 282062 */     GIR_EraseRootFromParent_Done,
     /* 282063 */   // Label 5479: @282063
     /* 282063 */   GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(282110), // Rule ID 8257 //
     /* 282068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 282076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 282079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 282082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 282085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 282088 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 282091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282095 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1657:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLS_ZPZZZ_B_UNDEF:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 282095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_B_UNDEF),
     /* 282098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282102 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282104 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282106 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282108 */     GIR_RootConstrainSelectedInstOperands,
     /* 282109 */     // GIR_Coverage, 8257,
     /* 282109 */     GIR_EraseRootFromParent_Done,
     /* 282110 */   // Label 5480: @282110
     /* 282110 */   GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(282157), // Rule ID 8259 //
     /* 282115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 282123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 282126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 282129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 282132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 282135 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 282138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282142 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1657:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLS_ZPZZZ_H_UNDEF:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 282142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_H_UNDEF),
     /* 282145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282149 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282151 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282153 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282155 */     GIR_RootConstrainSelectedInstOperands,
     /* 282156 */     // GIR_Coverage, 8259,
     /* 282156 */     GIR_EraseRootFromParent_Done,
     /* 282157 */   // Label 5481: @282157
     /* 282157 */   GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(282204), // Rule ID 8261 //
     /* 282162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 282170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 282173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 282176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 282179 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 282182 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 282185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282189 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1657:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLS_ZPZZZ_S_UNDEF:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 282189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_S_UNDEF),
     /* 282192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282198 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282200 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282202 */     GIR_RootConstrainSelectedInstOperands,
     /* 282203 */     // GIR_Coverage, 8261,
     /* 282203 */     GIR_EraseRootFromParent_Done,
     /* 282204 */   // Label 5482: @282204
     /* 282204 */   GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(282251), // Rule ID 8263 //
     /* 282209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_u),
     /* 282217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 282220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 282223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 282226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 282229 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 282232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282236 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1657:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLS_ZPZZZ_D_UNDEF:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 282236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPZZZ_D_UNDEF),
     /* 282239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 282241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282243 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282245 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282247 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 282249 */     GIR_RootConstrainSelectedInstOperands,
     /* 282250 */     // GIR_Coverage, 8263,
     /* 282250 */     GIR_EraseRootFromParent_Done,
     /* 282251 */   // Label 5483: @282251
     /* 282251 */   GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(282331), // Rule ID 6309 //
     /* 282256 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 282261 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 282264 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 282267 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 282270 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 282273 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 282276 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 282288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282292 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 282296 */     // MIs[1] Operand 1
     /* 282296 */     // No operand predicates
     /* 282296 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282300 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 282304 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282308 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 282312 */     // MIs[2] Operand 1
     /* 282312 */     // No operand predicates
     /* 282312 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282314 */     // (intrinsic_wo_chain:{ *:[v16i8] } 786:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, V128:{ *:[v16i8] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2)
     /* 282314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 282317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 282319 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282321 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 282324 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 282326 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 282329 */     GIR_RootConstrainSelectedInstOperands,
     /* 282330 */     // GIR_Coverage, 6309,
     /* 282330 */     GIR_EraseRootFromParent_Done,
     /* 282331 */   // Label 5484: @282331
     /* 282331 */   GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(282411), // Rule ID 6310 //
     /* 282336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 282341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 282344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 282347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 282350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 282353 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 282356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 282368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282372 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 282376 */     // MIs[1] Operand 1
     /* 282376 */     // No operand predicates
     /* 282376 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282380 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 282384 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282388 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 282392 */     // MIs[2] Operand 1
     /* 282392 */     // No operand predicates
     /* 282392 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282394 */     // (intrinsic_wo_chain:{ *:[v8i16] } 786:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, V128:{ *:[v8i16] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2)
     /* 282394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 282397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 282399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282401 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 282404 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 282406 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 282409 */     GIR_RootConstrainSelectedInstOperands,
     /* 282410 */     // GIR_Coverage, 6310,
     /* 282410 */     GIR_EraseRootFromParent_Done,
     /* 282411 */   // Label 5485: @282411
     /* 282411 */   GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(282491), // Rule ID 6311 //
     /* 282416 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 282421 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 282424 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 282427 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 282430 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 282433 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 282436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 282448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282452 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 282456 */     // MIs[1] Operand 1
     /* 282456 */     // No operand predicates
     /* 282456 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 282464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282468 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 282472 */     // MIs[2] Operand 1
     /* 282472 */     // No operand predicates
     /* 282472 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282474 */     // (intrinsic_wo_chain:{ *:[v4i32] } 786:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, V128:{ *:[v4i32] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2)
     /* 282474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 282477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 282479 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282481 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 282484 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 282486 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 282489 */     GIR_RootConstrainSelectedInstOperands,
     /* 282490 */     // GIR_Coverage, 6311,
     /* 282490 */     GIR_EraseRootFromParent_Done,
     /* 282491 */   // Label 5486: @282491
     /* 282491 */   GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(282571), // Rule ID 6312 //
     /* 282496 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_vcopy_lane),
     /* 282501 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 282504 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 282507 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 282510 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 282513 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s64,
     /* 282516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282524 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 282528 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282532 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 282536 */     // MIs[1] Operand 1
     /* 282536 */     // No operand predicates
     /* 282536 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282540 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/5, // MIs[2]
     /* 282544 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 282548 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 282552 */     // MIs[2] Operand 1
     /* 282552 */     // No operand predicates
     /* 282552 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 282554 */     // (intrinsic_wo_chain:{ *:[v2i64] } 786:{ *:[iPTR] }, V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Vd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, V128:{ *:[v2i64] }:$Vs, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2)
     /* 282554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 282557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 282559 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282561 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 282564 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vs
     /* 282566 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 282569 */     GIR_RootConstrainSelectedInstOperands,
     /* 282570 */     // GIR_Coverage, 6312,
     /* 282570 */     GIR_EraseRootFromParent_Done,
     /* 282571 */   // Label 5487: @282571
     /* 282571 */   GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(282635), // Rule ID 3942 //
     /* 282576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 282579 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1a),
     /* 282584 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 282587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 282590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 282593 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 282596 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282600 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282604 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282608 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282612 */     // MIs[0] imm
     /* 282612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282615 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 282620 */     // (intrinsic_wo_chain:{ *:[v4i32] } 561:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT1A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 282620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1A),
     /* 282623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 282625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 282629 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 282631 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 282633 */     GIR_RootConstrainSelectedInstOperands,
     /* 282634 */     // GIR_Coverage, 3942,
     /* 282634 */     GIR_EraseRootFromParent_Done,
     /* 282635 */   // Label 5488: @282635
     /* 282635 */   GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(282699), // Rule ID 3943 //
     /* 282640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 282643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt1b),
     /* 282648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 282651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 282654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 282657 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 282660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282668 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282672 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282676 */     // MIs[0] imm
     /* 282676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282679 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 282684 */     // (intrinsic_wo_chain:{ *:[v4i32] } 562:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT1B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 282684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT1B),
     /* 282687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 282689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 282693 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 282695 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 282697 */     GIR_RootConstrainSelectedInstOperands,
     /* 282698 */     // GIR_Coverage, 3943,
     /* 282698 */     GIR_EraseRootFromParent_Done,
     /* 282699 */   // Label 5489: @282699
     /* 282699 */   GIM_Try, /*On fail goto*//*Label 5490*/ GIMT_Encode4(282763), // Rule ID 3944 //
     /* 282704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 282707 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2a),
     /* 282712 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 282715 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 282718 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 282721 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 282724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282732 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282736 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282740 */     // MIs[0] imm
     /* 282740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282743 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 282748 */     // (intrinsic_wo_chain:{ *:[v4i32] } 563:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT2A:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 282748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2A),
     /* 282751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 282753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 282757 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 282759 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 282761 */     GIR_RootConstrainSelectedInstOperands,
     /* 282762 */     // GIR_Coverage, 3944,
     /* 282762 */     GIR_EraseRootFromParent_Done,
     /* 282763 */   // Label 5490: @282763
     /* 282763 */   GIM_Try, /*On fail goto*//*Label 5491*/ GIMT_Encode4(282827), // Rule ID 3945 //
     /* 282768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSM4),
     /* 282771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_crypto_sm3tt2b),
     /* 282776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 282779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 282782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 282785 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 282788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282792 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282796 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282800 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 282804 */     // MIs[0] imm
     /* 282804 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282807 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS_timm),
     /* 282812 */     // (intrinsic_wo_chain:{ *:[v4i32] } 564:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)  =>  (SM3TT2B:{ *:[v4i32] } V128:{ *:[v4i32] }:$Vd, V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm, (timm:{ *:[i64] })<<P:Predicate_VectorIndexS_timm>>:$imm)
     /* 282812 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SM3TT2B),
     /* 282815 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vdst]
     /* 282817 */     GIR_RootToRootCopy, /*OpIdx*/2, // Vd
     /* 282819 */     GIR_RootToRootCopy, /*OpIdx*/3, // Vn
     /* 282821 */     GIR_RootToRootCopy, /*OpIdx*/4, // Vm
     /* 282823 */     GIR_RootToRootCopy, /*OpIdx*/5, // imm
     /* 282825 */     GIR_RootConstrainSelectedInstOperands,
     /* 282826 */     // GIR_Coverage, 3945,
     /* 282826 */     GIR_EraseRootFromParent_Done,
     /* 282827 */   // Label 5491: @282827
     /* 282827 */   GIM_Try, /*On fail goto*//*Label 5492*/ GIMT_Encode4(282879), // Rule ID 2897 //
     /* 282832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282835 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 282840 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 282843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 282846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 282849 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 282852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282856 */     // MIs[0] idx
     /* 282856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282859 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 282864 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1499:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMLA_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 282864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_H),
     /* 282867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 282869 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282871 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282873 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282875 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 282877 */     GIR_RootConstrainSelectedInstOperands,
     /* 282878 */     // GIR_Coverage, 2897,
     /* 282878 */     GIR_EraseRootFromParent_Done,
     /* 282879 */   // Label 5492: @282879
     /* 282879 */   GIM_Try, /*On fail goto*//*Label 5493*/ GIMT_Encode4(282931), // Rule ID 2900 //
     /* 282884 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282887 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 282892 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 282895 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 282898 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 282901 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 282904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282908 */     // MIs[0] idx
     /* 282908 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282911 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 282916 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1499:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMLA_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 282916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_S),
     /* 282919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 282921 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282923 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282925 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282927 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 282929 */     GIR_RootConstrainSelectedInstOperands,
     /* 282930 */     // GIR_Coverage, 2900,
     /* 282930 */     GIR_EraseRootFromParent_Done,
     /* 282931 */   // Label 5493: @282931
     /* 282931 */   GIM_Try, /*On fail goto*//*Label 5494*/ GIMT_Encode4(282983), // Rule ID 2903 //
     /* 282936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 282939 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla_lane),
     /* 282944 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 282947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 282950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 282953 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 282956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 282960 */     // MIs[0] idx
     /* 282960 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 282963 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 282968 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1499:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMLA_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 282968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZZZI_D),
     /* 282971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 282973 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 282975 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 282977 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 282979 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 282981 */     GIR_RootConstrainSelectedInstOperands,
     /* 282982 */     // GIR_Coverage, 2903,
     /* 282982 */     GIR_EraseRootFromParent_Done,
     /* 282983 */   // Label 5494: @282983
     /* 282983 */   GIM_Try, /*On fail goto*//*Label 5495*/ GIMT_Encode4(283035), // Rule ID 3045 //
     /* 282988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 282991 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 282996 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 282999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 283002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283005 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283008 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283012 */     // MIs[0] Op4
     /* 283012 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283015 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 283020 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1653:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (MLA_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 283020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_H),
     /* 283023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283027 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283029 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283031 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283033 */     GIR_RootConstrainSelectedInstOperands,
     /* 283034 */     // GIR_Coverage, 3045,
     /* 283034 */     GIR_EraseRootFromParent_Done,
     /* 283035 */   // Label 5495: @283035
     /* 283035 */   GIM_Try, /*On fail goto*//*Label 5496*/ GIMT_Encode4(283087), // Rule ID 3046 //
     /* 283040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283043 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 283048 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283051 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283054 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 283057 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 283060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283064 */     // MIs[0] Op4
     /* 283064 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283067 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283072 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1653:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (MLA_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_S),
     /* 283075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283077 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283079 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283081 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283083 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283085 */     GIR_RootConstrainSelectedInstOperands,
     /* 283086 */     // GIR_Coverage, 3046,
     /* 283086 */     GIR_EraseRootFromParent_Done,
     /* 283087 */   // Label 5496: @283087
     /* 283087 */   GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(283139), // Rule ID 3047 //
     /* 283092 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283095 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla_lane),
     /* 283100 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283103 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 283109 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 283112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283116 */     // MIs[0] Op4
     /* 283116 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283119 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 283124 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1653:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (MLA_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 283124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZZZI_D),
     /* 283127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283131 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283133 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283135 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283137 */     GIR_RootConstrainSelectedInstOperands,
     /* 283138 */     // GIR_Coverage, 3047,
     /* 283138 */     GIR_EraseRootFromParent_Done,
     /* 283139 */   // Label 5497: @283139
     /* 283139 */   GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(283191), // Rule ID 3048 //
     /* 283144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283147 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
     /* 283152 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283155 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283158 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283161 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283164 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283168 */     // MIs[0] Op4
     /* 283168 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283171 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 283176 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1797:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 283176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_S),
     /* 283179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283183 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283185 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283187 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283189 */     GIR_RootConstrainSelectedInstOperands,
     /* 283190 */     // GIR_Coverage, 3048,
     /* 283190 */     GIR_EraseRootFromParent_Done,
     /* 283191 */   // Label 5498: @283191
     /* 283191 */   GIM_Try, /*On fail goto*//*Label 5499*/ GIMT_Encode4(283243), // Rule ID 3049 //
     /* 283196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalb_lane),
     /* 283204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 283213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 283216 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283220 */     // MIs[0] Op4
     /* 283220 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283223 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283228 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1797:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALB_ZZZI_D),
     /* 283231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283233 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283237 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283239 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283241 */     GIR_RootConstrainSelectedInstOperands,
     /* 283242 */     // GIR_Coverage, 3049,
     /* 283242 */     GIR_EraseRootFromParent_Done,
     /* 283243 */   // Label 5499: @283243
     /* 283243 */   GIM_Try, /*On fail goto*//*Label 5500*/ GIMT_Encode4(283295), // Rule ID 3053 //
     /* 283248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283251 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
     /* 283256 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283259 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283262 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 283265 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 283268 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283272 */     // MIs[0] Op4
     /* 283272 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283275 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283280 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1762:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SDOT_ZZZI_BtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_BtoS),
     /* 283283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283287 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283289 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283291 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283293 */     GIR_RootConstrainSelectedInstOperands,
     /* 283294 */     // GIR_Coverage, 3053,
     /* 283294 */     GIR_EraseRootFromParent_Done,
     /* 283295 */   // Label 5500: @283295
     /* 283295 */   GIM_Try, /*On fail goto*//*Label 5501*/ GIMT_Encode4(283347), // Rule ID 3054 //
     /* 283300 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283303 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane),
     /* 283308 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283311 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283314 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283317 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283324 */     // MIs[0] Op4
     /* 283324 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283327 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 283332 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1762:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SDOT_ZZZI_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 283332 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_HtoD),
     /* 283335 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283337 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283339 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283341 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283343 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283345 */     GIR_RootConstrainSelectedInstOperands,
     /* 283346 */     // GIR_Coverage, 3054,
     /* 283346 */     GIR_EraseRootFromParent_Done,
     /* 283347 */   // Label 5501: @283347
     /* 283347 */   GIM_Try, /*On fail goto*//*Label 5502*/ GIMT_Encode4(283399), // Rule ID 3543 //
     /* 283352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE_or_SME),
     /* 283355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_usdot_lane),
     /* 283360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 283369 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 283372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283376 */     // MIs[0] Op4
     /* 283376 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283379 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283384 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2117:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (USDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOT_ZZZI),
     /* 283387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283391 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283393 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283395 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283397 */     GIR_RootConstrainSelectedInstOperands,
     /* 283398 */     // GIR_Coverage, 3543,
     /* 283398 */     GIR_EraseRootFromParent_Done,
     /* 283399 */   // Label 5502: @283399
     /* 283399 */   GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(283451), // Rule ID 3588 //
     /* 283404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 283407 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sdot_lane_x2),
     /* 283412 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283415 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283418 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283421 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283428 */     // MIs[0] Op4
     /* 283428 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283431 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283436 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1763:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZI_HtoS),
     /* 283439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283443 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283445 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283447 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283449 */     GIR_RootConstrainSelectedInstOperands,
     /* 283450 */     // GIR_Coverage, 3588,
     /* 283450 */     GIR_EraseRootFromParent_Done,
     /* 283451 */   // Label 5503: @283451
     /* 283451 */   GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(283503), // Rule ID 8331 //
     /* 283456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283459 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
     /* 283464 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 283473 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 283476 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283480 */     // MIs[0] Op4
     /* 283480 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283483 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283488 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2013:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UDOT_ZZZI_BtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_BtoS),
     /* 283491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283493 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283495 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283497 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283499 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283501 */     GIR_RootConstrainSelectedInstOperands,
     /* 283502 */     // GIR_Coverage, 8331,
     /* 283502 */     GIR_EraseRootFromParent_Done,
     /* 283503 */   // Label 5504: @283503
     /* 283503 */   GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(283555), // Rule ID 8332 //
     /* 283508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283511 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane),
     /* 283516 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283519 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283522 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283525 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283528 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283532 */     // MIs[0] Op4
     /* 283532 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283535 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 283540 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2013:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (UDOT_ZZZI_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 283540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_HtoD),
     /* 283543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283545 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283547 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283549 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283551 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283553 */     GIR_RootConstrainSelectedInstOperands,
     /* 283554 */     // GIR_Coverage, 8332,
     /* 283554 */     GIR_EraseRootFromParent_Done,
     /* 283555 */   // Label 5505: @283555
     /* 283555 */   GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(283607), // Rule ID 8983 //
     /* 283560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 283568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 283571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 283574 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283577 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283584 */     // MIs[0] idx
     /* 283584 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283587 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 283592 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1506:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)  =>  (FMLS_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 283592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_H),
     /* 283595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283597 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283601 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283603 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 283605 */     GIR_RootConstrainSelectedInstOperands,
     /* 283606 */     // GIR_Coverage, 8983,
     /* 283606 */     GIR_EraseRootFromParent_Done,
     /* 283607 */   // Label 5506: @283607
     /* 283607 */   GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(283659), // Rule ID 8986 //
     /* 283612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 283620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 283629 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 283632 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283636 */     // MIs[0] idx
     /* 283636 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283639 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283644 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1506:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)  =>  (FMLS_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 283644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_S),
     /* 283647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283649 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283651 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283653 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283655 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 283657 */     GIR_RootConstrainSelectedInstOperands,
     /* 283658 */     // GIR_Coverage, 8986,
     /* 283658 */     GIR_EraseRootFromParent_Done,
     /* 283659 */   // Label 5507: @283659
     /* 283659 */   GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(283711), // Rule ID 8989 //
     /* 283664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 283667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_lane),
     /* 283672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 283681 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 283684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283688 */     // MIs[0] idx
     /* 283688 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283691 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 283696 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1506:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)  =>  (FMLS_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 283696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZZZI_D),
     /* 283699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283701 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283703 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283705 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283707 */     GIR_RootToRootCopy, /*OpIdx*/5, // idx
     /* 283709 */     GIR_RootConstrainSelectedInstOperands,
     /* 283710 */     // GIR_Coverage, 8989,
     /* 283710 */     GIR_EraseRootFromParent_Done,
     /* 283711 */   // Label 5508: @283711
     /* 283711 */   GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(283763), // Rule ID 12055 //
     /* 283716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE_or_SME),
     /* 283719 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sudot_lane),
     /* 283724 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283727 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283730 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 283733 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 283736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283740 */     // MIs[0] Op4
     /* 283740 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283743 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283748 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1962:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SUDOT_ZZZI:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOT_ZZZI),
     /* 283751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283755 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283757 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283759 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283761 */     GIR_RootConstrainSelectedInstOperands,
     /* 283762 */     // GIR_Coverage, 12055,
     /* 283762 */     GIR_EraseRootFromParent_Done,
     /* 283763 */   // Label 5509: @283763
     /* 283763 */   GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(283815), // Rule ID 12104 //
     /* 283768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 283776 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 283779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 283782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283785 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283792 */     // MIs[0] Op4
     /* 283792 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283795 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 283800 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1656:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (MLS_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 283800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_H),
     /* 283803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283809 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283811 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283813 */     GIR_RootConstrainSelectedInstOperands,
     /* 283814 */     // GIR_Coverage, 12104,
     /* 283814 */     GIR_EraseRootFromParent_Done,
     /* 283815 */   // Label 5510: @283815
     /* 283815 */   GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(283867), // Rule ID 12105 //
     /* 283820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 283828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 283837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 283840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283844 */     // MIs[0] Op4
     /* 283844 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283847 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 283852 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1656:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (MLS_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 283852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_S),
     /* 283855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283859 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283861 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283863 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283865 */     GIR_RootConstrainSelectedInstOperands,
     /* 283866 */     // GIR_Coverage, 12105,
     /* 283866 */     GIR_EraseRootFromParent_Done,
     /* 283867 */   // Label 5511: @283867
     /* 283867 */   GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(283919), // Rule ID 12106 //
     /* 283872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls_lane),
     /* 283880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 283883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 283886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 283889 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 283892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283896 */     // MIs[0] Op4
     /* 283896 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283899 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 283904 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1656:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (MLS_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 283904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZZZI_D),
     /* 283907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283909 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283913 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283915 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283917 */     GIR_RootConstrainSelectedInstOperands,
     /* 283918 */     // GIR_Coverage, 12106,
     /* 283918 */     GIR_EraseRootFromParent_Done,
     /* 283919 */   // Label 5512: @283919
     /* 283919 */   GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(283971), // Rule ID 12107 //
     /* 283924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283927 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 283932 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 283935 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 283938 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 283941 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 283944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 283948 */     // MIs[0] Op4
     /* 283948 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 283951 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 283956 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1876:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 283956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_H),
     /* 283959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 283961 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 283963 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 283965 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 283967 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 283969 */     GIR_RootConstrainSelectedInstOperands,
     /* 283970 */     // GIR_Coverage, 12107,
     /* 283970 */     GIR_EraseRootFromParent_Done,
     /* 283971 */   // Label 5513: @283971
     /* 283971 */   GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(284023), // Rule ID 12108 //
     /* 283976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 283979 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 283984 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 283987 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 283990 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 283993 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 283996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284000 */     // MIs[0] Op4
     /* 284000 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284003 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284008 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1876:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_S),
     /* 284011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284013 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284015 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284017 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284019 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284021 */     GIR_RootConstrainSelectedInstOperands,
     /* 284022 */     // GIR_Coverage, 12108,
     /* 284022 */     GIR_EraseRootFromParent_Done,
     /* 284023 */   // Label 5514: @284023
     /* 284023 */   GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(284075), // Rule ID 12109 //
     /* 284028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284031 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlah_lane),
     /* 284036 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284039 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284042 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 284045 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 284048 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284052 */     // MIs[0] Op4
     /* 284052 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284055 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 284060 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1876:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SQRDMLAH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 284060 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLAH_ZZZI_D),
     /* 284063 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284065 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284067 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284069 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284071 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284073 */     GIR_RootConstrainSelectedInstOperands,
     /* 284074 */     // GIR_Coverage, 12109,
     /* 284074 */     GIR_EraseRootFromParent_Done,
     /* 284075 */   // Label 5515: @284075
     /* 284075 */   GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(284127), // Rule ID 12110 //
     /* 284080 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284083 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 284088 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 284091 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 284094 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284097 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284104 */     // MIs[0] Op4
     /* 284104 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284107 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284112 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1878:{ *:[iPTR] }, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_H),
     /* 284115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284117 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284119 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284121 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284123 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284125 */     GIR_RootConstrainSelectedInstOperands,
     /* 284126 */     // GIR_Coverage, 12110,
     /* 284126 */     GIR_EraseRootFromParent_Done,
     /* 284127 */   // Label 5516: @284127
     /* 284127 */   GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(284179), // Rule ID 12111 //
     /* 284132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 284140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284149 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284156 */     // MIs[0] Op4
     /* 284156 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284159 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284164 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1878:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284164 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_S),
     /* 284167 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284169 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284173 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284175 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284177 */     GIR_RootConstrainSelectedInstOperands,
     /* 284178 */     // GIR_Coverage, 12111,
     /* 284178 */     GIR_EraseRootFromParent_Done,
     /* 284179 */   // Label 5517: @284179
     /* 284179 */   GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(284231), // Rule ID 12112 //
     /* 284184 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284187 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqrdmlsh_lane),
     /* 284192 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 284201 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 284204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284208 */     // MIs[0] Op4
     /* 284208 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284211 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 284216 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1878:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)  =>  (SQRDMLSH_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$Op4)
     /* 284216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRDMLSH_ZZZI_D),
     /* 284219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284221 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284223 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284225 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284227 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284229 */     GIR_RootConstrainSelectedInstOperands,
     /* 284230 */     // GIR_Coverage, 12112,
     /* 284230 */     GIR_EraseRootFromParent_Done,
     /* 284231 */   // Label 5518: @284231
     /* 284231 */   GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(284283), // Rule ID 12155 //
     /* 284236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284239 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
     /* 284244 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284247 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284250 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284253 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284260 */     // MIs[0] Op4
     /* 284260 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284263 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284268 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1799:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_S),
     /* 284271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284273 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284275 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284277 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284279 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284281 */     GIR_RootConstrainSelectedInstOperands,
     /* 284282 */     // GIR_Coverage, 12155,
     /* 284282 */     GIR_EraseRootFromParent_Done,
     /* 284283 */   // Label 5519: @284283
     /* 284283 */   GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(284335), // Rule ID 12156 //
     /* 284288 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284291 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlalt_lane),
     /* 284296 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284299 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284305 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284312 */     // MIs[0] Op4
     /* 284312 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284315 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284320 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1799:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLALT_ZZZI_D),
     /* 284323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284327 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284329 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284331 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284333 */     GIR_RootConstrainSelectedInstOperands,
     /* 284334 */     // GIR_Coverage, 12156,
     /* 284334 */     GIR_EraseRootFromParent_Done,
     /* 284335 */   // Label 5520: @284335
     /* 284335 */   GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(284387), // Rule ID 12157 //
     /* 284340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
     /* 284348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284357 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284364 */     // MIs[0] Op4
     /* 284364 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284367 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284372 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2039:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_S),
     /* 284375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284377 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284379 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284381 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284383 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284385 */     GIR_RootConstrainSelectedInstOperands,
     /* 284386 */     // GIR_Coverage, 12157,
     /* 284386 */     GIR_EraseRootFromParent_Done,
     /* 284387 */   // Label 5521: @284387
     /* 284387 */   GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(284439), // Rule ID 12158 //
     /* 284392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalb_lane),
     /* 284400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284409 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284412 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284416 */     // MIs[0] Op4
     /* 284416 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284419 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284424 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2039:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALB_ZZZI_D),
     /* 284427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284433 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284435 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284437 */     GIR_RootConstrainSelectedInstOperands,
     /* 284438 */     // GIR_Coverage, 12158,
     /* 284438 */     GIR_EraseRootFromParent_Done,
     /* 284439 */   // Label 5522: @284439
     /* 284439 */   GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(284491), // Rule ID 12159 //
     /* 284444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
     /* 284452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284461 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284468 */     // MIs[0] Op4
     /* 284468 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284471 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284476 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2041:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_S),
     /* 284479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284481 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284483 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284485 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284487 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284489 */     GIR_RootConstrainSelectedInstOperands,
     /* 284490 */     // GIR_Coverage, 12159,
     /* 284490 */     GIR_EraseRootFromParent_Done,
     /* 284491 */   // Label 5523: @284491
     /* 284491 */   GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(284543), // Rule ID 12160 //
     /* 284496 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284499 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlalt_lane),
     /* 284504 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284507 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284510 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284513 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284520 */     // MIs[0] Op4
     /* 284520 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284523 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284528 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2041:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLALT_ZZZI_D),
     /* 284531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284537 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284539 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284541 */     GIR_RootConstrainSelectedInstOperands,
     /* 284542 */     // GIR_Coverage, 12160,
     /* 284542 */     GIR_EraseRootFromParent_Done,
     /* 284543 */   // Label 5524: @284543
     /* 284543 */   GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(284595), // Rule ID 12161 //
     /* 284548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284551 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
     /* 284556 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284559 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284562 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284565 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284568 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284572 */     // MIs[0] Op4
     /* 284572 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284575 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284580 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1801:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_S),
     /* 284583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284585 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284587 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284589 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284591 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284593 */     GIR_RootConstrainSelectedInstOperands,
     /* 284594 */     // GIR_Coverage, 12161,
     /* 284594 */     GIR_EraseRootFromParent_Done,
     /* 284595 */   // Label 5525: @284595
     /* 284595 */   GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(284647), // Rule ID 12162 //
     /* 284600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284603 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslb_lane),
     /* 284608 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284611 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284614 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284617 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284624 */     // MIs[0] Op4
     /* 284624 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284627 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284632 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1801:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284632 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLB_ZZZI_D),
     /* 284635 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284641 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284643 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284645 */     GIR_RootConstrainSelectedInstOperands,
     /* 284646 */     // GIR_Coverage, 12162,
     /* 284646 */     GIR_EraseRootFromParent_Done,
     /* 284647 */   // Label 5526: @284647
     /* 284647 */   GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(284699), // Rule ID 12163 //
     /* 284652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284655 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
     /* 284660 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284663 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284666 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284669 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284672 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284676 */     // MIs[0] Op4
     /* 284676 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284679 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284684 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1803:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_S),
     /* 284687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284689 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284693 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284695 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284697 */     GIR_RootConstrainSelectedInstOperands,
     /* 284698 */     // GIR_Coverage, 12163,
     /* 284698 */     GIR_EraseRootFromParent_Done,
     /* 284699 */   // Label 5527: @284699
     /* 284699 */   GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(284751), // Rule ID 12164 //
     /* 284704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284707 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_smlslt_lane),
     /* 284712 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284715 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284718 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284721 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284728 */     // MIs[0] Op4
     /* 284728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284731 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284736 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1803:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMLSLT_ZZZI_D),
     /* 284739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284741 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284743 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284745 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284747 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284749 */     GIR_RootConstrainSelectedInstOperands,
     /* 284750 */     // GIR_Coverage, 12164,
     /* 284750 */     GIR_EraseRootFromParent_Done,
     /* 284751 */   // Label 5528: @284751
     /* 284751 */   GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(284803), // Rule ID 12165 //
     /* 284756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284759 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
     /* 284764 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284767 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284770 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284773 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284780 */     // MIs[0] Op4
     /* 284780 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284783 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284788 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2043:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_S),
     /* 284791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284793 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284797 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284799 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284801 */     GIR_RootConstrainSelectedInstOperands,
     /* 284802 */     // GIR_Coverage, 12165,
     /* 284802 */     GIR_EraseRootFromParent_Done,
     /* 284803 */   // Label 5529: @284803
     /* 284803 */   GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(284855), // Rule ID 12166 //
     /* 284808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284811 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslb_lane),
     /* 284816 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284819 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284822 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284825 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284828 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284832 */     // MIs[0] Op4
     /* 284832 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284835 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284840 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2043:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLB_ZZZI_D),
     /* 284843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284845 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284847 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284849 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284851 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284853 */     GIR_RootConstrainSelectedInstOperands,
     /* 284854 */     // GIR_Coverage, 12166,
     /* 284854 */     GIR_EraseRootFromParent_Done,
     /* 284855 */   // Label 5530: @284855
     /* 284855 */   GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(284907), // Rule ID 12167 //
     /* 284860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284863 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
     /* 284868 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284871 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284874 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284877 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284880 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284884 */     // MIs[0] Op4
     /* 284884 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284887 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284892 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2045:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (UMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284892 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_S),
     /* 284895 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284897 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284899 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284901 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284903 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284905 */     GIR_RootConstrainSelectedInstOperands,
     /* 284906 */     // GIR_Coverage, 12167,
     /* 284906 */     GIR_EraseRootFromParent_Done,
     /* 284907 */   // Label 5531: @284907
     /* 284907 */   GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(284959), // Rule ID 12168 //
     /* 284912 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284915 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_umlslt_lane),
     /* 284920 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 284923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 284926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 284929 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 284932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284936 */     // MIs[0] Op4
     /* 284936 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284939 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 284944 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 2045:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 284944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMLSLT_ZZZI_D),
     /* 284947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 284949 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 284951 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 284953 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 284955 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 284957 */     GIR_RootConstrainSelectedInstOperands,
     /* 284958 */     // GIR_Coverage, 12168,
     /* 284958 */     GIR_EraseRootFromParent_Done,
     /* 284959 */   // Label 5532: @284959
     /* 284959 */   GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(285011), // Rule ID 12196 //
     /* 284964 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 284967 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
     /* 284972 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 284975 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 284978 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 284981 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 284984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 284988 */     // MIs[0] Op4
     /* 284988 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 284991 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 284996 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1839:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLALB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 284996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_S),
     /* 284999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285001 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285003 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285005 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285007 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285009 */     GIR_RootConstrainSelectedInstOperands,
     /* 285010 */     // GIR_Coverage, 12196,
     /* 285010 */     GIR_EraseRootFromParent_Done,
     /* 285011 */   // Label 5533: @285011
     /* 285011 */   GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(285063), // Rule ID 12197 //
     /* 285016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalb_lane),
     /* 285024 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 285027 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 285030 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 285033 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 285036 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285040 */     // MIs[0] Op4
     /* 285040 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285043 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285048 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1839:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLALB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALB_ZZZI_D),
     /* 285051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285057 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285059 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285061 */     GIR_RootConstrainSelectedInstOperands,
     /* 285062 */     // GIR_Coverage, 12197,
     /* 285062 */     GIR_EraseRootFromParent_Done,
     /* 285063 */   // Label 5534: @285063
     /* 285063 */   GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(285115), // Rule ID 12198 //
     /* 285068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
     /* 285076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285092 */     // MIs[0] Op4
     /* 285092 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285095 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285100 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1842:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLALT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_S),
     /* 285103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285109 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285111 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285113 */     GIR_RootConstrainSelectedInstOperands,
     /* 285114 */     // GIR_Coverage, 12198,
     /* 285114 */     GIR_EraseRootFromParent_Done,
     /* 285115 */   // Label 5535: @285115
     /* 285115 */   GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(285167), // Rule ID 12199 //
     /* 285120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlalt_lane),
     /* 285128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 285131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 285134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 285137 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 285140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285144 */     // MIs[0] Op4
     /* 285144 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285147 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285152 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1842:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLALT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALT_ZZZI_D),
     /* 285155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285157 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285159 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285161 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285163 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285165 */     GIR_RootConstrainSelectedInstOperands,
     /* 285166 */     // GIR_Coverage, 12199,
     /* 285166 */     GIR_EraseRootFromParent_Done,
     /* 285167 */   // Label 5536: @285167
     /* 285167 */   GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(285219), // Rule ID 12200 //
     /* 285172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
     /* 285180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285189 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285196 */     // MIs[0] Op4
     /* 285196 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285199 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285204 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1844:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLSLB_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_S),
     /* 285207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285209 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285211 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285213 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285215 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285217 */     GIR_RootConstrainSelectedInstOperands,
     /* 285218 */     // GIR_Coverage, 12200,
     /* 285218 */     GIR_EraseRootFromParent_Done,
     /* 285219 */   // Label 5537: @285219
     /* 285219 */   GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(285271), // Rule ID 12201 //
     /* 285224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285227 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslb_lane),
     /* 285232 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 285235 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 285238 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 285241 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 285244 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285248 */     // MIs[0] Op4
     /* 285248 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285251 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285256 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1844:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLSLB_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLB_ZZZI_D),
     /* 285259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285261 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285263 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285265 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285267 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285269 */     GIR_RootConstrainSelectedInstOperands,
     /* 285270 */     // GIR_Coverage, 12201,
     /* 285270 */     GIR_EraseRootFromParent_Done,
     /* 285271 */   // Label 5538: @285271
     /* 285271 */   GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(285323), // Rule ID 12202 //
     /* 285276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285279 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
     /* 285284 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285287 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285290 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285293 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285296 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285300 */     // MIs[0] Op4
     /* 285300 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285303 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285308 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1847:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (SQDMLSLT_ZZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_S),
     /* 285311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285317 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285319 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285321 */     GIR_RootConstrainSelectedInstOperands,
     /* 285322 */     // GIR_Coverage, 12202,
     /* 285322 */     GIR_EraseRootFromParent_Done,
     /* 285323 */   // Label 5539: @285323
     /* 285323 */   GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(285375), // Rule ID 12203 //
     /* 285328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285331 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_sqdmlslt_lane),
     /* 285336 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 285339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 285342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 285345 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 285348 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285352 */     // MIs[0] Op4
     /* 285352 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285355 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285360 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1847:{ *:[iPTR] }, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (SQDMLSLT_ZZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLT_ZZZI_D),
     /* 285363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285365 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285367 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285369 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285371 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285373 */     GIR_RootConstrainSelectedInstOperands,
     /* 285374 */     // GIR_Coverage, 12203,
     /* 285374 */     GIR_EraseRootFromParent_Done,
     /* 285375 */   // Label 5540: @285375
     /* 285375 */   GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(285427), // Rule ID 12683 //
     /* 285380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285383 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalb_lane),
     /* 285388 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285391 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285394 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285397 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285404 */     // MIs[0] Op4
     /* 285404 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285407 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285412 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1502:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLALB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZI_SHH),
     /* 285415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285421 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285423 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285425 */     GIR_RootConstrainSelectedInstOperands,
     /* 285426 */     // GIR_Coverage, 12683,
     /* 285426 */     GIR_EraseRootFromParent_Done,
     /* 285427 */   // Label 5541: @285427
     /* 285427 */   GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(285479), // Rule ID 12684 //
     /* 285432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlalt_lane),
     /* 285440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285449 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285456 */     // MIs[0] Op4
     /* 285456 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285459 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285464 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1504:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLALT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZI_SHH),
     /* 285467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285471 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285473 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285475 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285477 */     GIR_RootConstrainSelectedInstOperands,
     /* 285478 */     // GIR_Coverage, 12684,
     /* 285478 */     GIR_EraseRootFromParent_Done,
     /* 285479 */   // Label 5542: @285479
     /* 285479 */   GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(285531), // Rule ID 12685 //
     /* 285484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslb_lane),
     /* 285492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285498 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285501 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285508 */     // MIs[0] Op4
     /* 285508 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285511 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285516 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1509:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLSLB_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLB_ZZZI_SHH),
     /* 285519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285523 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285525 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285527 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285529 */     GIR_RootConstrainSelectedInstOperands,
     /* 285530 */     // GIR_Coverage, 12685,
     /* 285530 */     GIR_EraseRootFromParent_Done,
     /* 285531 */   // Label 5543: @285531
     /* 285531 */   GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(285583), // Rule ID 12686 //
     /* 285536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 285539 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmlslt_lane),
     /* 285544 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285547 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285550 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285553 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285556 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285560 */     // MIs[0] Op4
     /* 285560 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285563 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 285568 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1511:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)  =>  (FMLSLT_ZZZI_SHH:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Op4)
     /* 285568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSLT_ZZZI_SHH),
     /* 285571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285573 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285577 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285579 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285581 */     GIR_RootConstrainSelectedInstOperands,
     /* 285582 */     // GIR_Coverage, 12686,
     /* 285582 */     GIR_EraseRootFromParent_Done,
     /* 285583 */   // Label 5544: @285583
     /* 285583 */   GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(285635), // Rule ID 12978 //
     /* 285588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 285591 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fdot_lane_x2),
     /* 285596 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285599 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285602 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285605 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285612 */     // MIs[0] Op4
     /* 285612 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285615 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285620 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1456:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (FDOT_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_S),
     /* 285623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285625 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285627 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285629 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285631 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285633 */     GIR_RootConstrainSelectedInstOperands,
     /* 285634 */     // GIR_Coverage, 12978,
     /* 285634 */     GIR_EraseRootFromParent_Done,
     /* 285635 */   // Label 5545: @285635
     /* 285635 */   GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(285687), // Rule ID 12980 //
     /* 285640 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2p1_or_SME2),
     /* 285643 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_udot_lane_x2),
     /* 285648 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285651 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 285654 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285657 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285664 */     // MIs[0] Op4
     /* 285664 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 285667 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 285672 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 2014:{ *:[iPTR] }, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)  =>  (UDOT_ZZZI_HtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Op4)
     /* 285672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZI_HtoS),
     /* 285675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285677 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285679 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285681 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285683 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285685 */     GIR_RootConstrainSelectedInstOperands,
     /* 285686 */     // GIR_Coverage, 12980,
     /* 285686 */     GIR_EraseRootFromParent_Done,
     /* 285687 */   // Label 5546: @285687
     /* 285687 */   GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(285734), // Rule ID 2874 //
     /* 285692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 285703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 285706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285709 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285712 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 285715 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285719 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1498:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 285719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 285722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285724 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285726 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285728 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285730 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285732 */     GIR_RootConstrainSelectedInstOperands,
     /* 285733 */     // GIR_Coverage, 2874,
     /* 285733 */     GIR_EraseRootFromParent_Done,
     /* 285734 */   // Label 5547: @285734
     /* 285734 */   GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(285781), // Rule ID 2877 //
     /* 285739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 285750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 285753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 285756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 285759 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 285762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285766 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1498:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 285766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 285769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285771 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285775 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285777 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285779 */     GIR_RootConstrainSelectedInstOperands,
     /* 285780 */     // GIR_Coverage, 2877,
     /* 285780 */     GIR_EraseRootFromParent_Done,
     /* 285781 */   // Label 5548: @285781
     /* 285781 */   GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(285828), // Rule ID 2880 //
     /* 285786 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285789 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285794 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 285797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 285800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 285803 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 285806 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 285809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285813 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1498:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 285813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_H),
     /* 285816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285818 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285822 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285824 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285826 */     GIR_RootConstrainSelectedInstOperands,
     /* 285827 */     // GIR_Coverage, 2880,
     /* 285827 */     GIR_EraseRootFromParent_Done,
     /* 285828 */   // Label 5549: @285828
     /* 285828 */   GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(285875), // Rule ID 2883 //
     /* 285833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285836 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285841 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 285844 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 285847 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 285850 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 285853 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 285856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285860 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1498:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 285860 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
     /* 285863 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285865 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285867 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285869 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285871 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285873 */     GIR_RootConstrainSelectedInstOperands,
     /* 285874 */     // GIR_Coverage, 2883,
     /* 285874 */     GIR_EraseRootFromParent_Done,
     /* 285875 */   // Label 5550: @285875
     /* 285875 */   GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(285922), // Rule ID 2886 //
     /* 285880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285883 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285888 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 285891 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 285894 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 285897 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 285900 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 285903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285907 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1498:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 285907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_S),
     /* 285910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285912 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285914 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285916 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285918 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285920 */     GIR_RootConstrainSelectedInstOperands,
     /* 285921 */     // GIR_Coverage, 2886,
     /* 285921 */     GIR_EraseRootFromParent_Done,
     /* 285922 */   // Label 5551: @285922
     /* 285922 */   GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(285969), // Rule ID 2889 //
     /* 285927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmla),
     /* 285935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 285938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 285941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 285944 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 285947 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 285950 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 285954 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1498:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 285954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLA_ZPmZZ_D),
     /* 285957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 285959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 285961 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 285963 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 285965 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 285967 */     GIR_RootConstrainSelectedInstOperands,
     /* 285968 */     // GIR_Coverage, 2889,
     /* 285968 */     GIR_EraseRootFromParent_Done,
     /* 285969 */   // Label 5552: @285969
     /* 285969 */   GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(286016), // Rule ID 2892 //
     /* 285974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 285977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 285982 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 285985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 285988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 285991 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 285994 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 285997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286001 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1461:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 286001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_H),
     /* 286004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286006 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286008 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286010 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286012 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286014 */     GIR_RootConstrainSelectedInstOperands,
     /* 286015 */     // GIR_Coverage, 2892,
     /* 286015 */     GIR_EraseRootFromParent_Done,
     /* 286016 */   // Label 5553: @286016
     /* 286016 */   GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(286063), // Rule ID 2893 //
     /* 286021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286024 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 286029 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 286032 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286035 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 286038 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 286041 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 286044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286048 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1461:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 286048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_S),
     /* 286051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286053 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286055 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286057 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286059 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286061 */     GIR_RootConstrainSelectedInstOperands,
     /* 286062 */     // GIR_Coverage, 2893,
     /* 286062 */     GIR_EraseRootFromParent_Done,
     /* 286063 */   // Label 5554: @286063
     /* 286063 */   GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(286110), // Rule ID 2894 //
     /* 286068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286071 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmad),
     /* 286076 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 286079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 286085 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 286088 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 286091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286095 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1461:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 286095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMAD_ZPmZZ_D),
     /* 286098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286102 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286104 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286106 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286108 */     GIR_RootConstrainSelectedInstOperands,
     /* 286109 */     // GIR_Coverage, 2894,
     /* 286109 */     GIR_EraseRootFromParent_Done,
     /* 286110 */   // Label 5555: @286110
     /* 286110 */   GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(286157), // Rule ID 3010 //
     /* 286115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286118 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 286123 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 286126 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 286129 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 286132 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 286135 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 286138 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286142 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1650:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MAD_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 286142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_B),
     /* 286145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286147 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286149 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286151 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286153 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286155 */     GIR_RootConstrainSelectedInstOperands,
     /* 286156 */     // GIR_Coverage, 3010,
     /* 286156 */     GIR_EraseRootFromParent_Done,
     /* 286157 */   // Label 5556: @286157
     /* 286157 */   GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(286204), // Rule ID 3013 //
     /* 286162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 286170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 286173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 286176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 286179 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 286182 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 286185 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286189 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1650:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MAD_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 286189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_H),
     /* 286192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286194 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286198 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286200 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286202 */     GIR_RootConstrainSelectedInstOperands,
     /* 286203 */     // GIR_Coverage, 3013,
     /* 286203 */     GIR_EraseRootFromParent_Done,
     /* 286204 */   // Label 5557: @286204
     /* 286204 */   GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(286251), // Rule ID 3016 //
     /* 286209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 286217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 286220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 286226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 286229 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 286232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286236 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1650:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MAD_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 286236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_S),
     /* 286239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286241 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286243 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286245 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286247 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286249 */     GIR_RootConstrainSelectedInstOperands,
     /* 286250 */     // GIR_Coverage, 3016,
     /* 286250 */     GIR_EraseRootFromParent_Done,
     /* 286251 */   // Label 5558: @286251
     /* 286251 */   GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(286298), // Rule ID 3019 //
     /* 286256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286259 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mad),
     /* 286264 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 286267 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286270 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 286273 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 286276 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 286279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286283 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1650:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MAD_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 286283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MAD_ZPmZZ_D),
     /* 286286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286290 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286292 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286294 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286296 */     GIR_RootConstrainSelectedInstOperands,
     /* 286297 */     // GIR_Coverage, 3019,
     /* 286297 */     GIR_EraseRootFromParent_Done,
     /* 286298 */   // Label 5559: @286298
     /* 286298 */   GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(286345), // Rule ID 3022 //
     /* 286303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 286311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 286314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 286317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 286320 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 286323 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 286326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286330 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1652:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLA_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 286330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_B),
     /* 286333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286337 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286339 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286341 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286343 */     GIR_RootConstrainSelectedInstOperands,
     /* 286344 */     // GIR_Coverage, 3022,
     /* 286344 */     GIR_EraseRootFromParent_Done,
     /* 286345 */   // Label 5560: @286345
     /* 286345 */   GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(286392), // Rule ID 3024 //
     /* 286350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 286358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 286361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 286364 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 286367 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 286370 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 286373 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286377 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1652:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLA_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 286377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_H),
     /* 286380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286386 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286388 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286390 */     GIR_RootConstrainSelectedInstOperands,
     /* 286391 */     // GIR_Coverage, 3024,
     /* 286391 */     GIR_EraseRootFromParent_Done,
     /* 286392 */   // Label 5561: @286392
     /* 286392 */   GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(286439), // Rule ID 3026 //
     /* 286397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 286405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 286408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 286414 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 286417 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 286420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286424 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1652:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLA_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 286424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_S),
     /* 286427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286429 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286431 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286433 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286435 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286437 */     GIR_RootConstrainSelectedInstOperands,
     /* 286438 */     // GIR_Coverage, 3026,
     /* 286438 */     GIR_EraseRootFromParent_Done,
     /* 286439 */   // Label 5562: @286439
     /* 286439 */   GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(286486), // Rule ID 3028 //
     /* 286444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286447 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mla),
     /* 286452 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 286455 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286458 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 286461 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 286464 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 286467 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286471 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1652:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLA_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 286471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLA_ZPmZZ_D),
     /* 286474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286476 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286478 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286480 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286482 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286484 */     GIR_RootConstrainSelectedInstOperands,
     /* 286485 */     // GIR_Coverage, 3028,
     /* 286485 */     GIR_EraseRootFromParent_Done,
     /* 286486 */   // Label 5563: @286486
     /* 286486 */   GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(286533), // Rule ID 8237 //
     /* 286491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 286499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 286502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 286505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 286508 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 286511 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 286514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286518 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1658:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MSB_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 286518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_B),
     /* 286521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286523 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286525 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286527 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286529 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286531 */     GIR_RootConstrainSelectedInstOperands,
     /* 286532 */     // GIR_Coverage, 8237,
     /* 286532 */     GIR_EraseRootFromParent_Done,
     /* 286533 */   // Label 5564: @286533
     /* 286533 */   GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(286580), // Rule ID 8240 //
     /* 286538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286541 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 286546 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 286549 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 286552 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 286555 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 286558 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 286561 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286565 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1658:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MSB_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 286565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_H),
     /* 286568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286574 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286576 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286578 */     GIR_RootConstrainSelectedInstOperands,
     /* 286579 */     // GIR_Coverage, 8240,
     /* 286579 */     GIR_EraseRootFromParent_Done,
     /* 286580 */   // Label 5565: @286580
     /* 286580 */   GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(286627), // Rule ID 8243 //
     /* 286585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286588 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 286593 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 286596 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286599 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 286602 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 286605 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 286608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286612 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1658:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MSB_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 286612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_S),
     /* 286615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286619 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286621 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286623 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286625 */     GIR_RootConstrainSelectedInstOperands,
     /* 286626 */     // GIR_Coverage, 8243,
     /* 286626 */     GIR_EraseRootFromParent_Done,
     /* 286627 */   // Label 5566: @286627
     /* 286627 */   GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(286674), // Rule ID 8246 //
     /* 286632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_msb),
     /* 286640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 286643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 286649 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 286652 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 286655 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286659 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1658:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MSB_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 286659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSB_ZPmZZ_D),
     /* 286662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 286664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286668 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286670 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286672 */     GIR_RootConstrainSelectedInstOperands,
     /* 286673 */     // GIR_Coverage, 8246,
     /* 286673 */     GIR_EraseRootFromParent_Done,
     /* 286674 */   // Label 5567: @286674
     /* 286674 */   GIM_Try, /*On fail goto*//*Label 5568*/ GIMT_Encode4(286721), // Rule ID 8249 //
     /* 286679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286682 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 286687 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s8,
     /* 286690 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 286693 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 286696 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 286699 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 286702 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286706 */     // (intrinsic_wo_chain:{ *:[nxv16i8] } 1655:{ *:[iPTR] }, nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op4)  =>  (MLS_ZPmZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[nxv16i8] }:$Op4)
     /* 286706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_B),
     /* 286709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286711 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286713 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286715 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286717 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286719 */     GIR_RootConstrainSelectedInstOperands,
     /* 286720 */     // GIR_Coverage, 8249,
     /* 286720 */     GIR_EraseRootFromParent_Done,
     /* 286721 */   // Label 5568: @286721
     /* 286721 */   GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(286768), // Rule ID 8251 //
     /* 286726 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 286734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 286737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 286740 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 286743 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 286746 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 286749 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286753 */     // (intrinsic_wo_chain:{ *:[nxv8i16] } 1655:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op4)  =>  (MLS_ZPmZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3, ?:{ *:[nxv8i16] }:$Op4)
     /* 286753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_H),
     /* 286756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286760 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286762 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286764 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286766 */     GIR_RootConstrainSelectedInstOperands,
     /* 286767 */     // GIR_Coverage, 8251,
     /* 286767 */     GIR_EraseRootFromParent_Done,
     /* 286768 */   // Label 5569: @286768
     /* 286768 */   GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(286815), // Rule ID 8253 //
     /* 286773 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286776 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 286781 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 286784 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286787 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 286790 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 286793 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 286796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286800 */     // (intrinsic_wo_chain:{ *:[nxv4i32] } 1655:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op4)  =>  (MLS_ZPmZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3, ?:{ *:[nxv4i32] }:$Op4)
     /* 286800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_S),
     /* 286803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286807 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286809 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286811 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286813 */     GIR_RootConstrainSelectedInstOperands,
     /* 286814 */     // GIR_Coverage, 8253,
     /* 286814 */     GIR_EraseRootFromParent_Done,
     /* 286815 */   // Label 5570: @286815
     /* 286815 */   GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(286862), // Rule ID 8255 //
     /* 286820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286823 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_mls),
     /* 286828 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 286831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 286837 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 286840 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 286843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286847 */     // (intrinsic_wo_chain:{ *:[nxv2i64] } 1655:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op4)  =>  (MLS_ZPmZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3, ?:{ *:[nxv2i64] }:$Op4)
     /* 286847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MLS_ZPmZZ_D),
     /* 286850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286854 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286856 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286858 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286860 */     GIR_RootConstrainSelectedInstOperands,
     /* 286861 */     // GIR_Coverage, 8255,
     /* 286861 */     GIR_EraseRootFromParent_Done,
     /* 286862 */   // Label 5571: @286862
     /* 286862 */   GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(286909), // Rule ID 8888 //
     /* 286867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286870 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 286875 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 286878 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 286881 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 286884 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 286887 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 286890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286894 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1505:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 286894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 286897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286899 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286901 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286903 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286905 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286907 */     GIR_RootConstrainSelectedInstOperands,
     /* 286908 */     // GIR_Coverage, 8888,
     /* 286908 */     GIR_EraseRootFromParent_Done,
     /* 286909 */   // Label 5572: @286909
     /* 286909 */   GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(286956), // Rule ID 8891 //
     /* 286914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 286922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 286925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 286928 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 286931 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 286934 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 286937 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286941 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1505:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 286941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 286944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286946 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286950 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286952 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 286954 */     GIR_RootConstrainSelectedInstOperands,
     /* 286955 */     // GIR_Coverage, 8891,
     /* 286955 */     GIR_EraseRootFromParent_Done,
     /* 286956 */   // Label 5573: @286956
     /* 286956 */   GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(287003), // Rule ID 8894 //
     /* 286961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 286964 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 286969 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 286972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 286975 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 286978 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 286981 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 286984 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 286988 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1505:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 286988 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_H),
     /* 286991 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 286993 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 286995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 286997 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 286999 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287001 */     GIR_RootConstrainSelectedInstOperands,
     /* 287002 */     // GIR_Coverage, 8894,
     /* 287002 */     GIR_EraseRootFromParent_Done,
     /* 287003 */   // Label 5574: @287003
     /* 287003 */   GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(287050), // Rule ID 8897 //
     /* 287008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287011 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 287016 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 287019 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287022 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 287025 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 287028 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 287031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287035 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1505:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 287035 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
     /* 287038 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287040 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287044 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287046 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287048 */     GIR_RootConstrainSelectedInstOperands,
     /* 287049 */     // GIR_Coverage, 8897,
     /* 287049 */     GIR_EraseRootFromParent_Done,
     /* 287050 */   // Label 5575: @287050
     /* 287050 */   GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(287097), // Rule ID 8900 //
     /* 287055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287058 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 287063 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 287066 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 287072 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 287075 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 287078 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287082 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1505:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 287082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_S),
     /* 287085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287091 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287093 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287095 */     GIR_RootConstrainSelectedInstOperands,
     /* 287096 */     // GIR_Coverage, 8900,
     /* 287096 */     GIR_EraseRootFromParent_Done,
     /* 287097 */   // Label 5576: @287097
     /* 287097 */   GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(287144), // Rule ID 8903 //
     /* 287102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287105 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls),
     /* 287110 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 287113 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287116 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 287119 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 287122 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 287125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287129 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1505:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 287129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPmZZ_D),
     /* 287132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287136 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287138 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287140 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287142 */     GIR_RootConstrainSelectedInstOperands,
     /* 287143 */     // GIR_Coverage, 8903,
     /* 287143 */     GIR_EraseRootFromParent_Done,
     /* 287144 */   // Label 5577: @287144
     /* 287144 */   GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(287191), // Rule ID 8906 //
     /* 287149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287152 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287157 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 287160 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 287163 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 287166 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 287169 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 287172 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287176 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1525:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 287176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 287179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287183 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287185 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287187 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287189 */     GIR_RootConstrainSelectedInstOperands,
     /* 287190 */     // GIR_Coverage, 8906,
     /* 287190 */     GIR_EraseRootFromParent_Done,
     /* 287191 */   // Label 5578: @287191
     /* 287191 */   GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(287238), // Rule ID 8907 //
     /* 287196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287199 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287204 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 287207 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287210 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 287213 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 287216 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 287219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287223 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1525:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 287223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 287226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287232 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287234 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287236 */     GIR_RootConstrainSelectedInstOperands,
     /* 287237 */     // GIR_Coverage, 8907,
     /* 287237 */     GIR_EraseRootFromParent_Done,
     /* 287238 */   // Label 5579: @287238
     /* 287238 */   GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(287285), // Rule ID 8908 //
     /* 287243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287251 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 287254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287257 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 287260 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 287263 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 287266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287270 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1525:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLA_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 287270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_H),
     /* 287273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287279 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287281 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287283 */     GIR_RootConstrainSelectedInstOperands,
     /* 287284 */     // GIR_Coverage, 8908,
     /* 287284 */     GIR_EraseRootFromParent_Done,
     /* 287285 */   // Label 5580: @287285
     /* 287285 */   GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(287332), // Rule ID 8909 //
     /* 287290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287293 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287298 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 287301 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287304 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 287307 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 287310 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 287313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287317 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1525:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLA_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 287317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
     /* 287320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287326 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287328 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287330 */     GIR_RootConstrainSelectedInstOperands,
     /* 287331 */     // GIR_Coverage, 8909,
     /* 287331 */     GIR_EraseRootFromParent_Done,
     /* 287332 */   // Label 5581: @287332
     /* 287332 */   GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(287379), // Rule ID 8910 //
     /* 287337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287340 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287345 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 287348 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287351 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 287354 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 287357 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 287360 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287364 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1525:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLA_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 287364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_S),
     /* 287367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287371 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287373 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287375 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287377 */     GIR_RootConstrainSelectedInstOperands,
     /* 287378 */     // GIR_Coverage, 8910,
     /* 287378 */     GIR_EraseRootFromParent_Done,
     /* 287379 */   // Label 5582: @287379
     /* 287379 */   GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(287426), // Rule ID 8911 //
     /* 287384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla),
     /* 287392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 287395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 287401 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 287404 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 287407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287411 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1525:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLA_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 287411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPmZZ_D),
     /* 287414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287416 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287420 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287422 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287424 */     GIR_RootConstrainSelectedInstOperands,
     /* 287425 */     // GIR_Coverage, 8911,
     /* 287425 */     GIR_EraseRootFromParent_Done,
     /* 287426 */   // Label 5583: @287426
     /* 287426 */   GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(287473), // Rule ID 8912 //
     /* 287431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 287442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 287445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 287448 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 287451 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 287454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287458 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1527:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 287458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 287461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287463 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287465 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287467 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287469 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287471 */     GIR_RootConstrainSelectedInstOperands,
     /* 287472 */     // GIR_Coverage, 8912,
     /* 287472 */     GIR_EraseRootFromParent_Done,
     /* 287473 */   // Label 5584: @287473
     /* 287473 */   GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(287520), // Rule ID 8913 //
     /* 287478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 287489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 287495 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 287498 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 287501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287505 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1527:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 287505 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 287508 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287510 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287512 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287514 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287516 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287518 */     GIR_RootConstrainSelectedInstOperands,
     /* 287519 */     // GIR_Coverage, 8913,
     /* 287519 */     GIR_EraseRootFromParent_Done,
     /* 287520 */   // Label 5585: @287520
     /* 287520 */   GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(287567), // Rule ID 8914 //
     /* 287525 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287528 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287533 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 287536 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287539 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 287542 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 287545 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 287548 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287552 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1527:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLS_ZPmZZ_H:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 287552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_H),
     /* 287555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287557 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287561 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287563 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287565 */     GIR_RootConstrainSelectedInstOperands,
     /* 287566 */     // GIR_Coverage, 8914,
     /* 287566 */     GIR_EraseRootFromParent_Done,
     /* 287567 */   // Label 5586: @287567
     /* 287567 */   GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(287614), // Rule ID 8915 //
     /* 287572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 287583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 287589 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 287592 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 287595 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287599 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1527:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLS_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 287599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
     /* 287602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287606 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287608 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287610 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287612 */     GIR_RootConstrainSelectedInstOperands,
     /* 287613 */     // GIR_Coverage, 8915,
     /* 287613 */     GIR_EraseRootFromParent_Done,
     /* 287614 */   // Label 5587: @287614
     /* 287614 */   GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(287661), // Rule ID 8916 //
     /* 287619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287622 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287627 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 287630 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287633 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 287636 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 287639 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 287642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287646 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1527:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLS_ZPmZZ_S:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 287646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_S),
     /* 287649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287651 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287653 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287655 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287657 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287659 */     GIR_RootConstrainSelectedInstOperands,
     /* 287660 */     // GIR_Coverage, 8916,
     /* 287660 */     GIR_EraseRootFromParent_Done,
     /* 287661 */   // Label 5588: @287661
     /* 287661 */   GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(287708), // Rule ID 8917 //
     /* 287666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls),
     /* 287674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 287677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287680 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 287683 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 287686 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 287689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287693 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1527:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLS_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 287693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPmZZ_D),
     /* 287696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 287698 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287700 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287702 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287704 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287706 */     GIR_RootConstrainSelectedInstOperands,
     /* 287707 */     // GIR_Coverage, 8917,
     /* 287707 */     GIR_EraseRootFromParent_Done,
     /* 287708 */   // Label 5589: @287708
     /* 287708 */   GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(287755), // Rule ID 8918 //
     /* 287713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287716 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 287721 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 287724 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 287727 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 287730 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 287733 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 287736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287740 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1513:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 287740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_H),
     /* 287743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287745 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287747 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287749 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287751 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287753 */     GIR_RootConstrainSelectedInstOperands,
     /* 287754 */     // GIR_Coverage, 8918,
     /* 287754 */     GIR_EraseRootFromParent_Done,
     /* 287755 */   // Label 5590: @287755
     /* 287755 */   GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(287802), // Rule ID 8919 //
     /* 287760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287763 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 287768 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 287771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 287777 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 287780 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 287783 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287787 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1513:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 287787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_S),
     /* 287790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287792 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287794 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287796 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287798 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287800 */     GIR_RootConstrainSelectedInstOperands,
     /* 287801 */     // GIR_Coverage, 8919,
     /* 287801 */     GIR_EraseRootFromParent_Done,
     /* 287802 */   // Label 5591: @287802
     /* 287802 */   GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(287849), // Rule ID 8920 //
     /* 287807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmsb),
     /* 287815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 287818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 287824 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 287827 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 287830 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287834 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1513:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 287834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSB_ZPmZZ_D),
     /* 287837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287841 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287843 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287845 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287847 */     GIR_RootConstrainSelectedInstOperands,
     /* 287848 */     // GIR_Coverage, 8920,
     /* 287848 */     GIR_EraseRootFromParent_Done,
     /* 287849 */   // Label 5592: @287849
     /* 287849 */   GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(287896), // Rule ID 8921 //
     /* 287854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 287862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 287865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 287868 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 287871 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 287874 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 287877 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287881 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1524:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMAD_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 287881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_H),
     /* 287884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287886 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287888 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287890 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287892 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287894 */     GIR_RootConstrainSelectedInstOperands,
     /* 287895 */     // GIR_Coverage, 8921,
     /* 287895 */     GIR_EraseRootFromParent_Done,
     /* 287896 */   // Label 5593: @287896
     /* 287896 */   GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(287943), // Rule ID 8922 //
     /* 287901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 287909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 287912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 287915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 287918 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 287921 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 287924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287928 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1524:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMAD_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 287928 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_S),
     /* 287931 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287933 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287935 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287937 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287939 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287941 */     GIR_RootConstrainSelectedInstOperands,
     /* 287942 */     // GIR_Coverage, 8922,
     /* 287942 */     GIR_EraseRootFromParent_Done,
     /* 287943 */   // Label 5594: @287943
     /* 287943 */   GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(287990), // Rule ID 8923 //
     /* 287948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287951 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmad),
     /* 287956 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 287959 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 287962 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 287965 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 287968 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 287971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 287975 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1524:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMAD_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 287975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMAD_ZPmZZ_D),
     /* 287978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 287980 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 287982 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 287984 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 287986 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 287988 */     GIR_RootConstrainSelectedInstOperands,
     /* 287989 */     // GIR_Coverage, 8923,
     /* 287989 */     GIR_EraseRootFromParent_Done,
     /* 287990 */   // Label 5595: @287990
     /* 287990 */   GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(288037), // Rule ID 8924 //
     /* 287995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 287998 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 288003 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 288006 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 288009 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 288012 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 288015 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 288018 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288022 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1529:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMSB_ZPmZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 288022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_H),
     /* 288025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 288027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288029 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288031 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288033 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288035 */     GIR_RootConstrainSelectedInstOperands,
     /* 288036 */     // GIR_Coverage, 8924,
     /* 288036 */     GIR_EraseRootFromParent_Done,
     /* 288037 */   // Label 5596: @288037
     /* 288037 */   GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(288084), // Rule ID 8925 //
     /* 288042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288045 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 288050 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 288053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 288059 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 288062 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 288065 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288069 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1529:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMSB_ZPmZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 288069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_S),
     /* 288072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 288074 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288076 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288078 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288080 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288082 */     GIR_RootConstrainSelectedInstOperands,
     /* 288083 */     // GIR_Coverage, 8925,
     /* 288083 */     GIR_EraseRootFromParent_Done,
     /* 288084 */   // Label 5597: @288084
     /* 288084 */   GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(288131), // Rule ID 8926 //
     /* 288089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288092 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmsb),
     /* 288097 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 288100 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288103 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 288106 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 288109 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 288112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288116 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1529:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMSB_ZPmZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 288116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSB_ZPmZZ_D),
     /* 288119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 288121 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288123 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288125 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288127 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288129 */     GIR_RootConstrainSelectedInstOperands,
     /* 288130 */     // GIR_Coverage, 8926,
     /* 288130 */     GIR_EraseRootFromParent_Done,
     /* 288131 */   // Label 5598: @288131
     /* 288131 */   GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(288178), // Rule ID 8927 //
     /* 288136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 288147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 288150 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 288153 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 288156 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 288159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288163 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1507:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 288163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 288166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288168 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288170 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288172 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288174 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288176 */     GIR_RootConstrainSelectedInstOperands,
     /* 288177 */     // GIR_Coverage, 8927,
     /* 288177 */     GIR_EraseRootFromParent_Done,
     /* 288178 */   // Label 5599: @288178
     /* 288178 */   GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(288225), // Rule ID 8930 //
     /* 288183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 288194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 288200 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 288203 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 288206 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288210 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1507:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 288210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 288213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288217 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288219 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288221 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288223 */     GIR_RootConstrainSelectedInstOperands,
     /* 288224 */     // GIR_Coverage, 8930,
     /* 288224 */     GIR_EraseRootFromParent_Done,
     /* 288225 */   // Label 5600: @288225
     /* 288225 */   GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(288272), // Rule ID 8933 //
     /* 288230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288233 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288238 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 288241 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288244 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 288247 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 288250 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 288253 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288257 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1507:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 288257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_H_UNDEF),
     /* 288260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288264 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288266 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288268 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288270 */     GIR_RootConstrainSelectedInstOperands,
     /* 288271 */     // GIR_Coverage, 8933,
     /* 288271 */     GIR_EraseRootFromParent_Done,
     /* 288272 */   // Label 5601: @288272
     /* 288272 */   GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(288319), // Rule ID 8936 //
     /* 288277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 288288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 288294 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 288297 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 288300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288304 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1507:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 288304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
     /* 288307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288313 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288315 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288317 */     GIR_RootConstrainSelectedInstOperands,
     /* 288318 */     // GIR_Coverage, 8936,
     /* 288318 */     GIR_EraseRootFromParent_Done,
     /* 288319 */   // Label 5602: @288319
     /* 288319 */   GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(288366), // Rule ID 8939 //
     /* 288324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 288335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 288341 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 288344 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 288347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288351 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1507:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 288351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_S_UNDEF),
     /* 288354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288356 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288360 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288362 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288364 */     GIR_RootConstrainSelectedInstOperands,
     /* 288365 */     // GIR_Coverage, 8939,
     /* 288365 */     GIR_EraseRootFromParent_Done,
     /* 288366 */   // Label 5603: @288366
     /* 288366 */   GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(288413), // Rule ID 8942 //
     /* 288371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288374 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fmls_u),
     /* 288379 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 288382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 288388 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 288391 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 288394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288398 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1507:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 288398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLS_ZPZZZ_D_UNDEF),
     /* 288401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288405 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288407 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288409 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288411 */     GIR_RootConstrainSelectedInstOperands,
     /* 288412 */     // GIR_Coverage, 8942,
     /* 288412 */     GIR_EraseRootFromParent_Done,
     /* 288413 */   // Label 5604: @288413
     /* 288413 */   GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(288460), // Rule ID 8945 //
     /* 288418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288426 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 288429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 288432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 288435 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 288438 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 288441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288445 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1526:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 288445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 288448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288450 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288452 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288454 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288456 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288458 */     GIR_RootConstrainSelectedInstOperands,
     /* 288459 */     // GIR_Coverage, 8945,
     /* 288459 */     GIR_EraseRootFromParent_Done,
     /* 288460 */   // Label 5605: @288460
     /* 288460 */   GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(288507), // Rule ID 8949 //
     /* 288465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 288476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 288482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 288485 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 288488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288492 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1526:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 288492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 288495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288497 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288499 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288501 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288503 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288505 */     GIR_RootConstrainSelectedInstOperands,
     /* 288506 */     // GIR_Coverage, 8949,
     /* 288506 */     GIR_EraseRootFromParent_Done,
     /* 288507 */   // Label 5606: @288507
     /* 288507 */   GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(288554), // Rule ID 8953 //
     /* 288512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 288523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 288529 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 288532 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 288535 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288539 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1526:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLA_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 288539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_H_UNDEF),
     /* 288542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288544 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288548 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288550 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288552 */     GIR_RootConstrainSelectedInstOperands,
     /* 288553 */     // GIR_Coverage, 8953,
     /* 288553 */     GIR_EraseRootFromParent_Done,
     /* 288554 */   // Label 5607: @288554
     /* 288554 */   GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(288601), // Rule ID 8957 //
     /* 288559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 288570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 288576 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 288579 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 288582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288586 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1526:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 288586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
     /* 288589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288595 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288597 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288599 */     GIR_RootConstrainSelectedInstOperands,
     /* 288600 */     // GIR_Coverage, 8957,
     /* 288600 */     GIR_EraseRootFromParent_Done,
     /* 288601 */   // Label 5608: @288601
     /* 288601 */   GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(288648), // Rule ID 8961 //
     /* 288606 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288609 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288614 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 288617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288620 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 288623 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 288626 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 288629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288633 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1526:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLA_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 288633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_S_UNDEF),
     /* 288636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288638 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288642 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288644 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288646 */     GIR_RootConstrainSelectedInstOperands,
     /* 288647 */     // GIR_Coverage, 8961,
     /* 288647 */     GIR_EraseRootFromParent_Done,
     /* 288648 */   // Label 5609: @288648
     /* 288648 */   GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(288695), // Rule ID 8965 //
     /* 288653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmla_u),
     /* 288661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 288664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 288670 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 288673 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 288676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288680 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1526:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLA_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 288680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLA_ZPZZZ_D_UNDEF),
     /* 288683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288685 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288687 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288689 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288691 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288693 */     GIR_RootConstrainSelectedInstOperands,
     /* 288694 */     // GIR_Coverage, 8965,
     /* 288694 */     GIR_EraseRootFromParent_Done,
     /* 288695 */   // Label 5610: @288695
     /* 288695 */   GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(288742), // Rule ID 8969 //
     /* 288700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288703 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288708 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 288711 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 288714 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 288717 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 288720 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 288723 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288727 */     // (intrinsic_wo_chain:{ *:[nxv8f16] } 1528:{ *:[iPTR] }, nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3, nxv8f16:{ *:[nxv8f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3, ?:{ *:[nxv8f16] }:$Op4)
     /* 288727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 288730 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288736 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288738 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288740 */     GIR_RootConstrainSelectedInstOperands,
     /* 288741 */     // GIR_Coverage, 8969,
     /* 288741 */     GIR_EraseRootFromParent_Done,
     /* 288742 */   // Label 5611: @288742
     /* 288742 */   GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(288789), // Rule ID 8971 //
     /* 288747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s16,
     /* 288758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 288764 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s16,
     /* 288767 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s16,
     /* 288770 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288774 */     // (intrinsic_wo_chain:{ *:[nxv4f16] } 1528:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3, nxv4f16:{ *:[nxv4f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3, ?:{ *:[nxv4f16] }:$Op4)
     /* 288774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 288777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288779 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288781 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288783 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288785 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288787 */     GIR_RootConstrainSelectedInstOperands,
     /* 288788 */     // GIR_Coverage, 8971,
     /* 288788 */     GIR_EraseRootFromParent_Done,
     /* 288789 */   // Label 5612: @288789
     /* 288789 */   GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(288836), // Rule ID 8973 //
     /* 288794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288802 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s16,
     /* 288805 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288808 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 288811 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s16,
     /* 288814 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s16,
     /* 288817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288821 */     // (intrinsic_wo_chain:{ *:[nxv2f16] } 1528:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3, nxv2f16:{ *:[nxv2f16] }:$Op4)  =>  (FNMLS_ZPZZZ_H_UNDEF:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3, ?:{ *:[nxv2f16] }:$Op4)
     /* 288821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_H_UNDEF),
     /* 288824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288826 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288828 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288830 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288832 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288834 */     GIR_RootConstrainSelectedInstOperands,
     /* 288835 */     // GIR_Coverage, 8973,
     /* 288835 */     GIR_EraseRootFromParent_Done,
     /* 288836 */   // Label 5613: @288836
     /* 288836 */   GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(288883), // Rule ID 8975 //
     /* 288841 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288844 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288849 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 288852 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 288855 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 288858 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 288861 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 288864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288868 */     // (intrinsic_wo_chain:{ *:[nxv4f32] } 1528:{ *:[iPTR] }, nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3, nxv4f32:{ *:[nxv4f32] }:$Op4)  =>  (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3, ?:{ *:[nxv4f32] }:$Op4)
     /* 288868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
     /* 288871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288875 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288877 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288879 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288881 */     GIR_RootConstrainSelectedInstOperands,
     /* 288882 */     // GIR_Coverage, 8975,
     /* 288882 */     GIR_EraseRootFromParent_Done,
     /* 288883 */   // Label 5614: @288883
     /* 288883 */   GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(288930), // Rule ID 8977 //
     /* 288888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288891 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288896 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s32,
     /* 288899 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288902 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 288905 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s32,
     /* 288908 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s32,
     /* 288911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288915 */     // (intrinsic_wo_chain:{ *:[nxv2f32] } 1528:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3, nxv2f32:{ *:[nxv2f32] }:$Op4)  =>  (FNMLS_ZPZZZ_S_UNDEF:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3, ?:{ *:[nxv2f32] }:$Op4)
     /* 288915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_S_UNDEF),
     /* 288918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288922 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288924 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288926 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288928 */     GIR_RootConstrainSelectedInstOperands,
     /* 288929 */     // GIR_Coverage, 8977,
     /* 288929 */     GIR_EraseRootFromParent_Done,
     /* 288930 */   // Label 5615: @288930
     /* 288930 */   GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(288977), // Rule ID 8979 //
     /* 288935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 288938 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fnmls_u),
     /* 288943 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 288946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 288949 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 288952 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 288955 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 288958 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 288962 */     // (intrinsic_wo_chain:{ *:[nxv2f64] } 1528:{ *:[iPTR] }, nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3, nxv2f64:{ *:[nxv2f64] }:$Op4)  =>  (FNMLS_ZPZZZ_D_UNDEF:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3, ?:{ *:[nxv2f64] }:$Op4)
     /* 288962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMLS_ZPZZZ_D_UNDEF),
     /* 288965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 288967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 288969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 288971 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 288973 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 288975 */     GIR_RootConstrainSelectedInstOperands,
     /* 288976 */     // GIR_Coverage, 8979,
     /* 288976 */     GIR_EraseRootFromParent_Done,
     /* 288977 */   // Label 5616: @288977
     /* 288977 */   GIM_Reject,
     /* 288978 */ // Label 5475: @288978
     /* 288978 */ GIM_Reject,
     /* 288979 */ // Label 44: @288979
     /* 288979 */ GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(289035),
     /* 288984 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
     /* 288987 */   GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(289012), // Rule ID 2419 //
     /* 288992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 288995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_setffr),
     /* 289000 */     // (intrinsic_void 1768:{ *:[iPTR] })  =>  (SETFFR:{ *:[i64] })
     /* 289000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SETFFR),
     /* 289003 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
     /* 289006 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289010 */     GIR_RootConstrainSelectedInstOperands,
     /* 289011 */     // GIR_Coverage, 2419,
     /* 289011 */     GIR_EraseRootFromParent_Done,
     /* 289012 */   // Label 5618: @289012
     /* 289012 */   GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(289034), // Rule ID 7788 //
     /* 289017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_clrex),
     /* 289022 */     // (intrinsic_void 524:{ *:[iPTR] })  =>  (CLREX 15:{ *:[i64] })
     /* 289022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLREX),
     /* 289025 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 289028 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289032 */     GIR_RootConstrainSelectedInstOperands,
     /* 289033 */     // GIR_Coverage, 7788,
     /* 289033 */     GIR_EraseRootFromParent_Done,
     /* 289034 */   // Label 5619: @289034
     /* 289034 */   GIM_Reject,
     /* 289035 */ // Label 5617: @289035
     /* 289035 */ GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(289545),
     /* 289040 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /* 289043 */   GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(289068), // Rule ID 221 //
     /* 289048 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_break),
     /* 289053 */     // MIs[0] imm
     /* 289053 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 289056 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
     /* 289061 */     // (intrinsic_void 522:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm)  =>  (BRK (timm:{ *:[i32] }):$imm)
     /* 289061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 289064 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 289066 */     GIR_RootConstrainSelectedInstOperands,
     /* 289067 */     // GIR_Coverage, 221,
     /* 289067 */     GIR_EraseRootFromParent_Done,
     /* 289068 */   // Label 5621: @289068
     /* 289068 */   GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(289093), // Rule ID 222 //
     /* 289073 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hlt),
     /* 289078 */     // MIs[0] imm
     /* 289078 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 289081 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_65535),
     /* 289086 */     // (intrinsic_void 581:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_65535>>:$imm)  =>  (HLT (timm:{ *:[i32] }):$imm)
     /* 289086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HLT),
     /* 289089 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 289091 */     GIR_RootConstrainSelectedInstOperands,
     /* 289092 */     // GIR_Coverage, 222,
     /* 289092 */     GIR_EraseRootFromParent_Done,
     /* 289093 */   // Label 5622: @289093
     /* 289093 */   GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(289125), // Rule ID 3707 //
     /* 289098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 289101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_zero),
     /* 289106 */     // MIs[0] imm
     /* 289106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 289109 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_255),
     /* 289114 */     // (intrinsic_void 1245:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm)  =>  (ZERO_M_PSEUDO (timm:{ *:[i32] })<<P:Predicate_timm32_0_255>>:$imm)
     /* 289114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZERO_M_PSEUDO),
     /* 289117 */     GIR_RootToRootCopy, /*OpIdx*/1, // imm
     /* 289119 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289123 */     GIR_RootConstrainSelectedInstOperands,
     /* 289124 */     // GIR_Coverage, 3707,
     /* 289124 */     GIR_EraseRootFromParent_Done,
     /* 289125 */   // Label 5623: @289125
     /* 289125 */   GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(289165), // Rule ID 16 //
     /* 289130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_hint),
     /* 289135 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289146 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_127),
     /* 289150 */     // MIs[1] Operand 1
     /* 289150 */     // No operand predicates
     /* 289150 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289152 */     // (intrinsic_void 580:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_127>>:$imm)  =>  (HINT (imm:{ *:[i32] }):$imm)
     /* 289152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HINT),
     /* 289155 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 289158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 289163 */     GIR_RootConstrainSelectedInstOperands,
     /* 289164 */     // GIR_Coverage, 16,
     /* 289164 */     GIR_EraseRootFromParent_Done,
     /* 289165 */   // Label 5624: @289165
     /* 289165 */   GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(289205), // Rule ID 17 //
     /* 289170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dmb),
     /* 289175 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289178 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289182 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289186 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 289190 */     // MIs[1] Operand 1
     /* 289190 */     // No operand predicates
     /* 289190 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289192 */     // (intrinsic_void 568:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DMB (imm:{ *:[i32] }):$CRm)
     /* 289192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DMB),
     /* 289195 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 289198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 289203 */     GIR_RootConstrainSelectedInstOperands,
     /* 289204 */     // GIR_Coverage, 17,
     /* 289204 */     GIR_EraseRootFromParent_Done,
     /* 289205 */   // Label 5625: @289205
     /* 289205 */   GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(289245), // Rule ID 18 //
     /* 289210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_dsb),
     /* 289215 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289226 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 289230 */     // MIs[1] Operand 1
     /* 289230 */     // No operand predicates
     /* 289230 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289232 */     // (intrinsic_void 569:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (DSB (imm:{ *:[i32] }):$CRm)
     /* 289232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DSB),
     /* 289235 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 289238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 289243 */     GIR_RootConstrainSelectedInstOperands,
     /* 289244 */     // GIR_Coverage, 18,
     /* 289244 */     GIR_EraseRootFromParent_Done,
     /* 289245 */   // Label 5626: @289245
     /* 289245 */   GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(289285), // Rule ID 19 //
     /* 289250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_isb),
     /* 289255 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 289258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 289262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 289266 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 289270 */     // MIs[1] Operand 1
     /* 289270 */     // No operand predicates
     /* 289270 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 289272 */     // (intrinsic_void 584:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$CRm)  =>  (ISB (imm:{ *:[i32] }):$CRm)
     /* 289272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ISB),
     /* 289275 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // CRm
     /* 289278 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 289283 */     GIR_RootConstrainSelectedInstOperands,
     /* 289284 */     // GIR_Coverage, 19,
     /* 289284 */     GIR_EraseRootFromParent_Done,
     /* 289285 */   // Label 5627: @289285
     /* 289285 */   GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(289309), // Rule ID 64 //
     /* 289290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpcr),
     /* 289295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289302 */     // (intrinsic_w_chain:{ *:[i64] } 577:{ *:[iPTR] })  =>  (MRS_FPCR:{ *:[i64] })
     /* 289302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPCR),
     /* 289305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289307 */     GIR_RootConstrainSelectedInstOperands,
     /* 289308 */     // GIR_Coverage, 64,
     /* 289308 */     GIR_EraseRootFromParent_Done,
     /* 289309 */   // Label 5628: @289309
     /* 289309 */   GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(289333), // Rule ID 66 //
     /* 289314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_get_fpsr),
     /* 289319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289322 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289326 */     // (intrinsic_w_chain:{ *:[i64] } 578:{ *:[iPTR] })  =>  (MRS_FPSR:{ *:[i64] })
     /* 289326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS_FPSR),
     /* 289329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289331 */     GIR_RootConstrainSelectedInstOperands,
     /* 289332 */     // GIR_Coverage, 66,
     /* 289332 */     GIR_EraseRootFromParent_Done,
     /* 289333 */   // Label 5629: @289333
     /* 289333 */   GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(289364), // Rule ID 2418 //
     /* 289338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 289341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr),
     /* 289346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 289349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 289353 */     // (intrinsic_w_chain:{ *:[nxv16i1] } 1719:{ *:[iPTR] })  =>  (RDFFR_P:{ *:[nxv16i1] })
     /* 289353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_P),
     /* 289356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 289358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289362 */     GIR_RootConstrainSelectedInstOperands,
     /* 289363 */     // GIR_Coverage, 2418,
     /* 289363 */     GIR_EraseRootFromParent_Done,
     /* 289364 */   // Label 5630: @289364
     /* 289364 */   GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(289404), // Rule ID 13839 //
     /* 289369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 289372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sme_get_tpidr2),
     /* 289377 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289384 */     // (intrinsic_w_chain:{ *:[i64] } 914:{ *:[iPTR] })  =>  (MRS:{ *:[i64] }:{ *:[i32] } 56965:{ *:[i32] })
     /* 289384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MRS),
     /* 289387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 289389 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
     /* 289399 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/0,
     /* 289402 */     GIR_RootConstrainSelectedInstOperands,
     /* 289403 */     // GIR_Coverage, 13839,
     /* 289403 */     GIR_EraseRootFromParent_Done,
     /* 289404 */   // Label 5631: @289404
     /* 289404 */   GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(289438), // Rule ID 2420 //
     /* 289409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 289412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_wrffr),
     /* 289417 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 289420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 289424 */     // (intrinsic_void 2206:{ *:[iPTR] }, PPR8:{ *:[nxv16i1] }:$Pn)  =>  (WRFFR:{ *:[i64] } PPR8:{ *:[nxv16i1] }:$Pn)
     /* 289424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::WRFFR),
     /* 289427 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pn
     /* 289429 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FFR*/0,
     /* 289432 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289436 */     GIR_RootConstrainSelectedInstOperands,
     /* 289437 */     // GIR_Coverage, 2420,
     /* 289437 */     GIR_EraseRootFromParent_Done,
     /* 289438 */   // Label 5632: @289438
     /* 289438 */   GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(289461), // Rule ID 65 //
     /* 289443 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpcr),
     /* 289448 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289451 */     // (intrinsic_void 806:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPCR i64:{ *:[i64] }:$val)
     /* 289451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPCR),
     /* 289454 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 289456 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPCR*/0,
     /* 289459 */     GIR_RootConstrainSelectedInstOperands,
     /* 289460 */     // GIR_Coverage, 65,
     /* 289460 */     GIR_EraseRootFromParent_Done,
     /* 289461 */   // Label 5633: @289461
     /* 289461 */   GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(289484), // Rule ID 67 //
     /* 289466 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpsr),
     /* 289471 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289474 */     // (intrinsic_void 808:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPSR i64:{ *:[i64] }:$val)
     /* 289474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPSR),
     /* 289477 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 289479 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPSR*/0,
     /* 289482 */     GIR_RootConstrainSelectedInstOperands,
     /* 289483 */     // GIR_Coverage, 67,
     /* 289483 */     GIR_EraseRootFromParent_Done,
     /* 289484 */   // Label 5634: @289484
     /* 289484 */   GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(289511), // Rule ID 68 //
     /* 289489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_set_fpmr),
     /* 289494 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289497 */     // (intrinsic_void 807:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR_FPMR i64:{ *:[i64] }:$val)
     /* 289497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR_FPMR),
     /* 289500 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 289502 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::FPMR*/0,
     /* 289505 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289509 */     GIR_RootConstrainSelectedInstOperands,
     /* 289510 */     // GIR_Coverage, 68,
     /* 289510 */     GIR_EraseRootFromParent_Done,
     /* 289511 */   // Label 5635: @289511
     /* 289511 */   GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(289544), // Rule ID 13838 //
     /* 289516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEandIsNonStreamingSafe),
     /* 289519 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_set_tpidr2),
     /* 289524 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 289527 */     // (intrinsic_void 989:{ *:[iPTR] }, i64:{ *:[i64] }:$val)  =>  (MSR 56965:{ *:[i32] }, GPR64:{ *:[i64] }:$val)
     /* 289527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSR),
     /* 289530 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(56965),
     /* 289540 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 289542 */     GIR_RootConstrainSelectedInstOperands,
     /* 289543 */     // GIR_Coverage, 13838,
     /* 289543 */     GIR_EraseRootFromParent_Done,
     /* 289544 */   // Label 5636: @289544
     /* 289544 */   GIM_Reject,
     /* 289545 */ // Label 5620: @289545
     /* 289545 */ GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(290516),
     /* 289550 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 289553 */   GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(289629), // Rule ID 7754 //
     /* 289558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 289563 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289570 */     // MIs[0] addr
     /* 289570 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289578 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_1),
     /* 289582 */     // (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 289582 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289585 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRB),
     /* 289589 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289594 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 289598 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289602 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 289604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289609 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 289612 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 289618 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289628 */     // GIR_Coverage, 7754,
     /* 289628 */     GIR_EraseRootFromParent_Done,
     /* 289629 */   // Label 5638: @289629
     /* 289629 */   GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(289705), // Rule ID 7755 //
     /* 289634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 289639 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289646 */     // MIs[0] addr
     /* 289646 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289654 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_2),
     /* 289658 */     // (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_2>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 289658 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289661 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRH),
     /* 289665 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289670 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 289674 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289678 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 289680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289685 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 289688 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289691 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 289694 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289699 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289704 */     // GIR_Coverage, 7755,
     /* 289704 */     GIR_EraseRootFromParent_Done,
     /* 289705 */   // Label 5639: @289705
     /* 289705 */   GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(289781), // Rule ID 7756 //
     /* 289710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 289715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289722 */     // MIs[0] addr
     /* 289722 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289730 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_4),
     /* 289734 */     // (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_4>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 289734 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289737 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDXRW),
     /* 289741 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289746 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 289750 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289754 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 289756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 289764 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289767 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 289770 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289775 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289780 */     // GIR_Coverage, 7756,
     /* 289780 */     GIR_EraseRootFromParent_Done,
     /* 289781 */   // Label 5640: @289781
     /* 289781 */   GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(289823), // Rule ID 7757 //
     /* 289786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldxr),
     /* 289791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289794 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 289798 */     // MIs[0] addr
     /* 289798 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289802 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289806 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldxr_8),
     /* 289810 */     // (intrinsic_w_chain:{ *:[i64] } 590:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldxr_8>>  =>  (LDXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
     /* 289810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDXRX),
     /* 289813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 289815 */     GIR_RootToRootCopy, /*OpIdx*/2, // addr
     /* 289817 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289821 */     GIR_RootConstrainSelectedInstOperands,
     /* 289822 */     // GIR_Coverage, 7757,
     /* 289822 */     GIR_EraseRootFromParent_Done,
     /* 289823 */   // Label 5641: @289823
     /* 289823 */   GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(289899), // Rule ID 7761 //
     /* 289828 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 289833 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289840 */     // MIs[0] addr
     /* 289840 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289848 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_1),
     /* 289852 */     // (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_1>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRB:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 289852 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289855 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRB),
     /* 289859 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289864 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 289868 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289872 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 289874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289879 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 289882 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 289888 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289893 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289898 */     // GIR_Coverage, 7761,
     /* 289898 */     GIR_EraseRootFromParent_Done,
     /* 289899 */   // Label 5642: @289899
     /* 289899 */   GIM_Try, /*On fail goto*//*Label 5643*/ GIMT_Encode4(289975), // Rule ID 7762 //
     /* 289904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 289909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289916 */     // MIs[0] addr
     /* 289916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 289924 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_2),
     /* 289928 */     // (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_2>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRH:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 289928 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 289931 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRH),
     /* 289935 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 289940 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 289944 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 289948 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 289950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 289953 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 289955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 289958 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 289961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 289964 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 289974 */     // GIR_Coverage, 7762,
     /* 289974 */     GIR_EraseRootFromParent_Done,
     /* 289975 */   // Label 5643: @289975
     /* 289975 */   GIM_Try, /*On fail goto*//*Label 5644*/ GIMT_Encode4(290051), // Rule ID 7763 //
     /* 289980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 289985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 289988 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 289992 */     // MIs[0] addr
     /* 289992 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 289996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290000 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_4),
     /* 290004 */     // (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_4>>  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (LDAXRW:{ *:[i32] } GPR64sp:{ *:[i64] }:$addr), sub_32:{ *:[i32] })
     /* 290004 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 290007 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDAXRW),
     /* 290011 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 290016 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // addr
     /* 290020 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290024 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 290026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 290029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 290031 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 290034 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 290037 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 290040 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 290045 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290050 */     // GIR_Coverage, 7763,
     /* 290050 */     GIR_EraseRootFromParent_Done,
     /* 290051 */   // Label 5644: @290051
     /* 290051 */   GIM_Try, /*On fail goto*//*Label 5645*/ GIMT_Encode4(290093), // Rule ID 7764 //
     /* 290056 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_ldaxr),
     /* 290061 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 290064 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290068 */     // MIs[0] addr
     /* 290068 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 290072 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290076 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_ldaxr_8),
     /* 290080 */     // (intrinsic_w_chain:{ *:[i64] } 587:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_ldaxr_8>>  =>  (LDAXRX:{ *:[i64] } GPR64sp:{ *:[i64] }:$addr)
     /* 290080 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAXRX),
     /* 290083 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 290085 */     GIR_RootToRootCopy, /*OpIdx*/2, // addr
     /* 290087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290091 */     GIR_RootConstrainSelectedInstOperands,
     /* 290092 */     // GIR_Coverage, 7764,
     /* 290092 */     GIR_EraseRootFromParent_Done,
     /* 290093 */   // Label 5645: @290093
     /* 290093 */   GIM_Try, /*On fail goto*//*Label 5646*/ GIMT_Encode4(290133), // Rule ID 20 //
     /* 290098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGCS),
     /* 290101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_gcspopm),
     /* 290106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 290109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290116 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290120 */     // (intrinsic_w_chain:{ *:[i64] } 575:{ *:[iPTR] }, GPR64:{ *:[i64] }:$src)  =>  (GCSPOPM:{ *:[i64] } GPR64:{ *:[i64] }:$src)
     /* 290120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::GCSPOPM),
     /* 290123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
     /* 290125 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 290127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290131 */     GIR_RootConstrainSelectedInstOperands,
     /* 290132 */     // GIR_Coverage, 20,
     /* 290132 */     GIR_EraseRootFromParent_Done,
     /* 290133 */   // Label 5646: @290133
     /* 290133 */   GIM_Try, /*On fail goto*//*Label 5647*/ GIMT_Encode4(290173), // Rule ID 2417 //
     /* 290138 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 290141 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_rdffr_z),
     /* 290146 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv16s1,
     /* 290149 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 290152 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 290156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 290160 */     // (intrinsic_w_chain:{ *:[nxv16i1] } 1720:{ *:[iPTR] }, PPRAny:{ *:[nxv16i1] }:$Pg)  =>  (RDFFR_PPz:{ *:[nxv16i1] } PPRAny:{ *:[nxv16i1] }:$Pg)
     /* 290160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RDFFR_PPz),
     /* 290163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 290165 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 290167 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290171 */     GIR_RootConstrainSelectedInstOperands,
     /* 290172 */     // GIR_Coverage, 2417,
     /* 290172 */     GIR_EraseRootFromParent_Done,
     /* 290173 */   // Label 5647: @290173
     /* 290173 */   GIM_Try, /*On fail goto*//*Label 5648*/ GIMT_Encode4(290213), // Rule ID 2525 //
     /* 290178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 290181 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl1),
     /* 290186 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 290189 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 290192 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290196 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290200 */     // (intrinsic_w_chain:{ *:[v8f16] } 636:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (F1CVTL:{ *:[v8f16] } V64:{ *:[v8i8] }:$Rn)
     /* 290200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTL),
     /* 290203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290205 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290211 */     GIR_RootConstrainSelectedInstOperands,
     /* 290212 */     // GIR_Coverage, 2525,
     /* 290212 */     GIR_EraseRootFromParent_Done,
     /* 290213 */   // Label 5648: @290213
     /* 290213 */   GIM_Try, /*On fail goto*//*Label 5649*/ GIMT_Encode4(290253), // Rule ID 2526 //
     /* 290218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 290221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl1),
     /* 290226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 290229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 290232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290236 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290240 */     // (intrinsic_w_chain:{ *:[v8f16] } 636:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (F1CVTL2:{ *:[v8f16] } V128:{ *:[v16i8] }:$Rn)
     /* 290240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTL2),
     /* 290243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290247 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290251 */     GIR_RootConstrainSelectedInstOperands,
     /* 290252 */     // GIR_Coverage, 2526,
     /* 290252 */     GIR_EraseRootFromParent_Done,
     /* 290253 */   // Label 5649: @290253
     /* 290253 */   GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(290293), // Rule ID 7633 //
     /* 290258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 290261 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl2),
     /* 290266 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 290269 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 290272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290276 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 290280 */     // (intrinsic_w_chain:{ *:[v8f16] } 637:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn)  =>  (F2CVTL:{ *:[v8f16] } V64:{ *:[v8i8] }:$Rn)
     /* 290280 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTL),
     /* 290283 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290285 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290287 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290291 */     GIR_RootConstrainSelectedInstOperands,
     /* 290292 */     // GIR_Coverage, 7633,
     /* 290292 */     GIR_EraseRootFromParent_Done,
     /* 290293 */   // Label 5650: @290293
     /* 290293 */   GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(290333), // Rule ID 7634 //
     /* 290298 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 290301 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_cvtl2),
     /* 290306 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 290309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 290312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290316 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 290320 */     // (intrinsic_w_chain:{ *:[v8f16] } 637:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn)  =>  (F2CVTL2:{ *:[v8f16] } V128:{ *:[v16i8] }:$Rn)
     /* 290320 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTL2),
     /* 290323 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290325 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 290327 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290331 */     GIR_RootConstrainSelectedInstOperands,
     /* 290332 */     // GIR_Coverage, 7634,
     /* 290332 */     GIR_EraseRootFromParent_Done,
     /* 290333 */   // Label 5651: @290333
     /* 290333 */   GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(290369), // Rule ID 3659 //
     /* 290338 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 290341 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvt1),
     /* 290346 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 290349 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 290352 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 290356 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1532:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F1CVT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 290356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVT_ZZ_BtoH),
     /* 290359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 290361 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 290363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290367 */     GIR_RootConstrainSelectedInstOperands,
     /* 290368 */     // GIR_Coverage, 3659,
     /* 290368 */     GIR_EraseRootFromParent_Done,
     /* 290369 */   // Label 5652: @290369
     /* 290369 */   GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(290407), // Rule ID 4097 //
     /* 290374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 290377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg_sp),
     /* 290382 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 290385 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290388 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290392 */     // (intrinsic_w_chain:{ *:[i64] } 583:{ *:[iPTR] }, i64:{ *:[i64] }:$Rm)  =>  (IRGstack:{ *:[i64] } SP:{ *:[i64] }, i64:{ *:[i64] }:$Rm)
     /* 290392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRGstack),
     /* 290395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 290397 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::SP), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 290403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 290405 */     GIR_RootConstrainSelectedInstOperands,
     /* 290406 */     // GIR_Coverage, 4097,
     /* 290406 */     GIR_EraseRootFromParent_Done,
     /* 290407 */   // Label 5653: @290407
     /* 290407 */   GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(290443), // Rule ID 13556 //
     /* 290412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 290415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvt2),
     /* 290420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 290423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 290426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 290430 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1534:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F2CVT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 290430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVT_ZZ_BtoH),
     /* 290433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 290435 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 290437 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290441 */     GIR_RootConstrainSelectedInstOperands,
     /* 290442 */     // GIR_Coverage, 13556,
     /* 290442 */     GIR_EraseRootFromParent_Done,
     /* 290443 */   // Label 5654: @290443
     /* 290443 */   GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(290479), // Rule ID 13557 //
     /* 290448 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 290451 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvtlt1),
     /* 290456 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 290459 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 290462 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 290466 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1538:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F1CVTLT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 290466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F1CVTLT_ZZ_BtoH),
     /* 290469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 290471 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 290473 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290477 */     GIR_RootConstrainSelectedInstOperands,
     /* 290478 */     // GIR_Coverage, 13557,
     /* 290478 */     GIR_EraseRootFromParent_Done,
     /* 290479 */   // Label 5655: @290479
     /* 290479 */   GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(290515), // Rule ID 13558 //
     /* 290484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8_HasNonStreamingSVE2_or_SME2),
     /* 290487 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_cvtlt2),
     /* 290492 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 290495 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 290498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 290502 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1539:{ *:[iPTR] }, nxv16i8:{ *:[nxv16i8] }:$Op1)  =>  (F2CVTLT_ZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv16i8] }:$Op1)
     /* 290502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::F2CVTLT_ZZ_BtoH),
     /* 290505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 290507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 290509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 290513 */     GIR_RootConstrainSelectedInstOperands,
     /* 290514 */     // GIR_Coverage, 13558,
     /* 290514 */     GIR_EraseRootFromParent_Done,
     /* 290515 */   // Label 5656: @290515
     /* 290515 */   GIM_Reject,
     /* 290516 */ // Label 5637: @290516
     /* 290516 */ GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(294684),
     /* 290521 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 290524 */   GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(290621), // Rule ID 7772 //
     /* 290529 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 290534 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 290537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290548 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290552 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 290560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 290564 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 290568 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 290572 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290577 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
     /* 290588 */     // MIs[0] addr
     /* 290588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 290592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290596 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 290600 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 290602 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 290602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 290605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 290607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 290611 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 290613 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 290619 */     GIR_RootConstrainSelectedInstOperands,
     /* 290620 */     // GIR_Coverage, 7772,
     /* 290620 */     GIR_EraseRootFromParent_Done,
     /* 290621 */   // Label 5658: @290621
     /* 290621 */   GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(290718), // Rule ID 7773 //
     /* 290626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 290631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 290634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290637 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290649 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290653 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 290657 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 290661 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 290665 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 290669 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290674 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /* 290685 */     // MIs[0] addr
     /* 290685 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 290689 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290693 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 290697 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 290699 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 290699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 290702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 290704 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 290708 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 290710 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 290716 */     GIR_RootConstrainSelectedInstOperands,
     /* 290717 */     // GIR_Coverage, 7773,
     /* 290717 */     GIR_EraseRootFromParent_Done,
     /* 290718 */   // Label 5659: @290718
     /* 290718 */   GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(290815), // Rule ID 7782 //
     /* 290723 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 290728 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 290731 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290750 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 290754 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 290758 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 290762 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 290766 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290771 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(255),
     /* 290782 */     // MIs[0] addr
     /* 290782 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 290786 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290790 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 290794 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 290796 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 255:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 290796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 290799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 290801 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 290805 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 290807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 290813 */     GIR_RootConstrainSelectedInstOperands,
     /* 290814 */     // GIR_Coverage, 7782,
     /* 290814 */     GIR_EraseRootFromParent_Done,
     /* 290815 */   // Label 5660: @290815
     /* 290815 */   GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(290912), // Rule ID 7783 //
     /* 290820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 290825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 290828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290831 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 290843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 290847 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 290851 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 290855 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 290859 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 290863 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290868 */     GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
     /* 290879 */     // MIs[0] addr
     /* 290879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 290883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290887 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 290891 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 290893 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (zext:{ *:[i64] } (and:{ *:[i32] } GPR32:{ *:[i32] }:$val, 65535:{ *:[i32] })), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 290893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 290896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 290898 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // val
     /* 290902 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 290904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 290910 */     GIR_RootConstrainSelectedInstOperands,
     /* 290911 */     // GIR_Coverage, 7783,
     /* 290911 */     GIR_EraseRootFromParent_Done,
     /* 290912 */   // Label 5661: @290912
     /* 290912 */   GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(291023), // Rule ID 7775 //
     /* 290917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 290922 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 290925 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 290928 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 290932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 290936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 290940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 290944 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 290948 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 290953 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
     /* 290964 */     // MIs[0] addr
     /* 290964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 290968 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 290972 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 290976 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 290978 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 290978 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 290981 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 290985 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 290990 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 290996 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 291009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291011 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291014 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291021 */     GIR_RootConstrainSelectedInstOperands,
     /* 291022 */     // GIR_Coverage, 7775,
     /* 291022 */     GIR_EraseRootFromParent_Done,
     /* 291023 */   // Label 5662: @291023
     /* 291023 */   GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(291134), // Rule ID 7776 //
     /* 291028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 291033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291043 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291047 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 291051 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 291055 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 291059 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291064 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 291075 */     // MIs[0] addr
     /* 291075 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291079 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291083 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 291087 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291089 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 291089 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 291092 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 291096 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 291101 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 291107 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291112 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 291120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291122 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291125 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291127 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291132 */     GIR_RootConstrainSelectedInstOperands,
     /* 291133 */     // GIR_Coverage, 7776,
     /* 291133 */     GIR_EraseRootFromParent_Done,
     /* 291134 */   // Label 5663: @291134
     /* 291134 */   GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(291245), // Rule ID 7777 //
     /* 291139 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 291144 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291147 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291154 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291158 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 291162 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 291166 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 291170 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291175 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /* 291186 */     // MIs[0] addr
     /* 291186 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291190 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291194 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 291198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291200 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 291200 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 291203 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 291207 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 291212 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 291218 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291223 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 291231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291233 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291236 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291238 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291243 */     GIR_RootConstrainSelectedInstOperands,
     /* 291244 */     // GIR_Coverage, 7777,
     /* 291244 */     GIR_EraseRootFromParent_Done,
     /* 291245 */   // Label 5664: @291245
     /* 291245 */   GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(291356), // Rule ID 7785 //
     /* 291250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 291255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291261 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 291273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 291277 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 291281 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291286 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
     /* 291297 */     // MIs[0] addr
     /* 291297 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291301 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291305 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 291309 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291311 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 255:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 291311 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 291314 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 291318 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 291323 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 291329 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291334 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291339 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 291342 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291344 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291347 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291354 */     GIR_RootConstrainSelectedInstOperands,
     /* 291355 */     // GIR_Coverage, 7785,
     /* 291355 */     GIR_EraseRootFromParent_Done,
     /* 291356 */   // Label 5665: @291356
     /* 291356 */   GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(291467), // Rule ID 7786 //
     /* 291361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 291366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291372 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291376 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291380 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 291384 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 291388 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 291392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291397 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 291408 */     // MIs[0] addr
     /* 291408 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291412 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291416 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 291420 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291422 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 65535:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 291422 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 291425 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 291429 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 291434 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 291440 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291445 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 291453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291455 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291458 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291460 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291465 */     GIR_RootConstrainSelectedInstOperands,
     /* 291466 */     // GIR_Coverage, 7786,
     /* 291466 */     GIR_EraseRootFromParent_Done,
     /* 291467 */   // Label 5666: @291467
     /* 291467 */   GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(291578), // Rule ID 7787 //
     /* 291472 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 291477 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291480 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291483 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 291495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 291499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 291503 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291508 */     GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294967295),
     /* 291519 */     // MIs[0] addr
     /* 291519 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291523 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291527 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 291531 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291533 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (and:{ *:[i64] } GPR64:{ *:[i64] }:$val, 4294967295:{ *:[i64] }), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 291533 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 291536 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 291540 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 291545 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 291551 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291556 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 291561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 291564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291566 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 291569 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291576 */     GIR_RootConstrainSelectedInstOperands,
     /* 291577 */     // GIR_Coverage, 7787,
     /* 291577 */     GIR_EraseRootFromParent_Done,
     /* 291578 */   // Label 5667: @291578
     /* 291578 */   GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(291629), // Rule ID 62 //
     /* 291583 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_fixedshadow),
     /* 291588 */     // MIs[0] ptr
     /* 291588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 291592 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 291596 */     // MIs[0] accessinfo
     /* 291596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 291599 */     // MIs[0] fixed_shadow
     /* 291599 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 291602 */     // (intrinsic_void 199:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)  =>  (HWASAN_CHECK_MEMACCESS_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
     /* 291602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_FIXEDSHADOW),
     /* 291605 */     GIR_RootToRootCopy, /*OpIdx*/1, // ptr
     /* 291607 */     GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
     /* 291609 */     GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
     /* 291611 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 291614 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 291617 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 291620 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 291623 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291627 */     GIR_RootConstrainSelectedInstOperands,
     /* 291628 */     // GIR_Coverage, 62,
     /* 291628 */     GIR_EraseRootFromParent_Done,
     /* 291629 */   // Label 5668: @291629
     /* 291629 */   GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(291680), // Rule ID 63 //
     /* 291634 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules_fixedshadow),
     /* 291639 */     // MIs[0] ptr
     /* 291639 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 291643 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 291647 */     // MIs[0] accessinfo
     /* 291647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 291650 */     // MIs[0] fixed_shadow
     /* 291650 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 291653 */     // (intrinsic_void 201:{ *:[iPTR] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo, (timm:{ *:[i64] }):$fixed_shadow)
     /* 291653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES_FIXEDSHADOW),
     /* 291656 */     GIR_RootToRootCopy, /*OpIdx*/1, // ptr
     /* 291658 */     GIR_RootToRootCopy, /*OpIdx*/2, // accessinfo
     /* 291660 */     GIR_RootToRootCopy, /*OpIdx*/3, // fixed_shadow
     /* 291662 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 291665 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 291668 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 291671 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 291674 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291678 */     GIR_RootConstrainSelectedInstOperands,
     /* 291679 */     // GIR_Coverage, 63,
     /* 291679 */     GIR_EraseRootFromParent_Done,
     /* 291680 */   // Label 5669: @291680
     /* 291680 */   GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(291749), // Rule ID 7774 //
     /* 291685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 291690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291696 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291700 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291704 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 291708 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 291712 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291717 */     // MIs[0] addr
     /* 291717 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291721 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291725 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 291729 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291731 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 291731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 291734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291736 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 291740 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291742 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291747 */     GIR_RootConstrainSelectedInstOperands,
     /* 291748 */     // GIR_Coverage, 7774,
     /* 291748 */     GIR_EraseRootFromParent_Done,
     /* 291749 */   // Label 5670: @291749
     /* 291749 */   GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(291818), // Rule ID 7784 //
     /* 291754 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 291759 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 291762 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 291765 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 291773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 291777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 291781 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 291786 */     // MIs[0] addr
     /* 291786 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 291790 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 291794 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 291798 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 291800 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$val), GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } GPR32:{ *:[i32] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 291800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 291803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 291805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // val
     /* 291809 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 291811 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 291816 */     GIR_RootConstrainSelectedInstOperands,
     /* 291817 */     // GIR_Coverage, 7784,
     /* 291817 */     GIR_EraseRootFromParent_Done,
     /* 291818 */   // Label 5671: @291818
     /* 291818 */   GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(291860), // Rule ID 3684 //
     /* 291823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 291826 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_wide_1x1),
     /* 291831 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 291834 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 291837 */     // MIs[0] tile
     /* 291837 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 291840 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 291845 */     // (intrinsic_void 1038:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 291845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_BToS_PSEUDO),
     /* 291848 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 291850 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 291852 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 291854 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291858 */     GIR_RootConstrainSelectedInstOperands,
     /* 291859 */     // GIR_Coverage, 3684,
     /* 291859 */     GIR_EraseRootFromParent_Done,
     /* 291860 */   // Label 5672: @291860
     /* 291860 */   GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(291902), // Rule ID 3688 //
     /* 291865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 291868 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_wide_1x1),
     /* 291873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 291876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 291879 */     // MIs[0] tile
     /* 291879 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 291882 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 291887 */     // (intrinsic_void 1038:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4A_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 291887 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_HToS_PSEUDO),
     /* 291890 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 291892 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 291894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 291896 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291900 */     GIR_RootConstrainSelectedInstOperands,
     /* 291901 */     // GIR_Coverage, 3688,
     /* 291901 */     GIR_EraseRootFromParent_Done,
     /* 291902 */   // Label 5673: @291902
     /* 291902 */   GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(291944), // Rule ID 3692 //
     /* 291907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 291910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4a_za64_wide_1x1),
     /* 291915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 291918 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 291921 */     // MIs[0] tile
     /* 291921 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 291924 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 291929 */     // (intrinsic_void 1042:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 291929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4A_MZZ_HtoD_PSEUDO),
     /* 291932 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 291934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 291936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 291938 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291942 */     GIR_RootConstrainSelectedInstOperands,
     /* 291943 */     // GIR_Coverage, 3692,
     /* 291943 */     GIR_EraseRootFromParent_Done,
     /* 291944 */   // Label 5674: @291944
     /* 291944 */   GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(291986), // Rule ID 3862 //
     /* 291949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16_HasSME_MOP4),
     /* 291952 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 291957 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 291960 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 291963 */     // MIs[0] tile
     /* 291963 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 291966 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 291971 */     // (intrinsic_void 935:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4A_MZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 291971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_H_PSEUDO),
     /* 291974 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 291976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 291978 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 291980 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 291984 */     GIR_RootConstrainSelectedInstOperands,
     /* 291985 */     // GIR_Coverage, 3862,
     /* 291985 */     GIR_EraseRootFromParent_Done,
     /* 291986 */   // Label 5675: @291986
     /* 291986 */   GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(292028), // Rule ID 3866 //
     /* 291991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F32_HasSME_MOP4),
     /* 291994 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmop4a_za32_1x1),
     /* 291999 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292002 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292005 */     // MIs[0] tile
     /* 292005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292008 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292013 */     // (intrinsic_void 898:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOP4A_MZZ_BtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_BtoS_PSEUDO),
     /* 292016 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292018 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292026 */     GIR_RootConstrainSelectedInstOperands,
     /* 292027 */     // GIR_Coverage, 3866,
     /* 292027 */     GIR_EraseRootFromParent_Done,
     /* 292028 */   // Label 5676: @292028
     /* 292028 */   GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(292070), // Rule ID 3870 //
     /* 292033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 292041 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 292044 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 292047 */     // MIs[0] tile
     /* 292047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292050 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292055 */     // (intrinsic_void 935:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOP4A_MZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 292055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_S_PSEUDO),
     /* 292058 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292060 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292062 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292068 */     GIR_RootConstrainSelectedInstOperands,
     /* 292069 */     // GIR_Coverage, 3870,
     /* 292069 */     GIR_EraseRootFromParent_Done,
     /* 292070 */   // Label 5677: @292070
     /* 292070 */   GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(292112), // Rule ID 3874 //
     /* 292075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64_HasSME_MOP4),
     /* 292078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_1x1),
     /* 292083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 292086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 292089 */     // MIs[0] tile
     /* 292089 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292092 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292097 */     // (intrinsic_void 935:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOP4A_MZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 292097 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_D_PSEUDO),
     /* 292100 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292102 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292110 */     GIR_RootConstrainSelectedInstOperands,
     /* 292111 */     // GIR_Coverage, 3874,
     /* 292111 */     GIR_EraseRootFromParent_Done,
     /* 292112 */   // Label 5678: @292112
     /* 292112 */   GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(292154), // Rule ID 3878 //
     /* 292117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4a_wide_1x1),
     /* 292125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292128 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292131 */     // MIs[0] tile
     /* 292131 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292134 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292139 */     // (intrinsic_void 939:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4A_MZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 292139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_HtoS_PSEUDO),
     /* 292142 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292146 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292148 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292152 */     GIR_RootConstrainSelectedInstOperands,
     /* 292153 */     // GIR_Coverage, 3878,
     /* 292153 */     GIR_EraseRootFromParent_Done,
     /* 292154 */   // Label 5679: @292154
     /* 292154 */   GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(292196), // Rule ID 3882 //
     /* 292159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F16_HasSME_MOP4),
     /* 292162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmop4a_za16_1x1),
     /* 292167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292173 */     // MIs[0] tile
     /* 292173 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292176 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 292181 */     // (intrinsic_void 894:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOP4A_MZZ_BtoH_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4A_MZZ_BtoH_PSEUDO),
     /* 292184 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292186 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292188 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292190 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292194 */     GIR_RootConstrainSelectedInstOperands,
     /* 292195 */     // GIR_Coverage, 3882,
     /* 292195 */     GIR_EraseRootFromParent_Done,
     /* 292196 */   // Label 5680: @292196
     /* 292196 */   GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(292238), // Rule ID 13643 //
     /* 292201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292204 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_wide_1x1),
     /* 292209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292212 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292215 */     // MIs[0] tile
     /* 292215 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292218 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292223 */     // (intrinsic_void 1046:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_BToS_PSEUDO),
     /* 292226 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292228 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292230 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292232 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292236 */     GIR_RootConstrainSelectedInstOperands,
     /* 292237 */     // GIR_Coverage, 13643,
     /* 292237 */     GIR_EraseRootFromParent_Done,
     /* 292238 */   // Label 5681: @292238
     /* 292238 */   GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(292280), // Rule ID 13647 //
     /* 292243 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292246 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4a_wide_1x1),
     /* 292251 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292254 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292257 */     // MIs[0] tile
     /* 292257 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292260 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292265 */     // (intrinsic_void 1090:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4A_MZZ_BToS_PSEUDO),
     /* 292268 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292274 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292278 */     GIR_RootConstrainSelectedInstOperands,
     /* 292279 */     // GIR_Coverage, 13647,
     /* 292279 */     GIR_EraseRootFromParent_Done,
     /* 292280 */   // Label 5682: @292280
     /* 292280 */   GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(292322), // Rule ID 13651 //
     /* 292285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292288 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4s_wide_1x1),
     /* 292293 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292296 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292299 */     // MIs[0] tile
     /* 292299 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292302 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292307 */     // (intrinsic_void 1098:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4S_MZZ_BToS_PSEUDO),
     /* 292310 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292316 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292320 */     GIR_RootConstrainSelectedInstOperands,
     /* 292321 */     // GIR_Coverage, 13651,
     /* 292321 */     GIR_EraseRootFromParent_Done,
     /* 292322 */   // Label 5683: @292322
     /* 292322 */   GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(292364), // Rule ID 13655 //
     /* 292327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292330 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4a_wide_1x1),
     /* 292335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292338 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292341 */     // MIs[0] tile
     /* 292341 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292344 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292349 */     // (intrinsic_void 1207:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4A_MZZ_BToS_PSEUDO),
     /* 292352 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292354 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292356 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292358 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292362 */     GIR_RootConstrainSelectedInstOperands,
     /* 292363 */     // GIR_Coverage, 13655,
     /* 292363 */     GIR_EraseRootFromParent_Done,
     /* 292364 */   // Label 5684: @292364
     /* 292364 */   GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(292406), // Rule ID 13659 //
     /* 292369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292372 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4s_wide_1x1),
     /* 292377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292383 */     // MIs[0] tile
     /* 292383 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292386 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292391 */     // (intrinsic_void 1215:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4S_MZZ_BToS_PSEUDO),
     /* 292394 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292396 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292400 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292404 */     GIR_RootConstrainSelectedInstOperands,
     /* 292405 */     // GIR_Coverage, 13659,
     /* 292405 */     GIR_EraseRootFromParent_Done,
     /* 292406 */   // Label 5685: @292406
     /* 292406 */   GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(292448), // Rule ID 13663 //
     /* 292411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292414 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_wide_1x1),
     /* 292419 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292422 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292425 */     // MIs[0] tile
     /* 292425 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292428 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292433 */     // (intrinsic_void 1173:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOP4A_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_BToS_PSEUDO),
     /* 292436 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292438 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292440 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292442 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292446 */     GIR_RootConstrainSelectedInstOperands,
     /* 292447 */     // GIR_Coverage, 13663,
     /* 292447 */     GIR_EraseRootFromParent_Done,
     /* 292448 */   // Label 5686: @292448
     /* 292448 */   GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(292490), // Rule ID 13667 //
     /* 292453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292456 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_wide_1x1),
     /* 292461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 292464 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 292467 */     // MIs[0] tile
     /* 292467 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292470 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292475 */     // (intrinsic_void 1181:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOP4S_MZZ_BToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 292475 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_BToS_PSEUDO),
     /* 292478 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292488 */     GIR_RootConstrainSelectedInstOperands,
     /* 292489 */     // GIR_Coverage, 13667,
     /* 292489 */     GIR_EraseRootFromParent_Done,
     /* 292490 */   // Label 5687: @292490
     /* 292490 */   GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(292532), // Rule ID 13671 //
     /* 292495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_wide_1x1),
     /* 292503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292509 */     // MIs[0] tile
     /* 292509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292512 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292517 */     // (intrinsic_void 1046:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4S_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_HToS_PSEUDO),
     /* 292520 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292526 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292530 */     GIR_RootConstrainSelectedInstOperands,
     /* 292531 */     // GIR_Coverage, 13671,
     /* 292531 */     GIR_EraseRootFromParent_Done,
     /* 292532 */   // Label 5688: @292532
     /* 292532 */   GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(292574), // Rule ID 13675 //
     /* 292537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_wide_1x1),
     /* 292545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292551 */     // MIs[0] tile
     /* 292551 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292554 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292559 */     // (intrinsic_void 1173:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4A_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_HToS_PSEUDO),
     /* 292562 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292568 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292572 */     GIR_RootConstrainSelectedInstOperands,
     /* 292573 */     // GIR_Coverage, 13675,
     /* 292573 */     GIR_EraseRootFromParent_Done,
     /* 292574 */   // Label 5689: @292574
     /* 292574 */   GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(292616), // Rule ID 13679 //
     /* 292579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_wide_1x1),
     /* 292587 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292590 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292593 */     // MIs[0] tile
     /* 292593 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292596 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292601 */     // (intrinsic_void 1181:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4S_MZZ_HToS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_HToS_PSEUDO),
     /* 292604 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292610 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292614 */     GIR_RootConstrainSelectedInstOperands,
     /* 292615 */     // GIR_Coverage, 13679,
     /* 292615 */     GIR_EraseRootFromParent_Done,
     /* 292616 */   // Label 5690: @292616
     /* 292616 */   GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(292658), // Rule ID 13683 //
     /* 292621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292624 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smop4s_za64_wide_1x1),
     /* 292629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292635 */     // MIs[0] tile
     /* 292635 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292638 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292643 */     // (intrinsic_void 1050:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOP4S_MZZ_HtoD_PSEUDO),
     /* 292646 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292648 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292656 */     GIR_RootConstrainSelectedInstOperands,
     /* 292657 */     // GIR_Coverage, 13683,
     /* 292657 */     GIR_EraseRootFromParent_Done,
     /* 292658 */   // Label 5691: @292658
     /* 292658 */   GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(292700), // Rule ID 13687 //
     /* 292663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4a_za64_wide_1x1),
     /* 292671 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292674 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292677 */     // MIs[0] tile
     /* 292677 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292680 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292685 */     // (intrinsic_void 1094:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4A_MZZ_HtoD_PSEUDO),
     /* 292688 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292692 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292694 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292698 */     GIR_RootConstrainSelectedInstOperands,
     /* 292699 */     // GIR_Coverage, 13687,
     /* 292699 */     GIR_EraseRootFromParent_Done,
     /* 292700 */   // Label 5692: @292700
     /* 292700 */   GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(292742), // Rule ID 13691 //
     /* 292705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292708 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumop4s_za64_wide_1x1),
     /* 292713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292719 */     // MIs[0] tile
     /* 292719 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292722 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292727 */     // (intrinsic_void 1102:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292727 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOP4S_MZZ_HtoD_PSEUDO),
     /* 292730 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292732 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292734 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292736 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292740 */     GIR_RootConstrainSelectedInstOperands,
     /* 292741 */     // GIR_Coverage, 13691,
     /* 292741 */     GIR_EraseRootFromParent_Done,
     /* 292742 */   // Label 5693: @292742
     /* 292742 */   GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(292784), // Rule ID 13695 //
     /* 292747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4a_za64_wide_1x1),
     /* 292755 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292758 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292761 */     // MIs[0] tile
     /* 292761 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292764 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292769 */     // (intrinsic_void 1177:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4A_MZZ_HtoD_PSEUDO),
     /* 292772 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292774 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292776 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292778 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292782 */     GIR_RootConstrainSelectedInstOperands,
     /* 292783 */     // GIR_Coverage, 13695,
     /* 292783 */     GIR_EraseRootFromParent_Done,
     /* 292784 */   // Label 5694: @292784
     /* 292784 */   GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(292826), // Rule ID 13699 //
     /* 292789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umop4s_za64_wide_1x1),
     /* 292797 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292800 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292803 */     // MIs[0] tile
     /* 292803 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292806 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292811 */     // (intrinsic_void 1185:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOP4S_MZZ_HtoD_PSEUDO),
     /* 292814 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292816 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292820 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292824 */     GIR_RootConstrainSelectedInstOperands,
     /* 292825 */     // GIR_Coverage, 13699,
     /* 292825 */     GIR_EraseRootFromParent_Done,
     /* 292826 */   // Label 5695: @292826
     /* 292826 */   GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(292868), // Rule ID 13703 //
     /* 292831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292834 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4a_za64_wide_1x1),
     /* 292839 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292842 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292845 */     // MIs[0] tile
     /* 292845 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292848 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292853 */     // (intrinsic_void 1211:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOP4A_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4A_MZZ_HtoD_PSEUDO),
     /* 292856 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292858 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292862 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292866 */     GIR_RootConstrainSelectedInstOperands,
     /* 292867 */     // GIR_Coverage, 13703,
     /* 292867 */     GIR_EraseRootFromParent_Done,
     /* 292868 */   // Label 5696: @292868
     /* 292868 */   GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(292910), // Rule ID 13707 //
     /* 292873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64_HasSME_MOP4),
     /* 292876 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmop4s_za64_wide_1x1),
     /* 292881 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292884 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292887 */     // MIs[0] tile
     /* 292887 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292890 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 292895 */     // (intrinsic_void 1219:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOP4S_MZZ_HtoD_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 292895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOP4S_MZZ_HtoD_PSEUDO),
     /* 292898 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292908 */     GIR_RootConstrainSelectedInstOperands,
     /* 292909 */     // GIR_Coverage, 13707,
     /* 292909 */     GIR_EraseRootFromParent_Done,
     /* 292910 */   // Label 5697: @292910
     /* 292910 */   GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(292952), // Rule ID 14160 //
     /* 292915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_wide_1x1),
     /* 292923 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 292926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 292929 */     // MIs[0] tile
     /* 292929 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292932 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292937 */     // (intrinsic_void 947:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4S_MZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 292937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_HtoS_PSEUDO),
     /* 292940 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292942 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292944 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292950 */     GIR_RootConstrainSelectedInstOperands,
     /* 292951 */     // GIR_Coverage, 14160,
     /* 292951 */     GIR_EraseRootFromParent_Done,
     /* 292952 */   // Label 5698: @292952
     /* 292952 */   GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(292994), // Rule ID 14164 //
     /* 292957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME_MOP4),
     /* 292960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 292965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 292968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 292971 */     // MIs[0] tile
     /* 292971 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 292974 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 292979 */     // (intrinsic_void 943:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOP4S_MZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 292979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_S_PSEUDO),
     /* 292982 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 292984 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 292986 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 292988 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 292992 */     GIR_RootConstrainSelectedInstOperands,
     /* 292993 */     // GIR_Coverage, 14164,
     /* 292993 */     GIR_EraseRootFromParent_Done,
     /* 292994 */   // Label 5699: @292994
     /* 292994 */   GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(293036), // Rule ID 14168 //
     /* 292999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16_HasSME_MOP4),
     /* 293002 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 293007 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 293010 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 293013 */     // MIs[0] tile
     /* 293013 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 293016 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 293021 */     // (intrinsic_void 943:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOP4S_MZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 293021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_H_PSEUDO),
     /* 293024 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 293026 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 293028 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 293030 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293034 */     GIR_RootConstrainSelectedInstOperands,
     /* 293035 */     // GIR_Coverage, 14168,
     /* 293035 */     GIR_EraseRootFromParent_Done,
     /* 293036 */   // Label 5700: @293036
     /* 293036 */   GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(293078), // Rule ID 14172 //
     /* 293041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64_HasSME_MOP4),
     /* 293044 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mop4s_1x1),
     /* 293049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 293052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 293055 */     // MIs[0] tile
     /* 293055 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 293058 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 293063 */     // (intrinsic_void 943:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOP4S_MZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 293063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOP4S_MZZ_D_PSEUDO),
     /* 293066 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 293068 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 293070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 293072 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293076 */     GIR_RootConstrainSelectedInstOperands,
     /* 293077 */     // GIR_Coverage, 14172,
     /* 293077 */     GIR_EraseRootFromParent_Done,
     /* 293078 */   // Label 5701: @293078
     /* 293078 */   GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(293132), // Rule ID 9583 //
     /* 293083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 293086 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 293091 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 293094 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 293098 */     // MIs[0] base
     /* 293098 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293106 */     // MIs[0] prfop
     /* 293106 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293109 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 293114 */     // (intrinsic_void 1687:{ *:[iPTR] }, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv16i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 293114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_PRI),
     /* 293117 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 293119 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 293121 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 293123 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 293126 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293130 */     GIR_RootConstrainSelectedInstOperands,
     /* 293131 */     // GIR_Coverage, 9583,
     /* 293131 */     GIR_EraseRootFromParent_Done,
     /* 293132 */   // Label 5702: @293132
     /* 293132 */   GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(293186), // Rule ID 9586 //
     /* 293137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 293140 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 293145 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 293148 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 293152 */     // MIs[0] base
     /* 293152 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293156 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293160 */     // MIs[0] prfop
     /* 293160 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293163 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 293168 */     // (intrinsic_void 1687:{ *:[iPTR] }, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv8i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 293168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_PRI),
     /* 293171 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 293173 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 293175 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 293177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 293180 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293184 */     GIR_RootConstrainSelectedInstOperands,
     /* 293185 */     // GIR_Coverage, 9586,
     /* 293185 */     GIR_EraseRootFromParent_Done,
     /* 293186 */   // Label 5703: @293186
     /* 293186 */   GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(293240), // Rule ID 9589 //
     /* 293191 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 293194 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 293199 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 293202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 293206 */     // MIs[0] base
     /* 293206 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293210 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293214 */     // MIs[0] prfop
     /* 293214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293217 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 293222 */     // (intrinsic_void 1687:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 293222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_PRI),
     /* 293225 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 293227 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 293229 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 293231 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 293234 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293238 */     GIR_RootConstrainSelectedInstOperands,
     /* 293239 */     // GIR_Coverage, 9589,
     /* 293239 */     GIR_EraseRootFromParent_Done,
     /* 293240 */   // Label 5704: @293240
     /* 293240 */   GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(293294), // Rule ID 9592 //
     /* 293245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 293248 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prf),
     /* 293253 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 293256 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 293260 */     // MIs[0] base
     /* 293260 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293264 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293268 */     // MIs[0] prfop
     /* 293268 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293271 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 293276 */     // (intrinsic_void 1687:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_PRI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$gp, GPR64:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 293276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_PRI),
     /* 293279 */     GIR_RootToRootCopy, /*OpIdx*/3, // prfop
     /* 293281 */     GIR_RootToRootCopy, /*OpIdx*/1, // gp
     /* 293283 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 293285 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 293288 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293292 */     GIR_RootConstrainSelectedInstOperands,
     /* 293293 */     // GIR_Coverage, 9592,
     /* 293293 */     GIR_EraseRootFromParent_Done,
     /* 293294 */   // Label 5705: @293294
     /* 293294 */   GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(293348), // Rule ID 15 //
     /* 293299 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_space),
     /* 293304 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 293307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 293310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 293313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293317 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 293321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 293325 */     // MIs[1] Operand 1
     /* 293325 */     // No operand predicates
     /* 293325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293329 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 293331 */     // (intrinsic_w_chain:{ *:[i64] } 1255:{ *:[iPTR] }, (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn)  =>  (SPACE:{ *:[i64] } (imm:{ *:[i32] }):$size, GPR64:{ *:[i64] }:$Rn)
     /* 293331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SPACE),
     /* 293334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 293336 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // size
     /* 293339 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 293341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 293346 */     GIR_RootConstrainSelectedInstOperands,
     /* 293347 */     // GIR_Coverage, 15,
     /* 293347 */     GIR_EraseRootFromParent_Done,
     /* 293348 */   // Label 5706: @293348
     /* 293348 */   GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(293416), // Rule ID 60 //
     /* 293353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess),
     /* 293358 */     // MIs[0] Operand 1
     /* 293358 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 293362 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64_with_sub_32_in_MatrixIndexGPR32_8_11RegClassID),
     /* 293366 */     // MIs[0] ptr
     /* 293366 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293370 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 293374 */     // MIs[0] accessinfo
     /* 293374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293377 */     // (intrinsic_void 198:{ *:[iPTR] }, X9:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
     /* 293377 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293381 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X9), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293387 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X9
     /* 293391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS),
     /* 293394 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 293396 */     GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
     /* 293398 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 293401 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 293404 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 293407 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 293410 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293414 */     GIR_RootConstrainSelectedInstOperands,
     /* 293415 */     // GIR_Coverage, 60,
     /* 293415 */     GIR_EraseRootFromParent_Done,
     /* 293416 */   // Label 5707: @293416
     /* 293416 */   GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(293484), // Rule ID 61 //
     /* 293421 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::hwasan_check_memaccess_shortgranules),
     /* 293426 */     // MIs[0] Operand 1
     /* 293426 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 293430 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64common_and_GPR64noipRegClassID),
     /* 293434 */     // MIs[0] ptr
     /* 293434 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 293438 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64noipRegClassID),
     /* 293442 */     // MIs[0] accessinfo
     /* 293442 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 293445 */     // (intrinsic_void 200:{ *:[iPTR] }, X20:{ *:[i64] }, GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)  =>  (HWASAN_CHECK_MEMACCESS_SHORTGRANULES:{ *:[i64] } GPR64noip:{ *:[i64] }:$ptr, (timm:{ *:[i32] }):$accessinfo)
     /* 293445 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293449 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::X20), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293455 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // X20
     /* 293459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES),
     /* 293462 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 293464 */     GIR_RootToRootCopy, /*OpIdx*/3, // accessinfo
     /* 293466 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X16*/0,
     /* 293469 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::X17*/1,
     /* 293472 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::LR*/2,
     /* 293475 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AArch64::NZCV*/3,
     /* 293478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293482 */     GIR_RootConstrainSelectedInstOperands,
     /* 293483 */     // GIR_Coverage, 61,
     /* 293483 */     GIR_EraseRootFromParent_Done,
     /* 293484 */   // Label 5708: @293484
     /* 293484 */   GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(293564), // Rule ID 7768 //
     /* 293489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 293494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293508 */     // MIs[0] addr
     /* 293508 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293512 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293516 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_1),
     /* 293520 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_1>>  =>  (STXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293520 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293523 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293527 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293532 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293538 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRB),
     /* 293551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293553 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 293556 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293558 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293562 */     GIR_RootConstrainSelectedInstOperands,
     /* 293563 */     // GIR_Coverage, 7768,
     /* 293563 */     GIR_EraseRootFromParent_Done,
     /* 293564 */   // Label 5709: @293564
     /* 293564 */   GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(293644), // Rule ID 7769 //
     /* 293569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 293574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293588 */     // MIs[0] addr
     /* 293588 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293596 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_2),
     /* 293600 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_2>>  =>  (STXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293600 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293603 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293607 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293612 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293618 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRH),
     /* 293631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293633 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 293636 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293638 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293642 */     GIR_RootConstrainSelectedInstOperands,
     /* 293643 */     // GIR_Coverage, 7769,
     /* 293643 */     GIR_EraseRootFromParent_Done,
     /* 293644 */   // Label 5710: @293644
     /* 293644 */   GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(293724), // Rule ID 7770 //
     /* 293649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 293654 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293668 */     // MIs[0] addr
     /* 293668 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293672 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293676 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_4),
     /* 293680 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_4>>  =>  (STXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293680 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293683 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293687 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293692 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293698 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293703 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRW),
     /* 293711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293713 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 293716 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293718 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293722 */     GIR_RootConstrainSelectedInstOperands,
     /* 293723 */     // GIR_Coverage, 7770,
     /* 293723 */     GIR_EraseRootFromParent_Done,
     /* 293724 */   // Label 5711: @293724
     /* 293724 */   GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(293775), // Rule ID 7771 //
     /* 293729 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxr),
     /* 293734 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293737 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293744 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293748 */     // MIs[0] addr
     /* 293748 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293752 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293756 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stxr_8),
     /* 293760 */     // (intrinsic_w_chain:{ *:[i32] } 1264:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stxr_8>>  =>  (STXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 293760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXRX),
     /* 293763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293765 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /* 293767 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293769 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293773 */     GIR_RootConstrainSelectedInstOperands,
     /* 293774 */     // GIR_Coverage, 7771,
     /* 293774 */     GIR_EraseRootFromParent_Done,
     /* 293775 */   // Label 5712: @293775
     /* 293775 */   GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(293855), // Rule ID 7778 //
     /* 293780 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 293785 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293788 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293791 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293795 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293799 */     // MIs[0] addr
     /* 293799 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293803 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293807 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_1),
     /* 293811 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_1>>  =>  (STLXRB:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293811 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293814 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293818 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293823 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293829 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293834 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRB),
     /* 293842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293844 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 293847 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293849 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293853 */     GIR_RootConstrainSelectedInstOperands,
     /* 293854 */     // GIR_Coverage, 7778,
     /* 293854 */     GIR_EraseRootFromParent_Done,
     /* 293855 */   // Label 5713: @293855
     /* 293855 */   GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(293935), // Rule ID 7779 //
     /* 293860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 293865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293879 */     // MIs[0] addr
     /* 293879 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293887 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_2),
     /* 293891 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_2>>  =>  (STLXRH:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293891 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293894 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293898 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293903 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293909 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293914 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRH),
     /* 293922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 293924 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 293927 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 293929 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 293933 */     GIR_RootConstrainSelectedInstOperands,
     /* 293934 */     // GIR_Coverage, 7779,
     /* 293934 */     GIR_EraseRootFromParent_Done,
     /* 293935 */   // Label 5714: @293935
     /* 293935 */   GIM_Try, /*On fail goto*//*Label 5715*/ GIMT_Encode4(294015), // Rule ID 7780 //
     /* 293940 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 293945 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 293948 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 293951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293959 */     // MIs[0] addr
     /* 293959 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 293963 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 293967 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_4),
     /* 293971 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_4>>  =>  (STLXRW:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$val, sub_32:{ *:[i32] }), GPR64sp:{ *:[i64] }:$addr)
     /* 293971 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 293974 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 293978 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 293983 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // val
     /* 293989 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 293994 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 293999 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRW),
     /* 294002 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 294004 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 294007 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 294009 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294013 */     GIR_RootConstrainSelectedInstOperands,
     /* 294014 */     // GIR_Coverage, 7780,
     /* 294014 */     GIR_EraseRootFromParent_Done,
     /* 294015 */   // Label 5715: @294015
     /* 294015 */   GIM_Try, /*On fail goto*//*Label 5716*/ GIMT_Encode4(294066), // Rule ID 7781 //
     /* 294020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxr),
     /* 294025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 294028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 294031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 294035 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 294039 */     // MIs[0] addr
     /* 294039 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294047 */     GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_stlxr_8),
     /* 294051 */     // (intrinsic_w_chain:{ *:[i32] } 1262:{ *:[iPTR] }, GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)<<P:Predicate_stlxr_8>>  =>  (STLXRX:{ *:[i32] } GPR64:{ *:[i64] }:$val, GPR64sp:{ *:[i64] }:$addr)
     /* 294051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXRX),
     /* 294054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 294056 */     GIR_RootToRootCopy, /*OpIdx*/2, // val
     /* 294058 */     GIR_RootToRootCopy, /*OpIdx*/3, // addr
     /* 294060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294064 */     GIR_RootConstrainSelectedInstOperands,
     /* 294065 */     // GIR_Coverage, 7781,
     /* 294065 */     GIR_EraseRootFromParent_Done,
     /* 294066 */   // Label 5716: @294066
     /* 294066 */   GIM_Try, /*On fail goto*//*Label 5717*/ GIMT_Encode4(294115), // Rule ID 2518 //
     /* 294071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 294074 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 294079 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 294082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 294085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 294088 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294100 */     // (intrinsic_w_chain:{ *:[v8i8] } 638:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCVTN_F16v8f8:{ *:[v8i8] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 294100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F16v8f8),
     /* 294103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294109 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294113 */     GIR_RootConstrainSelectedInstOperands,
     /* 294114 */     // GIR_Coverage, 2518,
     /* 294114 */     GIR_EraseRootFromParent_Done,
     /* 294115 */   // Label 5717: @294115
     /* 294115 */   GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(294164), // Rule ID 2519 //
     /* 294120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 294123 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 294128 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 294131 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 294134 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 294137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294141 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294145 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294149 */     // (intrinsic_w_chain:{ *:[v16i8] } 638:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTN_F16v16f8:{ *:[v16i8] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 294149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F16v16f8),
     /* 294152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294154 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294156 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294158 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294162 */     GIR_RootConstrainSelectedInstOperands,
     /* 294163 */     // GIR_Coverage, 2519,
     /* 294163 */     GIR_EraseRootFromParent_Done,
     /* 294164 */   // Label 5718: @294164
     /* 294164 */   GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(294213), // Rule ID 2520 //
     /* 294169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 294172 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn),
     /* 294177 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
     /* 294180 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 294183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 294186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 294190 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294194 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 294198 */     // (intrinsic_w_chain:{ *:[v8i8] } 638:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCVTN_F32v8f8:{ *:[v8i8] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 294198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F32v8f8),
     /* 294201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294205 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294207 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294211 */     GIR_RootConstrainSelectedInstOperands,
     /* 294212 */     // GIR_Coverage, 2520,
     /* 294212 */     GIR_EraseRootFromParent_Done,
     /* 294213 */   // Label 5719: @294213
     /* 294213 */   GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(294266), // Rule ID 9469 //
     /* 294218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294221 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
     /* 294226 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 294229 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294236 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294240 */     // MIs[0] base
     /* 294240 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294244 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294248 */     // (intrinsic_w_chain:{ *:[nxv4i32] } 1618:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1W_Q_IMM:{ *:[nxv4i32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
     /* 294251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 294253 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294255 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294257 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294260 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294264 */     GIR_RootConstrainSelectedInstOperands,
     /* 294265 */     // GIR_Coverage, 9469,
     /* 294265 */     GIR_EraseRootFromParent_Done,
     /* 294266 */   // Label 5720: @294266
     /* 294266 */   GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(294319), // Rule ID 9472 //
     /* 294271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294274 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1uwq),
     /* 294279 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 294282 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294285 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294293 */     // MIs[0] base
     /* 294293 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294297 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294301 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1618:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1W_Q_IMM:{ *:[nxv4f32] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1W_Q_IMM),
     /* 294304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 294306 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294308 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294310 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294313 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294317 */     GIR_RootConstrainSelectedInstOperands,
     /* 294318 */     // GIR_Coverage, 9472,
     /* 294318 */     GIR_EraseRootFromParent_Done,
     /* 294319 */   // Label 5721: @294319
     /* 294319 */   GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(294372), // Rule ID 9481 //
     /* 294324 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294327 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
     /* 294332 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 294335 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294338 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294342 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294346 */     // MIs[0] base
     /* 294346 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294350 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294354 */     // (intrinsic_w_chain:{ *:[nxv2i64] } 1617:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1D_Q_IMM:{ *:[nxv2i64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294354 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
     /* 294357 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 294359 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294361 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294363 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294366 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294370 */     GIR_RootConstrainSelectedInstOperands,
     /* 294371 */     // GIR_Coverage, 9481,
     /* 294371 */     GIR_EraseRootFromParent_Done,
     /* 294372 */   // Label 5722: @294372
     /* 294372 */   GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(294425), // Rule ID 9484 //
     /* 294377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_ld1udq),
     /* 294385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv2s64,
     /* 294388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294391 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294399 */     // MIs[0] base
     /* 294399 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294403 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294407 */     // (intrinsic_w_chain:{ *:[nxv2f64] } 1617:{ *:[iPTR] }, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (LD1D_Q_IMM:{ *:[nxv2f64] } PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1D_Q_IMM),
     /* 294410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zt]
     /* 294412 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294414 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294423 */     GIR_RootConstrainSelectedInstOperands,
     /* 294424 */     // GIR_Coverage, 9484,
     /* 294424 */     GIR_EraseRootFromParent_Done,
     /* 294425 */   // Label 5723: @294425
     /* 294425 */   GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(294471), // Rule ID 125 //
     /* 294430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMTE),
     /* 294433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_irg),
     /* 294438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 294441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 294444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294448 */     // MIs[0] Rn
     /* 294448 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 294452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294456 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 294460 */     // (intrinsic_w_chain:{ *:[i64] } 582:{ *:[iPTR] }, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (IRG:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 294460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::IRG),
     /* 294463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 294465 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 294467 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 294469 */     GIR_RootConstrainSelectedInstOperands,
     /* 294470 */     // GIR_Coverage, 125,
     /* 294470 */     GIR_EraseRootFromParent_Done,
     /* 294471 */   // Label 5724: @294471
     /* 294471 */   GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(294524), // Rule ID 9475 //
     /* 294476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294479 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
     /* 294484 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 294487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294490 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294494 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294498 */     // MIs[0] base
     /* 294498 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294502 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294506 */     // (intrinsic_void 1943:{ *:[iPTR] }, ZPR128:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1W_Q_IMM Z_q:{ *:[nxv4i32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
     /* 294509 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 294511 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294513 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294515 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294518 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294522 */     GIR_RootConstrainSelectedInstOperands,
     /* 294523 */     // GIR_Coverage, 9475,
     /* 294523 */     GIR_EraseRootFromParent_Done,
     /* 294524 */   // Label 5725: @294524
     /* 294524 */   GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(294577), // Rule ID 9478 //
     /* 294529 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294532 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1wq),
     /* 294537 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 294540 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294543 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294547 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294551 */     // MIs[0] base
     /* 294551 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294555 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294559 */     // (intrinsic_void 1943:{ *:[iPTR] }, ZPR128:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1W_Q_IMM Z_q:{ *:[nxv4f32] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1W_Q_IMM),
     /* 294562 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 294564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294566 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294568 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294571 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294575 */     GIR_RootConstrainSelectedInstOperands,
     /* 294576 */     // GIR_Coverage, 9478,
     /* 294576 */     GIR_EraseRootFromParent_Done,
     /* 294577 */   // Label 5726: @294577
     /* 294577 */   GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(294630), // Rule ID 9487 //
     /* 294582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
     /* 294590 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 294593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294596 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294600 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294604 */     // MIs[0] base
     /* 294604 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294608 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294612 */     // (intrinsic_void 1939:{ *:[iPTR] }, ZPR128:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1D_Q_IMM Z_q:{ *:[nxv2i64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
     /* 294615 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 294617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294619 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294624 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294628 */     GIR_RootConstrainSelectedInstOperands,
     /* 294629 */     // GIR_Coverage, 9487,
     /* 294629 */     GIR_EraseRootFromParent_Done,
     /* 294630 */   // Label 5727: @294630
     /* 294630 */   GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(294683), // Rule ID 9490 //
     /* 294635 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 294638 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_st1dq),
     /* 294643 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 294646 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 294649 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294657 */     // MIs[0] base
     /* 294657 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/3, /*SizeInBits*/64,
     /* 294661 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 294665 */     // (intrinsic_void 1939:{ *:[iPTR] }, ZPR128:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base)  =>  (ST1D_Q_IMM Z_q:{ *:[nxv2f64] }:$Zt, PPR3bAny:{ *:[nxv1i1] }:$Pg, GPR64sp:{ *:[i64] }:$base, 0:{ *:[i64] })
     /* 294665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ST1D_Q_IMM),
     /* 294668 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zt
     /* 294670 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pg
     /* 294672 */     GIR_RootToRootCopy, /*OpIdx*/3, // base
     /* 294674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 294677 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294681 */     GIR_RootConstrainSelectedInstOperands,
     /* 294682 */     // GIR_Coverage, 9490,
     /* 294682 */     GIR_EraseRootFromParent_Done,
     /* 294683 */   // Label 5728: @294683
     /* 294683 */   GIM_Reject,
     /* 294684 */ // Label 5657: @294684
     /* 294684 */ GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(297481),
     /* 294689 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /* 294692 */   GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(294763), // Rule ID 3494 //
     /* 294697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 294700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
     /* 294705 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 294708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 294711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 294714 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 294730 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 294734 */     // MIs[1] Operand 1
     /* 294734 */     // No operand predicates
     /* 294734 */     // MIs[0] prfop
     /* 294734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 294737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 294742 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294744 */     // (intrinsic_void 1689:{ *:[iPTR] }, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv4i1] }:$Pg, ZPR32:{ *:[nxv4i32] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 294744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_PZI),
     /* 294747 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 294749 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 294751 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 294753 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 294756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 294761 */     GIR_RootConstrainSelectedInstOperands,
     /* 294762 */     // GIR_Coverage, 3494,
     /* 294762 */     GIR_EraseRootFromParent_Done,
     /* 294763 */   // Label 5730: @294763
     /* 294763 */   GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(294834), // Rule ID 3507 //
     /* 294768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 294771 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_scalar_offset),
     /* 294776 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 294779 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 294782 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 294785 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294789 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 294797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 294801 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 294805 */     // MIs[1] Operand 1
     /* 294805 */     // No operand predicates
     /* 294805 */     // MIs[0] prfop
     /* 294805 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 294808 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 294813 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 294815 */     // (intrinsic_void 1689:{ *:[iPTR] }, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_PZI (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR_3b:{ *:[nxv2i1] }:$Pg, ZPR32:{ *:[nxv2i64] }:$Zn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 294815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_PZI),
     /* 294818 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 294820 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 294822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Zn
     /* 294824 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 294827 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 294832 */     GIR_RootConstrainSelectedInstOperands,
     /* 294833 */     // GIR_Coverage, 3507,
     /* 294833 */     GIR_EraseRootFromParent_Done,
     /* 294834 */   // Label 5731: @294834
     /* 294834 */   GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(294893), // Rule ID 3696 //
     /* 294839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 294842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
     /* 294847 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 294850 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 294853 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 294856 */     // MIs[0] tile
     /* 294856 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 294859 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 294864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294868 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294872 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294876 */     // (intrinsic_void 823:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn)  =>  (ADDHA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
     /* 294876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_S_PSEUDO_S),
     /* 294879 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 294881 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 294883 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 294885 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 294887 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294891 */     GIR_RootConstrainSelectedInstOperands,
     /* 294892 */     // GIR_Coverage, 3696,
     /* 294892 */     GIR_EraseRootFromParent_Done,
     /* 294893 */   // Label 5732: @294893
     /* 294893 */   GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(294952), // Rule ID 3697 //
     /* 294898 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 294901 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addha),
     /* 294906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 294909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 294912 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 294915 */     // MIs[0] tile
     /* 294915 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 294918 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 294923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294927 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294931 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294935 */     // (intrinsic_void 823:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn)  =>  (ADDHA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
     /* 294935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHA_MPPZ_D_PSEUDO_D),
     /* 294938 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 294940 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 294942 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 294944 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 294946 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 294950 */     GIR_RootConstrainSelectedInstOperands,
     /* 294951 */     // GIR_Coverage, 3697,
     /* 294951 */     GIR_EraseRootFromParent_Done,
     /* 294952 */   // Label 5733: @294952
     /* 294952 */   GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(295011), // Rule ID 13624 //
     /* 294957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 294960 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
     /* 294965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 294968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 294971 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 294974 */     // MIs[0] tile
     /* 294974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 294977 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 294982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294986 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 294990 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 294994 */     // (intrinsic_void 824:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$pn, PPR3bAny:{ *:[nxv4i1] }:$pm, ZPR32:{ *:[nxv4i32] }:$zn)  =>  (ADDVA_MPPZ_S_PSEUDO_S (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, ?:{ *:[nxv4i1] }:$pn, ?:{ *:[nxv4i1] }:$pm, ?:{ *:[nxv4i32] }:$zn)
     /* 294994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_S_PSEUDO_S),
     /* 294997 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 294999 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 295001 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 295003 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 295005 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295009 */     GIR_RootConstrainSelectedInstOperands,
     /* 295010 */     // GIR_Coverage, 13624,
     /* 295010 */     GIR_EraseRootFromParent_Done,
     /* 295011 */   // Label 5734: @295011
     /* 295011 */   GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(295070), // Rule ID 13625 //
     /* 295016 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 295019 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_addva),
     /* 295024 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 295027 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 295030 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 295033 */     // MIs[0] tile
     /* 295033 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 295036 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 295041 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295045 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295049 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295053 */     // (intrinsic_void 824:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$pn, PPR3bAny:{ *:[nxv2i1] }:$pm, ZPR64:{ *:[nxv2i64] }:$zn)  =>  (ADDVA_MPPZ_D_PSEUDO_D (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, ?:{ *:[nxv2i1] }:$pn, ?:{ *:[nxv2i1] }:$pm, ?:{ *:[nxv2i64] }:$zn)
     /* 295053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDVA_MPPZ_D_PSEUDO_D),
     /* 295056 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 295058 */     GIR_RootToRootCopy, /*OpIdx*/2, // pn
     /* 295060 */     GIR_RootToRootCopy, /*OpIdx*/3, // pm
     /* 295062 */     GIR_RootToRootCopy, /*OpIdx*/4, // zn
     /* 295064 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295068 */     GIR_RootConstrainSelectedInstOperands,
     /* 295069 */     // GIR_Coverage, 13625,
     /* 295069 */     GIR_EraseRootFromParent_Done,
     /* 295070 */   // Label 5735: @295070
     /* 295070 */   GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(295130), // Rule ID 3492 //
     /* 295075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295078 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
     /* 295083 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295089 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295093 */     // MIs[0] Rn
     /* 295093 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295097 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295101 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295105 */     // MIs[0] prfop
     /* 295105 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295108 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295113 */     // (intrinsic_void 1691:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW8Only:{ *:[nxv4i32] }:$Zm)
     /* 295113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_UXTW_SCALED),
     /* 295116 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295118 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295120 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295122 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295124 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295128 */     GIR_RootConstrainSelectedInstOperands,
     /* 295129 */     // GIR_Coverage, 3492,
     /* 295129 */     GIR_EraseRootFromParent_Done,
     /* 295130 */   // Label 5736: @295130
     /* 295130 */   GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(295190), // Rule ID 3493 //
     /* 295135 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295138 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
     /* 295143 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295149 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295153 */     // MIs[0] Rn
     /* 295153 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295157 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295161 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295165 */     // MIs[0] prfop
     /* 295165 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295168 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295173 */     // (intrinsic_void 1690:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW8Only:{ *:[nxv4i32] }:$Zm)
     /* 295173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_S_SXTW_SCALED),
     /* 295176 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295178 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295180 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295182 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295188 */     GIR_RootConstrainSelectedInstOperands,
     /* 295189 */     // GIR_Coverage, 3493,
     /* 295189 */     GIR_EraseRootFromParent_Done,
     /* 295190 */   // Label 5737: @295190
     /* 295190 */   GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(295250), // Rule ID 3504 //
     /* 295195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_uxtw_index),
     /* 295203 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295213 */     // MIs[0] Rn
     /* 295213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295217 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295221 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295225 */     // MIs[0] prfop
     /* 295225 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295228 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295233 */     // (intrinsic_void 1691:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW8Only:{ *:[nxv2i64] }:$Zm)
     /* 295233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_UXTW_SCALED),
     /* 295236 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295238 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295242 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295248 */     GIR_RootConstrainSelectedInstOperands,
     /* 295249 */     // GIR_Coverage, 3504,
     /* 295249 */     GIR_EraseRootFromParent_Done,
     /* 295250 */   // Label 5738: @295250
     /* 295250 */   GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(295310), // Rule ID 3505 //
     /* 295255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_sxtw_index),
     /* 295263 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295269 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295273 */     // MIs[0] Rn
     /* 295273 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295277 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295281 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295285 */     // MIs[0] prfop
     /* 295285 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295288 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295293 */     // (intrinsic_void 1690:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW8Only:{ *:[nxv2i64] }:$Zm)
     /* 295293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SXTW_SCALED),
     /* 295296 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295298 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295300 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295302 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295304 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295308 */     GIR_RootConstrainSelectedInstOperands,
     /* 295309 */     // GIR_Coverage, 3505,
     /* 295309 */     GIR_EraseRootFromParent_Done,
     /* 295310 */   // Label 5739: @295310
     /* 295310 */   GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(295370), // Rule ID 3506 //
     /* 295315 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295318 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfb_gather_index),
     /* 295323 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295329 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295333 */     // MIs[0] Rn
     /* 295333 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295341 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295345 */     // MIs[0] prfop
     /* 295345 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295348 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295353 */     // (intrinsic_void 1688:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFB_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL8:{ *:[nxv2i64] }:$Zm)
     /* 295353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFB_D_SCALED),
     /* 295356 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295358 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295364 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295368 */     GIR_RootConstrainSelectedInstOperands,
     /* 295369 */     // GIR_Coverage, 3506,
     /* 295369 */     GIR_EraseRootFromParent_Done,
     /* 295370 */   // Label 5740: @295370
     /* 295370 */   GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(295430), // Rule ID 9595 //
     /* 295375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295378 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
     /* 295383 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295386 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295389 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295393 */     // MIs[0] Rn
     /* 295393 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295397 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295401 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295405 */     // MIs[0] prfop
     /* 295405 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295408 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295413 */     // (intrinsic_void 1699:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW16:{ *:[nxv4i32] }:$Zm)
     /* 295413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_UXTW_SCALED),
     /* 295416 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295418 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295420 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295422 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295424 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295428 */     GIR_RootConstrainSelectedInstOperands,
     /* 295429 */     // GIR_Coverage, 9595,
     /* 295429 */     GIR_EraseRootFromParent_Done,
     /* 295430 */   // Label 5741: @295430
     /* 295430 */   GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(295490), // Rule ID 9596 //
     /* 295435 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295438 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
     /* 295443 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295449 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295453 */     // MIs[0] Rn
     /* 295453 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295457 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295461 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295465 */     // MIs[0] prfop
     /* 295465 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295468 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295473 */     // (intrinsic_void 1698:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW16:{ *:[nxv4i32] }:$Zm)
     /* 295473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_S_SXTW_SCALED),
     /* 295476 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295478 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295480 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295482 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295484 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295488 */     GIR_RootConstrainSelectedInstOperands,
     /* 295489 */     // GIR_Coverage, 9596,
     /* 295489 */     GIR_EraseRootFromParent_Done,
     /* 295490 */   // Label 5742: @295490
     /* 295490 */   GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(295550), // Rule ID 9597 //
     /* 295495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295498 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
     /* 295503 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295509 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295513 */     // MIs[0] Rn
     /* 295513 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295517 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295521 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295525 */     // MIs[0] prfop
     /* 295525 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295528 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295533 */     // (intrinsic_void 1703:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW32:{ *:[nxv4i32] }:$Zm)
     /* 295533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_UXTW_SCALED),
     /* 295536 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295538 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295540 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295544 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295548 */     GIR_RootConstrainSelectedInstOperands,
     /* 295549 */     // GIR_Coverage, 9597,
     /* 295549 */     GIR_EraseRootFromParent_Done,
     /* 295550 */   // Label 5743: @295550
     /* 295550 */   GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(295610), // Rule ID 9598 //
     /* 295555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295558 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
     /* 295563 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295569 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295573 */     // MIs[0] Rn
     /* 295573 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295581 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295585 */     // MIs[0] prfop
     /* 295585 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295588 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295593 */     // (intrinsic_void 1702:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW32:{ *:[nxv4i32] }:$Zm)
     /* 295593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_S_SXTW_SCALED),
     /* 295596 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295598 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295602 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295604 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295608 */     GIR_RootConstrainSelectedInstOperands,
     /* 295609 */     // GIR_Coverage, 9598,
     /* 295609 */     GIR_EraseRootFromParent_Done,
     /* 295610 */   // Label 5744: @295610
     /* 295610 */   GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(295670), // Rule ID 9599 //
     /* 295615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295618 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
     /* 295623 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295629 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295633 */     // MIs[0] Rn
     /* 295633 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295641 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295645 */     // MIs[0] prfop
     /* 295645 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295648 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295653 */     // (intrinsic_void 1695:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_S_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtUXTW64:{ *:[nxv4i32] }:$Zm)
     /* 295653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_UXTW_SCALED),
     /* 295656 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295658 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295660 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295664 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295668 */     GIR_RootConstrainSelectedInstOperands,
     /* 295669 */     // GIR_Coverage, 9599,
     /* 295669 */     GIR_EraseRootFromParent_Done,
     /* 295670 */   // Label 5745: @295670
     /* 295670 */   GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(295730), // Rule ID 9600 //
     /* 295675 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295678 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
     /* 295683 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 295686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 295689 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295693 */     // MIs[0] Rn
     /* 295693 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295701 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295705 */     // MIs[0] prfop
     /* 295705 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295708 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295713 */     // (intrinsic_void 1694:{ *:[iPTR] }, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_S_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv4i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR32ExtSXTW64:{ *:[nxv4i32] }:$Zm)
     /* 295713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_S_SXTW_SCALED),
     /* 295716 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295718 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295720 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295722 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295724 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295728 */     GIR_RootConstrainSelectedInstOperands,
     /* 295729 */     // GIR_Coverage, 9600,
     /* 295729 */     GIR_EraseRootFromParent_Done,
     /* 295730 */   // Label 5746: @295730
     /* 295730 */   GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(295790), // Rule ID 9601 //
     /* 295735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295738 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_uxtw_index),
     /* 295743 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295746 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295753 */     // MIs[0] Rn
     /* 295753 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295757 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295761 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295765 */     // MIs[0] prfop
     /* 295765 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295768 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295773 */     // (intrinsic_void 1699:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW16:{ *:[nxv2i64] }:$Zm)
     /* 295773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_UXTW_SCALED),
     /* 295776 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295778 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295782 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295784 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295788 */     GIR_RootConstrainSelectedInstOperands,
     /* 295789 */     // GIR_Coverage, 9601,
     /* 295789 */     GIR_EraseRootFromParent_Done,
     /* 295790 */   // Label 5747: @295790
     /* 295790 */   GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(295850), // Rule ID 9602 //
     /* 295795 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295798 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_sxtw_index),
     /* 295803 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295809 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295813 */     // MIs[0] Rn
     /* 295813 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295821 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295825 */     // MIs[0] prfop
     /* 295825 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295828 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295833 */     // (intrinsic_void 1698:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW16:{ *:[nxv2i64] }:$Zm)
     /* 295833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SXTW_SCALED),
     /* 295836 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295838 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295840 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295842 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295848 */     GIR_RootConstrainSelectedInstOperands,
     /* 295849 */     // GIR_Coverage, 9602,
     /* 295849 */     GIR_EraseRootFromParent_Done,
     /* 295850 */   // Label 5748: @295850
     /* 295850 */   GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(295910), // Rule ID 9603 //
     /* 295855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_uxtw_index),
     /* 295863 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295869 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295873 */     // MIs[0] Rn
     /* 295873 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295881 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295885 */     // MIs[0] prfop
     /* 295885 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295888 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295893 */     // (intrinsic_void 1703:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW32:{ *:[nxv2i64] }:$Zm)
     /* 295893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_UXTW_SCALED),
     /* 295896 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295902 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295904 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295908 */     GIR_RootConstrainSelectedInstOperands,
     /* 295909 */     // GIR_Coverage, 9603,
     /* 295909 */     GIR_EraseRootFromParent_Done,
     /* 295910 */   // Label 5749: @295910
     /* 295910 */   GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(295970), // Rule ID 9604 //
     /* 295915 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295918 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_sxtw_index),
     /* 295923 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295929 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295933 */     // MIs[0] Rn
     /* 295933 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 295941 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 295945 */     // MIs[0] prfop
     /* 295945 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 295948 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 295953 */     // (intrinsic_void 1702:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW32:{ *:[nxv2i64] }:$Zm)
     /* 295953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SXTW_SCALED),
     /* 295956 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 295958 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 295960 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 295962 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 295964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 295968 */     GIR_RootConstrainSelectedInstOperands,
     /* 295969 */     // GIR_Coverage, 9604,
     /* 295969 */     GIR_EraseRootFromParent_Done,
     /* 295970 */   // Label 5750: @295970
     /* 295970 */   GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(296030), // Rule ID 9605 //
     /* 295975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 295978 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_uxtw_index),
     /* 295983 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 295986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 295989 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 295993 */     // MIs[0] Rn
     /* 295993 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 295997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 296001 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 296005 */     // MIs[0] prfop
     /* 296005 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 296008 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 296013 */     // (intrinsic_void 1695:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_UXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtUXTW64:{ *:[nxv2i64] }:$Zm)
     /* 296013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_UXTW_SCALED),
     /* 296016 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 296018 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 296020 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296022 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 296024 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296028 */     GIR_RootConstrainSelectedInstOperands,
     /* 296029 */     // GIR_Coverage, 9605,
     /* 296029 */     GIR_EraseRootFromParent_Done,
     /* 296030 */   // Label 5751: @296030
     /* 296030 */   GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(296090), // Rule ID 9606 //
     /* 296035 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 296038 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_sxtw_index),
     /* 296043 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 296046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 296049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 296053 */     // MIs[0] Rn
     /* 296053 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 296057 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 296061 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 296065 */     // MIs[0] prfop
     /* 296065 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 296068 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 296073 */     // (intrinsic_void 1694:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_SXTW_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtSXTW64:{ *:[nxv2i64] }:$Zm)
     /* 296073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SXTW_SCALED),
     /* 296076 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 296078 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 296080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296082 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 296084 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296088 */     GIR_RootConstrainSelectedInstOperands,
     /* 296089 */     // GIR_Coverage, 9606,
     /* 296089 */     GIR_EraseRootFromParent_Done,
     /* 296090 */   // Label 5752: @296090
     /* 296090 */   GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(296150), // Rule ID 9607 //
     /* 296095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 296098 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfh_gather_index),
     /* 296103 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 296106 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 296109 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 296113 */     // MIs[0] Rn
     /* 296113 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 296117 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 296121 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 296125 */     // MIs[0] prfop
     /* 296125 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 296128 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 296133 */     // (intrinsic_void 1696:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFH_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL16:{ *:[nxv2i64] }:$Zm)
     /* 296133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFH_D_SCALED),
     /* 296136 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 296138 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 296140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296142 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 296144 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296148 */     GIR_RootConstrainSelectedInstOperands,
     /* 296149 */     // GIR_Coverage, 9607,
     /* 296149 */     GIR_EraseRootFromParent_Done,
     /* 296150 */   // Label 5753: @296150
     /* 296150 */   GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(296210), // Rule ID 9608 //
     /* 296155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 296158 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfw_gather_index),
     /* 296163 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 296166 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 296169 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 296173 */     // MIs[0] Rn
     /* 296173 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 296177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 296181 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 296185 */     // MIs[0] prfop
     /* 296185 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 296188 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 296193 */     // (intrinsic_void 1700:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFW_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL32:{ *:[nxv2i64] }:$Zm)
     /* 296193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFW_D_SCALED),
     /* 296196 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 296198 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 296200 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296202 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 296204 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296208 */     GIR_RootConstrainSelectedInstOperands,
     /* 296209 */     // GIR_Coverage, 9608,
     /* 296209 */     GIR_EraseRootFromParent_Done,
     /* 296210 */   // Label 5754: @296210
     /* 296210 */   GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(296270), // Rule ID 9609 //
     /* 296215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE),
     /* 296218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sve_prfd_gather_index),
     /* 296223 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 296226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 296229 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 296233 */     // MIs[0] Rn
     /* 296233 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/64,
     /* 296237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 296241 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 296245 */     // MIs[0] prfop
     /* 296245 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 296248 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_prfop),
     /* 296253 */     // (intrinsic_void 1692:{ *:[iPTR] }, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm, (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop)  =>  (PRFD_D_SCALED (timm:{ *:[i32] })<<P:Predicate_sve_prfop>>:$prfop, PPR3bAny:{ *:[nxv2i1] }:$Pg, GPR64sp:{ *:[i64] }:$Rn, ZPR64ExtLSL64:{ *:[nxv2i64] }:$Zm)
     /* 296253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFD_D_SCALED),
     /* 296256 */     GIR_RootToRootCopy, /*OpIdx*/4, // prfop
     /* 296258 */     GIR_RootToRootCopy, /*OpIdx*/1, // Pg
     /* 296260 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 296262 */     GIR_RootToRootCopy, /*OpIdx*/3, // Zm
     /* 296264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296268 */     GIR_RootConstrainSelectedInstOperands,
     /* 296269 */     // GIR_Coverage, 9609,
     /* 296269 */     GIR_EraseRootFromParent_Done,
     /* 296270 */   // Label 5755: @296270
     /* 296270 */   GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(296328), // Rule ID 2405 //
     /* 296275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalb),
     /* 296283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 296286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 296289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296307 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296311 */     // (intrinsic_w_chain:{ *:[v8f16] } 644:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALBv16i8_v8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALBv16i8_v8f16),
     /* 296314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296316 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296318 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296320 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296326 */     GIR_RootConstrainSelectedInstOperands,
     /* 296327 */     // GIR_Coverage, 2405,
     /* 296327 */     GIR_EraseRootFromParent_Done,
     /* 296328 */   // Label 5756: @296328
     /* 296328 */   GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(296386), // Rule ID 2406 //
     /* 296333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalt),
     /* 296341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 296344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 296347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296350 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296353 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296357 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296361 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296365 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296369 */     // (intrinsic_w_chain:{ *:[v8f16] } 654:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALTv16i8_v8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALTv16i8_v8f16),
     /* 296372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296374 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296376 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296378 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296380 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296384 */     GIR_RootConstrainSelectedInstOperands,
     /* 296385 */     // GIR_Coverage, 2406,
     /* 296385 */     GIR_EraseRootFromParent_Done,
     /* 296386 */   // Label 5757: @296386
     /* 296386 */   GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(296444), // Rule ID 2407 //
     /* 296391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296394 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbb),
     /* 296399 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 296402 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 296405 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296408 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296411 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296423 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296427 */     // (intrinsic_w_chain:{ *:[v4f32] } 646:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLBBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBBv4f32),
     /* 296430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296432 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296436 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296438 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296442 */     GIR_RootConstrainSelectedInstOperands,
     /* 296443 */     // GIR_Coverage, 2407,
     /* 296443 */     GIR_EraseRootFromParent_Done,
     /* 296444 */   // Label 5758: @296444
     /* 296444 */   GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(296502), // Rule ID 2408 //
     /* 296449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296452 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbt),
     /* 296457 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 296460 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 296463 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296466 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296481 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296485 */     // (intrinsic_w_chain:{ *:[v4f32] } 648:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLBTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296485 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBTv4f32),
     /* 296488 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296490 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296492 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296494 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296500 */     GIR_RootConstrainSelectedInstOperands,
     /* 296501 */     // GIR_Coverage, 2408,
     /* 296501 */     GIR_EraseRootFromParent_Done,
     /* 296502 */   // Label 5759: @296502
     /* 296502 */   GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(296560), // Rule ID 2409 //
     /* 296507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltb),
     /* 296515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 296518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 296521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296524 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296527 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296535 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296539 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296543 */     // (intrinsic_w_chain:{ *:[v4f32] } 650:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLTBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTBv4f32),
     /* 296546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296550 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296552 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296554 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296558 */     GIR_RootConstrainSelectedInstOperands,
     /* 296559 */     // GIR_Coverage, 2409,
     /* 296559 */     GIR_EraseRootFromParent_Done,
     /* 296560 */   // Label 5760: @296560
     /* 296560 */   GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(296618), // Rule ID 2410 //
     /* 296565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 296568 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltt),
     /* 296573 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 296576 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 296579 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296582 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296597 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296601 */     // (intrinsic_w_chain:{ *:[v4f32] } 652:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FMLALLTTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTTv4f32),
     /* 296604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296606 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296608 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296610 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296612 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296616 */     GIR_RootConstrainSelectedInstOperands,
     /* 296617 */     // GIR_Coverage, 2410,
     /* 296617 */     GIR_EraseRootFromParent_Done,
     /* 296618 */   // Label 5761: @296618
     /* 296618 */   GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(296676), // Rule ID 2411 //
     /* 296623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 296626 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2),
     /* 296631 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 296634 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 296637 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 296640 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 296643 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296647 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296651 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296655 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296659 */     // (intrinsic_w_chain:{ *:[v4f16] } 640:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (FDOTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 296659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv4f16),
     /* 296662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296664 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296668 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296670 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296674 */     GIR_RootConstrainSelectedInstOperands,
     /* 296675 */     // GIR_Coverage, 2411,
     /* 296675 */     GIR_EraseRootFromParent_Done,
     /* 296676 */   // Label 5762: @296676
     /* 296676 */   GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(296734), // Rule ID 2412 //
     /* 296681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 296684 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2),
     /* 296689 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 296692 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 296695 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296698 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296709 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296713 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296717 */     // (intrinsic_w_chain:{ *:[v8f16] } 640:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FDOTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv8f16),
     /* 296720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296722 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296724 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296726 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296728 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296732 */     GIR_RootConstrainSelectedInstOperands,
     /* 296733 */     // GIR_Coverage, 2412,
     /* 296733 */     GIR_EraseRootFromParent_Done,
     /* 296734 */   // Label 5763: @296734
     /* 296734 */   GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(296792), // Rule ID 2413 //
     /* 296739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 296742 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4),
     /* 296747 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 296750 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 296753 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 296756 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
     /* 296759 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296767 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296771 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 296775 */     // (intrinsic_w_chain:{ *:[v2f32] } 642:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (FDOTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 296775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv2f32),
     /* 296778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296780 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296782 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296784 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296790 */     GIR_RootConstrainSelectedInstOperands,
     /* 296791 */     // GIR_Coverage, 2413,
     /* 296791 */     GIR_EraseRootFromParent_Done,
     /* 296792 */   // Label 5764: @296792
     /* 296792 */   GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(296850), // Rule ID 2414 //
     /* 296797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 296800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4),
     /* 296805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 296808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 296811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 296814 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 296817 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296821 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296825 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296829 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296833 */     // (intrinsic_w_chain:{ *:[v4f32] } 642:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (FDOTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 296833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTv4f32),
     /* 296836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296838 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 296840 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296842 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296844 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296848 */     GIR_RootConstrainSelectedInstOperands,
     /* 296849 */     // GIR_Coverage, 2414,
     /* 296849 */     GIR_EraseRootFromParent_Done,
     /* 296850 */   // Label 5765: @296850
     /* 296850 */   GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(296908), // Rule ID 2521 //
     /* 296855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8),
     /* 296858 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fcvtn2),
     /* 296863 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 296866 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 296869 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 296872 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 296875 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296887 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 296891 */     // (intrinsic_w_chain:{ *:[v16i8] } 639:{ *:[iPTR] }, V128:{ *:[v16i8] }:$_Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCVTN_F322v16f8:{ *:[v16i8] } V128:{ *:[v16i8] }:$_Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 296891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTN_F322v16f8),
     /* 296894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 296896 */     GIR_RootToRootCopy, /*OpIdx*/2, // _Rd
     /* 296898 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 296900 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 296902 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296906 */     GIR_RootConstrainSelectedInstOperands,
     /* 296907 */     // GIR_Coverage, 2521,
     /* 296907 */     GIR_EraseRootFromParent_Done,
     /* 296908 */   // Label 5766: @296908
     /* 296908 */   GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(296964), // Rule ID 14181 //
     /* 296913 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stlxp),
     /* 296918 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 296921 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 296924 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 296927 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 296931 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 296935 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 296939 */     // MIs[0] addr
     /* 296939 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
     /* 296943 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 296947 */     // (intrinsic_w_chain:{ *:[i32] } 1261:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)  =>  (STLXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
     /* 296947 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STLXPX),
     /* 296950 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 296952 */     GIR_RootToRootCopy, /*OpIdx*/2, // lo
     /* 296954 */     GIR_RootToRootCopy, /*OpIdx*/3, // hi
     /* 296956 */     GIR_RootToRootCopy, /*OpIdx*/4, // addr
     /* 296958 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 296962 */     GIR_RootConstrainSelectedInstOperands,
     /* 296963 */     // GIR_Coverage, 14181,
     /* 296963 */     GIR_EraseRootFromParent_Done,
     /* 296964 */   // Label 5767: @296964
     /* 296964 */   GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(297020), // Rule ID 14182 //
     /* 296969 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_stxp),
     /* 296974 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 296977 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 296980 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 296983 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 296987 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 296991 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 296995 */     // MIs[0] addr
     /* 296995 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/4, /*SizeInBits*/64,
     /* 296999 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 297003 */     // (intrinsic_w_chain:{ *:[i32] } 1263:{ *:[iPTR] }, GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)  =>  (STXPX:{ *:[i32] } GPR64:{ *:[i64] }:$lo, GPR64:{ *:[i64] }:$hi, GPR64:{ *:[i64] }:$addr)
     /* 297003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::STXPX),
     /* 297006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Ws]
     /* 297008 */     GIR_RootToRootCopy, /*OpIdx*/2, // lo
     /* 297010 */     GIR_RootToRootCopy, /*OpIdx*/3, // hi
     /* 297012 */     GIR_RootToRootCopy, /*OpIdx*/4, // addr
     /* 297014 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297018 */     GIR_RootConstrainSelectedInstOperands,
     /* 297019 */     // GIR_Coverage, 14182,
     /* 297019 */     GIR_EraseRootFromParent_Done,
     /* 297020 */   // Label 5768: @297020
     /* 297020 */   GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(297066), // Rule ID 3539 //
     /* 297025 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT2),
     /* 297028 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot),
     /* 297033 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 297036 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 297039 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297042 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297049 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1544:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FDOT_ZZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_BtoH),
     /* 297052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297054 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297056 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297058 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297060 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297064 */     GIR_RootConstrainSelectedInstOperands,
     /* 297065 */     // GIR_Coverage, 3539,
     /* 297065 */     GIR_EraseRootFromParent_Done,
     /* 297066 */   // Label 5769: @297066
     /* 297066 */   GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(297112), // Rule ID 3663 //
     /* 297071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297074 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalb),
     /* 297079 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 297082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 297085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297088 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297091 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297095 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1546:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALB_ZZZ:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZ),
     /* 297098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297100 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297102 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297104 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297106 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297110 */     GIR_RootConstrainSelectedInstOperands,
     /* 297111 */     // GIR_Coverage, 3663,
     /* 297111 */     GIR_EraseRootFromParent_Done,
     /* 297112 */   // Label 5770: @297112
     /* 297112 */   GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(297158), // Rule ID 3665 //
     /* 297117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF8F32MM_HasSVE2),
     /* 297120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmmla),
     /* 297125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297134 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297137 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297141 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1558:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$acc, nxv16i8:{ *:[nxv16i8] }:$zn, nxv16i8:{ *:[nxv16i8] }:$zm)  =>  (FMMLA_ZZZ_BtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$acc, ?:{ *:[nxv16i8] }:$zn, ?:{ *:[nxv16i8] }:$zm)
     /* 297141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_BtoS),
     /* 297144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297146 */     GIR_RootToRootCopy, /*OpIdx*/2, // acc
     /* 297148 */     GIR_RootToRootCopy, /*OpIdx*/3, // zn
     /* 297150 */     GIR_RootToRootCopy, /*OpIdx*/4, // zm
     /* 297152 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297156 */     GIR_RootConstrainSelectedInstOperands,
     /* 297157 */     // GIR_Coverage, 3665,
     /* 297157 */     GIR_EraseRootFromParent_Done,
     /* 297158 */   // Label 5771: @297158
     /* 297158 */   GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(297204), // Rule ID 13603 //
     /* 297163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalt),
     /* 297171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 297174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 297177 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297180 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297183 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297187 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1556:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALT_ZZZ:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZ),
     /* 297190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297194 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297196 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297198 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297202 */     GIR_RootConstrainSelectedInstOperands,
     /* 297203 */     // GIR_Coverage, 13603,
     /* 297203 */     GIR_EraseRootFromParent_Done,
     /* 297204 */   // Label 5772: @297204
     /* 297204 */   GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(297250), // Rule ID 13607 //
     /* 297209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297212 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbb),
     /* 297217 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297220 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297223 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297226 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297233 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1548:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLBB_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBB_ZZZ),
     /* 297236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297242 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297244 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297248 */     GIR_RootConstrainSelectedInstOperands,
     /* 297249 */     // GIR_Coverage, 13607,
     /* 297249 */     GIR_EraseRootFromParent_Done,
     /* 297250 */   // Label 5773: @297250
     /* 297250 */   GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(297296), // Rule ID 13608 //
     /* 297255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297258 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbt),
     /* 297263 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297266 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297272 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297275 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297279 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1550:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLBT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBT_ZZZ),
     /* 297282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297284 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297286 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297288 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297290 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297294 */     GIR_RootConstrainSelectedInstOperands,
     /* 297295 */     // GIR_Coverage, 13608,
     /* 297295 */     GIR_EraseRootFromParent_Done,
     /* 297296 */   // Label 5774: @297296
     /* 297296 */   GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(297342), // Rule ID 13609 //
     /* 297301 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297304 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltb),
     /* 297309 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297312 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297315 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297318 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297321 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297325 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1552:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLTB_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTB_ZZZ),
     /* 297328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297330 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297334 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297336 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297340 */     GIR_RootConstrainSelectedInstOperands,
     /* 297341 */     // GIR_Coverage, 13609,
     /* 297341 */     GIR_EraseRootFromParent_Done,
     /* 297342 */   // Label 5775: @297342
     /* 297342 */   GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(297388), // Rule ID 13610 //
     /* 297347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 297350 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltt),
     /* 297355 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297358 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297361 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297364 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297367 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297371 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1554:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FMLALLTT_ZZZ:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTT_ZZZ),
     /* 297374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297376 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297378 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297380 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297382 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297386 */     GIR_RootConstrainSelectedInstOperands,
     /* 297387 */     // GIR_Coverage, 13610,
     /* 297387 */     GIR_EraseRootFromParent_Done,
     /* 297388 */   // Label 5776: @297388
     /* 297388 */   GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(297434), // Rule ID 13611 //
     /* 297393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasF8F16MM_HasSVE2),
     /* 297396 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmmla),
     /* 297401 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 297404 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 297407 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297410 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297413 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297417 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1558:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$acc, nxv16i8:{ *:[nxv16i8] }:$zn, nxv16i8:{ *:[nxv16i8] }:$zm)  =>  (FMMLA_ZZZ_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$acc, ?:{ *:[nxv16i8] }:$zn, ?:{ *:[nxv16i8] }:$zm)
     /* 297417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMMLA_ZZZ_BtoH),
     /* 297420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297422 */     GIR_RootToRootCopy, /*OpIdx*/2, // acc
     /* 297424 */     GIR_RootToRootCopy, /*OpIdx*/3, // zn
     /* 297426 */     GIR_RootToRootCopy, /*OpIdx*/4, // zm
     /* 297428 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297432 */     GIR_RootConstrainSelectedInstOperands,
     /* 297433 */     // GIR_Coverage, 13611,
     /* 297433 */     GIR_EraseRootFromParent_Done,
     /* 297434 */   // Label 5777: @297434
     /* 297434 */   GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(297480), // Rule ID 13612 //
     /* 297439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT4),
     /* 297442 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot),
     /* 297447 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 297450 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 297453 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 297456 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 297459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 297463 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1544:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (FDOT_ZZZ_BtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 297463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZ_BtoS),
     /* 297466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 297468 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 297470 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 297472 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 297474 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297478 */     GIR_RootConstrainSelectedInstOperands,
     /* 297479 */     // GIR_Coverage, 13612,
     /* 297479 */     GIR_EraseRootFromParent_Done,
     /* 297480 */   // Label 5778: @297480
     /* 297480 */   GIM_Reject,
     /* 297481 */ // Label 5729: @297481
     /* 297481 */ GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(300474),
     /* 297486 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
     /* 297489 */   GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(297557), // Rule ID 2552 //
     /* 297494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 297497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalb_lane),
     /* 297502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 297505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 297508 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297511 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297518 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297522 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297526 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 297530 */     // MIs[0] Idx
     /* 297530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297533 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 297538 */     // (intrinsic_w_chain:{ *:[v8f16] } 645:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALBlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALBlanev8f16),
     /* 297541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297543 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297545 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297547 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297549 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297551 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297555 */     GIR_RootConstrainSelectedInstOperands,
     /* 297556 */     // GIR_Coverage, 2552,
     /* 297556 */     GIR_EraseRootFromParent_Done,
     /* 297557 */   // Label 5780: @297557
     /* 297557 */   GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(297625), // Rule ID 2553 //
     /* 297562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 297565 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbb_lane),
     /* 297570 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 297573 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 297576 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297579 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297582 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297586 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297590 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297594 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 297598 */     // MIs[0] Idx
     /* 297598 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297601 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 297606 */     // (intrinsic_w_chain:{ *:[v4f32] } 647:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLBBlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBBlanev4f32),
     /* 297609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297611 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297613 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297615 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297617 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297619 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297623 */     GIR_RootConstrainSelectedInstOperands,
     /* 297624 */     // GIR_Coverage, 2553,
     /* 297624 */     GIR_EraseRootFromParent_Done,
     /* 297625 */   // Label 5781: @297625
     /* 297625 */   GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(297693), // Rule ID 2554 //
     /* 297630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 297633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4_lane),
     /* 297638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
     /* 297641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 297644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 297647 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297650 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297654 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297658 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297662 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297666 */     // MIs[0] Idx
     /* 297666 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297669 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 297674 */     // (intrinsic_w_chain:{ *:[v2f32] } 643:{ *:[iPTR] }, V64:{ *:[v2f32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Idx)  =>  (FDOTlanev2f32:{ *:[v2f32] } ?:{ *:[v2f32] }:$Rd, ?:{ *:[v8i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev2f32),
     /* 297677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297679 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297681 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297683 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297685 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297687 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297691 */     GIR_RootConstrainSelectedInstOperands,
     /* 297692 */     // GIR_Coverage, 2554,
     /* 297692 */     GIR_EraseRootFromParent_Done,
     /* 297693 */   // Label 5782: @297693
     /* 297693 */   GIM_Try, /*On fail goto*//*Label 5783*/ GIMT_Encode4(297761), // Rule ID 2555 //
     /* 297698 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT4),
     /* 297701 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot4_lane),
     /* 297706 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 297709 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 297712 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297715 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297722 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297726 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297730 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297734 */     // MIs[0] Idx
     /* 297734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 297742 */     // (intrinsic_w_chain:{ *:[v4f32] } 643:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$Idx)  =>  (FDOTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev4f32),
     /* 297745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297749 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297751 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297753 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297755 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297759 */     GIR_RootConstrainSelectedInstOperands,
     /* 297760 */     // GIR_Coverage, 2555,
     /* 297760 */     GIR_EraseRootFromParent_Done,
     /* 297761 */   // Label 5783: @297761
     /* 297761 */   GIM_Try, /*On fail goto*//*Label 5784*/ GIMT_Encode4(297829), // Rule ID 2556 //
     /* 297766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 297769 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2_lane),
     /* 297774 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
     /* 297777 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 297780 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 297783 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297790 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297794 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 297798 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 297802 */     // MIs[0] Idx
     /* 297802 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297805 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 297810 */     // (intrinsic_w_chain:{ *:[v4f16] } 641:{ *:[iPTR] }, V64:{ *:[v4f16] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128_lo:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Idx)  =>  (FDOTlanev4f16:{ *:[v4f16] } ?:{ *:[v4f16] }:$Rd, ?:{ *:[v8i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev4f16),
     /* 297813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297819 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297821 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297823 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297827 */     GIR_RootConstrainSelectedInstOperands,
     /* 297828 */     // GIR_Coverage, 2556,
     /* 297828 */     GIR_EraseRootFromParent_Done,
     /* 297829 */   // Label 5784: @297829
     /* 297829 */   GIM_Try, /*On fail goto*//*Label 5785*/ GIMT_Encode4(297897), // Rule ID 2557 //
     /* 297834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8DOT2),
     /* 297837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fdot2_lane),
     /* 297842 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 297845 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 297848 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297851 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297862 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297866 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 297870 */     // MIs[0] Idx
     /* 297870 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297873 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 297878 */     // (intrinsic_w_chain:{ *:[v8f16] } 641:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_lo:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$Idx)  =>  (FDOTlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOTlanev8f16),
     /* 297881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297883 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297885 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297887 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297889 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297895 */     GIR_RootConstrainSelectedInstOperands,
     /* 297896 */     // GIR_Coverage, 2557,
     /* 297896 */     GIR_EraseRootFromParent_Done,
     /* 297897 */   // Label 5785: @297897
     /* 297897 */   GIM_Try, /*On fail goto*//*Label 5786*/ GIMT_Encode4(297965), // Rule ID 7635 //
     /* 297902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 297905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalt_lane),
     /* 297910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 297913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 297916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297919 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297926 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297930 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297934 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 297938 */     // MIs[0] Idx
     /* 297938 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 297941 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 297946 */     // (intrinsic_w_chain:{ *:[v8f16] } 655:{ *:[iPTR] }, V128:{ *:[v8f16] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALTlanev8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 297946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALTlanev8f16),
     /* 297949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 297951 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 297953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 297955 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 297957 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 297959 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 297963 */     GIR_RootConstrainSelectedInstOperands,
     /* 297964 */     // GIR_Coverage, 7635,
     /* 297964 */     GIR_EraseRootFromParent_Done,
     /* 297965 */   // Label 5786: @297965
     /* 297965 */   GIM_Try, /*On fail goto*//*Label 5787*/ GIMT_Encode4(298033), // Rule ID 7636 //
     /* 297970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 297973 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlallbt_lane),
     /* 297978 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 297981 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 297984 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 297987 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 297990 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297994 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 297998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298002 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 298006 */     // MIs[0] Idx
     /* 298006 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 298009 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 298014 */     // (intrinsic_w_chain:{ *:[v4f32] } 649:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLBTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 298014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBTlanev4f32),
     /* 298017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 298019 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 298021 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 298023 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 298025 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 298027 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298031 */     GIR_RootConstrainSelectedInstOperands,
     /* 298032 */     // GIR_Coverage, 7636,
     /* 298032 */     GIR_EraseRootFromParent_Done,
     /* 298033 */   // Label 5787: @298033
     /* 298033 */   GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(298101), // Rule ID 7637 //
     /* 298038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 298041 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltb_lane),
     /* 298046 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 298049 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 298052 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 298055 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 298058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298062 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298066 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298070 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 298074 */     // MIs[0] Idx
     /* 298074 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 298077 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 298082 */     // (intrinsic_w_chain:{ *:[v4f32] } 651:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLTBlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 298082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTBlanev4f32),
     /* 298085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 298087 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 298089 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 298091 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 298093 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 298095 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298099 */     GIR_RootConstrainSelectedInstOperands,
     /* 298100 */     // GIR_Coverage, 7637,
     /* 298100 */     GIR_EraseRootFromParent_Done,
     /* 298101 */   // Label 5788: @298101
     /* 298101 */   GIM_Try, /*On fail goto*//*Label 5789*/ GIMT_Encode4(298169), // Rule ID 7638 //
     /* 298106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8FMA),
     /* 298109 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_fp8_fmlalltt_lane),
     /* 298114 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 298117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 298120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 298123 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 298126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298134 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 298138 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AArch64::FPR128_0to7RegClassID),
     /* 298142 */     // MIs[0] Idx
     /* 298142 */     GIM_CheckIsImm, /*MI*/0, /*Op*/5,
     /* 298145 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB32b_timm),
     /* 298150 */     // (intrinsic_w_chain:{ *:[v4f32] } 653:{ *:[iPTR] }, V128:{ *:[v4f32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128_0to7:{ *:[v16i8] }:$Rm, (timm:{ *:[i32] })<<P:Predicate_VectorIndexB32b_timm>>:$Idx)  =>  (FMLALLTTlanev4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rd, ?:{ *:[v16i8] }:$Rn, ?:{ *:[v16i8] }:$Rm, ?:{ *:[i32] }:$Idx)
     /* 298150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTTlanev4f32),
     /* 298153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 298155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 298157 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 298159 */     GIR_RootToRootCopy, /*OpIdx*/4, // Rm
     /* 298161 */     GIR_RootToRootCopy, /*OpIdx*/5, // Idx
     /* 298163 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298167 */     GIR_RootConstrainSelectedInstOperands,
     /* 298168 */     // GIR_Coverage, 7638,
     /* 298168 */     GIR_EraseRootFromParent_Done,
     /* 298169 */   // Label 5789: @298169
     /* 298169 */   GIM_Try, /*On fail goto*//*Label 5790*/ GIMT_Encode4(298229), // Rule ID 3676 //
     /* 298174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298177 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 298182 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 298185 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 298188 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 298191 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 298194 */     // MIs[0] tile
     /* 298194 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298197 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298202 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298206 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298210 */     // (intrinsic_void 951:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 298210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_S_PSEUDO),
     /* 298213 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298217 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298219 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298221 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298227 */     GIR_RootConstrainSelectedInstOperands,
     /* 298228 */     // GIR_Coverage, 3676,
     /* 298228 */     GIR_EraseRootFromParent_Done,
     /* 298229 */   // Label 5790: @298229
     /* 298229 */   GIM_Try, /*On fail goto*//*Label 5791*/ GIMT_Encode4(298289), // Rule ID 3677 //
     /* 298234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F32),
     /* 298237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmopa_za32),
     /* 298242 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 298245 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 298248 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 298251 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 298254 */     // MIs[0] tile
     /* 298254 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298257 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298266 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298270 */     // (intrinsic_void 903:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOPA_MPPZZ_BtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 298270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_BtoS_PSEUDO),
     /* 298273 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298279 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298281 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298283 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298287 */     GIR_RootConstrainSelectedInstOperands,
     /* 298288 */     // GIR_Coverage, 3677,
     /* 298288 */     GIR_EraseRootFromParent_Done,
     /* 298289 */   // Label 5791: @298289
     /* 298289 */   GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(298349), // Rule ID 3678 //
     /* 298294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
     /* 298297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 298302 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 298305 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 298308 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 298311 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 298314 */     // MIs[0] tile
     /* 298314 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298317 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 298322 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298326 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298330 */     // (intrinsic_void 951:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 298330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_D_PSEUDO),
     /* 298333 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298335 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298337 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298339 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298341 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298343 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298347 */     GIR_RootConstrainSelectedInstOperands,
     /* 298348 */     // GIR_Coverage, 3678,
     /* 298348 */     GIR_EraseRootFromParent_Done,
     /* 298349 */   // Label 5792: @298349
     /* 298349 */   GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(298409), // Rule ID 3679 //
     /* 298354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF8F16),
     /* 298357 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_fp8_fmopa_za16),
     /* 298362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 298365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 298368 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 298371 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 298374 */     // MIs[0] tile
     /* 298374 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298377 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 298382 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298386 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298390 */     // (intrinsic_void 902:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (FMOPA_MPPZZ_BtoH_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 298390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_BtoH_PSEUDO),
     /* 298393 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298395 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298397 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298399 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298401 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298403 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298407 */     GIR_RootConstrainSelectedInstOperands,
     /* 298408 */     // GIR_Coverage, 3679,
     /* 298408 */     GIR_EraseRootFromParent_Done,
     /* 298409 */   // Label 5793: @298409
     /* 298409 */   GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(298469), // Rule ID 3680 //
     /* 298414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16),
     /* 298417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa),
     /* 298422 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 298425 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 298428 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 298431 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 298434 */     // MIs[0] tile
     /* 298434 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298437 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 298442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298450 */     // (intrinsic_void 951:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPA_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 298450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPA_MPPZZ_H_PSEUDO),
     /* 298453 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298457 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298459 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298461 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298467 */     GIR_RootConstrainSelectedInstOperands,
     /* 298468 */     // GIR_Coverage, 3680,
     /* 298468 */     GIR_EraseRootFromParent_Done,
     /* 298469 */   // Label 5794: @298469
     /* 298469 */   GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(298529), // Rule ID 3681 //
     /* 298474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
     /* 298482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 298485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 298488 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 298491 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 298494 */     // MIs[0] tile
     /* 298494 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298497 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298506 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298510 */     // (intrinsic_void 1054:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 298510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_S_PSEUDO),
     /* 298513 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298515 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298517 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298519 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298521 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298523 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298527 */     GIR_RootConstrainSelectedInstOperands,
     /* 298528 */     // GIR_Coverage, 3681,
     /* 298528 */     GIR_EraseRootFromParent_Done,
     /* 298529 */   // Label 5795: @298529
     /* 298529 */   GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(298589), // Rule ID 3682 //
     /* 298534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 298537 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_wide),
     /* 298542 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 298545 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 298548 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 298551 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 298554 */     // MIs[0] tile
     /* 298554 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298557 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 298562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298566 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298570 */     // (intrinsic_void 1054:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 298570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_D_PSEUDO),
     /* 298573 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298575 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298577 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298579 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298581 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298583 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298587 */     GIR_RootConstrainSelectedInstOperands,
     /* 298588 */     // GIR_Coverage, 3682,
     /* 298588 */     GIR_EraseRootFromParent_Done,
     /* 298589 */   // Label 5796: @298589
     /* 298589 */   GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(298649), // Rule ID 3683 //
     /* 298594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mopa_wide),
     /* 298602 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 298605 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 298608 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 298611 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 298614 */     // MIs[0] tile
     /* 298614 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298617 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298622 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298626 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298630 */     // (intrinsic_void 953:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPAL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 298630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPAL_MPPZZ_PSEUDO),
     /* 298633 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298637 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298639 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298641 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298643 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298647 */     GIR_RootConstrainSelectedInstOperands,
     /* 298648 */     // GIR_Coverage, 3683,
     /* 298648 */     GIR_EraseRootFromParent_Done,
     /* 298649 */   // Label 5797: @298649
     /* 298649 */   GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(298709), // Rule ID 3777 //
     /* 298654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 298657 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smopa_za32),
     /* 298662 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 298665 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 298668 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 298671 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 298674 */     // MIs[0] tile
     /* 298674 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298677 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298682 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298686 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298690 */     // (intrinsic_void 1055:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 298690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPA_MPPZZ_HtoS_PSEUDO),
     /* 298693 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298697 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298699 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298701 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298703 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298707 */     GIR_RootConstrainSelectedInstOperands,
     /* 298708 */     // GIR_Coverage, 3777,
     /* 298708 */     GIR_EraseRootFromParent_Done,
     /* 298709 */   // Label 5798: @298709
     /* 298709 */   GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(298769), // Rule ID 3778 //
     /* 298714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 298717 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmopa_za32),
     /* 298722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 298725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 298728 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 298731 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 298734 */     // MIs[0] tile
     /* 298734 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298737 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298742 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298746 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298750 */     // (intrinsic_void 825:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm)  =>  (BMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
     /* 298750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPA_MPPZZ_S_PSEUDO),
     /* 298753 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298757 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298759 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298761 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298763 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298767 */     GIR_RootConstrainSelectedInstOperands,
     /* 298768 */     // GIR_Coverage, 3778,
     /* 298768 */     GIR_EraseRootFromParent_Done,
     /* 298769 */   // Label 5799: @298769
     /* 298769 */   GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(298829), // Rule ID 13626 //
     /* 298774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 298782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 298785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 298788 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 298791 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 298794 */     // MIs[0] tile
     /* 298794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298802 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298806 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298810 */     // (intrinsic_void 954:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4f32:{ *:[nxv4f32] }:$Zn, nxv4f32:{ *:[nxv4f32] }:$Zm)  =>  (FMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4f32] }:$Zn, ?:{ *:[nxv4f32] }:$Zm)
     /* 298810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_S_PSEUDO),
     /* 298813 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298817 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298819 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298821 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298823 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298827 */     GIR_RootConstrainSelectedInstOperands,
     /* 298828 */     // GIR_Coverage, 13626,
     /* 298828 */     GIR_EraseRootFromParent_Done,
     /* 298829 */   // Label 5800: @298829
     /* 298829 */   GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(298889), // Rule ID 13627 //
     /* 298834 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF64F64),
     /* 298837 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 298842 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 298845 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 298848 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv2s64,
     /* 298851 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv2s64,
     /* 298854 */     // MIs[0] tile
     /* 298854 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298857 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 298862 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298866 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298870 */     // (intrinsic_void 954:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv2i1] }:$Pn, PPR3bAny:{ *:[nxv2i1] }:$Pm, nxv2f64:{ *:[nxv2f64] }:$Zn, nxv2f64:{ *:[nxv2f64] }:$Zm)  =>  (FMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv2i1] }:$Pn, ?:{ *:[nxv2i1] }:$Pm, ?:{ *:[nxv2f64] }:$Zn, ?:{ *:[nxv2f64] }:$Zm)
     /* 298870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_D_PSEUDO),
     /* 298873 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298875 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298877 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298879 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298881 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298883 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298887 */     GIR_RootConstrainSelectedInstOperands,
     /* 298888 */     // GIR_Coverage, 13627,
     /* 298888 */     GIR_EraseRootFromParent_Done,
     /* 298889 */   // Label 5801: @298889
     /* 298889 */   GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(298949), // Rule ID 13628 //
     /* 298894 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298897 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops_wide),
     /* 298902 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 298905 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 298908 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 298911 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 298914 */     // MIs[0] tile
     /* 298914 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298917 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298922 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298926 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298930 */     // (intrinsic_void 956:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPSL_MPPZZ_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 298930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPSL_MPPZZ_PSEUDO),
     /* 298933 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298935 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298937 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298939 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 298941 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 298943 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 298947 */     GIR_RootConstrainSelectedInstOperands,
     /* 298948 */     // GIR_Coverage, 13628,
     /* 298948 */     GIR_EraseRootFromParent_Done,
     /* 298949 */   // Label 5802: @298949
     /* 298949 */   GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(299009), // Rule ID 13629 //
     /* 298954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 298957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
     /* 298962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 298965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 298968 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 298971 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 298974 */     // MIs[0] tile
     /* 298974 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 298977 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 298982 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298986 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 298990 */     // (intrinsic_void 1056:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 298990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_S_PSEUDO),
     /* 298993 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 298995 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 298997 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 298999 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299001 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299003 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299007 */     GIR_RootConstrainSelectedInstOperands,
     /* 299008 */     // GIR_Coverage, 13629,
     /* 299008 */     GIR_EraseRootFromParent_Done,
     /* 299009 */   // Label 5803: @299009
     /* 299009 */   GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(299069), // Rule ID 13630 //
     /* 299014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299017 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
     /* 299022 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299025 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299028 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299031 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299034 */     // MIs[0] tile
     /* 299034 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299037 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299042 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299046 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299050 */     // (intrinsic_void 1189:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_S_PSEUDO),
     /* 299053 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299055 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299057 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299059 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299061 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299063 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299067 */     GIR_RootConstrainSelectedInstOperands,
     /* 299068 */     // GIR_Coverage, 13630,
     /* 299068 */     GIR_EraseRootFromParent_Done,
     /* 299069 */   // Label 5804: @299069
     /* 299069 */   GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(299129), // Rule ID 13631 //
     /* 299074 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299077 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
     /* 299082 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299085 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299088 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299091 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299094 */     // MIs[0] tile
     /* 299094 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299097 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299102 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299106 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299110 */     // (intrinsic_void 1191:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (UMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_S_PSEUDO),
     /* 299113 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299115 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299117 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299119 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299121 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299123 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299127 */     GIR_RootConstrainSelectedInstOperands,
     /* 299128 */     // GIR_Coverage, 13631,
     /* 299128 */     GIR_EraseRootFromParent_Done,
     /* 299129 */   // Label 5805: @299129
     /* 299129 */   GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(299189), // Rule ID 13632 //
     /* 299134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
     /* 299142 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299145 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299148 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299151 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299154 */     // MIs[0] tile
     /* 299154 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299157 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299162 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299166 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299170 */     // (intrinsic_void 1106:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_S_PSEUDO),
     /* 299173 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299175 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299177 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299179 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299181 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299183 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299187 */     GIR_RootConstrainSelectedInstOperands,
     /* 299188 */     // GIR_Coverage, 13632,
     /* 299188 */     GIR_EraseRootFromParent_Done,
     /* 299189 */   // Label 5806: @299189
     /* 299189 */   GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(299249), // Rule ID 13633 //
     /* 299194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299197 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
     /* 299202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299208 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299211 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299214 */     // MIs[0] tile
     /* 299214 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299217 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299222 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299226 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299230 */     // (intrinsic_void 1107:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (SUMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_S_PSEUDO),
     /* 299233 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299237 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299239 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299241 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299247 */     GIR_RootConstrainSelectedInstOperands,
     /* 299248 */     // GIR_Coverage, 13633,
     /* 299248 */     GIR_EraseRootFromParent_Done,
     /* 299249 */   // Label 5807: @299249
     /* 299249 */   GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(299309), // Rule ID 13634 //
     /* 299254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
     /* 299262 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299265 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299268 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299271 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299274 */     // MIs[0] tile
     /* 299274 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299277 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299286 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299290 */     // (intrinsic_void 1223:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOPA_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_S_PSEUDO),
     /* 299293 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299295 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299297 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299299 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299301 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299303 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299307 */     GIR_RootConstrainSelectedInstOperands,
     /* 299308 */     // GIR_Coverage, 13634,
     /* 299308 */     GIR_EraseRootFromParent_Done,
     /* 299309 */   // Label 5808: @299309
     /* 299309 */   GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(299369), // Rule ID 13635 //
     /* 299314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME),
     /* 299317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
     /* 299322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 299325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 299328 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 299331 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv16s8,
     /* 299334 */     // MIs[0] tile
     /* 299334 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299337 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299342 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299346 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299350 */     // (intrinsic_void 1224:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv16i1] }:$Pn, PPR3bAny:{ *:[nxv16i1] }:$Pm, nxv16i8:{ *:[nxv16i8] }:$Zn, nxv16i8:{ *:[nxv16i8] }:$Zm)  =>  (USMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv16i1] }:$Pn, ?:{ *:[nxv16i1] }:$Pm, ?:{ *:[nxv16i8] }:$Zn, ?:{ *:[nxv16i8] }:$Zm)
     /* 299350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_S_PSEUDO),
     /* 299353 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299357 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299359 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299361 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299363 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299367 */     GIR_RootConstrainSelectedInstOperands,
     /* 299368 */     // GIR_Coverage, 13635,
     /* 299368 */     GIR_EraseRootFromParent_Done,
     /* 299369 */   // Label 5809: @299369
     /* 299369 */   GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(299429), // Rule ID 13636 //
     /* 299374 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299377 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_wide),
     /* 299382 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299385 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299388 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299391 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299394 */     // MIs[0] tile
     /* 299394 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299397 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299402 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299406 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299410 */     // (intrinsic_void 1056:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_D_PSEUDO),
     /* 299413 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299415 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299417 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299419 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299421 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299423 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299427 */     GIR_RootConstrainSelectedInstOperands,
     /* 299428 */     // GIR_Coverage, 13636,
     /* 299428 */     GIR_EraseRootFromParent_Done,
     /* 299429 */   // Label 5810: @299429
     /* 299429 */   GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(299489), // Rule ID 13637 //
     /* 299434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299437 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_wide),
     /* 299442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299445 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299448 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299451 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299454 */     // MIs[0] tile
     /* 299454 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299457 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299466 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299470 */     // (intrinsic_void 1189:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_D_PSEUDO),
     /* 299473 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299475 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299477 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299479 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299481 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299483 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299487 */     GIR_RootConstrainSelectedInstOperands,
     /* 299488 */     // GIR_Coverage, 13637,
     /* 299488 */     GIR_EraseRootFromParent_Done,
     /* 299489 */   // Label 5811: @299489
     /* 299489 */   GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(299549), // Rule ID 13638 //
     /* 299494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_wide),
     /* 299502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299508 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299511 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299514 */     // MIs[0] tile
     /* 299514 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299517 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299526 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299530 */     // (intrinsic_void 1191:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_D_PSEUDO),
     /* 299533 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299535 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299537 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299539 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299541 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299543 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299547 */     GIR_RootConstrainSelectedInstOperands,
     /* 299548 */     // GIR_Coverage, 13638,
     /* 299548 */     GIR_EraseRootFromParent_Done,
     /* 299549 */   // Label 5812: @299549
     /* 299549 */   GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(299609), // Rule ID 13639 //
     /* 299554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299557 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumopa_wide),
     /* 299562 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299565 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299568 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299571 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299574 */     // MIs[0] tile
     /* 299574 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299577 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299582 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299586 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299590 */     // (intrinsic_void 1106:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPA_MPPZZ_D_PSEUDO),
     /* 299593 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299597 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299599 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299601 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299607 */     GIR_RootConstrainSelectedInstOperands,
     /* 299608 */     // GIR_Coverage, 13639,
     /* 299608 */     GIR_EraseRootFromParent_Done,
     /* 299609 */   // Label 5813: @299609
     /* 299609 */   GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(299669), // Rule ID 13640 //
     /* 299614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299617 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_sumops_wide),
     /* 299622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299628 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299631 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299634 */     // MIs[0] tile
     /* 299634 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299637 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299642 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299646 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299650 */     // (intrinsic_void 1107:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SUMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUMOPS_MPPZZ_D_PSEUDO),
     /* 299653 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299657 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299659 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299661 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299663 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299667 */     GIR_RootConstrainSelectedInstOperands,
     /* 299668 */     // GIR_Coverage, 13640,
     /* 299668 */     GIR_EraseRootFromParent_Done,
     /* 299669 */   // Label 5814: @299669
     /* 299669 */   GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(299729), // Rule ID 13641 //
     /* 299674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmopa_wide),
     /* 299682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299688 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299691 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299694 */     // MIs[0] tile
     /* 299694 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299697 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299702 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299706 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299710 */     // (intrinsic_void 1223:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOPA_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPA_MPPZZ_D_PSEUDO),
     /* 299713 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299715 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299717 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299719 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299721 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299723 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299727 */     GIR_RootConstrainSelectedInstOperands,
     /* 299728 */     // GIR_Coverage, 13641,
     /* 299728 */     GIR_EraseRootFromParent_Done,
     /* 299729 */   // Label 5815: @299729
     /* 299729 */   GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(299789), // Rule ID 13642 //
     /* 299734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEI16I64),
     /* 299737 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_usmops_wide),
     /* 299742 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299745 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299748 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299751 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299754 */     // MIs[0] tile
     /* 299754 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299757 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_7),
     /* 299762 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299766 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299770 */     // (intrinsic_void 1224:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_7>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (USMOPS_MPPZZ_D_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USMOPS_MPPZZ_D_PSEUDO),
     /* 299773 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299777 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299779 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299781 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299783 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299787 */     GIR_RootConstrainSelectedInstOperands,
     /* 299788 */     // GIR_Coverage, 13642,
     /* 299788 */     GIR_EraseRootFromParent_Done,
     /* 299789 */   // Label 5816: @299789
     /* 299789 */   GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(299849), // Rule ID 14014 //
     /* 299794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 299797 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_bmops_za32),
     /* 299802 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 299805 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 299808 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv4s32,
     /* 299811 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv4s32,
     /* 299814 */     // MIs[0] tile
     /* 299814 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299817 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299822 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299826 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299830 */     // (intrinsic_void 826:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv4i1] }:$Pn, PPR3bAny:{ *:[nxv4i1] }:$Pm, nxv4i32:{ *:[nxv4i32] }:$Zn, nxv4i32:{ *:[nxv4i32] }:$Zm)  =>  (BMOPS_MPPZZ_S_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv4i1] }:$Pn, ?:{ *:[nxv4i1] }:$Pm, ?:{ *:[nxv4i32] }:$Zn, ?:{ *:[nxv4i32] }:$Zm)
     /* 299830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BMOPS_MPPZZ_S_PSEUDO),
     /* 299833 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299835 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299837 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299839 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299841 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299843 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299847 */     GIR_RootConstrainSelectedInstOperands,
     /* 299848 */     // GIR_Coverage, 14014,
     /* 299848 */     GIR_EraseRootFromParent_Done,
     /* 299849 */   // Label 5817: @299849
     /* 299849 */   GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(299909), // Rule ID 14015 //
     /* 299854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 299857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_smops_za32),
     /* 299862 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299865 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299868 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299871 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299874 */     // MIs[0] tile
     /* 299874 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299877 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299882 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299886 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299890 */     // (intrinsic_void 1057:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (SMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOPS_MPPZZ_HtoS_PSEUDO),
     /* 299893 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299895 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299897 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299899 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299901 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299903 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299907 */     GIR_RootConstrainSelectedInstOperands,
     /* 299908 */     // GIR_Coverage, 14015,
     /* 299908 */     GIR_EraseRootFromParent_Done,
     /* 299909 */   // Label 5818: @299909
     /* 299909 */   GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(299969), // Rule ID 14016 //
     /* 299914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 299917 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umopa_za32),
     /* 299922 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299925 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299928 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299931 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299934 */     // MIs[0] tile
     /* 299934 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299937 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 299942 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299946 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 299950 */     // (intrinsic_void 1190:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPA_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 299950 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPA_MPPZZ_HtoS_PSEUDO),
     /* 299953 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 299955 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 299957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 299959 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 299961 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 299963 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 299967 */     GIR_RootConstrainSelectedInstOperands,
     /* 299968 */     // GIR_Coverage, 14016,
     /* 299968 */     GIR_EraseRootFromParent_Done,
     /* 299969 */   // Label 5819: @299969
     /* 299969 */   GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(300029), // Rule ID 14017 //
     /* 299974 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSME2),
     /* 299977 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_umops_za32),
     /* 299982 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 299985 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 299988 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 299991 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 299994 */     // MIs[0] tile
     /* 299994 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 299997 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_3),
     /* 300002 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 300006 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 300010 */     // (intrinsic_void 1192:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_3>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8i16:{ *:[nxv8i16] }:$Zn, nxv8i16:{ *:[nxv8i16] }:$Zm)  =>  (UMOPS_MPPZZ_HtoS_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8i16] }:$Zn, ?:{ *:[nxv8i16] }:$Zm)
     /* 300010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOPS_MPPZZ_HtoS_PSEUDO),
     /* 300013 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 300015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 300017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 300019 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 300021 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 300023 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300027 */     GIR_RootConstrainSelectedInstOperands,
     /* 300028 */     // GIR_Coverage, 14017,
     /* 300028 */     GIR_EraseRootFromParent_Done,
     /* 300029 */   // Label 5820: @300029
     /* 300029 */   GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(300089), // Rule ID 14128 //
     /* 300034 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMEF16F16),
     /* 300037 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::aarch64_sme_mops),
     /* 300042 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 300045 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 300048 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv8s16,
     /* 300051 */     GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_nxv8s16,
     /* 300054 */     // MIs[0] tile
     /* 300054 */     GIM_CheckIsImm, /*MI*/0, /*Op*/1,
     /* 300057 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timm32_0_1),
     /* 300062 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 300066 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::PPR_3bRegClassID),
     /* 300070 */     // (intrinsic_void 954:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timm32_0_1>>:$tile, PPR3bAny:{ *:[nxv8i1] }:$Pn, PPR3bAny:{ *:[nxv8i1] }:$Pm, nxv8f16:{ *:[nxv8f16] }:$Zn, nxv8f16:{ *:[nxv8f16] }:$Zm)  =>  (FMOPS_MPPZZ_H_PSEUDO ?:{ *:[i32] }:$tile, ?:{ *:[nxv8i1] }:$Pn, ?:{ *:[nxv8i1] }:$Pm, ?:{ *:[nxv8f16] }:$Zn, ?:{ *:[nxv8f16] }:$Zm)
     /* 300070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOPS_MPPZZ_H_PSEUDO),
     /* 300073 */     GIR_RootToRootCopy, /*OpIdx*/1, // tile
     /* 300075 */     GIR_RootToRootCopy, /*OpIdx*/2, // Pn
     /* 300077 */     GIR_RootToRootCopy, /*OpIdx*/3, // Pm
     /* 300079 */     GIR_RootToRootCopy, /*OpIdx*/4, // Zn
     /* 300081 */     GIR_RootToRootCopy, /*OpIdx*/5, // Zm
     /* 300083 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300087 */     GIR_RootConstrainSelectedInstOperands,
     /* 300088 */     // GIR_Coverage, 14128,
     /* 300088 */     GIR_EraseRootFromParent_Done,
     /* 300089 */   // Label 5821: @300089
     /* 300089 */   GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(300137), // Rule ID 3662 //
     /* 300094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300097 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalb_lane),
     /* 300102 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 300105 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 300108 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300111 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300118 */     // MIs[0] Op4
     /* 300118 */     // No operand predicates
     /* 300118 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1547:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALB_ZZZI:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALB_ZZZI),
     /* 300121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300123 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300125 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300127 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300129 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300131 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300135 */     GIR_RootConstrainSelectedInstOperands,
     /* 300136 */     // GIR_Coverage, 3662,
     /* 300136 */     GIR_EraseRootFromParent_Done,
     /* 300137 */   // Label 5822: @300137
     /* 300137 */   GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(300185), // Rule ID 3664 //
     /* 300142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbb_lane),
     /* 300150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 300153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300159 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300162 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300166 */     // MIs[0] Op4
     /* 300166 */     // No operand predicates
     /* 300166 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1549:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLBB_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBB_ZZZI),
     /* 300169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300173 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300175 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300177 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300179 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300183 */     GIR_RootConstrainSelectedInstOperands,
     /* 300184 */     // GIR_Coverage, 3664,
     /* 300184 */     GIR_EraseRootFromParent_Done,
     /* 300185 */   // Label 5823: @300185
     /* 300185 */   GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(300233), // Rule ID 3666 //
     /* 300190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT2),
     /* 300193 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot_lane),
     /* 300198 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 300201 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 300204 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300207 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300210 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300214 */     // MIs[0] Op4
     /* 300214 */     // No operand predicates
     /* 300214 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1545:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FDOT_ZZZI_BtoH:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300214 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_BtoH),
     /* 300217 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300223 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300225 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300227 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300231 */     GIR_RootConstrainSelectedInstOperands,
     /* 300232 */     // GIR_Coverage, 3666,
     /* 300232 */     GIR_EraseRootFromParent_Done,
     /* 300233 */   // Label 5824: @300233
     /* 300233 */   GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(300281), // Rule ID 3667 //
     /* 300238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8DOT4),
     /* 300241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fdot_lane),
     /* 300246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 300249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300255 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300258 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300262 */     // MIs[0] Op4
     /* 300262 */     // No operand predicates
     /* 300262 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1545:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FDOT_ZZZI_BtoS:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDOT_ZZZI_BtoS),
     /* 300265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300267 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300271 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300273 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300275 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300279 */     GIR_RootConstrainSelectedInstOperands,
     /* 300280 */     // GIR_Coverage, 3667,
     /* 300280 */     GIR_EraseRootFromParent_Done,
     /* 300281 */   // Label 5825: @300281
     /* 300281 */   GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(300329), // Rule ID 13602 //
     /* 300286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300289 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalt_lane),
     /* 300294 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv8s16,
     /* 300297 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 300300 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300303 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300310 */     // MIs[0] Op4
     /* 300310 */     // No operand predicates
     /* 300310 */     // (intrinsic_w_chain:{ *:[nxv8f16] } 1557:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALT_ZZZI:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALT_ZZZI),
     /* 300313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300315 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300317 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300319 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300321 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300323 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300327 */     GIR_RootConstrainSelectedInstOperands,
     /* 300328 */     // GIR_Coverage, 13602,
     /* 300328 */     GIR_EraseRootFromParent_Done,
     /* 300329 */   // Label 5826: @300329
     /* 300329 */   GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(300377), // Rule ID 13604 //
     /* 300334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300337 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlallbt_lane),
     /* 300342 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 300345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300351 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300358 */     // MIs[0] Op4
     /* 300358 */     // No operand predicates
     /* 300358 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1551:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLBT_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLBT_ZZZI),
     /* 300361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300365 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300367 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300369 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300371 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300375 */     GIR_RootConstrainSelectedInstOperands,
     /* 300376 */     // GIR_Coverage, 13604,
     /* 300376 */     GIR_EraseRootFromParent_Done,
     /* 300377 */   // Label 5827: @300377
     /* 300377 */   GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(300425), // Rule ID 13605 //
     /* 300382 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300385 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltb_lane),
     /* 300390 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 300393 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300396 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300399 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300406 */     // MIs[0] Op4
     /* 300406 */     // No operand predicates
     /* 300406 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1553:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLTB_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTB_ZZZI),
     /* 300409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300411 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300413 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300415 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300417 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300419 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300423 */     GIR_RootConstrainSelectedInstOperands,
     /* 300424 */     // GIR_Coverage, 13605,
     /* 300424 */     GIR_EraseRootFromParent_Done,
     /* 300425 */   // Label 5828: @300425
     /* 300425 */   GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(300473), // Rule ID 13606 //
     /* 300430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSSVE_FP8FMA),
     /* 300433 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_fp8_fmlalltt_lane),
     /* 300438 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_nxv4s32,
     /* 300441 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 300444 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 300447 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_nxv16s8,
     /* 300450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 300454 */     // MIs[0] Op4
     /* 300454 */     // No operand predicates
     /* 300454 */     // (intrinsic_w_chain:{ *:[nxv4f32] } 1555:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3, i32:{ *:[i32] }:$Op4)  =>  (FMLALLTT_ZZZI:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3, ?:{ *:[i32] }:$Op4)
     /* 300454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLALLTT_ZZZI),
     /* 300457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zda]
     /* 300459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 300461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 300463 */     GIR_RootToRootCopy, /*OpIdx*/4, // Op3
     /* 300465 */     GIR_RootToRootCopy, /*OpIdx*/5, // Op4
     /* 300467 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 300471 */     GIR_RootConstrainSelectedInstOperands,
     /* 300472 */     // GIR_Coverage, 13606,
     /* 300472 */     GIR_EraseRootFromParent_Done,
     /* 300473 */   // Label 5829: @300473
     /* 300473 */   GIM_Reject,
     /* 300474 */ // Label 5779: @300474
     /* 300474 */ GIM_Reject,
     /* 300475 */ // Label 45: @300475
     /* 300475 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 5834*/ GIMT_Encode4(300764),
     /* 300486 */ /*GILLT_s64*//*Label 5830*/ GIMT_Encode4(300518), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300498 */ /*GILLT_v2s64*//*Label 5831*/ GIMT_Encode4(300578), GIMT_Encode4(0),
     /* 300506 */ /*GILLT_v4s32*//*Label 5832*/ GIMT_Encode4(300640), GIMT_Encode4(0),
     /* 300514 */ /*GILLT_v8s16*//*Label 5833*/ GIMT_Encode4(300702),
     /* 300518 */ // Label 5830: @300518
     /* 300518 */ GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(300577), // Rule ID 7142 //
     /* 300523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 300526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 300530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 300534 */   // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
     /* 300534 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 300537 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 300541 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 300546 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 300548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 300551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 300553 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 300556 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 300558 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 300561 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 300566 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 300571 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 300576 */   // GIR_Coverage, 7142,
     /* 300576 */   GIR_EraseRootFromParent_Done,
     /* 300577 */ // Label 5835: @300577
     /* 300577 */ GIM_Reject,
     /* 300578 */ // Label 5831: @300578
     /* 300578 */ GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(300639),
     /* 300583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 300586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300590 */   GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(300617), // Rule ID 7004 //
     /* 300595 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 300602 */     // (anyext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 300602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
     /* 300605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 300612 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300615 */     GIR_RootConstrainSelectedInstOperands,
     /* 300616 */     // GIR_Coverage, 7004,
     /* 300616 */     GIR_EraseRootFromParent_Done,
     /* 300617 */   // Label 5837: @300617
     /* 300617 */   GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(300638), // Rule ID 6997 //
     /* 300622 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300626 */     // (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 300626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 300629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300631 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 300633 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300636 */     GIR_RootConstrainSelectedInstOperands,
     /* 300637 */     // GIR_Coverage, 6997,
     /* 300637 */     GIR_EraseRootFromParent_Done,
     /* 300638 */   // Label 5838: @300638
     /* 300638 */   GIM_Reject,
     /* 300639 */ // Label 5836: @300639
     /* 300639 */ GIM_Reject,
     /* 300640 */ // Label 5832: @300640
     /* 300640 */ GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(300701),
     /* 300645 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 300648 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300652 */   GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(300679), // Rule ID 7001 //
     /* 300657 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 300664 */     // (anyext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 300664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
     /* 300667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 300674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300677 */     GIR_RootConstrainSelectedInstOperands,
     /* 300678 */     // GIR_Coverage, 7001,
     /* 300678 */     GIR_EraseRootFromParent_Done,
     /* 300679 */   // Label 5840: @300679
     /* 300679 */   GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(300700), // Rule ID 6994 //
     /* 300684 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300688 */     // (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 300688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 300691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300693 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 300695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300698 */     GIR_RootConstrainSelectedInstOperands,
     /* 300699 */     // GIR_Coverage, 6994,
     /* 300699 */     GIR_EraseRootFromParent_Done,
     /* 300700 */   // Label 5841: @300700
     /* 300700 */   GIM_Reject,
     /* 300701 */ // Label 5839: @300701
     /* 300701 */ GIM_Reject,
     /* 300702 */ // Label 5833: @300702
     /* 300702 */ GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(300763),
     /* 300707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 300710 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300714 */   GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(300741), // Rule ID 6998 //
     /* 300719 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 300726 */     // (anyext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 300726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
     /* 300729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300731 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 300736 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300739 */     GIR_RootConstrainSelectedInstOperands,
     /* 300740 */     // GIR_Coverage, 6998,
     /* 300740 */     GIR_EraseRootFromParent_Done,
     /* 300741 */   // Label 5843: @300741
     /* 300741 */   GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(300762), // Rule ID 6991 //
     /* 300746 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300750 */     // (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 300750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 300753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300755 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 300757 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 300760 */     GIR_RootConstrainSelectedInstOperands,
     /* 300761 */     // GIR_Coverage, 6991,
     /* 300761 */     GIR_EraseRootFromParent_Done,
     /* 300762 */   // Label 5844: @300762
     /* 300762 */   GIM_Reject,
     /* 300763 */ // Label 5842: @300763
     /* 300763 */ GIM_Reject,
     /* 300764 */ // Label 5834: @300764
     /* 300764 */ GIM_Reject,
     /* 300765 */ // Label 46: @300765
     /* 300765 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(10), /*)*//*default:*//*Label 5849*/ GIMT_Encode4(302183),
     /* 300776 */ /*GILLT_s32*//*Label 5845*/ GIMT_Encode4(300808), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 300788 */ /*GILLT_v2s32*//*Label 5846*/ GIMT_Encode4(300847), GIMT_Encode4(0),
     /* 300796 */ /*GILLT_v4s16*//*Label 5847*/ GIMT_Encode4(301197), GIMT_Encode4(0),
     /* 300804 */ /*GILLT_v8s8*//*Label 5848*/ GIMT_Encode4(301690),
     /* 300808 */ // Label 5845: @300808
     /* 300808 */ GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(300846), // Rule ID 7163 //
     /* 300813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 300816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 300820 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 300824 */   // (trunc:{ *:[i32] } GPR64sp:{ *:[i64] }:$src)  =>  (EXTRACT_SUBREG:{ *:[i32] } GPR64sp:{ *:[i64] }:$src, sub_32:{ *:[i32] })
     /* 300824 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 300827 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 300829 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(20), // src
     /* 300835 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 300840 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 300845 */   // GIR_Coverage, 7163,
     /* 300845 */   GIR_EraseRootFromParent_Done,
     /* 300846 */ // Label 5850: @300846
     /* 300846 */ GIM_Reject,
     /* 300847 */ // Label 5846: @300847
     /* 300847 */ GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(301196),
     /* 300852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 300859 */   GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(300937), // Rule ID 6029 //
     /* 300864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 300868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 300872 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300876 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 300880 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 300884 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300888 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 300892 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300897 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 300901 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 300907 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 300909 */     // MIs[1] Operand 2
     /* 300909 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 300920 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 300922 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (xor:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 300922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 300925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300927 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 300931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 300935 */     GIR_RootConstrainSelectedInstOperands,
     /* 300936 */     // GIR_Coverage, 6029,
     /* 300936 */     GIR_EraseRootFromParent_Done,
     /* 300937 */   // Label 5852: @300937
     /* 300937 */   GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(301008), // Rule ID 6025 //
     /* 300942 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 300946 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 300950 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300954 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 300958 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 300962 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 300966 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 300970 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300975 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 300980 */     // MIs[1] Operand 2
     /* 300980 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 300991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 300993 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (add:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (ADDHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 300993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv2i64_v2i32),
     /* 300996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 300998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301006 */     GIR_RootConstrainSelectedInstOperands,
     /* 301007 */     // GIR_Coverage, 6025,
     /* 301007 */     GIR_EraseRootFromParent_Done,
     /* 301008 */   // Label 5853: @301008
     /* 301008 */   GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(301079), // Rule ID 6027 //
     /* 301013 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301017 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301021 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301025 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301029 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 301033 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301037 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 301041 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301046 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301051 */     // MIs[1] Operand 2
     /* 301051 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(32),
     /* 301062 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 301064 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } (sub:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm), 32:{ *:[i32] }))  =>  (SUBHNv2i64_v2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 301064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv2i64_v2i32),
     /* 301067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301069 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301077 */     GIR_RootConstrainSelectedInstOperands,
     /* 301078 */     // GIR_Coverage, 6027,
     /* 301078 */     GIR_EraseRootFromParent_Done,
     /* 301079 */   // Label 5854: @301079
     /* 301079 */   GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(301129), // Rule ID 2193 //
     /* 301084 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301087 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301091 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 301095 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301099 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301104 */     // MIs[1] imm
     /* 301104 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 301107 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 301112 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301114 */     // (trunc:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 301114 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
     /* 301117 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301119 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 301123 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 301127 */     GIR_RootConstrainSelectedInstOperands,
     /* 301128 */     // GIR_Coverage, 2193,
     /* 301128 */     GIR_EraseRootFromParent_Done,
     /* 301129 */   // Label 5855: @301129
     /* 301129 */   GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(301176), // Rule ID 6979 //
     /* 301134 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301138 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301142 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301146 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301151 */     // MIs[1] imm
     /* 301151 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 301154 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 301159 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301161 */     // (trunc:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm)
     /* 301161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv2i32_shift),
     /* 301164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 301170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 301174 */     GIR_RootConstrainSelectedInstOperands,
     /* 301175 */     // GIR_Coverage, 6979,
     /* 301175 */     GIR_EraseRootFromParent_Done,
     /* 301176 */   // Label 5856: @301176
     /* 301176 */   GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(301195), // Rule ID 1129 //
     /* 301181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301184 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301188 */     // (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)  =>  (XTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
     /* 301188 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv2i32),
     /* 301193 */     GIR_RootConstrainSelectedInstOperands,
     /* 301194 */     // GIR_Coverage, 1129,
     /* 301194 */     GIR_Done,
     /* 301195 */   // Label 5857: @301195
     /* 301195 */   GIM_Reject,
     /* 301196 */ // Label 5851: @301196
     /* 301196 */ GIM_Reject,
     /* 301197 */ // Label 5847: @301197
     /* 301197 */ GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(301689),
     /* 301202 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301209 */   GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(301287), // Rule ID 6023 //
     /* 301214 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301218 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301222 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301226 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301230 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 301234 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301238 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 301242 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301247 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 301251 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 301257 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 301259 */     // MIs[1] Operand 2
     /* 301259 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 301270 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301272 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (xor:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 301272 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 301275 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301277 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301281 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301285 */     GIR_RootConstrainSelectedInstOperands,
     /* 301286 */     // GIR_Coverage, 6023,
     /* 301286 */     GIR_EraseRootFromParent_Done,
     /* 301287 */   // Label 5859: @301287
     /* 301287 */   GIM_Try, /*On fail goto*//*Label 5860*/ GIMT_Encode4(301358), // Rule ID 6019 //
     /* 301292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301300 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301304 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301308 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 301312 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301316 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 301320 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301325 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301330 */     // MIs[1] Operand 2
     /* 301330 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 301341 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 301343 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (add:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (ADDHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 301343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv4i32_v4i16),
     /* 301346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301348 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301352 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301356 */     GIR_RootConstrainSelectedInstOperands,
     /* 301357 */     // GIR_Coverage, 6019,
     /* 301357 */     GIR_EraseRootFromParent_Done,
     /* 301358 */   // Label 5860: @301358
     /* 301358 */   GIM_Try, /*On fail goto*//*Label 5861*/ GIMT_Encode4(301429), // Rule ID 6021 //
     /* 301363 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301367 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301371 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301375 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301379 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 301383 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301387 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 301391 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301396 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301401 */     // MIs[1] Operand 2
     /* 301401 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 301412 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 301414 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } (sub:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm), 16:{ *:[i32] }))  =>  (SUBHNv4i32_v4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 301414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv4i32_v4i16),
     /* 301417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301419 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301423 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301427 */     GIR_RootConstrainSelectedInstOperands,
     /* 301428 */     // GIR_Coverage, 6021,
     /* 301428 */     GIR_EraseRootFromParent_Done,
     /* 301429 */   // Label 5861: @301429
     /* 301429 */   GIM_Try, /*On fail goto*//*Label 5862*/ GIMT_Encode4(301521), // Rule ID 6145 //
     /* 301434 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301438 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 301442 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 301445 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 301449 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301453 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301457 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 301461 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301465 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301470 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 301474 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 301478 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 301482 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301487 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301489 */     // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vn), (trunc:{ *:[v2i32] } V128:{ *:[v2i64] }:$Vm)))  =>  (XTNv4i16:{ *:[v4i16] } (UZP1v4i32:{ *:[f128] } V128:{ *:[v2i64] }:$Vn, V128:{ *:[v2i64] }:$Vm))
     /* 301489 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 301492 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 301496 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 301501 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 301505 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
     /* 301509 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 301511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
     /* 301514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301516 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 301519 */     GIR_RootConstrainSelectedInstOperands,
     /* 301520 */     // GIR_Coverage, 6145,
     /* 301520 */     GIR_EraseRootFromParent_Done,
     /* 301521 */   // Label 5862: @301521
     /* 301521 */   GIM_Try, /*On fail goto*//*Label 5863*/ GIMT_Encode4(301571), // Rule ID 2192 //
     /* 301526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301529 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301533 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 301537 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301541 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301546 */     // MIs[1] imm
     /* 301546 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 301549 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 301554 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301556 */     // (trunc:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 301556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
     /* 301559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301561 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 301565 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 301569 */     GIR_RootConstrainSelectedInstOperands,
     /* 301570 */     // GIR_Coverage, 2192,
     /* 301570 */     GIR_EraseRootFromParent_Done,
     /* 301571 */   // Label 5863: @301571
     /* 301571 */   GIM_Try, /*On fail goto*//*Label 5864*/ GIMT_Encode4(301618), // Rule ID 6978 //
     /* 301576 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301580 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301584 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301588 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301593 */     // MIs[1] imm
     /* 301593 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 301596 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 301601 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301603 */     // (trunc:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm)
     /* 301603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv4i16_shift),
     /* 301606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 301612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 301616 */     GIR_RootConstrainSelectedInstOperands,
     /* 301617 */     // GIR_Coverage, 6978,
     /* 301617 */     GIR_EraseRootFromParent_Done,
     /* 301618 */   // Label 5864: @301618
     /* 301618 */   GIM_Try, /*On fail goto*//*Label 5865*/ GIMT_Encode4(301669), // Rule ID 6173 //
     /* 301623 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301627 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 301631 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 301634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 301638 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 301642 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301647 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301652 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 301654 */     // (trunc:{ *:[v4i16] } (concat_vectors:{ *:[v4i32] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm))  =>  (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vm)
     /* 301654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 301657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 301663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /* 301667 */     GIR_RootConstrainSelectedInstOperands,
     /* 301668 */     // GIR_Coverage, 6173,
     /* 301668 */     GIR_EraseRootFromParent_Done,
     /* 301669 */   // Label 5865: @301669
     /* 301669 */   GIM_Try, /*On fail goto*//*Label 5866*/ GIMT_Encode4(301688), // Rule ID 1128 //
     /* 301674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 301677 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301681 */     // (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)  =>  (XTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
     /* 301681 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv4i16),
     /* 301686 */     GIR_RootConstrainSelectedInstOperands,
     /* 301687 */     // GIR_Coverage, 1128,
     /* 301687 */     GIR_Done,
     /* 301688 */   // Label 5866: @301688
     /* 301688 */   GIM_Reject,
     /* 301689 */ // Label 5858: @301689
     /* 301689 */ GIM_Reject,
     /* 301690 */ // Label 5848: @301690
     /* 301690 */ GIM_Try, /*On fail goto*//*Label 5867*/ GIMT_Encode4(302182),
     /* 301695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 301702 */   GIM_Try, /*On fail goto*//*Label 5868*/ GIMT_Encode4(301780), // Rule ID 6017 //
     /* 301707 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301711 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301715 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301719 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301723 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 301727 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301731 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 301735 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301740 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 301744 */     GIM_CheckOpcodeIsEither, /*MI*/3, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 301750 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/3,
     /* 301752 */     // MIs[1] Operand 2
     /* 301752 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 301763 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301765 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (xor:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 301765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 301768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301770 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301774 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301778 */     GIR_RootConstrainSelectedInstOperands,
     /* 301779 */     // GIR_Coverage, 6017,
     /* 301779 */     GIR_EraseRootFromParent_Done,
     /* 301780 */   // Label 5868: @301780
     /* 301780 */   GIM_Try, /*On fail goto*//*Label 5869*/ GIMT_Encode4(301851), // Rule ID 6013 //
     /* 301785 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301789 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301793 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301797 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301801 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 301805 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301809 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 301813 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301823 */     // MIs[1] Operand 2
     /* 301823 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 301834 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 301836 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (add:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (ADDHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 301836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDHNv8i16_v8i8),
     /* 301839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301841 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301845 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301849 */     GIR_RootConstrainSelectedInstOperands,
     /* 301850 */     // GIR_Coverage, 6013,
     /* 301850 */     GIR_EraseRootFromParent_Done,
     /* 301851 */   // Label 5869: @301851
     /* 301851 */   GIM_Try, /*On fail goto*//*Label 5870*/ GIMT_Encode4(301922), // Rule ID 6015 //
     /* 301856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 301864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 301876 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 301880 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 301884 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301889 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301894 */     // MIs[1] Operand 2
     /* 301894 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 301905 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 301907 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } (sub:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm), 8:{ *:[i32] }))  =>  (SUBHNv8i16_v8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 301907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBHNv8i16_v8i8),
     /* 301910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 301912 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 301916 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 301920 */     GIR_RootConstrainSelectedInstOperands,
     /* 301921 */     // GIR_Coverage, 6015,
     /* 301921 */     GIR_EraseRootFromParent_Done,
     /* 301922 */   // Label 5870: @301922
     /* 301922 */   GIM_Try, /*On fail goto*//*Label 5871*/ GIMT_Encode4(302014), // Rule ID 6118 //
     /* 301927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 301931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 301935 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 301938 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 301942 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 301946 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 301950 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 301954 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301963 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 301967 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 301971 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 301975 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 301980 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 301982 */     // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vn), (trunc:{ *:[v4i16] } V128:{ *:[v4i32] }:$Vm)))  =>  (XTNv8i8:{ *:[v8i8] } (UZP1v8i16:{ *:[f128] } V128:{ *:[v4i32] }:$Vn, V128:{ *:[v4i32] }:$Vm))
     /* 301982 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 301985 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 301989 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 301994 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Vn
     /* 301998 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, // Vm
     /* 302002 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 302004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
     /* 302007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302009 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 302012 */     GIR_RootConstrainSelectedInstOperands,
     /* 302013 */     // GIR_Coverage, 6118,
     /* 302013 */     GIR_EraseRootFromParent_Done,
     /* 302014 */   // Label 5871: @302014
     /* 302014 */   GIM_Try, /*On fail goto*//*Label 5872*/ GIMT_Encode4(302064), // Rule ID 2191 //
     /* 302019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302022 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302026 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302030 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302034 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302039 */     // MIs[1] imm
     /* 302039 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302042 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 302047 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302049 */     // (trunc:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
     /* 302052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302054 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302058 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302062 */     GIR_RootConstrainSelectedInstOperands,
     /* 302063 */     // GIR_Coverage, 2191,
     /* 302063 */     GIR_EraseRootFromParent_Done,
     /* 302064 */   // Label 5872: @302064
     /* 302064 */   GIM_Try, /*On fail goto*//*Label 5873*/ GIMT_Encode4(302111), // Rule ID 6977 //
     /* 302069 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302073 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 302077 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302081 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302086 */     // MIs[1] imm
     /* 302086 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302089 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 302094 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302096 */     // (trunc:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm)
     /* 302096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SHRNv8i8_shift),
     /* 302099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302101 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302105 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302109 */     GIR_RootConstrainSelectedInstOperands,
     /* 302110 */     // GIR_Coverage, 6977,
     /* 302110 */     GIR_EraseRootFromParent_Done,
     /* 302111 */   // Label 5873: @302111
     /* 302111 */   GIM_Try, /*On fail goto*//*Label 5874*/ GIMT_Encode4(302162), // Rule ID 6172 //
     /* 302116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONCAT_VECTORS),
     /* 302124 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 302127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 302131 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 302135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302140 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302145 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302147 */     // (trunc:{ *:[v8i8] } (concat_vectors:{ *:[v8i16] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm))  =>  (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vm)
     /* 302147 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
     /* 302150 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302152 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 302156 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
     /* 302160 */     GIR_RootConstrainSelectedInstOperands,
     /* 302161 */     // GIR_Coverage, 6172,
     /* 302161 */     GIR_EraseRootFromParent_Done,
     /* 302162 */   // Label 5874: @302162
     /* 302162 */   GIM_Try, /*On fail goto*//*Label 5875*/ GIMT_Encode4(302181), // Rule ID 1127 //
     /* 302167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302170 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302174 */     // (trunc:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)  =>  (XTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
     /* 302174 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::XTNv8i8),
     /* 302179 */     GIR_RootConstrainSelectedInstOperands,
     /* 302180 */     // GIR_Coverage, 1127,
     /* 302180 */     GIR_Done,
     /* 302181 */   // Label 5875: @302181
     /* 302181 */   GIM_Reject,
     /* 302182 */ // Label 5867: @302182
     /* 302182 */ GIM_Reject,
     /* 302183 */ // Label 5849: @302183
     /* 302183 */ GIM_Reject,
     /* 302184 */ // Label 47: @302184
     /* 302184 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(10), /*)*//*default:*//*Label 5879*/ GIMT_Encode4(302614),
     /* 302195 */ /*GILLT_v2s32*//*Label 5876*/ GIMT_Encode4(302215), GIMT_Encode4(0),
     /* 302203 */ /*GILLT_v4s16*//*Label 5877*/ GIMT_Encode4(302348), GIMT_Encode4(0),
     /* 302211 */ /*GILLT_v8s8*//*Label 5878*/ GIMT_Encode4(302481),
     /* 302215 */ // Label 5876: @302215
     /* 302215 */ GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(302347),
     /* 302220 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302227 */   GIM_Try, /*On fail goto*//*Label 5881*/ GIMT_Encode4(302277), // Rule ID 2203 //
     /* 302232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302235 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302239 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302243 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302247 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302252 */     // MIs[1] imm
     /* 302252 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302255 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 302260 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302262 */     // (truncssat_s:{ *:[v2i32] } (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302262 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv2i32_shift),
     /* 302265 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302267 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302271 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302275 */     GIR_RootConstrainSelectedInstOperands,
     /* 302276 */     // GIR_Coverage, 2203,
     /* 302276 */     GIR_EraseRootFromParent_Done,
     /* 302277 */   // Label 5881: @302277
     /* 302277 */   GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(302327), // Rule ID 2223 //
     /* 302282 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302293 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302297 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302302 */     // MIs[1] imm
     /* 302302 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302305 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 302310 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302312 */     // (truncssat_s:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302312 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv2i32_shift),
     /* 302315 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302317 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302321 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302325 */     GIR_RootConstrainSelectedInstOperands,
     /* 302326 */     // GIR_Coverage, 2223,
     /* 302326 */     GIR_EraseRootFromParent_Done,
     /* 302327 */   // Label 5882: @302327
     /* 302327 */   GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(302346), // Rule ID 1068 //
     /* 302332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302339 */     // (truncssat_s:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)  =>  (SQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
     /* 302339 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv2i32),
     /* 302344 */     GIR_RootConstrainSelectedInstOperands,
     /* 302345 */     // GIR_Coverage, 1068,
     /* 302345 */     GIR_Done,
     /* 302346 */   // Label 5883: @302346
     /* 302346 */   GIM_Reject,
     /* 302347 */ // Label 5880: @302347
     /* 302347 */ GIM_Reject,
     /* 302348 */ // Label 5877: @302348
     /* 302348 */ GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(302480),
     /* 302353 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302360 */   GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(302410), // Rule ID 2202 //
     /* 302365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302380 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302385 */     // MIs[1] imm
     /* 302385 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302388 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 302393 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302395 */     // (truncssat_s:{ *:[v4i16] } (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302395 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv4i16_shift),
     /* 302398 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302408 */     GIR_RootConstrainSelectedInstOperands,
     /* 302409 */     // GIR_Coverage, 2202,
     /* 302409 */     GIR_EraseRootFromParent_Done,
     /* 302410 */   // Label 5885: @302410
     /* 302410 */   GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(302460), // Rule ID 2222 //
     /* 302415 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302426 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302435 */     // MIs[1] imm
     /* 302435 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302438 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 302443 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302445 */     // (truncssat_s:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv4i16_shift),
     /* 302448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302450 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302454 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302458 */     GIR_RootConstrainSelectedInstOperands,
     /* 302459 */     // GIR_Coverage, 2222,
     /* 302459 */     GIR_EraseRootFromParent_Done,
     /* 302460 */   // Label 5886: @302460
     /* 302460 */   GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(302479), // Rule ID 1067 //
     /* 302465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302468 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302472 */     // (truncssat_s:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)  =>  (SQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
     /* 302472 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv4i16),
     /* 302477 */     GIR_RootConstrainSelectedInstOperands,
     /* 302478 */     // GIR_Coverage, 1067,
     /* 302478 */     GIR_Done,
     /* 302479 */   // Label 5887: @302479
     /* 302479 */   GIM_Reject,
     /* 302480 */ // Label 5884: @302480
     /* 302480 */ GIM_Reject,
     /* 302481 */ // Label 5878: @302481
     /* 302481 */ GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(302613),
     /* 302486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302493 */   GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(302543), // Rule ID 2201 //
     /* 302498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302513 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302518 */     // MIs[1] imm
     /* 302518 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302521 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 302526 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302528 */     // (truncssat_s:{ *:[v8i8] } (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRNv8i8_shift),
     /* 302531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302537 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302541 */     GIR_RootConstrainSelectedInstOperands,
     /* 302542 */     // GIR_Coverage, 2201,
     /* 302542 */     GIR_EraseRootFromParent_Done,
     /* 302543 */   // Label 5889: @302543
     /* 302543 */   GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(302593), // Rule ID 2221 //
     /* 302548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302568 */     // MIs[1] imm
     /* 302568 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302571 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 302576 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302578 */     // (truncssat_s:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302578 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRNv8i8_shift),
     /* 302581 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302591 */     GIR_RootConstrainSelectedInstOperands,
     /* 302592 */     // GIR_Coverage, 2221,
     /* 302592 */     GIR_EraseRootFromParent_Done,
     /* 302593 */   // Label 5890: @302593
     /* 302593 */   GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(302612), // Rule ID 1066 //
     /* 302598 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302601 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302605 */     // (truncssat_s:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)  =>  (SQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
     /* 302605 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTNv8i8),
     /* 302610 */     GIR_RootConstrainSelectedInstOperands,
     /* 302611 */     // GIR_Coverage, 1066,
     /* 302611 */     GIR_Done,
     /* 302612 */   // Label 5891: @302612
     /* 302612 */   GIM_Reject,
     /* 302613 */ // Label 5888: @302613
     /* 302613 */ GIM_Reject,
     /* 302614 */ // Label 5879: @302614
     /* 302614 */ GIM_Reject,
     /* 302615 */ // Label 48: @302615
     /* 302615 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(10), /*)*//*default:*//*Label 5895*/ GIMT_Encode4(303045),
     /* 302626 */ /*GILLT_v2s32*//*Label 5892*/ GIMT_Encode4(302646), GIMT_Encode4(0),
     /* 302634 */ /*GILLT_v4s16*//*Label 5893*/ GIMT_Encode4(302779), GIMT_Encode4(0),
     /* 302642 */ /*GILLT_v8s8*//*Label 5894*/ GIMT_Encode4(302912),
     /* 302646 */ // Label 5892: @302646
     /* 302646 */ GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(302778),
     /* 302651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302658 */   GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(302708), // Rule ID 2206 //
     /* 302663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302666 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302670 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302674 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302678 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302683 */     // MIs[1] imm
     /* 302683 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302686 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 302691 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302693 */     // (truncssat_u:{ *:[v2i32] } (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SQRSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv2i32_shift),
     /* 302696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302698 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302706 */     GIR_RootConstrainSelectedInstOperands,
     /* 302707 */     // GIR_Coverage, 2206,
     /* 302707 */     GIR_EraseRootFromParent_Done,
     /* 302708 */   // Label 5897: @302708
     /* 302708 */   GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(302758), // Rule ID 2226 //
     /* 302713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302724 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 302728 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302733 */     // MIs[1] imm
     /* 302733 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302736 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 302741 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302743 */     // (truncssat_u:{ *:[v2i32] } (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (SQSHRUNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv2i32_shift),
     /* 302746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302756 */     GIR_RootConstrainSelectedInstOperands,
     /* 302757 */     // GIR_Coverage, 2226,
     /* 302757 */     GIR_EraseRootFromParent_Done,
     /* 302758 */   // Label 5898: @302758
     /* 302758 */   GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(302777), // Rule ID 1071 //
     /* 302763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302766 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302770 */     // (truncssat_u:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)  =>  (SQXTUNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
     /* 302770 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv2i32),
     /* 302775 */     GIR_RootConstrainSelectedInstOperands,
     /* 302776 */     // GIR_Coverage, 1071,
     /* 302776 */     GIR_Done,
     /* 302777 */   // Label 5899: @302777
     /* 302777 */   GIM_Reject,
     /* 302778 */ // Label 5896: @302778
     /* 302778 */ GIM_Reject,
     /* 302779 */ // Label 5893: @302779
     /* 302779 */ GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(302911),
     /* 302784 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302791 */   GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(302841), // Rule ID 2205 //
     /* 302796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302811 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302816 */     // MIs[1] imm
     /* 302816 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302819 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 302824 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302826 */     // (truncssat_u:{ *:[v4i16] } (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SQRSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv4i16_shift),
     /* 302829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302839 */     GIR_RootConstrainSelectedInstOperands,
     /* 302840 */     // GIR_Coverage, 2205,
     /* 302840 */     GIR_EraseRootFromParent_Done,
     /* 302841 */   // Label 5901: @302841
     /* 302841 */   GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(302891), // Rule ID 2225 //
     /* 302846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 302861 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302866 */     // MIs[1] imm
     /* 302866 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302869 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 302874 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302876 */     // (truncssat_u:{ *:[v4i16] } (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (SQSHRUNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv4i16_shift),
     /* 302879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302881 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302885 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302889 */     GIR_RootConstrainSelectedInstOperands,
     /* 302890 */     // GIR_Coverage, 2225,
     /* 302890 */     GIR_EraseRootFromParent_Done,
     /* 302891 */   // Label 5902: @302891
     /* 302891 */   GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(302910), // Rule ID 1070 //
     /* 302896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302899 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302903 */     // (truncssat_u:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)  =>  (SQXTUNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
     /* 302903 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv4i16),
     /* 302908 */     GIR_RootConstrainSelectedInstOperands,
     /* 302909 */     // GIR_Coverage, 1070,
     /* 302909 */     GIR_Done,
     /* 302910 */   // Label 5903: @302910
     /* 302910 */   GIM_Reject,
     /* 302911 */ // Label 5900: @302911
     /* 302911 */ GIM_Reject,
     /* 302912 */ // Label 5894: @302912
     /* 302912 */ GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(303044),
     /* 302917 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302920 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 302924 */   GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(302974), // Rule ID 2204 //
     /* 302929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302936 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SRSHR_I),
     /* 302940 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302944 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302949 */     // MIs[1] imm
     /* 302949 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 302952 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 302957 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 302959 */     // (truncssat_u:{ *:[v8i8] } (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SQRSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 302959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQRSHRUNv8i8_shift),
     /* 302962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 302964 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 302968 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 302972 */     GIR_RootConstrainSelectedInstOperands,
     /* 302973 */     // GIR_Coverage, 2204,
     /* 302973 */     GIR_EraseRootFromParent_Done,
     /* 302974 */   // Label 5905: @302974
     /* 302974 */   GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(303024), // Rule ID 2224 //
     /* 302979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 302982 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 302986 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VASHR),
     /* 302990 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 302994 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 302999 */     // MIs[1] imm
     /* 302999 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303002 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 303007 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303009 */     // (truncssat_u:{ *:[v8i8] } (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (SQSHRUNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303009 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQSHRUNv8i8_shift),
     /* 303012 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303014 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303018 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303022 */     GIR_RootConstrainSelectedInstOperands,
     /* 303023 */     // GIR_Coverage, 2224,
     /* 303023 */     GIR_EraseRootFromParent_Done,
     /* 303024 */   // Label 5906: @303024
     /* 303024 */   GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(303043), // Rule ID 1069 //
     /* 303029 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303032 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303036 */     // (truncssat_u:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)  =>  (SQXTUNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
     /* 303036 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQXTUNv8i8),
     /* 303041 */     GIR_RootConstrainSelectedInstOperands,
     /* 303042 */     // GIR_Coverage, 1069,
     /* 303042 */     GIR_Done,
     /* 303043 */   // Label 5907: @303043
     /* 303043 */   GIM_Reject,
     /* 303044 */ // Label 5904: @303044
     /* 303044 */ GIM_Reject,
     /* 303045 */ // Label 5895: @303045
     /* 303045 */ GIM_Reject,
     /* 303046 */ // Label 49: @303046
     /* 303046 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(10), /*)*//*default:*//*Label 5911*/ GIMT_Encode4(303476),
     /* 303057 */ /*GILLT_v2s32*//*Label 5908*/ GIMT_Encode4(303077), GIMT_Encode4(0),
     /* 303065 */ /*GILLT_v4s16*//*Label 5909*/ GIMT_Encode4(303210), GIMT_Encode4(0),
     /* 303073 */ /*GILLT_v8s8*//*Label 5910*/ GIMT_Encode4(303343),
     /* 303077 */ // Label 5908: @303077
     /* 303077 */ GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(303209),
     /* 303082 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 303085 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303089 */   GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(303139), // Rule ID 2282 //
     /* 303094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 303105 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 303109 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303114 */     // MIs[1] imm
     /* 303114 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303117 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 303122 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303124 */     // (truncusat_u:{ *:[v2i32] } (AArch64urshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (UQRSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv2i32_shift),
     /* 303127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303129 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303133 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303137 */     GIR_RootConstrainSelectedInstOperands,
     /* 303138 */     // GIR_Coverage, 2282,
     /* 303138 */     GIR_EraseRootFromParent_Done,
     /* 303139 */   // Label 5913: @303139
     /* 303139 */   GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(303189), // Rule ID 2292 //
     /* 303144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 303155 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 303159 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303164 */     // MIs[1] imm
     /* 303164 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303167 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64Narrow),
     /* 303172 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303174 */     // (truncusat_u:{ *:[v2i32] } (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64Narrow>>:$imm))  =>  (UQSHRNv2i32_shift:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv2i32_shift),
     /* 303177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303179 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303187 */     GIR_RootConstrainSelectedInstOperands,
     /* 303188 */     // GIR_Coverage, 2292,
     /* 303188 */     GIR_EraseRootFromParent_Done,
     /* 303189 */   // Label 5914: @303189
     /* 303189 */   GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(303208), // Rule ID 1115 //
     /* 303194 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303197 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303201 */     // (truncusat_u:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)  =>  (UQXTNv2i32:{ *:[v2i32] } V128:{ *:[v2i64] }:$Rn)
     /* 303201 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv2i32),
     /* 303206 */     GIR_RootConstrainSelectedInstOperands,
     /* 303207 */     // GIR_Coverage, 1115,
     /* 303207 */     GIR_Done,
     /* 303208 */   // Label 5915: @303208
     /* 303208 */   GIM_Reject,
     /* 303209 */ // Label 5912: @303209
     /* 303209 */ GIM_Reject,
     /* 303210 */ // Label 5909: @303210
     /* 303210 */ GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(303342),
     /* 303215 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303218 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303222 */   GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(303272), // Rule ID 2281 //
     /* 303227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303230 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303234 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 303238 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303242 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303247 */     // MIs[1] imm
     /* 303247 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303250 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 303255 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303257 */     // (truncusat_u:{ *:[v4i16] } (AArch64urshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (UQRSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv4i16_shift),
     /* 303260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303262 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303270 */     GIR_RootConstrainSelectedInstOperands,
     /* 303271 */     // GIR_Coverage, 2281,
     /* 303271 */     GIR_EraseRootFromParent_Done,
     /* 303272 */   // Label 5917: @303272
     /* 303272 */   GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(303322), // Rule ID 2291 //
     /* 303277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 303288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 303292 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303297 */     // MIs[1] imm
     /* 303297 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303300 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32Narrow),
     /* 303305 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303307 */     // (truncusat_u:{ *:[v4i16] } (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32Narrow>>:$imm))  =>  (UQSHRNv4i16_shift:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv4i16_shift),
     /* 303310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303320 */     GIR_RootConstrainSelectedInstOperands,
     /* 303321 */     // GIR_Coverage, 2291,
     /* 303321 */     GIR_EraseRootFromParent_Done,
     /* 303322 */   // Label 5918: @303322
     /* 303322 */   GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(303341), // Rule ID 1114 //
     /* 303327 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303330 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303334 */     // (truncusat_u:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)  =>  (UQXTNv4i16:{ *:[v4i16] } V128:{ *:[v4i32] }:$Rn)
     /* 303334 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv4i16),
     /* 303339 */     GIR_RootConstrainSelectedInstOperands,
     /* 303340 */     // GIR_Coverage, 1114,
     /* 303340 */     GIR_Done,
     /* 303341 */   // Label 5919: @303341
     /* 303341 */   GIM_Reject,
     /* 303342 */ // Label 5916: @303342
     /* 303342 */ GIM_Reject,
     /* 303343 */ // Label 5910: @303343
     /* 303343 */ GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(303475),
     /* 303348 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 303351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303355 */   GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(303405), // Rule ID 2280 //
     /* 303360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303363 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303367 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_URSHR_I),
     /* 303371 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 303375 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303380 */     // MIs[1] imm
     /* 303380 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303383 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 303388 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303390 */     // (truncusat_u:{ *:[v8i8] } (AArch64urshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (UQRSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQRSHRNv8i8_shift),
     /* 303393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303403 */     GIR_RootConstrainSelectedInstOperands,
     /* 303404 */     // GIR_Coverage, 2280,
     /* 303404 */     GIR_EraseRootFromParent_Done,
     /* 303405 */   // Label 5921: @303405
     /* 303405 */   GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(303455), // Rule ID 2290 //
     /* 303410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_VLSHR),
     /* 303421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 303425 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303430 */     // MIs[1] imm
     /* 303430 */     GIM_CheckIsImm, /*MI*/1, /*Op*/2,
     /* 303433 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16Narrow),
     /* 303438 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303440 */     // (truncusat_u:{ *:[v8i8] } (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16Narrow>>:$imm))  =>  (UQSHRNv8i8_shift:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 303440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UQSHRNv8i8_shift),
     /* 303443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 303449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // imm
     /* 303453 */     GIR_RootConstrainSelectedInstOperands,
     /* 303454 */     // GIR_Coverage, 2290,
     /* 303454 */     GIR_EraseRootFromParent_Done,
     /* 303455 */   // Label 5922: @303455
     /* 303455 */   GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(303474), // Rule ID 1113 //
     /* 303460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303463 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303467 */     // (truncusat_u:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)  =>  (UQXTNv8i8:{ *:[v8i8] } V128:{ *:[v8i16] }:$Rn)
     /* 303467 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQXTNv8i8),
     /* 303472 */     GIR_RootConstrainSelectedInstOperands,
     /* 303473 */     // GIR_Coverage, 1113,
     /* 303473 */     GIR_Done,
     /* 303474 */   // Label 5923: @303474
     /* 303474 */   GIM_Reject,
     /* 303475 */ // Label 5920: @303475
     /* 303475 */ GIM_Reject,
     /* 303476 */ // Label 5911: @303476
     /* 303476 */ GIM_Reject,
     /* 303477 */ // Label 50: @303477
     /* 303477 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 5926*/ GIMT_Encode4(303596),
     /* 303488 */ /*GILLT_s32*//*Label 5924*/ GIMT_Encode4(303496),
     /* 303492 */ /*GILLT_s64*//*Label 5925*/ GIMT_Encode4(303516),
     /* 303496 */ // Label 5924: @303496
     /* 303496 */ GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(303515), // Rule ID 69 //
     /* 303501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 303505 */   // MIs[0] Operand 1
     /* 303505 */   // No operand predicates
     /* 303505 */   // (imm:{ *:[i32] }):$src  =>  (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
     /* 303505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /* 303508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 303510 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
     /* 303513 */   GIR_RootConstrainSelectedInstOperands,
     /* 303514 */   // GIR_Coverage, 69,
     /* 303514 */   GIR_EraseRootFromParent_Done,
     /* 303515 */ // Label 5927: @303515
     /* 303515 */ GIM_Reject,
     /* 303516 */ // Label 5925: @303516
     /* 303516 */ GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(303576), // Rule ID 3999 //
     /* 303521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_OptimizedGISelOrOtherSelector),
     /* 303524 */   GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i64imm_32bit),
     /* 303528 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 303532 */   // MIs[0] Operand 1
     /* 303532 */   // No operand predicates
     /* 303532 */   // (imm:{ *:[i64] })<<P:Predicate_i64imm_32bit>>:$src  =>  (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i64] }, (MOVi32imm:{ *:[i32] } (trunc_imm:{ *:[i32] } (imm:{ *:[i64] }):$src)), sub_32:{ *:[i32] })
     /* 303532 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 303535 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVi32imm),
     /* 303539 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 303544 */   GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // src
     /* 303549 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 303551 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 303554 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 303556 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 303559 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 303562 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/20,
     /* 303565 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 303570 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 303575 */   // GIR_Coverage, 3999,
     /* 303575 */   GIR_EraseRootFromParent_Done,
     /* 303576 */ // Label 5928: @303576
     /* 303576 */ GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(303595), // Rule ID 70 //
     /* 303581 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 303585 */   // MIs[0] Operand 1
     /* 303585 */   // No operand predicates
     /* 303585 */   // (imm:{ *:[i64] }):$src  =>  (MOVi64imm:{ *:[i64] } (imm:{ *:[i64] }):$src)
     /* 303585 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MOVi64imm),
     /* 303588 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 303590 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
     /* 303593 */   GIR_RootConstrainSelectedInstOperands,
     /* 303594 */   // GIR_Coverage, 70,
     /* 303594 */   GIR_EraseRootFromParent_Done,
     /* 303595 */ // Label 5929: @303595
     /* 303595 */ GIM_Reject,
     /* 303596 */ // Label 5926: @303596
     /* 303596 */ GIM_Reject,
     /* 303597 */ // Label 51: @303597
     /* 303597 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 5933*/ GIMT_Encode4(303837),
     /* 303608 */ /*GILLT_s16*//*Label 5930*/ GIMT_Encode4(303620),
     /* 303612 */ /*GILLT_s32*//*Label 5931*/ GIMT_Encode4(303672),
     /* 303616 */ /*GILLT_s64*//*Label 5932*/ GIMT_Encode4(303785),
     /* 303620 */ // Label 5930: @303620
     /* 303620 */ GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(303643), // Rule ID 548 //
     /* 303625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 303628 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 303632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 303636 */   // MIs[0] Operand 1
     /* 303636 */   // No operand predicates
     /* 303636 */   // (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>  =>  (FMOVH0:{ *:[f16] })
     /* 303636 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVH0),
     /* 303639 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303641 */   GIR_RootConstrainSelectedInstOperands,
     /* 303642 */   // GIR_Coverage, 548,
     /* 303642 */   GIR_EraseRootFromParent_Done,
     /* 303643 */ // Label 5934: @303643
     /* 303643 */ GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(303671), // Rule ID 730 //
     /* 303648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 303651 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 303655 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 303659 */   // MIs[0] Operand 1
     /* 303659 */   // No operand predicates
     /* 303659 */   // (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm  =>  (FMOVHi:{ *:[f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] }):$imm))
     /* 303659 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVHi),
     /* 303662 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303664 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm
     /* 303669 */   GIR_RootConstrainSelectedInstOperands,
     /* 303670 */   // GIR_Coverage, 730,
     /* 303670 */   GIR_EraseRootFromParent_Done,
     /* 303671 */ // Label 5935: @303671
     /* 303671 */ GIM_Reject,
     /* 303672 */ // Label 5931: @303672
     /* 303672 */ GIM_Try, /*On fail goto*//*Label 5936*/ GIMT_Encode4(303695), // Rule ID 549 //
     /* 303677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 303680 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 303684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 303688 */   // MIs[0] Operand 1
     /* 303688 */   // No operand predicates
     /* 303688 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>  =>  (FMOVS0:{ *:[f32] })
     /* 303688 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVS0),
     /* 303691 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303693 */   GIR_RootConstrainSelectedInstOperands,
     /* 303694 */   // GIR_Coverage, 549,
     /* 303694 */   GIR_EraseRootFromParent_Done,
     /* 303695 */ // Label 5936: @303695
     /* 303695 */ GIM_Try, /*On fail goto*//*Label 5937*/ GIMT_Encode4(303723), // Rule ID 731 //
     /* 303700 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 303703 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 303707 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 303711 */   // MIs[0] Operand 1
     /* 303711 */   // No operand predicates
     /* 303711 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm  =>  (FMOVSi:{ *:[f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
     /* 303711 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVSi),
     /* 303714 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303716 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm
     /* 303721 */   GIR_RootConstrainSelectedInstOperands,
     /* 303722 */   // GIR_Coverage, 731,
     /* 303722 */   GIR_EraseRootFromParent_Done,
     /* 303723 */ // Label 5937: @303723
     /* 303723 */ GIM_Try, /*On fail goto*//*Label 5938*/ GIMT_Encode4(303784), // Rule ID 6652 //
     /* 303728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 303731 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32SIMDModImmType4),
     /* 303735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 303739 */   // MIs[0] Operand 1
     /* 303739 */   // No operand predicates
     /* 303739 */   // (fpimm:{ *:[f32] })<<P:Predicate_fpimm32SIMDModImmType4>><<X:fpimm32SIMDModImmType4XForm>>:$in  =>  (EXTRACT_SUBREG:{ *:[f32] } (MOVIv2i32:{ *:[i64] } (fpimm32SIMDModImmType4XForm:{ *:[i32] } f32:{ *:[f32] }:$in), 24:{ *:[i32] }), ssub:{ *:[i32] })
     /* 303739 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 303742 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2i32),
     /* 303746 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 303751 */   GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32SIMDModImmType4), // in
     /* 303756 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/24,
     /* 303759 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 303761 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 303764 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 303766 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 303773 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 303778 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303783 */   // GIR_Coverage, 6652,
     /* 303783 */   GIR_EraseRootFromParent_Done,
     /* 303784 */ // Label 5938: @303784
     /* 303784 */ GIM_Reject,
     /* 303785 */ // Label 5932: @303785
     /* 303785 */ GIM_Try, /*On fail goto*//*Label 5939*/ GIMT_Encode4(303808), // Rule ID 550 //
     /* 303790 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 303793 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 303797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303801 */   // MIs[0] Operand 1
     /* 303801 */   // No operand predicates
     /* 303801 */   // (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>  =>  (FMOVD0:{ *:[f64] })
     /* 303801 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVD0),
     /* 303804 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303806 */   GIR_RootConstrainSelectedInstOperands,
     /* 303807 */   // GIR_Coverage, 550,
     /* 303807 */   GIR_EraseRootFromParent_Done,
     /* 303808 */ // Label 5939: @303808
     /* 303808 */ GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(303836), // Rule ID 732 //
     /* 303813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 303816 */   GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 303820 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303824 */   // MIs[0] Operand 1
     /* 303824 */   // No operand predicates
     /* 303824 */   // (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm  =>  (FMOVDi:{ *:[f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
     /* 303824 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMOVDi),
     /* 303827 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303829 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm
     /* 303834 */   GIR_RootConstrainSelectedInstOperands,
     /* 303835 */   // GIR_Coverage, 732,
     /* 303835 */   GIR_EraseRootFromParent_Done,
     /* 303836 */ // Label 5940: @303836
     /* 303836 */ GIM_Reject,
     /* 303837 */ // Label 5933: @303837
     /* 303837 */ GIM_Reject,
     /* 303838 */ // Label 52: @303838
     /* 303838 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 5946*/ GIMT_Encode4(305735),
     /* 303849 */ /*GILLT_s32*//*Label 5941*/ GIMT_Encode4(303885),
     /* 303853 */ /*GILLT_s64*//*Label 5942*/ GIMT_Encode4(305326), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 303865 */ /*GILLT_v2s64*//*Label 5943*/ GIMT_Encode4(305549), GIMT_Encode4(0),
     /* 303873 */ /*GILLT_v4s32*//*Label 5944*/ GIMT_Encode4(305611), GIMT_Encode4(0),
     /* 303881 */ /*GILLT_v8s16*//*Label 5945*/ GIMT_Encode4(305673),
     /* 303885 */ // Label 5941: @303885
     /* 303885 */ GIM_Try, /*On fail goto*//*Label 5947*/ GIMT_Encode4(304005), // Rule ID 14183 //
     /* 303890 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 303893 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 303897 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 303901 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 303905 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 303908 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 303913 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 303917 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 303922 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 303924 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 687:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 303924 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 303927 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 303931 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 303936 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 303940 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 303942 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 303945 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 303949 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 303954 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 303956 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 303959 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 303963 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 303968 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 303971 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 303974 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 303977 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303982 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 303987 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 303992 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 303995 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 303997 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304003 */   GIR_RootConstrainSelectedInstOperands,
     /* 304004 */   // GIR_Coverage, 14183,
     /* 304004 */   GIR_EraseRootFromParent_Done,
     /* 304005 */ // Label 5947: @304005
     /* 304005 */ GIM_Try, /*On fail goto*//*Label 5948*/ GIMT_Encode4(304125), // Rule ID 14185 //
     /* 304010 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 304013 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304017 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304021 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304025 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304028 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 304033 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 304037 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304042 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304044 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 687:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304044 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 304047 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 304051 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304056 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304060 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304062 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304065 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304069 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304074 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304076 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304079 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304083 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304088 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304091 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304094 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 304097 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304102 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304107 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 304112 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 304115 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304117 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304120 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304123 */   GIR_RootConstrainSelectedInstOperands,
     /* 304124 */   // GIR_Coverage, 14185,
     /* 304124 */   GIR_EraseRootFromParent_Done,
     /* 304125 */ // Label 5948: @304125
     /* 304125 */ GIM_Try, /*On fail goto*//*Label 5949*/ GIMT_Encode4(304245), // Rule ID 14187 //
     /* 304130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 304133 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304137 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304141 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304145 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304148 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 304153 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304157 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304162 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304164 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 687:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304164 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 304167 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 304171 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304176 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304180 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304182 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304185 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304189 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304194 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304196 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304199 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304203 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304208 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304211 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304214 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 304217 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304222 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304227 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 304232 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 304235 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304237 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304240 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304243 */   GIR_RootConstrainSelectedInstOperands,
     /* 304244 */   // GIR_Coverage, 14187,
     /* 304244 */   GIR_EraseRootFromParent_Done,
     /* 304245 */ // Label 5949: @304245
     /* 304245 */ GIM_Try, /*On fail goto*//*Label 5950*/ GIMT_Encode4(304365), // Rule ID 14189 //
     /* 304250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 304253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304257 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304261 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304265 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304268 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddv),
     /* 304273 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 304277 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304282 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304284 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 687:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304284 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 304287 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 304291 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304296 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304300 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304302 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304305 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304309 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304314 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304316 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304319 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304323 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304328 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304331 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304334 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 304337 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304342 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304347 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 304352 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 304355 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304357 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304360 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304363 */   GIR_RootConstrainSelectedInstOperands,
     /* 304364 */   // GIR_Coverage, 14189,
     /* 304364 */   GIR_EraseRootFromParent_Done,
     /* 304365 */ // Label 5950: @304365
     /* 304365 */ GIM_Try, /*On fail goto*//*Label 5951*/ GIMT_Encode4(304485), // Rule ID 14205 //
     /* 304370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 304373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304377 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304381 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304385 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304388 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 304393 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 304397 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304402 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304404 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 697:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304404 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 304407 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 304411 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304416 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304420 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304422 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304425 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304429 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304434 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304436 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304439 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304443 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304448 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304451 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304454 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 304457 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304462 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304467 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 304472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 304475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304477 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304480 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304483 */   GIR_RootConstrainSelectedInstOperands,
     /* 304484 */   // GIR_Coverage, 14205,
     /* 304484 */   GIR_EraseRootFromParent_Done,
     /* 304485 */ // Label 5951: @304485
     /* 304485 */ GIM_Try, /*On fail goto*//*Label 5952*/ GIMT_Encode4(304605), // Rule ID 14207 //
     /* 304490 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 304493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304497 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304501 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304505 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304508 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 304513 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 304517 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304522 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304524 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 697:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304524 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 304527 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 304531 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304536 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304540 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304542 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304545 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304549 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304554 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304556 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304559 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304563 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304568 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304571 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304574 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 304577 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304582 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304587 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 304592 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 304595 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304597 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304600 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304603 */   GIR_RootConstrainSelectedInstOperands,
     /* 304604 */   // GIR_Coverage, 14207,
     /* 304604 */   GIR_EraseRootFromParent_Done,
     /* 304605 */ // Label 5952: @304605
     /* 304605 */ GIM_Try, /*On fail goto*//*Label 5953*/ GIMT_Encode4(304725), // Rule ID 14209 //
     /* 304610 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 304613 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304617 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304621 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304625 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304628 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 304633 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 304637 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304642 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304644 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 697:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304644 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 304647 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 304651 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304656 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304660 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304662 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304665 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304669 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304674 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304676 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304679 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304683 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304688 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304691 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304694 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 304697 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304702 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304707 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 304712 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 304715 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304717 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304720 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304723 */   GIR_RootConstrainSelectedInstOperands,
     /* 304724 */   // GIR_Coverage, 14209,
     /* 304724 */   GIR_EraseRootFromParent_Done,
     /* 304725 */ // Label 5953: @304725
     /* 304725 */ GIM_Try, /*On fail goto*//*Label 5954*/ GIMT_Encode4(304845), // Rule ID 14211 //
     /* 304730 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 304733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304737 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304741 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304745 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304748 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_smaxv),
     /* 304753 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 304757 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304762 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304764 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 697:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304764 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 304767 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 304771 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304776 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304780 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304782 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304785 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304789 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304794 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304796 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304799 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304803 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304808 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304811 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304814 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 304817 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304822 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304827 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 304832 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 304835 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304837 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304840 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304843 */   GIR_RootConstrainSelectedInstOperands,
     /* 304844 */   // GIR_Coverage, 14211,
     /* 304844 */   GIR_EraseRootFromParent_Done,
     /* 304845 */ // Label 5954: @304845
     /* 304845 */ GIM_Try, /*On fail goto*//*Label 5955*/ GIMT_Encode4(304965), // Rule ID 14215 //
     /* 304850 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 304853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304857 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304861 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304865 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304868 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 304873 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 304877 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 304882 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 304884 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 700:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 304884 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 304887 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 304891 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304896 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 304900 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 304902 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 304905 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 304909 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304914 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 304916 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 304919 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 304923 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 304928 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 304931 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 304934 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 304937 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304942 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 304947 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 304952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 304955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 304957 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 304960 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 304963 */   GIR_RootConstrainSelectedInstOperands,
     /* 304964 */   // GIR_Coverage, 14215,
     /* 304964 */   GIR_EraseRootFromParent_Done,
     /* 304965 */ // Label 5955: @304965
     /* 304965 */ GIM_Try, /*On fail goto*//*Label 5956*/ GIMT_Encode4(305085), // Rule ID 14217 //
     /* 304970 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 304973 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 304977 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 304981 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 304985 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 304988 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 304993 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 304997 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305002 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 305004 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 700:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SMOVvi8to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 305004 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 305007 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 305011 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305016 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 305020 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 305022 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 305025 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 305029 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305034 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 305036 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 305039 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 305043 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305048 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 305051 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 305054 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 305057 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305062 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305067 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 305072 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 305075 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305077 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305080 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305083 */   GIR_RootConstrainSelectedInstOperands,
     /* 305084 */   // GIR_Coverage, 14217,
     /* 305084 */   GIR_EraseRootFromParent_Done,
     /* 305085 */ // Label 5956: @305085
     /* 305085 */ GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(305205), // Rule ID 14219 //
     /* 305090 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 305093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 305097 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305101 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 305105 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 305108 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 305113 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 305117 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305122 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 305124 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 700:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 305124 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 305127 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 305131 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305136 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 305140 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 305142 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 305145 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 305149 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305154 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 305156 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 305159 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 305163 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305168 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 305171 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 305174 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 305177 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305182 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305187 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 305192 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 305195 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305197 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305200 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305203 */   GIR_RootConstrainSelectedInstOperands,
     /* 305204 */   // GIR_Coverage, 14219,
     /* 305204 */   GIR_EraseRootFromParent_Done,
     /* 305205 */ // Label 5957: @305205
     /* 305205 */ GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(305325), // Rule ID 14221 //
     /* 305210 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 305213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 305217 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305221 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 305225 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 305228 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sminv),
     /* 305233 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 305237 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305242 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 305244 */   // (sext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 700:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SMOVvi16to32:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (SMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 305244 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 305247 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 305251 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305256 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 305260 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 305262 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 305265 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 305269 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305274 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 305276 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 305279 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 305283 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305288 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 305291 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 305294 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 305297 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305302 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305307 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 305312 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 305315 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305317 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305320 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305323 */   GIR_RootConstrainSelectedInstOperands,
     /* 305324 */   // GIR_Coverage, 14221,
     /* 305324 */   GIR_EraseRootFromParent_Done,
     /* 305325 */ // Label 5958: @305325
     /* 305325 */ GIM_Reject,
     /* 305326 */ // Label 5942: @305326
     /* 305326 */ GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(305548),
     /* 305331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 305334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 305338 */   GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(305392), // Rule ID 6258 //
     /* 305343 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305347 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305351 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 305355 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305359 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305364 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 305368 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 305372 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 305376 */     // MIs[2] Operand 1
     /* 305376 */     // No operand predicates
     /* 305376 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305378 */     // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SMOVvi32to64:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 305378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
     /* 305381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305387 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 305390 */     GIR_RootConstrainSelectedInstOperands,
     /* 305391 */     // GIR_Coverage, 6258,
     /* 305391 */     GIR_EraseRootFromParent_Done,
     /* 305392 */   // Label 5960: @305392
     /* 305392 */   GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(305471), // Rule ID 12018 //
     /* 305397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 305400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305408 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 305412 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 305420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 305424 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 305428 */     // MIs[2] Operand 1
     /* 305428 */     // No operand predicates
     /* 305428 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305430 */     // (sext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index))  =>  (SMOVvi32to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
     /* 305430 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 305433 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 305437 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305442 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 305448 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305453 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 305458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi32to64),
     /* 305461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305463 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305466 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 305469 */     GIR_RootConstrainSelectedInstOperands,
     /* 305470 */     // GIR_Coverage, 12018,
     /* 305470 */     GIR_EraseRootFromParent_Done,
     /* 305471 */   // Label 5961: @305471
     /* 305471 */   GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(305547), // Rule ID 7144 //
     /* 305476 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 305480 */     // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i64] }, 31:{ *:[i64] })
     /* 305480 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 305483 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 305487 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305492 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 305494 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 305497 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 305501 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 305506 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 305509 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 305513 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 305516 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 305521 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 305526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 305531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 305534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305536 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 305539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 305545 */     GIR_RootConstrainSelectedInstOperands,
     /* 305546 */     // GIR_Coverage, 7144,
     /* 305546 */     GIR_EraseRootFromParent_Done,
     /* 305547 */   // Label 5962: @305547
     /* 305547 */   GIM_Reject,
     /* 305548 */ // Label 5959: @305548
     /* 305548 */ GIM_Reject,
     /* 305549 */ // Label 5943: @305549
     /* 305549 */ GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(305610),
     /* 305554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 305557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305561 */   GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(305588), // Rule ID 7006 //
     /* 305566 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 305573 */     // (sext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (SSHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 305573 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i32_shift),
     /* 305576 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 305583 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305586 */     GIR_RootConstrainSelectedInstOperands,
     /* 305587 */     // GIR_Coverage, 7006,
     /* 305587 */     GIR_EraseRootFromParent_Done,
     /* 305588 */   // Label 5964: @305588
     /* 305588 */   GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(305609), // Rule ID 6995 //
     /* 305593 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305597 */     // (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 305597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 305600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305602 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 305604 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305607 */     GIR_RootConstrainSelectedInstOperands,
     /* 305608 */     // GIR_Coverage, 6995,
     /* 305608 */     GIR_EraseRootFromParent_Done,
     /* 305609 */   // Label 5965: @305609
     /* 305609 */   GIM_Reject,
     /* 305610 */ // Label 5963: @305610
     /* 305610 */ GIM_Reject,
     /* 305611 */ // Label 5944: @305611
     /* 305611 */ GIM_Try, /*On fail goto*//*Label 5966*/ GIMT_Encode4(305672),
     /* 305616 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 305619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305623 */   GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(305650), // Rule ID 7003 //
     /* 305628 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 305635 */     // (sext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (SSHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 305635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i16_shift),
     /* 305638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305640 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 305645 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305648 */     GIR_RootConstrainSelectedInstOperands,
     /* 305649 */     // GIR_Coverage, 7003,
     /* 305649 */     GIR_EraseRootFromParent_Done,
     /* 305650 */   // Label 5967: @305650
     /* 305650 */   GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(305671), // Rule ID 6992 //
     /* 305655 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305659 */     // (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 305659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 305662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305664 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 305666 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305669 */     GIR_RootConstrainSelectedInstOperands,
     /* 305670 */     // GIR_Coverage, 6992,
     /* 305670 */     GIR_EraseRootFromParent_Done,
     /* 305671 */   // Label 5968: @305671
     /* 305671 */   GIM_Reject,
     /* 305672 */ // Label 5966: @305672
     /* 305672 */ GIM_Reject,
     /* 305673 */ // Label 5945: @305673
     /* 305673 */ GIM_Try, /*On fail goto*//*Label 5969*/ GIMT_Encode4(305734),
     /* 305678 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 305681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305685 */   GIM_Try, /*On fail goto*//*Label 5970*/ GIMT_Encode4(305712), // Rule ID 7000 //
     /* 305690 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 305697 */     // (sext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (SSHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 305697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv16i8_shift),
     /* 305700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305702 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 305707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305710 */     GIR_RootConstrainSelectedInstOperands,
     /* 305711 */     // GIR_Coverage, 7000,
     /* 305711 */     GIR_EraseRootFromParent_Done,
     /* 305712 */   // Label 5970: @305712
     /* 305712 */   GIM_Try, /*On fail goto*//*Label 5971*/ GIMT_Encode4(305733), // Rule ID 6989 //
     /* 305717 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 305721 */     // (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 305721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 305724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305726 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 305728 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 305731 */     GIR_RootConstrainSelectedInstOperands,
     /* 305732 */     // GIR_Coverage, 6989,
     /* 305732 */     GIR_EraseRootFromParent_Done,
     /* 305733 */   // Label 5971: @305733
     /* 305733 */   GIM_Reject,
     /* 305734 */ // Label 5969: @305734
     /* 305734 */ GIM_Reject,
     /* 305735 */ // Label 5946: @305735
     /* 305735 */ GIM_Reject,
     /* 305736 */ // Label 53: @305736
     /* 305736 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(22), /*)*//*default:*//*Label 5977*/ GIMT_Encode4(307389),
     /* 305747 */ /*GILLT_s32*//*Label 5972*/ GIMT_Encode4(305827),
     /* 305751 */ /*GILLT_s64*//*Label 5973*/ GIMT_Encode4(306321), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 305803 */ /*GILLT_nxv2s64*//*Label 5974*/ GIMT_Encode4(306963), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 305815 */ /*GILLT_nxv4s32*//*Label 5975*/ GIMT_Encode4(307172), GIMT_Encode4(0),
     /* 305823 */ /*GILLT_nxv8s16*//*Label 5976*/ GIMT_Encode4(307316),
     /* 305827 */ // Label 5972: @305827
     /* 305827 */ GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(306320),
     /* 305832 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 305835 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 305839 */   GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(305904), // Rule ID 6253 //
     /* 305844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305848 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305852 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 305856 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305860 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305865 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 305869 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 305873 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 305877 */     // MIs[2] Operand 1
     /* 305877 */     // No operand predicates
     /* 305877 */     // MIs[0] Operand 2
     /* 305877 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 305888 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305890 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), i8:{ *:[Other] })  =>  (SMOVvi8to32:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 305890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 305893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305899 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 305902 */     GIR_RootConstrainSelectedInstOperands,
     /* 305903 */     // GIR_Coverage, 6253,
     /* 305903 */     GIR_EraseRootFromParent_Done,
     /* 305904 */   // Label 5979: @305904
     /* 305904 */   GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(305969), // Rule ID 6255 //
     /* 305909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305917 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 305921 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305925 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305930 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 305934 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 305938 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 305942 */     // MIs[2] Operand 1
     /* 305942 */     // No operand predicates
     /* 305942 */     // MIs[0] Operand 2
     /* 305942 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 305953 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 305955 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 305955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 305958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 305960 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 305964 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 305967 */     GIR_RootConstrainSelectedInstOperands,
     /* 305968 */     // GIR_Coverage, 6255,
     /* 305968 */     GIR_EraseRootFromParent_Done,
     /* 305969 */   // Label 5980: @305969
     /* 305969 */   GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(306034), // Rule ID 6257 //
     /* 305974 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 305978 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 305982 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 305986 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 305990 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 305995 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 305999 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306003 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 306007 */     // MIs[2] Operand 1
     /* 306007 */     // No operand predicates
     /* 306007 */     // MIs[0] Operand 2
     /* 306007 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306018 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306020 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 306020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 306023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306029 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 306032 */     GIR_RootConstrainSelectedInstOperands,
     /* 306033 */     // GIR_Coverage, 6257,
     /* 306033 */     GIR_EraseRootFromParent_Done,
     /* 306034 */   // Label 5981: @306034
     /* 306034 */   GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(306124), // Rule ID 12014 //
     /* 306039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 306054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 306058 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 306062 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306066 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 306070 */     // MIs[2] Operand 1
     /* 306070 */     // No operand predicates
     /* 306070 */     // MIs[0] Operand 2
     /* 306070 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306081 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306083 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index), i8:{ *:[Other] })  =>  (SMOVvi8to32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 306083 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 306086 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306090 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306095 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 306101 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306106 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to32),
     /* 306114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306116 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 306119 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 306122 */     GIR_RootConstrainSelectedInstOperands,
     /* 306123 */     // GIR_Coverage, 12014,
     /* 306123 */     GIR_EraseRootFromParent_Done,
     /* 306124 */   // Label 5982: @306124
     /* 306124 */   GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(306214), // Rule ID 12016 //
     /* 306129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306140 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 306144 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 306148 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 306152 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306156 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 306160 */     // MIs[2] Operand 1
     /* 306160 */     // No operand predicates
     /* 306160 */     // MIs[0] Operand 2
     /* 306160 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306171 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306173 */     // (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index), i16:{ *:[Other] })  =>  (SMOVvi16to32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 306173 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 306176 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306180 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306185 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 306191 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306196 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to32),
     /* 306204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306206 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 306209 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 306212 */     GIR_RootConstrainSelectedInstOperands,
     /* 306213 */     // GIR_Coverage, 12016,
     /* 306213 */     GIR_EraseRootFromParent_Done,
     /* 306214 */   // Label 5983: @306214
     /* 306214 */   GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(306249), // Rule ID 7149 //
     /* 306219 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 306223 */     // MIs[0] Operand 2
     /* 306223 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306234 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i16:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 15:{ *:[i64] })
     /* 306234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 306237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306239 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306244 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 306247 */     GIR_RootConstrainSelectedInstOperands,
     /* 306248 */     // GIR_Coverage, 7149,
     /* 306248 */     GIR_EraseRootFromParent_Done,
     /* 306249 */   // Label 5984: @306249
     /* 306249 */   GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(306284), // Rule ID 7150 //
     /* 306254 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 306258 */     // MIs[0] Operand 2
     /* 306258 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306269 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i8:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 7:{ *:[i64] })
     /* 306269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 306272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306274 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306279 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 306282 */     GIR_RootConstrainSelectedInstOperands,
     /* 306283 */     // GIR_Coverage, 7150,
     /* 306283 */     GIR_EraseRootFromParent_Done,
     /* 306284 */   // Label 5985: @306284
     /* 306284 */   GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(306319), // Rule ID 7151 //
     /* 306289 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 306293 */     // MIs[0] Operand 2
     /* 306293 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 306304 */     // (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$src, i1:{ *:[Other] })  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$src, 0:{ *:[i64] }, 0:{ *:[i64] })
     /* 306304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 306307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306309 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306311 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306314 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306317 */     GIR_RootConstrainSelectedInstOperands,
     /* 306318 */     // GIR_Coverage, 7151,
     /* 306318 */     GIR_EraseRootFromParent_Done,
     /* 306319 */   // Label 5986: @306319
     /* 306319 */   GIM_Reject,
     /* 306320 */ // Label 5978: @306320
     /* 306320 */ GIM_Reject,
     /* 306321 */ // Label 5973: @306321
     /* 306321 */ GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(306962),
     /* 306326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 306329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 306333 */   GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(306410), // Rule ID 6259 //
     /* 306338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 306346 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 306350 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 306354 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306358 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 306362 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 306366 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306371 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 306375 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306379 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 306383 */     // MIs[3] Operand 1
     /* 306383 */     // No operand predicates
     /* 306383 */     // MIs[0] Operand 2
     /* 306383 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306394 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 306396 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 306396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 306399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306401 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 306405 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 306408 */     GIR_RootConstrainSelectedInstOperands,
     /* 306409 */     // GIR_Coverage, 6259,
     /* 306409 */     GIR_EraseRootFromParent_Done,
     /* 306410 */   // Label 5988: @306410
     /* 306410 */   GIM_Try, /*On fail goto*//*Label 5989*/ GIMT_Encode4(306487), // Rule ID 6260 //
     /* 306415 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306419 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 306423 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 306427 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 306431 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306435 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 306439 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 306443 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306448 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 306452 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306456 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 306460 */     // MIs[3] Operand 1
     /* 306460 */     // No operand predicates
     /* 306460 */     // MIs[0] Operand 2
     /* 306460 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306471 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 306473 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 306473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 306476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 306482 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 306485 */     GIR_RootConstrainSelectedInstOperands,
     /* 306486 */     // GIR_Coverage, 6260,
     /* 306486 */     GIR_EraseRootFromParent_Done,
     /* 306487 */   // Label 5989: @306487
     /* 306487 */   GIM_Try, /*On fail goto*//*Label 5990*/ GIMT_Encode4(306589), // Rule ID 12015 //
     /* 306492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 306503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 306507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 306511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 306519 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 306523 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 306527 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306531 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 306535 */     // MIs[3] Operand 1
     /* 306535 */     // No operand predicates
     /* 306535 */     // MIs[0] Operand 2
     /* 306535 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306546 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 306548 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 306548 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 306551 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306555 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306560 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 306566 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306571 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 306579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306581 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 306584 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // index
     /* 306587 */     GIR_RootConstrainSelectedInstOperands,
     /* 306588 */     // GIR_Coverage, 12015,
     /* 306588 */     GIR_EraseRootFromParent_Done,
     /* 306589 */   // Label 5990: @306589
     /* 306589 */   GIM_Try, /*On fail goto*//*Label 5991*/ GIMT_Encode4(306691), // Rule ID 12017 //
     /* 306594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 306597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 306605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 306609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 306613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306617 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 306621 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 306625 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 306629 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306633 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 306637 */     // MIs[3] Operand 1
     /* 306637 */     // No operand predicates
     /* 306637 */     // MIs[0] Operand 2
     /* 306637 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306648 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 306650 */     // (sext_inreg:{ *:[i64] } (anyext:{ *:[i64] } (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 306650 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 306653 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 306657 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 306662 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 306668 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306673 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 306681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306683 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 306686 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // index
     /* 306689 */     GIR_RootConstrainSelectedInstOperands,
     /* 306690 */     // GIR_Coverage, 12017,
     /* 306690 */     GIR_EraseRootFromParent_Done,
     /* 306691 */   // Label 5991: @306691
     /* 306691 */   GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(306756), // Rule ID 6254 //
     /* 306696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 306708 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 306712 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306717 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 306721 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306725 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 306729 */     // MIs[2] Operand 1
     /* 306729 */     // No operand predicates
     /* 306729 */     // MIs[0] Operand 2
     /* 306729 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306740 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306742 */     // (sext_inreg:{ *:[i64] } (vector_extract:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx), i8:{ *:[Other] })  =>  (SMOVvi8to64:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)
     /* 306742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi8to64),
     /* 306745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306751 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 306754 */     GIR_RootConstrainSelectedInstOperands,
     /* 306755 */     // GIR_Coverage, 6254,
     /* 306755 */     GIR_EraseRootFromParent_Done,
     /* 306756 */   // Label 5992: @306756
     /* 306756 */   GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(306821), // Rule ID 6256 //
     /* 306761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 306765 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 306769 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 306773 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 306777 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 306782 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 306786 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 306790 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 306794 */     // MIs[2] Operand 1
     /* 306794 */     // No operand predicates
     /* 306794 */     // MIs[0] Operand 2
     /* 306794 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306805 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 306807 */     // (sext_inreg:{ *:[i64] } (vector_extract:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), i16:{ *:[Other] })  =>  (SMOVvi16to64:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 306807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMOVvi16to64),
     /* 306810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306812 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 306816 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 306819 */     GIR_RootConstrainSelectedInstOperands,
     /* 306820 */     // GIR_Coverage, 6256,
     /* 306820 */     GIR_EraseRootFromParent_Done,
     /* 306821 */   // Label 5993: @306821
     /* 306821 */   GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(306856), // Rule ID 7145 //
     /* 306826 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 306830 */     // MIs[0] Operand 2
     /* 306830 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
     /* 306841 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 31:{ *:[i64] })
     /* 306841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 306844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306846 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306848 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306851 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 306854 */     GIR_RootConstrainSelectedInstOperands,
     /* 306855 */     // GIR_Coverage, 7145,
     /* 306855 */     GIR_EraseRootFromParent_Done,
     /* 306856 */   // Label 5994: @306856
     /* 306856 */   GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(306891), // Rule ID 7146 //
     /* 306861 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 306865 */     // MIs[0] Operand 2
     /* 306865 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 306876 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i16:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 15:{ *:[i64] })
     /* 306876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 306879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306881 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306886 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 306889 */     GIR_RootConstrainSelectedInstOperands,
     /* 306890 */     // GIR_Coverage, 7146,
     /* 306890 */     GIR_EraseRootFromParent_Done,
     /* 306891 */   // Label 5995: @306891
     /* 306891 */   GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(306926), // Rule ID 7147 //
     /* 306896 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 306900 */     // MIs[0] Operand 2
     /* 306900 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 306911 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i8:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 7:{ *:[i64] })
     /* 306911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 306914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306916 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306918 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306921 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 306924 */     GIR_RootConstrainSelectedInstOperands,
     /* 306925 */     // GIR_Coverage, 7147,
     /* 306925 */     GIR_EraseRootFromParent_Done,
     /* 306926 */   // Label 5996: @306926
     /* 306926 */   GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(306961), // Rule ID 7148 //
     /* 306931 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 306935 */     // MIs[0] Operand 2
     /* 306935 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 306946 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i1:{ *:[Other] })  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$src, 0:{ *:[i64] }, 0:{ *:[i64] })
     /* 306946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 306949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 306951 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 306953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306956 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 306959 */     GIR_RootConstrainSelectedInstOperands,
     /* 306960 */     // GIR_Coverage, 7148,
     /* 306960 */     GIR_EraseRootFromParent_Done,
     /* 306961 */   // Label 5997: @306961
     /* 306961 */   GIM_Reject,
     /* 306962 */ // Label 5987: @306962
     /* 306962 */ GIM_Reject,
     /* 306963 */ // Label 5974: @306963
     /* 306963 */ GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(307171),
     /* 306968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 306971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 306975 */   GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(307040), // Rule ID 11244 //
     /* 306980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 306983 */     // MIs[0] Operand 2
     /* 306983 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
     /* 306994 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i32:{ *:[Other] })  =>  (SXTW_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 306994 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 306997 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 307001 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307006 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307009 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307011 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307014 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307018 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307023 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTW_ZPmZ_D_UNDEF),
     /* 307028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307030 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307033 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307038 */     GIR_RootConstrainSelectedInstOperands,
     /* 307039 */     // GIR_Coverage, 11244,
     /* 307039 */     GIR_EraseRootFromParent_Done,
     /* 307040 */   // Label 5999: @307040
     /* 307040 */   GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(307105), // Rule ID 11245 //
     /* 307045 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307048 */     // MIs[0] Operand 2
     /* 307048 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 307059 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i16:{ *:[Other] })  =>  (SXTH_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 307059 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 307062 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 307066 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307071 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307074 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307076 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307079 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307083 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307088 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTH_ZPmZ_D_UNDEF),
     /* 307093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307095 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307101 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307103 */     GIR_RootConstrainSelectedInstOperands,
     /* 307104 */     // GIR_Coverage, 11245,
     /* 307104 */     GIR_EraseRootFromParent_Done,
     /* 307105 */   // Label 6000: @307105
     /* 307105 */   GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(307170), // Rule ID 11246 //
     /* 307110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307113 */     // MIs[0] Operand 2
     /* 307113 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 307124 */     // (sext_inreg:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, nxv2i8:{ *:[Other] })  =>  (SXTB_ZPmZ_D_UNDEF:{ *:[nxv2i64] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv2i64] }:$Zs)
     /* 307124 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 307127 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 307131 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307136 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307139 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307141 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307144 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307148 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307153 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_D_UNDEF),
     /* 307158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307160 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307163 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307166 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307168 */     GIR_RootConstrainSelectedInstOperands,
     /* 307169 */     // GIR_Coverage, 11246,
     /* 307169 */     GIR_EraseRootFromParent_Done,
     /* 307170 */   // Label 6001: @307170
     /* 307170 */   GIM_Reject,
     /* 307171 */ // Label 5998: @307171
     /* 307171 */ GIM_Reject,
     /* 307172 */ // Label 5975: @307172
     /* 307172 */ GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(307315),
     /* 307177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 307180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 307184 */   GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(307249), // Rule ID 11247 //
     /* 307189 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307192 */     // MIs[0] Operand 2
     /* 307192 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 307203 */     // (sext_inreg:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, nxv4i16:{ *:[Other] })  =>  (SXTH_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv4i32] }:$Zs)
     /* 307203 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 307206 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 307210 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307215 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307218 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307220 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307223 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307227 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307232 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307234 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTH_ZPmZ_S_UNDEF),
     /* 307237 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307239 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307242 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307245 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307247 */     GIR_RootConstrainSelectedInstOperands,
     /* 307248 */     // GIR_Coverage, 11247,
     /* 307248 */     GIR_EraseRootFromParent_Done,
     /* 307249 */   // Label 6003: @307249
     /* 307249 */   GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(307314), // Rule ID 11248 //
     /* 307254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307257 */     // MIs[0] Operand 2
     /* 307257 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 307268 */     // (sext_inreg:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, nxv4i8:{ *:[Other] })  =>  (SXTB_ZPmZ_S_UNDEF:{ *:[nxv4i32] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv4i32] }:$Zs)
     /* 307268 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 307271 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 307275 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307280 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307283 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307285 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307288 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307292 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307297 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307299 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_S_UNDEF),
     /* 307302 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307304 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307307 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307310 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307312 */     GIR_RootConstrainSelectedInstOperands,
     /* 307313 */     // GIR_Coverage, 11248,
     /* 307313 */     GIR_EraseRootFromParent_Done,
     /* 307314 */   // Label 6004: @307314
     /* 307314 */   GIM_Reject,
     /* 307315 */ // Label 6002: @307315
     /* 307315 */ GIM_Reject,
     /* 307316 */ // Label 5976: @307316
     /* 307316 */ GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(307388), // Rule ID 11249 //
     /* 307321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 307324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 307327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 307331 */   // MIs[0] Operand 2
     /* 307331 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 307342 */   // (sext_inreg:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Zs, nxv8i8:{ *:[Other] })  =>  (SXTB_ZPmZ_H_UNDEF:{ *:[nxv8i16] } (IMPLICIT_DEF:{ *:[nxv16i8] }), (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), ZPR:{ *:[nxv8i16] }:$Zs)
     /* 307342 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 307345 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 307349 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307354 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 307357 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 307359 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 307362 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307366 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307371 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 307373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SXTB_ZPmZ_H_UNDEF),
     /* 307376 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 307378 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307381 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 307384 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 307386 */   GIR_RootConstrainSelectedInstOperands,
     /* 307387 */   // GIR_Coverage, 11249,
     /* 307387 */   GIR_EraseRootFromParent_Done,
     /* 307388 */ // Label 6005: @307388
     /* 307388 */ GIM_Reject,
     /* 307389 */ // Label 5977: @307389
     /* 307389 */ GIM_Reject,
     /* 307390 */ // Label 54: @307390
     /* 307390 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6010*/ GIMT_Encode4(310072),
     /* 307401 */ /*GILLT_s32*//*Label 6006*/ GIMT_Encode4(307437), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 307417 */ /*GILLT_v2s64*//*Label 6007*/ GIMT_Encode4(309238), GIMT_Encode4(0),
     /* 307425 */ /*GILLT_v4s32*//*Label 6008*/ GIMT_Encode4(309516), GIMT_Encode4(0),
     /* 307433 */ /*GILLT_v8s16*//*Label 6009*/ GIMT_Encode4(309794),
     /* 307437 */ // Label 6006: @307437
     /* 307437 */ GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(307587), // Rule ID 14192 //
     /* 307442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 307445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307449 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307453 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 307457 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 307460 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 307465 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 307469 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307474 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307476 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 752:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 307476 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 307479 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 307483 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307488 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 307492 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 307494 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 307497 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307501 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307506 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 307508 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 307511 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 307515 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307520 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 307523 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 307526 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 307529 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307534 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307539 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 307544 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 307547 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307551 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307556 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 307563 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 307568 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307576 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 307578 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307581 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307586 */   // GIR_Coverage, 14192,
     /* 307586 */   GIR_EraseRootFromParent_Done,
     /* 307587 */ // Label 6011: @307587
     /* 307587 */ GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(307737), // Rule ID 14194 //
     /* 307592 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 307595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307599 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307603 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 307607 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 307610 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 307615 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 307619 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307624 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307626 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 752:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 307626 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 307629 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 307633 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307638 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 307642 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 307644 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 307647 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307651 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307656 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 307658 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 307661 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 307665 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307670 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 307673 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 307676 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 307679 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307684 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307689 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 307694 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 307697 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307701 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307706 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 307713 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 307718 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307723 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307726 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 307728 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307731 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307736 */   // GIR_Coverage, 14194,
     /* 307736 */   GIR_EraseRootFromParent_Done,
     /* 307737 */ // Label 6012: @307737
     /* 307737 */ GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(307887), // Rule ID 14196 //
     /* 307742 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 307745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307749 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307753 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 307757 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 307760 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 307765 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 307769 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 307774 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307776 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 752:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 307776 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 307779 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 307783 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307788 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 307792 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 307794 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 307797 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307801 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307806 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 307808 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 307811 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 307815 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307820 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 307823 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 307826 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 307829 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307834 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307839 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307844 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 307847 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307851 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307856 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 307863 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 307868 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 307876 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 307878 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 307881 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307886 */   // GIR_Coverage, 14196,
     /* 307886 */   GIR_EraseRootFromParent_Done,
     /* 307887 */ // Label 6013: @307887
     /* 307887 */ GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(308037), // Rule ID 14198 //
     /* 307892 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 307895 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 307899 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 307903 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 307907 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 307910 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddv),
     /* 307915 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 307919 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307924 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 307926 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 752:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 307926 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 307929 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 307933 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307938 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 307942 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 307944 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 307947 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 307951 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307956 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 307958 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 307961 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 307965 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 307970 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 307973 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 307976 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 307979 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307984 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 307989 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 307994 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 307997 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308001 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308006 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308013 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308018 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308023 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308026 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308028 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308031 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308036 */   // GIR_Coverage, 14198,
     /* 308036 */   GIR_EraseRootFromParent_Done,
     /* 308037 */ // Label 6014: @308037
     /* 308037 */ GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(308187), // Rule ID 14225 //
     /* 308042 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 308045 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308049 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308053 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308057 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308060 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 308065 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 308069 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 308074 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308076 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 758:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308076 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 308079 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 308083 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308088 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308092 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308094 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308097 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308101 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308106 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308108 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308111 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308115 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308120 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308123 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308126 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 308129 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308134 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308139 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 308144 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308147 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308151 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308156 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308163 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308168 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308173 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308176 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308178 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308181 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308186 */   // GIR_Coverage, 14225,
     /* 308186 */   GIR_EraseRootFromParent_Done,
     /* 308187 */ // Label 6015: @308187
     /* 308187 */ GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(308337), // Rule ID 14227 //
     /* 308192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 308195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308199 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308203 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308207 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308210 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 308215 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 308219 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308224 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308226 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 758:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308226 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 308229 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 308233 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308238 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308242 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308244 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308247 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308251 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308256 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308258 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308261 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308265 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308270 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308273 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308276 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 308279 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308284 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308289 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 308294 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308297 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308301 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308306 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308313 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308318 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308323 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308326 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308328 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308331 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308336 */   // GIR_Coverage, 14227,
     /* 308336 */   GIR_EraseRootFromParent_Done,
     /* 308337 */ // Label 6016: @308337
     /* 308337 */ GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(308487), // Rule ID 14229 //
     /* 308342 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 308345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308349 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308353 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308357 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308360 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 308365 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 308369 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 308374 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308376 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 758:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308376 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 308379 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 308383 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308388 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308392 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308394 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308397 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308401 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308406 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308408 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308411 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308415 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308420 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308423 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308426 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 308429 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308434 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308439 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308444 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308447 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308451 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308456 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308463 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308468 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308473 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308476 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308478 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308481 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308486 */   // GIR_Coverage, 14229,
     /* 308486 */   GIR_EraseRootFromParent_Done,
     /* 308487 */ // Label 6017: @308487
     /* 308487 */ GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(308637), // Rule ID 14231 //
     /* 308492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 308495 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308499 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308503 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308507 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308510 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_umaxv),
     /* 308515 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 308519 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308524 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308526 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 758:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMAXVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308526 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 308529 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 308533 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308538 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308542 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308544 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308547 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308551 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308556 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308558 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308561 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308565 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308570 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308573 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308576 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 308579 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308584 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308589 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 308594 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308597 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308601 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308606 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308613 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308618 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308623 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308626 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308628 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308631 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308636 */   // GIR_Coverage, 14231,
     /* 308636 */   GIR_EraseRootFromParent_Done,
     /* 308637 */ // Label 6018: @308637
     /* 308637 */ GIM_Try, /*On fail goto*//*Label 6019*/ GIMT_Encode4(308787), // Rule ID 14235 //
     /* 308642 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 308645 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308649 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308653 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308657 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308660 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 308665 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 308669 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 308674 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308676 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 761:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308676 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 308679 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 308683 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308688 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308692 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308694 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308697 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308701 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308706 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308708 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308711 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308715 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308720 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308723 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308726 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 308729 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308734 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308739 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 308744 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308747 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308751 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308756 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308763 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308768 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308773 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308776 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308778 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308781 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308786 */   // GIR_Coverage, 14235,
     /* 308786 */   GIR_EraseRootFromParent_Done,
     /* 308787 */ // Label 6019: @308787
     /* 308787 */ GIM_Try, /*On fail goto*//*Label 6020*/ GIMT_Encode4(308937), // Rule ID 14237 //
     /* 308792 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 308795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308799 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308803 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308807 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308810 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 308815 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 308819 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308824 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308826 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i8] } 761:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn), bsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308826 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s8,
     /* 308829 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 308833 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308838 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308842 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308844 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308847 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 308851 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308856 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 308858 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 308861 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 308865 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308870 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 308873 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 308876 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 308879 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308884 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308889 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 308894 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 308897 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308901 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308906 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 308913 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 308918 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 308923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 308926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 308928 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 308931 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308936 */   // GIR_Coverage, 14237,
     /* 308936 */   GIR_EraseRootFromParent_Done,
     /* 308937 */ // Label 6020: @308937
     /* 308937 */ GIM_Try, /*On fail goto*//*Label 6021*/ GIMT_Encode4(309087), // Rule ID 14239 //
     /* 308942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 308945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 308949 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 308953 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 308957 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 308960 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 308965 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 308969 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 308974 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 308976 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 761:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 308976 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 308979 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 308983 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 308988 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 308992 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 308994 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 308997 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 309001 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309006 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 309008 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 309011 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 309015 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309020 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 309023 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 309026 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 309029 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309034 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309039 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 309044 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 309047 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309051 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309056 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 309063 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 309068 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309076 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 309078 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309081 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 309086 */   // GIR_Coverage, 14239,
     /* 309086 */   GIR_EraseRootFromParent_Done,
     /* 309087 */ // Label 6021: @309087
     /* 309087 */ GIM_Try, /*On fail goto*//*Label 6022*/ GIMT_Encode4(309237), // Rule ID 14241 //
     /* 309092 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 309095 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 309099 */   GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309103 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 309107 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 309110 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uminv),
     /* 309115 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 309119 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309124 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309126 */   // (zext:{ *:[i32] } (intrinsic_wo_chain:{ *:[i16] } 761:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (UMINVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn), hsub:{ *:[i32] }), ssub:{ *:[i32] }), GPR32:{ *:[i32] })
     /* 309126 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
     /* 309129 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 309133 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309138 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 309142 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 309144 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 309147 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 309151 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309156 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 309158 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 309161 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 309165 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309170 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 309173 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
     /* 309176 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/9,
     /* 309179 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309184 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309189 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 309194 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 309197 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309201 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 309206 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 309213 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 309218 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309223 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 309226 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 309228 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 309231 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 309236 */   // GIR_Coverage, 14241,
     /* 309236 */   GIR_EraseRootFromParent_Done,
     /* 309237 */ // Label 6022: @309237
     /* 309237 */ GIM_Reject,
     /* 309238 */ // Label 6007: @309238
     /* 309238 */ GIM_Try, /*On fail goto*//*Label 6023*/ GIMT_Encode4(309515),
     /* 309243 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309250 */   GIM_Try, /*On fail goto*//*Label 6024*/ GIMT_Encode4(309307), // Rule ID 1742 //
     /* 309255 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309258 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309262 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309266 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309270 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 309274 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309276 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 309283 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 309290 */     // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 309290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i32_v2i64),
     /* 309293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309295 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309300 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309305 */     GIR_RootConstrainSelectedInstOperands,
     /* 309306 */     // GIR_Coverage, 1742,
     /* 309306 */     GIR_EraseRootFromParent_Done,
     /* 309307 */   // Label 6024: @309307
     /* 309307 */   GIM_Try, /*On fail goto*//*Label 6025*/ GIMT_Encode4(309364), // Rule ID 1808 //
     /* 309312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 309323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309327 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 309331 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309333 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 309340 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 309347 */     // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (UABDLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 309347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i32_v2i64),
     /* 309350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309352 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309357 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309362 */     GIR_RootConstrainSelectedInstOperands,
     /* 309363 */     // GIR_Coverage, 1808,
     /* 309363 */     GIR_EraseRootFromParent_Done,
     /* 309364 */   // Label 6025: @309364
     /* 309364 */   GIM_Try, /*On fail goto*//*Label 6026*/ GIMT_Encode4(309391), // Rule ID 7005 //
     /* 309369 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 309376 */     // (zext:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (USHLLv4i32_shift:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i32] })
     /* 309376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i32_shift),
     /* 309379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309386 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309389 */     GIR_RootConstrainSelectedInstOperands,
     /* 309390 */     // GIR_Coverage, 7005,
     /* 309390 */     GIR_EraseRootFromParent_Done,
     /* 309391 */   // Label 6026: @309391
     /* 309391 */   GIM_Try, /*On fail goto*//*Label 6027*/ GIMT_Encode4(309442), // Rule ID 1741 //
     /* 309396 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309399 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309403 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309407 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309411 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 309415 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309420 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309425 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309427 */     // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 309427 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv2i32_v2i64),
     /* 309430 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 309436 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 309440 */     GIR_RootConstrainSelectedInstOperands,
     /* 309441 */     // GIR_Coverage, 1741,
     /* 309441 */     GIR_EraseRootFromParent_Done,
     /* 309442 */   // Label 6027: @309442
     /* 309442 */   GIM_Try, /*On fail goto*//*Label 6028*/ GIMT_Encode4(309493), // Rule ID 1807 //
     /* 309447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309450 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309454 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 309458 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 309462 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 309466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309471 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309476 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309478 */     // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (UABDLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 309478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv2i32_v2i64),
     /* 309481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 309487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 309491 */     GIR_RootConstrainSelectedInstOperands,
     /* 309492 */     // GIR_Coverage, 1807,
     /* 309492 */     GIR_EraseRootFromParent_Done,
     /* 309493 */   // Label 6028: @309493
     /* 309493 */   GIM_Try, /*On fail goto*//*Label 6029*/ GIMT_Encode4(309514), // Rule ID 6996 //
     /* 309498 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309502 */     // (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, 0:{ *:[i32] })
     /* 309502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 309505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309507 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309509 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309512 */     GIR_RootConstrainSelectedInstOperands,
     /* 309513 */     // GIR_Coverage, 6996,
     /* 309513 */     GIR_EraseRootFromParent_Done,
     /* 309514 */   // Label 6029: @309514
     /* 309514 */   GIM_Reject,
     /* 309515 */ // Label 6023: @309515
     /* 309515 */ GIM_Reject,
     /* 309516 */ // Label 6008: @309516
     /* 309516 */ GIM_Try, /*On fail goto*//*Label 6030*/ GIMT_Encode4(309793),
     /* 309521 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 309524 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309528 */   GIM_Try, /*On fail goto*//*Label 6031*/ GIMT_Encode4(309585), // Rule ID 1740 //
     /* 309533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309536 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309540 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309544 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 309548 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 309552 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309554 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 309561 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 309568 */     // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 309568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i16_v4i32),
     /* 309571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309583 */     GIR_RootConstrainSelectedInstOperands,
     /* 309584 */     // GIR_Coverage, 1740,
     /* 309584 */     GIR_EraseRootFromParent_Done,
     /* 309585 */   // Label 6031: @309585
     /* 309585 */   GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(309642), // Rule ID 1806 //
     /* 309590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309593 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309597 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 309601 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 309605 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 309609 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309611 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 309618 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 309625 */     // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (UABDLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 309625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i16_v4i32),
     /* 309628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309630 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309635 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309640 */     GIR_RootConstrainSelectedInstOperands,
     /* 309641 */     // GIR_Coverage, 1806,
     /* 309641 */     GIR_EraseRootFromParent_Done,
     /* 309642 */   // Label 6032: @309642
     /* 309642 */   GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(309669), // Rule ID 7002 //
     /* 309647 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 309654 */     // (zext:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (USHLLv8i16_shift:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i32] })
     /* 309654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i16_shift),
     /* 309657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309664 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309667 */     GIR_RootConstrainSelectedInstOperands,
     /* 309668 */     // GIR_Coverage, 7002,
     /* 309668 */     GIR_EraseRootFromParent_Done,
     /* 309669 */   // Label 6033: @309669
     /* 309669 */   GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(309720), // Rule ID 1739 //
     /* 309674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309677 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309681 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309685 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 309689 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 309693 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309698 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309703 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309705 */     // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 309705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv4i16_v4i32),
     /* 309708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 309714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 309718 */     GIR_RootConstrainSelectedInstOperands,
     /* 309719 */     // GIR_Coverage, 1739,
     /* 309719 */     GIR_EraseRootFromParent_Done,
     /* 309720 */   // Label 6034: @309720
     /* 309720 */   GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(309771), // Rule ID 1805 //
     /* 309725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309732 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 309736 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 309740 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 309744 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309749 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309754 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309756 */     // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (UABDLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 309756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv4i16_v4i32),
     /* 309759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309761 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 309765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 309769 */     GIR_RootConstrainSelectedInstOperands,
     /* 309770 */     // GIR_Coverage, 1805,
     /* 309770 */     GIR_EraseRootFromParent_Done,
     /* 309771 */   // Label 6035: @309771
     /* 309771 */   GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(309792), // Rule ID 6993 //
     /* 309776 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309780 */     // (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, 0:{ *:[i32] })
     /* 309780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 309783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309785 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 309787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309790 */     GIR_RootConstrainSelectedInstOperands,
     /* 309791 */     // GIR_Coverage, 6993,
     /* 309791 */     GIR_EraseRootFromParent_Done,
     /* 309792 */   // Label 6036: @309792
     /* 309792 */   GIM_Reject,
     /* 309793 */ // Label 6030: @309793
     /* 309793 */ GIM_Reject,
     /* 309794 */ // Label 6009: @309794
     /* 309794 */ GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(310071),
     /* 309799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 309802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 309806 */   GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(309863), // Rule ID 1738 //
     /* 309811 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309814 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309818 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309822 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 309826 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 309830 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309832 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 309839 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 309846 */     // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (SABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 309846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv16i8_v8i16),
     /* 309849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309856 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309861 */     GIR_RootConstrainSelectedInstOperands,
     /* 309862 */     // GIR_Coverage, 1738,
     /* 309862 */     GIR_EraseRootFromParent_Done,
     /* 309863 */   // Label 6038: @309863
     /* 309863 */   GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(309920), // Rule ID 1804 //
     /* 309868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 309879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 309883 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 309887 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309889 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 309896 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 309903 */     // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm)))  =>  (UABDLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 309903 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv16i8_v8i16),
     /* 309906 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309908 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309913 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 309918 */     GIR_RootConstrainSelectedInstOperands,
     /* 309919 */     // GIR_Coverage, 1804,
     /* 309919 */     GIR_EraseRootFromParent_Done,
     /* 309920 */   // Label 6039: @309920
     /* 309920 */   GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(309947), // Rule ID 6999 //
     /* 309925 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 309932 */     // (zext:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn))  =>  (USHLLv16i8_shift:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i32] })
     /* 309932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv16i8_shift),
     /* 309935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 309942 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 309945 */     GIR_RootConstrainSelectedInstOperands,
     /* 309946 */     // GIR_Coverage, 6999,
     /* 309946 */     GIR_EraseRootFromParent_Done,
     /* 309947 */   // Label 6040: @309947
     /* 309947 */   GIM_Try, /*On fail goto*//*Label 6041*/ GIMT_Encode4(309998), // Rule ID 1737 //
     /* 309952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 309955 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 309959 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
     /* 309963 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 309967 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 309971 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309976 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 309981 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 309983 */     // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (SABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 309983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SABDLv8i8_v8i16),
     /* 309986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 309988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 309992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 309996 */     GIR_RootConstrainSelectedInstOperands,
     /* 309997 */     // GIR_Coverage, 1737,
     /* 309997 */     GIR_EraseRootFromParent_Done,
     /* 309998 */   // Label 6041: @309998
     /* 309998 */   GIM_Try, /*On fail goto*//*Label 6042*/ GIMT_Encode4(310049), // Rule ID 1803 //
     /* 310003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 310006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
     /* 310014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 310018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 310022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310032 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310034 */     // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm))  =>  (UABDLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 310034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UABDLv8i8_v8i16),
     /* 310037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 310043 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 310047 */     GIR_RootConstrainSelectedInstOperands,
     /* 310048 */     // GIR_Coverage, 1803,
     /* 310048 */     GIR_EraseRootFromParent_Done,
     /* 310049 */   // Label 6042: @310049
     /* 310049 */   GIM_Try, /*On fail goto*//*Label 6043*/ GIMT_Encode4(310070), // Rule ID 6990 //
     /* 310054 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310058 */     // (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn)  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, 0:{ *:[i32] })
     /* 310058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 310061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310063 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310065 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 310068 */     GIR_RootConstrainSelectedInstOperands,
     /* 310069 */     // GIR_Coverage, 6990,
     /* 310069 */     GIR_EraseRootFromParent_Done,
     /* 310070 */   // Label 6043: @310070
     /* 310070 */   GIM_Reject,
     /* 310071 */ // Label 6037: @310071
     /* 310071 */ GIM_Reject,
     /* 310072 */ // Label 6010: @310072
     /* 310072 */ GIM_Reject,
     /* 310073 */ // Label 55: @310073
     /* 310073 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 6049*/ GIMT_Encode4(310897),
     /* 310084 */ /*GILLT_s32*//*Label 6044*/ GIMT_Encode4(310120),
     /* 310088 */ /*GILLT_s64*//*Label 6045*/ GIMT_Encode4(310297), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 310100 */ /*GILLT_v2s64*//*Label 6046*/ GIMT_Encode4(310470), GIMT_Encode4(0),
     /* 310108 */ /*GILLT_v4s32*//*Label 6047*/ GIMT_Encode4(310615), GIMT_Encode4(0),
     /* 310116 */ /*GILLT_v8s16*//*Label 6048*/ GIMT_Encode4(310756),
     /* 310120 */ // Label 6044: @310120
     /* 310120 */ GIM_Try, /*On fail goto*//*Label 6050*/ GIMT_Encode4(310296),
     /* 310125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 310128 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 310131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310135 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310139 */   GIM_Try, /*On fail goto*//*Label 6051*/ GIMT_Encode4(310176), // Rule ID 4031 //
     /* 310144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 310152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310156 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310161 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310163 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 310163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 310166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310168 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310174 */     GIR_RootConstrainSelectedInstOperands,
     /* 310175 */     // GIR_Coverage, 4031,
     /* 310175 */     GIR_EraseRootFromParent_Done,
     /* 310176 */   // Label 6051: @310176
     /* 310176 */   GIM_Try, /*On fail goto*//*Label 6052*/ GIMT_Encode4(310213), // Rule ID 4032 //
     /* 310181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 310189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310193 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310200 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 310200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 310203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310205 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310211 */     GIR_RootConstrainSelectedInstOperands,
     /* 310212 */     // GIR_Coverage, 4032,
     /* 310212 */     GIR_EraseRootFromParent_Done,
     /* 310213 */   // Label 6052: @310213
     /* 310213 */   GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(310250), // Rule ID 4030 //
     /* 310218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 310226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310230 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310237 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 310237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 310240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310248 */     GIR_RootConstrainSelectedInstOperands,
     /* 310249 */     // GIR_Coverage, 4030,
     /* 310249 */     GIR_EraseRootFromParent_Done,
     /* 310250 */   // Label 6053: @310250
     /* 310250 */   GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(310295), // Rule ID 4029 //
     /* 310255 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (LSLVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 310255 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 310258 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 310262 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310267 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 310273 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310278 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 310283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVWr),
     /* 310286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310288 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310290 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310293 */     GIR_RootConstrainSelectedInstOperands,
     /* 310294 */     // GIR_Coverage, 4029,
     /* 310294 */     GIR_EraseRootFromParent_Done,
     /* 310295 */   // Label 6054: @310295
     /* 310295 */   GIM_Reject,
     /* 310296 */ // Label 6050: @310296
     /* 310296 */ GIM_Reject,
     /* 310297 */ // Label 6045: @310297
     /* 310297 */ GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(310469),
     /* 310302 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 310305 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 310308 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 310312 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 310316 */   GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(310384), // Rule ID 4033 //
     /* 310321 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310325 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 310329 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310333 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310338 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310340 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 310340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 310343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 310347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310352 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 310355 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310359 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 310362 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 310367 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 310375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310377 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310379 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310382 */     GIR_RootConstrainSelectedInstOperands,
     /* 310383 */     // GIR_Coverage, 4033,
     /* 310383 */     GIR_EraseRootFromParent_Done,
     /* 310384 */   // Label 6056: @310384
     /* 310384 */   GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(310452), // Rule ID 4034 //
     /* 310389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 310397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310406 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310408 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 310408 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 310411 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 310415 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 310420 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 310423 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310427 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 310430 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 310435 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310440 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 310443 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310445 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 310447 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 310450 */     GIR_RootConstrainSelectedInstOperands,
     /* 310451 */     // GIR_Coverage, 4034,
     /* 310451 */     GIR_EraseRootFromParent_Done,
     /* 310452 */   // Label 6057: @310452
     /* 310452 */   GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(310468), // Rule ID 108 //
     /* 310457 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 310461 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (LSLVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 310461 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSLVXr),
     /* 310466 */     GIR_RootConstrainSelectedInstOperands,
     /* 310467 */     // GIR_Coverage, 108,
     /* 310467 */     GIR_Done,
     /* 310468 */   // Label 6058: @310468
     /* 310468 */   GIM_Reject,
     /* 310469 */ // Label 6055: @310469
     /* 310469 */ GIM_Reject,
     /* 310470 */ // Label 6046: @310470
     /* 310470 */ GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(310614),
     /* 310475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 310478 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 310481 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310485 */   GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(310549), // Rule ID 6988 //
     /* 310490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 310498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 310502 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310507 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310511 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310515 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 310519 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310523 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310527 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 310531 */     // MIs[3] Operand 1
     /* 310531 */     // No operand predicates
     /* 310531 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310533 */     // (shl:{ *:[v2i64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), (AArch64dup:{ *:[v2i64] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))  =>  (SSHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))
     /* 310533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 310536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310538 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310542 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // size
     /* 310547 */     GIR_RootConstrainSelectedInstOperands,
     /* 310548 */     // GIR_Coverage, 6988,
     /* 310548 */     GIR_EraseRootFromParent_Done,
     /* 310549 */   // Label 6060: @310549
     /* 310549 */   GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(310613), // Rule ID 6985 //
     /* 310554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 310562 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 310566 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310579 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 310583 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310587 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310591 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 310595 */     // MIs[3] Operand 1
     /* 310595 */     // No operand predicates
     /* 310595 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310597 */     // (shl:{ *:[v2i64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm), (AArch64dup:{ *:[v2i64] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))  =>  (USHLLv2i32_shift:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rm, (trunc_imm:{ *:[i32] } (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$size))
     /* 310597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv2i32_shift),
     /* 310600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310606 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/3, /*Renderer*/GIMT_Encode2(GICR_renderTruncImm), // size
     /* 310611 */     GIR_RootConstrainSelectedInstOperands,
     /* 310612 */     // GIR_Coverage, 6985,
     /* 310612 */     GIR_EraseRootFromParent_Done,
     /* 310613 */   // Label 6061: @310613
     /* 310613 */   GIM_Reject,
     /* 310614 */ // Label 6059: @310614
     /* 310614 */ GIM_Reject,
     /* 310615 */ // Label 6047: @310615
     /* 310615 */ GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(310755),
     /* 310620 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 310623 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 310626 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310630 */   GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(310692), // Rule ID 6987 //
     /* 310635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 310643 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 310647 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310652 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310656 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310660 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 310664 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310668 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310672 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 310676 */     // MIs[3] Operand 1
     /* 310676 */     // No operand predicates
     /* 310676 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310678 */     // (shl:{ *:[v4i32] } (sext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), (AArch64dup:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size))  =>  (SSHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size)
     /* 310678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 310681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310687 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 310690 */     GIR_RootConstrainSelectedInstOperands,
     /* 310691 */     // GIR_Coverage, 6987,
     /* 310691 */     GIR_EraseRootFromParent_Done,
     /* 310692 */   // Label 6063: @310692
     /* 310692 */   GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(310754), // Rule ID 6984 //
     /* 310697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 310705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 310709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310722 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 310726 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310730 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310734 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_15),
     /* 310738 */     // MIs[3] Operand 1
     /* 310738 */     // No operand predicates
     /* 310738 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310740 */     // (shl:{ *:[v4i32] } (zext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm), (AArch64dup:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size))  =>  (USHLLv4i16_shift:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_15>>:$size)
     /* 310740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv4i16_shift),
     /* 310743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310745 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310749 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 310752 */     GIR_RootConstrainSelectedInstOperands,
     /* 310753 */     // GIR_Coverage, 6984,
     /* 310753 */     GIR_EraseRootFromParent_Done,
     /* 310754 */   // Label 6064: @310754
     /* 310754 */   GIM_Reject,
     /* 310755 */ // Label 6062: @310755
     /* 310755 */ GIM_Reject,
     /* 310756 */ // Label 6048: @310756
     /* 310756 */ GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(310896),
     /* 310761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 310764 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 310767 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 310771 */   GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(310833), // Rule ID 6986 //
     /* 310776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 310784 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 310788 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310793 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310797 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310801 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 310805 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310809 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310813 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_7),
     /* 310817 */     // MIs[3] Operand 1
     /* 310817 */     // No operand predicates
     /* 310817 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310819 */     // (shl:{ *:[v8i16] } (sext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), (AArch64dup:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size))  =>  (SSHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size)
     /* 310819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 310822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310824 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310828 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 310831 */     GIR_RootConstrainSelectedInstOperands,
     /* 310832 */     // GIR_Coverage, 6986,
     /* 310832 */     GIR_EraseRootFromParent_Done,
     /* 310833 */   // Label 6066: @310833
     /* 310833 */   GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(310895), // Rule ID 6983 //
     /* 310838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 310846 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 310850 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 310855 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 310859 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 310863 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 310867 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 310871 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310875 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm32_0_7),
     /* 310879 */     // MIs[3] Operand 1
     /* 310879 */     // No operand predicates
     /* 310879 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 310881 */     // (shl:{ *:[v8i16] } (zext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm), (AArch64dup:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size))  =>  (USHLLv8i8_shift:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm32_0_7>>:$size)
     /* 310881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USHLLv8i8_shift),
     /* 310884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 310890 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // size
     /* 310893 */     GIR_RootConstrainSelectedInstOperands,
     /* 310894 */     // GIR_Coverage, 6983,
     /* 310894 */     GIR_EraseRootFromParent_Done,
     /* 310895 */   // Label 6067: @310895
     /* 310895 */   GIM_Reject,
     /* 310896 */ // Label 6065: @310896
     /* 310896 */ GIM_Reject,
     /* 310897 */ // Label 6049: @310897
     /* 310897 */ GIM_Reject,
     /* 310898 */ // Label 56: @310898
     /* 310898 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6070*/ GIMT_Encode4(311441),
     /* 310909 */ /*GILLT_s32*//*Label 6068*/ GIMT_Encode4(310917),
     /* 310913 */ /*GILLT_s64*//*Label 6069*/ GIMT_Encode4(311183),
     /* 310917 */ // Label 6068: @310917
     /* 310917 */ GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(311182),
     /* 310922 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 310925 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 310928 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310932 */   GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(310971), // Rule ID 4109 //
     /* 310937 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 310941 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 310945 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 310949 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top16Zero),
     /* 310954 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
     /* 310958 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310960 */     // (srl:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_top16Zero>>:$Rn), 16:{ *:[i64] })  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 310960 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 310963 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 310969 */     GIR_RootConstrainSelectedInstOperands,
     /* 310970 */     // GIR_Coverage, 4109,
     /* 310970 */     GIR_EraseRootFromParent_Done,
     /* 310971 */   // Label 6072: @310971
     /* 310971 */   GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(311009), // Rule ID 4120 //
     /* 310976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 310980 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 310984 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 310988 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 310992 */     // MIs[1] Operand 1
     /* 310992 */     // No operand predicates
     /* 310992 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 310994 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (UBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 310994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMWri),
     /* 310997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 310999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311001 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 311004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 311007 */     GIR_RootConstrainSelectedInstOperands,
     /* 311008 */     // GIR_Coverage, 4120,
     /* 311008 */     GIR_EraseRootFromParent_Done,
     /* 311009 */   // Label 6073: @311009
     /* 311009 */   GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(311050), // Rule ID 4037 //
     /* 311014 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 311026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311030 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311035 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311037 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 311040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311042 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311048 */     GIR_RootConstrainSelectedInstOperands,
     /* 311049 */     // GIR_Coverage, 4037,
     /* 311049 */     GIR_EraseRootFromParent_Done,
     /* 311050 */   // Label 6074: @311050
     /* 311050 */   GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(311091), // Rule ID 4038 //
     /* 311055 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311059 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311063 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 311067 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311071 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311076 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311078 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 311081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311083 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311085 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311089 */     GIR_RootConstrainSelectedInstOperands,
     /* 311090 */     // GIR_Coverage, 4038,
     /* 311090 */     GIR_EraseRootFromParent_Done,
     /* 311091 */   // Label 6075: @311091
     /* 311091 */   GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(311132), // Rule ID 4036 //
     /* 311096 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311100 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311104 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 311108 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311117 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311119 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 311122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311124 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311130 */     GIR_RootConstrainSelectedInstOperands,
     /* 311131 */     // GIR_Coverage, 4036,
     /* 311131 */     GIR_EraseRootFromParent_Done,
     /* 311132 */   // Label 6076: @311132
     /* 311132 */   GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(311181), // Rule ID 4035 //
     /* 311137 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311141 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (LSRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 311141 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 311144 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 311148 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311153 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 311159 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311164 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVWr),
     /* 311172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311174 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311176 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311179 */     GIR_RootConstrainSelectedInstOperands,
     /* 311180 */     // GIR_Coverage, 4035,
     /* 311180 */     GIR_EraseRootFromParent_Done,
     /* 311181 */   // Label 6077: @311181
     /* 311181 */   GIM_Reject,
     /* 311182 */ // Label 6071: @311182
     /* 311182 */ GIM_Reject,
     /* 311183 */ // Label 6069: @311183
     /* 311183 */ GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(311440),
     /* 311188 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 311191 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 311194 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311198 */   GIM_Try, /*On fail goto*//*Label 6079*/ GIMT_Encode4(311237), // Rule ID 4110 //
     /* 311203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 311211 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 311215 */     GIM_CheckLeafOperandPredicate, /*MI*/1, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_top32Zero),
     /* 311220 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32,
     /* 311224 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311226 */     // (srl:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }<<P:Predicate_top32Zero>>:$Rn), 32:{ *:[i64] })  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 311226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 311229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311231 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 311235 */     GIR_RootConstrainSelectedInstOperands,
     /* 311236 */     // GIR_Coverage, 4110,
     /* 311236 */     GIR_EraseRootFromParent_Done,
     /* 311237 */   // Label 6079: @311237
     /* 311237 */   GIM_Try, /*On fail goto*//*Label 6080*/ GIMT_Encode4(311275), // Rule ID 4121 //
     /* 311242 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311250 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311254 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 311258 */     // MIs[1] Operand 1
     /* 311258 */     // No operand predicates
     /* 311258 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311260 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (UBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
     /* 311260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UBFMXri),
     /* 311263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311265 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311267 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 311270 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
     /* 311273 */     GIR_RootConstrainSelectedInstOperands,
     /* 311274 */     // GIR_Coverage, 4121,
     /* 311274 */     GIR_EraseRootFromParent_Done,
     /* 311275 */   // Label 6080: @311275
     /* 311275 */   GIM_Try, /*On fail goto*//*Label 6081*/ GIMT_Encode4(311347), // Rule ID 4039 //
     /* 311280 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 311292 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311301 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311303 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 311303 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 311306 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 311310 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311315 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 311318 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311322 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 311325 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 311330 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 311338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311340 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311342 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311345 */     GIR_RootConstrainSelectedInstOperands,
     /* 311346 */     // GIR_Coverage, 4039,
     /* 311346 */     GIR_EraseRootFromParent_Done,
     /* 311347 */   // Label 6081: @311347
     /* 311347 */   GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(311419), // Rule ID 4040 //
     /* 311352 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311356 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311360 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 311364 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311368 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311373 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311375 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 311375 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 311378 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 311382 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311387 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 311390 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311394 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 311397 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 311402 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 311410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311412 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311414 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311417 */     GIR_RootConstrainSelectedInstOperands,
     /* 311418 */     // GIR_Coverage, 4040,
     /* 311418 */     GIR_EraseRootFromParent_Done,
     /* 311419 */   // Label 6082: @311419
     /* 311419 */   GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(311439), // Rule ID 109 //
     /* 311424 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311428 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311432 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (LSRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 311432 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::LSRVXr),
     /* 311437 */     GIR_RootConstrainSelectedInstOperands,
     /* 311438 */     // GIR_Coverage, 109,
     /* 311438 */     GIR_Done,
     /* 311439 */   // Label 6083: @311439
     /* 311439 */   GIM_Reject,
     /* 311440 */ // Label 6078: @311440
     /* 311440 */ GIM_Reject,
     /* 311441 */ // Label 6070: @311441
     /* 311441 */ GIM_Reject,
     /* 311442 */ // Label 57: @311442
     /* 311442 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6086*/ GIMT_Encode4(312266),
     /* 311453 */ /*GILLT_s32*//*Label 6084*/ GIMT_Encode4(311461),
     /* 311457 */ /*GILLT_s64*//*Label 6085*/ GIMT_Encode4(311816),
     /* 311461 */ // Label 6084: @311461
     /* 311461 */ GIM_Try, /*On fail goto*//*Label 6087*/ GIMT_Encode4(311815),
     /* 311466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 311469 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 311472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311476 */   GIM_Try, /*On fail goto*//*Label 6088*/ GIMT_Encode4(311540), // Rule ID 7158 //
     /* 311481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 311489 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311498 */     // MIs[1] Operand 2
     /* 311498 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 311509 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 311513 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311517 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 311521 */     // MIs[2] Operand 1
     /* 311521 */     // No operand predicates
     /* 311521 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311523 */     // (sra:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i8:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm, 7:{ *:[i64] })
     /* 311523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 311526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311528 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 311532 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 311535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 311538 */     GIR_RootConstrainSelectedInstOperands,
     /* 311539 */     // GIR_Coverage, 7158,
     /* 311539 */     GIR_EraseRootFromParent_Done,
     /* 311540 */   // Label 6088: @311540
     /* 311540 */   GIM_Try, /*On fail goto*//*Label 6089*/ GIMT_Encode4(311604), // Rule ID 7160 //
     /* 311545 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311549 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 311553 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311557 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311562 */     // MIs[1] Operand 2
     /* 311562 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 311573 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 311577 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311581 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
     /* 311585 */     // MIs[2] Operand 1
     /* 311585 */     // No operand predicates
     /* 311585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311587 */     // (sra:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm, 15:{ *:[i64] })
     /* 311587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 311590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 311596 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 311599 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 311602 */     GIR_RootConstrainSelectedInstOperands,
     /* 311603 */     // GIR_Coverage, 7160,
     /* 311603 */     GIR_EraseRootFromParent_Done,
     /* 311604 */   // Label 6089: @311604
     /* 311604 */   GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(311642), // Rule ID 4118 //
     /* 311609 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311613 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311617 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311621 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 311625 */     // MIs[1] Operand 1
     /* 311625 */     // No operand predicates
     /* 311625 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311627 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 311627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMWri),
     /* 311630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311634 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 311637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 311640 */     GIR_RootConstrainSelectedInstOperands,
     /* 311641 */     // GIR_Coverage, 4118,
     /* 311641 */     GIR_EraseRootFromParent_Done,
     /* 311642 */   // Label 6090: @311642
     /* 311642 */   GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(311683), // Rule ID 2472 //
     /* 311647 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 311659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311663 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311668 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311670 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 311673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311675 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311677 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311681 */     GIR_RootConstrainSelectedInstOperands,
     /* 311682 */     // GIR_Coverage, 2472,
     /* 311682 */     GIR_EraseRootFromParent_Done,
     /* 311683 */   // Label 6091: @311683
     /* 311683 */   GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(311724), // Rule ID 2473 //
     /* 311688 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311692 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311696 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 311700 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311704 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311709 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311711 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 311714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311716 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311722 */     GIR_RootConstrainSelectedInstOperands,
     /* 311723 */     // GIR_Coverage, 2473,
     /* 311723 */     GIR_EraseRootFromParent_Done,
     /* 311724 */   // Label 6092: @311724
     /* 311724 */   GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(311765), // Rule ID 2471 //
     /* 311729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 311737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 311741 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311745 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 311752 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 311752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 311755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311757 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 311763 */     GIR_RootConstrainSelectedInstOperands,
     /* 311764 */     // GIR_Coverage, 2471,
     /* 311764 */     GIR_EraseRootFromParent_Done,
     /* 311765 */   // Label 6093: @311765
     /* 311765 */   GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(311814), // Rule ID 2470 //
     /* 311770 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311774 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (ASRVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 311774 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 311777 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 311781 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 311786 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 311792 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311797 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVWr),
     /* 311805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311807 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 311809 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 311812 */     GIR_RootConstrainSelectedInstOperands,
     /* 311813 */     // GIR_Coverage, 2470,
     /* 311813 */     GIR_EraseRootFromParent_Done,
     /* 311814 */   // Label 6094: @311814
     /* 311814 */   GIM_Reject,
     /* 311815 */ // Label 6087: @311815
     /* 311815 */ GIM_Reject,
     /* 311816 */ // Label 6085: @311816
     /* 311816 */ GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(312265),
     /* 311821 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 311824 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 311827 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311831 */   GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(311895), // Rule ID 7159 //
     /* 311836 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311840 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 311844 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 311848 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311853 */     // MIs[1] Operand 2
     /* 311853 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
     /* 311864 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 311868 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311872 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 311876 */     // MIs[2] Operand 1
     /* 311876 */     // No operand predicates
     /* 311876 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311878 */     // (sra:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i8:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm, 7:{ *:[i64] })
     /* 311878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 311881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311883 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 311887 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 311890 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
     /* 311893 */     GIR_RootConstrainSelectedInstOperands,
     /* 311894 */     // GIR_Coverage, 7159,
     /* 311894 */     GIR_EraseRootFromParent_Done,
     /* 311895 */   // Label 6096: @311895
     /* 311895 */   GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(311959), // Rule ID 7161 //
     /* 311900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 311908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 311912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 311917 */     // MIs[1] Operand 2
     /* 311917 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 311928 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 311932 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311936 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
     /* 311940 */     // MIs[2] Operand 1
     /* 311940 */     // No operand predicates
     /* 311940 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311942 */     // (sra:{ *:[i64] } (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, i16:{ *:[Other] }), (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_15>>:$imm, 15:{ *:[i64] })
     /* 311942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 311945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 311947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 311951 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 311954 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/15,
     /* 311957 */     GIR_RootConstrainSelectedInstOperands,
     /* 311958 */     // GIR_Coverage, 7161,
     /* 311958 */     GIR_EraseRootFromParent_Done,
     /* 311959 */   // Label 6097: @311959
     /* 311959 */   GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(312062), // Rule ID 7162 //
     /* 311964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 311968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 311972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 311976 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 311981 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 311985 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 311989 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 311993 */     // MIs[2] Operand 1
     /* 311993 */     // No operand predicates
     /* 311993 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 311995 */     // (sra:{ *:[i64] } (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rn), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (SBFMXri:{ *:[i64] } (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn, sub_32:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm, 31:{ *:[i64] })
     /* 311995 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 311998 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 312002 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312007 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 312009 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 312012 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 312016 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312021 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 312024 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 312028 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 312031 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312036 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 312049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312051 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312054 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 312057 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/31,
     /* 312060 */     GIR_RootConstrainSelectedInstOperands,
     /* 312061 */     // GIR_Coverage, 7162,
     /* 312061 */     GIR_EraseRootFromParent_Done,
     /* 312062 */   // Label 6098: @312062
     /* 312062 */   GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(312100), // Rule ID 4119 //
     /* 312067 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312071 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312075 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312079 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 312083 */     // MIs[1] Operand 1
     /* 312083 */     // No operand predicates
     /* 312083 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312085 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (SBFMXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm, 63:{ *:[i64] })
     /* 312085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SBFMXri),
     /* 312088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312090 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312092 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 312095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/63,
     /* 312098 */     GIR_RootConstrainSelectedInstOperands,
     /* 312099 */     // GIR_Coverage, 4119,
     /* 312099 */     GIR_EraseRootFromParent_Done,
     /* 312100 */   // Label 6099: @312100
     /* 312100 */   GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(312172), // Rule ID 2474 //
     /* 312105 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312113 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 312117 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312121 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312126 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312128 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 312128 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 312131 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 312135 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312140 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 312143 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312147 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 312150 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312155 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 312163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312165 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312167 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312170 */     GIR_RootConstrainSelectedInstOperands,
     /* 312171 */     // GIR_Coverage, 2474,
     /* 312171 */     GIR_EraseRootFromParent_Done,
     /* 312172 */   // Label 6100: @312172
     /* 312172 */   GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(312244), // Rule ID 2475 //
     /* 312177 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312181 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312185 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 312189 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312193 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312200 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 312200 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 312203 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 312207 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312212 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 312215 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312219 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 312222 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312227 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 312235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312237 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312239 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312242 */     GIR_RootConstrainSelectedInstOperands,
     /* 312243 */     // GIR_Coverage, 2475,
     /* 312243 */     GIR_EraseRootFromParent_Done,
     /* 312244 */   // Label 6101: @312244
     /* 312244 */   GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(312264), // Rule ID 107 //
     /* 312249 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312257 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (ASRVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 312257 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ASRVXr),
     /* 312262 */     GIR_RootConstrainSelectedInstOperands,
     /* 312263 */     // GIR_Coverage, 107,
     /* 312263 */     GIR_Done,
     /* 312264 */   // Label 6102: @312264
     /* 312264 */   GIM_Reject,
     /* 312265 */ // Label 6095: @312265
     /* 312265 */ GIM_Reject,
     /* 312266 */ // Label 6086: @312266
     /* 312266 */ GIM_Reject,
     /* 312267 */ // Label 58: @312267
     /* 312267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6105*/ GIMT_Encode4(312396),
     /* 312278 */ /*GILLT_s32*//*Label 6103*/ GIMT_Encode4(312286),
     /* 312282 */ /*GILLT_s64*//*Label 6104*/ GIMT_Encode4(312341),
     /* 312286 */ // Label 6103: @312286
     /* 312286 */ GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(312340), // Rule ID 182 //
     /* 312291 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 312294 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 312297 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 312300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312308 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312312 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 312316 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312320 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 312324 */   // MIs[1] Operand 1
     /* 312324 */   // No operand predicates
     /* 312324 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312326 */   // (fshr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] }):$imm)
     /* 312326 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
     /* 312329 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312331 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312333 */   GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 312335 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 312338 */   GIR_RootConstrainSelectedInstOperands,
     /* 312339 */   // GIR_Coverage, 182,
     /* 312339 */   GIR_EraseRootFromParent_Done,
     /* 312340 */ // Label 6106: @312340
     /* 312340 */ GIM_Reject,
     /* 312341 */ // Label 6104: @312341
     /* 312341 */ GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(312395), // Rule ID 183 //
     /* 312346 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 312349 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 312352 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 312355 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312359 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312363 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312367 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 312371 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312375 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 312379 */   // MIs[1] Operand 1
     /* 312379 */   // No operand predicates
     /* 312379 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312381 */   // (fshr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, (imm:{ *:[i64] }):$imm)
     /* 312381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
     /* 312384 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312386 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312388 */   GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 312390 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 312393 */   GIR_RootConstrainSelectedInstOperands,
     /* 312394 */   // GIR_Coverage, 183,
     /* 312394 */   GIR_EraseRootFromParent_Done,
     /* 312395 */ // Label 6107: @312395
     /* 312395 */ GIM_Reject,
     /* 312396 */ // Label 6105: @312396
     /* 312396 */ GIM_Reject,
     /* 312397 */ // Label 59: @312397
     /* 312397 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 6110*/ GIMT_Encode4(312938),
     /* 312408 */ /*GILLT_s32*//*Label 6108*/ GIMT_Encode4(312416),
     /* 312412 */ /*GILLT_s64*//*Label 6109*/ GIMT_Encode4(312681),
     /* 312416 */ // Label 6108: @312416
     /* 312416 */ GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(312680),
     /* 312421 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 312424 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 312427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312431 */   GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(312470), // Rule ID 178 //
     /* 312436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 312444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312448 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312453 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
     /* 312457 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312459 */     // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn), 16:{ *:[i64] })  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 312459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 312462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312464 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 312468 */     GIR_RootConstrainSelectedInstOperands,
     /* 312469 */     // GIR_Coverage, 178,
     /* 312469 */     GIR_EraseRootFromParent_Done,
     /* 312470 */   // Label 6112: @312470
     /* 312470 */   GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(312507), // Rule ID 4114 //
     /* 312475 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312487 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
     /* 312491 */     // MIs[1] Operand 1
     /* 312491 */     // No operand predicates
     /* 312491 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312493 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)  =>  (EXTRWrri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_31>>:$imm)
     /* 312493 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRWrri),
     /* 312496 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312498 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312500 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312502 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 312505 */     GIR_RootConstrainSelectedInstOperands,
     /* 312506 */     // GIR_Coverage, 4114,
     /* 312506 */     GIR_EraseRootFromParent_Done,
     /* 312507 */   // Label 6113: @312507
     /* 312507 */   GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(312548), // Rule ID 4043 //
     /* 312512 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312516 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312520 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 312524 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312528 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312533 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312535 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 312535 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 312538 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312540 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312546 */     GIR_RootConstrainSelectedInstOperands,
     /* 312547 */     // GIR_Coverage, 4043,
     /* 312547 */     GIR_EraseRootFromParent_Done,
     /* 312548 */   // Label 6114: @312548
     /* 312548 */   GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(312589), // Rule ID 4044 //
     /* 312553 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312557 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312561 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 312565 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312569 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312576 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 312576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 312579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312581 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312583 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312587 */     GIR_RootConstrainSelectedInstOperands,
     /* 312588 */     // GIR_Coverage, 4044,
     /* 312588 */     GIR_EraseRootFromParent_Done,
     /* 312589 */   // Label 6115: @312589
     /* 312589 */   GIM_Try, /*On fail goto*//*Label 6116*/ GIMT_Encode4(312630), // Rule ID 4042 //
     /* 312594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 312606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312617 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 312617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 312620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312622 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312628 */     GIR_RootConstrainSelectedInstOperands,
     /* 312629 */     // GIR_Coverage, 4042,
     /* 312629 */     GIR_EraseRootFromParent_Done,
     /* 312630 */   // Label 6116: @312630
     /* 312630 */   GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(312679), // Rule ID 4041 //
     /* 312635 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312639 */     // (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, i64:{ *:[i64] }:$Rm)  =>  (RORVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$Rm, sub_32:{ *:[i32] }))
     /* 312639 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 312642 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 312646 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312651 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(20), // Rm
     /* 312657 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312662 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVWr),
     /* 312670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312672 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312674 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312677 */     GIR_RootConstrainSelectedInstOperands,
     /* 312678 */     // GIR_Coverage, 4041,
     /* 312678 */     GIR_EraseRootFromParent_Done,
     /* 312679 */   // Label 6117: @312679
     /* 312679 */   GIM_Reject,
     /* 312680 */ // Label 6111: @312680
     /* 312680 */ GIM_Reject,
     /* 312681 */ // Label 6109: @312681
     /* 312681 */ GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(312937),
     /* 312686 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 312689 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 312692 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312696 */   GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(312735), // Rule ID 181 //
     /* 312701 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 312705 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
     /* 312709 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 312713 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312718 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 32,
     /* 312722 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312724 */     // (rotr:{ *:[i64] } (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn), 32:{ *:[i64] })  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 312724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 312727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 312733 */     GIR_RootConstrainSelectedInstOperands,
     /* 312734 */     // GIR_Coverage, 181,
     /* 312734 */     GIR_EraseRootFromParent_Done,
     /* 312735 */   // Label 6119: @312735
     /* 312735 */   GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(312772), // Rule ID 4115 //
     /* 312740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 312752 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_63),
     /* 312756 */     // MIs[1] Operand 1
     /* 312756 */     // No operand predicates
     /* 312756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312758 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)  =>  (EXTRXrri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_imm0_63>>:$imm)
     /* 312758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTRXrri),
     /* 312761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312763 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312765 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312767 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 312770 */     GIR_RootConstrainSelectedInstOperands,
     /* 312771 */     // GIR_Coverage, 4115,
     /* 312771 */     GIR_EraseRootFromParent_Done,
     /* 312772 */   // Label 6120: @312772
     /* 312772 */   GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(312844), // Rule ID 4045 //
     /* 312777 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 312789 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312793 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312798 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312800 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 312800 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 312803 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 312807 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312812 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 312815 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312819 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 312822 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312827 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 312835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312837 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312839 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312842 */     GIR_RootConstrainSelectedInstOperands,
     /* 312843 */     // GIR_Coverage, 4045,
     /* 312843 */     GIR_EraseRootFromParent_Done,
     /* 312844 */   // Label 6121: @312844
     /* 312844 */   GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(312916), // Rule ID 4046 //
     /* 312849 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 312857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 312861 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 312865 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312870 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 312872 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (zext:{ *:[i64] } GPR32:{ *:[i32] }:$Rm))  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (SUBREG_TO_REG:{ *:[i64] } 0:{ *:[i32] }, GPR32:{ *:[i32] }:$Rm, sub_32:{ *:[i32] }))
     /* 312872 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 312875 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 312879 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 312884 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 312887 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 312891 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/20,
     /* 312894 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::GPR64allRegClassID),
     /* 312899 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 312904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 312907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 312909 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 312911 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 312914 */     GIR_RootConstrainSelectedInstOperands,
     /* 312915 */     // GIR_Coverage, 4046,
     /* 312915 */     GIR_EraseRootFromParent_Done,
     /* 312916 */   // Label 6122: @312916
     /* 312916 */   GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(312936), // Rule ID 110 //
     /* 312921 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 312929 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (RORVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 312929 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RORVXr),
     /* 312934 */     GIR_RootConstrainSelectedInstOperands,
     /* 312935 */     // GIR_Coverage, 110,
     /* 312935 */     GIR_Done,
     /* 312936 */   // Label 6123: @312936
     /* 312936 */   GIM_Reject,
     /* 312937 */ // Label 6118: @312937
     /* 312937 */ GIM_Reject,
     /* 312938 */ // Label 6110: @312938
     /* 312938 */ GIM_Reject,
     /* 312939 */ // Label 60: @312939
     /* 312939 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 6132*/ GIMT_Encode4(320715),
     /* 312950 */ /*GILLT_s64*//*Label 6124*/ GIMT_Encode4(312986), GIMT_Encode4(0),
     /* 312958 */ /*GILLT_v2s32*//*Label 6125*/ GIMT_Encode4(313379),
     /* 312962 */ /*GILLT_v2s64*//*Label 6126*/ GIMT_Encode4(314427),
     /* 312966 */ /*GILLT_v4s16*//*Label 6127*/ GIMT_Encode4(315475),
     /* 312970 */ /*GILLT_v4s32*//*Label 6128*/ GIMT_Encode4(316523),
     /* 312974 */ /*GILLT_v8s8*//*Label 6129*/ GIMT_Encode4(317571),
     /* 312978 */ /*GILLT_v8s16*//*Label 6130*/ GIMT_Encode4(318619),
     /* 312982 */ /*GILLT_v16s8*//*Label 6131*/ GIMT_Encode4(319667),
     /* 312986 */ // Label 6124: @312986
     /* 312986 */ GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(313378),
     /* 312991 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 312994 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 312997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313001 */   GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(313037), // Rule ID 5307 //
     /* 313006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313009 */     // MIs[0] Operand 1
     /* 313009 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313014 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313018 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313024 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313026 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313028 */     // (setcc:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, v1i64:{ *:[v1i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv1i64rz),
     /* 313031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313033 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313035 */     GIR_RootConstrainSelectedInstOperands,
     /* 313036 */     // GIR_Coverage, 5307,
     /* 313036 */     GIR_EraseRootFromParent_Done,
     /* 313037 */   // Label 6134: @313037
     /* 313037 */   GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(313073), // Rule ID 5308 //
     /* 313042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313045 */     // MIs[0] Operand 1
     /* 313045 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313054 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313060 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313062 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313064 */     // (setcc:{ *:[v1i64] } immAllZerosV:{ *:[v1i64] }, v1i64:{ *:[v1i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv1i64rz),
     /* 313067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313069 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313071 */     GIR_RootConstrainSelectedInstOperands,
     /* 313072 */     // GIR_Coverage, 5308,
     /* 313072 */     GIR_EraseRootFromParent_Done,
     /* 313073 */   // Label 6135: @313073
     /* 313073 */   GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(313109), // Rule ID 2546 //
     /* 313078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313081 */     // MIs[0] Operand 1
     /* 313081 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 313086 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313090 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313096 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313098 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313100 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv1i64rz),
     /* 313103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313107 */     GIR_RootConstrainSelectedInstOperands,
     /* 313108 */     // GIR_Coverage, 2546,
     /* 313108 */     GIR_EraseRootFromParent_Done,
     /* 313109 */   // Label 6136: @313109
     /* 313109 */   GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(313145), // Rule ID 5304 //
     /* 313114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313117 */     // MIs[0] Operand 1
     /* 313117 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313126 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313132 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313134 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313136 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETGE:{ *:[Other] })  =>  (CMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64rz),
     /* 313139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313141 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313143 */     GIR_RootConstrainSelectedInstOperands,
     /* 313144 */     // GIR_Coverage, 5304,
     /* 313144 */     GIR_EraseRootFromParent_Done,
     /* 313145 */   // Label 6137: @313145
     /* 313145 */   GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(313181), // Rule ID 5305 //
     /* 313150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313153 */     // MIs[0] Operand 1
     /* 313153 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313162 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313168 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 313170 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313172 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllOnesV:{ *:[v1i64] }, SETGT:{ *:[Other] })  =>  (CMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64rz),
     /* 313175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313179 */     GIR_RootConstrainSelectedInstOperands,
     /* 313180 */     // GIR_Coverage, 5305,
     /* 313180 */     GIR_EraseRootFromParent_Done,
     /* 313181 */   // Label 6138: @313181
     /* 313181 */   GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(313217), // Rule ID 5306 //
     /* 313186 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313189 */     // MIs[0] Operand 1
     /* 313189 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313194 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313198 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313204 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313206 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313208 */     // (setcc:{ *:[v1i64] } v1i64:{ *:[v1i64] }:$Rn, immAllZerosV:{ *:[v1i64] }, SETGT:{ *:[Other] })  =>  (CMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 313208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv1i64rz),
     /* 313211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313213 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313215 */     GIR_RootConstrainSelectedInstOperands,
     /* 313216 */     // GIR_Coverage, 5306,
     /* 313216 */     GIR_EraseRootFromParent_Done,
     /* 313217 */   // Label 6139: @313217
     /* 313217 */   GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(313249), // Rule ID 1614 //
     /* 313222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313225 */     // MIs[0] Operand 1
     /* 313225 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 313230 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313234 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313238 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 313238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv1i64),
     /* 313241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 313247 */     GIR_RootConstrainSelectedInstOperands,
     /* 313248 */     // GIR_Coverage, 1614,
     /* 313248 */     GIR_EraseRootFromParent_Done,
     /* 313249 */   // Label 6140: @313249
     /* 313249 */   GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(313281), // Rule ID 1615 //
     /* 313254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313257 */     // MIs[0] Operand 1
     /* 313257 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313266 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313270 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 313270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv1i64),
     /* 313273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313275 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313277 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 313279 */     GIR_RootConstrainSelectedInstOperands,
     /* 313280 */     // GIR_Coverage, 1615,
     /* 313280 */     GIR_EraseRootFromParent_Done,
     /* 313281 */   // Label 6141: @313281
     /* 313281 */   GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(313313), // Rule ID 1616 //
     /* 313286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313289 */     // MIs[0] Operand 1
     /* 313289 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313298 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313302 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 313302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv1i64),
     /* 313305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313307 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313309 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 313311 */     GIR_RootConstrainSelectedInstOperands,
     /* 313312 */     // GIR_Coverage, 1616,
     /* 313312 */     GIR_EraseRootFromParent_Done,
     /* 313313 */   // Label 6142: @313313
     /* 313313 */   GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(313345), // Rule ID 1617 //
     /* 313318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313321 */     // MIs[0] Operand 1
     /* 313321 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 313326 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313330 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313334 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 313334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv1i64),
     /* 313337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313339 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 313343 */     GIR_RootConstrainSelectedInstOperands,
     /* 313344 */     // GIR_Coverage, 1617,
     /* 313344 */     GIR_EraseRootFromParent_Done,
     /* 313345 */   // Label 6143: @313345
     /* 313345 */   GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(313377), // Rule ID 1618 //
     /* 313350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313353 */     // MIs[0] Operand 1
     /* 313353 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 313358 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313362 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313366 */     // (setcc:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 313366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv1i64),
     /* 313369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313371 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 313375 */     GIR_RootConstrainSelectedInstOperands,
     /* 313376 */     // GIR_Coverage, 1618,
     /* 313376 */     GIR_EraseRootFromParent_Done,
     /* 313377 */   // Label 6144: @313377
     /* 313377 */   GIM_Reject,
     /* 313378 */ // Label 6133: @313378
     /* 313378 */ GIM_Reject,
     /* 313379 */ // Label 6125: @313379
     /* 313379 */ GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(314426),
     /* 313384 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 313387 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 313390 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313394 */   GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(313434), // Rule ID 784 //
     /* 313399 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313402 */     // MIs[0] Operand 1
     /* 313402 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313407 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313411 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313417 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313423 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313425 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 313428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313430 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313432 */     GIR_RootConstrainSelectedInstOperands,
     /* 313433 */     // GIR_Coverage, 784,
     /* 313433 */     GIR_EraseRootFromParent_Done,
     /* 313434 */   // Label 6146: @313434
     /* 313434 */   GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(313474), // Rule ID 791 //
     /* 313439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313442 */     // MIs[0] Operand 1
     /* 313442 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313447 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313451 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313457 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313459 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313463 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313465 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313465 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 313468 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313470 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313472 */     GIR_RootConstrainSelectedInstOperands,
     /* 313473 */     // GIR_Coverage, 791,
     /* 313473 */     GIR_EraseRootFromParent_Done,
     /* 313474 */   // Label 6147: @313474
     /* 313474 */   GIM_Try, /*On fail goto*//*Label 6148*/ GIMT_Encode4(313511), // Rule ID 5226 //
     /* 313479 */     // MIs[0] Operand 1
     /* 313479 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 313484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313488 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313494 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313496 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313500 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313502 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313502 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 313505 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313507 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313509 */     GIR_RootConstrainSelectedInstOperands,
     /* 313510 */     // GIR_Coverage, 5226,
     /* 313510 */     GIR_EraseRootFromParent_Done,
     /* 313511 */   // Label 6148: @313511
     /* 313511 */   GIM_Try, /*On fail goto*//*Label 6149*/ GIMT_Encode4(313548), // Rule ID 5233 //
     /* 313516 */     // MIs[0] Operand 1
     /* 313516 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313525 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313531 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313533 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313537 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313539 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 313542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313544 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313546 */     GIR_RootConstrainSelectedInstOperands,
     /* 313547 */     // GIR_Coverage, 5233,
     /* 313547 */     GIR_EraseRootFromParent_Done,
     /* 313548 */   // Label 6149: @313548
     /* 313548 */   GIM_Try, /*On fail goto*//*Label 6150*/ GIMT_Encode4(313585), // Rule ID 5240 //
     /* 313553 */     // MIs[0] Operand 1
     /* 313553 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313562 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313568 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313570 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313574 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313576 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 313579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313581 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313583 */     GIR_RootConstrainSelectedInstOperands,
     /* 313584 */     // GIR_Coverage, 5240,
     /* 313584 */     GIR_EraseRootFromParent_Done,
     /* 313585 */   // Label 6150: @313585
     /* 313585 */   GIM_Try, /*On fail goto*//*Label 6151*/ GIMT_Encode4(313622), // Rule ID 5247 //
     /* 313590 */     // MIs[0] Operand 1
     /* 313590 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 313595 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313599 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313605 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313607 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313611 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313613 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 313616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313620 */     GIR_RootConstrainSelectedInstOperands,
     /* 313621 */     // GIR_Coverage, 5247,
     /* 313621 */     GIR_EraseRootFromParent_Done,
     /* 313622 */   // Label 6151: @313622
     /* 313622 */   GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(313659), // Rule ID 5254 //
     /* 313627 */     // MIs[0] Operand 1
     /* 313627 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 313632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 313636 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313642 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313644 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313648 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313650 */     // (setcc:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, V64:{ *:[v2i32] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313650 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 313653 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313655 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 313657 */     GIR_RootConstrainSelectedInstOperands,
     /* 313658 */     // GIR_Coverage, 5254,
     /* 313658 */     GIR_EraseRootFromParent_Done,
     /* 313659 */   // Label 6152: @313659
     /* 313659 */   GIM_Try, /*On fail goto*//*Label 6153*/ GIMT_Encode4(313699), // Rule ID 756 //
     /* 313664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313667 */     // MIs[0] Operand 1
     /* 313667 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 313672 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313680 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313686 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313688 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313690 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 313693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313697 */     GIR_RootConstrainSelectedInstOperands,
     /* 313698 */     // GIR_Coverage, 756,
     /* 313698 */     GIR_EraseRootFromParent_Done,
     /* 313699 */   // Label 6153: @313699
     /* 313699 */   GIM_Try, /*On fail goto*//*Label 6154*/ GIMT_Encode4(313739), // Rule ID 767 //
     /* 313704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313707 */     // MIs[0] Operand 1
     /* 313707 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313712 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313720 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313726 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313728 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313730 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313730 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 313733 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313735 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313737 */     GIR_RootConstrainSelectedInstOperands,
     /* 313738 */     // GIR_Coverage, 767,
     /* 313738 */     GIR_EraseRootFromParent_Done,
     /* 313739 */   // Label 6154: @313739
     /* 313739 */   GIM_Try, /*On fail goto*//*Label 6155*/ GIMT_Encode4(313779), // Rule ID 768 //
     /* 313744 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313747 */     // MIs[0] Operand 1
     /* 313747 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313752 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313756 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313760 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313766 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 313768 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313770 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllOnesV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 313773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313775 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313777 */     GIR_RootConstrainSelectedInstOperands,
     /* 313778 */     // GIR_Coverage, 768,
     /* 313778 */     GIR_EraseRootFromParent_Done,
     /* 313779 */   // Label 6155: @313779
     /* 313779 */   GIM_Try, /*On fail goto*//*Label 6156*/ GIMT_Encode4(313819), // Rule ID 777 //
     /* 313784 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 313787 */     // MIs[0] Operand 1
     /* 313787 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313792 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313796 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313800 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313806 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313808 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313810 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 313813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313815 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313817 */     GIR_RootConstrainSelectedInstOperands,
     /* 313818 */     // GIR_Coverage, 777,
     /* 313818 */     GIR_EraseRootFromParent_Done,
     /* 313819 */   // Label 6156: @313819
     /* 313819 */   GIM_Try, /*On fail goto*//*Label 6157*/ GIMT_Encode4(313856), // Rule ID 5191 //
     /* 313824 */     // MIs[0] Operand 1
     /* 313824 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 313829 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313837 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313843 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313845 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313847 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32rz),
     /* 313850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313852 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313854 */     GIR_RootConstrainSelectedInstOperands,
     /* 313855 */     // GIR_Coverage, 5191,
     /* 313855 */     GIR_EraseRootFromParent_Done,
     /* 313856 */   // Label 6157: @313856
     /* 313856 */   GIM_Try, /*On fail goto*//*Label 6158*/ GIMT_Encode4(313893), // Rule ID 5198 //
     /* 313861 */     // MIs[0] Operand 1
     /* 313861 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 313866 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313874 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313880 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313882 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313884 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGT:{ *:[Other] })  =>  (CMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32rz),
     /* 313887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313889 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313891 */     GIR_RootConstrainSelectedInstOperands,
     /* 313892 */     // GIR_Coverage, 5198,
     /* 313892 */     GIR_EraseRootFromParent_Done,
     /* 313893 */   // Label 6158: @313893
     /* 313893 */   GIM_Try, /*On fail goto*//*Label 6159*/ GIMT_Encode4(313930), // Rule ID 5205 //
     /* 313898 */     // MIs[0] Operand 1
     /* 313898 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 313903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313907 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313911 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313917 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313919 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313921 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETGE:{ *:[Other] })  =>  (CMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32rz),
     /* 313924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313926 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313928 */     GIR_RootConstrainSelectedInstOperands,
     /* 313929 */     // GIR_Coverage, 5205,
     /* 313929 */     GIR_EraseRootFromParent_Done,
     /* 313930 */   // Label 6159: @313930
     /* 313930 */   GIM_Try, /*On fail goto*//*Label 6160*/ GIMT_Encode4(313967), // Rule ID 5212 //
     /* 313935 */     // MIs[0] Operand 1
     /* 313935 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 313940 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313948 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313954 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313956 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313958 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLT:{ *:[Other] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 313961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 313963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 313965 */     GIR_RootConstrainSelectedInstOperands,
     /* 313966 */     // GIR_Coverage, 5212,
     /* 313966 */     GIR_EraseRootFromParent_Done,
     /* 313967 */   // Label 6160: @313967
     /* 313967 */   GIM_Try, /*On fail goto*//*Label 6161*/ GIMT_Encode4(314004), // Rule ID 5219 //
     /* 313972 */     // MIs[0] Operand 1
     /* 313972 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 313977 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 313981 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 313985 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 313991 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 313993 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 313995 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, immAllZerosV:{ *:[v2i32] }, SETLE:{ *:[Other] })  =>  (CMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 313995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i32rz),
     /* 313998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314000 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314002 */     GIR_RootConstrainSelectedInstOperands,
     /* 314003 */     // GIR_Coverage, 5219,
     /* 314003 */     GIR_EraseRootFromParent_Done,
     /* 314004 */   // Label 6161: @314004
     /* 314004 */   GIM_Try, /*On fail goto*//*Label 6162*/ GIMT_Encode4(314036), // Rule ID 1155 //
     /* 314009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314012 */     // MIs[0] Operand 1
     /* 314012 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 314017 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314021 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314025 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314025 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32),
     /* 314028 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314030 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314032 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314034 */     GIR_RootConstrainSelectedInstOperands,
     /* 314035 */     // GIR_Coverage, 1155,
     /* 314035 */     GIR_EraseRootFromParent_Done,
     /* 314036 */   // Label 6162: @314036
     /* 314036 */   GIM_Try, /*On fail goto*//*Label 6163*/ GIMT_Encode4(314068), // Rule ID 1162 //
     /* 314041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314044 */     // MIs[0] Operand 1
     /* 314044 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314049 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314053 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314057 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 314060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314064 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314066 */     GIR_RootConstrainSelectedInstOperands,
     /* 314067 */     // GIR_Coverage, 1162,
     /* 314067 */     GIR_EraseRootFromParent_Done,
     /* 314068 */   // Label 6163: @314068
     /* 314068 */   GIM_Try, /*On fail goto*//*Label 6164*/ GIMT_Encode4(314100), // Rule ID 1169 //
     /* 314073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314076 */     // MIs[0] Operand 1
     /* 314076 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314081 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314085 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314089 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 314092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314094 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314096 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314098 */     GIR_RootConstrainSelectedInstOperands,
     /* 314099 */     // GIR_Coverage, 1169,
     /* 314099 */     GIR_EraseRootFromParent_Done,
     /* 314100 */   // Label 6164: @314100
     /* 314100 */   GIM_Try, /*On fail goto*//*Label 6165*/ GIMT_Encode4(314132), // Rule ID 1176 //
     /* 314105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314108 */     // MIs[0] Operand 1
     /* 314108 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 314113 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314117 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314121 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 314124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314130 */     GIR_RootConstrainSelectedInstOperands,
     /* 314131 */     // GIR_Coverage, 1176,
     /* 314131 */     GIR_EraseRootFromParent_Done,
     /* 314132 */   // Label 6165: @314132
     /* 314132 */   GIM_Try, /*On fail goto*//*Label 6166*/ GIMT_Encode4(314164), // Rule ID 1183 //
     /* 314137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314140 */     // MIs[0] Operand 1
     /* 314140 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 314145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314153 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 314156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314160 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314162 */     GIR_RootConstrainSelectedInstOperands,
     /* 314163 */     // GIR_Coverage, 1183,
     /* 314163 */     GIR_EraseRootFromParent_Done,
     /* 314164 */   // Label 6166: @314164
     /* 314164 */   GIM_Try, /*On fail goto*//*Label 6167*/ GIMT_Encode4(314193), // Rule ID 5128 //
     /* 314169 */     // MIs[0] Operand 1
     /* 314169 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 314174 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314178 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314182 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i32),
     /* 314185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314187 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314189 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314191 */     GIR_RootConstrainSelectedInstOperands,
     /* 314192 */     // GIR_Coverage, 5128,
     /* 314192 */     GIR_EraseRootFromParent_Done,
     /* 314193 */   // Label 6167: @314193
     /* 314193 */   GIM_Try, /*On fail goto*//*Label 6168*/ GIMT_Encode4(314222), // Rule ID 5135 //
     /* 314198 */     // MIs[0] Operand 1
     /* 314198 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314203 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314211 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 314214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314220 */     GIR_RootConstrainSelectedInstOperands,
     /* 314221 */     // GIR_Coverage, 5135,
     /* 314221 */     GIR_EraseRootFromParent_Done,
     /* 314222 */   // Label 6168: @314222
     /* 314222 */   GIM_Try, /*On fail goto*//*Label 6169*/ GIMT_Encode4(314251), // Rule ID 5142 //
     /* 314227 */     // MIs[0] Operand 1
     /* 314227 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314232 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314236 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314240 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 314243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314247 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314249 */     GIR_RootConstrainSelectedInstOperands,
     /* 314250 */     // GIR_Coverage, 5142,
     /* 314250 */     GIR_EraseRootFromParent_Done,
     /* 314251 */   // Label 6169: @314251
     /* 314251 */   GIM_Try, /*On fail goto*//*Label 6170*/ GIMT_Encode4(314280), // Rule ID 5149 //
     /* 314256 */     // MIs[0] Operand 1
     /* 314256 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 314261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314265 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314269 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 314272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314274 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314278 */     GIR_RootConstrainSelectedInstOperands,
     /* 314279 */     // GIR_Coverage, 5149,
     /* 314279 */     GIR_EraseRootFromParent_Done,
     /* 314280 */   // Label 6170: @314280
     /* 314280 */   GIM_Try, /*On fail goto*//*Label 6171*/ GIMT_Encode4(314309), // Rule ID 5156 //
     /* 314285 */     // MIs[0] Operand 1
     /* 314285 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 314290 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314294 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314298 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 314298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 314301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314305 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314307 */     GIR_RootConstrainSelectedInstOperands,
     /* 314308 */     // GIR_Coverage, 5156,
     /* 314308 */     GIR_EraseRootFromParent_Done,
     /* 314309 */   // Label 6171: @314309
     /* 314309 */   GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(314338), // Rule ID 5163 //
     /* 314314 */     // MIs[0] Operand 1
     /* 314314 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 314319 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314323 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314327 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 314327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i32),
     /* 314330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314332 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314336 */     GIR_RootConstrainSelectedInstOperands,
     /* 314337 */     // GIR_Coverage, 5163,
     /* 314337 */     GIR_EraseRootFromParent_Done,
     /* 314338 */   // Label 6172: @314338
     /* 314338 */   GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(314367), // Rule ID 5170 //
     /* 314343 */     // MIs[0] Operand 1
     /* 314343 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 314348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314352 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314356 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 314356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i32),
     /* 314359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314361 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314363 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314365 */     GIR_RootConstrainSelectedInstOperands,
     /* 314366 */     // GIR_Coverage, 5170,
     /* 314366 */     GIR_EraseRootFromParent_Done,
     /* 314367 */   // Label 6173: @314367
     /* 314367 */   GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(314396), // Rule ID 5177 //
     /* 314372 */     // MIs[0] Operand 1
     /* 314372 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 314377 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314381 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314385 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 314385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i32),
     /* 314388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314394 */     GIR_RootConstrainSelectedInstOperands,
     /* 314395 */     // GIR_Coverage, 5177,
     /* 314395 */     GIR_EraseRootFromParent_Done,
     /* 314396 */   // Label 6174: @314396
     /* 314396 */   GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(314425), // Rule ID 5184 //
     /* 314401 */     // MIs[0] Operand 1
     /* 314401 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 314406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314410 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 314414 */     // (setcc:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rm, V64:{ *:[v2i32] }:$Rn)
     /* 314414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i32),
     /* 314417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314419 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 314421 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314423 */     GIR_RootConstrainSelectedInstOperands,
     /* 314424 */     // GIR_Coverage, 5184,
     /* 314424 */     GIR_EraseRootFromParent_Done,
     /* 314425 */   // Label 6175: @314425
     /* 314425 */   GIM_Reject,
     /* 314426 */ // Label 6145: @314426
     /* 314426 */ GIM_Reject,
     /* 314427 */ // Label 6126: @314427
     /* 314427 */ GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(315474),
     /* 314432 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 314435 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 314438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314442 */   GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(314482), // Rule ID 786 //
     /* 314447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314450 */     // MIs[0] Operand 1
     /* 314450 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314455 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314459 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314465 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314467 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314471 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314473 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 314476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314478 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314480 */     GIR_RootConstrainSelectedInstOperands,
     /* 314481 */     // GIR_Coverage, 786,
     /* 314481 */     GIR_EraseRootFromParent_Done,
     /* 314482 */   // Label 6177: @314482
     /* 314482 */   GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(314522), // Rule ID 793 //
     /* 314487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314490 */     // MIs[0] Operand 1
     /* 314490 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314499 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314505 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314507 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314511 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314513 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 314516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314518 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314520 */     GIR_RootConstrainSelectedInstOperands,
     /* 314521 */     // GIR_Coverage, 793,
     /* 314521 */     GIR_EraseRootFromParent_Done,
     /* 314522 */   // Label 6178: @314522
     /* 314522 */   GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(314559), // Rule ID 5228 //
     /* 314527 */     // MIs[0] Operand 1
     /* 314527 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 314532 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314536 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314542 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314548 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314550 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 314553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314557 */     GIR_RootConstrainSelectedInstOperands,
     /* 314558 */     // GIR_Coverage, 5228,
     /* 314558 */     GIR_EraseRootFromParent_Done,
     /* 314559 */   // Label 6179: @314559
     /* 314559 */   GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(314596), // Rule ID 5235 //
     /* 314564 */     // MIs[0] Operand 1
     /* 314564 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314573 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314579 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314581 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314585 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314587 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 314590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314592 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314594 */     GIR_RootConstrainSelectedInstOperands,
     /* 314595 */     // GIR_Coverage, 5235,
     /* 314595 */     GIR_EraseRootFromParent_Done,
     /* 314596 */   // Label 6180: @314596
     /* 314596 */   GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(314633), // Rule ID 5242 //
     /* 314601 */     // MIs[0] Operand 1
     /* 314601 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314606 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314610 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314616 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314618 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314622 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314624 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 314627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314629 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314631 */     GIR_RootConstrainSelectedInstOperands,
     /* 314632 */     // GIR_Coverage, 5242,
     /* 314632 */     GIR_EraseRootFromParent_Done,
     /* 314633 */   // Label 6181: @314633
     /* 314633 */   GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(314670), // Rule ID 5249 //
     /* 314638 */     // MIs[0] Operand 1
     /* 314638 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 314643 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314647 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314653 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314655 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314659 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314661 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 314664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314666 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314668 */     GIR_RootConstrainSelectedInstOperands,
     /* 314669 */     // GIR_Coverage, 5249,
     /* 314669 */     GIR_EraseRootFromParent_Done,
     /* 314670 */   // Label 6182: @314670
     /* 314670 */   GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(314707), // Rule ID 5256 //
     /* 314675 */     // MIs[0] Operand 1
     /* 314675 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 314680 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 314684 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314690 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314692 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314696 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314698 */     // (setcc:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, V128:{ *:[v2i64] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 314701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314703 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 314705 */     GIR_RootConstrainSelectedInstOperands,
     /* 314706 */     // GIR_Coverage, 5256,
     /* 314706 */     GIR_EraseRootFromParent_Done,
     /* 314707 */   // Label 6183: @314707
     /* 314707 */   GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(314747), // Rule ID 758 //
     /* 314712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314715 */     // MIs[0] Operand 1
     /* 314715 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 314720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314728 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314734 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314736 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314738 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 314741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314745 */     GIR_RootConstrainSelectedInstOperands,
     /* 314746 */     // GIR_Coverage, 758,
     /* 314746 */     GIR_EraseRootFromParent_Done,
     /* 314747 */   // Label 6184: @314747
     /* 314747 */   GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(314787), // Rule ID 771 //
     /* 314752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314755 */     // MIs[0] Operand 1
     /* 314755 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314760 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314764 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314768 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314774 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314776 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314778 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 314781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314783 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314785 */     GIR_RootConstrainSelectedInstOperands,
     /* 314786 */     // GIR_Coverage, 771,
     /* 314786 */     GIR_EraseRootFromParent_Done,
     /* 314787 */   // Label 6185: @314787
     /* 314787 */   GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(314827), // Rule ID 772 //
     /* 314792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314795 */     // MIs[0] Operand 1
     /* 314795 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314804 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314808 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314814 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 314816 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314818 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllOnesV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 314821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314823 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314825 */     GIR_RootConstrainSelectedInstOperands,
     /* 314826 */     // GIR_Coverage, 772,
     /* 314826 */     GIR_EraseRootFromParent_Done,
     /* 314827 */   // Label 6186: @314827
     /* 314827 */   GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(314867), // Rule ID 779 //
     /* 314832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 314835 */     // MIs[0] Operand 1
     /* 314835 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314844 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314848 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314854 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314856 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314858 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 314861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314863 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314865 */     GIR_RootConstrainSelectedInstOperands,
     /* 314866 */     // GIR_Coverage, 779,
     /* 314866 */     GIR_EraseRootFromParent_Done,
     /* 314867 */   // Label 6187: @314867
     /* 314867 */   GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(314904), // Rule ID 5193 //
     /* 314872 */     // MIs[0] Operand 1
     /* 314872 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 314877 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314881 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314885 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314891 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314893 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314895 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETEQ:{ *:[Other] })  =>  (CMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64rz),
     /* 314898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314900 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314902 */     GIR_RootConstrainSelectedInstOperands,
     /* 314903 */     // GIR_Coverage, 5193,
     /* 314903 */     GIR_EraseRootFromParent_Done,
     /* 314904 */   // Label 6188: @314904
     /* 314904 */   GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(314941), // Rule ID 5200 //
     /* 314909 */     // MIs[0] Operand 1
     /* 314909 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 314914 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314918 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314922 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314928 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314930 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314932 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGT:{ *:[Other] })  =>  (CMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64rz),
     /* 314935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314937 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314939 */     GIR_RootConstrainSelectedInstOperands,
     /* 314940 */     // GIR_Coverage, 5200,
     /* 314940 */     GIR_EraseRootFromParent_Done,
     /* 314941 */   // Label 6189: @314941
     /* 314941 */   GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(314978), // Rule ID 5207 //
     /* 314946 */     // MIs[0] Operand 1
     /* 314946 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 314951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314955 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314959 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 314965 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 314967 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 314969 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETGE:{ *:[Other] })  =>  (CMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 314969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64rz),
     /* 314972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 314974 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 314976 */     GIR_RootConstrainSelectedInstOperands,
     /* 314977 */     // GIR_Coverage, 5207,
     /* 314977 */     GIR_EraseRootFromParent_Done,
     /* 314978 */   // Label 6190: @314978
     /* 314978 */   GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(315015), // Rule ID 5214 //
     /* 314983 */     // MIs[0] Operand 1
     /* 314983 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 314988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 314992 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 314996 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315002 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315004 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315006 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLT:{ *:[Other] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 315006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 315009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315013 */     GIR_RootConstrainSelectedInstOperands,
     /* 315014 */     // GIR_Coverage, 5214,
     /* 315014 */     GIR_EraseRootFromParent_Done,
     /* 315015 */   // Label 6191: @315015
     /* 315015 */   GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(315052), // Rule ID 5221 //
     /* 315020 */     // MIs[0] Operand 1
     /* 315020 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 315025 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315033 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315039 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315041 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315043 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, immAllZerosV:{ *:[v2i64] }, SETLE:{ *:[Other] })  =>  (CMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 315043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv2i64rz),
     /* 315046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315048 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315050 */     GIR_RootConstrainSelectedInstOperands,
     /* 315051 */     // GIR_Coverage, 5221,
     /* 315051 */     GIR_EraseRootFromParent_Done,
     /* 315052 */   // Label 6192: @315052
     /* 315052 */   GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(315084), // Rule ID 1157 //
     /* 315057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315060 */     // MIs[0] Operand 1
     /* 315060 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 315065 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315069 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315073 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64),
     /* 315076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315078 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315080 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315082 */     GIR_RootConstrainSelectedInstOperands,
     /* 315083 */     // GIR_Coverage, 1157,
     /* 315083 */     GIR_EraseRootFromParent_Done,
     /* 315084 */   // Label 6193: @315084
     /* 315084 */   GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(315116), // Rule ID 1164 //
     /* 315089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315092 */     // MIs[0] Operand 1
     /* 315092 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315097 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315101 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315105 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 315108 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315110 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315112 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315114 */     GIR_RootConstrainSelectedInstOperands,
     /* 315115 */     // GIR_Coverage, 1164,
     /* 315115 */     GIR_EraseRootFromParent_Done,
     /* 315116 */   // Label 6194: @315116
     /* 315116 */   GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(315148), // Rule ID 1171 //
     /* 315121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315124 */     // MIs[0] Operand 1
     /* 315124 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315133 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315137 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 315140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315142 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315144 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315146 */     GIR_RootConstrainSelectedInstOperands,
     /* 315147 */     // GIR_Coverage, 1171,
     /* 315147 */     GIR_EraseRootFromParent_Done,
     /* 315148 */   // Label 6195: @315148
     /* 315148 */   GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(315180), // Rule ID 1178 //
     /* 315153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315156 */     // MIs[0] Operand 1
     /* 315156 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 315161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315165 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315169 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 315172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315178 */     GIR_RootConstrainSelectedInstOperands,
     /* 315179 */     // GIR_Coverage, 1178,
     /* 315179 */     GIR_EraseRootFromParent_Done,
     /* 315180 */   // Label 6196: @315180
     /* 315180 */   GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(315212), // Rule ID 1185 //
     /* 315185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315188 */     // MIs[0] Operand 1
     /* 315188 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 315193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315197 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315201 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 315204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315210 */     GIR_RootConstrainSelectedInstOperands,
     /* 315211 */     // GIR_Coverage, 1185,
     /* 315211 */     GIR_EraseRootFromParent_Done,
     /* 315212 */   // Label 6197: @315212
     /* 315212 */   GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(315241), // Rule ID 5130 //
     /* 315217 */     // MIs[0] Operand 1
     /* 315217 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 315222 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315226 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315230 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv2i64),
     /* 315233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315235 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315237 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315239 */     GIR_RootConstrainSelectedInstOperands,
     /* 315240 */     // GIR_Coverage, 5130,
     /* 315240 */     GIR_EraseRootFromParent_Done,
     /* 315241 */   // Label 6198: @315241
     /* 315241 */   GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(315270), // Rule ID 5137 //
     /* 315246 */     // MIs[0] Operand 1
     /* 315246 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315251 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315255 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315259 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 315262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315264 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315266 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315268 */     GIR_RootConstrainSelectedInstOperands,
     /* 315269 */     // GIR_Coverage, 5137,
     /* 315269 */     GIR_EraseRootFromParent_Done,
     /* 315270 */   // Label 6199: @315270
     /* 315270 */   GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(315299), // Rule ID 5144 //
     /* 315275 */     // MIs[0] Operand 1
     /* 315275 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315284 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315288 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 315291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315295 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315297 */     GIR_RootConstrainSelectedInstOperands,
     /* 315298 */     // GIR_Coverage, 5144,
     /* 315298 */     GIR_EraseRootFromParent_Done,
     /* 315299 */   // Label 6200: @315299
     /* 315299 */   GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(315328), // Rule ID 5151 //
     /* 315304 */     // MIs[0] Operand 1
     /* 315304 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 315309 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315313 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315317 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 315320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315322 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315324 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315326 */     GIR_RootConstrainSelectedInstOperands,
     /* 315327 */     // GIR_Coverage, 5151,
     /* 315327 */     GIR_EraseRootFromParent_Done,
     /* 315328 */   // Label 6201: @315328
     /* 315328 */   GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(315357), // Rule ID 5158 //
     /* 315333 */     // MIs[0] Operand 1
     /* 315333 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 315338 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315342 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315346 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 315346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 315349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315351 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315353 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315355 */     GIR_RootConstrainSelectedInstOperands,
     /* 315356 */     // GIR_Coverage, 5158,
     /* 315356 */     GIR_EraseRootFromParent_Done,
     /* 315357 */   // Label 6202: @315357
     /* 315357 */   GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(315386), // Rule ID 5165 //
     /* 315362 */     // MIs[0] Operand 1
     /* 315362 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 315367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315371 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315375 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 315375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv2i64),
     /* 315378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315384 */     GIR_RootConstrainSelectedInstOperands,
     /* 315385 */     // GIR_Coverage, 5165,
     /* 315385 */     GIR_EraseRootFromParent_Done,
     /* 315386 */   // Label 6203: @315386
     /* 315386 */   GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(315415), // Rule ID 5172 //
     /* 315391 */     // MIs[0] Operand 1
     /* 315391 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 315396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315400 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315404 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 315404 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv2i64),
     /* 315407 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315409 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315411 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315413 */     GIR_RootConstrainSelectedInstOperands,
     /* 315414 */     // GIR_Coverage, 5172,
     /* 315414 */     GIR_EraseRootFromParent_Done,
     /* 315415 */   // Label 6204: @315415
     /* 315415 */   GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(315444), // Rule ID 5179 //
     /* 315420 */     // MIs[0] Operand 1
     /* 315420 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 315425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315429 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315433 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 315433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv2i64),
     /* 315436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315438 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315440 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315442 */     GIR_RootConstrainSelectedInstOperands,
     /* 315443 */     // GIR_Coverage, 5179,
     /* 315443 */     GIR_EraseRootFromParent_Done,
     /* 315444 */   // Label 6205: @315444
     /* 315444 */   GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(315473), // Rule ID 5186 //
     /* 315449 */     // MIs[0] Operand 1
     /* 315449 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 315454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 315462 */     // (setcc:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rm, V128:{ *:[v2i64] }:$Rn)
     /* 315462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv2i64),
     /* 315465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315467 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 315469 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315471 */     GIR_RootConstrainSelectedInstOperands,
     /* 315472 */     // GIR_Coverage, 5186,
     /* 315472 */     GIR_EraseRootFromParent_Done,
     /* 315473 */   // Label 6206: @315473
     /* 315473 */   GIM_Reject,
     /* 315474 */ // Label 6176: @315474
     /* 315474 */ GIM_Reject,
     /* 315475 */ // Label 6127: @315475
     /* 315475 */ GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(316522),
     /* 315480 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 315483 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 315486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315490 */   GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(315530), // Rule ID 782 //
     /* 315495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315498 */     // MIs[0] Operand 1
     /* 315498 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315507 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315513 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315515 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315519 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315521 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 315524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315526 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315528 */     GIR_RootConstrainSelectedInstOperands,
     /* 315529 */     // GIR_Coverage, 782,
     /* 315529 */     GIR_EraseRootFromParent_Done,
     /* 315530 */   // Label 6208: @315530
     /* 315530 */   GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(315570), // Rule ID 789 //
     /* 315535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315538 */     // MIs[0] Operand 1
     /* 315538 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315547 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315553 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315555 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315559 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315561 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 315564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315566 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315568 */     GIR_RootConstrainSelectedInstOperands,
     /* 315569 */     // GIR_Coverage, 789,
     /* 315569 */     GIR_EraseRootFromParent_Done,
     /* 315570 */   // Label 6209: @315570
     /* 315570 */   GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(315607), // Rule ID 5224 //
     /* 315575 */     // MIs[0] Operand 1
     /* 315575 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 315580 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315584 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315590 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315596 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315598 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 315601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315603 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315605 */     GIR_RootConstrainSelectedInstOperands,
     /* 315606 */     // GIR_Coverage, 5224,
     /* 315606 */     GIR_EraseRootFromParent_Done,
     /* 315607 */   // Label 6210: @315607
     /* 315607 */   GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(315644), // Rule ID 5231 //
     /* 315612 */     // MIs[0] Operand 1
     /* 315612 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315621 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315627 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315629 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315633 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315635 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 315638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315640 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315642 */     GIR_RootConstrainSelectedInstOperands,
     /* 315643 */     // GIR_Coverage, 5231,
     /* 315643 */     GIR_EraseRootFromParent_Done,
     /* 315644 */   // Label 6211: @315644
     /* 315644 */   GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(315681), // Rule ID 5238 //
     /* 315649 */     // MIs[0] Operand 1
     /* 315649 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315654 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315658 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315664 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315666 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315670 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315672 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 315675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315677 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315679 */     GIR_RootConstrainSelectedInstOperands,
     /* 315680 */     // GIR_Coverage, 5238,
     /* 315680 */     GIR_EraseRootFromParent_Done,
     /* 315681 */   // Label 6212: @315681
     /* 315681 */   GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(315718), // Rule ID 5245 //
     /* 315686 */     // MIs[0] Operand 1
     /* 315686 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 315691 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315695 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315701 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315703 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315707 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315709 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 315712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315714 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315716 */     GIR_RootConstrainSelectedInstOperands,
     /* 315717 */     // GIR_Coverage, 5245,
     /* 315717 */     GIR_EraseRootFromParent_Done,
     /* 315718 */   // Label 6213: @315718
     /* 315718 */   GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(315755), // Rule ID 5252 //
     /* 315723 */     // MIs[0] Operand 1
     /* 315723 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 315728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 315732 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315738 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315740 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315744 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315746 */     // (setcc:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, V64:{ *:[v4i16] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 315749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315751 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 315753 */     GIR_RootConstrainSelectedInstOperands,
     /* 315754 */     // GIR_Coverage, 5252,
     /* 315754 */     GIR_EraseRootFromParent_Done,
     /* 315755 */   // Label 6214: @315755
     /* 315755 */   GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(315795), // Rule ID 754 //
     /* 315760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315763 */     // MIs[0] Operand 1
     /* 315763 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 315768 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315776 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315782 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315784 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315786 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 315789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315791 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315793 */     GIR_RootConstrainSelectedInstOperands,
     /* 315794 */     // GIR_Coverage, 754,
     /* 315794 */     GIR_EraseRootFromParent_Done,
     /* 315795 */   // Label 6215: @315795
     /* 315795 */   GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(315835), // Rule ID 763 //
     /* 315800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315803 */     // MIs[0] Operand 1
     /* 315803 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315808 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315812 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315816 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315822 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315824 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315826 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 315829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315833 */     GIR_RootConstrainSelectedInstOperands,
     /* 315834 */     // GIR_Coverage, 763,
     /* 315834 */     GIR_EraseRootFromParent_Done,
     /* 315835 */   // Label 6216: @315835
     /* 315835 */   GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(315875), // Rule ID 764 //
     /* 315840 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315843 */     // MIs[0] Operand 1
     /* 315843 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315848 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315856 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315862 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 315864 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315866 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllOnesV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 315869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315871 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315873 */     GIR_RootConstrainSelectedInstOperands,
     /* 315874 */     // GIR_Coverage, 764,
     /* 315874 */     GIR_EraseRootFromParent_Done,
     /* 315875 */   // Label 6217: @315875
     /* 315875 */   GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(315915), // Rule ID 775 //
     /* 315880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 315883 */     // MIs[0] Operand 1
     /* 315883 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315888 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315892 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315896 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315902 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315904 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315906 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 315909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315911 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315913 */     GIR_RootConstrainSelectedInstOperands,
     /* 315914 */     // GIR_Coverage, 775,
     /* 315914 */     GIR_EraseRootFromParent_Done,
     /* 315915 */   // Label 6218: @315915
     /* 315915 */   GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(315952), // Rule ID 5189 //
     /* 315920 */     // MIs[0] Operand 1
     /* 315920 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 315925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315929 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315933 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315939 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315941 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315943 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315943 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16rz),
     /* 315946 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315948 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315950 */     GIR_RootConstrainSelectedInstOperands,
     /* 315951 */     // GIR_Coverage, 5189,
     /* 315951 */     GIR_EraseRootFromParent_Done,
     /* 315952 */   // Label 6219: @315952
     /* 315952 */   GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(315989), // Rule ID 5196 //
     /* 315957 */     // MIs[0] Operand 1
     /* 315957 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 315962 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 315966 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 315970 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 315976 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 315978 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 315980 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGT:{ *:[Other] })  =>  (CMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 315980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16rz),
     /* 315983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 315985 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 315987 */     GIR_RootConstrainSelectedInstOperands,
     /* 315988 */     // GIR_Coverage, 5196,
     /* 315988 */     GIR_EraseRootFromParent_Done,
     /* 315989 */   // Label 6220: @315989
     /* 315989 */   GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(316026), // Rule ID 5203 //
     /* 315994 */     // MIs[0] Operand 1
     /* 315994 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 315999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316003 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316007 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316013 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316015 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316017 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETGE:{ *:[Other] })  =>  (CMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 316017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16rz),
     /* 316020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316024 */     GIR_RootConstrainSelectedInstOperands,
     /* 316025 */     // GIR_Coverage, 5203,
     /* 316025 */     GIR_EraseRootFromParent_Done,
     /* 316026 */   // Label 6221: @316026
     /* 316026 */   GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(316063), // Rule ID 5210 //
     /* 316031 */     // MIs[0] Operand 1
     /* 316031 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 316036 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316044 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316050 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316052 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316054 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLT:{ *:[Other] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 316054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 316057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316059 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316061 */     GIR_RootConstrainSelectedInstOperands,
     /* 316062 */     // GIR_Coverage, 5210,
     /* 316062 */     GIR_EraseRootFromParent_Done,
     /* 316063 */   // Label 6222: @316063
     /* 316063 */   GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(316100), // Rule ID 5217 //
     /* 316068 */     // MIs[0] Operand 1
     /* 316068 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 316073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316077 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316081 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316087 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316089 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316091 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, immAllZerosV:{ *:[v4i16] }, SETLE:{ *:[Other] })  =>  (CMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 316091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i16rz),
     /* 316094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316096 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316098 */     GIR_RootConstrainSelectedInstOperands,
     /* 316099 */     // GIR_Coverage, 5217,
     /* 316099 */     GIR_EraseRootFromParent_Done,
     /* 316100 */   // Label 6223: @316100
     /* 316100 */   GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(316132), // Rule ID 1153 //
     /* 316105 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316108 */     // MIs[0] Operand 1
     /* 316108 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 316113 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316117 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316121 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16),
     /* 316124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316126 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316128 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316130 */     GIR_RootConstrainSelectedInstOperands,
     /* 316131 */     // GIR_Coverage, 1153,
     /* 316131 */     GIR_EraseRootFromParent_Done,
     /* 316132 */   // Label 6224: @316132
     /* 316132 */   GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(316164), // Rule ID 1160 //
     /* 316137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316140 */     // MIs[0] Operand 1
     /* 316140 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 316145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316153 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 316156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316158 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316160 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316162 */     GIR_RootConstrainSelectedInstOperands,
     /* 316163 */     // GIR_Coverage, 1160,
     /* 316163 */     GIR_EraseRootFromParent_Done,
     /* 316164 */   // Label 6225: @316164
     /* 316164 */   GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(316196), // Rule ID 1167 //
     /* 316169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316172 */     // MIs[0] Operand 1
     /* 316172 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316177 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316181 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316185 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 316188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316190 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316192 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316194 */     GIR_RootConstrainSelectedInstOperands,
     /* 316195 */     // GIR_Coverage, 1167,
     /* 316195 */     GIR_EraseRootFromParent_Done,
     /* 316196 */   // Label 6226: @316196
     /* 316196 */   GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(316228), // Rule ID 1174 //
     /* 316201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316204 */     // MIs[0] Operand 1
     /* 316204 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 316209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316213 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316217 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 316220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316224 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316226 */     GIR_RootConstrainSelectedInstOperands,
     /* 316227 */     // GIR_Coverage, 1174,
     /* 316227 */     GIR_EraseRootFromParent_Done,
     /* 316228 */   // Label 6227: @316228
     /* 316228 */   GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(316260), // Rule ID 1181 //
     /* 316233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316236 */     // MIs[0] Operand 1
     /* 316236 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 316241 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316245 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316249 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 316252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316258 */     GIR_RootConstrainSelectedInstOperands,
     /* 316259 */     // GIR_Coverage, 1181,
     /* 316259 */     GIR_EraseRootFromParent_Done,
     /* 316260 */   // Label 6228: @316260
     /* 316260 */   GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(316289), // Rule ID 5126 //
     /* 316265 */     // MIs[0] Operand 1
     /* 316265 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 316270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316274 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316278 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i16),
     /* 316281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316283 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316285 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316287 */     GIR_RootConstrainSelectedInstOperands,
     /* 316288 */     // GIR_Coverage, 5126,
     /* 316288 */     GIR_EraseRootFromParent_Done,
     /* 316289 */   // Label 6229: @316289
     /* 316289 */   GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(316318), // Rule ID 5133 //
     /* 316294 */     // MIs[0] Operand 1
     /* 316294 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316307 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316307 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 316310 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316316 */     GIR_RootConstrainSelectedInstOperands,
     /* 316317 */     // GIR_Coverage, 5133,
     /* 316317 */     GIR_EraseRootFromParent_Done,
     /* 316318 */   // Label 6230: @316318
     /* 316318 */   GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(316347), // Rule ID 5140 //
     /* 316323 */     // MIs[0] Operand 1
     /* 316323 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 316328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316336 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 316339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316341 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316343 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316345 */     GIR_RootConstrainSelectedInstOperands,
     /* 316346 */     // GIR_Coverage, 5140,
     /* 316346 */     GIR_EraseRootFromParent_Done,
     /* 316347 */   // Label 6231: @316347
     /* 316347 */   GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(316376), // Rule ID 5147 //
     /* 316352 */     // MIs[0] Operand 1
     /* 316352 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 316357 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316361 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316365 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 316368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316370 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316372 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316374 */     GIR_RootConstrainSelectedInstOperands,
     /* 316375 */     // GIR_Coverage, 5147,
     /* 316375 */     GIR_EraseRootFromParent_Done,
     /* 316376 */   // Label 6232: @316376
     /* 316376 */   GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(316405), // Rule ID 5154 //
     /* 316381 */     // MIs[0] Operand 1
     /* 316381 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 316386 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316390 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316394 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 316394 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 316397 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316399 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316401 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316403 */     GIR_RootConstrainSelectedInstOperands,
     /* 316404 */     // GIR_Coverage, 5154,
     /* 316404 */     GIR_EraseRootFromParent_Done,
     /* 316405 */   // Label 6233: @316405
     /* 316405 */   GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(316434), // Rule ID 5161 //
     /* 316410 */     // MIs[0] Operand 1
     /* 316410 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 316415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316419 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316423 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 316423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i16),
     /* 316426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316428 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316430 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316432 */     GIR_RootConstrainSelectedInstOperands,
     /* 316433 */     // GIR_Coverage, 5161,
     /* 316433 */     GIR_EraseRootFromParent_Done,
     /* 316434 */   // Label 6234: @316434
     /* 316434 */   GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(316463), // Rule ID 5168 //
     /* 316439 */     // MIs[0] Operand 1
     /* 316439 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 316444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316452 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 316452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i16),
     /* 316455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316457 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316459 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316461 */     GIR_RootConstrainSelectedInstOperands,
     /* 316462 */     // GIR_Coverage, 5168,
     /* 316462 */     GIR_EraseRootFromParent_Done,
     /* 316463 */   // Label 6235: @316463
     /* 316463 */   GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(316492), // Rule ID 5175 //
     /* 316468 */     // MIs[0] Operand 1
     /* 316468 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 316473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316481 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 316481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i16),
     /* 316484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316486 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316490 */     GIR_RootConstrainSelectedInstOperands,
     /* 316491 */     // GIR_Coverage, 5175,
     /* 316491 */     GIR_EraseRootFromParent_Done,
     /* 316492 */   // Label 6236: @316492
     /* 316492 */   GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(316521), // Rule ID 5182 //
     /* 316497 */     // MIs[0] Operand 1
     /* 316497 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 316502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316506 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 316510 */     // (setcc:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rm, V64:{ *:[v4i16] }:$Rn)
     /* 316510 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i16),
     /* 316513 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316515 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 316517 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316519 */     GIR_RootConstrainSelectedInstOperands,
     /* 316520 */     // GIR_Coverage, 5182,
     /* 316520 */     GIR_EraseRootFromParent_Done,
     /* 316521 */   // Label 6237: @316521
     /* 316521 */   GIM_Reject,
     /* 316522 */ // Label 6207: @316522
     /* 316522 */ GIM_Reject,
     /* 316523 */ // Label 6128: @316523
     /* 316523 */ GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(317570),
     /* 316528 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 316531 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 316534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316538 */   GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(316578), // Rule ID 785 //
     /* 316543 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316546 */     // MIs[0] Operand 1
     /* 316546 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 316551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316555 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316561 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316563 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316567 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316569 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 316572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316574 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316576 */     GIR_RootConstrainSelectedInstOperands,
     /* 316577 */     // GIR_Coverage, 785,
     /* 316577 */     GIR_EraseRootFromParent_Done,
     /* 316578 */   // Label 6239: @316578
     /* 316578 */   GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(316618), // Rule ID 792 //
     /* 316583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316586 */     // MIs[0] Operand 1
     /* 316586 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316595 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316601 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316603 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316607 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316609 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 316612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316616 */     GIR_RootConstrainSelectedInstOperands,
     /* 316617 */     // GIR_Coverage, 792,
     /* 316617 */     GIR_EraseRootFromParent_Done,
     /* 316618 */   // Label 6240: @316618
     /* 316618 */   GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(316655), // Rule ID 5227 //
     /* 316623 */     // MIs[0] Operand 1
     /* 316623 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 316628 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316632 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316638 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316640 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316644 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316646 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 316649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316651 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316653 */     GIR_RootConstrainSelectedInstOperands,
     /* 316654 */     // GIR_Coverage, 5227,
     /* 316654 */     GIR_EraseRootFromParent_Done,
     /* 316655 */   // Label 6241: @316655
     /* 316655 */   GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(316692), // Rule ID 5234 //
     /* 316660 */     // MIs[0] Operand 1
     /* 316660 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316669 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316675 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316677 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316681 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316683 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 316686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316688 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316690 */     GIR_RootConstrainSelectedInstOperands,
     /* 316691 */     // GIR_Coverage, 5234,
     /* 316691 */     GIR_EraseRootFromParent_Done,
     /* 316692 */   // Label 6242: @316692
     /* 316692 */   GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(316729), // Rule ID 5241 //
     /* 316697 */     // MIs[0] Operand 1
     /* 316697 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 316702 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316706 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316712 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316714 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316718 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316720 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316720 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 316723 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316725 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316727 */     GIR_RootConstrainSelectedInstOperands,
     /* 316728 */     // GIR_Coverage, 5241,
     /* 316728 */     GIR_EraseRootFromParent_Done,
     /* 316729 */   // Label 6243: @316729
     /* 316729 */   GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(316766), // Rule ID 5248 //
     /* 316734 */     // MIs[0] Operand 1
     /* 316734 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 316739 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316743 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316749 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316751 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316755 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316757 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 316760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316762 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316764 */     GIR_RootConstrainSelectedInstOperands,
     /* 316765 */     // GIR_Coverage, 5248,
     /* 316765 */     GIR_EraseRootFromParent_Done,
     /* 316766 */   // Label 6244: @316766
     /* 316766 */   GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(316803), // Rule ID 5255 //
     /* 316771 */     // MIs[0] Operand 1
     /* 316771 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 316776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 316780 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316786 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316788 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316792 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316794 */     // (setcc:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, V128:{ *:[v4i32] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 316797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316799 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 316801 */     GIR_RootConstrainSelectedInstOperands,
     /* 316802 */     // GIR_Coverage, 5255,
     /* 316802 */     GIR_EraseRootFromParent_Done,
     /* 316803 */   // Label 6245: @316803
     /* 316803 */   GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(316843), // Rule ID 757 //
     /* 316808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316811 */     // MIs[0] Operand 1
     /* 316811 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 316816 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316824 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316830 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316832 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316834 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 316837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316839 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316841 */     GIR_RootConstrainSelectedInstOperands,
     /* 316842 */     // GIR_Coverage, 757,
     /* 316842 */     GIR_EraseRootFromParent_Done,
     /* 316843 */   // Label 6246: @316843
     /* 316843 */   GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(316883), // Rule ID 769 //
     /* 316848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316851 */     // MIs[0] Operand 1
     /* 316851 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 316856 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316860 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316864 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316870 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316872 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316874 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 316877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316879 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316881 */     GIR_RootConstrainSelectedInstOperands,
     /* 316882 */     // GIR_Coverage, 769,
     /* 316882 */     GIR_EraseRootFromParent_Done,
     /* 316883 */   // Label 6247: @316883
     /* 316883 */   GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(316923), // Rule ID 770 //
     /* 316888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316891 */     // MIs[0] Operand 1
     /* 316891 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316896 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316904 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316910 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 316912 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316914 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllOnesV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316914 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 316917 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316919 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316921 */     GIR_RootConstrainSelectedInstOperands,
     /* 316922 */     // GIR_Coverage, 770,
     /* 316922 */     GIR_EraseRootFromParent_Done,
     /* 316923 */   // Label 6248: @316923
     /* 316923 */   GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(316963), // Rule ID 778 //
     /* 316928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 316931 */     // MIs[0] Operand 1
     /* 316931 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 316936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316944 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316950 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316952 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316954 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 316957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316959 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316961 */     GIR_RootConstrainSelectedInstOperands,
     /* 316962 */     // GIR_Coverage, 778,
     /* 316962 */     GIR_EraseRootFromParent_Done,
     /* 316963 */   // Label 6249: @316963
     /* 316963 */   GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(317000), // Rule ID 5192 //
     /* 316968 */     // MIs[0] Operand 1
     /* 316968 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 316973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 316977 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 316981 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 316987 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 316989 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 316991 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETEQ:{ *:[Other] })  =>  (CMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 316991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32rz),
     /* 316994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 316996 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 316998 */     GIR_RootConstrainSelectedInstOperands,
     /* 316999 */     // GIR_Coverage, 5192,
     /* 316999 */     GIR_EraseRootFromParent_Done,
     /* 317000 */   // Label 6250: @317000
     /* 317000 */   GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(317037), // Rule ID 5199 //
     /* 317005 */     // MIs[0] Operand 1
     /* 317005 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317014 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317018 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317024 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317026 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317028 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGT:{ *:[Other] })  =>  (CMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 317028 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32rz),
     /* 317031 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317033 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317035 */     GIR_RootConstrainSelectedInstOperands,
     /* 317036 */     // GIR_Coverage, 5199,
     /* 317036 */     GIR_EraseRootFromParent_Done,
     /* 317037 */   // Label 6251: @317037
     /* 317037 */   GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(317074), // Rule ID 5206 //
     /* 317042 */     // MIs[0] Operand 1
     /* 317042 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317047 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317051 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317055 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317061 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317063 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317065 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETGE:{ *:[Other] })  =>  (CMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 317065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32rz),
     /* 317068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317070 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317072 */     GIR_RootConstrainSelectedInstOperands,
     /* 317073 */     // GIR_Coverage, 5206,
     /* 317073 */     GIR_EraseRootFromParent_Done,
     /* 317074 */   // Label 6252: @317074
     /* 317074 */   GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(317111), // Rule ID 5213 //
     /* 317079 */     // MIs[0] Operand 1
     /* 317079 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 317084 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317088 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317092 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317098 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317100 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317102 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLT:{ *:[Other] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 317102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 317105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317107 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317109 */     GIR_RootConstrainSelectedInstOperands,
     /* 317110 */     // GIR_Coverage, 5213,
     /* 317110 */     GIR_EraseRootFromParent_Done,
     /* 317111 */   // Label 6253: @317111
     /* 317111 */   GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(317148), // Rule ID 5220 //
     /* 317116 */     // MIs[0] Operand 1
     /* 317116 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 317121 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317129 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317135 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317137 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317139 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, immAllZerosV:{ *:[v4i32] }, SETLE:{ *:[Other] })  =>  (CMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 317139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv4i32rz),
     /* 317142 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317144 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317146 */     GIR_RootConstrainSelectedInstOperands,
     /* 317147 */     // GIR_Coverage, 5220,
     /* 317147 */     GIR_EraseRootFromParent_Done,
     /* 317148 */   // Label 6254: @317148
     /* 317148 */   GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(317180), // Rule ID 1156 //
     /* 317153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317156 */     // MIs[0] Operand 1
     /* 317156 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 317161 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317165 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317169 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317169 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32),
     /* 317172 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317176 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317178 */     GIR_RootConstrainSelectedInstOperands,
     /* 317179 */     // GIR_Coverage, 1156,
     /* 317179 */     GIR_EraseRootFromParent_Done,
     /* 317180 */   // Label 6255: @317180
     /* 317180 */   GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(317212), // Rule ID 1163 //
     /* 317185 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317188 */     // MIs[0] Operand 1
     /* 317188 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317197 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317201 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 317204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317206 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317208 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317210 */     GIR_RootConstrainSelectedInstOperands,
     /* 317211 */     // GIR_Coverage, 1163,
     /* 317211 */     GIR_EraseRootFromParent_Done,
     /* 317212 */   // Label 6256: @317212
     /* 317212 */   GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(317244), // Rule ID 1170 //
     /* 317217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317220 */     // MIs[0] Operand 1
     /* 317220 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317233 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 317236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317238 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317242 */     GIR_RootConstrainSelectedInstOperands,
     /* 317243 */     // GIR_Coverage, 1170,
     /* 317243 */     GIR_EraseRootFromParent_Done,
     /* 317244 */   // Label 6257: @317244
     /* 317244 */   GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(317276), // Rule ID 1177 //
     /* 317249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317252 */     // MIs[0] Operand 1
     /* 317252 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 317257 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317261 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317265 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 317268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317274 */     GIR_RootConstrainSelectedInstOperands,
     /* 317275 */     // GIR_Coverage, 1177,
     /* 317275 */     GIR_EraseRootFromParent_Done,
     /* 317276 */   // Label 6258: @317276
     /* 317276 */   GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(317308), // Rule ID 1184 //
     /* 317281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317284 */     // MIs[0] Operand 1
     /* 317284 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 317289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317297 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 317300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317306 */     GIR_RootConstrainSelectedInstOperands,
     /* 317307 */     // GIR_Coverage, 1184,
     /* 317307 */     GIR_EraseRootFromParent_Done,
     /* 317308 */   // Label 6259: @317308
     /* 317308 */   GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(317337), // Rule ID 5129 //
     /* 317313 */     // MIs[0] Operand 1
     /* 317313 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 317318 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317322 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317326 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv4i32),
     /* 317329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317331 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317333 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317335 */     GIR_RootConstrainSelectedInstOperands,
     /* 317336 */     // GIR_Coverage, 5129,
     /* 317336 */     GIR_EraseRootFromParent_Done,
     /* 317337 */   // Label 6260: @317337
     /* 317337 */   GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(317366), // Rule ID 5136 //
     /* 317342 */     // MIs[0] Operand 1
     /* 317342 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317347 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317351 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317355 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317355 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 317358 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317362 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317364 */     GIR_RootConstrainSelectedInstOperands,
     /* 317365 */     // GIR_Coverage, 5136,
     /* 317365 */     GIR_EraseRootFromParent_Done,
     /* 317366 */   // Label 6261: @317366
     /* 317366 */   GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(317395), // Rule ID 5143 //
     /* 317371 */     // MIs[0] Operand 1
     /* 317371 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317380 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317384 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 317387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317389 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317391 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317393 */     GIR_RootConstrainSelectedInstOperands,
     /* 317394 */     // GIR_Coverage, 5143,
     /* 317394 */     GIR_EraseRootFromParent_Done,
     /* 317395 */   // Label 6262: @317395
     /* 317395 */   GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(317424), // Rule ID 5150 //
     /* 317400 */     // MIs[0] Operand 1
     /* 317400 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 317405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317409 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317413 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 317416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317422 */     GIR_RootConstrainSelectedInstOperands,
     /* 317423 */     // GIR_Coverage, 5150,
     /* 317423 */     GIR_EraseRootFromParent_Done,
     /* 317424 */   // Label 6263: @317424
     /* 317424 */   GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(317453), // Rule ID 5157 //
     /* 317429 */     // MIs[0] Operand 1
     /* 317429 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 317434 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317438 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317442 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 317442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 317445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317449 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317451 */     GIR_RootConstrainSelectedInstOperands,
     /* 317452 */     // GIR_Coverage, 5157,
     /* 317452 */     GIR_EraseRootFromParent_Done,
     /* 317453 */   // Label 6264: @317453
     /* 317453 */   GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(317482), // Rule ID 5164 //
     /* 317458 */     // MIs[0] Operand 1
     /* 317458 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 317463 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317467 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317471 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 317471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv4i32),
     /* 317474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317476 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317478 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317480 */     GIR_RootConstrainSelectedInstOperands,
     /* 317481 */     // GIR_Coverage, 5164,
     /* 317481 */     GIR_EraseRootFromParent_Done,
     /* 317482 */   // Label 6265: @317482
     /* 317482 */   GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(317511), // Rule ID 5171 //
     /* 317487 */     // MIs[0] Operand 1
     /* 317487 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 317492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317496 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317500 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 317500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv4i32),
     /* 317503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317509 */     GIR_RootConstrainSelectedInstOperands,
     /* 317510 */     // GIR_Coverage, 5171,
     /* 317510 */     GIR_EraseRootFromParent_Done,
     /* 317511 */   // Label 6266: @317511
     /* 317511 */   GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(317540), // Rule ID 5178 //
     /* 317516 */     // MIs[0] Operand 1
     /* 317516 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 317521 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317525 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317529 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 317529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv4i32),
     /* 317532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317534 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317536 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317538 */     GIR_RootConstrainSelectedInstOperands,
     /* 317539 */     // GIR_Coverage, 5178,
     /* 317539 */     GIR_EraseRootFromParent_Done,
     /* 317540 */   // Label 6267: @317540
     /* 317540 */   GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(317569), // Rule ID 5185 //
     /* 317545 */     // MIs[0] Operand 1
     /* 317545 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 317550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317554 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 317558 */     // (setcc:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, V128:{ *:[v4i32] }:$Rn)
     /* 317558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv4i32),
     /* 317561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317563 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 317565 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317567 */     GIR_RootConstrainSelectedInstOperands,
     /* 317568 */     // GIR_Coverage, 5185,
     /* 317568 */     GIR_EraseRootFromParent_Done,
     /* 317569 */   // Label 6268: @317569
     /* 317569 */   GIM_Reject,
     /* 317570 */ // Label 6238: @317570
     /* 317570 */ GIM_Reject,
     /* 317571 */ // Label 6129: @317571
     /* 317571 */ GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(318618),
     /* 317576 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 317579 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 317582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317586 */   GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(317626), // Rule ID 780 //
     /* 317591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317594 */     // MIs[0] Operand 1
     /* 317594 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317599 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317603 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317609 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317611 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317617 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 317620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317622 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317624 */     GIR_RootConstrainSelectedInstOperands,
     /* 317625 */     // GIR_Coverage, 780,
     /* 317625 */     GIR_EraseRootFromParent_Done,
     /* 317626 */   // Label 6270: @317626
     /* 317626 */   GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(317666), // Rule ID 787 //
     /* 317631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317634 */     // MIs[0] Operand 1
     /* 317634 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317643 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317649 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317651 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317655 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317657 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 317660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317662 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317664 */     GIR_RootConstrainSelectedInstOperands,
     /* 317665 */     // GIR_Coverage, 787,
     /* 317665 */     GIR_EraseRootFromParent_Done,
     /* 317666 */   // Label 6271: @317666
     /* 317666 */   GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(317703), // Rule ID 5222 //
     /* 317671 */     // MIs[0] Operand 1
     /* 317671 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 317676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317680 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317686 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317688 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317692 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317694 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317694 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 317697 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317699 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317701 */     GIR_RootConstrainSelectedInstOperands,
     /* 317702 */     // GIR_Coverage, 5222,
     /* 317702 */     GIR_EraseRootFromParent_Done,
     /* 317703 */   // Label 6272: @317703
     /* 317703 */   GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(317740), // Rule ID 5229 //
     /* 317708 */     // MIs[0] Operand 1
     /* 317708 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317713 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317717 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317723 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317725 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317729 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317731 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 317734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317736 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317738 */     GIR_RootConstrainSelectedInstOperands,
     /* 317739 */     // GIR_Coverage, 5229,
     /* 317739 */     GIR_EraseRootFromParent_Done,
     /* 317740 */   // Label 6273: @317740
     /* 317740 */   GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(317777), // Rule ID 5236 //
     /* 317745 */     // MIs[0] Operand 1
     /* 317745 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317750 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317754 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317760 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317762 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317766 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317768 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 317771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317773 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317775 */     GIR_RootConstrainSelectedInstOperands,
     /* 317776 */     // GIR_Coverage, 5236,
     /* 317776 */     GIR_EraseRootFromParent_Done,
     /* 317777 */   // Label 6274: @317777
     /* 317777 */   GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(317814), // Rule ID 5243 //
     /* 317782 */     // MIs[0] Operand 1
     /* 317782 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 317787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317791 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317797 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317799 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317803 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317805 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 317808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317810 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317812 */     GIR_RootConstrainSelectedInstOperands,
     /* 317813 */     // GIR_Coverage, 5243,
     /* 317813 */     GIR_EraseRootFromParent_Done,
     /* 317814 */   // Label 6275: @317814
     /* 317814 */   GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(317851), // Rule ID 5250 //
     /* 317819 */     // MIs[0] Operand 1
     /* 317819 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 317824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 317828 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317834 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317836 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317840 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317842 */     // (setcc:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, V64:{ *:[v8i8] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 317845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317847 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 317849 */     GIR_RootConstrainSelectedInstOperands,
     /* 317850 */     // GIR_Coverage, 5250,
     /* 317850 */     GIR_EraseRootFromParent_Done,
     /* 317851 */   // Label 6276: @317851
     /* 317851 */   GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(317891), // Rule ID 752 //
     /* 317856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317859 */     // MIs[0] Operand 1
     /* 317859 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 317864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317868 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317872 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317878 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317880 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317882 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 317885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317889 */     GIR_RootConstrainSelectedInstOperands,
     /* 317890 */     // GIR_Coverage, 752,
     /* 317890 */     GIR_EraseRootFromParent_Done,
     /* 317891 */   // Label 6277: @317891
     /* 317891 */   GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(317931), // Rule ID 759 //
     /* 317896 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317899 */     // MIs[0] Operand 1
     /* 317899 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 317904 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317912 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317918 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 317920 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317922 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 317925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317927 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317929 */     GIR_RootConstrainSelectedInstOperands,
     /* 317930 */     // GIR_Coverage, 759,
     /* 317930 */     GIR_EraseRootFromParent_Done,
     /* 317931 */   // Label 6278: @317931
     /* 317931 */   GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(317971), // Rule ID 760 //
     /* 317936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317939 */     // MIs[0] Operand 1
     /* 317939 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317948 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317952 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317958 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 317960 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 317962 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllOnesV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 317962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 317965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 317967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 317969 */     GIR_RootConstrainSelectedInstOperands,
     /* 317970 */     // GIR_Coverage, 760,
     /* 317970 */     GIR_EraseRootFromParent_Done,
     /* 317971 */   // Label 6279: @317971
     /* 317971 */   GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(318011), // Rule ID 773 //
     /* 317976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 317979 */     // MIs[0] Operand 1
     /* 317979 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 317984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 317988 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 317992 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 317998 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318000 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318002 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318002 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 318005 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318007 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318009 */     GIR_RootConstrainSelectedInstOperands,
     /* 318010 */     // GIR_Coverage, 773,
     /* 318010 */     GIR_EraseRootFromParent_Done,
     /* 318011 */   // Label 6280: @318011
     /* 318011 */   GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(318048), // Rule ID 5187 //
     /* 318016 */     // MIs[0] Operand 1
     /* 318016 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 318021 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318025 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318029 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318035 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318037 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318039 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8rz),
     /* 318042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318046 */     GIR_RootConstrainSelectedInstOperands,
     /* 318047 */     // GIR_Coverage, 5187,
     /* 318047 */     GIR_EraseRootFromParent_Done,
     /* 318048 */   // Label 6281: @318048
     /* 318048 */   GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(318085), // Rule ID 5194 //
     /* 318053 */     // MIs[0] Operand 1
     /* 318053 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318066 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318072 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318074 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318076 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGT:{ *:[Other] })  =>  (CMGTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8rz),
     /* 318079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318081 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318083 */     GIR_RootConstrainSelectedInstOperands,
     /* 318084 */     // GIR_Coverage, 5194,
     /* 318084 */     GIR_EraseRootFromParent_Done,
     /* 318085 */   // Label 6282: @318085
     /* 318085 */   GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(318122), // Rule ID 5201 //
     /* 318090 */     // MIs[0] Operand 1
     /* 318090 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318095 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318103 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318109 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318111 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318113 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETGE:{ *:[Other] })  =>  (CMGEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8rz),
     /* 318116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318118 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318120 */     GIR_RootConstrainSelectedInstOperands,
     /* 318121 */     // GIR_Coverage, 5201,
     /* 318121 */     GIR_EraseRootFromParent_Done,
     /* 318122 */   // Label 6283: @318122
     /* 318122 */   GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(318159), // Rule ID 5208 //
     /* 318127 */     // MIs[0] Operand 1
     /* 318127 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 318132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318136 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318140 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318146 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318148 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318150 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLT:{ *:[Other] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 318153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318157 */     GIR_RootConstrainSelectedInstOperands,
     /* 318158 */     // GIR_Coverage, 5208,
     /* 318158 */     GIR_EraseRootFromParent_Done,
     /* 318159 */   // Label 6284: @318159
     /* 318159 */   GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(318196), // Rule ID 5215 //
     /* 318164 */     // MIs[0] Operand 1
     /* 318164 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 318169 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318173 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318177 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318183 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318185 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318187 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, immAllZerosV:{ *:[v8i8] }, SETLE:{ *:[Other] })  =>  (CMLEv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 318187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i8rz),
     /* 318190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318194 */     GIR_RootConstrainSelectedInstOperands,
     /* 318195 */     // GIR_Coverage, 5215,
     /* 318195 */     GIR_EraseRootFromParent_Done,
     /* 318196 */   // Label 6285: @318196
     /* 318196 */   GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(318228), // Rule ID 1151 //
     /* 318201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318204 */     // MIs[0] Operand 1
     /* 318204 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 318209 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318213 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318217 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318217 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8),
     /* 318220 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318222 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318224 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318226 */     GIR_RootConstrainSelectedInstOperands,
     /* 318227 */     // GIR_Coverage, 1151,
     /* 318227 */     GIR_EraseRootFromParent_Done,
     /* 318228 */   // Label 6286: @318228
     /* 318228 */   GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(318260), // Rule ID 1158 //
     /* 318233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318236 */     // MIs[0] Operand 1
     /* 318236 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318241 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318245 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318249 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 318252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318254 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318256 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318258 */     GIR_RootConstrainSelectedInstOperands,
     /* 318259 */     // GIR_Coverage, 1158,
     /* 318259 */     GIR_EraseRootFromParent_Done,
     /* 318260 */   // Label 6287: @318260
     /* 318260 */   GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(318292), // Rule ID 1165 //
     /* 318265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318268 */     // MIs[0] Operand 1
     /* 318268 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318273 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318277 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318281 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 318284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318286 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318288 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318290 */     GIR_RootConstrainSelectedInstOperands,
     /* 318291 */     // GIR_Coverage, 1165,
     /* 318291 */     GIR_EraseRootFromParent_Done,
     /* 318292 */   // Label 6288: @318292
     /* 318292 */   GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(318324), // Rule ID 1172 //
     /* 318297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318300 */     // MIs[0] Operand 1
     /* 318300 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 318305 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318309 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318313 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 318316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318320 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318322 */     GIR_RootConstrainSelectedInstOperands,
     /* 318323 */     // GIR_Coverage, 1172,
     /* 318323 */     GIR_EraseRootFromParent_Done,
     /* 318324 */   // Label 6289: @318324
     /* 318324 */   GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(318356), // Rule ID 1179 //
     /* 318329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318332 */     // MIs[0] Operand 1
     /* 318332 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 318337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318341 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318345 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 318348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318350 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318352 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318354 */     GIR_RootConstrainSelectedInstOperands,
     /* 318355 */     // GIR_Coverage, 1179,
     /* 318355 */     GIR_EraseRootFromParent_Done,
     /* 318356 */   // Label 6290: @318356
     /* 318356 */   GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(318385), // Rule ID 5124 //
     /* 318361 */     // MIs[0] Operand 1
     /* 318361 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 318366 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318370 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318374 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i8),
     /* 318377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318379 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318383 */     GIR_RootConstrainSelectedInstOperands,
     /* 318384 */     // GIR_Coverage, 5124,
     /* 318384 */     GIR_EraseRootFromParent_Done,
     /* 318385 */   // Label 6291: @318385
     /* 318385 */   GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(318414), // Rule ID 5131 //
     /* 318390 */     // MIs[0] Operand 1
     /* 318390 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318399 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318403 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318403 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 318406 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318408 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318410 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318412 */     GIR_RootConstrainSelectedInstOperands,
     /* 318413 */     // GIR_Coverage, 5131,
     /* 318413 */     GIR_EraseRootFromParent_Done,
     /* 318414 */   // Label 6292: @318414
     /* 318414 */   GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(318443), // Rule ID 5138 //
     /* 318419 */     // MIs[0] Operand 1
     /* 318419 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318428 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318432 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 318435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318439 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318441 */     GIR_RootConstrainSelectedInstOperands,
     /* 318442 */     // GIR_Coverage, 5138,
     /* 318442 */     GIR_EraseRootFromParent_Done,
     /* 318443 */   // Label 6293: @318443
     /* 318443 */   GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(318472), // Rule ID 5145 //
     /* 318448 */     // MIs[0] Operand 1
     /* 318448 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 318453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318457 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318461 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 318464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318466 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318468 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318470 */     GIR_RootConstrainSelectedInstOperands,
     /* 318471 */     // GIR_Coverage, 5145,
     /* 318471 */     GIR_EraseRootFromParent_Done,
     /* 318472 */   // Label 6294: @318472
     /* 318472 */   GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(318501), // Rule ID 5152 //
     /* 318477 */     // MIs[0] Operand 1
     /* 318477 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 318482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318486 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318490 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 318490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 318493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318495 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318497 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318499 */     GIR_RootConstrainSelectedInstOperands,
     /* 318500 */     // GIR_Coverage, 5152,
     /* 318500 */     GIR_EraseRootFromParent_Done,
     /* 318501 */   // Label 6295: @318501
     /* 318501 */   GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(318530), // Rule ID 5159 //
     /* 318506 */     // MIs[0] Operand 1
     /* 318506 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 318511 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318515 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318519 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 318519 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i8),
     /* 318522 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318524 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318526 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318528 */     GIR_RootConstrainSelectedInstOperands,
     /* 318529 */     // GIR_Coverage, 5159,
     /* 318529 */     GIR_EraseRootFromParent_Done,
     /* 318530 */   // Label 6296: @318530
     /* 318530 */   GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(318559), // Rule ID 5166 //
     /* 318535 */     // MIs[0] Operand 1
     /* 318535 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 318540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318548 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 318548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i8),
     /* 318551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318553 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318557 */     GIR_RootConstrainSelectedInstOperands,
     /* 318558 */     // GIR_Coverage, 5166,
     /* 318558 */     GIR_EraseRootFromParent_Done,
     /* 318559 */   // Label 6297: @318559
     /* 318559 */   GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(318588), // Rule ID 5173 //
     /* 318564 */     // MIs[0] Operand 1
     /* 318564 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 318569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318573 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318577 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 318577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i8),
     /* 318580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318582 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318584 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318586 */     GIR_RootConstrainSelectedInstOperands,
     /* 318587 */     // GIR_Coverage, 5173,
     /* 318587 */     GIR_EraseRootFromParent_Done,
     /* 318588 */   // Label 6298: @318588
     /* 318588 */   GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(318617), // Rule ID 5180 //
     /* 318593 */     // MIs[0] Operand 1
     /* 318593 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 318598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318602 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 318606 */     // (setcc:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rm, V64:{ *:[v8i8] }:$Rn)
     /* 318606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i8),
     /* 318609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318611 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 318613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318615 */     GIR_RootConstrainSelectedInstOperands,
     /* 318616 */     // GIR_Coverage, 5180,
     /* 318616 */     GIR_EraseRootFromParent_Done,
     /* 318617 */   // Label 6299: @318617
     /* 318617 */   GIM_Reject,
     /* 318618 */ // Label 6269: @318618
     /* 318618 */ GIM_Reject,
     /* 318619 */ // Label 6130: @318619
     /* 318619 */ GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(319666),
     /* 318624 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 318627 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 318630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318634 */   GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(318674), // Rule ID 783 //
     /* 318639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318642 */     // MIs[0] Operand 1
     /* 318642 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318647 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318651 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318657 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318659 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318663 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318665 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318665 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 318668 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318670 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318672 */     GIR_RootConstrainSelectedInstOperands,
     /* 318673 */     // GIR_Coverage, 783,
     /* 318673 */     GIR_EraseRootFromParent_Done,
     /* 318674 */   // Label 6301: @318674
     /* 318674 */   GIM_Try, /*On fail goto*//*Label 6302*/ GIMT_Encode4(318714), // Rule ID 790 //
     /* 318679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318682 */     // MIs[0] Operand 1
     /* 318682 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318687 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318691 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318697 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318699 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318703 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318705 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 318708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318710 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318712 */     GIR_RootConstrainSelectedInstOperands,
     /* 318713 */     // GIR_Coverage, 790,
     /* 318713 */     GIR_EraseRootFromParent_Done,
     /* 318714 */   // Label 6302: @318714
     /* 318714 */   GIM_Try, /*On fail goto*//*Label 6303*/ GIMT_Encode4(318751), // Rule ID 5225 //
     /* 318719 */     // MIs[0] Operand 1
     /* 318719 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 318724 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318728 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318734 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318736 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318740 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318742 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 318745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318747 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318749 */     GIR_RootConstrainSelectedInstOperands,
     /* 318750 */     // GIR_Coverage, 5225,
     /* 318750 */     GIR_EraseRootFromParent_Done,
     /* 318751 */   // Label 6303: @318751
     /* 318751 */   GIM_Try, /*On fail goto*//*Label 6304*/ GIMT_Encode4(318788), // Rule ID 5232 //
     /* 318756 */     // MIs[0] Operand 1
     /* 318756 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318765 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318771 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318773 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318777 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318779 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 318782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318784 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318786 */     GIR_RootConstrainSelectedInstOperands,
     /* 318787 */     // GIR_Coverage, 5232,
     /* 318787 */     GIR_EraseRootFromParent_Done,
     /* 318788 */   // Label 6304: @318788
     /* 318788 */   GIM_Try, /*On fail goto*//*Label 6305*/ GIMT_Encode4(318825), // Rule ID 5239 //
     /* 318793 */     // MIs[0] Operand 1
     /* 318793 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318798 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318802 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318808 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318810 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318814 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318816 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 318819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318821 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318823 */     GIR_RootConstrainSelectedInstOperands,
     /* 318824 */     // GIR_Coverage, 5239,
     /* 318824 */     GIR_EraseRootFromParent_Done,
     /* 318825 */   // Label 6305: @318825
     /* 318825 */   GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(318862), // Rule ID 5246 //
     /* 318830 */     // MIs[0] Operand 1
     /* 318830 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 318835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318839 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318845 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318847 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318851 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318853 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318853 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 318856 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318858 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318860 */     GIR_RootConstrainSelectedInstOperands,
     /* 318861 */     // GIR_Coverage, 5246,
     /* 318861 */     GIR_EraseRootFromParent_Done,
     /* 318862 */   // Label 6306: @318862
     /* 318862 */   GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(318899), // Rule ID 5253 //
     /* 318867 */     // MIs[0] Operand 1
     /* 318867 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 318872 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 318876 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318882 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318884 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318888 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318890 */     // (setcc:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, V128:{ *:[v8i16] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 318893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318895 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 318897 */     GIR_RootConstrainSelectedInstOperands,
     /* 318898 */     // GIR_Coverage, 5253,
     /* 318898 */     GIR_EraseRootFromParent_Done,
     /* 318899 */   // Label 6307: @318899
     /* 318899 */   GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(318939), // Rule ID 755 //
     /* 318904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318907 */     // MIs[0] Operand 1
     /* 318907 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 318912 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318920 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318926 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318928 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318930 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 318933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318935 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318937 */     GIR_RootConstrainSelectedInstOperands,
     /* 318938 */     // GIR_Coverage, 755,
     /* 318938 */     GIR_EraseRootFromParent_Done,
     /* 318939 */   // Label 6308: @318939
     /* 318939 */   GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(318979), // Rule ID 765 //
     /* 318944 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318947 */     // MIs[0] Operand 1
     /* 318947 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 318952 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318956 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 318960 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 318966 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 318968 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 318970 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 318970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 318973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 318975 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 318977 */     GIR_RootConstrainSelectedInstOperands,
     /* 318978 */     // GIR_Coverage, 765,
     /* 318978 */     GIR_EraseRootFromParent_Done,
     /* 318979 */   // Label 6309: @318979
     /* 318979 */   GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(319019), // Rule ID 766 //
     /* 318984 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 318987 */     // MIs[0] Operand 1
     /* 318987 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 318992 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 318996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319000 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319006 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 319008 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319010 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllOnesV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 319013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319015 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319017 */     GIR_RootConstrainSelectedInstOperands,
     /* 319018 */     // GIR_Coverage, 766,
     /* 319018 */     GIR_EraseRootFromParent_Done,
     /* 319019 */   // Label 6310: @319019
     /* 319019 */   GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(319059), // Rule ID 776 //
     /* 319024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319027 */     // MIs[0] Operand 1
     /* 319027 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319040 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319046 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319048 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319050 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 319053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319055 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319057 */     GIR_RootConstrainSelectedInstOperands,
     /* 319058 */     // GIR_Coverage, 776,
     /* 319058 */     GIR_EraseRootFromParent_Done,
     /* 319059 */   // Label 6311: @319059
     /* 319059 */   GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(319096), // Rule ID 5190 //
     /* 319064 */     // MIs[0] Operand 1
     /* 319064 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 319069 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319073 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319077 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319083 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319087 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETEQ:{ *:[Other] })  =>  (CMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16rz),
     /* 319090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319092 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319094 */     GIR_RootConstrainSelectedInstOperands,
     /* 319095 */     // GIR_Coverage, 5190,
     /* 319095 */     GIR_EraseRootFromParent_Done,
     /* 319096 */   // Label 6312: @319096
     /* 319096 */   GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(319133), // Rule ID 5197 //
     /* 319101 */     // MIs[0] Operand 1
     /* 319101 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319106 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319114 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319120 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319122 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319124 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGT:{ *:[Other] })  =>  (CMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16rz),
     /* 319127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319131 */     GIR_RootConstrainSelectedInstOperands,
     /* 319132 */     // GIR_Coverage, 5197,
     /* 319132 */     GIR_EraseRootFromParent_Done,
     /* 319133 */   // Label 6313: @319133
     /* 319133 */   GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(319170), // Rule ID 5204 //
     /* 319138 */     // MIs[0] Operand 1
     /* 319138 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 319143 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319151 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319157 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319159 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319161 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETGE:{ *:[Other] })  =>  (CMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16rz),
     /* 319164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319166 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319168 */     GIR_RootConstrainSelectedInstOperands,
     /* 319169 */     // GIR_Coverage, 5204,
     /* 319169 */     GIR_EraseRootFromParent_Done,
     /* 319170 */   // Label 6314: @319170
     /* 319170 */   GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(319207), // Rule ID 5211 //
     /* 319175 */     // MIs[0] Operand 1
     /* 319175 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 319180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319188 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319194 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319196 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319198 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLT:{ *:[Other] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 319201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319203 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319205 */     GIR_RootConstrainSelectedInstOperands,
     /* 319206 */     // GIR_Coverage, 5211,
     /* 319206 */     GIR_EraseRootFromParent_Done,
     /* 319207 */   // Label 6315: @319207
     /* 319207 */   GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(319244), // Rule ID 5218 //
     /* 319212 */     // MIs[0] Operand 1
     /* 319212 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 319217 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319225 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319231 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319233 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319235 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, immAllZerosV:{ *:[v8i16] }, SETLE:{ *:[Other] })  =>  (CMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 319235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv8i16rz),
     /* 319238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319242 */     GIR_RootConstrainSelectedInstOperands,
     /* 319243 */     // GIR_Coverage, 5218,
     /* 319243 */     GIR_EraseRootFromParent_Done,
     /* 319244 */   // Label 6316: @319244
     /* 319244 */   GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(319276), // Rule ID 1154 //
     /* 319249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319252 */     // MIs[0] Operand 1
     /* 319252 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 319257 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319261 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319265 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16),
     /* 319268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319274 */     GIR_RootConstrainSelectedInstOperands,
     /* 319275 */     // GIR_Coverage, 1154,
     /* 319275 */     GIR_EraseRootFromParent_Done,
     /* 319276 */   // Label 6317: @319276
     /* 319276 */   GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(319308), // Rule ID 1161 //
     /* 319281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319284 */     // MIs[0] Operand 1
     /* 319284 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 319289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319293 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319297 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 319300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319302 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319304 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319306 */     GIR_RootConstrainSelectedInstOperands,
     /* 319307 */     // GIR_Coverage, 1161,
     /* 319307 */     GIR_EraseRootFromParent_Done,
     /* 319308 */   // Label 6318: @319308
     /* 319308 */   GIM_Try, /*On fail goto*//*Label 6319*/ GIMT_Encode4(319340), // Rule ID 1168 //
     /* 319313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319316 */     // MIs[0] Operand 1
     /* 319316 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319325 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319329 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319329 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 319332 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319334 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319336 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319338 */     GIR_RootConstrainSelectedInstOperands,
     /* 319339 */     // GIR_Coverage, 1168,
     /* 319339 */     GIR_EraseRootFromParent_Done,
     /* 319340 */   // Label 6319: @319340
     /* 319340 */   GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(319372), // Rule ID 1175 //
     /* 319345 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319348 */     // MIs[0] Operand 1
     /* 319348 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 319353 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319357 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319361 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 319364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319366 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319368 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319370 */     GIR_RootConstrainSelectedInstOperands,
     /* 319371 */     // GIR_Coverage, 1175,
     /* 319371 */     GIR_EraseRootFromParent_Done,
     /* 319372 */   // Label 6320: @319372
     /* 319372 */   GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(319404), // Rule ID 1182 //
     /* 319377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319380 */     // MIs[0] Operand 1
     /* 319380 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 319385 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319389 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319393 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 319396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319398 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319400 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319402 */     GIR_RootConstrainSelectedInstOperands,
     /* 319403 */     // GIR_Coverage, 1182,
     /* 319403 */     GIR_EraseRootFromParent_Done,
     /* 319404 */   // Label 6321: @319404
     /* 319404 */   GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(319433), // Rule ID 5127 //
     /* 319409 */     // MIs[0] Operand 1
     /* 319409 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 319414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319418 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319422 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv8i16),
     /* 319425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319427 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319429 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319431 */     GIR_RootConstrainSelectedInstOperands,
     /* 319432 */     // GIR_Coverage, 5127,
     /* 319432 */     GIR_EraseRootFromParent_Done,
     /* 319433 */   // Label 6322: @319433
     /* 319433 */   GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(319462), // Rule ID 5134 //
     /* 319438 */     // MIs[0] Operand 1
     /* 319438 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319451 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 319454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319456 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319458 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319460 */     GIR_RootConstrainSelectedInstOperands,
     /* 319461 */     // GIR_Coverage, 5134,
     /* 319461 */     GIR_EraseRootFromParent_Done,
     /* 319462 */   // Label 6323: @319462
     /* 319462 */   GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(319491), // Rule ID 5141 //
     /* 319467 */     // MIs[0] Operand 1
     /* 319467 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 319472 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319476 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319480 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 319483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319487 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319489 */     GIR_RootConstrainSelectedInstOperands,
     /* 319490 */     // GIR_Coverage, 5141,
     /* 319490 */     GIR_EraseRootFromParent_Done,
     /* 319491 */   // Label 6324: @319491
     /* 319491 */   GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(319520), // Rule ID 5148 //
     /* 319496 */     // MIs[0] Operand 1
     /* 319496 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 319501 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319505 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319509 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319509 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 319512 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319514 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319518 */     GIR_RootConstrainSelectedInstOperands,
     /* 319519 */     // GIR_Coverage, 5148,
     /* 319519 */     GIR_EraseRootFromParent_Done,
     /* 319520 */   // Label 6325: @319520
     /* 319520 */   GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(319549), // Rule ID 5155 //
     /* 319525 */     // MIs[0] Operand 1
     /* 319525 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 319530 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319534 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319538 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 319538 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 319541 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319543 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319545 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319547 */     GIR_RootConstrainSelectedInstOperands,
     /* 319548 */     // GIR_Coverage, 5155,
     /* 319548 */     GIR_EraseRootFromParent_Done,
     /* 319549 */   // Label 6326: @319549
     /* 319549 */   GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(319578), // Rule ID 5162 //
     /* 319554 */     // MIs[0] Operand 1
     /* 319554 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 319559 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319563 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319567 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 319567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv8i16),
     /* 319570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319576 */     GIR_RootConstrainSelectedInstOperands,
     /* 319577 */     // GIR_Coverage, 5162,
     /* 319577 */     GIR_EraseRootFromParent_Done,
     /* 319578 */   // Label 6327: @319578
     /* 319578 */   GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(319607), // Rule ID 5169 //
     /* 319583 */     // MIs[0] Operand 1
     /* 319583 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 319588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319596 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 319596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv8i16),
     /* 319599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319601 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319603 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319605 */     GIR_RootConstrainSelectedInstOperands,
     /* 319606 */     // GIR_Coverage, 5169,
     /* 319606 */     GIR_EraseRootFromParent_Done,
     /* 319607 */   // Label 6328: @319607
     /* 319607 */   GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(319636), // Rule ID 5176 //
     /* 319612 */     // MIs[0] Operand 1
     /* 319612 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 319617 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319621 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319625 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 319625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv8i16),
     /* 319628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319630 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319632 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319634 */     GIR_RootConstrainSelectedInstOperands,
     /* 319635 */     // GIR_Coverage, 5176,
     /* 319635 */     GIR_EraseRootFromParent_Done,
     /* 319636 */   // Label 6329: @319636
     /* 319636 */   GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(319665), // Rule ID 5183 //
     /* 319641 */     // MIs[0] Operand 1
     /* 319641 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 319646 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319650 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319654 */     // (setcc:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rm, V128:{ *:[v8i16] }:$Rn)
     /* 319654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv8i16),
     /* 319657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 319661 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319663 */     GIR_RootConstrainSelectedInstOperands,
     /* 319664 */     // GIR_Coverage, 5183,
     /* 319664 */     GIR_EraseRootFromParent_Done,
     /* 319665 */   // Label 6330: @319665
     /* 319665 */   GIM_Reject,
     /* 319666 */ // Label 6300: @319666
     /* 319666 */ GIM_Reject,
     /* 319667 */ // Label 6131: @319667
     /* 319667 */ GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(320714),
     /* 319672 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 319675 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 319678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319682 */   GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(319722), // Rule ID 781 //
     /* 319687 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319690 */     // MIs[0] Operand 1
     /* 319690 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 319695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319699 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319705 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319707 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319711 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319713 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 319716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319718 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319720 */     GIR_RootConstrainSelectedInstOperands,
     /* 319721 */     // GIR_Coverage, 781,
     /* 319721 */     GIR_EraseRootFromParent_Done,
     /* 319722 */   // Label 6332: @319722
     /* 319722 */   GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(319762), // Rule ID 788 //
     /* 319727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319730 */     // MIs[0] Operand 1
     /* 319730 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319735 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319739 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319745 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319747 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319751 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319753 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 319756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319760 */     GIR_RootConstrainSelectedInstOperands,
     /* 319761 */     // GIR_Coverage, 788,
     /* 319761 */     GIR_EraseRootFromParent_Done,
     /* 319762 */   // Label 6333: @319762
     /* 319762 */   GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(319799), // Rule ID 5223 //
     /* 319767 */     // MIs[0] Operand 1
     /* 319767 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 319772 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319776 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319782 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319784 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319788 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319790 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 319793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319795 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319797 */     GIR_RootConstrainSelectedInstOperands,
     /* 319798 */     // GIR_Coverage, 5223,
     /* 319798 */     GIR_EraseRootFromParent_Done,
     /* 319799 */   // Label 6334: @319799
     /* 319799 */   GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(319836), // Rule ID 5230 //
     /* 319804 */     // MIs[0] Operand 1
     /* 319804 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 319809 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319813 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319819 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319821 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319825 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319827 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 319830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319832 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319834 */     GIR_RootConstrainSelectedInstOperands,
     /* 319835 */     // GIR_Coverage, 5230,
     /* 319835 */     GIR_EraseRootFromParent_Done,
     /* 319836 */   // Label 6335: @319836
     /* 319836 */   GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(319873), // Rule ID 5237 //
     /* 319841 */     // MIs[0] Operand 1
     /* 319841 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 319846 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319850 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319856 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319858 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319862 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319864 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETGE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 319867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319869 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319871 */     GIR_RootConstrainSelectedInstOperands,
     /* 319872 */     // GIR_Coverage, 5237,
     /* 319872 */     GIR_EraseRootFromParent_Done,
     /* 319873 */   // Label 6336: @319873
     /* 319873 */   GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(319910), // Rule ID 5244 //
     /* 319878 */     // MIs[0] Operand 1
     /* 319878 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 319883 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319887 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319893 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319895 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319899 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319901 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 319904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319908 */     GIR_RootConstrainSelectedInstOperands,
     /* 319909 */     // GIR_Coverage, 5244,
     /* 319909 */     GIR_EraseRootFromParent_Done,
     /* 319910 */   // Label 6337: @319910
     /* 319910 */   GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(319947), // Rule ID 5251 //
     /* 319915 */     // MIs[0] Operand 1
     /* 319915 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 319920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 319924 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319930 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319932 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319936 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319938 */     // (setcc:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, V128:{ *:[v16i8] }:$Rn, SETLE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319938 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 319941 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319943 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 319945 */     GIR_RootConstrainSelectedInstOperands,
     /* 319946 */     // GIR_Coverage, 5251,
     /* 319946 */     GIR_EraseRootFromParent_Done,
     /* 319947 */   // Label 6338: @319947
     /* 319947 */   GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(319987), // Rule ID 753 //
     /* 319952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319955 */     // MIs[0] Operand 1
     /* 319955 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 319960 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 319964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 319968 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 319974 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 319976 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 319978 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 319978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 319981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 319983 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 319985 */     GIR_RootConstrainSelectedInstOperands,
     /* 319986 */     // GIR_Coverage, 753,
     /* 319986 */     GIR_EraseRootFromParent_Done,
     /* 319987 */   // Label 6339: @319987
     /* 319987 */   GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(320027), // Rule ID 761 //
     /* 319992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 319995 */     // MIs[0] Operand 1
     /* 319995 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 320000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320004 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320008 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320014 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320016 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320018 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 320021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320023 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320025 */     GIR_RootConstrainSelectedInstOperands,
     /* 320026 */     // GIR_Coverage, 761,
     /* 320026 */     GIR_EraseRootFromParent_Done,
     /* 320027 */   // Label 6340: @320027
     /* 320027 */   GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(320067), // Rule ID 762 //
     /* 320032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320035 */     // MIs[0] Operand 1
     /* 320035 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 320040 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320048 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320054 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
     /* 320056 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320058 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllOnesV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 320061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320063 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320065 */     GIR_RootConstrainSelectedInstOperands,
     /* 320066 */     // GIR_Coverage, 762,
     /* 320066 */     GIR_EraseRootFromParent_Done,
     /* 320067 */   // Label 6341: @320067
     /* 320067 */   GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(320107), // Rule ID 774 //
     /* 320072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320075 */     // MIs[0] Operand 1
     /* 320075 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 320080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320084 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320088 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320094 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320096 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320098 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 320101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320103 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320105 */     GIR_RootConstrainSelectedInstOperands,
     /* 320106 */     // GIR_Coverage, 774,
     /* 320106 */     GIR_EraseRootFromParent_Done,
     /* 320107 */   // Label 6342: @320107
     /* 320107 */   GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(320144), // Rule ID 5188 //
     /* 320112 */     // MIs[0] Operand 1
     /* 320112 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 320117 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320121 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320125 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320131 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320133 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320135 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETEQ:{ *:[Other] })  =>  (CMEQv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8rz),
     /* 320138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320140 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320142 */     GIR_RootConstrainSelectedInstOperands,
     /* 320143 */     // GIR_Coverage, 5188,
     /* 320143 */     GIR_EraseRootFromParent_Done,
     /* 320144 */   // Label 6343: @320144
     /* 320144 */   GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(320181), // Rule ID 5195 //
     /* 320149 */     // MIs[0] Operand 1
     /* 320149 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 320154 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320162 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320168 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320170 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320172 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGT:{ *:[Other] })  =>  (CMGTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8rz),
     /* 320175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320177 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320179 */     GIR_RootConstrainSelectedInstOperands,
     /* 320180 */     // GIR_Coverage, 5195,
     /* 320180 */     GIR_EraseRootFromParent_Done,
     /* 320181 */   // Label 6344: @320181
     /* 320181 */   GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(320218), // Rule ID 5202 //
     /* 320186 */     // MIs[0] Operand 1
     /* 320186 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 320191 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320199 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320205 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320209 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETGE:{ *:[Other] })  =>  (CMGEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8rz),
     /* 320212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320214 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320216 */     GIR_RootConstrainSelectedInstOperands,
     /* 320217 */     // GIR_Coverage, 5202,
     /* 320217 */     GIR_EraseRootFromParent_Done,
     /* 320218 */   // Label 6345: @320218
     /* 320218 */   GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(320255), // Rule ID 5209 //
     /* 320223 */     // MIs[0] Operand 1
     /* 320223 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 320228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320232 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320236 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320242 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320244 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320246 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLT:{ *:[Other] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 320249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320251 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320253 */     GIR_RootConstrainSelectedInstOperands,
     /* 320254 */     // GIR_Coverage, 5209,
     /* 320254 */     GIR_EraseRootFromParent_Done,
     /* 320255 */   // Label 6346: @320255
     /* 320255 */   GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(320292), // Rule ID 5216 //
     /* 320260 */     // MIs[0] Operand 1
     /* 320260 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 320265 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 320273 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 320279 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 320281 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 320283 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, immAllZerosV:{ *:[v16i8] }, SETLE:{ *:[Other] })  =>  (CMLEv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 320283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLEv16i8rz),
     /* 320286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320288 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320290 */     GIR_RootConstrainSelectedInstOperands,
     /* 320291 */     // GIR_Coverage, 5216,
     /* 320291 */     GIR_EraseRootFromParent_Done,
     /* 320292 */   // Label 6347: @320292
     /* 320292 */   GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(320324), // Rule ID 1152 //
     /* 320297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320300 */     // MIs[0] Operand 1
     /* 320300 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 320305 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320309 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320313 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8),
     /* 320316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320318 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320320 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320322 */     GIR_RootConstrainSelectedInstOperands,
     /* 320323 */     // GIR_Coverage, 1152,
     /* 320323 */     GIR_EraseRootFromParent_Done,
     /* 320324 */   // Label 6348: @320324
     /* 320324 */   GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(320356), // Rule ID 1159 //
     /* 320329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320332 */     // MIs[0] Operand 1
     /* 320332 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 320337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320341 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320345 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 320348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320350 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320352 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320354 */     GIR_RootConstrainSelectedInstOperands,
     /* 320355 */     // GIR_Coverage, 1159,
     /* 320355 */     GIR_EraseRootFromParent_Done,
     /* 320356 */   // Label 6349: @320356
     /* 320356 */   GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(320388), // Rule ID 1166 //
     /* 320361 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320364 */     // MIs[0] Operand 1
     /* 320364 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 320369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320377 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320377 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 320380 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320382 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320384 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320386 */     GIR_RootConstrainSelectedInstOperands,
     /* 320387 */     // GIR_Coverage, 1166,
     /* 320387 */     GIR_EraseRootFromParent_Done,
     /* 320388 */   // Label 6350: @320388
     /* 320388 */   GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(320420), // Rule ID 1173 //
     /* 320393 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320396 */     // MIs[0] Operand 1
     /* 320396 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 320401 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320405 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320409 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 320412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320414 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320416 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320418 */     GIR_RootConstrainSelectedInstOperands,
     /* 320419 */     // GIR_Coverage, 1173,
     /* 320419 */     GIR_EraseRootFromParent_Done,
     /* 320420 */   // Label 6351: @320420
     /* 320420 */   GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(320452), // Rule ID 1180 //
     /* 320425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 320428 */     // MIs[0] Operand 1
     /* 320428 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 320433 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320437 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320441 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 320444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320446 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320448 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320450 */     GIR_RootConstrainSelectedInstOperands,
     /* 320451 */     // GIR_Coverage, 1180,
     /* 320451 */     GIR_EraseRootFromParent_Done,
     /* 320452 */   // Label 6352: @320452
     /* 320452 */   GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(320481), // Rule ID 5125 //
     /* 320457 */     // MIs[0] Operand 1
     /* 320457 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 320462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320466 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320470 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETEQ:{ *:[Other] })  =>  (CMEQv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMEQv16i8),
     /* 320473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320475 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320477 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320479 */     GIR_RootConstrainSelectedInstOperands,
     /* 320480 */     // GIR_Coverage, 5125,
     /* 320480 */     GIR_EraseRootFromParent_Done,
     /* 320481 */   // Label 6353: @320481
     /* 320481 */   GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(320510), // Rule ID 5132 //
     /* 320486 */     // MIs[0] Operand 1
     /* 320486 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 320491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320495 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320499 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 320502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320506 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320508 */     GIR_RootConstrainSelectedInstOperands,
     /* 320509 */     // GIR_Coverage, 5132,
     /* 320509 */     GIR_EraseRootFromParent_Done,
     /* 320510 */   // Label 6354: @320510
     /* 320510 */   GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(320539), // Rule ID 5139 //
     /* 320515 */     // MIs[0] Operand 1
     /* 320515 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 320520 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320524 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320528 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETGE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320528 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 320531 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320533 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320535 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320537 */     GIR_RootConstrainSelectedInstOperands,
     /* 320538 */     // GIR_Coverage, 5139,
     /* 320538 */     GIR_EraseRootFromParent_Done,
     /* 320539 */   // Label 6355: @320539
     /* 320539 */   GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(320568), // Rule ID 5146 //
     /* 320544 */     // MIs[0] Operand 1
     /* 320544 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 320549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320553 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320557 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 320560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320562 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320564 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320566 */     GIR_RootConstrainSelectedInstOperands,
     /* 320567 */     // GIR_Coverage, 5146,
     /* 320567 */     GIR_EraseRootFromParent_Done,
     /* 320568 */   // Label 6356: @320568
     /* 320568 */   GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(320597), // Rule ID 5153 //
     /* 320573 */     // MIs[0] Operand 1
     /* 320573 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 320578 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320582 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320586 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETUGE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 320586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 320589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320591 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320593 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320595 */     GIR_RootConstrainSelectedInstOperands,
     /* 320596 */     // GIR_Coverage, 5153,
     /* 320596 */     GIR_EraseRootFromParent_Done,
     /* 320597 */   // Label 6357: @320597
     /* 320597 */   GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(320626), // Rule ID 5160 //
     /* 320602 */     // MIs[0] Operand 1
     /* 320602 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 320607 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320611 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320615 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLT:{ *:[Other] })  =>  (CMGTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 320615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGTv16i8),
     /* 320618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320620 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320624 */     GIR_RootConstrainSelectedInstOperands,
     /* 320625 */     // GIR_Coverage, 5160,
     /* 320625 */     GIR_EraseRootFromParent_Done,
     /* 320626 */   // Label 6358: @320626
     /* 320626 */   GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(320655), // Rule ID 5167 //
     /* 320631 */     // MIs[0] Operand 1
     /* 320631 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 320636 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320640 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320644 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETLE:{ *:[Other] })  =>  (CMGEv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 320644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMGEv16i8),
     /* 320647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320649 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320651 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320653 */     GIR_RootConstrainSelectedInstOperands,
     /* 320654 */     // GIR_Coverage, 5167,
     /* 320654 */     GIR_EraseRootFromParent_Done,
     /* 320655 */   // Label 6359: @320655
     /* 320655 */   GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(320684), // Rule ID 5174 //
     /* 320660 */     // MIs[0] Operand 1
     /* 320660 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 320665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320673 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULT:{ *:[Other] })  =>  (CMHIv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 320673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHIv16i8),
     /* 320676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320678 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320680 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320682 */     GIR_RootConstrainSelectedInstOperands,
     /* 320683 */     // GIR_Coverage, 5174,
     /* 320683 */     GIR_EraseRootFromParent_Done,
     /* 320684 */   // Label 6360: @320684
     /* 320684 */   GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(320713), // Rule ID 5181 //
     /* 320689 */     // MIs[0] Operand 1
     /* 320689 */     GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 320694 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320698 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 320702 */     // (setcc:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, SETULE:{ *:[Other] })  =>  (CMHSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rm, V128:{ *:[v16i8] }:$Rn)
     /* 320702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMHSv16i8),
     /* 320705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 320707 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rm
     /* 320709 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 320711 */     GIR_RootConstrainSelectedInstOperands,
     /* 320712 */     // GIR_Coverage, 5181,
     /* 320712 */     GIR_EraseRootFromParent_Done,
     /* 320713 */   // Label 6361: @320713
     /* 320713 */   GIM_Reject,
     /* 320714 */ // Label 6331: @320714
     /* 320714 */ GIM_Reject,
     /* 320715 */ // Label 6132: @320715
     /* 320715 */ GIM_Reject,
     /* 320716 */ // Label 61: @320716
     /* 320716 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(24), /*)*//*default:*//*Label 6374*/ GIMT_Encode4(321760),
     /* 320727 */ /*GILLT_nxv1s1*//*Label 6362*/ GIMT_Encode4(320775),
     /* 320731 */ /*GILLT_nxv2s1*//*Label 6363*/ GIMT_Encode4(320804),
     /* 320735 */ /*GILLT_nxv2s16*//*Label 6364*/ GIMT_Encode4(320833),
     /* 320739 */ /*GILLT_nxv2s32*//*Label 6365*/ GIMT_Encode4(320918),
     /* 320743 */ /*GILLT_nxv2s64*//*Label 6366*/ GIMT_Encode4(321003),
     /* 320747 */ /*GILLT_nxv4s1*//*Label 6367*/ GIMT_Encode4(321169),
     /* 320751 */ /*GILLT_nxv4s16*//*Label 6368*/ GIMT_Encode4(321198),
     /* 320755 */ /*GILLT_nxv4s32*//*Label 6369*/ GIMT_Encode4(321283),
     /* 320759 */ /*GILLT_nxv8s1*//*Label 6370*/ GIMT_Encode4(321449),
     /* 320763 */ /*GILLT_nxv8s16*//*Label 6371*/ GIMT_Encode4(321478),
     /* 320767 */ /*GILLT_nxv16s1*//*Label 6372*/ GIMT_Encode4(321644),
     /* 320771 */ /*GILLT_nxv16s8*//*Label 6373*/ GIMT_Encode4(321673),
     /* 320775 */ // Label 6362: @320775
     /* 320775 */ GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(320803), // Rule ID 9181 //
     /* 320780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320783 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv1s1,
     /* 320786 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv1s1,
     /* 320789 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv1s1,
     /* 320792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 320796 */   // (vselect:{ *:[nxv1i1] } nxv1i1:{ *:[nxv1i1] }:$Op1, nxv1i1:{ *:[nxv1i1] }:$Op2, nxv1i1:{ *:[nxv1i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv1i1] } ?:{ *:[nxv1i1] }:$Op1, ?:{ *:[nxv1i1] }:$Op2, ?:{ *:[nxv1i1] }:$Op3)
     /* 320796 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 320801 */   GIR_RootConstrainSelectedInstOperands,
     /* 320802 */   // GIR_Coverage, 9181,
     /* 320802 */   GIR_Done,
     /* 320803 */ // Label 6375: @320803
     /* 320803 */ GIM_Reject,
     /* 320804 */ // Label 6363: @320804
     /* 320804 */ GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(320832), // Rule ID 9180 //
     /* 320809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320812 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 320815 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 320818 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s1,
     /* 320821 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 320825 */   // (vselect:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2, nxv2i1:{ *:[nxv2i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2, ?:{ *:[nxv2i1] }:$Op3)
     /* 320825 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 320830 */   GIR_RootConstrainSelectedInstOperands,
     /* 320831 */   // GIR_Coverage, 9180,
     /* 320831 */   GIR_Done,
     /* 320832 */ // Label 6376: @320832
     /* 320832 */ GIM_Reject,
     /* 320833 */ // Label 6364: @320833
     /* 320833 */ GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(320917),
     /* 320838 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 320841 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 320844 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s16,
     /* 320847 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 320851 */   GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(320901), // Rule ID 3231 //
     /* 320856 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320859 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320863 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 320867 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 320871 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320875 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 320879 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 320883 */     // MIs[2] Operand 1
     /* 320883 */     // No operand predicates
     /* 320883 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 320885 */     // (vselect:{ *:[nxv2f16] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv2f16:{ *:[nxv2f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 320885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 320888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 320890 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 320892 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 320894 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 320899 */     GIR_RootConstrainSelectedInstOperands,
     /* 320900 */     // GIR_Coverage, 3231,
     /* 320900 */     GIR_EraseRootFromParent_Done,
     /* 320901 */   // Label 6378: @320901
     /* 320901 */   GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(320916), // Rule ID 2780 //
     /* 320906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320909 */     // (vselect:{ *:[nxv2f16] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2, nxv2f16:{ *:[nxv2f16] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f16] }:$Op2, ?:{ *:[nxv2f16] }:$Op3)
     /* 320909 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 320914 */     GIR_RootConstrainSelectedInstOperands,
     /* 320915 */     // GIR_Coverage, 2780,
     /* 320915 */     GIR_Done,
     /* 320916 */   // Label 6379: @320916
     /* 320916 */   GIM_Reject,
     /* 320917 */ // Label 6377: @320917
     /* 320917 */ GIM_Reject,
     /* 320918 */ // Label 6365: @320918
     /* 320918 */ GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(321002),
     /* 320923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 320926 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 320929 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s32,
     /* 320932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 320936 */   GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(320986), // Rule ID 3233 //
     /* 320941 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 320948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 320952 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 320956 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 320960 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 320964 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 320968 */     // MIs[2] Operand 1
     /* 320968 */     // No operand predicates
     /* 320968 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 320970 */     // (vselect:{ *:[nxv2f32] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8), nxv2f32:{ *:[nxv2f32] }:$zd)  =>  (FCPY_ZPmI_S:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 320970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_S),
     /* 320973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 320975 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 320977 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 320979 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 320984 */     GIR_RootConstrainSelectedInstOperands,
     /* 320985 */     // GIR_Coverage, 3233,
     /* 320985 */     GIR_EraseRootFromParent_Done,
     /* 320986 */   // Label 6381: @320986
     /* 320986 */   GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(321001), // Rule ID 2781 //
     /* 320991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 320994 */     // (vselect:{ *:[nxv2f32] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2, nxv2f32:{ *:[nxv2f32] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f32] }:$Op2, ?:{ *:[nxv2f32] }:$Op3)
     /* 320994 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 320999 */     GIR_RootConstrainSelectedInstOperands,
     /* 321000 */     // GIR_Coverage, 2781,
     /* 321000 */     GIR_Done,
     /* 321001 */   // Label 6382: @321001
     /* 321001 */   GIM_Reject,
     /* 321002 */ // Label 6380: @321002
     /* 321002 */ GIM_Reject,
     /* 321003 */ // Label 6366: @321003
     /* 321003 */ GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(321168),
     /* 321008 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 321011 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 321014 */   GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(321071), // Rule ID 3234 //
     /* 321019 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321022 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 321025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 321037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 321041 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321045 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 321049 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 321053 */     // MIs[2] Operand 1
     /* 321053 */     // No operand predicates
     /* 321053 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321055 */     // (vselect:{ *:[nxv2f64] } nxv2i1:{ *:[nxv2i1] }:$pg, (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm8), nxv2f64:{ *:[nxv2f64] }:$zd)  =>  (FCPY_ZPmI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$zd, ?:{ *:[nxv2i1] }:$pg, (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>>:$imm8))
     /* 321055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_D),
     /* 321058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 321060 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 321062 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 321064 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm8
     /* 321069 */     GIR_RootConstrainSelectedInstOperands,
     /* 321070 */     // GIR_Coverage, 3234,
     /* 321070 */     GIR_EraseRootFromParent_Done,
     /* 321071 */   // Label 6384: @321071
     /* 321071 */   GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(321123), // Rule ID 8165 //
     /* 321076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321083 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321087 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 321091 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 321095 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 321099 */     // MIs[0] Op2
     /* 321099 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 321104 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321106 */     // (vselect:{ *:[nxv2i64] } nxv2i1:{ *:[nxv2i1] }:$Op1, (sub:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op2), nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SUBR_ZPmZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 321106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_D),
     /* 321109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 321111 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 321113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 321117 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 321121 */     GIR_RootConstrainSelectedInstOperands,
     /* 321122 */     // GIR_Coverage, 8165,
     /* 321122 */     GIR_EraseRootFromParent_Done,
     /* 321123 */   // Label 6385: @321123
     /* 321123 */   GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(321145), // Rule ID 2776 //
     /* 321128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 321134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321138 */     // (vselect:{ *:[nxv2i64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, nxv2i64:{ *:[nxv2i64] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 321138 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 321143 */     GIR_RootConstrainSelectedInstOperands,
     /* 321144 */     // GIR_Coverage, 2776,
     /* 321144 */     GIR_Done,
     /* 321145 */   // Label 6386: @321145
     /* 321145 */   GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(321167), // Rule ID 2782 //
     /* 321150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 321156 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321160 */     // (vselect:{ *:[nxv2f64] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2, nxv2f64:{ *:[nxv2f64] }:$Op3)  =>  (SEL_ZPZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, ?:{ *:[nxv2f64] }:$Op3)
     /* 321160 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_D),
     /* 321165 */     GIR_RootConstrainSelectedInstOperands,
     /* 321166 */     // GIR_Coverage, 2782,
     /* 321166 */     GIR_Done,
     /* 321167 */   // Label 6387: @321167
     /* 321167 */   GIM_Reject,
     /* 321168 */ // Label 6383: @321168
     /* 321168 */ GIM_Reject,
     /* 321169 */ // Label 6367: @321169
     /* 321169 */ GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(321197), // Rule ID 9179 //
     /* 321174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 321180 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 321183 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s1,
     /* 321186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 321190 */   // (vselect:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2, nxv4i1:{ *:[nxv4i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2, ?:{ *:[nxv4i1] }:$Op3)
     /* 321190 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 321195 */   GIR_RootConstrainSelectedInstOperands,
     /* 321196 */   // GIR_Coverage, 9179,
     /* 321196 */   GIR_Done,
     /* 321197 */ // Label 6388: @321197
     /* 321197 */ GIM_Reject,
     /* 321198 */ // Label 6368: @321198
     /* 321198 */ GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(321282),
     /* 321203 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 321206 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 321209 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s16,
     /* 321212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321216 */   GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(321266), // Rule ID 3230 //
     /* 321221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 321232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 321236 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321240 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 321244 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 321248 */     // MIs[2] Operand 1
     /* 321248 */     // No operand predicates
     /* 321248 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321250 */     // (vselect:{ *:[nxv4f16] } nxv4i1:{ *:[nxv4i1] }:$pg, (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv4f16:{ *:[nxv4f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$zd, ?:{ *:[nxv4i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 321250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 321253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 321255 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 321257 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 321259 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 321264 */     GIR_RootConstrainSelectedInstOperands,
     /* 321265 */     // GIR_Coverage, 3230,
     /* 321265 */     GIR_EraseRootFromParent_Done,
     /* 321266 */   // Label 6390: @321266
     /* 321266 */   GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(321281), // Rule ID 2778 //
     /* 321271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321274 */     // (vselect:{ *:[nxv4f16] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2, nxv4f16:{ *:[nxv4f16] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f16] }:$Op2, ?:{ *:[nxv4f16] }:$Op3)
     /* 321274 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 321279 */     GIR_RootConstrainSelectedInstOperands,
     /* 321280 */     // GIR_Coverage, 2778,
     /* 321280 */     GIR_Done,
     /* 321281 */   // Label 6391: @321281
     /* 321281 */   GIM_Reject,
     /* 321282 */ // Label 6389: @321282
     /* 321282 */ GIM_Reject,
     /* 321283 */ // Label 6369: @321283
     /* 321283 */ GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(321448),
     /* 321288 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 321291 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 321294 */   GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(321351), // Rule ID 3232 //
     /* 321299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321302 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 321305 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321309 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321313 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 321317 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 321321 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321325 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 321329 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 321333 */     // MIs[2] Operand 1
     /* 321333 */     // No operand predicates
     /* 321333 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321335 */     // (vselect:{ *:[nxv4f32] } nxv4i1:{ *:[nxv4i1] }:$pg, (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8), nxv4f32:{ *:[nxv4f32] }:$zd)  =>  (FCPY_ZPmI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$zd, ?:{ *:[nxv4i1] }:$pg, (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 321335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_S),
     /* 321338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 321340 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 321342 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 321344 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 321349 */     GIR_RootConstrainSelectedInstOperands,
     /* 321350 */     // GIR_Coverage, 3232,
     /* 321350 */     GIR_EraseRootFromParent_Done,
     /* 321351 */   // Label 6393: @321351
     /* 321351 */   GIM_Try, /*On fail goto*//*Label 6394*/ GIMT_Encode4(321403), // Rule ID 8163 //
     /* 321356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321363 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321367 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 321371 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 321375 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 321379 */     // MIs[0] Op2
     /* 321379 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 321384 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321386 */     // (vselect:{ *:[nxv4i32] } nxv4i1:{ *:[nxv4i1] }:$Op1, (sub:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op2), nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SUBR_ZPmZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 321386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_S),
     /* 321389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 321391 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 321393 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 321397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 321401 */     GIR_RootConstrainSelectedInstOperands,
     /* 321402 */     // GIR_Coverage, 8163,
     /* 321402 */     GIR_EraseRootFromParent_Done,
     /* 321403 */   // Label 6394: @321403
     /* 321403 */   GIM_Try, /*On fail goto*//*Label 6395*/ GIMT_Encode4(321425), // Rule ID 2775 //
     /* 321408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 321414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321418 */     // (vselect:{ *:[nxv4i32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, nxv4i32:{ *:[nxv4i32] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 321418 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 321423 */     GIR_RootConstrainSelectedInstOperands,
     /* 321424 */     // GIR_Coverage, 2775,
     /* 321424 */     GIR_Done,
     /* 321425 */   // Label 6395: @321425
     /* 321425 */   GIM_Try, /*On fail goto*//*Label 6396*/ GIMT_Encode4(321447), // Rule ID 2779 //
     /* 321430 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 321436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321440 */     // (vselect:{ *:[nxv4f32] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2, nxv4f32:{ *:[nxv4f32] }:$Op3)  =>  (SEL_ZPZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, ?:{ *:[nxv4f32] }:$Op3)
     /* 321440 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_S),
     /* 321445 */     GIR_RootConstrainSelectedInstOperands,
     /* 321446 */     // GIR_Coverage, 2779,
     /* 321446 */     GIR_Done,
     /* 321447 */   // Label 6396: @321447
     /* 321447 */   GIM_Reject,
     /* 321448 */ // Label 6392: @321448
     /* 321448 */ GIM_Reject,
     /* 321449 */ // Label 6370: @321449
     /* 321449 */ GIM_Try, /*On fail goto*//*Label 6397*/ GIMT_Encode4(321477), // Rule ID 9178 //
     /* 321454 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321457 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 321460 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 321463 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s1,
     /* 321466 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 321470 */   // (vselect:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2, nxv8i1:{ *:[nxv8i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2, ?:{ *:[nxv8i1] }:$Op3)
     /* 321470 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 321475 */   GIR_RootConstrainSelectedInstOperands,
     /* 321476 */   // GIR_Coverage, 9178,
     /* 321476 */   GIR_Done,
     /* 321477 */ // Label 6397: @321477
     /* 321477 */ GIM_Reject,
     /* 321478 */ // Label 6371: @321478
     /* 321478 */ GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(321643),
     /* 321483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 321486 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 321489 */   GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(321546), // Rule ID 3229 //
     /* 321494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321497 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 321500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SPLAT_VECTOR),
     /* 321512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 321516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 321520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 321524 */     GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 321528 */     // MIs[2] Operand 1
     /* 321528 */     // No operand predicates
     /* 321528 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 321530 */     // (vselect:{ *:[nxv8f16] } nxv8i1:{ *:[nxv8i1] }:$pg, (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8), nxv8f16:{ *:[nxv8f16] }:$zd)  =>  (FCPY_ZPmI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$zd, ?:{ *:[nxv8i1] }:$pg, (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 321530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCPY_ZPmI_H),
     /* 321533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 321535 */     GIR_RootToRootCopy, /*OpIdx*/3, // zd
     /* 321537 */     GIR_RootToRootCopy, /*OpIdx*/1, // pg
     /* 321539 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 321544 */     GIR_RootConstrainSelectedInstOperands,
     /* 321545 */     // GIR_Coverage, 3229,
     /* 321545 */     GIR_EraseRootFromParent_Done,
     /* 321546 */   // Label 6399: @321546
     /* 321546 */   GIM_Try, /*On fail goto*//*Label 6400*/ GIMT_Encode4(321598), // Rule ID 8161 //
     /* 321551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 321566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 321570 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 321574 */     // MIs[0] Op2
     /* 321574 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 321579 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321581 */     // (vselect:{ *:[nxv8i16] } nxv8i1:{ *:[nxv8i1] }:$Op1, (sub:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op2), nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SUBR_ZPmZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 321581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_H),
     /* 321584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 321586 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 321588 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 321592 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 321596 */     GIR_RootConstrainSelectedInstOperands,
     /* 321597 */     // GIR_Coverage, 8161,
     /* 321597 */     GIR_EraseRootFromParent_Done,
     /* 321598 */   // Label 6400: @321598
     /* 321598 */   GIM_Try, /*On fail goto*//*Label 6401*/ GIMT_Encode4(321620), // Rule ID 2774 //
     /* 321603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321606 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 321609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321613 */     // (vselect:{ *:[nxv8i16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SEL_ZPZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 321613 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
     /* 321618 */     GIR_RootConstrainSelectedInstOperands,
     /* 321619 */     // GIR_Coverage, 2774,
     /* 321619 */     GIR_Done,
     /* 321620 */   // Label 6401: @321620
     /* 321620 */   GIM_Try, /*On fail goto*//*Label 6402*/ GIMT_Encode4(321642), // Rule ID 2777 //
     /* 321625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 321631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321635 */     // (vselect:{ *:[nxv8f16] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2, nxv8f16:{ *:[nxv8f16] }:$Op3)  =>  (SEL_ZPZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, ?:{ *:[nxv8f16] }:$Op3)
     /* 321635 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_H),
     /* 321640 */     GIR_RootConstrainSelectedInstOperands,
     /* 321641 */     // GIR_Coverage, 2777,
     /* 321641 */     GIR_Done,
     /* 321642 */   // Label 6402: @321642
     /* 321642 */   GIM_Reject,
     /* 321643 */ // Label 6398: @321643
     /* 321643 */ GIM_Reject,
     /* 321644 */ // Label 6372: @321644
     /* 321644 */ GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(321672), // Rule ID 9177 //
     /* 321649 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321652 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 321655 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 321658 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s1,
     /* 321661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRorPNRRegClassID),
     /* 321665 */   // (vselect:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i1:{ *:[nxv16i1] }:$Op2, nxv16i1:{ *:[nxv16i1] }:$Op3)  =>  (SEL_PPPP:{ *:[nxv16i1] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i1] }:$Op2, ?:{ *:[nxv16i1] }:$Op3)
     /* 321665 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_PPPP),
     /* 321670 */   GIR_RootConstrainSelectedInstOperands,
     /* 321671 */   // GIR_Coverage, 9177,
     /* 321671 */   GIR_Done,
     /* 321672 */ // Label 6403: @321672
     /* 321672 */ GIM_Reject,
     /* 321673 */ // Label 6373: @321673
     /* 321673 */ GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(321759),
     /* 321678 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 321681 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 321684 */   GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(321736), // Rule ID 8159 //
     /* 321689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321692 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 321700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 321704 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 321708 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 321712 */     // MIs[0] Op2
     /* 321712 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 321717 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 321719 */     // (vselect:{ *:[nxv16i8] } nxv16i1:{ *:[nxv16i1] }:$Op1, (sub:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op2), nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SUBR_ZPmZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 321719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBR_ZPmZ_B),
     /* 321722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 321724 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 321726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 321730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op3
     /* 321734 */     GIR_RootConstrainSelectedInstOperands,
     /* 321735 */     // GIR_Coverage, 8159,
     /* 321735 */     GIR_EraseRootFromParent_Done,
     /* 321736 */   // Label 6405: @321736
     /* 321736 */   GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(321758), // Rule ID 2773 //
     /* 321741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 321744 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 321747 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 321751 */     // (vselect:{ *:[nxv16i8] } nxv16i1:{ *:[nxv16i1] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SEL_ZPZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i1] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 321751 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SEL_ZPZZ_B),
     /* 321756 */     GIR_RootConstrainSelectedInstOperands,
     /* 321757 */     // GIR_Coverage, 2773,
     /* 321757 */     GIR_Done,
     /* 321758 */   // Label 6406: @321758
     /* 321758 */   GIM_Reject,
     /* 321759 */ // Label 6404: @321759
     /* 321759 */ GIM_Reject,
     /* 321760 */ // Label 6374: @321760
     /* 321760 */ GIM_Reject,
     /* 321761 */ // Label 62: @321761
     /* 321761 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 6411*/ GIMT_Encode4(322244),
     /* 321772 */ /*GILLT_s64*//*Label 6407*/ GIMT_Encode4(321808), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 321792 */ /*GILLT_v4s32*//*Label 6408*/ GIMT_Encode4(321839), GIMT_Encode4(0),
     /* 321800 */ /*GILLT_v8s16*//*Label 6409*/ GIMT_Encode4(321974),
     /* 321804 */ /*GILLT_v16s8*//*Label 6410*/ GIMT_Encode4(322109),
     /* 321808 */ // Label 6407: @321808
     /* 321808 */ GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(321838), // Rule ID 116 //
     /* 321813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 321816 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 321819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 321823 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 321827 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 321831 */   // (mulhu:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 321831 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULHrr),
     /* 321836 */   GIR_RootConstrainSelectedInstOperands,
     /* 321837 */   // GIR_Coverage, 116,
     /* 321837 */   GIR_Done,
     /* 321838 */ // Label 6412: @321838
     /* 321838 */ GIM_Reject,
     /* 321839 */ // Label 6408: @321839
     /* 321839 */ GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(321973), // Rule ID 7172 //
     /* 321844 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 321847 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 321850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321854 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321858 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321862 */   // (mulhu:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } (UMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (UMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
     /* 321862 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 321865 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
     /* 321869 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 321874 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 321878 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 321882 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 321884 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 321887 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 321891 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 321896 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 321902 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321907 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321912 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 321915 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 321919 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 321924 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 321930 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 321935 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321940 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 321943 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
     /* 321947 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 321952 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 321955 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 321958 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 321960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 321963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 321965 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 321968 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 321971 */   GIR_RootConstrainSelectedInstOperands,
     /* 321972 */   // GIR_Coverage, 7172,
     /* 321972 */   GIR_EraseRootFromParent_Done,
     /* 321973 */ // Label 6413: @321973
     /* 321973 */ GIM_Reject,
     /* 321974 */ // Label 6409: @321974
     /* 321974 */ GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(322108), // Rule ID 7171 //
     /* 321979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 321982 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 321985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321989 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321993 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 321997 */   // (mulhu:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } (UMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (UMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
     /* 321997 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 322000 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
     /* 322004 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322009 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 322013 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 322017 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 322019 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 322022 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322026 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322031 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 322037 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322042 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322047 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 322050 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322054 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322059 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 322065 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322070 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322075 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322078 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
     /* 322082 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322087 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 322090 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 322093 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 322095 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 322098 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 322100 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322103 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 322106 */   GIR_RootConstrainSelectedInstOperands,
     /* 322107 */   // GIR_Coverage, 7171,
     /* 322107 */   GIR_EraseRootFromParent_Done,
     /* 322108 */ // Label 6414: @322108
     /* 322108 */ GIM_Reject,
     /* 322109 */ // Label 6410: @322109
     /* 322109 */ GIM_Try, /*On fail goto*//*Label 6415*/ GIMT_Encode4(322243), // Rule ID 7170 //
     /* 322114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 322117 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 322120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322124 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322128 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322132 */   // (mulhu:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } (UMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (UMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
     /* 322132 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 322135 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
     /* 322139 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322144 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 322148 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 322152 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 322154 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 322157 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322161 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322166 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 322172 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322177 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322182 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 322185 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322189 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322194 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 322200 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322205 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322210 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322213 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
     /* 322217 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322222 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 322225 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 322228 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 322230 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 322233 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 322235 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322238 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 322241 */   GIR_RootConstrainSelectedInstOperands,
     /* 322242 */   // GIR_Coverage, 7170,
     /* 322242 */   GIR_EraseRootFromParent_Done,
     /* 322243 */ // Label 6415: @322243
     /* 322243 */ GIM_Reject,
     /* 322244 */ // Label 6411: @322244
     /* 322244 */ GIM_Reject,
     /* 322245 */ // Label 63: @322245
     /* 322245 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 6420*/ GIMT_Encode4(322728),
     /* 322256 */ /*GILLT_s64*//*Label 6416*/ GIMT_Encode4(322292), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 322276 */ /*GILLT_v4s32*//*Label 6417*/ GIMT_Encode4(322323), GIMT_Encode4(0),
     /* 322284 */ /*GILLT_v8s16*//*Label 6418*/ GIMT_Encode4(322458),
     /* 322288 */ /*GILLT_v16s8*//*Label 6419*/ GIMT_Encode4(322593),
     /* 322292 */ // Label 6416: @322292
     /* 322292 */ GIM_Try, /*On fail goto*//*Label 6421*/ GIMT_Encode4(322322), // Rule ID 115 //
     /* 322297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 322300 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 322303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 322307 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 322311 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 322315 */   // (mulhs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMULHrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 322315 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULHrr),
     /* 322320 */   GIR_RootConstrainSelectedInstOperands,
     /* 322321 */   // GIR_Coverage, 115,
     /* 322321 */   GIR_Done,
     /* 322322 */ // Label 6421: @322322
     /* 322322 */ GIM_Reject,
     /* 322323 */ // Label 6417: @322323
     /* 322323 */ GIM_Try, /*On fail goto*//*Label 6422*/ GIMT_Encode4(322457), // Rule ID 7169 //
     /* 322328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 322331 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 322334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322338 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322342 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322346 */   // (mulhs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } (SMULLv2i32_v2i64:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v4i32] }:$Rm, dsub:{ *:[i32] })), (SMULLv4i32_v2i64:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm))
     /* 322346 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 322349 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
     /* 322353 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322358 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 322362 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 322366 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 322368 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 322371 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322375 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322380 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 322386 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322391 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322396 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 322399 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322403 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322408 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 322414 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322419 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322424 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322427 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
     /* 322431 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322436 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 322439 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 322442 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 322444 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 322447 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 322449 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322452 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 322455 */   GIR_RootConstrainSelectedInstOperands,
     /* 322456 */   // GIR_Coverage, 7169,
     /* 322456 */   GIR_EraseRootFromParent_Done,
     /* 322457 */ // Label 6422: @322457
     /* 322457 */ GIM_Reject,
     /* 322458 */ // Label 6418: @322458
     /* 322458 */ GIM_Try, /*On fail goto*//*Label 6423*/ GIMT_Encode4(322592), // Rule ID 7168 //
     /* 322463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 322466 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 322469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322477 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322481 */   // (mulhs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } (SMULLv4i16_v4i32:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v8i16] }:$Rm, dsub:{ *:[i32] })), (SMULLv8i16_v4i32:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm))
     /* 322481 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 322484 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
     /* 322488 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322493 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 322497 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 322501 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 322503 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 322506 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322510 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322515 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 322521 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322526 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322531 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 322534 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322538 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322543 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 322549 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322554 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322559 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322562 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
     /* 322566 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322571 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 322574 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 322577 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 322579 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 322582 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 322584 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322587 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 322590 */   GIR_RootConstrainSelectedInstOperands,
     /* 322591 */   // GIR_Coverage, 7168,
     /* 322591 */   GIR_EraseRootFromParent_Done,
     /* 322592 */ // Label 6423: @322592
     /* 322592 */ GIM_Reject,
     /* 322593 */ // Label 6419: @322593
     /* 322593 */ GIM_Try, /*On fail goto*//*Label 6424*/ GIMT_Encode4(322727), // Rule ID 7167 //
     /* 322598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 322601 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 322604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322608 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322612 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322616 */   // (mulhs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } (SMULLv8i8_v8i16:{ *:[f128] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v16i8] }:$Rm, dsub:{ *:[i32] })), (SMULLv16i8_v8i16:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm))
     /* 322616 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 322619 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
     /* 322623 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322628 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 322632 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 322636 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 322638 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 322641 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322645 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322650 */   GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 322656 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322661 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322666 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 322669 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 322673 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322678 */   GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 322684 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322689 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322694 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 322697 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
     /* 322701 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 322706 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 322709 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 322712 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 322714 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 322717 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 322719 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 322722 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
     /* 322725 */   GIR_RootConstrainSelectedInstOperands,
     /* 322726 */   // GIR_Coverage, 7167,
     /* 322726 */   GIR_EraseRootFromParent_Done,
     /* 322727 */ // Label 6424: @322727
     /* 322727 */ GIM_Reject,
     /* 322728 */ // Label 6420: @322728
     /* 322728 */ GIM_Reject,
     /* 322729 */ // Label 64: @322729
     /* 322729 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6437*/ GIMT_Encode4(323200),
     /* 322740 */ /*GILLT_s64*//*Label 6425*/ GIMT_Encode4(322824), GIMT_Encode4(0),
     /* 322748 */ /*GILLT_v2s32*//*Label 6426*/ GIMT_Encode4(322858),
     /* 322752 */ /*GILLT_v2s64*//*Label 6427*/ GIMT_Encode4(322892),
     /* 322756 */ /*GILLT_v4s16*//*Label 6428*/ GIMT_Encode4(322926),
     /* 322760 */ /*GILLT_v4s32*//*Label 6429*/ GIMT_Encode4(322960),
     /* 322764 */ /*GILLT_v8s8*//*Label 6430*/ GIMT_Encode4(322994),
     /* 322768 */ /*GILLT_v8s16*//*Label 6431*/ GIMT_Encode4(323028),
     /* 322772 */ /*GILLT_v16s8*//*Label 6432*/ GIMT_Encode4(323062), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 322792 */ /*GILLT_nxv2s64*//*Label 6433*/ GIMT_Encode4(323096), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 322804 */ /*GILLT_nxv4s32*//*Label 6434*/ GIMT_Encode4(323122), GIMT_Encode4(0),
     /* 322812 */ /*GILLT_nxv8s16*//*Label 6435*/ GIMT_Encode4(323148), GIMT_Encode4(0),
     /* 322820 */ /*GILLT_nxv16s8*//*Label 6436*/ GIMT_Encode4(323174),
     /* 322824 */ // Label 6425: @322824
     /* 322824 */ GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(322857), // Rule ID 1651 //
     /* 322829 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322832 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 322835 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 322838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322842 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322846 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322850 */   // (uaddsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 322850 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv1i64),
     /* 322855 */   GIR_RootConstrainSelectedInstOperands,
     /* 322856 */   // GIR_Coverage, 1651,
     /* 322856 */   GIR_Done,
     /* 322857 */ // Label 6438: @322857
     /* 322857 */ GIM_Reject,
     /* 322858 */ // Label 6426: @322858
     /* 322858 */ GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(322891), // Rule ID 1549 //
     /* 322863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322866 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 322869 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 322872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322876 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322880 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322884 */   // (uaddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 322884 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i32),
     /* 322889 */   GIR_RootConstrainSelectedInstOperands,
     /* 322890 */   // GIR_Coverage, 1549,
     /* 322890 */   GIR_Done,
     /* 322891 */ // Label 6439: @322891
     /* 322891 */ GIM_Reject,
     /* 322892 */ // Label 6427: @322892
     /* 322892 */ GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(322925), // Rule ID 1551 //
     /* 322897 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322900 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 322903 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 322906 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322910 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322914 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322918 */   // (uaddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 322918 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv2i64),
     /* 322923 */   GIR_RootConstrainSelectedInstOperands,
     /* 322924 */   // GIR_Coverage, 1551,
     /* 322924 */   GIR_Done,
     /* 322925 */ // Label 6440: @322925
     /* 322925 */ GIM_Reject,
     /* 322926 */ // Label 6428: @322926
     /* 322926 */ GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(322959), // Rule ID 1547 //
     /* 322931 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322934 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 322937 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 322940 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322944 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322948 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 322952 */   // (uaddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 322952 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i16),
     /* 322957 */   GIR_RootConstrainSelectedInstOperands,
     /* 322958 */   // GIR_Coverage, 1547,
     /* 322958 */   GIR_Done,
     /* 322959 */ // Label 6441: @322959
     /* 322959 */ GIM_Reject,
     /* 322960 */ // Label 6429: @322960
     /* 322960 */ GIM_Try, /*On fail goto*//*Label 6442*/ GIMT_Encode4(322993), // Rule ID 1550 //
     /* 322965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 322968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 322971 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 322974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322982 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 322986 */   // (uaddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 322986 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv4i32),
     /* 322991 */   GIR_RootConstrainSelectedInstOperands,
     /* 322992 */   // GIR_Coverage, 1550,
     /* 322992 */   GIR_Done,
     /* 322993 */ // Label 6442: @322993
     /* 322993 */ GIM_Reject,
     /* 322994 */ // Label 6430: @322994
     /* 322994 */ GIM_Try, /*On fail goto*//*Label 6443*/ GIMT_Encode4(323027), // Rule ID 1545 //
     /* 322999 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 323005 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 323008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323012 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323016 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323020 */   // (uaddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 323020 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i8),
     /* 323025 */   GIR_RootConstrainSelectedInstOperands,
     /* 323026 */   // GIR_Coverage, 1545,
     /* 323026 */   GIR_Done,
     /* 323027 */ // Label 6443: @323027
     /* 323027 */ GIM_Reject,
     /* 323028 */ // Label 6431: @323028
     /* 323028 */ GIM_Try, /*On fail goto*//*Label 6444*/ GIMT_Encode4(323061), // Rule ID 1548 //
     /* 323033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323036 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 323039 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 323042 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323046 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323050 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323054 */   // (uaddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 323054 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv8i16),
     /* 323059 */   GIR_RootConstrainSelectedInstOperands,
     /* 323060 */   // GIR_Coverage, 1548,
     /* 323060 */   GIR_Done,
     /* 323061 */ // Label 6444: @323061
     /* 323061 */ GIM_Reject,
     /* 323062 */ // Label 6432: @323062
     /* 323062 */ GIM_Try, /*On fail goto*//*Label 6445*/ GIMT_Encode4(323095), // Rule ID 1546 //
     /* 323067 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323070 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 323073 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 323076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323080 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323084 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323088 */   // (uaddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 323088 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADDv16i8),
     /* 323093 */   GIR_RootConstrainSelectedInstOperands,
     /* 323094 */   // GIR_Coverage, 1546,
     /* 323094 */   GIR_Done,
     /* 323095 */ // Label 6445: @323095
     /* 323095 */ GIM_Reject,
     /* 323096 */ // Label 6433: @323096
     /* 323096 */ GIM_Try, /*On fail goto*//*Label 6446*/ GIMT_Encode4(323121), // Rule ID 8117 //
     /* 323101 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 323104 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 323107 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 323110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 323114 */   // (uaddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 323114 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_D),
     /* 323119 */   GIR_RootConstrainSelectedInstOperands,
     /* 323120 */   // GIR_Coverage, 8117,
     /* 323120 */   GIR_Done,
     /* 323121 */ // Label 6446: @323121
     /* 323121 */ GIM_Reject,
     /* 323122 */ // Label 6434: @323122
     /* 323122 */ GIM_Try, /*On fail goto*//*Label 6447*/ GIMT_Encode4(323147), // Rule ID 8116 //
     /* 323127 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 323130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 323133 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 323136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 323140 */   // (uaddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 323140 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_S),
     /* 323145 */   GIR_RootConstrainSelectedInstOperands,
     /* 323146 */   // GIR_Coverage, 8116,
     /* 323146 */   GIR_Done,
     /* 323147 */ // Label 6447: @323147
     /* 323147 */ GIM_Reject,
     /* 323148 */ // Label 6435: @323148
     /* 323148 */ GIM_Try, /*On fail goto*//*Label 6448*/ GIMT_Encode4(323173), // Rule ID 8115 //
     /* 323153 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 323156 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 323159 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 323162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 323166 */   // (uaddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 323166 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_H),
     /* 323171 */   GIR_RootConstrainSelectedInstOperands,
     /* 323172 */   // GIR_Coverage, 8115,
     /* 323172 */   GIR_Done,
     /* 323173 */ // Label 6448: @323173
     /* 323173 */ GIM_Reject,
     /* 323174 */ // Label 6436: @323174
     /* 323174 */ GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(323199), // Rule ID 8114 //
     /* 323179 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 323182 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 323185 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 323188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 323192 */   // (uaddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 323192 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQADD_ZZZ_B),
     /* 323197 */   GIR_RootConstrainSelectedInstOperands,
     /* 323198 */   // GIR_Coverage, 8114,
     /* 323198 */   GIR_Done,
     /* 323199 */ // Label 6449: @323199
     /* 323199 */ GIM_Reject,
     /* 323200 */ // Label 6437: @323200
     /* 323200 */ GIM_Reject,
     /* 323201 */ // Label 65: @323201
     /* 323201 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6462*/ GIMT_Encode4(325576),
     /* 323212 */ /*GILLT_s64*//*Label 6450*/ GIMT_Encode4(323296), GIMT_Encode4(0),
     /* 323220 */ /*GILLT_v2s32*//*Label 6451*/ GIMT_Encode4(323330),
     /* 323224 */ /*GILLT_v2s64*//*Label 6452*/ GIMT_Encode4(323364),
     /* 323228 */ /*GILLT_v4s16*//*Label 6453*/ GIMT_Encode4(324350),
     /* 323232 */ /*GILLT_v4s32*//*Label 6454*/ GIMT_Encode4(324384),
     /* 323236 */ /*GILLT_v8s8*//*Label 6455*/ GIMT_Encode4(325370),
     /* 323240 */ /*GILLT_v8s16*//*Label 6456*/ GIMT_Encode4(325404),
     /* 323244 */ /*GILLT_v16s8*//*Label 6457*/ GIMT_Encode4(325438), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 323264 */ /*GILLT_nxv2s64*//*Label 6458*/ GIMT_Encode4(325472), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 323276 */ /*GILLT_nxv4s32*//*Label 6459*/ GIMT_Encode4(325498), GIMT_Encode4(0),
     /* 323284 */ /*GILLT_nxv8s16*//*Label 6460*/ GIMT_Encode4(325524), GIMT_Encode4(0),
     /* 323292 */ /*GILLT_nxv16s8*//*Label 6461*/ GIMT_Encode4(325550),
     /* 323296 */ // Label 6450: @323296
     /* 323296 */ GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(323329), // Rule ID 1642 //
     /* 323301 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323304 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 323307 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 323310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323314 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323318 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323322 */   // (saddsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQADDv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 323322 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv1i64),
     /* 323327 */   GIR_RootConstrainSelectedInstOperands,
     /* 323328 */   // GIR_Coverage, 1642,
     /* 323328 */   GIR_Done,
     /* 323329 */ // Label 6463: @323329
     /* 323329 */ GIM_Reject,
     /* 323330 */ // Label 6451: @323330
     /* 323330 */ GIM_Try, /*On fail goto*//*Label 6464*/ GIMT_Encode4(323363), // Rule ID 1438 //
     /* 323335 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 323341 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323348 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323352 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323356 */   // (saddsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQADDv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 323356 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i32),
     /* 323361 */   GIR_RootConstrainSelectedInstOperands,
     /* 323362 */   // GIR_Coverage, 1438,
     /* 323362 */   GIR_Done,
     /* 323363 */ // Label 6464: @323363
     /* 323363 */ GIM_Reject,
     /* 323364 */ // Label 6452: @323364
     /* 323364 */ GIM_Try, /*On fail goto*//*Label 6465*/ GIMT_Encode4(324349),
     /* 323369 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 323372 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 323375 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323379 */   GIM_Try, /*On fail goto*//*Label 6466*/ GIMT_Encode4(323501), // Rule ID 14548 //
     /* 323384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323387 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323391 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323395 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323398 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323403 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323407 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323411 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 323415 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 323419 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323423 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 323427 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 323431 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323435 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 323439 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323444 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 323448 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323452 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 323456 */     // MIs[4] Operand 1
     /* 323456 */     // No operand predicates
     /* 323456 */     // MIs[2] Operand 2
     /* 323456 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 323467 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323471 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 323473 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323480 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 323480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_indexed),
     /* 323483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323485 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 323487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 323492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 323496 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 323499 */     GIR_RootConstrainSelectedInstOperands,
     /* 323500 */     // GIR_Coverage, 14548,
     /* 323500 */     GIR_EraseRootFromParent_Done,
     /* 323501 */   // Label 6466: @323501
     /* 323501 */   GIM_Try, /*On fail goto*//*Label 6467*/ GIMT_Encode4(323623), // Rule ID 2091 //
     /* 323506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323509 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323521 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323524 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323533 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 323541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 323545 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323549 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 323553 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 323557 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323561 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 323565 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323570 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 323574 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323578 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 323582 */     // MIs[4] Operand 1
     /* 323582 */     // No operand predicates
     /* 323582 */     // MIs[2] Operand 2
     /* 323582 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 323593 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 323595 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323602 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SQDMLALv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 323602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_indexed),
     /* 323605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323607 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 323609 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 323614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 323618 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 323621 */     GIR_RootConstrainSelectedInstOperands,
     /* 323622 */     // GIR_Coverage, 2091,
     /* 323622 */     GIR_EraseRootFromParent_Done,
     /* 323623 */   // Label 6467: @323623
     /* 323623 */   GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(323742), // Rule ID 14546 //
     /* 323628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323639 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323642 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323651 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323655 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323660 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 323664 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 323668 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323672 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 323676 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 323680 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323684 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 323688 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323693 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 323697 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323701 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 323705 */     // MIs[4] Operand 1
     /* 323705 */     // No operand predicates
     /* 323705 */     // MIs[2] Operand 2
     /* 323705 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 323716 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323720 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 323722 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 323722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 323725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 323729 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 323733 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 323737 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 323740 */     GIR_RootConstrainSelectedInstOperands,
     /* 323741 */     // GIR_Coverage, 14546,
     /* 323741 */     GIR_EraseRootFromParent_Done,
     /* 323742 */   // Label 6468: @323742
     /* 323742 */   GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(323861), // Rule ID 2089 //
     /* 323747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323750 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323754 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323758 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323762 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323765 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323770 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323774 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323778 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 323783 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 323787 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 323791 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323795 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 323799 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 323803 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 323807 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 323811 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323816 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 323820 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 323824 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 323828 */     // MIs[4] Operand 1
     /* 323828 */     // No operand predicates
     /* 323828 */     // MIs[2] Operand 2
     /* 323828 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 323839 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 323841 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 323841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 323844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323846 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 323848 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 323852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 323856 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 323859 */     GIR_RootConstrainSelectedInstOperands,
     /* 323860 */     // GIR_Coverage, 2089,
     /* 323860 */     GIR_EraseRootFromParent_Done,
     /* 323861 */   // Label 6469: @323861
     /* 323861 */   GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(323932), // Rule ID 14452 //
     /* 323866 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 323873 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323877 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323880 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323885 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323889 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323897 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 323899 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323906 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323913 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 323913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_v2i64),
     /* 323916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323918 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 323920 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 323925 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 323930 */     GIR_RootConstrainSelectedInstOperands,
     /* 323931 */     // GIR_Coverage, 14452,
     /* 323931 */     GIR_EraseRootFromParent_Done,
     /* 323932 */   // Label 6470: @323932
     /* 323932 */   GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(324003), // Rule ID 1776 //
     /* 323937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 323940 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 323944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 323948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 323952 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 323955 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 323960 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 323964 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 323968 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 323970 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323977 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 323984 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SQDMLALv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 323984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i32_v2i64),
     /* 323987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 323989 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 323991 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 323996 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 324001 */     GIR_RootConstrainSelectedInstOperands,
     /* 324002 */     // GIR_Coverage, 1776,
     /* 324002 */     GIR_EraseRootFromParent_Done,
     /* 324003 */   // Label 6471: @324003
     /* 324003 */   GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(324099), // Rule ID 14547 //
     /* 324008 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324015 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324019 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324022 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324027 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 324031 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 324035 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 324048 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 324052 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 324056 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324061 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 324065 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324069 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 324073 */     // MIs[3] Operand 1
     /* 324073 */     // No operand predicates
     /* 324073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324077 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324079 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 324082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324084 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 324086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324090 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324094 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 324097 */     GIR_RootConstrainSelectedInstOperands,
     /* 324098 */     // GIR_Coverage, 14547,
     /* 324098 */     GIR_EraseRootFromParent_Done,
     /* 324099 */   // Label 6472: @324099
     /* 324099 */   GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(324195), // Rule ID 2090 //
     /* 324104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324107 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324119 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324122 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324127 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 324131 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 324135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324140 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324144 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 324148 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 324152 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 324156 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324161 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 324165 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324169 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 324173 */     // MIs[3] Operand 1
     /* 324173 */     // No operand predicates
     /* 324173 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 324175 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLALv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_indexed),
     /* 324178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324180 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 324182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 324190 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 324193 */     GIR_RootConstrainSelectedInstOperands,
     /* 324194 */     // GIR_Coverage, 2090,
     /* 324194 */     GIR_EraseRootFromParent_Done,
     /* 324195 */   // Label 6473: @324195
     /* 324195 */   GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(324260), // Rule ID 14451 //
     /* 324200 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324207 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324211 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324214 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324219 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 324223 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 324227 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324232 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324237 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324241 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324243 */     // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm), V128:{ *:[v2i64] }:$Rd)  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 324243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_v2i64),
     /* 324246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 324250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324254 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 324258 */     GIR_RootConstrainSelectedInstOperands,
     /* 324259 */     // GIR_Coverage, 14451,
     /* 324259 */     GIR_EraseRootFromParent_Done,
     /* 324260 */   // Label 6474: @324260
     /* 324260 */   GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(324325), // Rule ID 1775 //
     /* 324265 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324268 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324280 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324283 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324288 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 324292 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 324296 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324301 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324306 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324308 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLALv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 324308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv2i32_v2i64),
     /* 324311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324313 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 324315 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324319 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 324323 */     GIR_RootConstrainSelectedInstOperands,
     /* 324324 */     // GIR_Coverage, 1775,
     /* 324324 */     GIR_EraseRootFromParent_Done,
     /* 324325 */   // Label 6475: @324325
     /* 324325 */   GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(324348), // Rule ID 1440 //
     /* 324330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324333 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324337 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324341 */     // (saddsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQADDv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 324341 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv2i64),
     /* 324346 */     GIR_RootConstrainSelectedInstOperands,
     /* 324347 */     // GIR_Coverage, 1440,
     /* 324347 */     GIR_Done,
     /* 324348 */   // Label 6476: @324348
     /* 324348 */   GIM_Reject,
     /* 324349 */ // Label 6465: @324349
     /* 324349 */ GIM_Reject,
     /* 324350 */ // Label 6453: @324350
     /* 324350 */ GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(324383), // Rule ID 1436 //
     /* 324355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324358 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 324361 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324368 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324372 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324376 */   // (saddsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQADDv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 324376 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i16),
     /* 324381 */   GIR_RootConstrainSelectedInstOperands,
     /* 324382 */   // GIR_Coverage, 1436,
     /* 324382 */   GIR_Done,
     /* 324383 */ // Label 6477: @324383
     /* 324383 */ GIM_Reject,
     /* 324384 */ // Label 6454: @324384
     /* 324384 */ GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(325369),
     /* 324389 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 324392 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 324395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324399 */   GIM_Try, /*On fail goto*//*Label 6479*/ GIMT_Encode4(324521), // Rule ID 14545 //
     /* 324404 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324407 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324411 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324415 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324418 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324423 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324427 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324431 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324435 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 324439 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324443 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 324447 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324451 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324455 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 324459 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324464 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 324468 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324472 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324476 */     // MIs[4] Operand 1
     /* 324476 */     // No operand predicates
     /* 324476 */     // MIs[2] Operand 2
     /* 324476 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 324487 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324491 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 324493 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 324500 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_indexed),
     /* 324503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324505 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 324507 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 324512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 324516 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 324519 */     GIR_RootConstrainSelectedInstOperands,
     /* 324520 */     // GIR_Coverage, 14545,
     /* 324520 */     GIR_EraseRootFromParent_Done,
     /* 324521 */   // Label 6479: @324521
     /* 324521 */   GIM_Try, /*On fail goto*//*Label 6480*/ GIMT_Encode4(324643), // Rule ID 2088 //
     /* 324526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324529 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324533 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324537 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324541 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324544 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324549 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324553 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324557 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324561 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 324565 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324569 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 324573 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324577 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324581 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 324585 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324590 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 324594 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324598 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324602 */     // MIs[4] Operand 1
     /* 324602 */     // No operand predicates
     /* 324602 */     // MIs[2] Operand 2
     /* 324602 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 324613 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 324615 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 324622 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SQDMLALv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_indexed),
     /* 324625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324627 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 324629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 324634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 324638 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 324641 */     GIR_RootConstrainSelectedInstOperands,
     /* 324642 */     // GIR_Coverage, 2088,
     /* 324642 */     GIR_EraseRootFromParent_Done,
     /* 324643 */   // Label 6480: @324643
     /* 324643 */   GIM_Try, /*On fail goto*//*Label 6481*/ GIMT_Encode4(324762), // Rule ID 14543 //
     /* 324648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324659 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324662 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324667 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324671 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324675 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 324688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324692 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 324696 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324700 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324704 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 324708 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324713 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 324717 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324721 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324725 */     // MIs[4] Operand 1
     /* 324725 */     // No operand predicates
     /* 324725 */     // MIs[2] Operand 2
     /* 324725 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 324736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324740 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 324742 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 324745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 324749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324753 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 324757 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 324760 */     GIR_RootConstrainSelectedInstOperands,
     /* 324761 */     // GIR_Coverage, 14543,
     /* 324761 */     GIR_EraseRootFromParent_Done,
     /* 324762 */   // Label 6481: @324762
     /* 324762 */   GIM_Try, /*On fail goto*//*Label 6482*/ GIMT_Encode4(324881), // Rule ID 2086 //
     /* 324767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324770 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324782 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324785 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324790 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324794 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324798 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 324803 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 324807 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 324811 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324815 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 324819 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 324823 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 324827 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 324831 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 324836 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 324840 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 324844 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 324848 */     // MIs[4] Operand 1
     /* 324848 */     // No operand predicates
     /* 324848 */     // MIs[2] Operand 2
     /* 324848 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 324859 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 324861 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 324861 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 324864 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324866 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 324868 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 324872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 324876 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 324879 */     GIR_RootConstrainSelectedInstOperands,
     /* 324880 */     // GIR_Coverage, 2086,
     /* 324880 */     GIR_EraseRootFromParent_Done,
     /* 324881 */   // Label 6482: @324881
     /* 324881 */   GIM_Try, /*On fail goto*//*Label 6483*/ GIMT_Encode4(324952), // Rule ID 14450 //
     /* 324886 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324889 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 324893 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324897 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324900 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324905 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324909 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324917 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324919 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 324926 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 324933 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 324933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_v4i32),
     /* 324936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 324938 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 324940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 324945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 324950 */     GIR_RootConstrainSelectedInstOperands,
     /* 324951 */     // GIR_Coverage, 14450,
     /* 324951 */     GIR_EraseRootFromParent_Done,
     /* 324952 */   // Label 6483: @324952
     /* 324952 */   GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(325023), // Rule ID 1774 //
     /* 324957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 324960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 324964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 324968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 324972 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 324975 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 324980 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 324984 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 324988 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 324990 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 324997 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 325004 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SQDMLALv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 325004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv8i16_v4i32),
     /* 325007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325009 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 325011 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 325016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 325021 */     GIR_RootConstrainSelectedInstOperands,
     /* 325022 */     // GIR_Coverage, 1774,
     /* 325022 */     GIR_EraseRootFromParent_Done,
     /* 325023 */   // Label 6484: @325023
     /* 325023 */   GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(325119), // Rule ID 14544 //
     /* 325028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325031 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325035 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 325039 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 325042 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 325047 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 325051 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 325055 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325060 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 325064 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 325068 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 325072 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 325076 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 325081 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 325085 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 325089 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 325093 */     // MIs[3] Operand 1
     /* 325093 */     // No operand predicates
     /* 325093 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325097 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 325099 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 325099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 325102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325104 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 325106 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 325110 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325114 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 325117 */     GIR_RootConstrainSelectedInstOperands,
     /* 325118 */     // GIR_Coverage, 14544,
     /* 325118 */     GIR_EraseRootFromParent_Done,
     /* 325119 */   // Label 6485: @325119
     /* 325119 */   GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(325215), // Rule ID 2087 //
     /* 325124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 325135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 325139 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 325142 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 325147 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 325151 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 325155 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325160 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 325164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 325168 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 325172 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 325176 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 325181 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 325185 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 325189 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 325193 */     // MIs[3] Operand 1
     /* 325193 */     // No operand predicates
     /* 325193 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 325195 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SQDMLALv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 325195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_indexed),
     /* 325198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325200 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 325202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 325206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 325210 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 325213 */     GIR_RootConstrainSelectedInstOperands,
     /* 325214 */     // GIR_Coverage, 2087,
     /* 325214 */     GIR_EraseRootFromParent_Done,
     /* 325215 */   // Label 6486: @325215
     /* 325215 */   GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(325280), // Rule ID 14449 //
     /* 325220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 325227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 325231 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 325234 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 325239 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 325243 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 325247 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325252 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325257 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325261 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325263 */     // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm), V128:{ *:[v4i32] }:$Rd)  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 325263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_v4i32),
     /* 325266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325268 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rd
     /* 325270 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 325274 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 325278 */     GIR_RootConstrainSelectedInstOperands,
     /* 325279 */     // GIR_Coverage, 14449,
     /* 325279 */     GIR_EraseRootFromParent_Done,
     /* 325280 */   // Label 6487: @325280
     /* 325280 */   GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(325345), // Rule ID 1773 //
     /* 325285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325288 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 325296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 325300 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 325303 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 325308 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 325312 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 325316 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325321 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325326 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 325328 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLALv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 325328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLALv4i16_v4i32),
     /* 325331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 325333 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 325335 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 325339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 325343 */     GIR_RootConstrainSelectedInstOperands,
     /* 325344 */     // GIR_Coverage, 1773,
     /* 325344 */     GIR_EraseRootFromParent_Done,
     /* 325345 */   // Label 6488: @325345
     /* 325345 */   GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(325368), // Rule ID 1439 //
     /* 325350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325353 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325357 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325361 */     // (saddsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQADDv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 325361 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv4i32),
     /* 325366 */     GIR_RootConstrainSelectedInstOperands,
     /* 325367 */     // GIR_Coverage, 1439,
     /* 325367 */     GIR_Done,
     /* 325368 */   // Label 6489: @325368
     /* 325368 */   GIM_Reject,
     /* 325369 */ // Label 6478: @325369
     /* 325369 */ GIM_Reject,
     /* 325370 */ // Label 6455: @325370
     /* 325370 */ GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(325403), // Rule ID 1434 //
     /* 325375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 325381 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 325384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325388 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325392 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325396 */   // (saddsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQADDv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 325396 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i8),
     /* 325401 */   GIR_RootConstrainSelectedInstOperands,
     /* 325402 */   // GIR_Coverage, 1434,
     /* 325402 */   GIR_Done,
     /* 325403 */ // Label 6490: @325403
     /* 325403 */ GIM_Reject,
     /* 325404 */ // Label 6456: @325404
     /* 325404 */ GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(325437), // Rule ID 1437 //
     /* 325409 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325412 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 325415 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 325418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325422 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325426 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325430 */   // (saddsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQADDv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 325430 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv8i16),
     /* 325435 */   GIR_RootConstrainSelectedInstOperands,
     /* 325436 */   // GIR_Coverage, 1437,
     /* 325436 */   GIR_Done,
     /* 325437 */ // Label 6491: @325437
     /* 325437 */ GIM_Reject,
     /* 325438 */ // Label 6457: @325438
     /* 325438 */ GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(325471), // Rule ID 1435 //
     /* 325443 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325446 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 325449 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 325452 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325456 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325460 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325464 */   // (saddsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQADDv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 325464 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADDv16i8),
     /* 325469 */   GIR_RootConstrainSelectedInstOperands,
     /* 325470 */   // GIR_Coverage, 1435,
     /* 325470 */   GIR_Done,
     /* 325471 */ // Label 6492: @325471
     /* 325471 */ GIM_Reject,
     /* 325472 */ // Label 6458: @325472
     /* 325472 */ GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(325497), // Rule ID 8113 //
     /* 325477 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325480 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 325483 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 325486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325490 */   // (saddsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQADD_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 325490 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_D),
     /* 325495 */   GIR_RootConstrainSelectedInstOperands,
     /* 325496 */   // GIR_Coverage, 8113,
     /* 325496 */   GIR_Done,
     /* 325497 */ // Label 6493: @325497
     /* 325497 */ GIM_Reject,
     /* 325498 */ // Label 6459: @325498
     /* 325498 */ GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(325523), // Rule ID 8112 //
     /* 325503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325506 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 325509 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 325512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325516 */   // (saddsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQADD_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 325516 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_S),
     /* 325521 */   GIR_RootConstrainSelectedInstOperands,
     /* 325522 */   // GIR_Coverage, 8112,
     /* 325522 */   GIR_Done,
     /* 325523 */ // Label 6494: @325523
     /* 325523 */ GIM_Reject,
     /* 325524 */ // Label 6460: @325524
     /* 325524 */ GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(325549), // Rule ID 8111 //
     /* 325529 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325532 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 325535 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 325538 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325542 */   // (saddsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQADD_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 325542 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_H),
     /* 325547 */   GIR_RootConstrainSelectedInstOperands,
     /* 325548 */   // GIR_Coverage, 8111,
     /* 325548 */   GIR_Done,
     /* 325549 */ // Label 6495: @325549
     /* 325549 */ GIM_Reject,
     /* 325550 */ // Label 6461: @325550
     /* 325550 */ GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(325575), // Rule ID 8110 //
     /* 325555 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325558 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 325561 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 325564 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325568 */   // (saddsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQADD_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 325568 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQADD_ZZZ_B),
     /* 325573 */   GIR_RootConstrainSelectedInstOperands,
     /* 325574 */   // GIR_Coverage, 8110,
     /* 325574 */   GIR_Done,
     /* 325575 */ // Label 6496: @325575
     /* 325575 */ GIM_Reject,
     /* 325576 */ // Label 6462: @325576
     /* 325576 */ GIM_Reject,
     /* 325577 */ // Label 66: @325577
     /* 325577 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6509*/ GIMT_Encode4(326048),
     /* 325588 */ /*GILLT_s64*//*Label 6497*/ GIMT_Encode4(325672), GIMT_Encode4(0),
     /* 325596 */ /*GILLT_v2s32*//*Label 6498*/ GIMT_Encode4(325706),
     /* 325600 */ /*GILLT_v2s64*//*Label 6499*/ GIMT_Encode4(325740),
     /* 325604 */ /*GILLT_v4s16*//*Label 6500*/ GIMT_Encode4(325774),
     /* 325608 */ /*GILLT_v4s32*//*Label 6501*/ GIMT_Encode4(325808),
     /* 325612 */ /*GILLT_v8s8*//*Label 6502*/ GIMT_Encode4(325842),
     /* 325616 */ /*GILLT_v8s16*//*Label 6503*/ GIMT_Encode4(325876),
     /* 325620 */ /*GILLT_v16s8*//*Label 6504*/ GIMT_Encode4(325910), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 325640 */ /*GILLT_nxv2s64*//*Label 6505*/ GIMT_Encode4(325944), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 325652 */ /*GILLT_nxv4s32*//*Label 6506*/ GIMT_Encode4(325970), GIMT_Encode4(0),
     /* 325660 */ /*GILLT_nxv8s16*//*Label 6507*/ GIMT_Encode4(325996), GIMT_Encode4(0),
     /* 325668 */ /*GILLT_nxv16s8*//*Label 6508*/ GIMT_Encode4(326022),
     /* 325672 */ // Label 6497: @325672
     /* 325672 */ GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(325705), // Rule ID 1654 //
     /* 325677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325680 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 325683 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 325686 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325690 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325694 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325698 */   // (usubsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (UQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 325698 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv1i64),
     /* 325703 */   GIR_RootConstrainSelectedInstOperands,
     /* 325704 */   // GIR_Coverage, 1654,
     /* 325704 */   GIR_Done,
     /* 325705 */ // Label 6510: @325705
     /* 325705 */ GIM_Reject,
     /* 325706 */ // Label 6498: @325706
     /* 325706 */ GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(325739), // Rule ID 1570 //
     /* 325711 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325714 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 325717 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 325720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325724 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325728 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325732 */   // (usubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 325732 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i32),
     /* 325737 */   GIR_RootConstrainSelectedInstOperands,
     /* 325738 */   // GIR_Coverage, 1570,
     /* 325738 */   GIR_Done,
     /* 325739 */ // Label 6511: @325739
     /* 325739 */ GIM_Reject,
     /* 325740 */ // Label 6499: @325740
     /* 325740 */ GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(325773), // Rule ID 1572 //
     /* 325745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325748 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 325751 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 325754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325758 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325762 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325766 */   // (usubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 325766 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv2i64),
     /* 325771 */   GIR_RootConstrainSelectedInstOperands,
     /* 325772 */   // GIR_Coverage, 1572,
     /* 325772 */   GIR_Done,
     /* 325773 */ // Label 6512: @325773
     /* 325773 */ GIM_Reject,
     /* 325774 */ // Label 6500: @325774
     /* 325774 */ GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(325807), // Rule ID 1568 //
     /* 325779 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325782 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 325785 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 325788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325792 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325796 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325800 */   // (usubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 325800 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i16),
     /* 325805 */   GIR_RootConstrainSelectedInstOperands,
     /* 325806 */   // GIR_Coverage, 1568,
     /* 325806 */   GIR_Done,
     /* 325807 */ // Label 6513: @325807
     /* 325807 */ GIM_Reject,
     /* 325808 */ // Label 6501: @325808
     /* 325808 */ GIM_Try, /*On fail goto*//*Label 6514*/ GIMT_Encode4(325841), // Rule ID 1571 //
     /* 325813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 325819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 325822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325830 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325834 */   // (usubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 325834 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv4i32),
     /* 325839 */   GIR_RootConstrainSelectedInstOperands,
     /* 325840 */   // GIR_Coverage, 1571,
     /* 325840 */   GIR_Done,
     /* 325841 */ // Label 6514: @325841
     /* 325841 */ GIM_Reject,
     /* 325842 */ // Label 6502: @325842
     /* 325842 */ GIM_Try, /*On fail goto*//*Label 6515*/ GIMT_Encode4(325875), // Rule ID 1566 //
     /* 325847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325850 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 325853 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 325856 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325860 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325864 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 325868 */   // (usubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 325868 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i8),
     /* 325873 */   GIR_RootConstrainSelectedInstOperands,
     /* 325874 */   // GIR_Coverage, 1566,
     /* 325874 */   GIR_Done,
     /* 325875 */ // Label 6515: @325875
     /* 325875 */ GIM_Reject,
     /* 325876 */ // Label 6503: @325876
     /* 325876 */ GIM_Try, /*On fail goto*//*Label 6516*/ GIMT_Encode4(325909), // Rule ID 1569 //
     /* 325881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 325887 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 325890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325894 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325898 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325902 */   // (usubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 325902 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv8i16),
     /* 325907 */   GIR_RootConstrainSelectedInstOperands,
     /* 325908 */   // GIR_Coverage, 1569,
     /* 325908 */   GIR_Done,
     /* 325909 */ // Label 6516: @325909
     /* 325909 */ GIM_Reject,
     /* 325910 */ // Label 6504: @325910
     /* 325910 */ GIM_Try, /*On fail goto*//*Label 6517*/ GIMT_Encode4(325943), // Rule ID 1567 //
     /* 325915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 325918 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 325921 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 325924 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325928 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325932 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 325936 */   // (usubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 325936 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUBv16i8),
     /* 325941 */   GIR_RootConstrainSelectedInstOperands,
     /* 325942 */   // GIR_Coverage, 1567,
     /* 325942 */   GIR_Done,
     /* 325943 */ // Label 6517: @325943
     /* 325943 */ GIM_Reject,
     /* 325944 */ // Label 6505: @325944
     /* 325944 */ GIM_Try, /*On fail goto*//*Label 6518*/ GIMT_Encode4(325969), // Rule ID 8125 //
     /* 325949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325952 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 325955 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 325958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325962 */   // (usubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 325962 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_D),
     /* 325967 */   GIR_RootConstrainSelectedInstOperands,
     /* 325968 */   // GIR_Coverage, 8125,
     /* 325968 */   GIR_Done,
     /* 325969 */ // Label 6518: @325969
     /* 325969 */ GIM_Reject,
     /* 325970 */ // Label 6506: @325970
     /* 325970 */ GIM_Try, /*On fail goto*//*Label 6519*/ GIMT_Encode4(325995), // Rule ID 8124 //
     /* 325975 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 325978 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 325981 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 325984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 325988 */   // (usubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 325988 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_S),
     /* 325993 */   GIR_RootConstrainSelectedInstOperands,
     /* 325994 */   // GIR_Coverage, 8124,
     /* 325994 */   GIR_Done,
     /* 325995 */ // Label 6519: @325995
     /* 325995 */ GIM_Reject,
     /* 325996 */ // Label 6507: @325996
     /* 325996 */ GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(326021), // Rule ID 8123 //
     /* 326001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 326004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 326007 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 326010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 326014 */   // (usubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 326014 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_H),
     /* 326019 */   GIR_RootConstrainSelectedInstOperands,
     /* 326020 */   // GIR_Coverage, 8123,
     /* 326020 */   GIR_Done,
     /* 326021 */ // Label 6520: @326021
     /* 326021 */ GIM_Reject,
     /* 326022 */ // Label 6508: @326022
     /* 326022 */ GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(326047), // Rule ID 8122 //
     /* 326027 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 326030 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 326033 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 326036 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 326040 */   // (usubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 326040 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UQSUB_ZZZ_B),
     /* 326045 */   GIR_RootConstrainSelectedInstOperands,
     /* 326046 */   // GIR_Coverage, 8122,
     /* 326046 */   GIR_Done,
     /* 326047 */ // Label 6521: @326047
     /* 326047 */ GIM_Reject,
     /* 326048 */ // Label 6509: @326048
     /* 326048 */ GIM_Reject,
     /* 326049 */ // Label 67: @326049
     /* 326049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 6534*/ GIMT_Encode4(327438),
     /* 326060 */ /*GILLT_s64*//*Label 6522*/ GIMT_Encode4(326144), GIMT_Encode4(0),
     /* 326068 */ /*GILLT_v2s32*//*Label 6523*/ GIMT_Encode4(326178),
     /* 326072 */ /*GILLT_v2s64*//*Label 6524*/ GIMT_Encode4(326212),
     /* 326076 */ /*GILLT_v4s16*//*Label 6525*/ GIMT_Encode4(326705),
     /* 326080 */ /*GILLT_v4s32*//*Label 6526*/ GIMT_Encode4(326739),
     /* 326084 */ /*GILLT_v8s8*//*Label 6527*/ GIMT_Encode4(327232),
     /* 326088 */ /*GILLT_v8s16*//*Label 6528*/ GIMT_Encode4(327266),
     /* 326092 */ /*GILLT_v16s8*//*Label 6529*/ GIMT_Encode4(327300), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 326112 */ /*GILLT_nxv2s64*//*Label 6530*/ GIMT_Encode4(327334), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 326124 */ /*GILLT_nxv4s32*//*Label 6531*/ GIMT_Encode4(327360), GIMT_Encode4(0),
     /* 326132 */ /*GILLT_nxv8s16*//*Label 6532*/ GIMT_Encode4(327386), GIMT_Encode4(0),
     /* 326140 */ /*GILLT_nxv16s8*//*Label 6533*/ GIMT_Encode4(327412),
     /* 326144 */ // Label 6522: @326144
     /* 326144 */ GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(326177), // Rule ID 1647 //
     /* 326149 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326152 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 326155 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 326158 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326162 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326166 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326170 */   // (ssubsat:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)  =>  (SQSUBv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, FPR64:{ *:[v1i64] }:$Rm)
     /* 326170 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv1i64),
     /* 326175 */   GIR_RootConstrainSelectedInstOperands,
     /* 326176 */   // GIR_Coverage, 1647,
     /* 326176 */   GIR_Done,
     /* 326177 */ // Label 6535: @326177
     /* 326177 */ GIM_Reject,
     /* 326178 */ // Label 6523: @326178
     /* 326178 */ GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(326211), // Rule ID 1467 //
     /* 326183 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326186 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 326189 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326196 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326200 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326204 */   // (ssubsat:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SQSUBv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 326204 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i32),
     /* 326209 */   GIR_RootConstrainSelectedInstOperands,
     /* 326210 */   // GIR_Coverage, 1467,
     /* 326210 */   GIR_Done,
     /* 326211 */ // Label 6536: @326211
     /* 326211 */ GIM_Reject,
     /* 326212 */ // Label 6524: @326212
     /* 326212 */ GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(326704),
     /* 326217 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 326220 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 326223 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326227 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326231 */   GIM_Try, /*On fail goto*//*Label 6538*/ GIMT_Encode4(326349), // Rule ID 2098 //
     /* 326236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326247 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326250 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326255 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326259 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 326263 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 326267 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 326271 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326275 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 326279 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326283 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326287 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 326291 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326296 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 326300 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326304 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326308 */     // MIs[4] Operand 1
     /* 326308 */     // No operand predicates
     /* 326308 */     // MIs[2] Operand 2
     /* 326308 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 326319 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 326321 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 326328 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] })))  =>  (SQDMLSLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 326328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i32_indexed),
     /* 326331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326333 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 326340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 326344 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 326347 */     GIR_RootConstrainSelectedInstOperands,
     /* 326348 */     // GIR_Coverage, 2098,
     /* 326348 */     GIR_EraseRootFromParent_Done,
     /* 326349 */   // Label 6538: @326349
     /* 326349 */   GIM_Try, /*On fail goto*//*Label 6539*/ GIMT_Encode4(326464), // Rule ID 2096 //
     /* 326354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326365 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326368 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326373 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326377 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 326381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 326390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 326394 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326398 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 326402 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326406 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326410 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 326414 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326419 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 326423 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326427 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326431 */     // MIs[4] Operand 1
     /* 326431 */     // No operand predicates
     /* 326431 */     // MIs[2] Operand 2
     /* 326431 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 326442 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 326444 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 326444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_indexed),
     /* 326447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326449 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 326455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 326459 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 326462 */     GIR_RootConstrainSelectedInstOperands,
     /* 326463 */     // GIR_Coverage, 2096,
     /* 326463 */     GIR_EraseRootFromParent_Done,
     /* 326464 */   // Label 6539: @326464
     /* 326464 */   GIM_Try, /*On fail goto*//*Label 6540*/ GIMT_Encode4(326531), // Rule ID 1780 //
     /* 326469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326472 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326476 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326480 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326483 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326488 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326492 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 326496 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 326498 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 326505 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 326512 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm)))  =>  (SQDMLSLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 326512 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i32_v2i64),
     /* 326515 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326517 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 326524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 326529 */     GIR_RootConstrainSelectedInstOperands,
     /* 326530 */     // GIR_Coverage, 1780,
     /* 326530 */     GIR_EraseRootFromParent_Done,
     /* 326531 */   // Label 6540: @326531
     /* 326531 */   GIM_Try, /*On fail goto*//*Label 6541*/ GIMT_Encode4(326623), // Rule ID 2097 //
     /* 326536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326547 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326550 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326559 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 326563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326568 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 326572 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 326576 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326580 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 326584 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326589 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 326593 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326597 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 326601 */     // MIs[3] Operand 1
     /* 326601 */     // No operand predicates
     /* 326601 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 326603 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SQDMLSLv2i32_indexed:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 326603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_indexed),
     /* 326606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326608 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 326614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 326618 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 326621 */     GIR_RootConstrainSelectedInstOperands,
     /* 326622 */     // GIR_Coverage, 2097,
     /* 326622 */     GIR_EraseRootFromParent_Done,
     /* 326623 */   // Label 6541: @326623
     /* 326623 */   GIM_Try, /*On fail goto*//*Label 6542*/ GIMT_Encode4(326684), // Rule ID 1779 //
     /* 326628 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326631 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326635 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326639 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326642 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326647 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 326651 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 326655 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326660 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326665 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 326667 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (intrinsic_wo_chain:{ *:[v2i64] } 708:{ *:[iPTR] }, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm))  =>  (SQDMLSLv2i32_v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 326667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv2i32_v2i64),
     /* 326670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326672 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326674 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 326678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 326682 */     GIR_RootConstrainSelectedInstOperands,
     /* 326683 */     // GIR_Coverage, 1779,
     /* 326683 */     GIR_EraseRootFromParent_Done,
     /* 326684 */   // Label 6542: @326684
     /* 326684 */   GIM_Try, /*On fail goto*//*Label 6543*/ GIMT_Encode4(326703), // Rule ID 1469 //
     /* 326689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326696 */     // (ssubsat:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (SQSUBv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 326696 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv2i64),
     /* 326701 */     GIR_RootConstrainSelectedInstOperands,
     /* 326702 */     // GIR_Coverage, 1469,
     /* 326702 */     GIR_Done,
     /* 326703 */   // Label 6543: @326703
     /* 326703 */   GIM_Reject,
     /* 326704 */ // Label 6537: @326704
     /* 326704 */ GIM_Reject,
     /* 326705 */ // Label 6525: @326705
     /* 326705 */ GIM_Try, /*On fail goto*//*Label 6544*/ GIMT_Encode4(326738), // Rule ID 1465 //
     /* 326710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 326716 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 326719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326723 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326727 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326731 */   // (ssubsat:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SQSUBv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 326731 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i16),
     /* 326736 */   GIR_RootConstrainSelectedInstOperands,
     /* 326737 */   // GIR_Coverage, 1465,
     /* 326737 */   GIR_Done,
     /* 326738 */ // Label 6544: @326738
     /* 326738 */ GIM_Reject,
     /* 326739 */ // Label 6526: @326739
     /* 326739 */ GIM_Try, /*On fail goto*//*Label 6545*/ GIMT_Encode4(327231),
     /* 326744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 326747 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 326750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326754 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 326758 */   GIM_Try, /*On fail goto*//*Label 6546*/ GIMT_Encode4(326876), // Rule ID 2095 //
     /* 326763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326766 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326770 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326774 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326777 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326782 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 326786 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 326790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 326794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 326798 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 326802 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 326806 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 326810 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 326814 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 326818 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 326823 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 326827 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326831 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 326835 */     // MIs[4] Operand 1
     /* 326835 */     // No operand predicates
     /* 326835 */     // MIs[2] Operand 2
     /* 326835 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 326846 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 326848 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 326855 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] })))  =>  (SQDMLSLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 326855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv8i16_indexed),
     /* 326858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326860 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326862 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 326867 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 326871 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 326874 */     GIR_RootConstrainSelectedInstOperands,
     /* 326875 */     // GIR_Coverage, 2095,
     /* 326875 */     GIR_EraseRootFromParent_Done,
     /* 326876 */   // Label 6546: @326876
     /* 326876 */   GIM_Try, /*On fail goto*//*Label 6547*/ GIMT_Encode4(326991), // Rule ID 2093 //
     /* 326881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 326888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 326892 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 326895 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 326900 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 326904 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 326908 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 326913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 326917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 326921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 326925 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 326929 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 326933 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 326937 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 326941 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 326946 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 326950 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 326954 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 326958 */     // MIs[4] Operand 1
     /* 326958 */     // No operand predicates
     /* 326958 */     // MIs[2] Operand 2
     /* 326958 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(0),
     /* 326969 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 326971 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] })))  =>  (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 326971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_indexed),
     /* 326974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 326976 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 326978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 326982 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 326986 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 326989 */     GIR_RootConstrainSelectedInstOperands,
     /* 326990 */     // GIR_Coverage, 2093,
     /* 326990 */     GIR_EraseRootFromParent_Done,
     /* 326991 */   // Label 6547: @326991
     /* 326991 */   GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(327058), // Rule ID 1778 //
     /* 326996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 326999 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327003 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 327007 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 327010 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 327015 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 327019 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 327023 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 327025 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 327032 */     GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 327039 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm)))  =>  (SQDMLSLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 327039 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv8i16_v4i32),
     /* 327042 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327044 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 327046 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 327051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 327056 */     GIR_RootConstrainSelectedInstOperands,
     /* 327057 */     // GIR_Coverage, 1778,
     /* 327057 */     GIR_EraseRootFromParent_Done,
     /* 327058 */   // Label 6548: @327058
     /* 327058 */   GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(327150), // Rule ID 2094 //
     /* 327063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 327074 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 327077 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 327082 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 327086 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 327090 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327095 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/3, // MIs[2]
     /* 327099 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 327103 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327107 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327111 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 327116 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 327120 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 327124 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 327128 */     // MIs[3] Operand 1
     /* 327128 */     // No operand predicates
     /* 327128 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 327130 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)))  =>  (SQDMLSLv4i16_indexed:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 327130 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_indexed),
     /* 327133 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327135 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 327137 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 327141 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 327145 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 327148 */     GIR_RootConstrainSelectedInstOperands,
     /* 327149 */     // GIR_Coverage, 2094,
     /* 327149 */     GIR_EraseRootFromParent_Done,
     /* 327150 */   // Label 6549: @327150
     /* 327150 */   GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(327211), // Rule ID 1777 //
     /* 327155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 327162 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 327166 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 327169 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_sqdmull),
     /* 327174 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 327178 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 327182 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327187 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327192 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 327194 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (intrinsic_wo_chain:{ *:[v4i32] } 708:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm))  =>  (SQDMLSLv4i16_v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 327194 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SQDMLSLv4i16_v4i32),
     /* 327197 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 327199 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 327201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 327205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Rm
     /* 327209 */     GIR_RootConstrainSelectedInstOperands,
     /* 327210 */     // GIR_Coverage, 1777,
     /* 327210 */     GIR_EraseRootFromParent_Done,
     /* 327211 */   // Label 6550: @327211
     /* 327211 */   GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(327230), // Rule ID 1468 //
     /* 327216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327223 */     // (ssubsat:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SQSUBv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 327223 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv4i32),
     /* 327228 */     GIR_RootConstrainSelectedInstOperands,
     /* 327229 */     // GIR_Coverage, 1468,
     /* 327229 */     GIR_Done,
     /* 327230 */   // Label 6551: @327230
     /* 327230 */   GIM_Reject,
     /* 327231 */ // Label 6545: @327231
     /* 327231 */ GIM_Reject,
     /* 327232 */ // Label 6527: @327232
     /* 327232 */ GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(327265), // Rule ID 1463 //
     /* 327237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327240 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 327243 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 327246 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327250 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327254 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327258 */   // (ssubsat:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SQSUBv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 327258 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i8),
     /* 327263 */   GIR_RootConstrainSelectedInstOperands,
     /* 327264 */   // GIR_Coverage, 1463,
     /* 327264 */   GIR_Done,
     /* 327265 */ // Label 6552: @327265
     /* 327265 */ GIM_Reject,
     /* 327266 */ // Label 6528: @327266
     /* 327266 */ GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(327299), // Rule ID 1466 //
     /* 327271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327274 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327277 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 327280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327284 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327288 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327292 */   // (ssubsat:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SQSUBv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 327292 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv8i16),
     /* 327297 */   GIR_RootConstrainSelectedInstOperands,
     /* 327298 */   // GIR_Coverage, 1466,
     /* 327298 */   GIR_Done,
     /* 327299 */ // Label 6553: @327299
     /* 327299 */ GIM_Reject,
     /* 327300 */ // Label 6529: @327300
     /* 327300 */ GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(327333), // Rule ID 1464 //
     /* 327305 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 327308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 327311 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 327314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327318 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327322 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327326 */   // (ssubsat:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SQSUBv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 327326 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUBv16i8),
     /* 327331 */   GIR_RootConstrainSelectedInstOperands,
     /* 327332 */   // GIR_Coverage, 1464,
     /* 327332 */   GIR_Done,
     /* 327333 */ // Label 6554: @327333
     /* 327333 */ GIM_Reject,
     /* 327334 */ // Label 6530: @327334
     /* 327334 */ GIM_Try, /*On fail goto*//*Label 6555*/ GIMT_Encode4(327359), // Rule ID 8121 //
     /* 327339 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 327342 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 327345 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 327348 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 327352 */   // (ssubsat:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (SQSUB_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 327352 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_D),
     /* 327357 */   GIR_RootConstrainSelectedInstOperands,
     /* 327358 */   // GIR_Coverage, 8121,
     /* 327358 */   GIR_Done,
     /* 327359 */ // Label 6555: @327359
     /* 327359 */ GIM_Reject,
     /* 327360 */ // Label 6531: @327360
     /* 327360 */ GIM_Try, /*On fail goto*//*Label 6556*/ GIMT_Encode4(327385), // Rule ID 8120 //
     /* 327365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 327368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 327371 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 327374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 327378 */   // (ssubsat:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (SQSUB_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 327378 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_S),
     /* 327383 */   GIR_RootConstrainSelectedInstOperands,
     /* 327384 */   // GIR_Coverage, 8120,
     /* 327384 */   GIR_Done,
     /* 327385 */ // Label 6556: @327385
     /* 327385 */ GIM_Reject,
     /* 327386 */ // Label 6532: @327386
     /* 327386 */ GIM_Try, /*On fail goto*//*Label 6557*/ GIMT_Encode4(327411), // Rule ID 8119 //
     /* 327391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 327394 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 327397 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 327400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 327404 */   // (ssubsat:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (SQSUB_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 327404 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_H),
     /* 327409 */   GIR_RootConstrainSelectedInstOperands,
     /* 327410 */   // GIR_Coverage, 8119,
     /* 327410 */   GIR_Done,
     /* 327411 */ // Label 6557: @327411
     /* 327411 */ GIM_Reject,
     /* 327412 */ // Label 6533: @327412
     /* 327412 */ GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(327437), // Rule ID 8118 //
     /* 327417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 327420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 327423 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 327426 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 327430 */   // (ssubsat:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (SQSUB_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 327430 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSUB_ZZZ_B),
     /* 327435 */   GIR_RootConstrainSelectedInstOperands,
     /* 327436 */   // GIR_Coverage, 8118,
     /* 327436 */   GIR_Done,
     /* 327437 */ // Label 6558: @327437
     /* 327437 */ GIM_Reject,
     /* 327438 */ // Label 6534: @327438
     /* 327438 */ GIM_Reject,
     /* 327439 */ // Label 68: @327439
     /* 327439 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6570*/ GIMT_Encode4(329236),
     /* 327450 */ /*GILLT_s16*//*Label 6559*/ GIMT_Encode4(327534),
     /* 327454 */ /*GILLT_s32*//*Label 6560*/ GIMT_Encode4(327760),
     /* 327458 */ /*GILLT_s64*//*Label 6561*/ GIMT_Encode4(328114), GIMT_Encode4(0),
     /* 327466 */ /*GILLT_v2s32*//*Label 6562*/ GIMT_Encode4(328286),
     /* 327470 */ /*GILLT_v2s64*//*Label 6563*/ GIMT_Encode4(328324),
     /* 327474 */ /*GILLT_v4s16*//*Label 6564*/ GIMT_Encode4(328500),
     /* 327478 */ /*GILLT_v4s32*//*Label 6565*/ GIMT_Encode4(328538), GIMT_Encode4(0),
     /* 327486 */ /*GILLT_v8s16*//*Label 6566*/ GIMT_Encode4(328714), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 327510 */ /*GILLT_nxv2s64*//*Label 6567*/ GIMT_Encode4(329158), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 327522 */ /*GILLT_nxv4s32*//*Label 6568*/ GIMT_Encode4(329184), GIMT_Encode4(0),
     /* 327530 */ /*GILLT_nxv8s16*//*Label 6569*/ GIMT_Encode4(329210),
     /* 327534 */ // Label 6559: @327534
     /* 327534 */ GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(327759),
     /* 327539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 327542 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 327545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 327549 */   GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(327640), // Rule ID 7564 //
     /* 327554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327562 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327566 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327570 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327575 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 327579 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327583 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327587 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327591 */     // MIs[2] Rn
     /* 327591 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 327596 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 327600 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327602 */     // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 327602 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 327605 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 327609 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327614 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 327620 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327625 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 327633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 327635 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327638 */     GIR_RootConstrainSelectedInstOperands,
     /* 327639 */     // GIR_Coverage, 7564,
     /* 327639 */     GIR_EraseRootFromParent_Done,
     /* 327640 */   // Label 6572: @327640
     /* 327640 */   GIM_Try, /*On fail goto*//*Label 6573*/ GIMT_Encode4(327731), // Rule ID 15001 //
     /* 327645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327649 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327653 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 327657 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327666 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 327670 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327674 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327678 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327682 */     // MIs[2] Rn
     /* 327682 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 327687 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 327691 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327693 */     // (fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 327693 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 327696 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 327700 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327705 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 327711 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327716 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 327724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 327726 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327729 */     GIR_RootConstrainSelectedInstOperands,
     /* 327730 */     // GIR_Coverage, 15001,
     /* 327730 */     GIR_EraseRootFromParent_Done,
     /* 327731 */   // Label 6573: @327731
     /* 327731 */   GIM_Try, /*On fail goto*//*Label 6574*/ GIMT_Encode4(327758), // Rule ID 626 //
     /* 327736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 327739 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 327743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 327747 */     // (fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 327747 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
     /* 327752 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 327756 */     GIR_RootConstrainSelectedInstOperands,
     /* 327757 */     // GIR_Coverage, 626,
     /* 327757 */     GIR_Done,
     /* 327758 */   // Label 6574: @327758
     /* 327758 */   GIM_Reject,
     /* 327759 */ // Label 6571: @327759
     /* 327759 */ GIM_Reject,
     /* 327760 */ // Label 6560: @327760
     /* 327760 */ GIM_Try, /*On fail goto*//*Label 6575*/ GIMT_Encode4(328113),
     /* 327765 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 327768 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 327771 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 327775 */   GIM_Try, /*On fail goto*//*Label 6576*/ GIMT_Encode4(327866), // Rule ID 7562 //
     /* 327780 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327784 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327788 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 327792 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327796 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327801 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 327805 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327809 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327813 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327817 */     // MIs[2] Rn
     /* 327817 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 327822 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 327826 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327828 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 327828 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 327831 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 327835 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327840 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 327846 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327851 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 327859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 327861 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 327864 */     GIR_RootConstrainSelectedInstOperands,
     /* 327865 */     // GIR_Coverage, 7562,
     /* 327865 */     GIR_EraseRootFromParent_Done,
     /* 327866 */   // Label 6576: @327866
     /* 327866 */   GIM_Try, /*On fail goto*//*Label 6577*/ GIMT_Encode4(327930), // Rule ID 14176 //
     /* 327871 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327875 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327879 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 327883 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 327892 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 327896 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327900 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327904 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327908 */     // MIs[2] Rn
     /* 327908 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 327913 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 327917 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327919 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
     /* 327919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 327922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 327924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 327928 */     GIR_RootConstrainSelectedInstOperands,
     /* 327929 */     // GIR_Coverage, 14176,
     /* 327929 */     GIR_EraseRootFromParent_Done,
     /* 327930 */   // Label 6577: @327930
     /* 327930 */   GIM_Try, /*On fail goto*//*Label 6578*/ GIMT_Encode4(328021), // Rule ID 14999 //
     /* 327935 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 327939 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327943 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 327947 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 327951 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 327956 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 327960 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 327964 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 327968 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 327972 */     // MIs[2] Rn
     /* 327972 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 327977 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 327981 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 327983 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 327983 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 327986 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 327990 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 327995 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 328001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328006 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 328014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 328019 */     GIR_RootConstrainSelectedInstOperands,
     /* 328020 */     // GIR_Coverage, 14999,
     /* 328020 */     GIR_EraseRootFromParent_Done,
     /* 328021 */   // Label 6578: @328021
     /* 328021 */   GIM_Try, /*On fail goto*//*Label 6579*/ GIMT_Encode4(328085), // Rule ID 17178 //
     /* 328026 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328030 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328034 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 328038 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 328042 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328047 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 328051 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328055 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328059 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 328063 */     // MIs[2] Rn
     /* 328063 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328068 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 328072 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328074 */     // (fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } FPR64:{ *:[v2f32] }:$Rn)
     /* 328074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 328077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328079 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328083 */     GIR_RootConstrainSelectedInstOperands,
     /* 328084 */     // GIR_Coverage, 17178,
     /* 328084 */     GIR_EraseRootFromParent_Done,
     /* 328085 */   // Label 6579: @328085
     /* 328085 */   GIM_Try, /*On fail goto*//*Label 6580*/ GIMT_Encode4(328112), // Rule ID 628 //
     /* 328090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 328093 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 328097 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 328101 */     // (fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 328101 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
     /* 328106 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328110 */     GIR_RootConstrainSelectedInstOperands,
     /* 328111 */     // GIR_Coverage, 628,
     /* 328111 */     GIR_Done,
     /* 328112 */   // Label 6580: @328112
     /* 328112 */   GIM_Reject,
     /* 328113 */ // Label 6575: @328113
     /* 328113 */ GIM_Reject,
     /* 328114 */ // Label 6561: @328114
     /* 328114 */ GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(328285),
     /* 328119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 328122 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 328125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328129 */   GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(328193), // Rule ID 7560 //
     /* 328134 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328138 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328142 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328146 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 328150 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328155 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 328159 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328163 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328167 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 328171 */     // MIs[2] Rn
     /* 328171 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328176 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 328180 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328182 */     // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 328182 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 328185 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328187 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328191 */     GIR_RootConstrainSelectedInstOperands,
     /* 328192 */     // GIR_Coverage, 7560,
     /* 328192 */     GIR_EraseRootFromParent_Done,
     /* 328193 */   // Label 6582: @328193
     /* 328193 */   GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(328257), // Rule ID 14997 //
     /* 328198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 328214 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328219 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 328223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 328231 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 328235 */     // MIs[2] Rn
     /* 328235 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328240 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 328244 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328246 */     // (fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 328246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 328249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328251 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328255 */     GIR_RootConstrainSelectedInstOperands,
     /* 328256 */     // GIR_Coverage, 14997,
     /* 328256 */     GIR_EraseRootFromParent_Done,
     /* 328257 */   // Label 6583: @328257
     /* 328257 */   GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(328284), // Rule ID 630 //
     /* 328262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 328265 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328273 */     // (fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 328273 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
     /* 328278 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328282 */     GIR_RootConstrainSelectedInstOperands,
     /* 328283 */     // GIR_Coverage, 630,
     /* 328283 */     GIR_Done,
     /* 328284 */   // Label 6584: @328284
     /* 328284 */   GIM_Reject,
     /* 328285 */ // Label 6581: @328285
     /* 328285 */ GIM_Reject,
     /* 328286 */ // Label 6562: @328286
     /* 328286 */ GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(328323), // Rule ID 1233 //
     /* 328291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328294 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 328297 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 328300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328308 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328312 */   // (fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 328312 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
     /* 328317 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328321 */   GIR_RootConstrainSelectedInstOperands,
     /* 328322 */   // GIR_Coverage, 1233,
     /* 328322 */   GIR_Done,
     /* 328323 */ // Label 6585: @328323
     /* 328323 */ GIM_Reject,
     /* 328324 */ // Label 6563: @328324
     /* 328324 */ GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(328499),
     /* 328329 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328332 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 328335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328339 */   GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(328405), // Rule ID 7582 //
     /* 328344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328348 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP1),
     /* 328352 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328356 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 328360 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328365 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328370 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328374 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP2),
     /* 328378 */     // MIs[2] Rn
     /* 328378 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328383 */     // MIs[2] Rm
     /* 328383 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328388 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328390 */     // (fadd:{ *:[v2f64] } (AArch64zip1:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm), (AArch64zip2:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm))  =>  (FADDPv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm)
     /* 328390 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 328393 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328399 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328403 */     GIR_RootConstrainSelectedInstOperands,
     /* 328404 */     // GIR_Coverage, 7582,
     /* 328404 */     GIR_EraseRootFromParent_Done,
     /* 328405 */   // Label 6587: @328405
     /* 328405 */   GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(328471), // Rule ID 15009 //
     /* 328410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_ZIP2),
     /* 328418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 328422 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 328426 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328431 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328436 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328440 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_ZIP1),
     /* 328444 */     // MIs[2] Rn
     /* 328444 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328449 */     // MIs[2] Rm
     /* 328449 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328454 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328456 */     // (fadd:{ *:[v2f64] } (AArch64zip2:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm), (AArch64zip1:{ *:[v2f64] } FPR128:{ *:[v2f64] }:$Rn, FPR128:{ *:[v2f64] }:$Rm))  =>  (FADDPv2f64:{ *:[v2f64] } ?:{ *:[v2f64] }:$Rn, ?:{ *:[v2f64] }:$Rm)
     /* 328456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2f64),
     /* 328459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328469 */     GIR_RootConstrainSelectedInstOperands,
     /* 328470 */     // GIR_Coverage, 15009,
     /* 328470 */     GIR_EraseRootFromParent_Done,
     /* 328471 */   // Label 6588: @328471
     /* 328471 */   GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(328498), // Rule ID 1237 //
     /* 328476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328479 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328483 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328487 */     // (fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 328487 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
     /* 328492 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328496 */     GIR_RootConstrainSelectedInstOperands,
     /* 328497 */     // GIR_Coverage, 1237,
     /* 328497 */     GIR_Done,
     /* 328498 */   // Label 6589: @328498
     /* 328498 */   GIM_Reject,
     /* 328499 */ // Label 6586: @328499
     /* 328499 */ GIM_Reject,
     /* 328500 */ // Label 6564: @328500
     /* 328500 */ GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(328537), // Rule ID 1229 //
     /* 328505 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328508 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 328511 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 328514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328518 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328522 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328526 */   // (fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 328526 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
     /* 328531 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328535 */   GIR_RootConstrainSelectedInstOperands,
     /* 328536 */   // GIR_Coverage, 1229,
     /* 328536 */   GIR_Done,
     /* 328537 */ // Label 6590: @328537
     /* 328537 */ GIM_Reject,
     /* 328538 */ // Label 6565: @328538
     /* 328538 */ GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(328713),
     /* 328543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 328546 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 328549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328553 */   GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(328619), // Rule ID 7583 //
     /* 328558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /* 328566 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 328570 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 328574 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /* 328592 */     // MIs[2] Rn
     /* 328592 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328597 */     // MIs[2] Rm
     /* 328597 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328602 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328604 */     // (fadd:{ *:[v4f32] } (AArch64uzp1:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm), (AArch64uzp2:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm))  =>  (FADDPv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm)
     /* 328604 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 328607 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328609 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328613 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328617 */     GIR_RootConstrainSelectedInstOperands,
     /* 328618 */     // GIR_Coverage, 7583,
     /* 328618 */     GIR_EraseRootFromParent_Done,
     /* 328619 */   // Label 6592: @328619
     /* 328619 */   GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(328685), // Rule ID 15010 //
     /* 328624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /* 328632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 328636 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 328640 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328645 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328650 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328654 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /* 328658 */     // MIs[2] Rn
     /* 328658 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328663 */     // MIs[2] Rm
     /* 328663 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328668 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328670 */     // (fadd:{ *:[v4f32] } (AArch64uzp2:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm), (AArch64uzp1:{ *:[v4f32] } FPR128:{ *:[v4f32] }:$Rn, FPR128:{ *:[v4f32] }:$Rm))  =>  (FADDPv4f32:{ *:[v4f32] } ?:{ *:[v4f32] }:$Rn, ?:{ *:[v4f32] }:$Rm)
     /* 328670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 328673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328683 */     GIR_RootConstrainSelectedInstOperands,
     /* 328684 */     // GIR_Coverage, 15010,
     /* 328684 */     GIR_EraseRootFromParent_Done,
     /* 328685 */   // Label 6593: @328685
     /* 328685 */   GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(328712), // Rule ID 1235 //
     /* 328690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 328693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328697 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328701 */     // (fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 328701 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 328706 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328710 */     GIR_RootConstrainSelectedInstOperands,
     /* 328711 */     // GIR_Coverage, 1235,
     /* 328711 */     GIR_Done,
     /* 328712 */   // Label 6594: @328712
     /* 328712 */   GIM_Reject,
     /* 328713 */ // Label 6591: @328713
     /* 328713 */ GIM_Reject,
     /* 328714 */ // Label 6566: @328714
     /* 328714 */ GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(329157),
     /* 328719 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328722 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 328725 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328729 */   GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(328798), // Rule ID 7584 //
     /* 328734 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 328737 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328741 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP1),
     /* 328745 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328749 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 328753 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328758 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328763 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328767 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP2),
     /* 328771 */     // MIs[2] Rn
     /* 328771 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328776 */     // MIs[2] Rm
     /* 328776 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328781 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328783 */     // (fadd:{ *:[v8f16] } (AArch64uzp1:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm), (AArch64uzp2:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm))  =>  (FADDPv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm)
     /* 328783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 328786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328788 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328796 */     GIR_RootConstrainSelectedInstOperands,
     /* 328797 */     // GIR_Coverage, 7584,
     /* 328797 */     GIR_EraseRootFromParent_Done,
     /* 328798 */   // Label 6596: @328798
     /* 328798 */   GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(328867), // Rule ID 15011 //
     /* 328803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 328806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 328810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UZP2),
     /* 328814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 328818 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 328822 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328827 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 328836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_UZP1),
     /* 328840 */     // MIs[2] Rn
     /* 328840 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 328845 */     // MIs[2] Rm
     /* 328845 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
     /* 328850 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 328852 */     // (fadd:{ *:[v8f16] } (AArch64uzp2:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm), (AArch64uzp1:{ *:[v8f16] } FPR128:{ *:[v8f16] }:$Rn, FPR128:{ *:[v8f16] }:$Rm))  =>  (FADDPv8f16:{ *:[v8f16] } ?:{ *:[v8f16] }:$Rn, ?:{ *:[v8f16] }:$Rm)
     /* 328852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 328855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 328857 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 328861 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 328865 */     GIR_RootConstrainSelectedInstOperands,
     /* 328866 */     // GIR_Coverage, 15011,
     /* 328866 */     GIR_EraseRootFromParent_Done,
     /* 328867 */   // Label 6597: @328867
     /* 328867 */   GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(328894), // Rule ID 1231 //
     /* 328872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 328875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328883 */     // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 328883 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
     /* 328888 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 328892 */     GIR_RootConstrainSelectedInstOperands,
     /* 328893 */     // GIR_Coverage, 1231,
     /* 328893 */     GIR_Done,
     /* 328894 */   // Label 6598: @328894
     /* 328894 */   GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(329156), // Rule ID 7660 //
     /* 328899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 328902 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328906 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328910 */     // (fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 328910 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 328913 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 328917 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328922 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 328926 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 328928 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 328931 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 328935 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328940 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 328944 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 328946 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 328949 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 328953 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328958 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 328961 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 328964 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 328966 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 328969 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 328973 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 328978 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 328984 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 328989 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 328994 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 328997 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 329001 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329006 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 329009 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 329011 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 329014 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329018 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329023 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 329029 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329034 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329039 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 329042 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 329046 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329051 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 329054 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 329056 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 329059 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 329063 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329068 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 329071 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 329074 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 329076 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 329079 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 329083 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329088 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 329091 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 329093 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 329096 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 329100 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329105 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 329107 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 329110 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 329114 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329119 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 329122 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 329125 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 329128 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329138 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 329146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 329148 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329151 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 329154 */     GIR_RootConstrainSelectedInstOperands,
     /* 329155 */     // GIR_Coverage, 7660,
     /* 329155 */     GIR_EraseRootFromParent_Done,
     /* 329156 */   // Label 6599: @329156
     /* 329156 */   GIM_Reject,
     /* 329157 */ // Label 6595: @329157
     /* 329157 */ GIM_Reject,
     /* 329158 */ // Label 6567: @329158
     /* 329158 */ GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(329183), // Rule ID 2869 //
     /* 329163 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329166 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 329169 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 329172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329176 */   // (fadd:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FADD_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 329176 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_D),
     /* 329181 */   GIR_RootConstrainSelectedInstOperands,
     /* 329182 */   // GIR_Coverage, 2869,
     /* 329182 */   GIR_Done,
     /* 329183 */ // Label 6600: @329183
     /* 329183 */ GIM_Reject,
     /* 329184 */ // Label 6568: @329184
     /* 329184 */ GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(329209), // Rule ID 2867 //
     /* 329189 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329192 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 329195 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 329198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329202 */   // (fadd:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FADD_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 329202 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_S),
     /* 329207 */   GIR_RootConstrainSelectedInstOperands,
     /* 329208 */   // GIR_Coverage, 2867,
     /* 329208 */   GIR_Done,
     /* 329209 */ // Label 6601: @329209
     /* 329209 */ GIM_Reject,
     /* 329210 */ // Label 6569: @329210
     /* 329210 */ GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(329235), // Rule ID 2865 //
     /* 329215 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329218 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 329221 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 329224 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329228 */   // (fadd:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FADD_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 329228 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADD_ZZZ_H),
     /* 329233 */   GIR_RootConstrainSelectedInstOperands,
     /* 329234 */   // GIR_Coverage, 2865,
     /* 329234 */   GIR_Done,
     /* 329235 */ // Label 6602: @329235
     /* 329235 */ GIM_Reject,
     /* 329236 */ // Label 6570: @329236
     /* 329236 */ GIM_Reject,
     /* 329237 */ // Label 69: @329237
     /* 329237 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6614*/ GIMT_Encode4(329974),
     /* 329248 */ /*GILLT_s16*//*Label 6603*/ GIMT_Encode4(329332),
     /* 329252 */ /*GILLT_s32*//*Label 6604*/ GIMT_Encode4(329370),
     /* 329256 */ /*GILLT_s64*//*Label 6605*/ GIMT_Encode4(329408), GIMT_Encode4(0),
     /* 329264 */ /*GILLT_v2s32*//*Label 6606*/ GIMT_Encode4(329446),
     /* 329268 */ /*GILLT_v2s64*//*Label 6607*/ GIMT_Encode4(329484),
     /* 329272 */ /*GILLT_v4s16*//*Label 6608*/ GIMT_Encode4(329522),
     /* 329276 */ /*GILLT_v4s32*//*Label 6609*/ GIMT_Encode4(329560), GIMT_Encode4(0),
     /* 329284 */ /*GILLT_v8s16*//*Label 6610*/ GIMT_Encode4(329598), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 329308 */ /*GILLT_nxv2s64*//*Label 6611*/ GIMT_Encode4(329896), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 329320 */ /*GILLT_nxv4s32*//*Label 6612*/ GIMT_Encode4(329922), GIMT_Encode4(0),
     /* 329328 */ /*GILLT_nxv8s16*//*Label 6613*/ GIMT_Encode4(329948),
     /* 329332 */ // Label 6603: @329332
     /* 329332 */ GIM_Try, /*On fail goto*//*Label 6615*/ GIMT_Encode4(329369), // Rule ID 674 //
     /* 329337 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 329340 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 329343 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 329346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329350 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329354 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 329358 */   // (fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 329358 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
     /* 329363 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329367 */   GIR_RootConstrainSelectedInstOperands,
     /* 329368 */   // GIR_Coverage, 674,
     /* 329368 */   GIR_Done,
     /* 329369 */ // Label 6615: @329369
     /* 329369 */ GIM_Reject,
     /* 329370 */ // Label 6604: @329370
     /* 329370 */ GIM_Try, /*On fail goto*//*Label 6616*/ GIMT_Encode4(329407), // Rule ID 676 //
     /* 329375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 329378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 329381 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 329384 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 329388 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 329392 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 329396 */   // (fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 329396 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
     /* 329401 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329405 */   GIR_RootConstrainSelectedInstOperands,
     /* 329406 */   // GIR_Coverage, 676,
     /* 329406 */   GIR_Done,
     /* 329407 */ // Label 6616: @329407
     /* 329407 */ GIM_Reject,
     /* 329408 */ // Label 6605: @329408
     /* 329408 */ GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(329445), // Rule ID 678 //
     /* 329413 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 329416 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 329419 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 329422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329426 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329430 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329434 */   // (fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 329434 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
     /* 329439 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329443 */   GIR_RootConstrainSelectedInstOperands,
     /* 329444 */   // GIR_Coverage, 678,
     /* 329444 */   GIR_Done,
     /* 329445 */ // Label 6617: @329445
     /* 329445 */ GIM_Reject,
     /* 329446 */ // Label 6606: @329446
     /* 329446 */ GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(329483), // Rule ID 1373 //
     /* 329451 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 329454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 329457 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 329460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329464 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329468 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329472 */   // (fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 329472 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
     /* 329477 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329481 */   GIR_RootConstrainSelectedInstOperands,
     /* 329482 */   // GIR_Coverage, 1373,
     /* 329482 */   GIR_Done,
     /* 329483 */ // Label 6618: @329483
     /* 329483 */ GIM_Reject,
     /* 329484 */ // Label 6607: @329484
     /* 329484 */ GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(329521), // Rule ID 1377 //
     /* 329489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 329492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 329495 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 329498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329502 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329506 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329510 */   // (fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 329510 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
     /* 329515 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329519 */   GIR_RootConstrainSelectedInstOperands,
     /* 329520 */   // GIR_Coverage, 1377,
     /* 329520 */   GIR_Done,
     /* 329521 */ // Label 6619: @329521
     /* 329521 */ GIM_Reject,
     /* 329522 */ // Label 6608: @329522
     /* 329522 */ GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(329559), // Rule ID 1369 //
     /* 329527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 329530 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 329533 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 329536 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329540 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329544 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329548 */   // (fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 329548 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
     /* 329553 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329557 */   GIR_RootConstrainSelectedInstOperands,
     /* 329558 */   // GIR_Coverage, 1369,
     /* 329558 */   GIR_Done,
     /* 329559 */ // Label 6620: @329559
     /* 329559 */ GIM_Reject,
     /* 329560 */ // Label 6609: @329560
     /* 329560 */ GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(329597), // Rule ID 1375 //
     /* 329565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 329568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 329571 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 329574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329578 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329582 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329586 */   // (fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 329586 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 329591 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329595 */   GIR_RootConstrainSelectedInstOperands,
     /* 329596 */   // GIR_Coverage, 1375,
     /* 329596 */   GIR_Done,
     /* 329597 */ // Label 6621: @329597
     /* 329597 */ GIM_Reject,
     /* 329598 */ // Label 6610: @329598
     /* 329598 */ GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(329895),
     /* 329603 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 329606 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 329609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329613 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329617 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329621 */   GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(329640), // Rule ID 1371 //
     /* 329626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 329629 */     // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 329629 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
     /* 329634 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 329638 */     GIR_RootConstrainSelectedInstOperands,
     /* 329639 */     // GIR_Coverage, 1371,
     /* 329639 */     GIR_Done,
     /* 329640 */   // Label 6623: @329640
     /* 329640 */   GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(329894), // Rule ID 7666 //
     /* 329645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 329648 */     // (fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 329648 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 329651 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 329655 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329660 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 329664 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 329666 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 329669 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 329673 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329678 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 329682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 329684 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 329687 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 329691 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329696 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 329699 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 329702 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 329704 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 329707 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329711 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329716 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 329722 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329727 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329732 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 329735 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 329739 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329744 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 329747 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 329749 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 329752 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 329756 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329761 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 329767 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329772 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329777 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 329780 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 329784 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329789 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 329792 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 329794 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 329797 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 329801 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329806 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 329809 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 329812 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 329814 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 329817 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 329821 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329826 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 329829 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 329831 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 329834 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 329838 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329843 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 329845 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 329848 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 329852 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 329857 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 329860 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 329863 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 329866 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329871 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 329876 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 329881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 329884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 329886 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 329889 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 329892 */     GIR_RootConstrainSelectedInstOperands,
     /* 329893 */     // GIR_Coverage, 7666,
     /* 329893 */     GIR_EraseRootFromParent_Done,
     /* 329894 */   // Label 6624: @329894
     /* 329894 */   GIM_Reject,
     /* 329895 */ // Label 6622: @329895
     /* 329895 */ GIM_Reject,
     /* 329896 */ // Label 6611: @329896
     /* 329896 */ GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(329921), // Rule ID 8871 //
     /* 329901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329904 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 329907 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 329910 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329914 */   // (fsub:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FSUB_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 329914 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_D),
     /* 329919 */   GIR_RootConstrainSelectedInstOperands,
     /* 329920 */   // GIR_Coverage, 8871,
     /* 329920 */   GIR_Done,
     /* 329921 */ // Label 6625: @329921
     /* 329921 */ GIM_Reject,
     /* 329922 */ // Label 6612: @329922
     /* 329922 */ GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(329947), // Rule ID 8869 //
     /* 329927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 329933 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 329936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329940 */   // (fsub:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FSUB_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 329940 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_S),
     /* 329945 */   GIR_RootConstrainSelectedInstOperands,
     /* 329946 */   // GIR_Coverage, 8869,
     /* 329946 */   GIR_Done,
     /* 329947 */ // Label 6626: @329947
     /* 329947 */ GIM_Reject,
     /* 329948 */ // Label 6613: @329948
     /* 329948 */ GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(329973), // Rule ID 8867 //
     /* 329953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 329956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 329959 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 329962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 329966 */   // (fsub:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FSUB_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 329966 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUB_ZZZ_H),
     /* 329971 */   GIR_RootConstrainSelectedInstOperands,
     /* 329972 */   // GIR_Coverage, 8867,
     /* 329972 */   GIR_Done,
     /* 329973 */ // Label 6627: @329973
     /* 329973 */ GIM_Reject,
     /* 329974 */ // Label 6614: @329974
     /* 329974 */ GIM_Reject,
     /* 329975 */ // Label 70: @329975
     /* 329975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(22), /*)*//*default:*//*Label 6639*/ GIMT_Encode4(334590),
     /* 329986 */ /*GILLT_s16*//*Label 6628*/ GIMT_Encode4(330070),
     /* 329990 */ /*GILLT_s32*//*Label 6629*/ GIMT_Encode4(330712),
     /* 329994 */ /*GILLT_s64*//*Label 6630*/ GIMT_Encode4(331342), GIMT_Encode4(0),
     /* 330002 */ /*GILLT_v2s32*//*Label 6631*/ GIMT_Encode4(331972),
     /* 330006 */ /*GILLT_v2s64*//*Label 6632*/ GIMT_Encode4(332502),
     /* 330010 */ /*GILLT_v4s16*//*Label 6633*/ GIMT_Encode4(332860),
     /* 330014 */ /*GILLT_v4s32*//*Label 6634*/ GIMT_Encode4(333202), GIMT_Encode4(0),
     /* 330022 */ /*GILLT_v8s16*//*Label 6635*/ GIMT_Encode4(333560), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 330046 */ /*GILLT_nxv2s64*//*Label 6636*/ GIMT_Encode4(333992), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 330058 */ /*GILLT_nxv4s32*//*Label 6637*/ GIMT_Encode4(334306), GIMT_Encode4(0),
     /* 330066 */ /*GILLT_nxv8s16*//*Label 6638*/ GIMT_Encode4(334448),
     /* 330070 */ // Label 6628: @330070
     /* 330070 */ GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(330711),
     /* 330075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 330078 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 330081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330085 */   GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(330198), // Rule ID 6875 //
     /* 330090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 330093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330109 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330114 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 330118 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 330122 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330126 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330130 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330134 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330139 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 330143 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330147 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 330151 */     // MIs[3] Operand 1
     /* 330151 */     // No operand predicates
     /* 330151 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330153 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 330153 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 330156 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330160 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330165 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 330171 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330176 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 330184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330186 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330189 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 330193 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 330196 */     GIR_RootConstrainSelectedInstOperands,
     /* 330197 */     // GIR_Coverage, 6875,
     /* 330197 */     GIR_EraseRootFromParent_Done,
     /* 330198 */   // Label 6641: @330198
     /* 330198 */   GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(330311), // Rule ID 14978 //
     /* 330203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 330206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330214 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330218 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330222 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330227 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330231 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330235 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 330239 */     // MIs[2] Operand 1
     /* 330239 */     // No operand predicates
     /* 330239 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 330243 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330247 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330251 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 330255 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330260 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 330264 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330266 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 330266 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 330269 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330273 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330278 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 330284 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330289 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 330297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330299 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330302 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 330306 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 330309 */     GIR_RootConstrainSelectedInstOperands,
     /* 330310 */     // GIR_Coverage, 14978,
     /* 330310 */     GIR_EraseRootFromParent_Done,
     /* 330311 */   // Label 6642: @330311
     /* 330311 */   GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(330390), // Rule ID 14867 //
     /* 330316 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330319 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330323 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330327 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330331 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330335 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330340 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 330344 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330348 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330350 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 330350 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 330353 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330357 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330362 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 330368 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330373 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 330381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 330385 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330388 */     GIR_RootConstrainSelectedInstOperands,
     /* 330389 */     // GIR_Coverage, 14867,
     /* 330389 */     GIR_EraseRootFromParent_Done,
     /* 330390 */   // Label 6643: @330390
     /* 330390 */   GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(330469), // Rule ID 4880 //
     /* 330395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330398 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330402 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 330406 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330410 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330414 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330418 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330423 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 330427 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330429 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 330429 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 330432 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330436 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330441 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 330447 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330452 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 330460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330462 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 330464 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330467 */     GIR_RootConstrainSelectedInstOperands,
     /* 330468 */     // GIR_Coverage, 4880,
     /* 330468 */     GIR_EraseRootFromParent_Done,
     /* 330469 */   // Label 6644: @330469
     /* 330469 */   GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(330532), // Rule ID 14502 //
     /* 330474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 330477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330485 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330489 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 330498 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330502 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330506 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 330510 */     // MIs[2] Operand 1
     /* 330510 */     // No operand predicates
     /* 330510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330514 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330516 */     // (fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 330516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 330519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 330523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 330527 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 330530 */     GIR_RootConstrainSelectedInstOperands,
     /* 330531 */     // GIR_Coverage, 14502,
     /* 330531 */     GIR_EraseRootFromParent_Done,
     /* 330532 */   // Label 6645: @330532
     /* 330532 */   GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(330595), // Rule ID 2043 //
     /* 330537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 330540 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 330548 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330552 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 330556 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330560 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 330565 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330569 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330573 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 330577 */     // MIs[2] Operand 1
     /* 330577 */     // No operand predicates
     /* 330577 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 330579 */     // (fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 330579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 330582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330584 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 330586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 330590 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 330593 */     GIR_RootConstrainSelectedInstOperands,
     /* 330594 */     // GIR_Coverage, 2043,
     /* 330594 */     GIR_EraseRootFromParent_Done,
     /* 330595 */   // Label 6646: @330595
     /* 330595 */   GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(330639), // Rule ID 4885 //
     /* 330600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 330611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 330615 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330624 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330626 */     // (fmul:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a), FPR16:{ *:[f16] }:$b)  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 330626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 330629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330631 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 330635 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 330637 */     GIR_RootConstrainSelectedInstOperands,
     /* 330638 */     // GIR_Coverage, 4885,
     /* 330638 */     GIR_EraseRootFromParent_Done,
     /* 330639 */   // Label 6647: @330639
     /* 330639 */   GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(330683), // Rule ID 14872 //
     /* 330644 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330647 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 330655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 330659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 330663 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330668 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330670 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$b, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$a))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 330670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 330673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 330679 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 330681 */     GIR_RootConstrainSelectedInstOperands,
     /* 330682 */     // GIR_Coverage, 14872,
     /* 330682 */     GIR_EraseRootFromParent_Done,
     /* 330683 */   // Label 6648: @330683
     /* 330683 */   GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(330710), // Rule ID 662 //
     /* 330688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 330691 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 330699 */     // (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 330699 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 330704 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 330708 */     GIR_RootConstrainSelectedInstOperands,
     /* 330709 */     // GIR_Coverage, 662,
     /* 330709 */     GIR_Done,
     /* 330710 */   // Label 6649: @330710
     /* 330710 */   GIM_Reject,
     /* 330711 */ // Label 6640: @330711
     /* 330711 */ GIM_Reject,
     /* 330712 */ // Label 6629: @330712
     /* 330712 */ GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(331341),
     /* 330717 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 330720 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 330723 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330727 */   GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(330840), // Rule ID 6877 //
     /* 330732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 330735 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330739 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330743 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330747 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330751 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330756 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 330760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 330764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330768 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330772 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 330776 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330781 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 330785 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330789 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 330793 */     // MIs[3] Operand 1
     /* 330793 */     // No operand predicates
     /* 330793 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330795 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 330795 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330798 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330802 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330807 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330813 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330818 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 330826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330828 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 330835 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 330838 */     GIR_RootConstrainSelectedInstOperands,
     /* 330839 */     // GIR_Coverage, 6877,
     /* 330839 */     GIR_EraseRootFromParent_Done,
     /* 330840 */   // Label 6651: @330840
     /* 330840 */   GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(330953), // Rule ID 14980 //
     /* 330845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 330848 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330852 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330856 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330860 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330864 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330869 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 330873 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 330877 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 330881 */     // MIs[2] Operand 1
     /* 330881 */     // No operand predicates
     /* 330881 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 330885 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330889 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330893 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 330897 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330902 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 330906 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 330908 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 330908 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330911 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330915 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 330920 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 330926 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330931 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 330939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 330941 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 330944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 330948 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 330951 */     GIR_RootConstrainSelectedInstOperands,
     /* 330952 */     // GIR_Coverage, 14980,
     /* 330952 */     GIR_EraseRootFromParent_Done,
     /* 330953 */   // Label 6652: @330953
     /* 330953 */   GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(331029), // Rule ID 14869 //
     /* 330958 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 330962 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 330966 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 330970 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 330974 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 330979 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 330983 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 330987 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 330989 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 330989 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 330992 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 330996 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331001 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 331007 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331012 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 331020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331022 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 331024 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331027 */     GIR_RootConstrainSelectedInstOperands,
     /* 331028 */     // GIR_Coverage, 14869,
     /* 331028 */     GIR_EraseRootFromParent_Done,
     /* 331029 */   // Label 6653: @331029
     /* 331029 */   GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(331105), // Rule ID 4882 //
     /* 331034 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331042 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331046 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 331050 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331054 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331059 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 331063 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331065 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 331065 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 331068 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331072 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331077 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 331083 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331088 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 331096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331098 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 331100 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331103 */     GIR_RootConstrainSelectedInstOperands,
     /* 331104 */     // GIR_Coverage, 4882,
     /* 331104 */     GIR_EraseRootFromParent_Done,
     /* 331105 */   // Label 6654: @331105
     /* 331105 */   GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(331168), // Rule ID 14504 //
     /* 331110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331121 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 331125 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331129 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331134 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331138 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331142 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 331146 */     // MIs[2] Operand 1
     /* 331146 */     // No operand predicates
     /* 331146 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331150 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331152 */     // (fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 331152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 331155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331157 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 331159 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 331163 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 331166 */     GIR_RootConstrainSelectedInstOperands,
     /* 331167 */     // GIR_Coverage, 14504,
     /* 331167 */     GIR_EraseRootFromParent_Done,
     /* 331168 */   // Label 6655: @331168
     /* 331168 */   GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(331231), // Rule ID 2045 //
     /* 331173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331176 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 331192 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331201 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331205 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331209 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 331213 */     // MIs[2] Operand 1
     /* 331213 */     // No operand predicates
     /* 331213 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331215 */     // (fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 331215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 331218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331220 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 331222 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 331226 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 331229 */     GIR_RootConstrainSelectedInstOperands,
     /* 331230 */     // GIR_Coverage, 2045,
     /* 331230 */     GIR_EraseRootFromParent_Done,
     /* 331231 */   // Label 6656: @331231
     /* 331231 */   GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(331272), // Rule ID 4886 //
     /* 331236 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331240 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 331244 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331248 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331257 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331259 */     // (fmul:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a), FPR32:{ *:[f32] }:$b)  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 331259 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 331262 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331264 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 331268 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 331270 */     GIR_RootConstrainSelectedInstOperands,
     /* 331271 */     // GIR_Coverage, 4886,
     /* 331271 */     GIR_EraseRootFromParent_Done,
     /* 331272 */   // Label 6657: @331272
     /* 331272 */   GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(331313), // Rule ID 14873 //
     /* 331277 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331281 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331285 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 331289 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 331293 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331298 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331300 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$b, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$a))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 331300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 331303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 331309 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 331311 */     GIR_RootConstrainSelectedInstOperands,
     /* 331312 */     // GIR_Coverage, 14873,
     /* 331312 */     GIR_EraseRootFromParent_Done,
     /* 331313 */   // Label 6658: @331313
     /* 331313 */   GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(331340), // Rule ID 664 //
     /* 331318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 331329 */     // (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 331329 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 331334 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 331338 */     GIR_RootConstrainSelectedInstOperands,
     /* 331339 */     // GIR_Coverage, 664,
     /* 331339 */     GIR_Done,
     /* 331340 */   // Label 6659: @331340
     /* 331340 */   GIM_Reject,
     /* 331341 */ // Label 6650: @331341
     /* 331341 */ GIM_Reject,
     /* 331342 */ // Label 6630: @331342
     /* 331342 */ GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(331971),
     /* 331347 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 331350 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 331353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331357 */   GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(331470), // Rule ID 6879 //
     /* 331362 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331369 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331373 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331377 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331381 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331386 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 331390 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 331394 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331398 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331402 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 331406 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331411 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 331415 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331419 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 331423 */     // MIs[3] Operand 1
     /* 331423 */     // No operand predicates
     /* 331423 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 331425 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 331425 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331428 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331432 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331437 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331448 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 331456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331458 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 331465 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 331468 */     GIR_RootConstrainSelectedInstOperands,
     /* 331469 */     // GIR_Coverage, 6879,
     /* 331469 */     GIR_EraseRootFromParent_Done,
     /* 331470 */   // Label 6661: @331470
     /* 331470 */   GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(331583), // Rule ID 14982 //
     /* 331475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331482 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331486 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331490 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331494 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331499 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331503 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331507 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 331511 */     // MIs[2] Operand 1
     /* 331511 */     // No operand predicates
     /* 331511 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 331515 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331519 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331523 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 331527 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331532 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 331536 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 331538 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 331538 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331541 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331545 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331550 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 331556 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331561 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 331569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331571 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 331578 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 331581 */     GIR_RootConstrainSelectedInstOperands,
     /* 331582 */     // GIR_Coverage, 14982,
     /* 331582 */     GIR_EraseRootFromParent_Done,
     /* 331583 */   // Label 6662: @331583
     /* 331583 */   GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(331659), // Rule ID 14871 //
     /* 331588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331604 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331609 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 331613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331617 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331619 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 331619 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331622 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331626 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331631 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 331637 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331642 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 331650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331652 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 331654 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331657 */     GIR_RootConstrainSelectedInstOperands,
     /* 331658 */     // GIR_Coverage, 14871,
     /* 331658 */     GIR_EraseRootFromParent_Done,
     /* 331659 */   // Label 6663: @331659
     /* 331659 */   GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(331735), // Rule ID 4884 //
     /* 331664 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331676 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331680 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331689 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 331693 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331695 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 331695 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 331698 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 331702 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 331707 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 331713 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331718 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 331726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331728 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 331730 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 331733 */     GIR_RootConstrainSelectedInstOperands,
     /* 331734 */     // GIR_Coverage, 4884,
     /* 331734 */     GIR_EraseRootFromParent_Done,
     /* 331735 */   // Label 6664: @331735
     /* 331735 */   GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(331798), // Rule ID 14506 //
     /* 331740 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331747 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331751 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331755 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331759 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331764 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331768 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331772 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 331776 */     // MIs[2] Operand 1
     /* 331776 */     // No operand predicates
     /* 331776 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331780 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331782 */     // (fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 331782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 331785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331787 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 331789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 331793 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 331796 */     GIR_RootConstrainSelectedInstOperands,
     /* 331797 */     // GIR_Coverage, 14506,
     /* 331797 */     GIR_EraseRootFromParent_Done,
     /* 331798 */   // Label 6665: @331798
     /* 331798 */   GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(331861), // Rule ID 2047 //
     /* 331803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331806 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 331818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 331822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 331826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 331831 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 331835 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 331839 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 331843 */     // MIs[2] Operand 1
     /* 331843 */     // No operand predicates
     /* 331843 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 331845 */     // (fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 331845 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 331848 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331850 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 331852 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 331856 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 331859 */     GIR_RootConstrainSelectedInstOperands,
     /* 331860 */     // GIR_Coverage, 2047,
     /* 331860 */     GIR_EraseRootFromParent_Done,
     /* 331861 */   // Label 6666: @331861
     /* 331861 */   GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(331902), // Rule ID 4887 //
     /* 331866 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331870 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 331874 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331878 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331883 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331887 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331889 */     // (fmul:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a), FPR64:{ *:[f64] }:$b)  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 331889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 331892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331894 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 331898 */     GIR_RootToRootCopy, /*OpIdx*/2, // b
     /* 331900 */     GIR_RootConstrainSelectedInstOperands,
     /* 331901 */     // GIR_Coverage, 4887,
     /* 331901 */     GIR_EraseRootFromParent_Done,
     /* 331902 */   // Label 6667: @331902
     /* 331902 */   GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(331943), // Rule ID 14874 //
     /* 331907 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 331915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 331919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 331923 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331928 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 331930 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$b, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$a))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 331930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 331933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 331935 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
     /* 331939 */     GIR_RootToRootCopy, /*OpIdx*/1, // b
     /* 331941 */     GIR_RootConstrainSelectedInstOperands,
     /* 331942 */     // GIR_Coverage, 14874,
     /* 331942 */     GIR_EraseRootFromParent_Done,
     /* 331943 */   // Label 6668: @331943
     /* 331943 */   GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(331970), // Rule ID 666 //
     /* 331948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 331951 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331959 */     // (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 331959 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 331964 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 331968 */     GIR_RootConstrainSelectedInstOperands,
     /* 331969 */     // GIR_Coverage, 666,
     /* 331969 */     GIR_Done,
     /* 331970 */   // Label 6669: @331970
     /* 331970 */   GIM_Reject,
     /* 331971 */ // Label 6660: @331971
     /* 331971 */ GIM_Reject,
     /* 331972 */ // Label 6631: @331972
     /* 331972 */ GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(332501),
     /* 331977 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 331980 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 331983 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 331987 */   GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(332073), // Rule ID 14495 //
     /* 331992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 331995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 331999 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 332003 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 332011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 332015 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332019 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 332023 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332028 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 332032 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332036 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 332040 */     // MIs[3] Operand 1
     /* 332040 */     // No operand predicates
     /* 332040 */     // MIs[1] Operand 2
     /* 332040 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 332051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332055 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 332057 */     // (fmul:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332062 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332064 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 332068 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 332071 */     GIR_RootConstrainSelectedInstOperands,
     /* 332072 */     // GIR_Coverage, 14495,
     /* 332072 */     GIR_EraseRootFromParent_Done,
     /* 332073 */   // Label 6671: @332073
     /* 332073 */   GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(332159), // Rule ID 2036 //
     /* 332078 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332081 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 332093 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332097 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 332101 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 332105 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332109 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 332113 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332118 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 332122 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332126 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 332130 */     // MIs[3] Operand 1
     /* 332130 */     // No operand predicates
     /* 332130 */     // MIs[1] Operand 2
     /* 332130 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 332141 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 332143 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332148 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 332154 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 332157 */     GIR_RootConstrainSelectedInstOperands,
     /* 332158 */     // GIR_Coverage, 2036,
     /* 332158 */     GIR_EraseRootFromParent_Done,
     /* 332159 */   // Label 6672: @332159
     /* 332159 */   GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(332222), // Rule ID 14496 //
     /* 332164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 332175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332179 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332183 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332188 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 332192 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332196 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 332200 */     // MIs[2] Operand 1
     /* 332200 */     // No operand predicates
     /* 332200 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332204 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 332206 */     // (fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332211 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332213 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332217 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 332220 */     GIR_RootConstrainSelectedInstOperands,
     /* 332221 */     // GIR_Coverage, 14496,
     /* 332221 */     GIR_EraseRootFromParent_Done,
     /* 332222 */   // Label 6673: @332222
     /* 332222 */   GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(332285), // Rule ID 2037 //
     /* 332227 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332230 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 332242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 332246 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332250 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332255 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 332259 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332263 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 332267 */     // MIs[2] Operand 1
     /* 332267 */     // No operand predicates
     /* 332267 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 332269 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332269 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332272 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332274 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332280 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 332283 */     GIR_RootConstrainSelectedInstOperands,
     /* 332284 */     // GIR_Coverage, 2037,
     /* 332284 */     GIR_EraseRootFromParent_Done,
     /* 332285 */   // Label 6674: @332285
     /* 332285 */   GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(332379), // Rule ID 14984 //
     /* 332290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 332298 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 332302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332307 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332311 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332313 */     // (fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 332313 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 332316 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 332320 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332325 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 332327 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 332330 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 332334 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332339 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 332342 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332346 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 332349 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332354 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332359 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332369 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332371 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332374 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 332377 */     GIR_RootConstrainSelectedInstOperands,
     /* 332378 */     // GIR_Coverage, 14984,
     /* 332378 */     GIR_EraseRootFromParent_Done,
     /* 332379 */   // Label 6675: @332379
     /* 332379 */   GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(332473), // Rule ID 6881 //
     /* 332384 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 332396 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 332400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332405 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332407 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 332407 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 332410 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 332414 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332419 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 332421 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 332424 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 332428 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332433 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 332436 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332440 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 332443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332448 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332453 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 332458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 332461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332463 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332465 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 332471 */     GIR_RootConstrainSelectedInstOperands,
     /* 332472 */     // GIR_Coverage, 6881,
     /* 332472 */     GIR_EraseRootFromParent_Done,
     /* 332473 */   // Label 6676: @332473
     /* 332473 */   GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(332500), // Rule ID 1353 //
     /* 332478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332481 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332485 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332489 */     // (fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 332489 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
     /* 332494 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332498 */     GIR_RootConstrainSelectedInstOperands,
     /* 332499 */     // GIR_Coverage, 1353,
     /* 332499 */     GIR_Done,
     /* 332500 */   // Label 6677: @332500
     /* 332500 */   GIM_Reject,
     /* 332501 */ // Label 6670: @332501
     /* 332501 */ GIM_Reject,
     /* 332502 */ // Label 6632: @332502
     /* 332502 */ GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(332859),
     /* 332507 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 332510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 332513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332517 */   GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(332580), // Rule ID 14500 //
     /* 332522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332525 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332529 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 332533 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 332537 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332541 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 332550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332554 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 332558 */     // MIs[2] Operand 1
     /* 332558 */     // No operand predicates
     /* 332558 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332562 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 332564 */     // (fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332564 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 332567 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332569 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332575 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 332578 */     GIR_RootConstrainSelectedInstOperands,
     /* 332579 */     // GIR_Coverage, 14500,
     /* 332579 */     GIR_EraseRootFromParent_Done,
     /* 332580 */   // Label 6679: @332580
     /* 332580 */   GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(332643), // Rule ID 2041 //
     /* 332585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332588 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 332600 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 332604 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 332608 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332613 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 332617 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332621 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 332625 */     // MIs[2] Operand 1
     /* 332625 */     // No operand predicates
     /* 332625 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 332627 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 332630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332632 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332638 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 332641 */     GIR_RootConstrainSelectedInstOperands,
     /* 332642 */     // GIR_Coverage, 2041,
     /* 332642 */     GIR_EraseRootFromParent_Done,
     /* 332643 */   // Label 6680: @332643
     /* 332643 */   GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(332737), // Rule ID 14988 //
     /* 332648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 332656 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332660 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332665 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332669 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332671 */     // (fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 332671 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 332674 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 332678 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332683 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 332685 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 332688 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 332692 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332697 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 332700 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332704 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 332707 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332712 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332717 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 332725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332727 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332729 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 332735 */     GIR_RootConstrainSelectedInstOperands,
     /* 332736 */     // GIR_Coverage, 14988,
     /* 332736 */     GIR_EraseRootFromParent_Done,
     /* 332737 */   // Label 6681: @332737
     /* 332737 */   GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(332831), // Rule ID 6885 //
     /* 332742 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332746 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332750 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 332754 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 332758 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332763 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 332765 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 332765 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 332768 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 332772 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332777 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 332779 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 332782 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 332786 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 332791 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 332794 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 332798 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 332801 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332806 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332811 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 332819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332821 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 332823 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 332826 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 332829 */     GIR_RootConstrainSelectedInstOperands,
     /* 332830 */     // GIR_Coverage, 6885,
     /* 332830 */     GIR_EraseRootFromParent_Done,
     /* 332831 */   // Label 6682: @332831
     /* 332831 */   GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(332858), // Rule ID 1357 //
     /* 332836 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 332839 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 332847 */     // (fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 332847 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
     /* 332852 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 332856 */     GIR_RootConstrainSelectedInstOperands,
     /* 332857 */     // GIR_Coverage, 1357,
     /* 332857 */     GIR_Done,
     /* 332858 */   // Label 6683: @332858
     /* 332858 */   GIM_Reject,
     /* 332859 */ // Label 6678: @332859
     /* 332859 */ GIM_Reject,
     /* 332860 */ // Label 6633: @332860
     /* 332860 */ GIM_Try, /*On fail goto*//*Label 6684*/ GIMT_Encode4(333201),
     /* 332865 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 332868 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 332871 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332875 */   GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(332961), // Rule ID 14489 //
     /* 332880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 332883 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 332887 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 332891 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 332895 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 332899 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 332903 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 332907 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 332911 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 332916 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 332920 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 332924 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 332928 */     // MIs[3] Operand 1
     /* 332928 */     // No operand predicates
     /* 332928 */     // MIs[1] Operand 2
     /* 332928 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 332939 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332943 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 332945 */     // (fmul:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 332945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 332948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 332950 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 332952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 332956 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 332959 */     GIR_RootConstrainSelectedInstOperands,
     /* 332960 */     // GIR_Coverage, 14489,
     /* 332960 */     GIR_EraseRootFromParent_Done,
     /* 332961 */   // Label 6685: @332961
     /* 332961 */   GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(333047), // Rule ID 2030 //
     /* 332966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 332969 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 332973 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 332977 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 332981 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 332985 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 332989 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 332993 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 332997 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 333001 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 333006 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 333010 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333014 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 333018 */     // MIs[3] Operand 1
     /* 333018 */     // No operand predicates
     /* 333018 */     // MIs[1] Operand 2
     /* 333018 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 333029 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 333031 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 333034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333036 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 333038 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 333042 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 333045 */     GIR_RootConstrainSelectedInstOperands,
     /* 333046 */     // GIR_Coverage, 2030,
     /* 333046 */     GIR_EraseRootFromParent_Done,
     /* 333047 */   // Label 6686: @333047
     /* 333047 */   GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(333110), // Rule ID 14490 //
     /* 333052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333055 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333059 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 333063 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333067 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333071 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 333076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333084 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 333088 */     // MIs[2] Operand 1
     /* 333088 */     // No operand predicates
     /* 333088 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333092 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333094 */     // (fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 333097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333099 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 333101 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333105 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333108 */     GIR_RootConstrainSelectedInstOperands,
     /* 333109 */     // GIR_Coverage, 14490,
     /* 333109 */     GIR_EraseRootFromParent_Done,
     /* 333110 */   // Label 6687: @333110
     /* 333110 */   GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(333173), // Rule ID 2031 //
     /* 333115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333118 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 333126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 333130 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333134 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333138 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 333143 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333147 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333151 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 333155 */     // MIs[2] Operand 1
     /* 333155 */     // No operand predicates
     /* 333155 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333157 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 333160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333162 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 333164 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333168 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333171 */     GIR_RootConstrainSelectedInstOperands,
     /* 333172 */     // GIR_Coverage, 2031,
     /* 333172 */     GIR_EraseRootFromParent_Done,
     /* 333173 */   // Label 6688: @333173
     /* 333173 */   GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(333200), // Rule ID 1349 //
     /* 333178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333189 */     // (fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 333189 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
     /* 333194 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333198 */     GIR_RootConstrainSelectedInstOperands,
     /* 333199 */     // GIR_Coverage, 1349,
     /* 333199 */     GIR_Done,
     /* 333200 */   // Label 6689: @333200
     /* 333200 */   GIM_Reject,
     /* 333201 */ // Label 6684: @333201
     /* 333201 */ GIM_Reject,
     /* 333202 */ // Label 6634: @333202
     /* 333202 */ GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(333559),
     /* 333207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 333210 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 333213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333217 */   GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(333280), // Rule ID 14498 //
     /* 333222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333225 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333229 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 333233 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 333237 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333241 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333246 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333250 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333254 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 333258 */     // MIs[2] Operand 1
     /* 333258 */     // No operand predicates
     /* 333258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333262 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333264 */     // (fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 333267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333269 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 333271 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333275 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333278 */     GIR_RootConstrainSelectedInstOperands,
     /* 333279 */     // GIR_Coverage, 14498,
     /* 333279 */     GIR_EraseRootFromParent_Done,
     /* 333280 */   // Label 6691: @333280
     /* 333280 */   GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(333343), // Rule ID 2039 //
     /* 333285 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333288 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333292 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 333296 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 333300 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 333304 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333308 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333313 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333317 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333321 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 333325 */     // MIs[2] Operand 1
     /* 333325 */     // No operand predicates
     /* 333325 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333327 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 333330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333332 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 333334 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333338 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333341 */     GIR_RootConstrainSelectedInstOperands,
     /* 333342 */     // GIR_Coverage, 2039,
     /* 333342 */     GIR_EraseRootFromParent_Done,
     /* 333343 */   // Label 6692: @333343
     /* 333343 */   GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(333437), // Rule ID 14986 //
     /* 333348 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333352 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 333356 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333360 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333365 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333369 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333371 */     // (fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 333371 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 333374 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 333378 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333383 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 333385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 333388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 333392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333397 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 333400 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333404 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 333407 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333412 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333417 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 333425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333427 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 333429 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 333432 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 333435 */     GIR_RootConstrainSelectedInstOperands,
     /* 333436 */     // GIR_Coverage, 14986,
     /* 333436 */     GIR_EraseRootFromParent_Done,
     /* 333437 */   // Label 6693: @333437
     /* 333437 */   GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(333531), // Rule ID 6883 //
     /* 333442 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 333450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 333454 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 333458 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333463 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 333465 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 333465 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 333468 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 333472 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333477 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 333479 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 333482 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 333486 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333491 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 333494 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333498 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 333501 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333506 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333511 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 333516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 333519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333521 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 333523 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 333526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 333529 */     GIR_RootConstrainSelectedInstOperands,
     /* 333530 */     // GIR_Coverage, 6883,
     /* 333530 */     GIR_EraseRootFromParent_Done,
     /* 333531 */   // Label 6694: @333531
     /* 333531 */   GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(333558), // Rule ID 1355 //
     /* 333536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 333539 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333547 */     // (fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 333547 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 333552 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333556 */     GIR_RootConstrainSelectedInstOperands,
     /* 333557 */     // GIR_Coverage, 1355,
     /* 333557 */     GIR_Done,
     /* 333558 */   // Label 6695: @333558
     /* 333558 */   GIM_Reject,
     /* 333559 */ // Label 6690: @333559
     /* 333559 */ GIM_Reject,
     /* 333560 */ // Label 6635: @333560
     /* 333560 */ GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(333991),
     /* 333565 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333568 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 333571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333575 */   GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(333638), // Rule ID 14492 //
     /* 333580 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 333587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 333591 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333595 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333599 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 333604 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333608 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333612 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 333616 */     // MIs[2] Operand 1
     /* 333616 */     // No operand predicates
     /* 333616 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333620 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333622 */     // (fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 333625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333627 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 333629 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333633 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333636 */     GIR_RootConstrainSelectedInstOperands,
     /* 333637 */     // GIR_Coverage, 14492,
     /* 333637 */     GIR_EraseRootFromParent_Done,
     /* 333638 */   // Label 6697: @333638
     /* 333638 */   GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(333701), // Rule ID 2033 //
     /* 333643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333646 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 333654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 333658 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 333662 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 333666 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 333671 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 333675 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 333679 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 333683 */     // MIs[2] Operand 1
     /* 333683 */     // No operand predicates
     /* 333683 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 333685 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 333685 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 333688 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 333690 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 333692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 333696 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 333699 */     GIR_RootConstrainSelectedInstOperands,
     /* 333700 */     // GIR_Coverage, 2033,
     /* 333700 */     GIR_EraseRootFromParent_Done,
     /* 333701 */   // Label 6698: @333701
     /* 333701 */   GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(333728), // Rule ID 1351 //
     /* 333706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 333709 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333717 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 333717 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
     /* 333722 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 333726 */     GIR_RootConstrainSelectedInstOperands,
     /* 333727 */     // GIR_Coverage, 1351,
     /* 333727 */     GIR_Done,
     /* 333728 */   // Label 6699: @333728
     /* 333728 */   GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(333990), // Rule ID 7664 //
     /* 333733 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 333736 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333740 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333744 */     // (fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 333744 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 333747 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 333751 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333756 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 333760 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 333762 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 333765 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 333769 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333774 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 333778 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 333780 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 333783 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 333787 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333792 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 333795 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 333798 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 333800 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 333803 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 333807 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333812 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 333818 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333823 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333828 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 333831 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 333835 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333840 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 333843 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 333845 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 333848 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 333852 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333857 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 333863 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333868 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333873 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 333876 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 333880 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333885 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 333888 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 333890 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 333893 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 333897 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333902 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 333905 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 333908 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 333910 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 333913 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 333917 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333922 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 333925 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 333927 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 333930 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 333934 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333939 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 333941 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 333944 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 333948 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 333953 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 333956 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 333959 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 333962 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333967 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 333972 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 333977 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 333980 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 333982 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 333985 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 333988 */     GIR_RootConstrainSelectedInstOperands,
     /* 333989 */     // GIR_Coverage, 7664,
     /* 333989 */     GIR_EraseRootFromParent_Done,
     /* 333990 */   // Label 6700: @333990
     /* 333990 */   GIM_Reject,
     /* 333991 */ // Label 6696: @333991
     /* 333991 */ GIM_Reject,
     /* 333992 */ // Label 6636: @333992
     /* 333992 */ GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(334305),
     /* 333997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 334000 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 334003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 334007 */   GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(334062), // Rule ID 14725 //
     /* 334012 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334015 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334019 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334023 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334026 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334031 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 334035 */     // MIs[1] idx
     /* 334035 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334038 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 334043 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334045 */     // (fmul:{ *:[nxv2f64] } (intrinsic_wo_chain:{ *:[nxv2f64] } 1376:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx), nxv2f64:{ *:[nxv2f64] }:$Op1)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 334045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334050 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 334052 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334056 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334060 */     GIR_RootConstrainSelectedInstOperands,
     /* 334061 */     // GIR_Coverage, 14725,
     /* 334061 */     GIR_EraseRootFromParent_Done,
     /* 334062 */   // Label 6702: @334062
     /* 334062 */   GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(334117), // Rule ID 2912 //
     /* 334067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334070 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 334074 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334078 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334081 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334086 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 334090 */     // MIs[1] idx
     /* 334090 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334093 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD32b_timm),
     /* 334098 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334100 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, (intrinsic_wo_chain:{ *:[nxv2f64] } 1376:{ *:[iPTR] }, nxv2f64:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexD32b_timm>>:$idx)
     /* 334100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334105 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 334107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334111 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334115 */     GIR_RootConstrainSelectedInstOperands,
     /* 334116 */     // GIR_Coverage, 2912,
     /* 334116 */     GIR_EraseRootFromParent_Done,
     /* 334117 */   // Label 6703: @334117
     /* 334117 */   GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(334160), // Rule ID 16110 //
     /* 334122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334125 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334129 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN1),
     /* 334133 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 334137 */     // MIs[1] R
     /* 334137 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 334142 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334144 */     // (fmul:{ *:[nxv2f64] } (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R), nxv2f64:{ *:[nxv2f64] }:$L)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 0:{ *:[i32] })
     /* 334144 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334147 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334149 */     GIR_RootToRootCopy, /*OpIdx*/2, // L
     /* 334151 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 334155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 334158 */     GIR_RootConstrainSelectedInstOperands,
     /* 334159 */     // GIR_Coverage, 16110,
     /* 334159 */     GIR_EraseRootFromParent_Done,
     /* 334160 */   // Label 6704: @334160
     /* 334160 */   GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(334203), // Rule ID 16111 //
     /* 334165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN2),
     /* 334176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 334180 */     // MIs[1] R
     /* 334180 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 334185 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334187 */     // (fmul:{ *:[nxv2f64] } (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R), nxv2f64:{ *:[nxv2f64] }:$L)  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 1:{ *:[i32] })
     /* 334187 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334190 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334192 */     GIR_RootToRootCopy, /*OpIdx*/2, // L
     /* 334194 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 334198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 334201 */     GIR_RootConstrainSelectedInstOperands,
     /* 334202 */     // GIR_Coverage, 16111,
     /* 334202 */     GIR_EraseRootFromParent_Done,
     /* 334203 */   // Label 6705: @334203
     /* 334203 */   GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(334246), // Rule ID 8990 //
     /* 334208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 334215 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN1),
     /* 334219 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 334223 */     // MIs[1] R
     /* 334223 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 334228 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334230 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$L, (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 0:{ *:[i32] })
     /* 334230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334235 */     GIR_RootToRootCopy, /*OpIdx*/1, // L
     /* 334237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 334241 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 334244 */     GIR_RootConstrainSelectedInstOperands,
     /* 334245 */     // GIR_Coverage, 8990,
     /* 334245 */     GIR_EraseRootFromParent_Done,
     /* 334246 */   // Label 6706: @334246
     /* 334246 */   GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(334289), // Rule ID 8993 //
     /* 334251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334254 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 334258 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_TRN2),
     /* 334262 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 334266 */     // MIs[1] R
     /* 334266 */     GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 334271 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334273 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$L, (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$R, nxv2f64:{ *:[nxv2f64] }:$R))  =>  (FMUL_ZZZI_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$L, ?:{ *:[nxv2f64] }:$R, 1:{ *:[i32] })
     /* 334273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_D),
     /* 334276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334278 */     GIR_RootToRootCopy, /*OpIdx*/1, // L
     /* 334280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // R
     /* 334284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 334287 */     GIR_RootConstrainSelectedInstOperands,
     /* 334288 */     // GIR_Coverage, 8993,
     /* 334288 */     GIR_EraseRootFromParent_Done,
     /* 334289 */   // Label 6707: @334289
     /* 334289 */   GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(334304), // Rule ID 8879 //
     /* 334294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334297 */     // (fmul:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (FMUL_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 334297 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_D),
     /* 334302 */     GIR_RootConstrainSelectedInstOperands,
     /* 334303 */     // GIR_Coverage, 8879,
     /* 334303 */     GIR_Done,
     /* 334304 */   // Label 6708: @334304
     /* 334304 */   GIM_Reject,
     /* 334305 */ // Label 6701: @334305
     /* 334305 */ GIM_Reject,
     /* 334306 */ // Label 6637: @334306
     /* 334306 */ GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(334447),
     /* 334311 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 334314 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 334317 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 334321 */   GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(334376), // Rule ID 14724 //
     /* 334326 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334329 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334333 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334337 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334340 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334345 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 334349 */     // MIs[1] idx
     /* 334349 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334352 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 334357 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334359 */     // (fmul:{ *:[nxv4f32] } (intrinsic_wo_chain:{ *:[nxv4f32] } 1376:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx), nxv4f32:{ *:[nxv4f32] }:$Op1)  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 334359 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 334362 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334364 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 334366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334370 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334374 */     GIR_RootConstrainSelectedInstOperands,
     /* 334375 */     // GIR_Coverage, 14724,
     /* 334375 */     GIR_EraseRootFromParent_Done,
     /* 334376 */   // Label 6710: @334376
     /* 334376 */   GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(334431), // Rule ID 2908 //
     /* 334381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 334388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334392 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334395 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334400 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 334404 */     // MIs[1] idx
     /* 334404 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334407 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS32b_timm),
     /* 334412 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334414 */     // (fmul:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, (intrinsic_wo_chain:{ *:[nxv4f32] } 1376:{ *:[iPTR] }, nxv4f32:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx))  =>  (FMUL_ZZZI_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexS32b_timm>>:$idx)
     /* 334414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_S),
     /* 334417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334419 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 334421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334429 */     GIR_RootConstrainSelectedInstOperands,
     /* 334430 */     // GIR_Coverage, 2908,
     /* 334430 */     GIR_EraseRootFromParent_Done,
     /* 334431 */   // Label 6711: @334431
     /* 334431 */   GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(334446), // Rule ID 8876 //
     /* 334436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334439 */     // (fmul:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (FMUL_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 334439 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_S),
     /* 334444 */     GIR_RootConstrainSelectedInstOperands,
     /* 334445 */     // GIR_Coverage, 8876,
     /* 334445 */     GIR_Done,
     /* 334446 */   // Label 6712: @334446
     /* 334446 */   GIM_Reject,
     /* 334447 */ // Label 6709: @334447
     /* 334447 */ GIM_Reject,
     /* 334448 */ // Label 6638: @334448
     /* 334448 */ GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(334589),
     /* 334453 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 334456 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 334459 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 334463 */   GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(334518), // Rule ID 14723 //
     /* 334468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334471 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334475 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334479 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334482 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334487 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 334491 */     // MIs[1] idx
     /* 334491 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334494 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 334499 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334501 */     // (fmul:{ *:[nxv8f16] } (intrinsic_wo_chain:{ *:[nxv8f16] } 1376:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx), nxv8f16:{ *:[nxv8f16] }:$Op1)  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 334501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 334504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334506 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 334508 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334516 */     GIR_RootConstrainSelectedInstOperands,
     /* 334517 */     // GIR_Coverage, 14723,
     /* 334517 */     GIR_EraseRootFromParent_Done,
     /* 334518 */   // Label 6714: @334518
     /* 334518 */   GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(334573), // Rule ID 2904 //
     /* 334523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 334530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 334534 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
     /* 334537 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_sve_dup_laneq),
     /* 334542 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 334546 */     // MIs[1] idx
     /* 334546 */     GIM_CheckIsImm, /*MI*/1, /*Op*/3,
     /* 334549 */     GIM_CheckImmOperandPredicate, /*MI*/1, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH32b_timm),
     /* 334554 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 334556 */     // (fmul:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, (intrinsic_wo_chain:{ *:[nxv8f16] } 1376:{ *:[iPTR] }, nxv8f16:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx))  =>  (FMUL_ZZZI_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_VectorIndexH32b_timm>>:$idx)
     /* 334556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZI_H),
     /* 334559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 334561 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 334563 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Op2
     /* 334567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // idx
     /* 334571 */     GIR_RootConstrainSelectedInstOperands,
     /* 334572 */     // GIR_Coverage, 2904,
     /* 334572 */     GIR_EraseRootFromParent_Done,
     /* 334573 */   // Label 6715: @334573
     /* 334573 */   GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(334588), // Rule ID 8873 //
     /* 334578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 334581 */     // (fmul:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (FMUL_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 334581 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMUL_ZZZ_H),
     /* 334586 */     GIR_RootConstrainSelectedInstOperands,
     /* 334587 */     // GIR_Coverage, 8873,
     /* 334587 */     GIR_Done,
     /* 334588 */   // Label 6716: @334588
     /* 334588 */   GIM_Reject,
     /* 334589 */ // Label 6713: @334589
     /* 334589 */ GIM_Reject,
     /* 334590 */ // Label 6639: @334590
     /* 334590 */ GIM_Reject,
     /* 334591 */ // Label 71: @334591
     /* 334591 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6725*/ GIMT_Encode4(350863),
     /* 334602 */ /*GILLT_s16*//*Label 6717*/ GIMT_Encode4(334642),
     /* 334606 */ /*GILLT_s32*//*Label 6718*/ GIMT_Encode4(337646),
     /* 334610 */ /*GILLT_s64*//*Label 6719*/ GIMT_Encode4(340794), GIMT_Encode4(0),
     /* 334618 */ /*GILLT_v2s32*//*Label 6720*/ GIMT_Encode4(343942),
     /* 334622 */ /*GILLT_v2s64*//*Label 6721*/ GIMT_Encode4(345463),
     /* 334626 */ /*GILLT_v4s16*//*Label 6722*/ GIMT_Encode4(346984),
     /* 334630 */ /*GILLT_v4s32*//*Label 6723*/ GIMT_Encode4(348163), GIMT_Encode4(0),
     /* 334638 */ /*GILLT_v8s16*//*Label 6724*/ GIMT_Encode4(349684),
     /* 334642 */ // Label 6717: @334642
     /* 334642 */ GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(337645),
     /* 334647 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 334650 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 334653 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 334656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334660 */   GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(334810), // Rule ID 4942 //
     /* 334665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 334668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 334676 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334680 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 334684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334689 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 334693 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 334697 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 334701 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334705 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 334709 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334714 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 334718 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 334722 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 334726 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 334730 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334735 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 334737 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 334737 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 334740 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 334744 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 334749 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 334755 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334760 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 334768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 334772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 334777 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 334783 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 334796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334798 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 334801 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 334804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 334808 */     GIR_RootConstrainSelectedInstOperands,
     /* 334809 */     // GIR_Coverage, 4942,
     /* 334809 */     GIR_EraseRootFromParent_Done,
     /* 334810 */   // Label 6727: @334810
     /* 334810 */   GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(334957), // Rule ID 4906 //
     /* 334815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 334818 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334822 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 334826 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334830 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 334834 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334839 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 334843 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 334847 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 334851 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 334855 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 334859 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 334863 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334867 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 334871 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334876 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 334880 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334884 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 334886 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 334886 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 334889 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 334893 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 334898 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 334904 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334909 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 334917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 334921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 334926 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 334932 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 334937 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 334945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 334947 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 334950 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 334953 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 334955 */     GIR_RootConstrainSelectedInstOperands,
     /* 334956 */     // GIR_Coverage, 4906,
     /* 334956 */     GIR_EraseRootFromParent_Done,
     /* 334957 */   // Label 6728: @334957
     /* 334957 */   GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(335104), // Rule ID 14880 //
     /* 334962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 334965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 334969 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 334973 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 334977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 334981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 334985 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 334989 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 334993 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 334998 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 335002 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 335006 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335010 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335014 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 335018 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335023 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 335027 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335031 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 335033 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 335033 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 335036 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335040 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335045 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 335051 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335056 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335061 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335064 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335068 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335073 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335079 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335084 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 335092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335094 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335097 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 335100 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 335102 */     GIR_RootConstrainSelectedInstOperands,
     /* 335103 */     // GIR_Coverage, 14880,
     /* 335103 */     GIR_EraseRootFromParent_Done,
     /* 335104 */   // Label 6729: @335104
     /* 335104 */   GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(335235), // Rule ID 6713 //
     /* 335109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335112 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335116 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335120 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335124 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335128 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335133 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 335137 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 335141 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 335145 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 335149 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 335153 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335157 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335161 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 335165 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335170 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 335174 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335178 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335182 */     // MIs[4] Operand 1
     /* 335182 */     // No operand predicates
     /* 335182 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335186 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 335188 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335188 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335191 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335195 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335200 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335206 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335211 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 335219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335221 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335223 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335226 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 335230 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 335233 */     GIR_RootConstrainSelectedInstOperands,
     /* 335234 */     // GIR_Coverage, 6713,
     /* 335234 */     GIR_EraseRootFromParent_Done,
     /* 335235 */   // Label 6730: @335235
     /* 335235 */   GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(335366), // Rule ID 6745 //
     /* 335240 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335243 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335247 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335251 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335255 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335259 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335264 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 335268 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335272 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335276 */     // MIs[2] Operand 1
     /* 335276 */     // No operand predicates
     /* 335276 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 335280 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 335284 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 335288 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 335292 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335296 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335300 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 335304 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335309 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 335313 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335317 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 335319 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335319 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335322 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335326 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335331 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335342 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 335350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335352 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335354 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 335361 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 335364 */     GIR_RootConstrainSelectedInstOperands,
     /* 335365 */     // GIR_Coverage, 6745,
     /* 335365 */     GIR_EraseRootFromParent_Done,
     /* 335366 */   // Label 6731: @335366
     /* 335366 */   GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(335497), // Rule ID 6809 //
     /* 335371 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 335382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 335386 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 335390 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335394 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335398 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 335402 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335407 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 335411 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 335415 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335419 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335423 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 335427 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335432 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 335436 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335440 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335444 */     // MIs[4] Operand 1
     /* 335444 */     // No operand predicates
     /* 335444 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335448 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 335450 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335450 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335453 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335457 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335462 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335468 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335473 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 335481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335483 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335485 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 335492 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 335495 */     GIR_RootConstrainSelectedInstOperands,
     /* 335496 */     // GIR_Coverage, 6809,
     /* 335496 */     GIR_EraseRootFromParent_Done,
     /* 335497 */   // Label 6732: @335497
     /* 335497 */   GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(335628), // Rule ID 6777 //
     /* 335502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335505 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335509 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 335513 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 335517 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 335521 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335525 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335529 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 335533 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335538 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 335542 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335546 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335550 */     // MIs[3] Operand 1
     /* 335550 */     // No operand predicates
     /* 335550 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 335554 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335558 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335562 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 335566 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335571 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 335575 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335579 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 335581 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335581 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335584 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335588 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335593 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335599 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335604 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 335612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335614 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335616 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335619 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 335623 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 335626 */     GIR_RootConstrainSelectedInstOperands,
     /* 335627 */     // GIR_Coverage, 6777,
     /* 335627 */     GIR_EraseRootFromParent_Done,
     /* 335628 */   // Label 6733: @335628
     /* 335628 */   GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(335763), // Rule ID 2493 //
     /* 335633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 335636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335657 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 335661 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 335665 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335669 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335673 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 335677 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335682 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 335686 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335690 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 335692 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 335692 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 335695 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335699 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335704 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 335710 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335715 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335720 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335723 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335727 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335732 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335738 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335743 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 335751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 335753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335756 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 335759 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 335761 */     GIR_RootConstrainSelectedInstOperands,
     /* 335762 */     // GIR_Coverage, 2493,
     /* 335762 */     GIR_EraseRootFromParent_Done,
     /* 335763 */   // Label 6734: @335763
     /* 335763 */   GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(335882), // Rule ID 6681 //
     /* 335768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335771 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335775 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335779 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335783 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335787 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335792 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 335796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 335800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335804 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335808 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 335812 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335817 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 335821 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335825 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335829 */     // MIs[3] Operand 1
     /* 335829 */     // No operand predicates
     /* 335829 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335833 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 335835 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335835 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335838 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335842 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335847 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335853 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335858 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 335866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335868 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335870 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335873 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 335877 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 335880 */     GIR_RootConstrainSelectedInstOperands,
     /* 335881 */     // GIR_Coverage, 6681,
     /* 335881 */     GIR_EraseRootFromParent_Done,
     /* 335882 */   // Label 6735: @335882
     /* 335882 */   GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(336001), // Rule ID 2572 //
     /* 335887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 335890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 335894 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335898 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335902 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 335906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 335911 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 335915 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 335919 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 335923 */     // MIs[2] Operand 1
     /* 335923 */     // No operand predicates
     /* 335923 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 335927 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 335931 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 335935 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 335939 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335944 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 335948 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335952 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 335954 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 335954 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 335957 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 335961 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 335966 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 335972 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 335977 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 335982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 335985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 335987 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 335989 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 335992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 335996 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 335999 */     GIR_RootConstrainSelectedInstOperands,
     /* 336000 */     // GIR_Coverage, 2572,
     /* 336000 */     GIR_EraseRootFromParent_Done,
     /* 336001 */   // Label 6736: @336001
     /* 336001 */   GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(336101), // Rule ID 4904 //
     /* 336006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336009 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336013 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336017 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336021 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 336025 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336030 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 336034 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 336038 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336042 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 336046 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336051 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336055 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336057 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 336057 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336060 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336064 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336069 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 336075 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336080 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336085 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 336088 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336090 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336093 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 336097 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 336099 */     GIR_RootConstrainSelectedInstOperands,
     /* 336100 */     // GIR_Coverage, 4904,
     /* 336100 */     GIR_EraseRootFromParent_Done,
     /* 336101 */   // Label 6737: @336101
     /* 336101 */   GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(336201), // Rule ID 4940 //
     /* 336106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336113 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336117 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336121 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 336125 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336130 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 336134 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336138 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 336142 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336146 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 336150 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336155 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336157 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 336157 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336160 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336164 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336169 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 336175 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336180 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 336188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336190 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336193 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 336195 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 336199 */     GIR_RootConstrainSelectedInstOperands,
     /* 336200 */     // GIR_Coverage, 4940,
     /* 336200 */     GIR_EraseRootFromParent_Done,
     /* 336201 */   // Label 6738: @336201
     /* 336201 */   GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(336298), // Rule ID 14876 //
     /* 336206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336209 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336213 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336217 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336221 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 336225 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336229 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336233 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336237 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336242 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 336246 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336250 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336254 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336256 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 336256 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336259 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336263 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336268 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 336274 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336279 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 336287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336289 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 336291 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336294 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 336296 */     GIR_RootConstrainSelectedInstOperands,
     /* 336297 */     // GIR_Coverage, 14876,
     /* 336297 */     GIR_EraseRootFromParent_Done,
     /* 336298 */   // Label 6739: @336298
     /* 336298 */   GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(336398), // Rule ID 14878 //
     /* 336303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336314 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336318 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336323 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 336327 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336331 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336335 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336339 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336344 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 336348 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336352 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336354 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 336354 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336357 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336361 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336366 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 336372 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336377 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336382 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 336385 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336387 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336390 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 336394 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 336396 */     GIR_RootConstrainSelectedInstOperands,
     /* 336397 */     // GIR_Coverage, 14878,
     /* 336397 */     GIR_EraseRootFromParent_Done,
     /* 336398 */   // Label 6740: @336398
     /* 336398 */   GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(336498), // Rule ID 4938 //
     /* 336403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336406 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 336414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336422 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 336426 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336431 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 336435 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 336439 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336443 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 336447 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336452 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336454 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 336454 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336457 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336461 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336466 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 336472 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336477 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 336485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336487 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 336489 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 336496 */     GIR_RootConstrainSelectedInstOperands,
     /* 336497 */     // GIR_Coverage, 4938,
     /* 336497 */     GIR_EraseRootFromParent_Done,
     /* 336498 */   // Label 6741: @336498
     /* 336498 */   GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(336595), // Rule ID 4902 //
     /* 336503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336506 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 336514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 336526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336530 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336534 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336538 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336543 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 336547 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336551 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 336553 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 336553 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336556 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336560 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336565 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 336571 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336576 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 336584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 336586 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 336588 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 336591 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 336593 */     GIR_RootConstrainSelectedInstOperands,
     /* 336594 */     // GIR_Coverage, 4902,
     /* 336594 */     GIR_EraseRootFromParent_Done,
     /* 336595 */   // Label 6742: @336595
     /* 336595 */   GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(336679), // Rule ID 6743 //
     /* 336600 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 336603 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336607 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336611 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336615 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 336619 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 336624 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 336628 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 336632 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 336636 */     // MIs[2] Operand 1
     /* 336636 */     // No operand predicates
     /* 336636 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 336640 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336644 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 336648 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336653 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336657 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 336659 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 336659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 336662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 336664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 336666 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 336670 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 336674 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 336677 */     GIR_RootConstrainSelectedInstOperands,
     /* 336678 */     // GIR_Coverage, 6743,
     /* 336678 */     GIR_EraseRootFromParent_Done,
     /* 336679 */   // Label 6743: @336679
     /* 336679 */   GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(336760), // Rule ID 6775 //
     /* 336684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 336687 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336691 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336695 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336699 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 336703 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336707 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336711 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336715 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 336720 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 336724 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 336728 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 336732 */     // MIs[3] Operand 1
     /* 336732 */     // No operand predicates
     /* 336732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336736 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336740 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 336742 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 336742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 336745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 336747 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 336749 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 336751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 336755 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 336758 */     GIR_RootConstrainSelectedInstOperands,
     /* 336759 */     // GIR_Coverage, 6775,
     /* 336759 */     GIR_EraseRootFromParent_Done,
     /* 336760 */   // Label 6744: @336760
     /* 336760 */   GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(336844), // Rule ID 6807 //
     /* 336765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 336768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336776 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336780 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336785 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 336789 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336793 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336797 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336801 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 336806 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 336810 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 336814 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 336818 */     // MIs[3] Operand 1
     /* 336818 */     // No operand predicates
     /* 336818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336822 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 336824 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 336824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 336827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 336829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 336831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 336835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 336839 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 336842 */     GIR_RootConstrainSelectedInstOperands,
     /* 336843 */     // GIR_Coverage, 6807,
     /* 336843 */     GIR_EraseRootFromParent_Done,
     /* 336844 */   // Label 6745: @336844
     /* 336844 */   GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(336925), // Rule ID 6711 //
     /* 336849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 336852 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 336860 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 336864 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 336868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 336872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336876 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336880 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 336884 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 336889 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 336893 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 336897 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 336901 */     // MIs[3] Operand 1
     /* 336901 */     // No operand predicates
     /* 336901 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336905 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 336907 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 336907 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 336910 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 336912 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 336914 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 336916 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 336920 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 336923 */     GIR_RootConstrainSelectedInstOperands,
     /* 336924 */     // GIR_Coverage, 6711,
     /* 336924 */     GIR_EraseRootFromParent_Done,
     /* 336925 */   // Label 6746: @336925
     /* 336925 */   GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(337010), // Rule ID 2491 //
     /* 336930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 336933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 336937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 336941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 336945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 336949 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336954 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 336958 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336962 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336966 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 336968 */     // (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 336968 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 336971 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 336975 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 336980 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 336986 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 336991 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 336996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 336999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337001 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337004 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 337006 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337008 */     GIR_RootConstrainSelectedInstOperands,
     /* 337009 */     // GIR_Coverage, 2491,
     /* 337009 */     GIR_EraseRootFromParent_Done,
     /* 337010 */   // Label 6747: @337010
     /* 337010 */   GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(337095), // Rule ID 2489 //
     /* 337015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 337018 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337022 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 337026 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337030 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 337034 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337038 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337043 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 337047 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337051 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337053 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 337053 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 337056 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337060 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337065 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 337071 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337076 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 337084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337086 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 337088 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337091 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337093 */     GIR_RootConstrainSelectedInstOperands,
     /* 337094 */     // GIR_Coverage, 2489,
     /* 337094 */     GIR_EraseRootFromParent_Done,
     /* 337095 */   // Label 6748: @337095
     /* 337095 */   GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(337164), // Rule ID 2570 //
     /* 337100 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337103 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337107 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337111 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 337115 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337119 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 337124 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 337128 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 337132 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 337136 */     // MIs[2] Operand 1
     /* 337136 */     // No operand predicates
     /* 337136 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337140 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337144 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 337146 */     // (fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 337146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 337149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 337151 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 337153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 337155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 337159 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 337162 */     GIR_RootConstrainSelectedInstOperands,
     /* 337163 */     // GIR_Coverage, 2570,
     /* 337163 */     GIR_EraseRootFromParent_Done,
     /* 337164 */   // Label 6749: @337164
     /* 337164 */   GIM_Try, /*On fail goto*//*Label 6750*/ GIMT_Encode4(337233), // Rule ID 6679 //
     /* 337169 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337172 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337176 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 337180 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337184 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 337188 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 337197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 337201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 337205 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 337209 */     // MIs[2] Operand 1
     /* 337209 */     // No operand predicates
     /* 337209 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337213 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 337215 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 337215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 337218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 337220 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 337222 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 337224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 337228 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 337231 */     GIR_RootConstrainSelectedInstOperands,
     /* 337232 */     // GIR_Coverage, 6679,
     /* 337232 */     GIR_EraseRootFromParent_Done,
     /* 337233 */   // Label 6750: @337233
     /* 337233 */   GIM_Try, /*On fail goto*//*Label 6751*/ GIMT_Encode4(337298), // Rule ID 4958 //
     /* 337238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337241 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337245 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337249 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337262 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 337266 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337270 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 337274 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337279 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 337281 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 337284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 337290 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 337292 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 337296 */     GIR_RootConstrainSelectedInstOperands,
     /* 337297 */     // GIR_Coverage, 4958,
     /* 337297 */     GIR_EraseRootFromParent_Done,
     /* 337298 */   // Label 6751: @337298
     /* 337298 */   GIM_Try, /*On fail goto*//*Label 6752*/ GIMT_Encode4(337363), // Rule ID 14896 //
     /* 337303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337306 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 337314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337322 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 337331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337335 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 337339 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337344 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 337346 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337346 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 337349 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 337355 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 337357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 337361 */     GIR_RootConstrainSelectedInstOperands,
     /* 337362 */     // GIR_Coverage, 14896,
     /* 337362 */     GIR_EraseRootFromParent_Done,
     /* 337363 */   // Label 6752: @337363
     /* 337363 */   GIM_Try, /*On fail goto*//*Label 6753*/ GIMT_Encode4(337413), // Rule ID 4955 //
     /* 337368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337371 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337375 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337379 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337383 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337392 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337396 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337398 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 337401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337403 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 337407 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 337409 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337411 */     GIR_RootConstrainSelectedInstOperands,
     /* 337412 */     // GIR_Coverage, 4955,
     /* 337412 */     GIR_EraseRootFromParent_Done,
     /* 337413 */   // Label 6753: @337413
     /* 337413 */   GIM_Try, /*On fail goto*//*Label 6754*/ GIMT_Encode4(337463), // Rule ID 14362 //
     /* 337418 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 337421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337429 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337433 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337438 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337442 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337446 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337448 */     // (fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 337451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337453 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 337455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 337459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337461 */     GIR_RootConstrainSelectedInstOperands,
     /* 337462 */     // GIR_Coverage, 14362,
     /* 337462 */     GIR_EraseRootFromParent_Done,
     /* 337463 */   // Label 6754: @337463
     /* 337463 */   GIM_Try, /*On fail goto*//*Label 6755*/ GIMT_Encode4(337513), // Rule ID 686 //
     /* 337468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 337471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337475 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 337479 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337483 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337487 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337492 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337496 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337498 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337498 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 337501 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337503 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 337505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 337509 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337511 */     GIR_RootConstrainSelectedInstOperands,
     /* 337512 */     // GIR_Coverage, 686,
     /* 337512 */     GIR_EraseRootFromParent_Done,
     /* 337513 */   // Label 6755: @337513
     /* 337513 */   GIM_Try, /*On fail goto*//*Label 6756*/ GIMT_Encode4(337563), // Rule ID 14893 //
     /* 337518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 337521 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337525 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 337529 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337533 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337542 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337546 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337548 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 337551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337553 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 337557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 337559 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337561 */     GIR_RootConstrainSelectedInstOperands,
     /* 337562 */     // GIR_Coverage, 14893,
     /* 337562 */     GIR_EraseRootFromParent_Done,
     /* 337563 */   // Label 6756: @337563
     /* 337563 */   GIM_Try, /*On fail goto*//*Label 6757*/ GIMT_Encode4(337613), // Rule ID 698 //
     /* 337568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 337571 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337575 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337579 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 337583 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337587 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 337591 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337596 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 337598 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 337601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337603 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 337605 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 337607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 337611 */     GIR_RootConstrainSelectedInstOperands,
     /* 337612 */     // GIR_Coverage, 698,
     /* 337612 */     GIR_EraseRootFromParent_Done,
     /* 337613 */   // Label 6757: @337613
     /* 337613 */   GIM_Try, /*On fail goto*//*Label 6758*/ GIMT_Encode4(337644), // Rule ID 680 //
     /* 337618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 337621 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337629 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 337633 */     // (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 337633 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 337638 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 337642 */     GIR_RootConstrainSelectedInstOperands,
     /* 337643 */     // GIR_Coverage, 680,
     /* 337643 */     GIR_Done,
     /* 337644 */   // Label 6758: @337644
     /* 337644 */   GIM_Reject,
     /* 337645 */ // Label 6726: @337645
     /* 337645 */ GIM_Reject,
     /* 337646 */ // Label 6718: @337646
     /* 337646 */ GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(340793),
     /* 337651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 337654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 337657 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 337660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337664 */   GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(337814), // Rule ID 4948 //
     /* 337669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 337672 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337676 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337680 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337684 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337688 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337693 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 337697 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 337701 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337705 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337709 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 337713 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337718 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 337722 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 337726 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337730 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 337734 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337739 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 337741 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 337741 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 337744 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337748 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337753 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 337759 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337764 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337769 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 337772 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337776 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337781 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 337787 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337792 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 337800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337802 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337805 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 337808 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 337812 */     GIR_RootConstrainSelectedInstOperands,
     /* 337813 */     // GIR_Coverage, 4948,
     /* 337813 */     GIR_EraseRootFromParent_Done,
     /* 337814 */   // Label 6760: @337814
     /* 337814 */   GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(337961), // Rule ID 4912 //
     /* 337819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 337822 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337826 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337830 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337834 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 337838 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337843 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 337847 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 337851 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337855 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 337859 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 337863 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337867 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337871 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 337875 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337880 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 337884 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337888 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 337890 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 337890 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 337893 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337897 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337902 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 337908 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337913 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337918 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 337921 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 337925 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 337930 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 337936 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 337941 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 337946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 337949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 337951 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 337954 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 337957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 337959 */     GIR_RootConstrainSelectedInstOperands,
     /* 337960 */     // GIR_Coverage, 4912,
     /* 337960 */     GIR_EraseRootFromParent_Done,
     /* 337961 */   // Label 6761: @337961
     /* 337961 */   GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(338108), // Rule ID 14886 //
     /* 337966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 337969 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 337973 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 337977 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 337981 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 337985 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 337989 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 337993 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 337997 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338002 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 338006 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 338010 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338014 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338018 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 338022 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338027 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 338031 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338035 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 338037 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 338037 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 338040 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338044 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338049 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 338055 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338060 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338065 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338068 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338072 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338077 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338083 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338088 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 338096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338101 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 338104 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 338106 */     GIR_RootConstrainSelectedInstOperands,
     /* 338107 */     // GIR_Coverage, 14886,
     /* 338107 */     GIR_EraseRootFromParent_Done,
     /* 338108 */   // Label 6762: @338108
     /* 338108 */   GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(338239), // Rule ID 6729 //
     /* 338113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338116 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338120 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338124 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338128 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 338132 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338137 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 338141 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 338145 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 338149 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 338153 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 338157 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338161 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338165 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 338169 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338174 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 338178 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338182 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338186 */     // MIs[4] Operand 1
     /* 338186 */     // No operand predicates
     /* 338186 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338190 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 338192 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338192 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338195 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338199 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338204 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338210 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338215 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 338223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338225 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338227 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338230 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 338234 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 338237 */     GIR_RootConstrainSelectedInstOperands,
     /* 338238 */     // GIR_Coverage, 6729,
     /* 338238 */     GIR_EraseRootFromParent_Done,
     /* 338239 */   // Label 6763: @338239
     /* 338239 */   GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(338370), // Rule ID 6761 //
     /* 338244 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338247 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338251 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338255 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338259 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 338263 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338268 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 338272 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338276 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338280 */     // MIs[2] Operand 1
     /* 338280 */     // No operand predicates
     /* 338280 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 338284 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 338288 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 338292 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 338296 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338300 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338304 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 338308 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338313 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 338317 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338321 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 338323 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338323 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338326 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338330 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338335 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338341 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338346 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 338354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338356 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338358 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 338365 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 338368 */     GIR_RootConstrainSelectedInstOperands,
     /* 338369 */     // GIR_Coverage, 6761,
     /* 338369 */     GIR_EraseRootFromParent_Done,
     /* 338370 */   // Label 6764: @338370
     /* 338370 */   GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(338501), // Rule ID 6825 //
     /* 338375 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338378 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338382 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 338386 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 338390 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 338394 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338398 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338402 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 338406 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338411 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 338415 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 338419 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338423 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338427 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 338431 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338436 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 338440 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338444 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338448 */     // MIs[4] Operand 1
     /* 338448 */     // No operand predicates
     /* 338448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338452 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 338454 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338454 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338457 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338461 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338466 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338472 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338477 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 338485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338487 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338489 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 338496 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 338499 */     GIR_RootConstrainSelectedInstOperands,
     /* 338500 */     // GIR_Coverage, 6825,
     /* 338500 */     GIR_EraseRootFromParent_Done,
     /* 338501 */   // Label 6765: @338501
     /* 338501 */   GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(338632), // Rule ID 6793 //
     /* 338506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338513 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 338517 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 338521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 338525 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338529 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338533 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 338537 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338542 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 338546 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338550 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338554 */     // MIs[3] Operand 1
     /* 338554 */     // No operand predicates
     /* 338554 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 338558 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338562 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338566 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 338570 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338575 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 338579 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338583 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 338585 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338585 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338588 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338592 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338597 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338603 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338608 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 338616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338618 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338620 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338623 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 338627 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 338630 */     GIR_RootConstrainSelectedInstOperands,
     /* 338631 */     // GIR_Coverage, 6793,
     /* 338631 */     GIR_EraseRootFromParent_Done,
     /* 338632 */   // Label 6766: @338632
     /* 338632 */   GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(338767), // Rule ID 2499 //
     /* 338637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 338640 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338644 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338648 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338652 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 338656 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338661 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 338665 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 338669 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338673 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338677 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 338681 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338686 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 338690 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338694 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 338696 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 338696 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 338699 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338703 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338708 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 338714 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338719 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338724 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338727 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338731 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338736 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338742 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338747 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 338755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 338757 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338760 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 338763 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 338765 */     GIR_RootConstrainSelectedInstOperands,
     /* 338766 */     // GIR_Coverage, 2499,
     /* 338766 */     GIR_EraseRootFromParent_Done,
     /* 338767 */   // Label 6767: @338767
     /* 338767 */   GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(338886), // Rule ID 6697 //
     /* 338772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338779 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338783 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338787 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 338791 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338796 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 338800 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 338804 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338808 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338812 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 338816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338821 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 338825 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338829 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338833 */     // MIs[3] Operand 1
     /* 338833 */     // No operand predicates
     /* 338833 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338837 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 338839 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338842 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338846 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338851 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338857 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338862 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 338870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338874 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 338881 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 338884 */     GIR_RootConstrainSelectedInstOperands,
     /* 338885 */     // GIR_Coverage, 6697,
     /* 338885 */     GIR_EraseRootFromParent_Done,
     /* 338886 */   // Label 6768: @338886
     /* 338886 */   GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(339005), // Rule ID 2588 //
     /* 338891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 338894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 338898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 338910 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338915 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 338919 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 338923 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 338927 */     // MIs[2] Operand 1
     /* 338927 */     // No operand predicates
     /* 338927 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 338931 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 338935 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 338939 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 338943 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338948 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 338952 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338956 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 338958 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 338958 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 338961 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 338965 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 338970 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 338976 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 338981 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 338986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 338989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 338991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 338993 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 338996 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 339000 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 339003 */     GIR_RootConstrainSelectedInstOperands,
     /* 339004 */     // GIR_Coverage, 2588,
     /* 339004 */     GIR_EraseRootFromParent_Done,
     /* 339005 */   // Label 6769: @339005
     /* 339005 */   GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(339105), // Rule ID 4910 //
     /* 339010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339013 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339017 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339021 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339025 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339029 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339034 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339038 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 339042 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339046 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 339050 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339055 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339059 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339061 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 339061 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339064 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339068 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339073 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 339079 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339084 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339089 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 339092 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339094 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339097 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 339101 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 339103 */     GIR_RootConstrainSelectedInstOperands,
     /* 339104 */     // GIR_Coverage, 4910,
     /* 339104 */     GIR_EraseRootFromParent_Done,
     /* 339105 */   // Label 6770: @339105
     /* 339105 */   GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(339205), // Rule ID 4946 //
     /* 339110 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339121 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339125 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339129 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339134 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339138 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 339146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339150 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 339154 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339159 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339161 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 339161 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339164 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339168 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339173 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 339179 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339184 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339189 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 339192 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339194 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339197 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 339199 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 339203 */     GIR_RootConstrainSelectedInstOperands,
     /* 339204 */     // GIR_Coverage, 4946,
     /* 339204 */     GIR_EraseRootFromParent_Done,
     /* 339205 */   // Label 6771: @339205
     /* 339205 */   GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(339302), // Rule ID 14882 //
     /* 339210 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339213 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339217 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339221 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339225 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339229 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339233 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339237 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339241 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339246 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 339250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339254 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339258 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339260 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 339260 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339263 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339267 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339272 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 339278 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339283 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 339291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339293 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 339295 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339298 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 339300 */     GIR_RootConstrainSelectedInstOperands,
     /* 339301 */     // GIR_Coverage, 14882,
     /* 339301 */     GIR_EraseRootFromParent_Done,
     /* 339302 */   // Label 6772: @339302
     /* 339302 */   GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(339402), // Rule ID 14884 //
     /* 339307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339318 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339322 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 339331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339335 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339339 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339343 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339348 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 339352 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339356 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339358 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 339358 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339361 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339365 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339370 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 339376 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339381 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 339389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339391 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 339398 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 339400 */     GIR_RootConstrainSelectedInstOperands,
     /* 339401 */     // GIR_Coverage, 14884,
     /* 339401 */     GIR_EraseRootFromParent_Done,
     /* 339402 */   // Label 6773: @339402
     /* 339402 */   GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(339502), // Rule ID 4944 //
     /* 339407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 339418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339426 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339435 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 339439 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 339443 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339447 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 339451 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339456 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339458 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 339458 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339461 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339465 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339470 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 339476 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339481 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 339489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339491 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 339493 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 339500 */     GIR_RootConstrainSelectedInstOperands,
     /* 339501 */     // GIR_Coverage, 4944,
     /* 339501 */     GIR_EraseRootFromParent_Done,
     /* 339502 */   // Label 6774: @339502
     /* 339502 */   GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(339599), // Rule ID 4908 //
     /* 339507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 339510 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339514 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 339518 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339522 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339526 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339530 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339534 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339538 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339542 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339547 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 339551 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339555 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 339557 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 339557 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 339560 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 339564 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 339569 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 339575 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339580 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 339588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 339590 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 339592 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 339595 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 339597 */     GIR_RootConstrainSelectedInstOperands,
     /* 339598 */     // GIR_Coverage, 4908,
     /* 339598 */     GIR_EraseRootFromParent_Done,
     /* 339599 */   // Label 6775: @339599
     /* 339599 */   GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(339677), // Rule ID 6847 //
     /* 339604 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339608 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339612 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339616 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339620 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339624 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339628 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339632 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339637 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 339641 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 339645 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 339649 */     // MIs[3] Operand 1
     /* 339649 */     // No operand predicates
     /* 339649 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339653 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339657 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 339659 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 339659 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 339662 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 339664 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 339666 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 339668 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 339672 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 339675 */     GIR_RootConstrainSelectedInstOperands,
     /* 339676 */     // GIR_Coverage, 6847,
     /* 339676 */     GIR_EraseRootFromParent_Done,
     /* 339677 */   // Label 6776: @339677
     /* 339677 */   GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(339761), // Rule ID 6759 //
     /* 339682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339685 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339689 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339693 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339697 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339701 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339706 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 339710 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 339714 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 339718 */     // MIs[2] Operand 1
     /* 339718 */     // No operand predicates
     /* 339718 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 339722 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339726 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 339730 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339735 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339739 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 339741 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 339741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 339744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 339746 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 339748 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 339752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 339756 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 339759 */     GIR_RootConstrainSelectedInstOperands,
     /* 339760 */     // GIR_Coverage, 6759,
     /* 339760 */     GIR_EraseRootFromParent_Done,
     /* 339761 */   // Label 6777: @339761
     /* 339761 */   GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(339842), // Rule ID 6791 //
     /* 339766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339781 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339785 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339789 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339793 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339797 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339802 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 339806 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 339810 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 339814 */     // MIs[3] Operand 1
     /* 339814 */     // No operand predicates
     /* 339814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339818 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339822 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 339824 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 339824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 339827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 339829 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 339831 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 339833 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 339837 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 339840 */     GIR_RootConstrainSelectedInstOperands,
     /* 339841 */     // GIR_Coverage, 6791,
     /* 339841 */     GIR_EraseRootFromParent_Done,
     /* 339842 */   // Label 6778: @339842
     /* 339842 */   GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(339926), // Rule ID 6823 //
     /* 339847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 339850 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 339854 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339858 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 339862 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339867 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 339871 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339875 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339879 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 339883 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339888 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 339892 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 339896 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 339900 */     // MIs[3] Operand 1
     /* 339900 */     // No operand predicates
     /* 339900 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339904 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 339906 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 339906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 339909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 339911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 339913 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 339917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 339921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 339924 */     GIR_RootConstrainSelectedInstOperands,
     /* 339925 */     // GIR_Coverage, 6823,
     /* 339925 */     GIR_EraseRootFromParent_Done,
     /* 339926 */   // Label 6779: @339926
     /* 339926 */   GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(340004), // Rule ID 6869 //
     /* 339931 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339935 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 339939 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 339943 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339947 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 339951 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 339955 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 339959 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 339963 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 339968 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 339972 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 339976 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 339980 */     // MIs[3] Operand 1
     /* 339980 */     // No operand predicates
     /* 339980 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 339984 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 339986 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 339986 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 339989 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 339991 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 339993 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 339995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 339999 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 340002 */     GIR_RootConstrainSelectedInstOperands,
     /* 340003 */     // GIR_Coverage, 6869,
     /* 340003 */     GIR_EraseRootFromParent_Done,
     /* 340004 */   // Label 6780: @340004
     /* 340004 */   GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(340085), // Rule ID 6727 //
     /* 340009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 340012 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340016 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340020 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340024 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340028 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 340032 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340036 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 340040 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 340044 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340049 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 340053 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 340057 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 340061 */     // MIs[3] Operand 1
     /* 340061 */     // No operand predicates
     /* 340061 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340065 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 340067 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 340067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 340070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 340072 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 340074 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 340076 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 340080 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 340083 */     GIR_RootConstrainSelectedInstOperands,
     /* 340084 */     // GIR_Coverage, 6727,
     /* 340084 */     GIR_EraseRootFromParent_Done,
     /* 340085 */   // Label 6781: @340085
     /* 340085 */   GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(340170), // Rule ID 2497 //
     /* 340090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 340105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340109 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340114 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 340118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340122 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340126 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340128 */     // (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340128 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340131 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 340135 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340140 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 340146 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340151 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 340159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340161 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340164 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 340166 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340168 */     GIR_RootConstrainSelectedInstOperands,
     /* 340169 */     // GIR_Coverage, 2497,
     /* 340169 */     GIR_EraseRootFromParent_Done,
     /* 340170 */   // Label 6782: @340170
     /* 340170 */   GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(340255), // Rule ID 2495 //
     /* 340175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340178 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340182 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340186 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340190 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 340194 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340203 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 340207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340211 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340213 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 340213 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 340216 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 340220 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340225 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 340231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340236 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 340244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340246 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 340248 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340251 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340253 */     GIR_RootConstrainSelectedInstOperands,
     /* 340254 */     // GIR_Coverage, 2495,
     /* 340254 */     GIR_EraseRootFromParent_Done,
     /* 340255 */   // Label 6783: @340255
     /* 340255 */   GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(340324), // Rule ID 2586 //
     /* 340260 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 340263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340271 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 340275 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340279 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340284 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 340288 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 340292 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 340296 */     // MIs[2] Operand 1
     /* 340296 */     // No operand predicates
     /* 340296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340300 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340304 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 340306 */     // (fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 340306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 340309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 340311 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 340313 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 340315 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 340319 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 340322 */     GIR_RootConstrainSelectedInstOperands,
     /* 340323 */     // GIR_Coverage, 2586,
     /* 340323 */     GIR_EraseRootFromParent_Done,
     /* 340324 */   // Label 6784: @340324
     /* 340324 */   GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(340393), // Rule ID 6695 //
     /* 340329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 340332 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340336 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340340 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340344 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 340348 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340352 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340357 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 340361 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 340365 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 340369 */     // MIs[2] Operand 1
     /* 340369 */     // No operand predicates
     /* 340369 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340373 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 340375 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 340375 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 340378 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 340380 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 340382 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 340384 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 340388 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 340391 */     GIR_RootConstrainSelectedInstOperands,
     /* 340392 */     // GIR_Coverage, 6695,
     /* 340392 */     GIR_EraseRootFromParent_Done,
     /* 340393 */   // Label 6785: @340393
     /* 340393 */   GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(340455), // Rule ID 4959 //
     /* 340398 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340402 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340406 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340410 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340415 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 340423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340427 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 340431 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340436 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 340438 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 340441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 340447 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 340449 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 340453 */     GIR_RootConstrainSelectedInstOperands,
     /* 340454 */     // GIR_Coverage, 4959,
     /* 340454 */     GIR_EraseRootFromParent_Done,
     /* 340455 */   // Label 6786: @340455
     /* 340455 */   GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(340517), // Rule ID 14897 //
     /* 340460 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340476 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340481 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 340485 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340489 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 340493 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340498 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 340500 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 340503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 340509 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 340511 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 340515 */     GIR_RootConstrainSelectedInstOperands,
     /* 340516 */     // GIR_Coverage, 14897,
     /* 340516 */     GIR_EraseRootFromParent_Done,
     /* 340517 */   // Label 6787: @340517
     /* 340517 */   GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(340564), // Rule ID 4956 //
     /* 340522 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340526 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340530 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340534 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340539 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340543 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340547 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340549 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 340552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340554 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 340558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 340560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340562 */     GIR_RootConstrainSelectedInstOperands,
     /* 340563 */     // GIR_Coverage, 4956,
     /* 340563 */     GIR_EraseRootFromParent_Done,
     /* 340564 */   // Label 6788: @340564
     /* 340564 */   GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(340614), // Rule ID 14364 //
     /* 340569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340580 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340584 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340597 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340599 */     // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 340602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340604 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 340606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 340610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340612 */     GIR_RootConstrainSelectedInstOperands,
     /* 340613 */     // GIR_Coverage, 14364,
     /* 340613 */     GIR_EraseRootFromParent_Done,
     /* 340614 */   // Label 6789: @340614
     /* 340614 */   GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(340664), // Rule ID 688 //
     /* 340619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340622 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340626 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340630 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340634 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340638 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340643 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340647 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340649 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 340652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340654 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 340656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 340660 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340662 */     GIR_RootConstrainSelectedInstOperands,
     /* 340663 */     // GIR_Coverage, 688,
     /* 340663 */     GIR_EraseRootFromParent_Done,
     /* 340664 */   // Label 6790: @340664
     /* 340664 */   GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(340711), // Rule ID 14894 //
     /* 340669 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 340677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340685 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340690 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340694 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340696 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 340699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340701 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 340705 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 340707 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 340709 */     GIR_RootConstrainSelectedInstOperands,
     /* 340710 */     // GIR_Coverage, 14894,
     /* 340710 */     GIR_EraseRootFromParent_Done,
     /* 340711 */   // Label 6791: @340711
     /* 340711 */   GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(340761), // Rule ID 700 //
     /* 340716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340719 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 340731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 340739 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340744 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 340746 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 340749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340751 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 340753 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 340755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 340759 */     GIR_RootConstrainSelectedInstOperands,
     /* 340760 */     // GIR_Coverage, 700,
     /* 340760 */     GIR_EraseRootFromParent_Done,
     /* 340761 */   // Label 6792: @340761
     /* 340761 */   GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(340792), // Rule ID 682 //
     /* 340766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340769 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340777 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 340781 */     // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 340781 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 340786 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 340790 */     GIR_RootConstrainSelectedInstOperands,
     /* 340791 */     // GIR_Coverage, 682,
     /* 340791 */     GIR_Done,
     /* 340792 */   // Label 6793: @340792
     /* 340792 */   GIM_Reject,
     /* 340793 */ // Label 6759: @340793
     /* 340793 */ GIM_Reject,
     /* 340794 */ // Label 6719: @340794
     /* 340794 */ GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(343941),
     /* 340799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 340802 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 340805 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 340808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 340812 */   GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(340962), // Rule ID 4954 //
     /* 340817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340828 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 340832 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340836 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340841 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 340845 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 340849 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340853 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 340857 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 340861 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340866 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 340870 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 340874 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 340878 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 340882 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 340887 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 340889 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 340889 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 340892 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 340896 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340901 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 340907 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 340912 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340917 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 340920 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 340924 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 340929 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 340935 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 340940 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 340948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 340950 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 340953 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 340956 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 340960 */     GIR_RootConstrainSelectedInstOperands,
     /* 340961 */     // GIR_Coverage, 4954,
     /* 340961 */     GIR_EraseRootFromParent_Done,
     /* 340962 */   // Label 6795: @340962
     /* 340962 */   GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(341109), // Rule ID 4918 //
     /* 340967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 340970 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 340974 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 340978 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 340982 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 340986 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 340991 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 340995 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 340999 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341003 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 341007 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 341011 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341015 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341019 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 341023 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341028 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 341032 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341036 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 341038 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 341038 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341041 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341045 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341050 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 341056 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341061 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341066 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341069 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341073 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341078 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341084 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341089 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 341097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341099 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341102 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 341105 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 341107 */     GIR_RootConstrainSelectedInstOperands,
     /* 341108 */     // GIR_Coverage, 4918,
     /* 341108 */     GIR_EraseRootFromParent_Done,
     /* 341109 */   // Label 6796: @341109
     /* 341109 */   GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(341256), // Rule ID 14892 //
     /* 341114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 341117 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341121 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341125 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 341129 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 341133 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341137 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341141 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 341145 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341150 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 341154 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 341158 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341162 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341166 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 341170 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341175 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 341179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341183 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 341185 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 341185 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341188 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341192 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341197 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 341203 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341208 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341213 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341216 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341220 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341225 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341236 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 341244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341246 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341249 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 341252 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 341254 */     GIR_RootConstrainSelectedInstOperands,
     /* 341255 */     // GIR_Coverage, 14892,
     /* 341255 */     GIR_EraseRootFromParent_Done,
     /* 341256 */   // Label 6797: @341256
     /* 341256 */   GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(341387), // Rule ID 6733 //
     /* 341261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 341264 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341268 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341272 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341276 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341280 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341285 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 341289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 341293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341297 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 341301 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 341305 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341309 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341313 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 341317 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341322 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 341326 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 341330 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 341334 */     // MIs[4] Operand 1
     /* 341334 */     // No operand predicates
     /* 341334 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341338 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 341340 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 341340 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341343 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341347 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341352 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341358 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341363 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 341371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 341373 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 341375 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341378 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 341382 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 341385 */     GIR_RootConstrainSelectedInstOperands,
     /* 341386 */     // GIR_Coverage, 6733,
     /* 341386 */     GIR_EraseRootFromParent_Done,
     /* 341387 */   // Label 6798: @341387
     /* 341387 */   GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(341518), // Rule ID 6765 //
     /* 341392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 341395 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341399 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341403 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341407 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341411 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 341420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 341424 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 341428 */     // MIs[2] Operand 1
     /* 341428 */     // No operand predicates
     /* 341428 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 341432 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341436 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 341440 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 341444 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341448 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341452 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 341456 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341461 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 341465 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341469 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 341471 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 341471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341483 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341489 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341494 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341499 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 341502 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 341504 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 341506 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 341513 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 341516 */     GIR_RootConstrainSelectedInstOperands,
     /* 341517 */     // GIR_Coverage, 6765,
     /* 341517 */     GIR_EraseRootFromParent_Done,
     /* 341518 */   // Label 6799: @341518
     /* 341518 */   GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(341649), // Rule ID 6829 //
     /* 341523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 341526 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341530 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341534 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 341538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 341542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341546 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341550 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 341554 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341559 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 341563 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 341567 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341571 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341575 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 341579 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341584 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 341588 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 341592 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 341596 */     // MIs[4] Operand 1
     /* 341596 */     // No operand predicates
     /* 341596 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341600 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 341602 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 341602 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341605 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341609 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341614 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341620 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341625 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 341633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 341635 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 341637 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 341644 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 341647 */     GIR_RootConstrainSelectedInstOperands,
     /* 341648 */     // GIR_Coverage, 6829,
     /* 341648 */     GIR_EraseRootFromParent_Done,
     /* 341649 */   // Label 6800: @341649
     /* 341649 */   GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(341780), // Rule ID 6797 //
     /* 341654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 341657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 341665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 341669 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 341673 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341677 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341681 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 341685 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341690 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 341694 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 341698 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 341702 */     // MIs[3] Operand 1
     /* 341702 */     // No operand predicates
     /* 341702 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 341706 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341710 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341714 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 341718 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341723 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 341727 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341731 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 341733 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 341733 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341736 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341740 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341745 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341751 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341756 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 341764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 341766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 341768 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341771 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 341775 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 341778 */     GIR_RootConstrainSelectedInstOperands,
     /* 341779 */     // GIR_Coverage, 6797,
     /* 341779 */     GIR_EraseRootFromParent_Done,
     /* 341780 */   // Label 6801: @341780
     /* 341780 */   GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(341915), // Rule ID 2505 //
     /* 341785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 341788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341800 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341804 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341809 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 341813 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 341817 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341821 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341825 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 341829 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341834 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 341838 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341842 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 341844 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 341844 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 341847 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341851 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341856 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 341862 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341867 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341872 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341875 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341879 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341884 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 341890 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341895 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 341903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 341905 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 341908 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 341911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 341913 */     GIR_RootConstrainSelectedInstOperands,
     /* 341914 */     // GIR_Coverage, 2505,
     /* 341914 */     GIR_EraseRootFromParent_Done,
     /* 341915 */   // Label 6802: @341915
     /* 341915 */   GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(342034), // Rule ID 6701 //
     /* 341920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 341923 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 341927 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341931 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341935 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 341939 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341944 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 341948 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 341952 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 341956 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 341960 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 341964 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 341969 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 341973 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 341977 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 341981 */     // MIs[3] Operand 1
     /* 341981 */     // No operand predicates
     /* 341981 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 341985 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 341987 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 341987 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 341990 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 341994 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 341999 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 342005 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342010 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 342018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 342020 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 342022 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342025 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 342029 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 342032 */     GIR_RootConstrainSelectedInstOperands,
     /* 342033 */     // GIR_Coverage, 6701,
     /* 342033 */     GIR_EraseRootFromParent_Done,
     /* 342034 */   // Label 6803: @342034
     /* 342034 */   GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(342153), // Rule ID 2592 //
     /* 342039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 342042 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342046 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342050 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342054 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342058 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342063 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 342067 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 342071 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 342075 */     // MIs[2] Operand 1
     /* 342075 */     // No operand predicates
     /* 342075 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 342079 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342083 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342087 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 342091 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342096 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 342100 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342104 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 342106 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 342106 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342109 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342113 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342118 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 342124 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342129 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 342137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 342139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 342141 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 342148 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 342151 */     GIR_RootConstrainSelectedInstOperands,
     /* 342152 */     // GIR_Coverage, 2592,
     /* 342152 */     GIR_EraseRootFromParent_Done,
     /* 342153 */   // Label 6804: @342153
     /* 342153 */   GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(342253), // Rule ID 4916 //
     /* 342158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342169 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342173 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342177 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342182 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 342186 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 342190 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342194 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 342198 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342203 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342207 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342209 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 342209 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342212 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342216 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342221 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 342227 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342232 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342237 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 342240 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342242 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342245 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 342249 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 342251 */     GIR_RootConstrainSelectedInstOperands,
     /* 342252 */     // GIR_Coverage, 4916,
     /* 342252 */     GIR_EraseRootFromParent_Done,
     /* 342253 */   // Label 6805: @342253
     /* 342253 */   GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(342353), // Rule ID 4952 //
     /* 342258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342261 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342265 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342269 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342273 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342277 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342282 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 342286 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342290 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 342294 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342298 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 342302 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342307 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342309 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 342309 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342312 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342316 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342321 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 342327 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342332 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342337 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 342340 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342342 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342345 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 342347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 342351 */     GIR_RootConstrainSelectedInstOperands,
     /* 342352 */     // GIR_Coverage, 4952,
     /* 342352 */     GIR_EraseRootFromParent_Done,
     /* 342353 */   // Label 6806: @342353
     /* 342353 */   GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(342450), // Rule ID 14888 //
     /* 342358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342369 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 342373 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 342377 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342381 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342385 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 342389 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342394 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 342398 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342402 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342406 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342408 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 342408 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342411 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342415 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342420 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 342426 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342431 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 342439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342441 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 342443 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342446 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 342448 */     GIR_RootConstrainSelectedInstOperands,
     /* 342449 */     // GIR_Coverage, 14888,
     /* 342449 */     GIR_EraseRootFromParent_Done,
     /* 342450 */   // Label 6807: @342450
     /* 342450 */   GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(342550), // Rule ID 14890 //
     /* 342455 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342458 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342462 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342466 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 342470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 342479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342483 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342487 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 342491 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342496 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 342500 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342504 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342506 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 342506 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342509 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342513 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342518 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 342524 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342529 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 342537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342539 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342542 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 342546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 342548 */     GIR_RootConstrainSelectedInstOperands,
     /* 342549 */     // GIR_Coverage, 14890,
     /* 342549 */     GIR_EraseRootFromParent_Done,
     /* 342550 */   // Label 6808: @342550
     /* 342550 */   GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(342650), // Rule ID 4950 //
     /* 342555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342558 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342562 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 342566 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342570 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342574 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342578 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342583 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 342587 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 342591 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342595 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 342599 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342604 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342606 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 342606 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342609 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342613 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342618 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 342624 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 342637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342639 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 342641 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 342648 */     GIR_RootConstrainSelectedInstOperands,
     /* 342649 */     // GIR_Coverage, 4950,
     /* 342649 */     GIR_EraseRootFromParent_Done,
     /* 342650 */   // Label 6809: @342650
     /* 342650 */   GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(342747), // Rule ID 4914 //
     /* 342655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 342658 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342662 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 342666 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342670 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 342674 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 342678 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342682 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342686 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 342690 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342695 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 342699 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342703 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 342705 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 342705 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 342708 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 342712 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 342717 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 342723 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342728 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 342736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 342738 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 342740 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 342743 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 342745 */     GIR_RootConstrainSelectedInstOperands,
     /* 342746 */     // GIR_Coverage, 4914,
     /* 342746 */     GIR_EraseRootFromParent_Done,
     /* 342747 */   // Label 6810: @342747
     /* 342747 */   GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(342825), // Rule ID 6851 //
     /* 342752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342764 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342768 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 342772 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342776 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342780 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342785 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 342789 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 342793 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 342797 */     // MIs[3] Operand 1
     /* 342797 */     // No operand predicates
     /* 342797 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342801 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342805 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 342807 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 342807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 342810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 342812 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 342814 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 342816 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 342820 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 342823 */     GIR_RootConstrainSelectedInstOperands,
     /* 342824 */     // GIR_Coverage, 6851,
     /* 342824 */     GIR_EraseRootFromParent_Done,
     /* 342825 */   // Label 6811: @342825
     /* 342825 */   GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(342909), // Rule ID 6763 //
     /* 342830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 342833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342845 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 342849 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342854 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 342858 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 342862 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 342866 */     // MIs[2] Operand 1
     /* 342866 */     // No operand predicates
     /* 342866 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 342870 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342874 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 342878 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342887 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 342889 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 342889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 342892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 342894 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 342896 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 342900 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 342904 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 342907 */     GIR_RootConstrainSelectedInstOperands,
     /* 342908 */     // GIR_Coverage, 6763,
     /* 342908 */     GIR_EraseRootFromParent_Done,
     /* 342909 */   // Label 6812: @342909
     /* 342909 */   GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(342990), // Rule ID 6795 //
     /* 342914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 342917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 342921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 342925 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 342929 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 342933 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 342937 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 342941 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 342945 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 342950 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 342954 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 342958 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 342962 */     // MIs[3] Operand 1
     /* 342962 */     // No operand predicates
     /* 342962 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342966 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 342970 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 342972 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 342972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 342975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 342977 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 342979 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 342981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 342985 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 342988 */     GIR_RootConstrainSelectedInstOperands,
     /* 342989 */     // GIR_Coverage, 6795,
     /* 342989 */     GIR_EraseRootFromParent_Done,
     /* 342990 */   // Label 6813: @342990
     /* 342990 */   GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(343074), // Rule ID 6827 //
     /* 342995 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 342998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343010 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343015 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 343019 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343023 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343027 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 343031 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343036 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 343040 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 343044 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 343048 */     // MIs[3] Operand 1
     /* 343048 */     // No operand predicates
     /* 343048 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343052 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 343054 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 343054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 343057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 343059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 343061 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343065 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 343069 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 343072 */     GIR_RootConstrainSelectedInstOperands,
     /* 343073 */     // GIR_Coverage, 6827,
     /* 343073 */     GIR_EraseRootFromParent_Done,
     /* 343074 */   // Label 6814: @343074
     /* 343074 */   GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(343152), // Rule ID 6873 //
     /* 343079 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343083 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343087 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343091 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343095 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343099 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 343103 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343107 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343111 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343116 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 343120 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 343124 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 343128 */     // MIs[3] Operand 1
     /* 343128 */     // No operand predicates
     /* 343128 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343132 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 343134 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 343134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 343137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 343139 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 343141 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 343147 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 343150 */     GIR_RootConstrainSelectedInstOperands,
     /* 343151 */     // GIR_Coverage, 6873,
     /* 343151 */     GIR_EraseRootFromParent_Done,
     /* 343152 */   // Label 6815: @343152
     /* 343152 */   GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(343233), // Rule ID 6731 //
     /* 343157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343160 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343164 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343168 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343172 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 343180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343184 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343188 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 343192 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343197 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 343201 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 343205 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 343209 */     // MIs[3] Operand 1
     /* 343209 */     // No operand predicates
     /* 343209 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343213 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 343215 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 343215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 343218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 343220 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 343222 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 343228 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 343231 */     GIR_RootConstrainSelectedInstOperands,
     /* 343232 */     // GIR_Coverage, 6731,
     /* 343232 */     GIR_EraseRootFromParent_Done,
     /* 343233 */   // Label 6816: @343233
     /* 343233 */   GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(343318), // Rule ID 2503 //
     /* 343238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343241 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343245 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343249 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343253 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343257 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343262 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 343266 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343270 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343274 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343276 */     // (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343276 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 343279 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 343283 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343288 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 343294 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343299 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 343307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343309 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343312 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 343314 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343316 */     GIR_RootConstrainSelectedInstOperands,
     /* 343317 */     // GIR_Coverage, 2503,
     /* 343317 */     GIR_EraseRootFromParent_Done,
     /* 343318 */   // Label 6817: @343318
     /* 343318 */   GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(343403), // Rule ID 2501 //
     /* 343323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343326 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343342 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343346 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343351 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 343355 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343359 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343361 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 343361 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 343364 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 343368 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 343373 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 343379 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343384 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 343392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343394 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343396 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 343399 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343401 */     GIR_RootConstrainSelectedInstOperands,
     /* 343402 */     // GIR_Coverage, 2501,
     /* 343402 */     GIR_EraseRootFromParent_Done,
     /* 343403 */   // Label 6818: @343403
     /* 343403 */   GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(343472), // Rule ID 2590 //
     /* 343408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343415 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343419 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343423 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343427 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343432 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 343436 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 343440 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 343444 */     // MIs[2] Operand 1
     /* 343444 */     // No operand predicates
     /* 343444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343452 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 343454 */     // (fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 343454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 343457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 343459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 343461 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 343463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 343467 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 343470 */     GIR_RootConstrainSelectedInstOperands,
     /* 343471 */     // GIR_Coverage, 2590,
     /* 343471 */     GIR_EraseRootFromParent_Done,
     /* 343472 */   // Label 6819: @343472
     /* 343472 */   GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(343541), // Rule ID 6699 //
     /* 343477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 343480 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343484 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343488 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 343492 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 343496 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343500 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343505 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 343509 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 343513 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 343517 */     // MIs[2] Operand 1
     /* 343517 */     // No operand predicates
     /* 343517 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343521 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 343523 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 343523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 343526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 343528 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 343530 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343532 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 343536 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 343539 */     GIR_RootConstrainSelectedInstOperands,
     /* 343540 */     // GIR_Coverage, 6699,
     /* 343540 */     GIR_EraseRootFromParent_Done,
     /* 343541 */   // Label 6820: @343541
     /* 343541 */   GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(343603), // Rule ID 4960 //
     /* 343546 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343550 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343554 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343558 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343563 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343567 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 343571 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343575 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 343579 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343584 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 343586 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 343589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343591 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343595 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 343597 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 343601 */     GIR_RootConstrainSelectedInstOperands,
     /* 343602 */     // GIR_Coverage, 4960,
     /* 343602 */     GIR_EraseRootFromParent_Done,
     /* 343603 */   // Label 6821: @343603
     /* 343603 */   GIM_Try, /*On fail goto*//*Label 6822*/ GIMT_Encode4(343665), // Rule ID 14898 //
     /* 343608 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343612 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343616 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343620 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343624 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343629 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 343633 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343637 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 343641 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343646 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 343648 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 343651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343653 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343657 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 343659 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 343663 */     GIR_RootConstrainSelectedInstOperands,
     /* 343664 */     // GIR_Coverage, 14898,
     /* 343664 */     GIR_EraseRootFromParent_Done,
     /* 343665 */   // Label 6822: @343665
     /* 343665 */   GIM_Try, /*On fail goto*//*Label 6823*/ GIMT_Encode4(343712), // Rule ID 4957 //
     /* 343670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343682 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343687 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343691 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343695 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343697 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 343700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343706 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 343708 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343710 */     GIR_RootConstrainSelectedInstOperands,
     /* 343711 */     // GIR_Coverage, 4957,
     /* 343711 */     GIR_EraseRootFromParent_Done,
     /* 343712 */   // Label 6823: @343712
     /* 343712 */   GIM_Try, /*On fail goto*//*Label 6824*/ GIMT_Encode4(343762), // Rule ID 14366 //
     /* 343717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343724 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343728 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343741 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343745 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343747 */     // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 343750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343752 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 343754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 343758 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343760 */     GIR_RootConstrainSelectedInstOperands,
     /* 343761 */     // GIR_Coverage, 14366,
     /* 343761 */     GIR_EraseRootFromParent_Done,
     /* 343762 */   // Label 6824: @343762
     /* 343762 */   GIM_Try, /*On fail goto*//*Label 6825*/ GIMT_Encode4(343812), // Rule ID 690 //
     /* 343767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343770 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343774 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343778 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343782 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343786 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343791 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343795 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343797 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 343800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343802 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343804 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 343808 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343810 */     GIR_RootConstrainSelectedInstOperands,
     /* 343811 */     // GIR_Coverage, 690,
     /* 343811 */     GIR_EraseRootFromParent_Done,
     /* 343812 */   // Label 6825: @343812
     /* 343812 */   GIM_Try, /*On fail goto*//*Label 6826*/ GIMT_Encode4(343859), // Rule ID 14895 //
     /* 343817 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343821 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 343825 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343829 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343833 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343838 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343842 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343844 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 343847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343849 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 343853 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 343855 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 343857 */     GIR_RootConstrainSelectedInstOperands,
     /* 343858 */     // GIR_Coverage, 14895,
     /* 343858 */     GIR_EraseRootFromParent_Done,
     /* 343859 */   // Label 6826: @343859
     /* 343859 */   GIM_Try, /*On fail goto*//*Label 6827*/ GIMT_Encode4(343909), // Rule ID 702 //
     /* 343864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343867 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343871 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343875 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 343879 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343883 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 343887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343892 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 343894 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 343897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 343899 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 343901 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 343903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 343907 */     GIR_RootConstrainSelectedInstOperands,
     /* 343908 */     // GIR_Coverage, 702,
     /* 343908 */     GIR_EraseRootFromParent_Done,
     /* 343909 */   // Label 6827: @343909
     /* 343909 */   GIM_Try, /*On fail goto*//*Label 6828*/ GIMT_Encode4(343940), // Rule ID 684 //
     /* 343914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 343917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343929 */     // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 343929 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 343934 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 343938 */     GIR_RootConstrainSelectedInstOperands,
     /* 343939 */     // GIR_Coverage, 684,
     /* 343939 */     GIR_Done,
     /* 343940 */   // Label 6828: @343940
     /* 343940 */   GIM_Reject,
     /* 343941 */ // Label 6794: @343941
     /* 343941 */ GIM_Reject,
     /* 343942 */ // Label 6720: @343942
     /* 343942 */ GIM_Try, /*On fail goto*//*Label 6829*/ GIMT_Encode4(345462),
     /* 343947 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 343950 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 343953 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 343956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 343960 */   GIM_Try, /*On fail goto*//*Label 6830*/ GIMT_Encode4(344038), // Rule ID 6831 //
     /* 343965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 343969 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 343973 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 343977 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 343981 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 343985 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 343989 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 343993 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 343998 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 344002 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344006 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344010 */     // MIs[3] Operand 1
     /* 344010 */     // No operand predicates
     /* 344010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344014 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344018 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344020 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344020 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344023 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344025 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344027 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 344029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344033 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 344036 */     GIR_RootConstrainSelectedInstOperands,
     /* 344037 */     // GIR_Coverage, 6831,
     /* 344037 */     GIR_EraseRootFromParent_Done,
     /* 344038 */   // Label 6830: @344038
     /* 344038 */   GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(344122), // Rule ID 6747 //
     /* 344043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344054 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344058 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 344062 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344067 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 344071 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344075 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344079 */     // MIs[2] Operand 1
     /* 344079 */     // No operand predicates
     /* 344079 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 344083 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344087 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344091 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344096 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344100 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344102 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344107 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 344113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 344117 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 344120 */     GIR_RootConstrainSelectedInstOperands,
     /* 344121 */     // GIR_Coverage, 6747,
     /* 344121 */     GIR_EraseRootFromParent_Done,
     /* 344122 */   // Label 6831: @344122
     /* 344122 */   GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(344203), // Rule ID 6779 //
     /* 344127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344134 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344138 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344150 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344154 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 344158 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344163 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 344167 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344171 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344175 */     // MIs[3] Operand 1
     /* 344175 */     // No operand predicates
     /* 344175 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344179 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344183 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344185 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344190 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344192 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 344194 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344198 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 344201 */     GIR_RootConstrainSelectedInstOperands,
     /* 344202 */     // GIR_Coverage, 6779,
     /* 344202 */     GIR_EraseRootFromParent_Done,
     /* 344203 */   // Label 6832: @344203
     /* 344203 */   GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(344287), // Rule ID 6811 //
     /* 344208 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344211 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344215 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344219 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344223 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344228 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 344232 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344236 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344240 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 344244 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344249 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 344253 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344257 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344261 */     // MIs[3] Operand 1
     /* 344261 */     // No operand predicates
     /* 344261 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344265 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344267 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344270 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344272 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344274 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344282 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 344285 */     GIR_RootConstrainSelectedInstOperands,
     /* 344286 */     // GIR_Coverage, 6811,
     /* 344286 */     GIR_EraseRootFromParent_Done,
     /* 344287 */   // Label 6833: @344287
     /* 344287 */   GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(344365), // Rule ID 6853 //
     /* 344292 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344296 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 344300 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344304 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344308 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 344312 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344316 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344320 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344324 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344329 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 344333 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344337 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344341 */     // MIs[3] Operand 1
     /* 344341 */     // No operand predicates
     /* 344341 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344345 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344347 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344352 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344354 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 344356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344360 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 344363 */     GIR_RootConstrainSelectedInstOperands,
     /* 344364 */     // GIR_Coverage, 6853,
     /* 344364 */     GIR_EraseRootFromParent_Done,
     /* 344365 */   // Label 6834: @344365
     /* 344365 */   GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(344446), // Rule ID 6715 //
     /* 344370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344373 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344377 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 344381 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344385 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344389 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344393 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344397 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344401 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 344405 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344410 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 344414 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344418 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344422 */     // MIs[3] Operand 1
     /* 344422 */     // No operand predicates
     /* 344422 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344426 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 344428 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344433 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344435 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 344437 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344441 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 344444 */     GIR_RootConstrainSelectedInstOperands,
     /* 344445 */     // GIR_Coverage, 6715,
     /* 344445 */     GIR_EraseRootFromParent_Done,
     /* 344446 */   // Label 6835: @344446
     /* 344446 */   GIM_Try, /*On fail goto*//*Label 6836*/ GIMT_Encode4(344515), // Rule ID 2574 //
     /* 344451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344466 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 344470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344475 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 344479 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344483 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344487 */     // MIs[2] Operand 1
     /* 344487 */     // No operand predicates
     /* 344487 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344491 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344495 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344497 */     // (fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 344500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344502 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344504 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 344506 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 344510 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 344513 */     GIR_RootConstrainSelectedInstOperands,
     /* 344514 */     // GIR_Coverage, 2574,
     /* 344514 */     GIR_EraseRootFromParent_Done,
     /* 344515 */   // Label 6836: @344515
     /* 344515 */   GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(344584), // Rule ID 6683 //
     /* 344520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 344531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 344535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 344539 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 344543 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344548 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 344552 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 344556 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 344560 */     // MIs[2] Operand 1
     /* 344560 */     // No operand predicates
     /* 344560 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344564 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344566 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 344566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 344569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344571 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344573 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 344575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 344579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 344582 */     GIR_RootConstrainSelectedInstOperands,
     /* 344583 */     // GIR_Coverage, 6683,
     /* 344583 */     GIR_EraseRootFromParent_Done,
     /* 344584 */   // Label 6837: @344584
     /* 344584 */   GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(344677), // Rule ID 6835 //
     /* 344589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 344597 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 344601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344609 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 344613 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344618 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344622 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344626 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344628 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 344628 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 344631 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 344635 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344640 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 344643 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344647 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 344650 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344655 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344665 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344667 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 344669 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 344672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 344675 */     GIR_RootConstrainSelectedInstOperands,
     /* 344676 */     // GIR_Coverage, 6835,
     /* 344676 */     GIR_EraseRootFromParent_Done,
     /* 344677 */   // Label 6838: @344677
     /* 344677 */   GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(344776), // Rule ID 6749 //
     /* 344682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344685 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344689 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 344693 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 344697 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 344706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344710 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344714 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344719 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344723 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344725 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 344725 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 344728 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 344732 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344737 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 344740 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 344744 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 344747 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344752 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344757 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344760 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344762 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344764 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 344768 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 344771 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 344774 */     GIR_RootConstrainSelectedInstOperands,
     /* 344775 */     // GIR_Coverage, 6749,
     /* 344775 */     GIR_EraseRootFromParent_Done,
     /* 344776 */   // Label 6839: @344776
     /* 344776 */   GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(344872), // Rule ID 6781 //
     /* 344781 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344796 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344800 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 344804 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 344808 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344813 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344817 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344821 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344823 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 344823 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 344826 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 344830 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344835 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 344838 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344842 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 344845 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344850 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344855 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344858 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344860 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344862 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 344864 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 344867 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 344870 */     GIR_RootConstrainSelectedInstOperands,
     /* 344871 */     // GIR_Coverage, 6781,
     /* 344871 */     GIR_EraseRootFromParent_Done,
     /* 344872 */   // Label 6840: @344872
     /* 344872 */   GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(344971), // Rule ID 6813 //
     /* 344877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 344880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 344884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 344888 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 344892 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344897 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 344901 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 344905 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 344909 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344914 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344918 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 344920 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 344920 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 344923 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 344927 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 344932 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 344935 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 344939 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 344942 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 344947 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 344952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 344955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 344957 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 344959 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 344963 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 344966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 344969 */     GIR_RootConstrainSelectedInstOperands,
     /* 344970 */     // GIR_Coverage, 6813,
     /* 344970 */     GIR_EraseRootFromParent_Done,
     /* 344971 */   // Label 6841: @344971
     /* 344971 */   GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(345064), // Rule ID 6857 //
     /* 344976 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 344980 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 344984 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 344988 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 344992 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 344996 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345000 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 345004 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345009 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345013 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 345015 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 345015 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 345018 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 345022 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 345027 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 345030 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345034 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 345037 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345042 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345047 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 345050 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345052 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345054 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 345059 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 345062 */     GIR_RootConstrainSelectedInstOperands,
     /* 345063 */     // GIR_Coverage, 6857,
     /* 345063 */     GIR_EraseRootFromParent_Done,
     /* 345064 */   // Label 6842: @345064
     /* 345064 */   GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(345160), // Rule ID 6717 //
     /* 345069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345072 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 345080 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345084 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345088 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 345092 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 345096 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 345100 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345105 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345109 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 345111 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 345111 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 345114 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 345118 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 345123 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 345126 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345130 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 345133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345138 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 345146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345148 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345150 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345152 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 345155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 345158 */     GIR_RootConstrainSelectedInstOperands,
     /* 345159 */     // GIR_Coverage, 6717,
     /* 345159 */     GIR_EraseRootFromParent_Done,
     /* 345160 */   // Label 6843: @345160
     /* 345160 */   GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(345244), // Rule ID 2576 //
     /* 345165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 345176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 345180 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345189 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345193 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 345195 */     // (fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 345195 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 345198 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 345202 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 345207 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 345210 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 345214 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 345217 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345222 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345227 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 345230 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345232 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345234 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 345236 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 345239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 345242 */     GIR_RootConstrainSelectedInstOperands,
     /* 345243 */     // GIR_Coverage, 2576,
     /* 345243 */     GIR_EraseRootFromParent_Done,
     /* 345244 */   // Label 6844: @345244
     /* 345244 */   GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(345294), // Rule ID 14396 //
     /* 345249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345252 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345256 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345260 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345264 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345269 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345273 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345277 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 345279 */     // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 345279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 345282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345284 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345286 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 345288 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 345292 */     GIR_RootConstrainSelectedInstOperands,
     /* 345293 */     // GIR_Coverage, 14396,
     /* 345293 */     GIR_EraseRootFromParent_Done,
     /* 345294 */   // Label 6845: @345294
     /* 345294 */   GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(345378), // Rule ID 6685 //
     /* 345299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345302 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 345310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 345314 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 345318 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345323 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345327 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 345329 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 345329 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 345332 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 345336 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 345341 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 345344 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 345348 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 345351 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345356 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 345361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 345364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345366 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345368 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345370 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 345373 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 345376 */     GIR_RootConstrainSelectedInstOperands,
     /* 345377 */     // GIR_Coverage, 6685,
     /* 345377 */     GIR_EraseRootFromParent_Done,
     /* 345378 */   // Label 6846: @345378
     /* 345378 */   GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(345428), // Rule ID 1338 //
     /* 345383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345386 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 345394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345398 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 345402 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345407 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345411 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 345413 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 345413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 345416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345418 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345420 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345422 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 345426 */     GIR_RootConstrainSelectedInstOperands,
     /* 345427 */     // GIR_Coverage, 1338,
     /* 345427 */     GIR_EraseRootFromParent_Done,
     /* 345428 */   // Label 6847: @345428
     /* 345428 */   GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(345461), // Rule ID 1328 //
     /* 345433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345436 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345444 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 345448 */     // (fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 345448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
     /* 345451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345453 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 345457 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 345459 */     GIR_RootConstrainSelectedInstOperands,
     /* 345460 */     // GIR_Coverage, 1328,
     /* 345460 */     GIR_EraseRootFromParent_Done,
     /* 345461 */   // Label 6848: @345461
     /* 345461 */   GIM_Reject,
     /* 345462 */ // Label 6829: @345462
     /* 345462 */ GIM_Reject,
     /* 345463 */ // Label 6721: @345463
     /* 345463 */ GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(346983),
     /* 345468 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345471 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 345474 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 345477 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345481 */   GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(345559), // Rule ID 6843 //
     /* 345486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345498 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 345502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 345506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345510 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345514 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345519 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 345523 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345527 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345531 */     // MIs[3] Operand 1
     /* 345531 */     // No operand predicates
     /* 345531 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345535 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345539 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345541 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345546 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345548 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 345550 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345554 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 345557 */     GIR_RootConstrainSelectedInstOperands,
     /* 345558 */     // GIR_Coverage, 6843,
     /* 345558 */     GIR_EraseRootFromParent_Done,
     /* 345559 */   // Label 6850: @345559
     /* 345559 */   GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(345643), // Rule ID 6755 //
     /* 345564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345579 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 345583 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 345592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345596 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345600 */     // MIs[2] Operand 1
     /* 345600 */     // No operand predicates
     /* 345600 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 345604 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345608 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345612 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345617 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345621 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345623 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345628 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345630 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 345634 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 345638 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 345641 */     GIR_RootConstrainSelectedInstOperands,
     /* 345642 */     // GIR_Coverage, 6755,
     /* 345642 */     GIR_EraseRootFromParent_Done,
     /* 345643 */   // Label 6851: @345643
     /* 345643 */   GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(345724), // Rule ID 6787 //
     /* 345648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345663 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 345667 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345671 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345675 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 345679 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345684 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 345688 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345692 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345696 */     // MIs[3] Operand 1
     /* 345696 */     // No operand predicates
     /* 345696 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345700 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345704 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345706 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345711 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345713 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 345715 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345719 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 345722 */     GIR_RootConstrainSelectedInstOperands,
     /* 345723 */     // GIR_Coverage, 6787,
     /* 345723 */     GIR_EraseRootFromParent_Done,
     /* 345724 */   // Label 6852: @345724
     /* 345724 */   GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(345808), // Rule ID 6819 //
     /* 345729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345740 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345744 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345749 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 345753 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345757 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345761 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 345765 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345770 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 345774 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345778 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345782 */     // MIs[3] Operand 1
     /* 345782 */     // No operand predicates
     /* 345782 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345786 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345788 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345793 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 345799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345803 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 345806 */     GIR_RootConstrainSelectedInstOperands,
     /* 345807 */     // GIR_Coverage, 6819,
     /* 345807 */     GIR_EraseRootFromParent_Done,
     /* 345808 */   // Label 6853: @345808
     /* 345808 */   GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(345886), // Rule ID 6865 //
     /* 345813 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345817 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 345821 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345825 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345829 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 345833 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 345837 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345841 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345845 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345850 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 345854 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345858 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345862 */     // MIs[3] Operand 1
     /* 345862 */     // No operand predicates
     /* 345862 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345866 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345868 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345873 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345875 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345881 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 345884 */     GIR_RootConstrainSelectedInstOperands,
     /* 345885 */     // GIR_Coverage, 6865,
     /* 345885 */     GIR_EraseRootFromParent_Done,
     /* 345886 */   // Label 6854: @345886
     /* 345886 */   GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(345967), // Rule ID 6723 //
     /* 345891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345894 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 345902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 345906 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345910 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 345914 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345918 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345922 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 345926 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345931 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 345935 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 345939 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 345943 */     // MIs[3] Operand 1
     /* 345943 */     // No operand predicates
     /* 345943 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345947 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 345949 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 345949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 345952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 345954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 345956 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 345958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 345962 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 345965 */     GIR_RootConstrainSelectedInstOperands,
     /* 345966 */     // GIR_Coverage, 6723,
     /* 345966 */     GIR_EraseRootFromParent_Done,
     /* 345967 */   // Label 6855: @345967
     /* 345967 */   GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(346036), // Rule ID 2582 //
     /* 345972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 345975 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 345979 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 345983 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 345987 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 345991 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 345996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 346000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 346004 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 346008 */     // MIs[2] Operand 1
     /* 346008 */     // No operand predicates
     /* 346008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346012 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346016 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346018 */     // (fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 346018 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 346021 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346023 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346025 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346027 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346031 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 346034 */     GIR_RootConstrainSelectedInstOperands,
     /* 346035 */     // GIR_Coverage, 2582,
     /* 346035 */     GIR_EraseRootFromParent_Done,
     /* 346036 */   // Label 6856: @346036
     /* 346036 */   GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(346105), // Rule ID 6691 //
     /* 346041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346044 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346048 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 346052 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 346056 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346060 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 346064 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346069 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 346073 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 346077 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 346081 */     // MIs[2] Operand 1
     /* 346081 */     // No operand predicates
     /* 346081 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346085 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346087 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 346087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 346090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346092 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346094 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 346096 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346100 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 346103 */     GIR_RootConstrainSelectedInstOperands,
     /* 346104 */     // GIR_Coverage, 6691,
     /* 346104 */     GIR_EraseRootFromParent_Done,
     /* 346105 */   // Label 6857: @346105
     /* 346105 */   GIM_Try, /*On fail goto*//*Label 6858*/ GIMT_Encode4(346198), // Rule ID 6845 //
     /* 346110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 346118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 346122 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 346126 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346130 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 346134 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346143 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346147 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346149 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346149 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346152 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346156 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346161 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346164 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 346168 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346171 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346176 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346186 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346188 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346190 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346196 */     GIR_RootConstrainSelectedInstOperands,
     /* 346197 */     // GIR_Coverage, 6845,
     /* 346197 */     GIR_EraseRootFromParent_Done,
     /* 346198 */   // Label 6858: @346198
     /* 346198 */   GIM_Try, /*On fail goto*//*Label 6859*/ GIMT_Encode4(346297), // Rule ID 6757 //
     /* 346203 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 346214 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 346218 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 346227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346231 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346235 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346240 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346244 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346246 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346246 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346249 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346253 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346258 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346261 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346265 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346268 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346273 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346283 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346285 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 346289 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346292 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346295 */     GIR_RootConstrainSelectedInstOperands,
     /* 346296 */     // GIR_Coverage, 6757,
     /* 346296 */     GIR_EraseRootFromParent_Done,
     /* 346297 */   // Label 6859: @346297
     /* 346297 */   GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(346393), // Rule ID 6789 //
     /* 346302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346305 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346309 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346313 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346317 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 346321 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 346325 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 346329 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346334 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346338 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346342 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346344 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346344 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346347 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346351 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346356 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346359 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 346363 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346366 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346371 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346383 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346385 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346388 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346391 */     GIR_RootConstrainSelectedInstOperands,
     /* 346392 */     // GIR_Coverage, 6789,
     /* 346392 */     GIR_EraseRootFromParent_Done,
     /* 346393 */   // Label 6860: @346393
     /* 346393 */   GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(346492), // Rule ID 6821 //
     /* 346398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346409 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346413 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346418 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 346422 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 346426 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 346430 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346435 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346439 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346441 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346441 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346444 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346448 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346453 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346456 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 346460 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346463 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346468 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346478 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346480 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 346484 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346487 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346490 */     GIR_RootConstrainSelectedInstOperands,
     /* 346491 */     // GIR_Coverage, 6821,
     /* 346491 */     GIR_EraseRootFromParent_Done,
     /* 346492 */   // Label 6861: @346492
     /* 346492 */   GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(346585), // Rule ID 6867 //
     /* 346497 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 346505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 346509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 346513 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 346517 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346521 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 346525 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346530 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346534 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346536 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346536 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346539 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346543 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346548 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346551 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 346555 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346558 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346563 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346575 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 346577 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346580 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346583 */     GIR_RootConstrainSelectedInstOperands,
     /* 346584 */     // GIR_Coverage, 6867,
     /* 346584 */     GIR_EraseRootFromParent_Done,
     /* 346585 */   // Label 6862: @346585
     /* 346585 */   GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(346681), // Rule ID 6725 //
     /* 346590 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346593 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346597 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 346601 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346605 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 346613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 346617 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 346621 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346626 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346630 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 346632 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346632 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346635 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346639 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346644 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346647 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 346651 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346654 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346659 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 346667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346669 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346671 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 346673 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346676 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346679 */     GIR_RootConstrainSelectedInstOperands,
     /* 346680 */     // GIR_Coverage, 6725,
     /* 346680 */     GIR_EraseRootFromParent_Done,
     /* 346681 */   // Label 6863: @346681
     /* 346681 */   GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(346765), // Rule ID 2584 //
     /* 346686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346689 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346693 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 346697 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 346701 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346706 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346710 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346714 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 346716 */     // (fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346716 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346719 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346723 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346728 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346731 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346735 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346738 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346743 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346748 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 346751 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346753 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346755 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346757 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346760 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346763 */     GIR_RootConstrainSelectedInstOperands,
     /* 346764 */     // GIR_Coverage, 2584,
     /* 346764 */     GIR_EraseRootFromParent_Done,
     /* 346765 */   // Label 6864: @346765
     /* 346765 */   GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(346815), // Rule ID 14400 //
     /* 346770 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346773 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 346777 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346781 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346785 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346790 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346794 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346798 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 346800 */     // (fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 346800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 346803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346805 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346807 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346809 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346813 */     GIR_RootConstrainSelectedInstOperands,
     /* 346814 */     // GIR_Coverage, 14400,
     /* 346814 */     GIR_EraseRootFromParent_Done,
     /* 346815 */   // Label 6865: @346815
     /* 346815 */   GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(346899), // Rule ID 6693 //
     /* 346820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346823 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346827 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 346831 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 346835 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 346839 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346848 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 346850 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 346850 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 346853 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 346857 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 346862 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 346865 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346869 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 346872 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346877 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 346882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 346885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346887 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346889 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 346891 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 346894 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 346897 */     GIR_RootConstrainSelectedInstOperands,
     /* 346898 */     // GIR_Coverage, 6693,
     /* 346898 */     GIR_EraseRootFromParent_Done,
     /* 346899 */   // Label 6866: @346899
     /* 346899 */   GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(346949), // Rule ID 1342 //
     /* 346904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346907 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 346915 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 346919 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 346923 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346928 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346932 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 346934 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 346934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 346937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346939 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346941 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 346943 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 346947 */     GIR_RootConstrainSelectedInstOperands,
     /* 346948 */     // GIR_Coverage, 1342,
     /* 346948 */     GIR_EraseRootFromParent_Done,
     /* 346949 */   // Label 6867: @346949
     /* 346949 */   GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(346982), // Rule ID 1332 //
     /* 346954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 346957 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346961 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346965 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 346969 */     // (fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 346969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
     /* 346972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 346974 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 346976 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 346978 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 346980 */     GIR_RootConstrainSelectedInstOperands,
     /* 346981 */     // GIR_Coverage, 1332,
     /* 346981 */     GIR_EraseRootFromParent_Done,
     /* 346982 */   // Label 6868: @346982
     /* 346982 */   GIM_Reject,
     /* 346983 */ // Label 6849: @346983
     /* 346983 */ GIM_Reject,
     /* 346984 */ // Label 6722: @346984
     /* 346984 */ GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(348162),
     /* 346989 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 346992 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 346995 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 346998 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347002 */   GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(347086), // Rule ID 6739 //
     /* 347007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347018 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347022 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 347026 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347031 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 347035 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347039 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347043 */     // MIs[2] Operand 1
     /* 347043 */     // No operand predicates
     /* 347043 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 347047 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347051 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347055 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347060 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347064 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 347066 */     // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347071 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347073 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 347077 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347081 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 347084 */     GIR_RootConstrainSelectedInstOperands,
     /* 347085 */     // GIR_Coverage, 6739,
     /* 347085 */     GIR_EraseRootFromParent_Done,
     /* 347086 */   // Label 6870: @347086
     /* 347086 */   GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(347167), // Rule ID 6771 //
     /* 347091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347094 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347098 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347102 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347106 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 347110 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347114 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347118 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 347122 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347127 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 347131 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347135 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347139 */     // MIs[3] Operand 1
     /* 347139 */     // No operand predicates
     /* 347139 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347143 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347147 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 347149 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347154 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347156 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 347158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347162 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 347165 */     GIR_RootConstrainSelectedInstOperands,
     /* 347166 */     // GIR_Coverage, 6771,
     /* 347166 */     GIR_EraseRootFromParent_Done,
     /* 347167 */   // Label 6871: @347167
     /* 347167 */   GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(347251), // Rule ID 6803 //
     /* 347172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347175 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347179 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347183 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347187 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347192 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347196 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347200 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347204 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 347208 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347213 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 347217 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347221 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347225 */     // MIs[3] Operand 1
     /* 347225 */     // No operand predicates
     /* 347225 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347229 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 347231 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347236 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347246 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 347249 */     GIR_RootConstrainSelectedInstOperands,
     /* 347250 */     // GIR_Coverage, 6803,
     /* 347250 */     GIR_EraseRootFromParent_Done,
     /* 347251 */   // Label 6872: @347251
     /* 347251 */   GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(347332), // Rule ID 6707 //
     /* 347256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347259 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 347267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347271 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347275 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 347279 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347283 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347287 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 347291 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347296 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 347300 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347304 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347308 */     // MIs[3] Operand 1
     /* 347308 */     // No operand predicates
     /* 347308 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347312 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 347314 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347314 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347317 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347319 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347321 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 347323 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347327 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 347330 */     GIR_RootConstrainSelectedInstOperands,
     /* 347331 */     // GIR_Coverage, 6707,
     /* 347331 */     GIR_EraseRootFromParent_Done,
     /* 347332 */   // Label 6873: @347332
     /* 347332 */   GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(347401), // Rule ID 2566 //
     /* 347337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347348 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347352 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 347356 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347361 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 347365 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347369 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347373 */     // MIs[2] Operand 1
     /* 347373 */     // No operand predicates
     /* 347373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347377 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347381 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347383 */     // (fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347383 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 347386 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347388 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347390 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 347392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347396 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 347399 */     GIR_RootConstrainSelectedInstOperands,
     /* 347400 */     // GIR_Coverage, 2566,
     /* 347400 */     GIR_EraseRootFromParent_Done,
     /* 347401 */   // Label 6874: @347401
     /* 347401 */   GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(347470), // Rule ID 6675 //
     /* 347406 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347409 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347413 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 347417 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 347421 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 347425 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 347429 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 347434 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 347438 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 347442 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 347446 */     // MIs[2] Operand 1
     /* 347446 */     // No operand predicates
     /* 347446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347450 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347452 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 347452 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 347455 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347457 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347459 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 347461 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347465 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 347468 */     GIR_RootConstrainSelectedInstOperands,
     /* 347469 */     // GIR_Coverage, 6675,
     /* 347469 */     GIR_EraseRootFromParent_Done,
     /* 347470 */   // Label 6875: @347470
     /* 347470 */   GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(347569), // Rule ID 6741 //
     /* 347475 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347482 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 347486 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 347490 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347495 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347499 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347503 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347507 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347512 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347516 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347518 */     // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 347518 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 347521 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 347525 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 347530 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 347533 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347537 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 347540 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347545 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347555 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347557 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 347561 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 347564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 347567 */     GIR_RootConstrainSelectedInstOperands,
     /* 347568 */     // GIR_Coverage, 6741,
     /* 347568 */     GIR_EraseRootFromParent_Done,
     /* 347569 */   // Label 6876: @347569
     /* 347569 */   GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(347665), // Rule ID 6773 //
     /* 347574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347589 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 347593 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 347597 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 347601 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347606 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347610 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347614 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347616 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 347616 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 347619 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 347623 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 347628 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 347631 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347635 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 347638 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347643 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347648 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347651 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347653 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347655 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 347657 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 347660 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 347663 */     GIR_RootConstrainSelectedInstOperands,
     /* 347664 */     // GIR_Coverage, 6773,
     /* 347664 */     GIR_EraseRootFromParent_Done,
     /* 347665 */   // Label 6877: @347665
     /* 347665 */   GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(347764), // Rule ID 6805 //
     /* 347670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347673 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347677 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347681 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347685 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 347694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 347698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 347702 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347707 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347711 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347713 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 347713 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 347716 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 347720 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 347725 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 347728 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347732 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 347735 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347740 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347750 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 347756 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 347759 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 347762 */     GIR_RootConstrainSelectedInstOperands,
     /* 347763 */     // GIR_Coverage, 6805,
     /* 347763 */     GIR_EraseRootFromParent_Done,
     /* 347764 */   // Label 6878: @347764
     /* 347764 */   GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(347860), // Rule ID 6709 //
     /* 347769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347772 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 347780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347784 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347788 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 347792 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 347796 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 347800 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347805 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347809 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 347811 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 347811 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 347814 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 347818 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 347823 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 347826 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 347830 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 347833 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347838 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347843 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 347846 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347850 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 347852 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 347855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 347858 */     GIR_RootConstrainSelectedInstOperands,
     /* 347859 */     // GIR_Coverage, 6709,
     /* 347859 */     GIR_EraseRootFromParent_Done,
     /* 347860 */   // Label 6879: @347860
     /* 347860 */   GIM_Try, /*On fail goto*//*Label 6880*/ GIMT_Encode4(347944), // Rule ID 2568 //
     /* 347865 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347868 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347872 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 347876 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 347880 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347885 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347889 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347893 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 347895 */     // (fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 347895 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 347898 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 347902 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 347907 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 347910 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347914 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 347917 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 347922 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 347927 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 347930 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347932 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347934 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 347936 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 347939 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 347942 */     GIR_RootConstrainSelectedInstOperands,
     /* 347943 */     // GIR_Coverage, 2568,
     /* 347943 */     GIR_EraseRootFromParent_Done,
     /* 347944 */   // Label 6880: @347944
     /* 347944 */   GIM_Try, /*On fail goto*//*Label 6881*/ GIMT_Encode4(347994), // Rule ID 14392 //
     /* 347949 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 347952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 347956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 347960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 347964 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347969 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347973 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 347977 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 347979 */     // (fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 347979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 347982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 347984 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 347986 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 347988 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 347992 */     GIR_RootConstrainSelectedInstOperands,
     /* 347993 */     // GIR_Coverage, 14392,
     /* 347993 */     GIR_EraseRootFromParent_Done,
     /* 347994 */   // Label 6881: @347994
     /* 347994 */   GIM_Try, /*On fail goto*//*Label 6882*/ GIMT_Encode4(348078), // Rule ID 6677 //
     /* 347999 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 348002 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 348014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 348018 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 348023 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348027 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348029 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 348029 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 348032 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 348036 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 348041 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 348044 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348048 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 348051 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348056 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 348061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 348064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348068 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348070 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 348073 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 348076 */     GIR_RootConstrainSelectedInstOperands,
     /* 348077 */     // GIR_Coverage, 6677,
     /* 348077 */     GIR_EraseRootFromParent_Done,
     /* 348078 */   // Label 6882: @348078
     /* 348078 */   GIM_Try, /*On fail goto*//*Label 6883*/ GIMT_Encode4(348128), // Rule ID 1334 //
     /* 348083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 348086 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348090 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348094 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348098 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 348102 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348107 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348111 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 348113 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 348113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 348116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348118 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348120 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348122 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348126 */     GIR_RootConstrainSelectedInstOperands,
     /* 348127 */     // GIR_Coverage, 1334,
     /* 348127 */     GIR_EraseRootFromParent_Done,
     /* 348128 */   // Label 6883: @348128
     /* 348128 */   GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(348161), // Rule ID 1324 //
     /* 348133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 348136 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348144 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 348148 */     // (fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 348148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
     /* 348151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 348157 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 348159 */     GIR_RootConstrainSelectedInstOperands,
     /* 348160 */     // GIR_Coverage, 1324,
     /* 348160 */     GIR_EraseRootFromParent_Done,
     /* 348161 */   // Label 6884: @348161
     /* 348161 */   GIM_Reject,
     /* 348162 */ // Label 6869: @348162
     /* 348162 */ GIM_Reject,
     /* 348163 */ // Label 6723: @348163
     /* 348163 */ GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(349683),
     /* 348168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348171 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 348174 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 348177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348181 */   GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(348259), // Rule ID 6837 //
     /* 348186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348198 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348202 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348206 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348210 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348214 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348219 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 348223 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348227 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348231 */     // MIs[3] Operand 1
     /* 348231 */     // No operand predicates
     /* 348231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348235 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348239 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348241 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348246 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348248 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 348250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348254 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 348257 */     GIR_RootConstrainSelectedInstOperands,
     /* 348258 */     // GIR_Coverage, 6837,
     /* 348258 */     GIR_EraseRootFromParent_Done,
     /* 348259 */   // Label 6886: @348259
     /* 348259 */   GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(348343), // Rule ID 6751 //
     /* 348264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348288 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348292 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348296 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348300 */     // MIs[2] Operand 1
     /* 348300 */     // No operand predicates
     /* 348300 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 348304 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348308 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348312 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348317 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348321 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348323 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348328 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348330 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 348334 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348338 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 348341 */     GIR_RootConstrainSelectedInstOperands,
     /* 348342 */     // GIR_Coverage, 6751,
     /* 348342 */     GIR_EraseRootFromParent_Done,
     /* 348343 */   // Label 6887: @348343
     /* 348343 */   GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(348424), // Rule ID 6783 //
     /* 348348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348363 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348367 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348371 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348375 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348379 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348384 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 348388 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348392 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348396 */     // MIs[3] Operand 1
     /* 348396 */     // No operand predicates
     /* 348396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348400 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348404 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348406 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348411 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348413 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 348415 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348419 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 348422 */     GIR_RootConstrainSelectedInstOperands,
     /* 348423 */     // GIR_Coverage, 6783,
     /* 348423 */     GIR_EraseRootFromParent_Done,
     /* 348424 */   // Label 6888: @348424
     /* 348424 */   GIM_Try, /*On fail goto*//*Label 6889*/ GIMT_Encode4(348508), // Rule ID 6815 //
     /* 348429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348440 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348444 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 348453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348457 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348461 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348465 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348470 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 348474 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348478 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348482 */     // MIs[3] Operand 1
     /* 348482 */     // No operand predicates
     /* 348482 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348486 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348488 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348493 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 348499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348503 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 348506 */     GIR_RootConstrainSelectedInstOperands,
     /* 348507 */     // GIR_Coverage, 6815,
     /* 348507 */     GIR_EraseRootFromParent_Done,
     /* 348508 */   // Label 6889: @348508
     /* 348508 */   GIM_Try, /*On fail goto*//*Label 6890*/ GIMT_Encode4(348586), // Rule ID 6859 //
     /* 348513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348533 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348537 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348541 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348545 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348550 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 348554 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348558 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348562 */     // MIs[3] Operand 1
     /* 348562 */     // No operand predicates
     /* 348562 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348566 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348568 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348573 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348575 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348577 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348581 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 348584 */     GIR_RootConstrainSelectedInstOperands,
     /* 348585 */     // GIR_Coverage, 6859,
     /* 348585 */     GIR_EraseRootFromParent_Done,
     /* 348586 */   // Label 6890: @348586
     /* 348586 */   GIM_Try, /*On fail goto*//*Label 6891*/ GIMT_Encode4(348667), // Rule ID 6719 //
     /* 348591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348610 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348614 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348618 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348622 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 348626 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348631 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 348635 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348639 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348643 */     // MIs[3] Operand 1
     /* 348643 */     // No operand predicates
     /* 348643 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348647 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 348649 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348656 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348658 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348662 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 348665 */     GIR_RootConstrainSelectedInstOperands,
     /* 348666 */     // GIR_Coverage, 6719,
     /* 348666 */     GIR_EraseRootFromParent_Done,
     /* 348667 */   // Label 6891: @348667
     /* 348667 */   GIM_Try, /*On fail goto*//*Label 6892*/ GIMT_Encode4(348736), // Rule ID 2578 //
     /* 348672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348683 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348687 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348691 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348696 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348700 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348704 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348708 */     // MIs[2] Operand 1
     /* 348708 */     // No operand predicates
     /* 348708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348712 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348716 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348718 */     // (fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 348721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348723 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348725 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 348727 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348731 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 348734 */     GIR_RootConstrainSelectedInstOperands,
     /* 348735 */     // GIR_Coverage, 2578,
     /* 348735 */     GIR_EraseRootFromParent_Done,
     /* 348736 */   // Label 6892: @348736
     /* 348736 */   GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(348805), // Rule ID 6687 //
     /* 348741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348744 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 348752 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 348756 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348760 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 348764 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348769 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 348773 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 348777 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 348781 */     // MIs[2] Operand 1
     /* 348781 */     // No operand predicates
     /* 348781 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348785 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348787 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 348787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 348790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348792 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348794 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 348796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348800 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 348803 */     GIR_RootConstrainSelectedInstOperands,
     /* 348804 */     // GIR_Coverage, 6687,
     /* 348804 */     GIR_EraseRootFromParent_Done,
     /* 348805 */   // Label 6893: @348805
     /* 348805 */   GIM_Try, /*On fail goto*//*Label 6894*/ GIMT_Encode4(348898), // Rule ID 6841 //
     /* 348810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 348818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 348822 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 348826 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348830 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 348834 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 348839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348847 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348849 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 348849 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 348852 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 348856 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 348861 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 348864 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 348868 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 348871 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348876 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 348881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348886 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348888 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 348890 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 348893 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 348896 */     GIR_RootConstrainSelectedInstOperands,
     /* 348897 */     // GIR_Coverage, 6841,
     /* 348897 */     GIR_EraseRootFromParent_Done,
     /* 348898 */   // Label 6894: @348898
     /* 348898 */   GIM_Try, /*On fail goto*//*Label 6895*/ GIMT_Encode4(348997), // Rule ID 6753 //
     /* 348903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 348906 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 348910 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 348914 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 348918 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 348923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 348927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 348931 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 348935 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348940 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348944 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 348946 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 348946 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 348949 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 348953 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 348958 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 348961 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 348965 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 348968 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 348973 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 348978 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 348981 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 348983 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 348985 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 348989 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 348992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 348995 */     GIR_RootConstrainSelectedInstOperands,
     /* 348996 */     // GIR_Coverage, 6753,
     /* 348996 */     GIR_EraseRootFromParent_Done,
     /* 348997 */   // Label 6895: @348997
     /* 348997 */   GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(349093), // Rule ID 6785 //
     /* 349002 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349005 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349009 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349013 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349017 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 349021 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 349025 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 349029 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349034 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349038 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349042 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 349044 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349044 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349047 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349051 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349056 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349059 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349063 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349066 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349071 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 349079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349081 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349083 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 349085 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349088 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349091 */     GIR_RootConstrainSelectedInstOperands,
     /* 349092 */     // GIR_Coverage, 6785,
     /* 349092 */     GIR_EraseRootFromParent_Done,
     /* 349093 */   // Label 6896: @349093
     /* 349093 */   GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(349192), // Rule ID 6817 //
     /* 349098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349101 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349105 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349109 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349113 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349118 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 349122 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 349126 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 349130 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349135 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349139 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 349141 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349141 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349144 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349148 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349153 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349156 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349160 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349163 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349168 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 349176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349178 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349180 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 349184 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349190 */     GIR_RootConstrainSelectedInstOperands,
     /* 349191 */     // GIR_Coverage, 6817,
     /* 349191 */     GIR_EraseRootFromParent_Done,
     /* 349192 */   // Label 6897: @349192
     /* 349192 */   GIM_Try, /*On fail goto*//*Label 6898*/ GIMT_Encode4(349285), // Rule ID 6863 //
     /* 349197 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349201 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349205 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 349209 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 349213 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 349217 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349221 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 349225 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349230 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349234 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 349236 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349236 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349239 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349243 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349248 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349251 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349255 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349258 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349263 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349268 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 349271 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349273 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349275 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349277 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349280 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349283 */     GIR_RootConstrainSelectedInstOperands,
     /* 349284 */     // GIR_Coverage, 6863,
     /* 349284 */     GIR_EraseRootFromParent_Done,
     /* 349285 */   // Label 6898: @349285
     /* 349285 */   GIM_Try, /*On fail goto*//*Label 6899*/ GIMT_Encode4(349381), // Rule ID 6721 //
     /* 349290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349293 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349297 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349301 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349305 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349309 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 349313 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 349317 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 349321 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349326 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349330 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 349332 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349332 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349335 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349339 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349344 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349347 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349351 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349354 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349359 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 349367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349369 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349371 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349373 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349379 */     GIR_RootConstrainSelectedInstOperands,
     /* 349380 */     // GIR_Coverage, 6721,
     /* 349380 */     GIR_EraseRootFromParent_Done,
     /* 349381 */   // Label 6899: @349381
     /* 349381 */   GIM_Try, /*On fail goto*//*Label 6900*/ GIMT_Encode4(349465), // Rule ID 2580 //
     /* 349386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 349397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 349401 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349410 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349414 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349416 */     // (fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349416 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349419 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349423 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349428 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349431 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 349435 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349438 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349448 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 349451 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349453 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349455 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 349457 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349463 */     GIR_RootConstrainSelectedInstOperands,
     /* 349464 */     // GIR_Coverage, 2580,
     /* 349464 */     GIR_EraseRootFromParent_Done,
     /* 349465 */   // Label 6900: @349465
     /* 349465 */   GIM_Try, /*On fail goto*//*Label 6901*/ GIMT_Encode4(349515), // Rule ID 14398 //
     /* 349470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349473 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349477 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349481 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349485 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349490 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349494 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349498 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349500 */     // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 349500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 349503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349507 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 349509 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 349513 */     GIR_RootConstrainSelectedInstOperands,
     /* 349514 */     // GIR_Coverage, 14398,
     /* 349514 */     GIR_EraseRootFromParent_Done,
     /* 349515 */   // Label 6901: @349515
     /* 349515 */   GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(349599), // Rule ID 6689 //
     /* 349520 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349523 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349527 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349531 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 349535 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 349539 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349544 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349548 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349550 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 349550 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 349553 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 349557 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 349562 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 349565 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 349569 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 349572 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349577 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 349582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 349585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349587 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349589 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349591 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 349594 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 349597 */     GIR_RootConstrainSelectedInstOperands,
     /* 349598 */     // GIR_Coverage, 6689,
     /* 349598 */     GIR_EraseRootFromParent_Done,
     /* 349599 */   // Label 6902: @349599
     /* 349599 */   GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(349649), // Rule ID 1340 //
     /* 349604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349607 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349611 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349615 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349619 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 349623 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349628 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349632 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 349634 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 349634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 349637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349639 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349641 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 349643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 349647 */     GIR_RootConstrainSelectedInstOperands,
     /* 349648 */     // GIR_Coverage, 1340,
     /* 349648 */     GIR_EraseRootFromParent_Done,
     /* 349649 */   // Label 6903: @349649
     /* 349649 */   GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(349682), // Rule ID 1330 //
     /* 349654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 349657 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349661 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349665 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349669 */     // (fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 349669 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
     /* 349672 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349674 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349676 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 349678 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 349680 */     GIR_RootConstrainSelectedInstOperands,
     /* 349681 */     // GIR_Coverage, 1330,
     /* 349681 */     GIR_EraseRootFromParent_Done,
     /* 349682 */   // Label 6904: @349682
     /* 349682 */   GIM_Reject,
     /* 349683 */ // Label 6885: @349683
     /* 349683 */ GIM_Reject,
     /* 349684 */ // Label 6724: @349684
     /* 349684 */ GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(350862),
     /* 349689 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349692 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 349695 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 349698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349702 */   GIM_Try, /*On fail goto*//*Label 6906*/ GIMT_Encode4(349786), // Rule ID 6735 //
     /* 349707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 349710 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349714 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 349718 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349722 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 349726 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 349731 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 349735 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349739 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 349743 */     // MIs[2] Operand 1
     /* 349743 */     // No operand predicates
     /* 349743 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 349747 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349751 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349755 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349760 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349764 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 349766 */     // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 349766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 349769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349771 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349773 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 349777 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 349781 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 349784 */     GIR_RootConstrainSelectedInstOperands,
     /* 349785 */     // GIR_Coverage, 6735,
     /* 349785 */     GIR_EraseRootFromParent_Done,
     /* 349786 */   // Label 6906: @349786
     /* 349786 */   GIM_Try, /*On fail goto*//*Label 6907*/ GIMT_Encode4(349867), // Rule ID 6767 //
     /* 349791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 349794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349806 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 349810 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 349814 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349818 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 349822 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 349827 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 349831 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349835 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 349839 */     // MIs[3] Operand 1
     /* 349839 */     // No operand predicates
     /* 349839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349847 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 349849 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 349849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 349852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349854 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349856 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 349858 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349862 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 349865 */     GIR_RootConstrainSelectedInstOperands,
     /* 349866 */     // GIR_Coverage, 6767,
     /* 349866 */     GIR_EraseRootFromParent_Done,
     /* 349867 */   // Label 6907: @349867
     /* 349867 */   GIM_Try, /*On fail goto*//*Label 6908*/ GIMT_Encode4(349951), // Rule ID 6799 //
     /* 349872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 349875 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 349879 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349883 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349892 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 349896 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 349900 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349904 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 349908 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 349913 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 349917 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 349921 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 349925 */     // MIs[3] Operand 1
     /* 349925 */     // No operand predicates
     /* 349925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349929 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 349931 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 349931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 349934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 349936 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 349938 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 349942 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 349946 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 349949 */     GIR_RootConstrainSelectedInstOperands,
     /* 349950 */     // GIR_Coverage, 6799,
     /* 349950 */     GIR_EraseRootFromParent_Done,
     /* 349951 */   // Label 6908: @349951
     /* 349951 */   GIM_Try, /*On fail goto*//*Label 6909*/ GIMT_Encode4(350032), // Rule ID 6703 //
     /* 349956 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 349959 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 349963 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 349967 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 349971 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349975 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 349979 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 349983 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 349987 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 349991 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 349996 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 350000 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 350004 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 350008 */     // MIs[3] Operand 1
     /* 350008 */     // No operand predicates
     /* 350008 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350012 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 350014 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 350014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 350017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350019 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350021 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350023 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 350027 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 350030 */     GIR_RootConstrainSelectedInstOperands,
     /* 350031 */     // GIR_Coverage, 6703,
     /* 350031 */     GIR_EraseRootFromParent_Done,
     /* 350032 */   // Label 6909: @350032
     /* 350032 */   GIM_Try, /*On fail goto*//*Label 6910*/ GIMT_Encode4(350101), // Rule ID 2562 //
     /* 350037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350044 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 350048 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350052 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 350056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 350061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 350065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 350069 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 350073 */     // MIs[2] Operand 1
     /* 350073 */     // No operand predicates
     /* 350073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350077 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350081 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350083 */     // (fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 350083 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 350086 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350088 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350090 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 350092 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350096 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 350099 */     GIR_RootConstrainSelectedInstOperands,
     /* 350100 */     // GIR_Coverage, 2562,
     /* 350100 */     GIR_EraseRootFromParent_Done,
     /* 350101 */   // Label 6910: @350101
     /* 350101 */   GIM_Try, /*On fail goto*//*Label 6911*/ GIMT_Encode4(350170), // Rule ID 6671 //
     /* 350106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350109 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 350117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 350121 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350125 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 350129 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 350134 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 350138 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 350142 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 350146 */     // MIs[2] Operand 1
     /* 350146 */     // No operand predicates
     /* 350146 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350150 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350152 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 350152 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 350155 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350157 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350159 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350161 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350165 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 350168 */     GIR_RootConstrainSelectedInstOperands,
     /* 350169 */     // GIR_Coverage, 6671,
     /* 350169 */     GIR_EraseRootFromParent_Done,
     /* 350170 */   // Label 6911: @350170
     /* 350170 */   GIM_Try, /*On fail goto*//*Label 6912*/ GIMT_Encode4(350269), // Rule ID 6737 //
     /* 350175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350178 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350182 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 350186 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 350190 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350195 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 350199 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350203 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350207 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350212 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350216 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350218 */     // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350218 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350221 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350225 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350230 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350233 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350237 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350240 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350245 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 350253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350255 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350257 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 350261 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350267 */     GIR_RootConstrainSelectedInstOperands,
     /* 350268 */     // GIR_Coverage, 6737,
     /* 350268 */     GIR_EraseRootFromParent_Done,
     /* 350269 */   // Label 6912: @350269
     /* 350269 */   GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(350365), // Rule ID 6769 //
     /* 350274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350285 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 350297 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 350301 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350306 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350310 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350314 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350316 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350316 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350319 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350323 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350328 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350331 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 350335 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350338 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350343 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 350351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350353 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350355 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 350357 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350360 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350363 */     GIR_RootConstrainSelectedInstOperands,
     /* 350364 */     // GIR_Coverage, 6769,
     /* 350364 */     GIR_EraseRootFromParent_Done,
     /* 350365 */   // Label 6913: @350365
     /* 350365 */   GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(350464), // Rule ID 6801 //
     /* 350370 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350381 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350385 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350390 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 350394 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 350398 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 350402 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350407 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350411 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350413 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350413 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350416 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350420 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350425 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350428 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 350432 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350435 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350440 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350445 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 350448 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350450 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350452 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 350456 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350459 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350462 */     GIR_RootConstrainSelectedInstOperands,
     /* 350463 */     // GIR_Coverage, 6801,
     /* 350463 */     GIR_EraseRootFromParent_Done,
     /* 350464 */   // Label 6914: @350464
     /* 350464 */   GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(350560), // Rule ID 6705 //
     /* 350469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350472 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350476 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 350480 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350484 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350488 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 350492 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 350496 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 350500 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350505 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350509 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 350511 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350511 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350514 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350518 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350523 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350526 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 350530 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350533 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350538 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 350546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350548 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350550 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350552 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350555 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350558 */     GIR_RootConstrainSelectedInstOperands,
     /* 350559 */     // GIR_Coverage, 6705,
     /* 350559 */     GIR_EraseRootFromParent_Done,
     /* 350560 */   // Label 6915: @350560
     /* 350560 */   GIM_Try, /*On fail goto*//*Label 6916*/ GIMT_Encode4(350644), // Rule ID 2564 //
     /* 350565 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350568 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350572 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 350576 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 350580 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350585 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350589 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350593 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350595 */     // (fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350595 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350598 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350602 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350607 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350610 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350614 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350617 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350622 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350627 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 350630 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350632 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350634 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 350636 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350639 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350642 */     GIR_RootConstrainSelectedInstOperands,
     /* 350643 */     // GIR_Coverage, 2564,
     /* 350643 */     GIR_EraseRootFromParent_Done,
     /* 350644 */   // Label 6916: @350644
     /* 350644 */   GIM_Try, /*On fail goto*//*Label 6917*/ GIMT_Encode4(350694), // Rule ID 14394 //
     /* 350649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 350656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350664 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350669 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350673 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350677 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350679 */     // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 350679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 350682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350684 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350686 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 350688 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350692 */     GIR_RootConstrainSelectedInstOperands,
     /* 350693 */     // GIR_Coverage, 14394,
     /* 350693 */     GIR_EraseRootFromParent_Done,
     /* 350694 */   // Label 6917: @350694
     /* 350694 */   GIM_Try, /*On fail goto*//*Label 6918*/ GIMT_Encode4(350778), // Rule ID 6673 //
     /* 350699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350702 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350706 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 350710 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 350714 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 350718 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350723 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350727 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350729 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 350729 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 350732 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 350736 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 350741 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 350744 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350748 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 350751 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350756 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 350761 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 350764 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350766 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350768 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350770 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 350773 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 350776 */     GIR_RootConstrainSelectedInstOperands,
     /* 350777 */     // GIR_Coverage, 6673,
     /* 350777 */     GIR_EraseRootFromParent_Done,
     /* 350778 */   // Label 6918: @350778
     /* 350778 */   GIM_Try, /*On fail goto*//*Label 6919*/ GIMT_Encode4(350828), // Rule ID 1336 //
     /* 350783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350790 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 350794 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 350798 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 350802 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350807 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350811 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 350813 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 350813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 350816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350818 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350820 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 350822 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 350826 */     GIR_RootConstrainSelectedInstOperands,
     /* 350827 */     // GIR_Coverage, 1336,
     /* 350827 */     GIR_EraseRootFromParent_Done,
     /* 350828 */   // Label 6919: @350828
     /* 350828 */   GIM_Try, /*On fail goto*//*Label 6920*/ GIMT_Encode4(350861), // Rule ID 1326 //
     /* 350833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 350836 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 350848 */     // (fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 350848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
     /* 350851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 350853 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 350855 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 350857 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 350859 */     GIR_RootConstrainSelectedInstOperands,
     /* 350860 */     // GIR_Coverage, 1326,
     /* 350860 */     GIR_EraseRootFromParent_Done,
     /* 350861 */   // Label 6920: @350861
     /* 350861 */   GIM_Reject,
     /* 350862 */ // Label 6905: @350862
     /* 350862 */ GIM_Reject,
     /* 350863 */ // Label 6725: @350863
     /* 350863 */ GIM_Reject,
     /* 350864 */ // Label 72: @350864
     /* 350864 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6929*/ GIMT_Encode4(351479),
     /* 350875 */ /*GILLT_s16*//*Label 6921*/ GIMT_Encode4(350915),
     /* 350879 */ /*GILLT_s32*//*Label 6922*/ GIMT_Encode4(350953),
     /* 350883 */ /*GILLT_s64*//*Label 6923*/ GIMT_Encode4(350991), GIMT_Encode4(0),
     /* 350891 */ /*GILLT_v2s32*//*Label 6924*/ GIMT_Encode4(351029),
     /* 350895 */ /*GILLT_v2s64*//*Label 6925*/ GIMT_Encode4(351067),
     /* 350899 */ /*GILLT_v4s16*//*Label 6926*/ GIMT_Encode4(351105),
     /* 350903 */ /*GILLT_v4s32*//*Label 6927*/ GIMT_Encode4(351143), GIMT_Encode4(0),
     /* 350911 */ /*GILLT_v8s16*//*Label 6928*/ GIMT_Encode4(351181),
     /* 350915 */ // Label 6921: @350915
     /* 350915 */ GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(350952), // Rule ID 632 //
     /* 350920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 350923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 350926 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 350929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 350933 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 350937 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 350941 */   // (fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 350941 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
     /* 350946 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 350950 */   GIR_RootConstrainSelectedInstOperands,
     /* 350951 */   // GIR_Coverage, 632,
     /* 350951 */   GIR_Done,
     /* 350952 */ // Label 6930: @350952
     /* 350952 */ GIM_Reject,
     /* 350953 */ // Label 6922: @350953
     /* 350953 */ GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(350990), // Rule ID 634 //
     /* 350958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 350961 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 350964 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 350967 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 350971 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 350975 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 350979 */   // (fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 350979 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
     /* 350984 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 350988 */   GIR_RootConstrainSelectedInstOperands,
     /* 350989 */   // GIR_Coverage, 634,
     /* 350989 */   GIR_Done,
     /* 350990 */ // Label 6931: @350990
     /* 350990 */ GIM_Reject,
     /* 350991 */ // Label 6923: @350991
     /* 350991 */ GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(351028), // Rule ID 636 //
     /* 350996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 350999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 351002 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 351005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351009 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351013 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351017 */   // (fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 351017 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
     /* 351022 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351026 */   GIR_RootConstrainSelectedInstOperands,
     /* 351027 */   // GIR_Coverage, 636,
     /* 351027 */   GIR_Done,
     /* 351028 */ // Label 6932: @351028
     /* 351028 */ GIM_Reject,
     /* 351029 */ // Label 6924: @351029
     /* 351029 */ GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(351066), // Rule ID 1258 //
     /* 351034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 351037 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 351040 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 351043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351047 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351051 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351055 */   // (fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 351055 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
     /* 351060 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351064 */   GIR_RootConstrainSelectedInstOperands,
     /* 351065 */   // GIR_Coverage, 1258,
     /* 351065 */   GIR_Done,
     /* 351066 */ // Label 6933: @351066
     /* 351066 */ GIM_Reject,
     /* 351067 */ // Label 6925: @351067
     /* 351067 */ GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(351104), // Rule ID 1262 //
     /* 351072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 351075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 351078 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 351081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351085 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351089 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351093 */   // (fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 351093 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
     /* 351098 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351102 */   GIR_RootConstrainSelectedInstOperands,
     /* 351103 */   // GIR_Coverage, 1262,
     /* 351103 */   GIR_Done,
     /* 351104 */ // Label 6934: @351104
     /* 351104 */ GIM_Reject,
     /* 351105 */ // Label 6926: @351105
     /* 351105 */ GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(351142), // Rule ID 1254 //
     /* 351110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 351113 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 351116 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 351119 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351123 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351127 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351131 */   // (fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 351131 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
     /* 351136 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351140 */   GIR_RootConstrainSelectedInstOperands,
     /* 351141 */   // GIR_Coverage, 1254,
     /* 351141 */   GIR_Done,
     /* 351142 */ // Label 6935: @351142
     /* 351142 */ GIM_Reject,
     /* 351143 */ // Label 6927: @351143
     /* 351143 */ GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(351180), // Rule ID 1260 //
     /* 351148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 351151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 351154 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 351157 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351161 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351165 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351169 */   // (fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 351169 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 351174 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351178 */   GIR_RootConstrainSelectedInstOperands,
     /* 351179 */   // GIR_Coverage, 1260,
     /* 351179 */   GIR_Done,
     /* 351180 */ // Label 6936: @351180
     /* 351180 */ GIM_Reject,
     /* 351181 */ // Label 6928: @351181
     /* 351181 */ GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(351478),
     /* 351186 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351189 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 351192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351196 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351200 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351204 */   GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(351223), // Rule ID 1256 //
     /* 351209 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 351212 */     // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 351212 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
     /* 351217 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 351221 */     GIR_RootConstrainSelectedInstOperands,
     /* 351222 */     // GIR_Coverage, 1256,
     /* 351222 */     GIR_Done,
     /* 351223 */   // Label 6938: @351223
     /* 351223 */   GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(351477), // Rule ID 7662 //
     /* 351228 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 351231 */     // (fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 351231 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 351234 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 351238 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351243 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 351247 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 351249 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 351252 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 351256 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351261 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 351265 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 351267 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 351270 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 351274 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351279 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 351282 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 351285 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 351287 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 351290 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351294 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351299 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 351305 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351310 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351315 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 351318 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 351322 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351327 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 351330 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 351332 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 351335 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351339 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351344 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 351350 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351355 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351360 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 351363 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 351367 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351372 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 351375 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 351377 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 351380 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 351384 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351389 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 351392 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 351395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 351397 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 351400 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 351404 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351409 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 351412 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 351414 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 351417 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 351421 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351426 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 351428 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 351431 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 351435 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351440 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 351443 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 351446 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 351449 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351454 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351459 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 351464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 351467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 351469 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 351472 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 351475 */     GIR_RootConstrainSelectedInstOperands,
     /* 351476 */     // GIR_Coverage, 7662,
     /* 351476 */     GIR_EraseRootFromParent_Done,
     /* 351477 */   // Label 6939: @351477
     /* 351477 */   GIM_Reject,
     /* 351478 */ // Label 6937: @351478
     /* 351478 */ GIM_Reject,
     /* 351479 */ // Label 6929: @351479
     /* 351479 */ GIM_Reject,
     /* 351480 */ // Label 73: @351480
     /* 351480 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 6948*/ GIMT_Encode4(354986),
     /* 351491 */ /*GILLT_s16*//*Label 6940*/ GIMT_Encode4(351531),
     /* 351495 */ /*GILLT_s32*//*Label 6941*/ GIMT_Encode4(352699),
     /* 351499 */ /*GILLT_s64*//*Label 6942*/ GIMT_Encode4(353722), GIMT_Encode4(0),
     /* 351507 */ /*GILLT_v2s32*//*Label 6943*/ GIMT_Encode4(354745),
     /* 351511 */ /*GILLT_v2s64*//*Label 6944*/ GIMT_Encode4(354772),
     /* 351515 */ /*GILLT_v4s16*//*Label 6945*/ GIMT_Encode4(354799),
     /* 351519 */ /*GILLT_v4s32*//*Label 6946*/ GIMT_Encode4(354879), GIMT_Encode4(0),
     /* 351527 */ /*GILLT_v8s16*//*Label 6947*/ GIMT_Encode4(354906),
     /* 351531 */ // Label 6940: @351531
     /* 351531 */ GIM_Try, /*On fail goto*//*Label 6949*/ GIMT_Encode4(352698),
     /* 351536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 351539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351543 */   GIM_Try, /*On fail goto*//*Label 6950*/ GIMT_Encode4(351701), // Rule ID 4924 //
     /* 351548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 351559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 351563 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 351567 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 351571 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 351575 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 351579 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351583 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 351587 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351592 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 351596 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 351600 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 351604 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351608 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 351612 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351617 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 351621 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351626 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 351628 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 351628 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 351631 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351635 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351640 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 351646 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351651 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 351659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351668 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 351674 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351679 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 351687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351689 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 351692 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 351695 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 351699 */     GIR_RootConstrainSelectedInstOperands,
     /* 351700 */     // GIR_Coverage, 4924,
     /* 351700 */     GIR_EraseRootFromParent_Done,
     /* 351701 */   // Label 6950: @351701
     /* 351701 */   GIM_Try, /*On fail goto*//*Label 6951*/ GIMT_Encode4(351859), // Rule ID 4923 //
     /* 351706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 351717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 351721 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 351725 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 351729 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 351733 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 351737 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351741 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 351745 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351750 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 351754 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 351758 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 351762 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351766 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 351770 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351775 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 351779 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351784 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 351786 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 351786 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 351789 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351793 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351798 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 351804 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351809 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351814 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 351817 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351821 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351826 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 351832 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351837 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351842 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 351845 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351847 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 351850 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 351853 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 351857 */     GIR_RootConstrainSelectedInstOperands,
     /* 351858 */     // GIR_Coverage, 4923,
     /* 351858 */     GIR_EraseRootFromParent_Done,
     /* 351859 */   // Label 6951: @351859
     /* 351859 */   GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(351970), // Rule ID 4922 //
     /* 351864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351867 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351871 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 351875 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 351879 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 351883 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 351887 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 351891 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 351895 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 351899 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 351903 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351908 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 351912 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351917 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351922 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 351924 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 351924 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 351927 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 351931 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 351936 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 351942 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 351947 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 351952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 351955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 351957 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 351960 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 351964 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 351968 */     GIR_RootConstrainSelectedInstOperands,
     /* 351969 */     // GIR_Coverage, 4922,
     /* 351969 */     GIR_EraseRootFromParent_Done,
     /* 351970 */   // Label 6952: @351970
     /* 351970 */   GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(352081), // Rule ID 4920 //
     /* 351975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 351978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 351982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 351986 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 351990 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 351994 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 351998 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352003 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 352007 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352011 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 352015 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 352019 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352024 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 352028 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352033 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 352035 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 352035 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 352038 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352042 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352047 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 352053 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352058 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 352066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352072 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 352075 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352079 */     GIR_RootConstrainSelectedInstOperands,
     /* 352080 */     // GIR_Coverage, 4920,
     /* 352080 */     GIR_EraseRootFromParent_Done,
     /* 352081 */   // Label 6953: @352081
     /* 352081 */   GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(352192), // Rule ID 4921 //
     /* 352086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352093 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 352097 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352101 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352105 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 352109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 352113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352117 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 352121 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 352125 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352130 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 352134 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352139 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352144 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 352146 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 352146 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 352149 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352153 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352158 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 352164 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352169 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352174 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 352177 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352179 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 352182 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 352186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352190 */     GIR_RootConstrainSelectedInstOperands,
     /* 352191 */     // GIR_Coverage, 4921,
     /* 352191 */     GIR_EraseRootFromParent_Done,
     /* 352192 */   // Label 6954: @352192
     /* 352192 */   GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(352303), // Rule ID 4919 //
     /* 352197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352200 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352204 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 352208 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352212 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352216 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 352220 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352225 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 352229 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352233 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 352237 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 352241 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352246 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 352250 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352255 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 352257 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 352257 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 352260 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352264 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352269 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 352275 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352280 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352285 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 352288 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352290 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352294 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 352297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352301 */     GIR_RootConstrainSelectedInstOperands,
     /* 352302 */     // GIR_Coverage, 4919,
     /* 352302 */     GIR_EraseRootFromParent_Done,
     /* 352303 */   // Label 6955: @352303
     /* 352303 */   GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(352367), // Rule ID 692 //
     /* 352308 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352311 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352315 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 352319 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352323 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352327 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 352331 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352336 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352346 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352348 */     // (fneg:{ *:[f16] } (fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 352348 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 352351 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352353 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 352361 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352365 */     GIR_RootConstrainSelectedInstOperands,
     /* 352366 */     // GIR_Coverage, 692,
     /* 352366 */     GIR_EraseRootFromParent_Done,
     /* 352367 */   // Label 6956: @352367
     /* 352367 */   GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(352431), // Rule ID 691 //
     /* 352372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352375 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352379 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 352383 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352387 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352391 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
     /* 352395 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352405 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352410 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352412 */     // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra))  =>  (FNMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 352412 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDHrrr),
     /* 352415 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352417 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 352425 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352429 */     GIR_RootConstrainSelectedInstOperands,
     /* 352430 */     // GIR_Coverage, 691,
     /* 352430 */     GIR_EraseRootFromParent_Done,
     /* 352431 */   // Label 6957: @352431
     /* 352431 */   GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(352482), // Rule ID 668 //
     /* 352436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 352447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352451 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352455 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352465 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352467 */     // (fneg:{ *:[f16] } (fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 352467 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 352470 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352472 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352476 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 352480 */     GIR_RootConstrainSelectedInstOperands,
     /* 352481 */     // GIR_Coverage, 668,
     /* 352481 */     GIR_EraseRootFromParent_Done,
     /* 352482 */   // Label 6958: @352482
     /* 352482 */   GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(352533), // Rule ID 667 //
     /* 352487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 352498 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 352502 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 352506 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352516 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 352518 */     // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm))  =>  (FNMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 352518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULHrr),
     /* 352521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 352527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 352531 */     GIR_RootConstrainSelectedInstOperands,
     /* 352532 */     // GIR_Coverage, 667,
     /* 352532 */     GIR_EraseRootFromParent_Done,
     /* 352533 */   // Label 6959: @352533
     /* 352533 */   GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(352552), // Rule ID 566 //
     /* 352538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 352541 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352545 */     // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FNEGHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 352545 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGHr),
     /* 352550 */     GIR_RootConstrainSelectedInstOperands,
     /* 352551 */     // GIR_Coverage, 566,
     /* 352551 */     GIR_Done,
     /* 352552 */   // Label 6960: @352552
     /* 352552 */   GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(352697), // Rule ID 7008 //
     /* 352557 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352561 */     // (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (EORWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32768:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
     /* 352561 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 352564 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 352568 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352573 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 352575 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /* 352578 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 352582 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352587 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 352590 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 352594 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 352597 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352602 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352607 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352612 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 352615 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352619 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352624 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 352627 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 352632 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 352635 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::EORWri),
     /* 352639 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352644 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 352647 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // 
     /* 352652 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 352654 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 352657 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352661 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352666 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 352669 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 352679 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 352686 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 352691 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352696 */     // GIR_Coverage, 7008,
     /* 352696 */     GIR_EraseRootFromParent_Done,
     /* 352697 */   // Label 6961: @352697
     /* 352697 */   GIM_Reject,
     /* 352698 */ // Label 6949: @352698
     /* 352698 */ GIM_Reject,
     /* 352699 */ // Label 6941: @352699
     /* 352699 */ GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(353721),
     /* 352704 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 352707 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352711 */   GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(352869), // Rule ID 4930 //
     /* 352716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 352719 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352723 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 352727 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 352731 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 352735 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 352739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 352743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352747 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 352751 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 352755 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352760 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 352764 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 352768 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352772 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 352776 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 352780 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352785 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 352789 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352794 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 352796 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 352796 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 352799 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352803 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352808 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 352814 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352819 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352824 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 352827 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352831 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352836 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 352842 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352847 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 352855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 352857 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 352860 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 352863 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 352867 */     GIR_RootConstrainSelectedInstOperands,
     /* 352868 */     // GIR_Coverage, 4930,
     /* 352868 */     GIR_EraseRootFromParent_Done,
     /* 352869 */   // Label 6963: @352869
     /* 352869 */   GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(353027), // Rule ID 4929 //
     /* 352874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 352877 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 352881 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 352885 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 352889 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 352893 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 352897 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 352901 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352905 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 352909 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 352913 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352918 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 352922 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 352926 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 352930 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 352934 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 352938 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352943 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 352947 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352952 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 352954 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 352954 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 352957 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352961 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352966 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 352972 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 352977 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 352982 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 352985 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 352989 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 352994 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 353000 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353005 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353010 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353013 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353015 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353018 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 353021 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353025 */     GIR_RootConstrainSelectedInstOperands,
     /* 353026 */     // GIR_Coverage, 4929,
     /* 353026 */     GIR_EraseRootFromParent_Done,
     /* 353027 */   // Label 6964: @353027
     /* 353027 */   GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(353138), // Rule ID 4928 //
     /* 353032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353035 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353039 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 353043 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353047 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353051 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353055 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 353059 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353063 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 353067 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353071 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353076 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353085 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353090 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 353092 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 353092 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 353095 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353099 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353104 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 353110 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353115 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353125 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353136 */     GIR_RootConstrainSelectedInstOperands,
     /* 353137 */     // GIR_Coverage, 4928,
     /* 353137 */     GIR_EraseRootFromParent_Done,
     /* 353138 */   // Label 6965: @353138
     /* 353138 */   GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(353249), // Rule ID 4926 //
     /* 353143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 353154 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353158 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353162 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353166 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353171 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 353175 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353179 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 353183 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353187 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353192 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353201 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 353203 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 353203 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 353206 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353210 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353215 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 353221 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353226 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353236 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353240 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353243 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353247 */     GIR_RootConstrainSelectedInstOperands,
     /* 353248 */     // GIR_Coverage, 4926,
     /* 353248 */     GIR_EraseRootFromParent_Done,
     /* 353249 */   // Label 6966: @353249
     /* 353249 */   GIM_Try, /*On fail goto*//*Label 6967*/ GIMT_Encode4(353360), // Rule ID 4927 //
     /* 353254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353257 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353261 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 353265 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353269 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353273 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353277 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 353281 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353285 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 353289 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353293 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353298 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353307 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353312 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 353314 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 353314 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 353317 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353321 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353326 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 353332 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353347 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353358 */     GIR_RootConstrainSelectedInstOperands,
     /* 353359 */     // GIR_Coverage, 4927,
     /* 353359 */     GIR_EraseRootFromParent_Done,
     /* 353360 */   // Label 6967: @353360
     /* 353360 */   GIM_Try, /*On fail goto*//*Label 6968*/ GIMT_Encode4(353471), // Rule ID 4925 //
     /* 353365 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353368 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353372 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 353376 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353380 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353384 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353388 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353393 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 353397 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353401 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 353405 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353409 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353414 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353418 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353423 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 353425 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 353425 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 353428 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353432 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353437 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 353443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353448 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353458 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353462 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353469 */     GIR_RootConstrainSelectedInstOperands,
     /* 353470 */     // GIR_Coverage, 4925,
     /* 353470 */     GIR_EraseRootFromParent_Done,
     /* 353471 */   // Label 6968: @353471
     /* 353471 */   GIM_Try, /*On fail goto*//*Label 6969*/ GIMT_Encode4(353535), // Rule ID 694 //
     /* 353476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353479 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353483 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 353487 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353491 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353495 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353499 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353504 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353509 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353514 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 353516 */     // (fneg:{ *:[f32] } (fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 353516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353521 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353525 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353529 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353533 */     GIR_RootConstrainSelectedInstOperands,
     /* 353534 */     // GIR_Coverage, 694,
     /* 353534 */     GIR_EraseRootFromParent_Done,
     /* 353535 */   // Label 6969: @353535
     /* 353535 */   GIM_Try, /*On fail goto*//*Label 6970*/ GIMT_Encode4(353599), // Rule ID 693 //
     /* 353540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353547 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 353551 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353559 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 353563 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353568 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353573 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353578 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 353580 */     // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra))  =>  (FNMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 353580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDSrrr),
     /* 353583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353585 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353589 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353593 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353597 */     GIR_RootConstrainSelectedInstOperands,
     /* 353598 */     // GIR_Coverage, 693,
     /* 353598 */     GIR_EraseRootFromParent_Done,
     /* 353599 */   // Label 6970: @353599
     /* 353599 */   GIM_Try, /*On fail goto*//*Label 6971*/ GIMT_Encode4(353650), // Rule ID 670 //
     /* 353604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353607 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353611 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 353615 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353619 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353623 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353628 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353633 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 353635 */     // (fneg:{ *:[f32] } (fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 353635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 353638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353648 */     GIR_RootConstrainSelectedInstOperands,
     /* 353649 */     // GIR_Coverage, 670,
     /* 353649 */     GIR_EraseRootFromParent_Done,
     /* 353650 */   // Label 6971: @353650
     /* 353650 */   GIM_Try, /*On fail goto*//*Label 6972*/ GIMT_Encode4(353701), // Rule ID 669 //
     /* 353655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 353666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 353670 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 353674 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353679 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353684 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 353686 */     // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm))  =>  (FNMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 353686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULSrr),
     /* 353689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353691 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 353695 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 353699 */     GIR_RootConstrainSelectedInstOperands,
     /* 353700 */     // GIR_Coverage, 669,
     /* 353700 */     GIR_EraseRootFromParent_Done,
     /* 353701 */   // Label 6972: @353701
     /* 353701 */   GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(353720), // Rule ID 567 //
     /* 353706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353709 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 353713 */     // (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FNEGSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 353713 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGSr),
     /* 353718 */     GIR_RootConstrainSelectedInstOperands,
     /* 353719 */     // GIR_Coverage, 567,
     /* 353719 */     GIR_Done,
     /* 353720 */   // Label 6973: @353720
     /* 353720 */   GIM_Reject,
     /* 353721 */ // Label 6962: @353721
     /* 353721 */ GIM_Reject,
     /* 353722 */ // Label 6942: @353722
     /* 353722 */ GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(354744),
     /* 353727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 353730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 353734 */   GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(353892), // Rule ID 4936 //
     /* 353739 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353746 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 353750 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 353754 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 353758 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 353762 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 353766 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353770 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 353774 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353778 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353783 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353787 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 353791 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353795 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 353799 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 353803 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353808 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 353812 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 353817 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 353819 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 353819 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 353822 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353826 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353831 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 353837 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 353842 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353847 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 353850 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353854 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353859 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 353865 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 353870 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353875 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 353878 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 353880 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 353883 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 353886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 353890 */     GIR_RootConstrainSelectedInstOperands,
     /* 353891 */     // GIR_Coverage, 4936,
     /* 353891 */     GIR_EraseRootFromParent_Done,
     /* 353892 */   // Label 6975: @353892
     /* 353892 */   GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(354050), // Rule ID 4935 //
     /* 353897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 353900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 353904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 353908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 353912 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 353916 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 353920 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 353924 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353928 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 353932 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 353936 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353941 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 353945 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 353949 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 353953 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 353957 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 353961 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 353966 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 353970 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 353975 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 353977 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 353977 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 353980 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 353984 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 353989 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 353995 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354000 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354005 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354008 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 354012 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354017 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 354023 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354028 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354038 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354041 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 354044 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354048 */     GIR_RootConstrainSelectedInstOperands,
     /* 354049 */     // GIR_Coverage, 4935,
     /* 354049 */     GIR_EraseRootFromParent_Done,
     /* 354050 */   // Label 6976: @354050
     /* 354050 */   GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(354161), // Rule ID 4934 //
     /* 354055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354058 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354062 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 354066 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354070 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354074 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354078 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 354082 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 354086 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 354090 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 354094 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354099 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 354103 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354108 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354113 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 354115 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 354115 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 354122 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354127 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 354133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354138 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354148 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354151 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354155 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354159 */     GIR_RootConstrainSelectedInstOperands,
     /* 354160 */     // GIR_Coverage, 4934,
     /* 354160 */     GIR_EraseRootFromParent_Done,
     /* 354161 */   // Label 6977: @354161
     /* 354161 */   GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(354272), // Rule ID 4932 //
     /* 354166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354169 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354173 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 354177 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354181 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354185 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354189 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354194 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 354198 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 354202 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 354206 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 354210 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354215 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 354219 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354224 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 354226 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 354226 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354229 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 354233 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354238 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 354244 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354249 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354263 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354266 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354270 */     GIR_RootConstrainSelectedInstOperands,
     /* 354271 */     // GIR_Coverage, 4932,
     /* 354271 */     GIR_EraseRootFromParent_Done,
     /* 354272 */   // Label 6978: @354272
     /* 354272 */   GIM_Try, /*On fail goto*//*Label 6979*/ GIMT_Encode4(354383), // Rule ID 4933 //
     /* 354277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 354288 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354292 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354296 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354300 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 354304 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 354308 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 354312 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 354316 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354321 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 354325 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354330 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354335 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 354337 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 354337 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354340 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 354344 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354349 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 354355 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354360 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354370 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354377 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354381 */     GIR_RootConstrainSelectedInstOperands,
     /* 354382 */     // GIR_Coverage, 4933,
     /* 354382 */     GIR_EraseRootFromParent_Done,
     /* 354383 */   // Label 6979: @354383
     /* 354383 */   GIM_Try, /*On fail goto*//*Label 6980*/ GIMT_Encode4(354494), // Rule ID 4931 //
     /* 354388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 354399 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354403 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354407 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354411 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354416 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 354420 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 354424 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 354428 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 354432 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354437 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 354441 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354446 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 354448 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 354448 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354451 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 354455 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354460 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 354466 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354471 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354481 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354485 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354492 */     GIR_RootConstrainSelectedInstOperands,
     /* 354493 */     // GIR_Coverage, 4931,
     /* 354493 */     GIR_EraseRootFromParent_Done,
     /* 354494 */   // Label 6980: @354494
     /* 354494 */   GIM_Try, /*On fail goto*//*Label 6981*/ GIMT_Encode4(354558), // Rule ID 696 //
     /* 354499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354502 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354506 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
     /* 354510 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354514 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354518 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354522 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354527 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354532 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354537 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 354539 */     // (fneg:{ *:[f64] } (fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 354539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354544 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354548 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354552 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354556 */     GIR_RootConstrainSelectedInstOperands,
     /* 354557 */     // GIR_Coverage, 696,
     /* 354557 */     GIR_EraseRootFromParent_Done,
     /* 354558 */   // Label 6981: @354558
     /* 354558 */   GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(354622), // Rule ID 695 //
     /* 354563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354570 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
     /* 354574 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354578 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354582 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 354586 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354591 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354596 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354601 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 354603 */     // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra))  =>  (FNMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 354603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMADDDrrr),
     /* 354606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354616 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ra
     /* 354620 */     GIR_RootConstrainSelectedInstOperands,
     /* 354621 */     // GIR_Coverage, 695,
     /* 354621 */     GIR_EraseRootFromParent_Done,
     /* 354622 */   // Label 6982: @354622
     /* 354622 */   GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(354673), // Rule ID 672 //
     /* 354627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 354638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354646 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354651 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354656 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 354658 */     // (fneg:{ *:[f64] } (fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 354658 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 354661 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354663 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354667 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354671 */     GIR_RootConstrainSelectedInstOperands,
     /* 354672 */     // GIR_Coverage, 672,
     /* 354672 */     GIR_EraseRootFromParent_Done,
     /* 354673 */   // Label 6983: @354673
     /* 354673 */   GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(354724), // Rule ID 671 //
     /* 354678 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354681 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 354685 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 354689 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 354693 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 354697 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354702 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354707 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 354709 */     // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm))  =>  (FNMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 354709 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMULDrr),
     /* 354712 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354714 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 354718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 354722 */     GIR_RootConstrainSelectedInstOperands,
     /* 354723 */     // GIR_Coverage, 671,
     /* 354723 */     GIR_EraseRootFromParent_Done,
     /* 354724 */   // Label 6984: @354724
     /* 354724 */   GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(354743), // Rule ID 568 //
     /* 354729 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 354732 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354736 */     // (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FNEGDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 354736 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGDr),
     /* 354741 */     GIR_RootConstrainSelectedInstOperands,
     /* 354742 */     // GIR_Coverage, 568,
     /* 354742 */     GIR_Done,
     /* 354743 */   // Label 6985: @354743
     /* 354743 */   GIM_Reject,
     /* 354744 */ // Label 6974: @354744
     /* 354744 */ GIM_Reject,
     /* 354745 */ // Label 6943: @354745
     /* 354745 */ GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(354771), // Rule ID 890 //
     /* 354750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 354753 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 354756 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354760 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354764 */   // (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FNEGv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 354764 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f32),
     /* 354769 */   GIR_RootConstrainSelectedInstOperands,
     /* 354770 */   // GIR_Coverage, 890,
     /* 354770 */   GIR_Done,
     /* 354771 */ // Label 6986: @354771
     /* 354771 */ GIM_Reject,
     /* 354772 */ // Label 6944: @354772
     /* 354772 */ GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(354798), // Rule ID 892 //
     /* 354777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 354780 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 354783 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354787 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354791 */   // (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FNEGv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 354791 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv2f64),
     /* 354796 */   GIR_RootConstrainSelectedInstOperands,
     /* 354797 */   // GIR_Coverage, 892,
     /* 354797 */   GIR_Done,
     /* 354798 */ // Label 6987: @354798
     /* 354798 */ GIM_Reject,
     /* 354799 */ // Label 6945: @354799
     /* 354799 */ GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(354878),
     /* 354804 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 354807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354811 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 354815 */   GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(354830), // Rule ID 888 //
     /* 354820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 354823 */     // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FNEGv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 354823 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f16),
     /* 354828 */     GIR_RootConstrainSelectedInstOperands,
     /* 354829 */     // GIR_Coverage, 888,
     /* 354829 */     GIR_Done,
     /* 354830 */   // Label 6989: @354830
     /* 354830 */   GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(354877), // Rule ID 7011 //
     /* 354835 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 354838 */     // (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (EORv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (MOVIv4i16:{ *:[i64] } 128:{ *:[i32] }, 8:{ *:[i32] }))
     /* 354838 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 354841 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv4i16),
     /* 354845 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354850 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
     /* 354860 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 354863 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv8i8),
     /* 354868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354870 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 354872 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354875 */     GIR_RootConstrainSelectedInstOperands,
     /* 354876 */     // GIR_Coverage, 7011,
     /* 354876 */     GIR_EraseRootFromParent_Done,
     /* 354877 */   // Label 6990: @354877
     /* 354877 */   GIM_Reject,
     /* 354878 */ // Label 6988: @354878
     /* 354878 */ GIM_Reject,
     /* 354879 */ // Label 6946: @354879
     /* 354879 */ GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(354905), // Rule ID 891 //
     /* 354884 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 354887 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 354890 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354894 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354898 */   // (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FNEGv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 354898 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv4f32),
     /* 354903 */   GIR_RootConstrainSelectedInstOperands,
     /* 354904 */   // GIR_Coverage, 891,
     /* 354904 */   GIR_Done,
     /* 354905 */ // Label 6991: @354905
     /* 354905 */ GIM_Reject,
     /* 354906 */ // Label 6947: @354906
     /* 354906 */ GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(354985),
     /* 354911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 354914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 354922 */   GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(354937), // Rule ID 889 //
     /* 354927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 354930 */     // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FNEGv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 354930 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FNEGv8f16),
     /* 354935 */     GIR_RootConstrainSelectedInstOperands,
     /* 354936 */     // GIR_Coverage, 889,
     /* 354936 */     GIR_Done,
     /* 354937 */   // Label 6993: @354937
     /* 354937 */   GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(354984), // Rule ID 7012 //
     /* 354942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 354945 */     // (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (EORv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (MOVIv8i16:{ *:[f128] } 128:{ *:[i32] }, 8:{ *:[i32] }))
     /* 354945 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 354948 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv8i16),
     /* 354952 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 354957 */     GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(128),
     /* 354967 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 354970 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 354972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EORv16i8),
     /* 354975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 354977 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 354979 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 354982 */     GIR_RootConstrainSelectedInstOperands,
     /* 354983 */     // GIR_Coverage, 7012,
     /* 354983 */     GIR_EraseRootFromParent_Done,
     /* 354984 */   // Label 6994: @354984
     /* 354984 */   GIM_Reject,
     /* 354985 */ // Label 6992: @354985
     /* 354985 */ GIM_Reject,
     /* 354986 */ // Label 6948: @354986
     /* 354986 */ GIM_Reject,
     /* 354987 */ // Label 74: @354987
     /* 354987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(9), /*)*//*default:*//*Label 6999*/ GIMT_Encode4(355234),
     /* 354998 */ /*GILLT_s32*//*Label 6995*/ GIMT_Encode4(355026),
     /* 355002 */ /*GILLT_s64*//*Label 6996*/ GIMT_Encode4(355057), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 355014 */ /*GILLT_v2s64*//*Label 6997*/ GIMT_Encode4(355118), GIMT_Encode4(0),
     /* 355022 */ /*GILLT_v4s32*//*Label 6998*/ GIMT_Encode4(355176),
     /* 355026 */ // Label 6995: @355026
     /* 355026 */ GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(355056), // Rule ID 558 //
     /* 355031 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355034 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 355037 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355041 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355045 */   // (fpextend:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTSHr:{ *:[f32] } FPR16:{ *:[f16] }:$Rn)
     /* 355045 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSHr),
     /* 355050 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355054 */   GIR_RootConstrainSelectedInstOperands,
     /* 355055 */   // GIR_Coverage, 558,
     /* 355055 */   GIR_Done,
     /* 355056 */ // Label 7000: @355056
     /* 355056 */ GIM_Reject,
     /* 355057 */ // Label 6996: @355057
     /* 355057 */ GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(355087), // Rule ID 556 //
     /* 355062 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355065 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 355068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355072 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355076 */   // (fpextend:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTDHr:{ *:[f64] } FPR16:{ *:[f16] }:$Rn)
     /* 355076 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDHr),
     /* 355081 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355085 */   GIR_RootConstrainSelectedInstOperands,
     /* 355086 */   // GIR_Coverage, 556,
     /* 355086 */   GIR_Done,
     /* 355087 */ // Label 7001: @355087
     /* 355087 */ GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(355117), // Rule ID 560 //
     /* 355092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355095 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355102 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355106 */   // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 355106 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTDSr),
     /* 355111 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355115 */   GIR_RootConstrainSelectedInstOperands,
     /* 355116 */   // GIR_Coverage, 560,
     /* 355116 */   GIR_Done,
     /* 355117 */ // Label 7002: @355117
     /* 355117 */ GIM_Reject,
     /* 355118 */ // Label 6997: @355118
     /* 355118 */ GIM_Try, /*On fail goto*//*Label 7003*/ GIMT_Encode4(355175),
     /* 355123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 355126 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 355130 */   GIM_Try, /*On fail goto*//*Label 7004*/ GIMT_Encode4(355154), // Rule ID 4973 //
     /* 355135 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4f32),
     /* 355142 */     // (fpextend:{ *:[v2f64] } (extract_high_v4f32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn))  =>  (FCVTLv4i32:{ *:[v2f64] } V128:{ *:[v4f32] }:$Rn)
     /* 355142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i32),
     /* 355145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 355152 */     GIR_RootConstrainSelectedInstOperands,
     /* 355153 */     // GIR_Coverage, 4973,
     /* 355153 */     GIR_EraseRootFromParent_Done,
     /* 355154 */   // Label 7004: @355154
     /* 355154 */   GIM_Try, /*On fail goto*//*Label 7005*/ GIMT_Encode4(355174), // Rule ID 4971 //
     /* 355159 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355163 */     // (fpextend:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTLv2i32:{ *:[v2f64] } V64:{ *:[v2f32] }:$Rn)
     /* 355163 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv2i32),
     /* 355168 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355172 */     GIR_RootConstrainSelectedInstOperands,
     /* 355173 */     // GIR_Coverage, 4971,
     /* 355173 */     GIR_Done,
     /* 355174 */   // Label 7005: @355174
     /* 355174 */   GIM_Reject,
     /* 355175 */ // Label 7003: @355175
     /* 355175 */ GIM_Reject,
     /* 355176 */ // Label 6998: @355176
     /* 355176 */ GIM_Try, /*On fail goto*//*Label 7006*/ GIMT_Encode4(355233),
     /* 355181 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 355184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 355188 */   GIM_Try, /*On fail goto*//*Label 7007*/ GIMT_Encode4(355212), // Rule ID 4977 //
     /* 355193 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8f16),
     /* 355200 */     // (fpextend:{ *:[v4f32] } (extract_high_v8f16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn))  =>  (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)
     /* 355200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 355203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 355210 */     GIR_RootConstrainSelectedInstOperands,
     /* 355211 */     // GIR_Coverage, 4977,
     /* 355211 */     GIR_EraseRootFromParent_Done,
     /* 355212 */   // Label 7007: @355212
     /* 355212 */   GIM_Try, /*On fail goto*//*Label 7008*/ GIMT_Encode4(355232), // Rule ID 4975 //
     /* 355217 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355221 */     // (fpextend:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTLv4i16:{ *:[v4f32] } V64:{ *:[v4f16] }:$Rn)
     /* 355221 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 355226 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355230 */     GIR_RootConstrainSelectedInstOperands,
     /* 355231 */     // GIR_Coverage, 4975,
     /* 355231 */     GIR_Done,
     /* 355232 */   // Label 7008: @355232
     /* 355232 */   GIM_Reject,
     /* 355233 */ // Label 7006: @355233
     /* 355233 */ GIM_Reject,
     /* 355234 */ // Label 6999: @355234
     /* 355234 */ GIM_Reject,
     /* 355235 */ // Label 75: @355235
     /* 355235 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(8), /*)*//*default:*//*Label 7013*/ GIMT_Encode4(355422),
     /* 355246 */ /*GILLT_s16*//*Label 7009*/ GIMT_Encode4(355274),
     /* 355250 */ /*GILLT_s32*//*Label 7010*/ GIMT_Encode4(355335), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 355262 */ /*GILLT_v2s32*//*Label 7011*/ GIMT_Encode4(355366), GIMT_Encode4(0),
     /* 355270 */ /*GILLT_v4s16*//*Label 7012*/ GIMT_Encode4(355394),
     /* 355274 */ // Label 7009: @355274
     /* 355274 */ GIM_Try, /*On fail goto*//*Label 7014*/ GIMT_Encode4(355304), // Rule ID 552 //
     /* 355279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355282 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355289 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355293 */   // (fpround:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)
     /* 355293 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHDr),
     /* 355298 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355302 */   GIR_RootConstrainSelectedInstOperands,
     /* 355303 */   // GIR_Coverage, 552,
     /* 355303 */   GIR_Done,
     /* 355304 */ // Label 7014: @355304
     /* 355304 */ GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(355334), // Rule ID 562 //
     /* 355309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355319 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355323 */   // (fpround:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)
     /* 355323 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTHSr),
     /* 355328 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355332 */   GIR_RootConstrainSelectedInstOperands,
     /* 355333 */   // GIR_Coverage, 562,
     /* 355333 */   GIR_Done,
     /* 355334 */ // Label 7015: @355334
     /* 355334 */ GIM_Reject,
     /* 355335 */ // Label 7010: @355335
     /* 355335 */ GIM_Try, /*On fail goto*//*Label 7016*/ GIMT_Encode4(355365), // Rule ID 554 //
     /* 355340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 355343 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355350 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355354 */   // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 355354 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTSDr),
     /* 355359 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355363 */   GIR_RootConstrainSelectedInstOperands,
     /* 355364 */   // GIR_Coverage, 554,
     /* 355364 */   GIR_Done,
     /* 355365 */ // Label 7016: @355365
     /* 355365 */ GIM_Reject,
     /* 355366 */ // Label 7011: @355366
     /* 355366 */ GIM_Try, /*On fail goto*//*Label 7017*/ GIMT_Encode4(355393), // Rule ID 4981 //
     /* 355371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 355374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 355382 */   // (fpround:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTNv2i32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
     /* 355382 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv2i32),
     /* 355387 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355391 */   GIR_RootConstrainSelectedInstOperands,
     /* 355392 */   // GIR_Coverage, 4981,
     /* 355392 */   GIR_Done,
     /* 355393 */ // Label 7017: @355393
     /* 355393 */ GIM_Reject,
     /* 355394 */ // Label 7012: @355394
     /* 355394 */ GIM_Try, /*On fail goto*//*Label 7018*/ GIMT_Encode4(355421), // Rule ID 4983 //
     /* 355399 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 355402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 355406 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 355410 */   // (fpround:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTNv4i16:{ *:[v4f16] } V128:{ *:[v4f32] }:$Rn)
     /* 355410 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 355415 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355419 */   GIR_RootConstrainSelectedInstOperands,
     /* 355420 */   // GIR_Coverage, 4983,
     /* 355420 */   GIR_Done,
     /* 355421 */ // Label 7018: @355421
     /* 355421 */ GIM_Reject,
     /* 355422 */ // Label 7013: @355422
     /* 355422 */ GIM_Reject,
     /* 355423 */ // Label 76: @355423
     /* 355423 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7027*/ GIMT_Encode4(357230),
     /* 355434 */ /*GILLT_s16*//*Label 7019*/ GIMT_Encode4(355474),
     /* 355438 */ /*GILLT_s32*//*Label 7020*/ GIMT_Encode4(355505),
     /* 355442 */ /*GILLT_s64*//*Label 7021*/ GIMT_Encode4(356290), GIMT_Encode4(0),
     /* 355450 */ /*GILLT_v2s32*//*Label 7022*/ GIMT_Encode4(357075),
     /* 355454 */ /*GILLT_v2s64*//*Label 7023*/ GIMT_Encode4(357106),
     /* 355458 */ /*GILLT_v4s16*//*Label 7024*/ GIMT_Encode4(357137),
     /* 355462 */ /*GILLT_v4s32*//*Label 7025*/ GIMT_Encode4(357168), GIMT_Encode4(0),
     /* 355470 */ /*GILLT_v8s16*//*Label 7026*/ GIMT_Encode4(357199),
     /* 355474 */ // Label 7019: @355474
     /* 355474 */ GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(355504), // Rule ID 1690 //
     /* 355479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 355482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 355485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355489 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 355493 */   // (fp_to_sint:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 355493 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1f16),
     /* 355498 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 355502 */   GIR_RootConstrainSelectedInstOperands,
     /* 355503 */   // GIR_Coverage, 1690,
     /* 355503 */   GIR_Done,
     /* 355504 */ // Label 7028: @355504
     /* 355504 */ GIM_Reject,
     /* 355505 */ // Label 7020: @355505
     /* 355505 */ GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(355542), // Rule ID 5532 //
     /* 355510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355517 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355521 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 355525 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355529 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355531 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355531 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWSr),
     /* 355534 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355536 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355540 */   GIR_RootConstrainSelectedInstOperands,
     /* 355541 */   // GIR_Coverage, 5532,
     /* 355541 */   GIR_EraseRootFromParent_Done,
     /* 355542 */ // Label 7029: @355542
     /* 355542 */ GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(355579), // Rule ID 5534 //
     /* 355547 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355554 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355558 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 355562 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355566 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355568 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUWDr),
     /* 355571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355573 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355577 */   GIR_RootConstrainSelectedInstOperands,
     /* 355578 */   // GIR_Coverage, 5534,
     /* 355578 */   GIR_EraseRootFromParent_Done,
     /* 355579 */ // Label 7030: @355579
     /* 355579 */ GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(355619), // Rule ID 5537 //
     /* 355584 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 355587 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355590 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355594 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355598 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 355602 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355606 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355608 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSDr),
     /* 355611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355613 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355617 */   GIR_RootConstrainSelectedInstOperands,
     /* 355618 */   // GIR_Coverage, 5537,
     /* 355618 */   GIR_EraseRootFromParent_Done,
     /* 355619 */ // Label 7031: @355619
     /* 355619 */ GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(355656), // Rule ID 5538 //
     /* 355624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355631 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355635 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 355639 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355643 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355645 */   // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355645 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i32),
     /* 355648 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355650 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355654 */   GIR_RootConstrainSelectedInstOperands,
     /* 355655 */   // GIR_Coverage, 5538,
     /* 355655 */   GIR_EraseRootFromParent_Done,
     /* 355656 */ // Label 7032: @355656
     /* 355656 */ GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(355693), // Rule ID 5592 //
     /* 355661 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355668 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355672 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 355676 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355680 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355682 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWSr),
     /* 355685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355687 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355691 */   GIR_RootConstrainSelectedInstOperands,
     /* 355692 */   // GIR_Coverage, 5592,
     /* 355692 */   GIR_EraseRootFromParent_Done,
     /* 355693 */ // Label 7033: @355693
     /* 355693 */ GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(355730), // Rule ID 5594 //
     /* 355698 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355701 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355705 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355709 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 355713 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355717 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355719 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355719 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUWDr),
     /* 355722 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355724 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355728 */   GIR_RootConstrainSelectedInstOperands,
     /* 355729 */   // GIR_Coverage, 5594,
     /* 355729 */   GIR_EraseRootFromParent_Done,
     /* 355730 */ // Label 7034: @355730
     /* 355730 */ GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(355770), // Rule ID 5597 //
     /* 355735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 355738 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355745 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355749 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 355753 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355757 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355759 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355759 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSDr),
     /* 355762 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355764 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355768 */   GIR_RootConstrainSelectedInstOperands,
     /* 355769 */   // GIR_Coverage, 5597,
     /* 355769 */   GIR_EraseRootFromParent_Done,
     /* 355770 */ // Label 7035: @355770
     /* 355770 */ GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(355807), // Rule ID 5598 //
     /* 355775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355782 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355786 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 355790 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355794 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355796 */   // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i32),
     /* 355799 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355801 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355805 */   GIR_RootConstrainSelectedInstOperands,
     /* 355806 */   // GIR_Coverage, 5598,
     /* 355806 */   GIR_EraseRootFromParent_Done,
     /* 355807 */ // Label 7036: @355807
     /* 355807 */ GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(355844), // Rule ID 5712 //
     /* 355812 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355815 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355819 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355823 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 355827 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355831 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355833 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355833 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 355836 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355838 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355842 */   GIR_RootConstrainSelectedInstOperands,
     /* 355843 */   // GIR_Coverage, 5712,
     /* 355843 */   GIR_EraseRootFromParent_Done,
     /* 355844 */ // Label 7037: @355844
     /* 355844 */ GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(355881), // Rule ID 5714 //
     /* 355849 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355856 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355860 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 355864 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355868 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355870 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 355873 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355875 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355879 */   GIR_RootConstrainSelectedInstOperands,
     /* 355880 */   // GIR_Coverage, 5714,
     /* 355880 */   GIR_EraseRootFromParent_Done,
     /* 355881 */ // Label 7038: @355881
     /* 355881 */ GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(355921), // Rule ID 5717 //
     /* 355886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 355889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 355892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355896 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355900 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 355904 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 355908 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355910 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 355910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 355913 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355915 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355919 */   GIR_RootConstrainSelectedInstOperands,
     /* 355920 */   // GIR_Coverage, 5717,
     /* 355920 */   GIR_EraseRootFromParent_Done,
     /* 355921 */ // Label 7039: @355921
     /* 355921 */ GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(355958), // Rule ID 5718 //
     /* 355926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 355933 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355937 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 355941 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355945 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355947 */   // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 355950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355952 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355956 */   GIR_RootConstrainSelectedInstOperands,
     /* 355957 */   // GIR_Coverage, 5718,
     /* 355957 */   GIR_EraseRootFromParent_Done,
     /* 355958 */ // Label 7040: @355958
     /* 355958 */ GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(355995), // Rule ID 5652 //
     /* 355963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 355966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 355970 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 355974 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 355978 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 355982 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 355984 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 355984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 355987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 355989 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 355993 */   GIR_RootConstrainSelectedInstOperands,
     /* 355994 */   // GIR_Coverage, 5652,
     /* 355994 */   GIR_EraseRootFromParent_Done,
     /* 355995 */ // Label 7041: @355995
     /* 355995 */ GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(356032), // Rule ID 5654 //
     /* 356000 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 356007 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356011 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356015 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356019 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356021 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 356021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 356024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356026 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356030 */   GIR_RootConstrainSelectedInstOperands,
     /* 356031 */   // GIR_Coverage, 5654,
     /* 356031 */   GIR_EraseRootFromParent_Done,
     /* 356032 */ // Label 7042: @356032
     /* 356032 */ GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(356072), // Rule ID 5657 //
     /* 356037 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 356040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356047 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356051 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356055 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356059 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356061 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 356061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 356064 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356066 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356070 */   GIR_RootConstrainSelectedInstOperands,
     /* 356071 */   // GIR_Coverage, 5657,
     /* 356071 */   GIR_EraseRootFromParent_Done,
     /* 356072 */ // Label 7043: @356072
     /* 356072 */ GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(356109), // Rule ID 5658 //
     /* 356077 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356080 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356084 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356088 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356092 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356096 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356098 */   // (fp_to_sint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 356098 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 356101 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356103 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356107 */   GIR_RootConstrainSelectedInstOperands,
     /* 356108 */   // GIR_Coverage, 5658,
     /* 356108 */   GIR_EraseRootFromParent_Done,
     /* 356109 */ // Label 7044: @356109
     /* 356109 */ GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(356139), // Rule ID 389 //
     /* 356114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 356117 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 356120 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 356124 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 356128 */   // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 356128 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 356133 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356137 */   GIR_RootConstrainSelectedInstOperands,
     /* 356138 */   // GIR_Coverage, 389,
     /* 356138 */   GIR_Done,
     /* 356139 */ // Label 7045: @356139
     /* 356139 */ GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(356169), // Rule ID 393 //
     /* 356144 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 356147 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356150 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 356154 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356158 */   // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 356158 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 356163 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356167 */   GIR_RootConstrainSelectedInstOperands,
     /* 356168 */   // GIR_Coverage, 393,
     /* 356168 */   GIR_Done,
     /* 356169 */ // Label 7046: @356169
     /* 356169 */ GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(356199), // Rule ID 397 //
     /* 356174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 356177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356180 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 356184 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356188 */   // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 356188 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 356193 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356197 */   GIR_RootConstrainSelectedInstOperands,
     /* 356198 */   // GIR_Coverage, 397,
     /* 356198 */   GIR_Done,
     /* 356199 */ // Label 7047: @356199
     /* 356199 */ GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(356229), // Rule ID 469 //
     /* 356204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 356207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356214 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356218 */   // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 356218 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 356223 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356227 */   GIR_RootConstrainSelectedInstOperands,
     /* 356228 */   // GIR_Coverage, 469,
     /* 356228 */   GIR_Done,
     /* 356229 */ // Label 7048: @356229
     /* 356229 */ GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(356259), // Rule ID 471 //
     /* 356234 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 356237 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 356240 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356244 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 356248 */   // (fp_to_sint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 356248 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 356253 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356257 */   GIR_RootConstrainSelectedInstOperands,
     /* 356258 */   // GIR_Coverage, 471,
     /* 356258 */   GIR_Done,
     /* 356259 */ // Label 7049: @356259
     /* 356259 */ GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(356289), // Rule ID 1688 //
     /* 356264 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 356267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356274 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356278 */   // (fp_to_sint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 356278 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 356283 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356287 */   GIR_RootConstrainSelectedInstOperands,
     /* 356288 */   // GIR_Coverage, 1688,
     /* 356288 */   GIR_Done,
     /* 356289 */ // Label 7050: @356289
     /* 356289 */ GIM_Reject,
     /* 356290 */ // Label 7021: @356290
     /* 356290 */ GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(356327), // Rule ID 5533 //
     /* 356295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356302 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356306 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 356310 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356314 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356316 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356316 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXSr),
     /* 356319 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356321 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356325 */   GIR_RootConstrainSelectedInstOperands,
     /* 356326 */   // GIR_Coverage, 5533,
     /* 356326 */   GIR_EraseRootFromParent_Done,
     /* 356327 */ // Label 7051: @356327
     /* 356327 */ GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(356364), // Rule ID 5535 //
     /* 356332 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356339 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356343 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 356347 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356351 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356353 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSUXDr),
     /* 356356 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356358 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356362 */   GIR_RootConstrainSelectedInstOperands,
     /* 356363 */   // GIR_Coverage, 5535,
     /* 356363 */   GIR_EraseRootFromParent_Done,
     /* 356364 */ // Label 7052: @356364
     /* 356364 */ GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(356404), // Rule ID 5536 //
     /* 356369 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 356372 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356375 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356379 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356383 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 356387 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356391 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356393 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDSr),
     /* 356396 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356398 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356402 */   GIR_RootConstrainSelectedInstOperands,
     /* 356403 */   // GIR_Coverage, 5536,
     /* 356403 */   GIR_EraseRootFromParent_Done,
     /* 356404 */ // Label 7053: @356404
     /* 356404 */ GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(356441), // Rule ID 5539 //
     /* 356409 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356416 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356420 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 356424 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356428 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356430 */   // (fp_to_sint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 356433 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356435 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356439 */   GIR_RootConstrainSelectedInstOperands,
     /* 356440 */   // GIR_Coverage, 5539,
     /* 356440 */   GIR_EraseRootFromParent_Done,
     /* 356441 */ // Label 7054: @356441
     /* 356441 */ GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(356478), // Rule ID 5593 //
     /* 356446 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356449 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356453 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356457 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 356461 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356465 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356467 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXSr),
     /* 356470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356472 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356476 */   GIR_RootConstrainSelectedInstOperands,
     /* 356477 */   // GIR_Coverage, 5593,
     /* 356477 */   GIR_EraseRootFromParent_Done,
     /* 356478 */ // Label 7055: @356478
     /* 356478 */ GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(356515), // Rule ID 5595 //
     /* 356483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356490 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356494 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 356498 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356502 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356504 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSUXDr),
     /* 356507 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356509 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356513 */   GIR_RootConstrainSelectedInstOperands,
     /* 356514 */   // GIR_Coverage, 5595,
     /* 356514 */   GIR_EraseRootFromParent_Done,
     /* 356515 */ // Label 7056: @356515
     /* 356515 */ GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(356555), // Rule ID 5596 //
     /* 356520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 356523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356530 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356534 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 356538 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356542 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356544 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356544 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDSr),
     /* 356547 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356549 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356553 */   GIR_RootConstrainSelectedInstOperands,
     /* 356554 */   // GIR_Coverage, 5596,
     /* 356554 */   GIR_EraseRootFromParent_Done,
     /* 356555 */ // Label 7057: @356555
     /* 356555 */ GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(356592), // Rule ID 5599 //
     /* 356560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356567 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356571 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 356575 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356579 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356581 */   // (fp_to_sint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 356584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356586 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356590 */   GIR_RootConstrainSelectedInstOperands,
     /* 356591 */   // GIR_Coverage, 5599,
     /* 356591 */   GIR_EraseRootFromParent_Done,
     /* 356592 */ // Label 7058: @356592
     /* 356592 */ GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(356629), // Rule ID 5713 //
     /* 356597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356604 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356608 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 356612 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356616 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356618 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 356621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356623 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356627 */   GIR_RootConstrainSelectedInstOperands,
     /* 356628 */   // GIR_Coverage, 5713,
     /* 356628 */   GIR_EraseRootFromParent_Done,
     /* 356629 */ // Label 7059: @356629
     /* 356629 */ GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(356666), // Rule ID 5715 //
     /* 356634 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356641 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356645 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 356649 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356653 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356655 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356655 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 356658 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356660 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356664 */   GIR_RootConstrainSelectedInstOperands,
     /* 356665 */   // GIR_Coverage, 5715,
     /* 356665 */   GIR_EraseRootFromParent_Done,
     /* 356666 */ // Label 7060: @356666
     /* 356666 */ GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(356706), // Rule ID 5716 //
     /* 356671 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 356674 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356677 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356681 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356685 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 356689 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356693 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356695 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356695 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 356698 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356700 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356704 */   GIR_RootConstrainSelectedInstOperands,
     /* 356705 */   // GIR_Coverage, 5716,
     /* 356705 */   GIR_EraseRootFromParent_Done,
     /* 356706 */ // Label 7061: @356706
     /* 356706 */ GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(356743), // Rule ID 5719 //
     /* 356711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356718 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356722 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 356726 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356730 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356732 */   // (fp_to_sint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356732 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 356735 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356737 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356741 */   GIR_RootConstrainSelectedInstOperands,
     /* 356742 */   // GIR_Coverage, 5719,
     /* 356742 */   GIR_EraseRootFromParent_Done,
     /* 356743 */ // Label 7062: @356743
     /* 356743 */ GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(356780), // Rule ID 5653 //
     /* 356748 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356751 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356755 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356759 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356763 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356767 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356769 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 356772 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356774 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356778 */   GIR_RootConstrainSelectedInstOperands,
     /* 356779 */   // GIR_Coverage, 5653,
     /* 356779 */   GIR_EraseRootFromParent_Done,
     /* 356780 */ // Label 7063: @356780
     /* 356780 */ GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(356817), // Rule ID 5655 //
     /* 356785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356792 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356796 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356800 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356804 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356806 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356806 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 356809 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356811 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356815 */   GIR_RootConstrainSelectedInstOperands,
     /* 356816 */   // GIR_Coverage, 5655,
     /* 356816 */   GIR_EraseRootFromParent_Done,
     /* 356817 */ // Label 7064: @356817
     /* 356817 */ GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(356857), // Rule ID 5656 //
     /* 356822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 356825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356832 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356836 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356840 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 356844 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356846 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 356846 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 356849 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356851 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356855 */   GIR_RootConstrainSelectedInstOperands,
     /* 356856 */   // GIR_Coverage, 5656,
     /* 356856 */   GIR_EraseRootFromParent_Done,
     /* 356857 */ // Label 7065: @356857
     /* 356857 */ GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(356894), // Rule ID 5659 //
     /* 356862 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356865 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356869 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 356873 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 356877 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 356881 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 356883 */   // (fp_to_sint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 356883 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 356886 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 356888 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 356892 */   GIR_RootConstrainSelectedInstOperands,
     /* 356893 */   // GIR_Coverage, 5659,
     /* 356893 */   GIR_EraseRootFromParent_Done,
     /* 356894 */ // Label 7066: @356894
     /* 356894 */ GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(356924), // Rule ID 391 //
     /* 356899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 356902 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 356905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356909 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 356913 */   // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 356913 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 356918 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356922 */   GIR_RootConstrainSelectedInstOperands,
     /* 356923 */   // GIR_Coverage, 391,
     /* 356923 */   GIR_Done,
     /* 356924 */ // Label 7067: @356924
     /* 356924 */ GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(356954), // Rule ID 395 //
     /* 356929 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 356932 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 356935 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356939 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 356943 */   // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 356943 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 356948 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356952 */   GIR_RootConstrainSelectedInstOperands,
     /* 356953 */   // GIR_Coverage, 395,
     /* 356953 */   GIR_Done,
     /* 356954 */ // Label 7068: @356954
     /* 356954 */ GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(356984), // Rule ID 399 //
     /* 356959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 356962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 356965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 356969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356973 */   // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 356973 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 356978 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 356982 */   GIR_RootConstrainSelectedInstOperands,
     /* 356983 */   // GIR_Coverage, 399,
     /* 356983 */   GIR_Done,
     /* 356984 */ // Label 7069: @356984
     /* 356984 */ GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(357014), // Rule ID 473 //
     /* 356989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 356992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 356995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 356999 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 357003 */   // (fp_to_sint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZSDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 357003 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 357008 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357012 */   GIR_RootConstrainSelectedInstOperands,
     /* 357013 */   // GIR_Coverage, 473,
     /* 357013 */   GIR_Done,
     /* 357014 */ // Label 7070: @357014
     /* 357014 */ GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(357044), // Rule ID 475 //
     /* 357019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 357022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357029 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357033 */   // (fp_to_sint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZSDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 357033 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 357038 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357042 */   GIR_RootConstrainSelectedInstOperands,
     /* 357043 */   // GIR_Coverage, 475,
     /* 357043 */   GIR_Done,
     /* 357044 */ // Label 7071: @357044
     /* 357044 */ GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(357074), // Rule ID 1686 //
     /* 357049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 357052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357059 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357063 */   // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 357063 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 357068 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357072 */   GIR_RootConstrainSelectedInstOperands,
     /* 357073 */   // GIR_Coverage, 1686,
     /* 357073 */   GIR_Done,
     /* 357074 */ // Label 7072: @357074
     /* 357074 */ GIM_Reject,
     /* 357075 */ // Label 7022: @357075
     /* 357075 */ GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(357105), // Rule ID 873 //
     /* 357080 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 357083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 357086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357090 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357094 */   // (fp_to_sint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 357094 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 357099 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357103 */   GIR_RootConstrainSelectedInstOperands,
     /* 357104 */   // GIR_Coverage, 873,
     /* 357104 */   GIR_Done,
     /* 357105 */ // Label 7073: @357105
     /* 357105 */ GIM_Reject,
     /* 357106 */ // Label 7023: @357106
     /* 357106 */ GIM_Try, /*On fail goto*//*Label 7074*/ GIMT_Encode4(357136), // Rule ID 877 //
     /* 357111 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 357114 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 357117 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357121 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357125 */   // (fp_to_sint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 357125 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 357130 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357134 */   GIR_RootConstrainSelectedInstOperands,
     /* 357135 */   // GIR_Coverage, 877,
     /* 357135 */   GIR_Done,
     /* 357136 */ // Label 7074: @357136
     /* 357136 */ GIM_Reject,
     /* 357137 */ // Label 7024: @357137
     /* 357137 */ GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(357167), // Rule ID 869 //
     /* 357142 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 357145 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 357148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357152 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357156 */   // (fp_to_sint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 357156 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 357161 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357165 */   GIR_RootConstrainSelectedInstOperands,
     /* 357166 */   // GIR_Coverage, 869,
     /* 357166 */   GIR_Done,
     /* 357167 */ // Label 7075: @357167
     /* 357167 */ GIM_Reject,
     /* 357168 */ // Label 7025: @357168
     /* 357168 */ GIM_Try, /*On fail goto*//*Label 7076*/ GIMT_Encode4(357198), // Rule ID 875 //
     /* 357173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 357176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 357179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357183 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357187 */   // (fp_to_sint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 357187 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 357192 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357196 */   GIR_RootConstrainSelectedInstOperands,
     /* 357197 */   // GIR_Coverage, 875,
     /* 357197 */   GIR_Done,
     /* 357198 */ // Label 7076: @357198
     /* 357198 */ GIM_Reject,
     /* 357199 */ // Label 7026: @357199
     /* 357199 */ GIM_Try, /*On fail goto*//*Label 7077*/ GIMT_Encode4(357229), // Rule ID 871 //
     /* 357204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 357207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 357210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357214 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 357218 */   // (fp_to_sint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 357218 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 357223 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357227 */   GIR_RootConstrainSelectedInstOperands,
     /* 357228 */   // GIR_Coverage, 871,
     /* 357228 */   GIR_Done,
     /* 357229 */ // Label 7077: @357229
     /* 357229 */ GIM_Reject,
     /* 357230 */ // Label 7027: @357230
     /* 357230 */ GIM_Reject,
     /* 357231 */ // Label 77: @357231
     /* 357231 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7086*/ GIMT_Encode4(359038),
     /* 357242 */ /*GILLT_s16*//*Label 7078*/ GIMT_Encode4(357282),
     /* 357246 */ /*GILLT_s32*//*Label 7079*/ GIMT_Encode4(357313),
     /* 357250 */ /*GILLT_s64*//*Label 7080*/ GIMT_Encode4(358098), GIMT_Encode4(0),
     /* 357258 */ /*GILLT_v2s32*//*Label 7081*/ GIMT_Encode4(358883),
     /* 357262 */ /*GILLT_v2s64*//*Label 7082*/ GIMT_Encode4(358914),
     /* 357266 */ /*GILLT_v4s16*//*Label 7083*/ GIMT_Encode4(358945),
     /* 357270 */ /*GILLT_v4s32*//*Label 7084*/ GIMT_Encode4(358976), GIMT_Encode4(0),
     /* 357278 */ /*GILLT_v8s16*//*Label 7085*/ GIMT_Encode4(359007),
     /* 357282 */ // Label 7078: @357282
     /* 357282 */ GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(357312), // Rule ID 1696 //
     /* 357287 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 357290 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 357293 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 357297 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 357301 */   // (fp_to_uint:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUv1f16:{ *:[i16] } FPR16:{ *:[f16] }:$Rn)
     /* 357301 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1f16),
     /* 357306 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357310 */   GIR_RootConstrainSelectedInstOperands,
     /* 357311 */   // GIR_Coverage, 1696,
     /* 357311 */   GIR_Done,
     /* 357312 */ // Label 7087: @357312
     /* 357312 */ GIM_Reject,
     /* 357313 */ // Label 7079: @357313
     /* 357313 */ GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(357350), // Rule ID 5562 //
     /* 357318 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357325 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357329 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 357333 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357337 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357339 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357339 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWSr),
     /* 357342 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357344 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357348 */   GIR_RootConstrainSelectedInstOperands,
     /* 357349 */   // GIR_Coverage, 5562,
     /* 357349 */   GIR_EraseRootFromParent_Done,
     /* 357350 */ // Label 7088: @357350
     /* 357350 */ GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(357387), // Rule ID 5564 //
     /* 357355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357362 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357366 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 357370 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357374 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357376 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUWDr),
     /* 357379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357381 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357385 */   GIR_RootConstrainSelectedInstOperands,
     /* 357386 */   // GIR_Coverage, 5564,
     /* 357386 */   GIR_EraseRootFromParent_Done,
     /* 357387 */ // Label 7089: @357387
     /* 357387 */ GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(357427), // Rule ID 5567 //
     /* 357392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 357395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357402 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357406 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 357410 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357414 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357416 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSDr),
     /* 357419 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357421 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357425 */   GIR_RootConstrainSelectedInstOperands,
     /* 357426 */   // GIR_Coverage, 5567,
     /* 357426 */   GIR_EraseRootFromParent_Done,
     /* 357427 */ // Label 7090: @357427
     /* 357427 */ GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(357464), // Rule ID 5568 //
     /* 357432 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357439 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357443 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 357447 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357451 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357453 */   // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i32),
     /* 357456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357458 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357462 */   GIR_RootConstrainSelectedInstOperands,
     /* 357463 */   // GIR_Coverage, 5568,
     /* 357463 */   GIR_EraseRootFromParent_Done,
     /* 357464 */ // Label 7091: @357464
     /* 357464 */ GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(357501), // Rule ID 5622 //
     /* 357469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357476 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357480 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 357484 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357488 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357490 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWSr),
     /* 357493 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357495 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357499 */   GIR_RootConstrainSelectedInstOperands,
     /* 357500 */   // GIR_Coverage, 5622,
     /* 357500 */   GIR_EraseRootFromParent_Done,
     /* 357501 */ // Label 7092: @357501
     /* 357501 */ GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(357538), // Rule ID 5624 //
     /* 357506 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357513 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357517 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 357521 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357525 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357527 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357527 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUWDr),
     /* 357530 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357532 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357536 */   GIR_RootConstrainSelectedInstOperands,
     /* 357537 */   // GIR_Coverage, 5624,
     /* 357537 */   GIR_EraseRootFromParent_Done,
     /* 357538 */ // Label 7093: @357538
     /* 357538 */ GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(357578), // Rule ID 5627 //
     /* 357543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 357546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357553 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357557 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 357561 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357565 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357567 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSDr),
     /* 357570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357572 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357576 */   GIR_RootConstrainSelectedInstOperands,
     /* 357577 */   // GIR_Coverage, 5627,
     /* 357577 */   GIR_EraseRootFromParent_Done,
     /* 357578 */ // Label 7094: @357578
     /* 357578 */ GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(357615), // Rule ID 5628 //
     /* 357583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357590 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357594 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 357598 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357602 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357604 */   // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357604 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i32),
     /* 357607 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357609 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357613 */   GIR_RootConstrainSelectedInstOperands,
     /* 357614 */   // GIR_Coverage, 5628,
     /* 357614 */   GIR_EraseRootFromParent_Done,
     /* 357615 */ // Label 7095: @357615
     /* 357615 */ GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(357652), // Rule ID 5742 //
     /* 357620 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357627 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357631 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 357635 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357639 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357641 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWSr),
     /* 357644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357646 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357650 */   GIR_RootConstrainSelectedInstOperands,
     /* 357651 */   // GIR_Coverage, 5742,
     /* 357651 */   GIR_EraseRootFromParent_Done,
     /* 357652 */ // Label 7096: @357652
     /* 357652 */ GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(357689), // Rule ID 5744 //
     /* 357657 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357664 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357668 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 357672 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357676 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357678 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357678 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUWDr),
     /* 357681 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357683 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357687 */   GIR_RootConstrainSelectedInstOperands,
     /* 357688 */   // GIR_Coverage, 5744,
     /* 357688 */   GIR_EraseRootFromParent_Done,
     /* 357689 */ // Label 7097: @357689
     /* 357689 */ GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(357729), // Rule ID 5747 //
     /* 357694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 357697 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357700 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357704 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357708 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 357712 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357716 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357718 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357718 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSDr),
     /* 357721 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357723 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357727 */   GIR_RootConstrainSelectedInstOperands,
     /* 357728 */   // GIR_Coverage, 5747,
     /* 357728 */   GIR_EraseRootFromParent_Done,
     /* 357729 */ // Label 7098: @357729
     /* 357729 */ GIM_Try, /*On fail goto*//*Label 7099*/ GIMT_Encode4(357766), // Rule ID 5748 //
     /* 357734 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357737 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357741 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357745 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 357749 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357753 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357755 */   // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357755 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i32),
     /* 357758 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357760 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357764 */   GIR_RootConstrainSelectedInstOperands,
     /* 357765 */   // GIR_Coverage, 5748,
     /* 357765 */   GIR_EraseRootFromParent_Done,
     /* 357766 */ // Label 7099: @357766
     /* 357766 */ GIM_Try, /*On fail goto*//*Label 7100*/ GIMT_Encode4(357803), // Rule ID 5682 //
     /* 357771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357778 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357782 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 357786 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357790 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357792 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 357795 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357797 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357801 */   GIR_RootConstrainSelectedInstOperands,
     /* 357802 */   // GIR_Coverage, 5682,
     /* 357802 */   GIR_EraseRootFromParent_Done,
     /* 357803 */ // Label 7100: @357803
     /* 357803 */ GIM_Try, /*On fail goto*//*Label 7101*/ GIMT_Encode4(357840), // Rule ID 5684 //
     /* 357808 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357815 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357819 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 357823 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357827 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357829 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 357832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357834 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357838 */   GIR_RootConstrainSelectedInstOperands,
     /* 357839 */   // GIR_Coverage, 5684,
     /* 357839 */   GIR_EraseRootFromParent_Done,
     /* 357840 */ // Label 7101: @357840
     /* 357840 */ GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(357880), // Rule ID 5687 //
     /* 357845 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 357848 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357855 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357859 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 357863 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 357867 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357869 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 357869 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 357872 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357874 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357878 */   GIR_RootConstrainSelectedInstOperands,
     /* 357879 */   // GIR_Coverage, 5687,
     /* 357879 */   GIR_EraseRootFromParent_Done,
     /* 357880 */ // Label 7102: @357880
     /* 357880 */ GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(357917), // Rule ID 5688 //
     /* 357885 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357892 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 357896 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 357900 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 357904 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 357906 */   // (fp_to_uint:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 357906 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 357909 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 357911 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 357915 */   GIR_RootConstrainSelectedInstOperands,
     /* 357916 */   // GIR_Coverage, 5688,
     /* 357916 */   GIR_EraseRootFromParent_Done,
     /* 357917 */ // Label 7103: @357917
     /* 357917 */ GIM_Try, /*On fail goto*//*Label 7104*/ GIMT_Encode4(357947), // Rule ID 401 //
     /* 357922 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 357925 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 357928 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357932 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 357936 */   // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 357936 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 357941 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357945 */   GIR_RootConstrainSelectedInstOperands,
     /* 357946 */   // GIR_Coverage, 401,
     /* 357946 */   GIR_Done,
     /* 357947 */ // Label 7104: @357947
     /* 357947 */ GIM_Try, /*On fail goto*//*Label 7105*/ GIMT_Encode4(357977), // Rule ID 405 //
     /* 357952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 357955 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 357958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357962 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 357966 */   // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 357966 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 357971 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 357975 */   GIR_RootConstrainSelectedInstOperands,
     /* 357976 */   // GIR_Coverage, 405,
     /* 357976 */   GIR_Done,
     /* 357977 */ // Label 7105: @357977
     /* 357977 */ GIM_Try, /*On fail goto*//*Label 7106*/ GIMT_Encode4(358007), // Rule ID 409 //
     /* 357982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 357985 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 357988 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 357992 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 357996 */   // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 357996 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 358001 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358005 */   GIR_RootConstrainSelectedInstOperands,
     /* 358006 */   // GIR_Coverage, 409,
     /* 358006 */   GIR_Done,
     /* 358007 */ // Label 7106: @358007
     /* 358007 */ GIM_Try, /*On fail goto*//*Label 7107*/ GIMT_Encode4(358037), // Rule ID 477 //
     /* 358012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 358015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358026 */   // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUSDr:{ *:[i32] } FPR64:{ *:[f64] }:$Rn)
     /* 358026 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 358031 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358035 */   GIR_RootConstrainSelectedInstOperands,
     /* 358036 */   // GIR_Coverage, 477,
     /* 358036 */   GIR_Done,
     /* 358037 */ // Label 7107: @358037
     /* 358037 */ GIM_Try, /*On fail goto*//*Label 7108*/ GIMT_Encode4(358067), // Rule ID 479 //
     /* 358042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 358045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 358048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358052 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 358056 */   // (fp_to_uint:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUSHr:{ *:[i32] } FPR16:{ *:[f16] }:$Rn)
     /* 358056 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 358061 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358065 */   GIR_RootConstrainSelectedInstOperands,
     /* 358066 */   // GIR_Coverage, 479,
     /* 358066 */   GIR_Done,
     /* 358067 */ // Label 7108: @358067
     /* 358067 */ GIM_Try, /*On fail goto*//*Label 7109*/ GIMT_Encode4(358097), // Rule ID 1694 //
     /* 358072 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 358075 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358082 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358086 */   // (fp_to_uint:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUv1i32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn)
     /* 358086 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 358091 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358095 */   GIR_RootConstrainSelectedInstOperands,
     /* 358096 */   // GIR_Coverage, 1694,
     /* 358096 */   GIR_Done,
     /* 358097 */ // Label 7109: @358097
     /* 358097 */ GIM_Reject,
     /* 358098 */ // Label 7080: @358098
     /* 358098 */ GIM_Try, /*On fail goto*//*Label 7110*/ GIMT_Encode4(358135), // Rule ID 5563 //
     /* 358103 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358106 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358110 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358114 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 358118 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358122 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358124 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358124 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXSr),
     /* 358127 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358129 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358133 */   GIR_RootConstrainSelectedInstOperands,
     /* 358134 */   // GIR_Coverage, 5563,
     /* 358134 */   GIR_EraseRootFromParent_Done,
     /* 358135 */ // Label 7110: @358135
     /* 358135 */ GIM_Try, /*On fail goto*//*Label 7111*/ GIMT_Encode4(358172), // Rule ID 5565 //
     /* 358140 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358147 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358151 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 358155 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358159 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358161 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUUXDr),
     /* 358164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358166 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358170 */   GIR_RootConstrainSelectedInstOperands,
     /* 358171 */   // GIR_Coverage, 5565,
     /* 358171 */   GIR_EraseRootFromParent_Done,
     /* 358172 */ // Label 7111: @358172
     /* 358172 */ GIM_Try, /*On fail goto*//*Label 7112*/ GIMT_Encode4(358212), // Rule ID 5566 //
     /* 358177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 358180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358187 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358191 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 358195 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358199 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358201 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDSr),
     /* 358204 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358206 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358210 */   GIR_RootConstrainSelectedInstOperands,
     /* 358211 */   // GIR_Coverage, 5566,
     /* 358211 */   GIR_EraseRootFromParent_Done,
     /* 358212 */ // Label 7112: @358212
     /* 358212 */ GIM_Try, /*On fail goto*//*Label 7113*/ GIMT_Encode4(358249), // Rule ID 5569 //
     /* 358217 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358220 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358224 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358228 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 358232 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358236 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358238 */   // (fp_to_uint:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358238 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 358241 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358243 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358247 */   GIR_RootConstrainSelectedInstOperands,
     /* 358248 */   // GIR_Coverage, 5569,
     /* 358248 */   GIR_EraseRootFromParent_Done,
     /* 358249 */ // Label 7113: @358249
     /* 358249 */ GIM_Try, /*On fail goto*//*Label 7114*/ GIMT_Encode4(358286), // Rule ID 5623 //
     /* 358254 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358261 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358265 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 358269 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358273 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358275 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358275 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXSr),
     /* 358278 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358280 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358284 */   GIR_RootConstrainSelectedInstOperands,
     /* 358285 */   // GIR_Coverage, 5623,
     /* 358285 */   GIR_EraseRootFromParent_Done,
     /* 358286 */ // Label 7114: @358286
     /* 358286 */ GIM_Try, /*On fail goto*//*Label 7115*/ GIMT_Encode4(358323), // Rule ID 5625 //
     /* 358291 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358298 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358302 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 358306 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358310 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358312 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358312 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUUXDr),
     /* 358315 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358317 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358321 */   GIR_RootConstrainSelectedInstOperands,
     /* 358322 */   // GIR_Coverage, 5625,
     /* 358322 */   GIR_EraseRootFromParent_Done,
     /* 358323 */ // Label 7115: @358323
     /* 358323 */ GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(358363), // Rule ID 5626 //
     /* 358328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 358331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358334 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358338 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358342 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 358346 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358350 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358352 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358352 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDSr),
     /* 358355 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358357 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358361 */   GIR_RootConstrainSelectedInstOperands,
     /* 358362 */   // GIR_Coverage, 5626,
     /* 358362 */   GIR_EraseRootFromParent_Done,
     /* 358363 */ // Label 7116: @358363
     /* 358363 */ GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(358400), // Rule ID 5629 //
     /* 358368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358375 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358379 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 358383 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358387 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358389 */   // (fp_to_uint:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358389 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 358392 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358394 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358398 */   GIR_RootConstrainSelectedInstOperands,
     /* 358399 */   // GIR_Coverage, 5629,
     /* 358399 */   GIR_EraseRootFromParent_Done,
     /* 358400 */ // Label 7117: @358400
     /* 358400 */ GIM_Try, /*On fail goto*//*Label 7118*/ GIMT_Encode4(358437), // Rule ID 5743 //
     /* 358405 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358412 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358416 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 358420 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358424 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358426 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXSr),
     /* 358429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358431 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358435 */   GIR_RootConstrainSelectedInstOperands,
     /* 358436 */   // GIR_Coverage, 5743,
     /* 358436 */   GIR_EraseRootFromParent_Done,
     /* 358437 */ // Label 7118: @358437
     /* 358437 */ GIM_Try, /*On fail goto*//*Label 7119*/ GIMT_Encode4(358474), // Rule ID 5745 //
     /* 358442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358449 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358453 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 358457 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358461 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358463 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUUXDr),
     /* 358466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358468 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358472 */   GIR_RootConstrainSelectedInstOperands,
     /* 358473 */   // GIR_Coverage, 5745,
     /* 358473 */   GIR_EraseRootFromParent_Done,
     /* 358474 */ // Label 7119: @358474
     /* 358474 */ GIM_Try, /*On fail goto*//*Label 7120*/ GIMT_Encode4(358514), // Rule ID 5746 //
     /* 358479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 358482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358489 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358493 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 358497 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358501 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358503 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358503 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDSr),
     /* 358506 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358508 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358512 */   GIR_RootConstrainSelectedInstOperands,
     /* 358513 */   // GIR_Coverage, 5746,
     /* 358513 */   GIR_EraseRootFromParent_Done,
     /* 358514 */ // Label 7120: @358514
     /* 358514 */ GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(358551), // Rule ID 5749 //
     /* 358519 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358526 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358530 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 358534 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358538 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358540 */   // (fp_to_uint:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358540 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 358543 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358545 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358549 */   GIR_RootConstrainSelectedInstOperands,
     /* 358550 */   // GIR_Coverage, 5749,
     /* 358550 */   GIR_EraseRootFromParent_Done,
     /* 358551 */ // Label 7121: @358551
     /* 358551 */ GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(358588), // Rule ID 5683 //
     /* 358556 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358563 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358567 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 358571 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358575 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358577 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358577 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 358580 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358582 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358586 */   GIR_RootConstrainSelectedInstOperands,
     /* 358587 */   // GIR_Coverage, 5683,
     /* 358587 */   GIR_EraseRootFromParent_Done,
     /* 358588 */ // Label 7122: @358588
     /* 358588 */ GIM_Try, /*On fail goto*//*Label 7123*/ GIMT_Encode4(358625), // Rule ID 5685 //
     /* 358593 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358600 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358604 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 358608 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358612 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358614 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358614 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 358617 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358619 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358623 */   GIR_RootConstrainSelectedInstOperands,
     /* 358624 */   // GIR_Coverage, 5685,
     /* 358624 */   GIR_EraseRootFromParent_Done,
     /* 358625 */ // Label 7123: @358625
     /* 358625 */ GIM_Try, /*On fail goto*//*Label 7124*/ GIMT_Encode4(358665), // Rule ID 5686 //
     /* 358630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 358633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358640 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358644 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 358648 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 358652 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358654 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 358654 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 358657 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358659 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358663 */   GIR_RootConstrainSelectedInstOperands,
     /* 358664 */   // GIR_Coverage, 5686,
     /* 358664 */   GIR_EraseRootFromParent_Done,
     /* 358665 */ // Label 7124: @358665
     /* 358665 */ GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(358702), // Rule ID 5689 //
     /* 358670 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358677 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 358681 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 358685 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 358689 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 358691 */   // (fp_to_uint:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 358691 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 358694 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 358696 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 358700 */   GIR_RootConstrainSelectedInstOperands,
     /* 358701 */   // GIR_Coverage, 5689,
     /* 358701 */   GIR_EraseRootFromParent_Done,
     /* 358702 */ // Label 7125: @358702
     /* 358702 */ GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(358732), // Rule ID 403 //
     /* 358707 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 358710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 358713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358717 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 358721 */   // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 358721 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 358726 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358730 */   GIR_RootConstrainSelectedInstOperands,
     /* 358731 */   // GIR_Coverage, 403,
     /* 358731 */   GIR_Done,
     /* 358732 */ // Label 7126: @358732
     /* 358732 */ GIM_Try, /*On fail goto*//*Label 7127*/ GIMT_Encode4(358762), // Rule ID 407 //
     /* 358737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 358740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358747 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358751 */   // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 358751 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 358756 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358760 */   GIR_RootConstrainSelectedInstOperands,
     /* 358761 */   // GIR_Coverage, 407,
     /* 358761 */   GIR_Done,
     /* 358762 */ // Label 7127: @358762
     /* 358762 */ GIM_Try, /*On fail goto*//*Label 7128*/ GIMT_Encode4(358792), // Rule ID 411 //
     /* 358767 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 358770 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 358777 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358781 */   // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 358781 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 358786 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358790 */   GIR_RootConstrainSelectedInstOperands,
     /* 358791 */   // GIR_Coverage, 411,
     /* 358791 */   GIR_Done,
     /* 358792 */ // Label 7128: @358792
     /* 358792 */ GIM_Try, /*On fail goto*//*Label 7129*/ GIMT_Encode4(358822), // Rule ID 481 //
     /* 358797 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 358800 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 358803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358807 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 358811 */   // (fp_to_uint:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)  =>  (FCVTZUDHr:{ *:[i64] } FPR16:{ *:[f16] }:$Rn)
     /* 358811 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 358816 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358820 */   GIR_RootConstrainSelectedInstOperands,
     /* 358821 */   // GIR_Coverage, 481,
     /* 358821 */   GIR_Done,
     /* 358822 */ // Label 7129: @358822
     /* 358822 */ GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(358852), // Rule ID 483 //
     /* 358827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 358830 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 358833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358837 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 358841 */   // (fp_to_uint:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)  =>  (FCVTZUDSr:{ *:[i64] } FPR32:{ *:[f32] }:$Rn)
     /* 358841 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 358846 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358850 */   GIR_RootConstrainSelectedInstOperands,
     /* 358851 */   // GIR_Coverage, 483,
     /* 358851 */   GIR_Done,
     /* 358852 */ // Label 7130: @358852
     /* 358852 */ GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(358882), // Rule ID 1692 //
     /* 358857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 358860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 358863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358871 */   // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTZUv1i64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn)
     /* 358871 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 358876 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358880 */   GIR_RootConstrainSelectedInstOperands,
     /* 358881 */   // GIR_Coverage, 1692,
     /* 358881 */   GIR_Done,
     /* 358882 */ // Label 7131: @358882
     /* 358882 */ GIM_Reject,
     /* 358883 */ // Label 7081: @358883
     /* 358883 */ GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(358913), // Rule ID 883 //
     /* 358888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 358891 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 358894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358898 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358902 */   // (fp_to_uint:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 358902 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 358907 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358911 */   GIR_RootConstrainSelectedInstOperands,
     /* 358912 */   // GIR_Coverage, 883,
     /* 358912 */   GIR_Done,
     /* 358913 */ // Label 7132: @358913
     /* 358913 */ GIM_Reject,
     /* 358914 */ // Label 7082: @358914
     /* 358914 */ GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(358944), // Rule ID 887 //
     /* 358919 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 358922 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 358925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 358929 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 358933 */   // (fp_to_uint:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 358933 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 358938 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358942 */   GIR_RootConstrainSelectedInstOperands,
     /* 358943 */   // GIR_Coverage, 887,
     /* 358943 */   GIR_Done,
     /* 358944 */ // Label 7133: @358944
     /* 358944 */ GIM_Reject,
     /* 358945 */ // Label 7083: @358945
     /* 358945 */ GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(358975), // Rule ID 879 //
     /* 358950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 358953 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 358956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358960 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 358964 */   // (fp_to_uint:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 358964 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 358969 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 358973 */   GIR_RootConstrainSelectedInstOperands,
     /* 358974 */   // GIR_Coverage, 879,
     /* 358974 */   GIR_Done,
     /* 358975 */ // Label 7134: @358975
     /* 358975 */ GIM_Reject,
     /* 358976 */ // Label 7084: @358976
     /* 358976 */ GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(359006), // Rule ID 885 //
     /* 358981 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 358984 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 358987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 358991 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 358995 */   // (fp_to_uint:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 358995 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 359000 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359004 */   GIR_RootConstrainSelectedInstOperands,
     /* 359005 */   // GIR_Coverage, 885,
     /* 359005 */   GIR_Done,
     /* 359006 */ // Label 7135: @359006
     /* 359006 */ GIM_Reject,
     /* 359007 */ // Label 7085: @359007
     /* 359007 */ GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(359037), // Rule ID 881 //
     /* 359012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 359015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 359018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359026 */   // (fp_to_uint:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 359026 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 359031 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359035 */   GIR_RootConstrainSelectedInstOperands,
     /* 359036 */   // GIR_Coverage, 881,
     /* 359036 */   GIR_Done,
     /* 359037 */ // Label 7136: @359037
     /* 359037 */ GIM_Reject,
     /* 359038 */ // Label 7086: @359038
     /* 359038 */ GIM_Reject,
     /* 359039 */ // Label 78: @359039
     /* 359039 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7145*/ GIMT_Encode4(363936),
     /* 359050 */ /*GILLT_s16*//*Label 7137*/ GIMT_Encode4(359090),
     /* 359054 */ /*GILLT_s32*//*Label 7138*/ GIMT_Encode4(359623),
     /* 359058 */ /*GILLT_s64*//*Label 7139*/ GIMT_Encode4(361708), GIMT_Encode4(0),
     /* 359066 */ /*GILLT_v2s32*//*Label 7140*/ GIMT_Encode4(363781),
     /* 359070 */ /*GILLT_v2s64*//*Label 7141*/ GIMT_Encode4(363812),
     /* 359074 */ /*GILLT_v4s16*//*Label 7142*/ GIMT_Encode4(363843),
     /* 359078 */ /*GILLT_v4s32*//*Label 7143*/ GIMT_Encode4(363874), GIMT_Encode4(0),
     /* 359086 */ /*GILLT_v8s16*//*Label 7144*/ GIMT_Encode4(363905),
     /* 359090 */ // Label 7137: @359090
     /* 359090 */ GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(359193), // Rule ID 5918 //
     /* 359095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 359098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359105 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359109 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
     /* 359113 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 359117 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 359121 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359125 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 359129 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 359133 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359138 */   GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 359142 */   // MIs[1] Operand 2
     /* 359142 */   GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
     /* 359153 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 359155 */   // (sint_to_fp:{ *:[f16] } (sext_inreg:{ *:[i32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), i16:{ *:[Other] }))  =>  (SCVTFv1i16:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR128:{ *:[v8i16] }:$Rn, hsub:{ *:[i32] }))
     /* 359155 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 359158 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359162 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359167 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 359173 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359178 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359183 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 359186 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359188 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359191 */   GIR_RootConstrainSelectedInstOperands,
     /* 359192 */   // GIR_Coverage, 5918,
     /* 359192 */   GIR_EraseRootFromParent_Done,
     /* 359193 */ // Label 7146: @359193
     /* 359193 */ GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(359273), // Rule ID 2481 //
     /* 359198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 359201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359208 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359212 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359216 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 359220 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359224 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359229 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 359233 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359235 */   // (sint_to_fp:{ *:[f16] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFHSr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 359235 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 359238 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359242 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359247 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 359253 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359258 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359263 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHSr),
     /* 359266 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359268 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359271 */   GIR_RootConstrainSelectedInstOperands,
     /* 359272 */   // GIR_Coverage, 2481,
     /* 359272 */   GIR_EraseRootFromParent_Done,
     /* 359273 */ // Label 7147: @359273
     /* 359273 */ GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(359353), // Rule ID 2485 //
     /* 359278 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 359281 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 359284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359288 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359292 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 359296 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 359300 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 359304 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359309 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 359313 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359315 */   // (sint_to_fp:{ *:[f16] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFHDr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 359315 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 359318 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359322 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359327 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 359333 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359338 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359343 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHDr),
     /* 359346 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359348 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359351 */   GIR_RootConstrainSelectedInstOperands,
     /* 359352 */   // GIR_Coverage, 2485,
     /* 359352 */   GIR_EraseRootFromParent_Done,
     /* 359353 */ // Label 7148: @359353
     /* 359353 */ GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(359412), // Rule ID 5901 //
     /* 359358 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 359361 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359368 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359372 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 359376 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 359380 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 359382 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359384 */   // (sint_to_fp:{ *:[f16] } (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$Rn)<<P:Predicate_any_fp_to_sint_oneuse>>)  =>  (SCVTFv1i16:{ *:[f16] } (FCVTZSv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
     /* 359384 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 359387 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1f16),
     /* 359391 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359396 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359400 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 359402 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 359405 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359407 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359410 */   GIR_RootConstrainSelectedInstOperands,
     /* 359411 */   // GIR_Coverage, 5901,
     /* 359411 */   GIR_EraseRootFromParent_Done,
     /* 359412 */ // Label 7149: @359412
     /* 359412 */ GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(359457), // Rule ID 5319 //
     /* 359417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 359420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359427 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359431 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 359435 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 359439 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359444 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359446 */   // (sint_to_fp:{ *:[f16] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (SCVTFHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)
     /* 359446 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHSr),
     /* 359449 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359451 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359455 */   GIR_RootConstrainSelectedInstOperands,
     /* 359456 */   // GIR_Coverage, 5319,
     /* 359456 */   GIR_EraseRootFromParent_Done,
     /* 359457 */ // Label 7150: @359457
     /* 359457 */ GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(359502), // Rule ID 5321 //
     /* 359462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 359465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 359468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359472 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359476 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 359480 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 359484 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359489 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359491 */   // (sint_to_fp:{ *:[f16] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (SCVTFHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)
     /* 359491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHDr),
     /* 359494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359496 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 359500 */   GIR_RootConstrainSelectedInstOperands,
     /* 359501 */   // GIR_Coverage, 5321,
     /* 359501 */   GIR_EraseRootFromParent_Done,
     /* 359502 */ // Label 7151: @359502
     /* 359502 */ GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(359532), // Rule ID 485 //
     /* 359507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 359510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 359521 */   // (sint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
     /* 359521 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWHri),
     /* 359526 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359530 */   GIR_RootConstrainSelectedInstOperands,
     /* 359531 */   // GIR_Coverage, 485,
     /* 359531 */   GIR_Done,
     /* 359532 */ // Label 7152: @359532
     /* 359532 */ GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(359562), // Rule ID 491 //
     /* 359537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 359540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 359543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359547 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 359551 */   // (sint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
     /* 359551 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXHri),
     /* 359556 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359560 */   GIR_RootConstrainSelectedInstOperands,
     /* 359561 */   // GIR_Coverage, 491,
     /* 359561 */   GIR_Done,
     /* 359562 */ // Label 7153: @359562
     /* 359562 */ GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(359592), // Rule ID 533 //
     /* 359567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 359570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359573 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359577 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359581 */   // (sint_to_fp:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)  =>  (SCVTFHSr:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)
     /* 359581 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHSr),
     /* 359586 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359590 */   GIR_RootConstrainSelectedInstOperands,
     /* 359591 */   // GIR_Coverage, 533,
     /* 359591 */   GIR_Done,
     /* 359592 */ // Label 7154: @359592
     /* 359592 */ GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(359622), // Rule ID 537 //
     /* 359597 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 359600 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 359603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 359607 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359611 */   // (sint_to_fp:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)  =>  (SCVTFHDr:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)
     /* 359611 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFHDr),
     /* 359616 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 359620 */   GIR_RootConstrainSelectedInstOperands,
     /* 359621 */   // GIR_Coverage, 537,
     /* 359621 */   GIR_Done,
     /* 359622 */ // Label 7155: @359622
     /* 359622 */ GIM_Reject,
     /* 359623 */ // Label 7138: @359623
     /* 359623 */ GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(359861), // Rule ID 7013 //
     /* 359628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 359631 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359634 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359638 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359642 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 359646 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359649 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 359656 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 359660 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359662 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 359669 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 359669 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 359672 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 359676 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359681 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 359686 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 359691 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 359696 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 359701 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 359703 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 359706 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 359710 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359715 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 359717 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 359720 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 359724 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359729 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 359732 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 359735 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 359738 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359743 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359748 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 359753 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 359756 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 359760 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359765 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 359768 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 359771 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 359773 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 359776 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359780 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359785 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 359792 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359797 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359802 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 359805 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 359809 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359814 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 359817 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 359820 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 359822 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 359825 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 359829 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359834 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 359841 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359846 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 359851 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 359854 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 359856 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 359859 */   GIR_RootConstrainSelectedInstOperands,
     /* 359860 */   // GIR_Coverage, 7013,
     /* 359860 */   GIR_EraseRootFromParent_Done,
     /* 359861 */ // Label 7156: @359861
     /* 359861 */ GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(360099), // Rule ID 7014 //
     /* 359866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 359869 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 359872 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 359876 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 359880 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 359884 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 359887 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 359894 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 359898 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 359900 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 359907 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$ext), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 359907 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 359910 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 359914 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359919 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 359924 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 359929 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 359934 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 359939 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 359941 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 359944 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 359948 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359953 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 359955 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 359958 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 359962 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 359967 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 359970 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 359973 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 359976 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359981 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 359986 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 359991 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 359994 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 359998 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360003 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 360006 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 360009 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 360011 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 360014 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360018 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360023 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360030 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360035 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360040 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360043 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 360047 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360052 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360055 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360058 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 360060 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 360063 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360067 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360072 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 360079 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360084 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360089 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 360092 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 360094 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360097 */   GIR_RootConstrainSelectedInstOperands,
     /* 360098 */   // GIR_Coverage, 7014,
     /* 360098 */   GIR_EraseRootFromParent_Done,
     /* 360099 */ // Label 7157: @360099
     /* 360099 */ GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(360288), // Rule ID 7017 //
     /* 360104 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 360107 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 360110 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360114 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360118 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 360122 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360125 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 360132 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 360136 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360138 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 360145 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 360145 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 360148 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 360152 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360157 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 360162 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 360167 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 360172 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 360177 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 360179 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 360182 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360186 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360191 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 360193 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 360196 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360200 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360205 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 360208 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 360211 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 360214 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360219 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360224 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 360229 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360232 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 360236 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360241 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360244 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360247 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 360249 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 360252 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360256 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360261 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 360268 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360273 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360278 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 360281 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 360283 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360286 */   GIR_RootConstrainSelectedInstOperands,
     /* 360287 */   // GIR_Coverage, 7017,
     /* 360287 */   GIR_EraseRootFromParent_Done,
     /* 360288 */ // Label 7158: @360288
     /* 360288 */ GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(360477), // Rule ID 7018 //
     /* 360293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 360296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 360299 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360303 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360307 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 360311 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360314 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 360321 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 360325 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360327 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 360334 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 360334 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 360337 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 360341 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360346 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 360351 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 360356 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 360361 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 360366 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 360368 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 360371 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360375 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360380 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 360382 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 360385 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360389 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360394 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 360397 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 360400 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 360403 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360408 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360413 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 360418 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360421 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 360425 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360430 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360433 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360436 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 360438 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 360441 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360445 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360450 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 360457 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360462 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360467 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 360470 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 360472 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360475 */   GIR_RootConstrainSelectedInstOperands,
     /* 360476 */   // GIR_Coverage, 7018,
     /* 360476 */   GIR_EraseRootFromParent_Done,
     /* 360477 */ // Label 7159: @360477
     /* 360477 */ GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(360710), // Rule ID 7015 //
     /* 360482 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 360485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 360488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360492 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360496 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 360500 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360503 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 360510 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 360514 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360516 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 360523 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 360523 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 360526 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 360530 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360535 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 360540 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 360545 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 360550 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 360552 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 360555 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360559 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360564 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 360566 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 360569 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360573 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360578 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 360581 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 360584 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 360587 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360592 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360597 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 360602 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 360605 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 360609 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360614 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 360617 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 360620 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 360622 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 360625 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360629 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360634 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360641 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360646 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360651 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360654 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 360658 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360663 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360666 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360669 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 360671 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 360674 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360678 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360683 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 360690 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360695 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 360703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 360705 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360708 */   GIR_RootConstrainSelectedInstOperands,
     /* 360709 */   // GIR_Coverage, 7015,
     /* 360709 */   GIR_EraseRootFromParent_Done,
     /* 360710 */ // Label 7160: @360710
     /* 360710 */ GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(360943), // Rule ID 7016 //
     /* 360715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 360718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 360721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360725 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360729 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 360733 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360736 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 360743 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 360747 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360749 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 360756 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv8i8_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 360756 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s8,
     /* 360759 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 360763 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 360773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 360778 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 360783 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 360785 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 360788 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 360792 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360797 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 360799 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 360802 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 360806 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360811 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 360814 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 360817 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/1,
     /* 360820 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360825 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360830 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 360835 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 360838 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv8i8_shift),
     /* 360842 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360847 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 360850 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 360853 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 360855 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 360858 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360862 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360867 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 360874 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 360879 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360884 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 360887 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 360891 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360896 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 360899 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 360902 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 360904 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 360907 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 360911 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 360916 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 360923 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360928 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 360933 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 360936 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 360938 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 360941 */   GIR_RootConstrainSelectedInstOperands,
     /* 360942 */   // GIR_Coverage, 7016,
     /* 360942 */   GIR_EraseRootFromParent_Done,
     /* 360943 */ // Label 7161: @360943
     /* 360943 */ GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(361127), // Rule ID 7019 //
     /* 360948 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 360951 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 360954 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 360958 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 360962 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 360966 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 360969 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 360976 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 360980 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 360982 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 360989 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 360989 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 360992 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 360996 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361001 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361006 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 361011 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 361016 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 361018 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 361021 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 361025 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361030 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 361032 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 361035 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 361039 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361044 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 361047 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 361050 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 361053 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361058 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361063 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 361068 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 361071 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 361075 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361080 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 361083 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 361086 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 361088 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 361091 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361095 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361100 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 361107 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361112 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 361120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361122 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361125 */   GIR_RootConstrainSelectedInstOperands,
     /* 361126 */   // GIR_Coverage, 7019,
     /* 361126 */   GIR_EraseRootFromParent_Done,
     /* 361127 */ // Label 7162: @361127
     /* 361127 */ GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(361311), // Rule ID 7020 //
     /* 361132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 361135 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361138 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361142 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361146 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 361150 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361153 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 361160 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 361164 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361166 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 361173 */   // (sint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[f32] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), ssub:{ *:[i32] }))
     /* 361173 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
     /* 361176 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 361180 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361185 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361190 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 361195 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 361200 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 361202 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 361205 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 361209 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361214 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 361216 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 361219 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 361223 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361228 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 361231 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 361234 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/9,
     /* 361237 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361242 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361247 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 361252 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 361255 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 361259 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361264 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 361267 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 361270 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 361272 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 361275 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361279 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361284 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 361291 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361296 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361301 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 361304 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361306 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361309 */   GIR_RootConstrainSelectedInstOperands,
     /* 361310 */   // GIR_Coverage, 7020,
     /* 361310 */   GIR_EraseRootFromParent_Done,
     /* 361311 */ // Label 7163: @361311
     /* 361311 */ GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(361391), // Rule ID 2487 //
     /* 361316 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 361319 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 361322 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361326 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361330 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 361334 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 361338 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 361342 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361347 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 361351 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361353 */   // (sint_to_fp:{ *:[f32] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFSDr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 361353 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361356 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361360 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361365 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 361371 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361376 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361381 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFSDr),
     /* 361384 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361386 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361389 */   GIR_RootConstrainSelectedInstOperands,
     /* 361390 */   // GIR_Coverage, 2487,
     /* 361390 */   GIR_EraseRootFromParent_Done,
     /* 361391 */ // Label 7164: @361391
     /* 361391 */ GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(361471), // Rule ID 5914 //
     /* 361396 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 361399 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361406 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361410 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 361414 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 361418 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 361422 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361427 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 361431 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361433 */   // (sint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 361433 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 361436 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361440 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361445 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 361451 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361456 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361461 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 361464 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361466 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361469 */   GIR_RootConstrainSelectedInstOperands,
     /* 361470 */   // GIR_Coverage, 5914,
     /* 361470 */   GIR_EraseRootFromParent_Done,
     /* 361471 */ // Label 7165: @361471
     /* 361471 */ GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(361530), // Rule ID 5889 //
     /* 361476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 361479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361486 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361490 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 361494 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 361498 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 361500 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361502 */   // (sint_to_fp:{ *:[f32] } (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$Rn)<<P:Predicate_any_fp_to_sint_oneuse>>)  =>  (SCVTFv1i32:{ *:[f32] } (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 361502 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 361505 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 361509 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361514 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 361518 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 361520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 361523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361525 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361528 */   GIR_RootConstrainSelectedInstOperands,
     /* 361529 */   // GIR_Coverage, 5889,
     /* 361529 */   GIR_EraseRootFromParent_Done,
     /* 361530 */ // Label 7166: @361530
     /* 361530 */ GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(361575), // Rule ID 5323 //
     /* 361535 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 361538 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 361541 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361545 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361549 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 361553 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 361557 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361562 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361564 */   // (sint_to_fp:{ *:[f32] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (SCVTFSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 361564 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFSDr),
     /* 361567 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361569 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 361573 */   GIR_RootConstrainSelectedInstOperands,
     /* 361574 */   // GIR_Coverage, 5323,
     /* 361574 */   GIR_EraseRootFromParent_Done,
     /* 361575 */ // Label 7167: @361575
     /* 361575 */ GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(361617), // Rule ID 5325 //
     /* 361580 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361587 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361591 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 361595 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 361599 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361604 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361606 */   // (sint_to_fp:{ *:[f32] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 361606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 361609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361611 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 361615 */   GIR_RootConstrainSelectedInstOperands,
     /* 361616 */   // GIR_Coverage, 5325,
     /* 361616 */   GIR_EraseRootFromParent_Done,
     /* 361617 */ // Label 7168: @361617
     /* 361617 */ GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(361647), // Rule ID 487 //
     /* 361622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 361625 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361632 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 361636 */   // (sint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
     /* 361636 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWSri),
     /* 361641 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 361645 */   GIR_RootConstrainSelectedInstOperands,
     /* 361646 */   // GIR_Coverage, 487,
     /* 361646 */   GIR_Done,
     /* 361647 */ // Label 7169: @361647
     /* 361647 */ GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(361677), // Rule ID 493 //
     /* 361652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 361655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 361658 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361662 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 361666 */   // (sint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
     /* 361666 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXSri),
     /* 361671 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 361675 */   GIR_RootConstrainSelectedInstOperands,
     /* 361676 */   // GIR_Coverage, 493,
     /* 361676 */   GIR_Done,
     /* 361677 */ // Label 7170: @361677
     /* 361677 */ GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(361707), // Rule ID 539 //
     /* 361682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 361685 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 361688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361692 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361696 */   // (sint_to_fp:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)  =>  (SCVTFSDr:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)
     /* 361696 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFSDr),
     /* 361701 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 361705 */   GIR_RootConstrainSelectedInstOperands,
     /* 361706 */   // GIR_Coverage, 539,
     /* 361706 */   GIR_Done,
     /* 361707 */ // Label 7171: @361707
     /* 361707 */ GIM_Reject,
     /* 361708 */ // Label 7139: @361708
     /* 361708 */ GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(361894), // Rule ID 7025 //
     /* 361713 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 361716 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361723 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361727 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361731 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361734 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 361738 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 361742 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361744 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 361751 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 361751 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 361754 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 361758 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361763 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361768 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361773 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 361778 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 361783 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 361785 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 361788 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 361792 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361797 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 361799 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 361802 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 361806 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361811 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 361814 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 361817 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 361820 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361825 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361830 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 361835 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 361838 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 361842 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361847 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 361850 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 361853 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 361855 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 361858 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 361862 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361867 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 361874 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361879 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 361884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 361887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 361889 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 361892 */   GIR_RootConstrainSelectedInstOperands,
     /* 361893 */   // GIR_Coverage, 7025,
     /* 361893 */   GIR_EraseRootFromParent_Done,
     /* 361894 */ // Label 7172: @361894
     /* 361894 */ GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(362080), // Rule ID 7026 //
     /* 361899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 361902 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 361905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 361909 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 361913 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 361917 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 361920 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 361924 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 361928 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 361930 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 361937 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$ext), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 361937 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 361940 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 361944 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361949 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 361954 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 361959 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 361964 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 361969 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 361971 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 361974 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 361978 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361983 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 361985 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 361988 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 361992 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 361997 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 362000 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 362003 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 362006 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362011 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362016 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 362021 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 362024 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 362028 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362033 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 362036 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 362039 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362041 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362044 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362048 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362053 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362060 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362065 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362070 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 362073 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 362075 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362078 */   GIR_RootConstrainSelectedInstOperands,
     /* 362079 */   // GIR_Coverage, 7026,
     /* 362079 */   GIR_EraseRootFromParent_Done,
     /* 362080 */ // Label 7173: @362080
     /* 362080 */ GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(362318), // Rule ID 7021 //
     /* 362085 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 362088 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 362091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362095 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362099 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 362103 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362106 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 362113 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 362117 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 362119 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 362126 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 362126 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 362129 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 362133 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 362148 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 362153 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 362158 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 362160 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 362163 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 362167 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362172 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 362174 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 362177 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 362181 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362186 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 362189 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 362192 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 362195 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362200 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362205 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 362210 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 362213 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 362217 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362222 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 362225 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 362228 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 362230 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 362233 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362237 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362242 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362249 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362254 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362259 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 362262 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 362266 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362271 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 362274 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 362277 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362279 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362282 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362286 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362291 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362298 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362303 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362308 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 362311 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 362313 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362316 */   GIR_RootConstrainSelectedInstOperands,
     /* 362317 */   // GIR_Coverage, 7021,
     /* 362317 */   GIR_EraseRootFromParent_Done,
     /* 362318 */ // Label 7174: @362318
     /* 362318 */ GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(362556), // Rule ID 7022 //
     /* 362323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 362326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 362329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362333 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362337 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 362341 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362344 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 362351 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 362355 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 362357 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 362364 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$ext), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 362364 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 362367 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 362371 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362376 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362381 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 362386 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // ext
     /* 362391 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 362396 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 362398 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 362401 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 362405 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362410 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 362412 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 362415 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 362419 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362424 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 362427 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 362430 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 362433 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362438 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362443 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 362448 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 362451 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 362455 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362460 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 362463 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 362466 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 362468 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 362471 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362475 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362480 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362487 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362492 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362497 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 362500 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 362504 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362509 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 362512 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 362515 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362517 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362520 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362524 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362529 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362536 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362541 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362546 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 362549 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 362551 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362554 */   GIR_RootConstrainSelectedInstOperands,
     /* 362555 */   // GIR_Coverage, 7022,
     /* 362555 */   GIR_EraseRootFromParent_Done,
     /* 362556 */ // Label 7175: @362556
     /* 362556 */ GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(362737), // Rule ID 7027 //
     /* 362561 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 362564 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 362567 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362571 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362575 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362579 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362582 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 362586 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 362590 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 362592 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 362599 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 362599 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 362602 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 362606 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362611 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362616 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362621 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 362626 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 362628 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 362631 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 362635 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362640 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 362642 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 362645 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 362649 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362654 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 362657 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 362660 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 362663 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362668 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362673 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 362678 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 362681 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 362685 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362690 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 362693 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 362696 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362698 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362701 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362705 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362710 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362717 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362722 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 362730 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 362732 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362735 */   GIR_RootConstrainSelectedInstOperands,
     /* 362736 */   // GIR_Coverage, 7027,
     /* 362736 */   GIR_EraseRootFromParent_Done,
     /* 362737 */ // Label 7176: @362737
     /* 362737 */ GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(362918), // Rule ID 7028 //
     /* 362742 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 362745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 362748 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362752 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362756 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 362760 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362763 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 362767 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 362771 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 362773 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 362780 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 362780 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 362783 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 362787 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362792 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362797 */   GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362802 */   GIR_MergeMemOperands, /*InsnID*/5, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 362807 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 362809 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 362812 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 362816 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362821 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 362823 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 362826 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 362830 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362835 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 362838 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
     /* 362841 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/18,
     /* 362844 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362849 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362854 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 362859 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 362862 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 362866 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362871 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 362874 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 362877 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 362879 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 362882 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 362886 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362891 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 362898 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362903 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 362908 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 362911 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 362913 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 362916 */   GIR_RootConstrainSelectedInstOperands,
     /* 362917 */   // GIR_Coverage, 7028,
     /* 362917 */   GIR_EraseRootFromParent_Done,
     /* 362918 */ // Label 7177: @362918
     /* 362918 */ GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(363151), // Rule ID 7023 //
     /* 362923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 362926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 362929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 362933 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 362937 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 362941 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 362944 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 362951 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 362955 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 362957 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 362964 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 362964 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 362967 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 362971 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 362976 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 362981 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 362986 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 362991 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 362993 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 362996 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 363000 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363005 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 363007 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 363010 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 363014 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363019 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 363022 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 363025 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 363028 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363033 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363038 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 363043 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 363046 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 363050 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363055 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 363058 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 363061 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 363063 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 363066 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363070 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363075 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 363082 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363087 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363092 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 363095 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 363099 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363104 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 363107 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 363110 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 363112 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 363115 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363119 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363124 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 363131 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363136 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363141 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 363144 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363146 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363149 */   GIR_RootConstrainSelectedInstOperands,
     /* 363150 */   // GIR_Coverage, 7023,
     /* 363150 */   GIR_EraseRootFromParent_Done,
     /* 363151 */ // Label 7178: @363151
     /* 363151 */ GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(363384), // Rule ID 7024 //
     /* 363156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_NotForCodeSize_UseAlternateSExtLoadCVTF32),
     /* 363159 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363162 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363166 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363170 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXTLOAD),
     /* 363174 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 363177 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 363184 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 363188 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363190 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 363197 */   // (sint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>)  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv2i32_shift:{ *:[f128] } (EXTRACT_SUBREG:{ *:[f64] } (SSHLLv4i16_shift:{ *:[f128] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }), 0:{ *:[i32] }), dsub:{ *:[i32] }))
     /* 363197 */   GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
     /* 363200 */   GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 363204 */   GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363209 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 363214 */   GIR_ComplexSubOperandRenderer, /*InsnID*/7, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 363219 */   GIR_MergeMemOperands, /*InsnID*/7, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 363224 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 363226 */   GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s64,
     /* 363229 */   GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 363233 */   GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363238 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
     /* 363240 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s64,
     /* 363243 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 363247 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363252 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 363255 */   GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
     /* 363258 */   GIR_AddImm8, /*InsnID*/5, /*Imm*/9,
     /* 363261 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363266 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363271 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 363276 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 363279 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv4i16_shift),
     /* 363283 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363288 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 363291 */   GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
     /* 363294 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 363296 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 363299 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363303 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363308 */   GIR_AddTempSubRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 363315 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363320 */   GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363325 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 363328 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SSHLLv2i32_shift),
     /* 363332 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363337 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 363340 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 363343 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 363345 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 363348 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363352 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363357 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 363364 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363369 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363374 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 363377 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363379 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363382 */   GIR_RootConstrainSelectedInstOperands,
     /* 363383 */   // GIR_Coverage, 7024,
     /* 363383 */   GIR_EraseRootFromParent_Done,
     /* 363384 */ // Label 7179: @363384
     /* 363384 */ GIM_Try, /*On fail goto*//*Label 7180*/ GIMT_Encode4(363464), // Rule ID 2483 //
     /* 363389 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 363392 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363395 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363399 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363403 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363407 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 363411 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363415 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363420 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 363424 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363426 */   // (sint_to_fp:{ *:[f64] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFDSr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 363426 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 363429 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363433 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363438 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 363444 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 363449 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363454 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 363457 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363459 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363462 */   GIR_RootConstrainSelectedInstOperands,
     /* 363463 */   // GIR_Coverage, 2483,
     /* 363463 */   GIR_EraseRootFromParent_Done,
     /* 363464 */ // Label 7180: @363464
     /* 363464 */ GIM_Try, /*On fail goto*//*Label 7181*/ GIMT_Encode4(363544), // Rule ID 5916 //
     /* 363469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 363472 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 363475 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363479 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363483 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 363487 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 363491 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 363495 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363500 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 363504 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363506 */   // (sint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (SCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 363506 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 363509 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 363513 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363518 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 363524 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363529 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363534 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 363537 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363539 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363542 */   GIR_RootConstrainSelectedInstOperands,
     /* 363543 */   // GIR_Coverage, 5916,
     /* 363543 */   GIR_EraseRootFromParent_Done,
     /* 363544 */ // Label 7181: @363544
     /* 363544 */ GIM_Try, /*On fail goto*//*Label 7182*/ GIMT_Encode4(363603), // Rule ID 5885 //
     /* 363549 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 363552 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 363555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363559 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363563 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOSI),
     /* 363567 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 363571 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 363573 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363575 */   // (sint_to_fp:{ *:[f64] } (fp_to_sint:{ *:[i64] } f64:{ *:[f64] }:$Rn)<<P:Predicate_any_fp_to_sint_oneuse>>)  =>  (SCVTFv1i64:{ *:[f64] } (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 363575 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 363578 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 363582 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 363587 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363591 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 363593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 363596 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363598 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 363601 */   GIR_RootConstrainSelectedInstOperands,
     /* 363602 */   // GIR_Coverage, 5885,
     /* 363602 */   GIR_EraseRootFromParent_Done,
     /* 363603 */ // Label 7182: @363603
     /* 363603 */ GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(363648), // Rule ID 5317 //
     /* 363608 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 363611 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363614 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363618 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363622 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 363626 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 363630 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 363635 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363637 */   // (sint_to_fp:{ *:[f64] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (SCVTFDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 363637 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 363640 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363642 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363646 */   GIR_RootConstrainSelectedInstOperands,
     /* 363647 */   // GIR_Coverage, 5317,
     /* 363647 */   GIR_EraseRootFromParent_Done,
     /* 363648 */ // Label 7183: @363648
     /* 363648 */ GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(363690), // Rule ID 5327 //
     /* 363653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 363656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363660 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 363664 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 363668 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 363672 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363677 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 363679 */   // (sint_to_fp:{ *:[f64] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 363679 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 363682 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 363684 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 363688 */   GIR_RootConstrainSelectedInstOperands,
     /* 363689 */   // GIR_Coverage, 5327,
     /* 363689 */   GIR_EraseRootFromParent_Done,
     /* 363690 */ // Label 7184: @363690
     /* 363690 */ GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(363720), // Rule ID 489 //
     /* 363695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 363698 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363701 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363705 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 363709 */   // (sint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)  =>  (SCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
     /* 363709 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUWDri),
     /* 363714 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363718 */   GIR_RootConstrainSelectedInstOperands,
     /* 363719 */   // GIR_Coverage, 489,
     /* 363719 */   GIR_Done,
     /* 363720 */ // Label 7185: @363720
     /* 363720 */ GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(363750), // Rule ID 495 //
     /* 363725 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 363728 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 363731 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363735 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 363739 */   // (sint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)  =>  (SCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
     /* 363739 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFUXDri),
     /* 363744 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363748 */   GIR_RootConstrainSelectedInstOperands,
     /* 363749 */   // GIR_Coverage, 495,
     /* 363749 */   GIR_Done,
     /* 363750 */ // Label 7186: @363750
     /* 363750 */ GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(363780), // Rule ID 535 //
     /* 363755 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 363758 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363761 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363765 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 363769 */   // (sint_to_fp:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)  =>  (SCVTFDSr:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)
     /* 363769 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 363774 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363778 */   GIR_RootConstrainSelectedInstOperands,
     /* 363779 */   // GIR_Coverage, 535,
     /* 363779 */   GIR_Done,
     /* 363780 */ // Label 7187: @363780
     /* 363780 */ GIM_Reject,
     /* 363781 */ // Label 7140: @363781
     /* 363781 */ GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(363811), // Rule ID 1047 //
     /* 363786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 363789 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 363792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363796 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363800 */   // (sint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)  =>  (SCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
     /* 363800 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f32),
     /* 363805 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363809 */   GIR_RootConstrainSelectedInstOperands,
     /* 363810 */   // GIR_Coverage, 1047,
     /* 363810 */   GIR_Done,
     /* 363811 */ // Label 7188: @363811
     /* 363811 */ GIM_Reject,
     /* 363812 */ // Label 7141: @363812
     /* 363812 */ GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(363842), // Rule ID 1051 //
     /* 363817 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 363820 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 363823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363827 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363831 */   // (sint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)  =>  (SCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
     /* 363831 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv2f64),
     /* 363836 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363840 */   GIR_RootConstrainSelectedInstOperands,
     /* 363841 */   // GIR_Coverage, 1051,
     /* 363841 */   GIR_Done,
     /* 363842 */ // Label 7189: @363842
     /* 363842 */ GIM_Reject,
     /* 363843 */ // Label 7142: @363843
     /* 363843 */ GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(363873), // Rule ID 1043 //
     /* 363848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 363851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 363854 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363858 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 363862 */   // (sint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)  =>  (SCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
     /* 363862 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f16),
     /* 363867 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363871 */   GIR_RootConstrainSelectedInstOperands,
     /* 363872 */   // GIR_Coverage, 1043,
     /* 363872 */   GIR_Done,
     /* 363873 */ // Label 7190: @363873
     /* 363873 */ GIM_Reject,
     /* 363874 */ // Label 7143: @363874
     /* 363874 */ GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(363904), // Rule ID 1049 //
     /* 363879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 363882 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 363885 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363889 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363893 */   // (sint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)  =>  (SCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
     /* 363893 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv4f32),
     /* 363898 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363902 */   GIR_RootConstrainSelectedInstOperands,
     /* 363903 */   // GIR_Coverage, 1049,
     /* 363903 */   GIR_Done,
     /* 363904 */ // Label 7191: @363904
     /* 363904 */ GIM_Reject,
     /* 363905 */ // Label 7144: @363905
     /* 363905 */ GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(363935), // Rule ID 1045 //
     /* 363910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 363913 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 363916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363920 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 363924 */   // (sint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)  =>  (SCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
     /* 363924 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv8f16),
     /* 363929 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 363933 */   GIR_RootConstrainSelectedInstOperands,
     /* 363934 */   // GIR_Coverage, 1045,
     /* 363934 */   GIR_Done,
     /* 363935 */ // Label 7192: @363935
     /* 363935 */ GIM_Reject,
     /* 363936 */ // Label 7145: @363936
     /* 363936 */ GIM_Reject,
     /* 363937 */ // Label 79: @363937
     /* 363937 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7201*/ GIMT_Encode4(368762),
     /* 363948 */ /*GILLT_s16*//*Label 7193*/ GIMT_Encode4(363988),
     /* 363952 */ /*GILLT_s32*//*Label 7194*/ GIMT_Encode4(365075),
     /* 363956 */ /*GILLT_s64*//*Label 7195*/ GIMT_Encode4(366572), GIMT_Encode4(0),
     /* 363964 */ /*GILLT_v2s32*//*Label 7196*/ GIMT_Encode4(368607),
     /* 363968 */ /*GILLT_v2s64*//*Label 7197*/ GIMT_Encode4(368638),
     /* 363972 */ /*GILLT_v4s16*//*Label 7198*/ GIMT_Encode4(368669),
     /* 363976 */ /*GILLT_v4s32*//*Label 7199*/ GIMT_Encode4(368700), GIMT_Encode4(0),
     /* 363984 */ /*GILLT_v8s16*//*Label 7200*/ GIMT_Encode4(368731),
     /* 363988 */ // Label 7193: @363988
     /* 363988 */ GIM_Try, /*On fail goto*//*Label 7202*/ GIMT_Encode4(364128), // Rule ID 5920 //
     /* 363993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 363996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 363999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364003 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364007 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 364011 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364014 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 364021 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 364025 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364027 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 364034 */   // (uint_to_fp:{ *:[f16] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i16:{ *:[f16] } (INSERT_SUBREG:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 364034 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 364037 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 364041 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364046 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364051 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364056 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364061 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 364066 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 364068 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 364071 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364075 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364080 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364082 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364085 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364089 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364094 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364097 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 364100 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 364103 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364108 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364113 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 364118 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364121 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364123 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364126 */   GIR_RootConstrainSelectedInstOperands,
     /* 364127 */   // GIR_Coverage, 5920,
     /* 364127 */   GIR_EraseRootFromParent_Done,
     /* 364128 */ // Label 7202: @364128
     /* 364128 */ GIM_Try, /*On fail goto*//*Label 7203*/ GIMT_Encode4(364268), // Rule ID 5921 //
     /* 364133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 364136 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364143 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364147 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 364151 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364154 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 364161 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 364165 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364167 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 364174 */   // (uint_to_fp:{ *:[f16] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i16:{ *:[f16] } (INSERT_SUBREG:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 364174 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 364177 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 364181 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364186 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364191 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 364196 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 364201 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 364206 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 364208 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 364211 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364215 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364220 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364222 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364225 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364229 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364234 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364237 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 364240 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 364243 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364248 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364253 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 364258 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364261 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364263 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364266 */   GIR_RootConstrainSelectedInstOperands,
     /* 364267 */   // GIR_Coverage, 5921,
     /* 364267 */   GIR_EraseRootFromParent_Done,
     /* 364268 */ // Label 7203: @364268
     /* 364268 */ GIM_Try, /*On fail goto*//*Label 7204*/ GIMT_Encode4(364375), // Rule ID 5919 //
     /* 364273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 364276 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364279 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364283 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364287 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 364291 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 364295 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 364299 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 364303 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 364307 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 364311 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 364315 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364320 */   GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 364324 */   GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
     /* 364335 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 364337 */   // (uint_to_fp:{ *:[f16] } (and:{ *:[i32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), 65535:{ *:[i32] }))  =>  (UCVTFv1i16:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } FPR128:{ *:[v8i16] }:$Rn, hsub:{ *:[i32] }))
     /* 364337 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364340 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 364344 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364349 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 364355 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364360 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364365 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364368 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364370 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364373 */   GIR_RootConstrainSelectedInstOperands,
     /* 364374 */   // GIR_Coverage, 5919,
     /* 364374 */   GIR_EraseRootFromParent_Done,
     /* 364375 */ // Label 7204: @364375
     /* 364375 */ GIM_Try, /*On fail goto*//*Label 7205*/ GIMT_Encode4(364510), // Rule ID 5922 //
     /* 364380 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 364383 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364386 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364390 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364394 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 364398 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364401 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 364408 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 364412 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364414 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 364421 */   // (uint_to_fp:{ *:[f16] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i16:{ *:[f16] } (INSERT_SUBREG:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
     /* 364421 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 364424 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 364428 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364433 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364438 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 364443 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 364448 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 364450 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 364453 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364457 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364462 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364464 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364467 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364471 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364476 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364479 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 364482 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 364485 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364490 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364495 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 364500 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364503 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364505 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364508 */   GIR_RootConstrainSelectedInstOperands,
     /* 364509 */   // GIR_Coverage, 5922,
     /* 364509 */   GIR_EraseRootFromParent_Done,
     /* 364510 */ // Label 7205: @364510
     /* 364510 */ GIM_Try, /*On fail goto*//*Label 7206*/ GIMT_Encode4(364645), // Rule ID 5923 //
     /* 364515 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 364518 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364525 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364529 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 364533 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 364536 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 364543 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 364547 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364549 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 364556 */   // (uint_to_fp:{ *:[f16] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i16:{ *:[f16] } (INSERT_SUBREG:{ *:[f16] } (IMPLICIT_DEF:{ *:[f16] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
     /* 364556 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 364559 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 364563 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364568 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 364573 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 364578 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 364583 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 364585 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 364588 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 364592 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364597 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 364599 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364602 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 364606 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364611 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 364614 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 364617 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 364620 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364625 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364630 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 364635 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364638 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364640 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364643 */   GIR_RootConstrainSelectedInstOperands,
     /* 364644 */   // GIR_Coverage, 5923,
     /* 364644 */   GIR_EraseRootFromParent_Done,
     /* 364645 */ // Label 7206: @364645
     /* 364645 */ GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(364725), // Rule ID 4823 //
     /* 364650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 364653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364660 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364664 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 364668 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 364672 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 364676 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364681 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 364685 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364687 */   // (uint_to_fp:{ *:[f16] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFHSr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 364687 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 364690 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 364694 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364699 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 364705 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 364710 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364715 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHSr),
     /* 364718 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364720 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364723 */   GIR_RootConstrainSelectedInstOperands,
     /* 364724 */   // GIR_Coverage, 4823,
     /* 364724 */   GIR_EraseRootFromParent_Done,
     /* 364725 */ // Label 7207: @364725
     /* 364725 */ GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(364805), // Rule ID 4827 //
     /* 364730 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 364733 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 364736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364740 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364744 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 364748 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 364752 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 364756 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364761 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 364765 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364767 */   // (uint_to_fp:{ *:[f16] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFHDr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 364767 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 364770 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 364774 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364779 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 364785 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364790 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 364795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHDr),
     /* 364798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364800 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364803 */   GIR_RootConstrainSelectedInstOperands,
     /* 364804 */   // GIR_Coverage, 4827,
     /* 364804 */   GIR_EraseRootFromParent_Done,
     /* 364805 */ // Label 7208: @364805
     /* 364805 */ GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(364864), // Rule ID 5905 //
     /* 364810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsSME2p2StreamingSafe),
     /* 364813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364820 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364824 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 364828 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 364832 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 364834 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364836 */   // (uint_to_fp:{ *:[f16] } (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$Rn)<<P:Predicate_any_fp_to_uint_oneuse>>)  =>  (UCVTFv1i16:{ *:[f16] } (FCVTZUv1f16:{ *:[f16] } f16:{ *:[f16] }:$Rn))
     /* 364836 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 364839 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1f16),
     /* 364843 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 364848 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 364852 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 364854 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 364857 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364859 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 364862 */   GIR_RootConstrainSelectedInstOperands,
     /* 364863 */   // GIR_Coverage, 5905,
     /* 364863 */   GIR_EraseRootFromParent_Done,
     /* 364864 */ // Label 7209: @364864
     /* 364864 */ GIM_Try, /*On fail goto*//*Label 7210*/ GIMT_Encode4(364909), // Rule ID 5331 //
     /* 364869 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 364872 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364875 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364879 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364883 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 364887 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 364891 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 364896 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364898 */   // (uint_to_fp:{ *:[f16] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (UCVTFHSr:{ *:[f16] } FPR32:{ *:[f32] }:$Rn)
     /* 364898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHSr),
     /* 364901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364903 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 364907 */   GIR_RootConstrainSelectedInstOperands,
     /* 364908 */   // GIR_Coverage, 5331,
     /* 364908 */   GIR_EraseRootFromParent_Done,
     /* 364909 */ // Label 7210: @364909
     /* 364909 */ GIM_Try, /*On fail goto*//*Label 7211*/ GIMT_Encode4(364954), // Rule ID 5333 //
     /* 364914 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 364917 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 364920 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364924 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 364928 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 364932 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 364936 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 364941 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 364943 */   // (uint_to_fp:{ *:[f16] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (UCVTFHDr:{ *:[f16] } FPR64:{ *:[f64] }:$Rn)
     /* 364943 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHDr),
     /* 364946 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 364948 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 364952 */   GIR_RootConstrainSelectedInstOperands,
     /* 364953 */   // GIR_Coverage, 5333,
     /* 364953 */   GIR_EraseRootFromParent_Done,
     /* 364954 */ // Label 7211: @364954
     /* 364954 */ GIM_Try, /*On fail goto*//*Label 7212*/ GIMT_Encode4(364984), // Rule ID 509 //
     /* 364959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 364962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 364965 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364969 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 364973 */   // (uint_to_fp:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWHri:{ *:[f16] } GPR32:{ *:[i32] }:$Rn)
     /* 364973 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWHri),
     /* 364978 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 364982 */   GIR_RootConstrainSelectedInstOperands,
     /* 364983 */   // GIR_Coverage, 509,
     /* 364983 */   GIR_Done,
     /* 364984 */ // Label 7212: @364984
     /* 364984 */ GIM_Try, /*On fail goto*//*Label 7213*/ GIMT_Encode4(365014), // Rule ID 515 //
     /* 364989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 364992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 364995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 364999 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 365003 */   // (uint_to_fp:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXHri:{ *:[f16] } GPR64:{ *:[i64] }:$Rn)
     /* 365003 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXHri),
     /* 365008 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 365012 */   GIR_RootConstrainSelectedInstOperands,
     /* 365013 */   // GIR_Coverage, 515,
     /* 365013 */   GIR_Done,
     /* 365014 */ // Label 7213: @365014
     /* 365014 */ GIM_Try, /*On fail goto*//*Label 7214*/ GIMT_Encode4(365044), // Rule ID 541 //
     /* 365019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 365022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365025 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365029 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365033 */   // (uint_to_fp:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)  =>  (UCVTFHSr:{ *:[f16] } FPR32:{ *:[i32] }:$Rn)
     /* 365033 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHSr),
     /* 365038 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 365042 */   GIR_RootConstrainSelectedInstOperands,
     /* 365043 */   // GIR_Coverage, 541,
     /* 365043 */   GIR_Done,
     /* 365044 */ // Label 7214: @365044
     /* 365044 */ GIM_Try, /*On fail goto*//*Label 7215*/ GIMT_Encode4(365074), // Rule ID 545 //
     /* 365049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 365052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 365055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365059 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 365063 */   // (uint_to_fp:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)  =>  (UCVTFHDr:{ *:[f16] } FPR64:{ *:[i64] }:$Rn)
     /* 365063 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFHDr),
     /* 365068 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 365072 */   GIR_RootConstrainSelectedInstOperands,
     /* 365073 */   // GIR_Coverage, 545,
     /* 365073 */   GIR_Done,
     /* 365074 */ // Label 7215: @365074
     /* 365074 */ GIM_Reject,
     /* 365075 */ // Label 7194: @365075
     /* 365075 */ GIM_Try, /*On fail goto*//*Label 7216*/ GIMT_Encode4(365215), // Rule ID 5924 //
     /* 365080 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365090 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365094 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365098 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365101 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 365108 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365112 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365114 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 365121 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 365121 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 365124 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 365128 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365143 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365148 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365153 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365155 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365158 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365162 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365167 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365169 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365172 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365176 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365181 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365184 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365187 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 365190 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365195 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365200 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 365205 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365208 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365210 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365213 */   GIR_RootConstrainSelectedInstOperands,
     /* 365214 */   // GIR_Coverage, 5924,
     /* 365214 */   GIR_EraseRootFromParent_Done,
     /* 365215 */ // Label 7216: @365215
     /* 365215 */ GIM_Try, /*On fail goto*//*Label 7217*/ GIMT_Encode4(365355), // Rule ID 5925 //
     /* 365220 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365223 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365230 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365234 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365238 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365241 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 365248 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365252 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365254 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 365261 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 365261 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 365264 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 365268 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365273 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365278 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365283 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365288 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365293 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365295 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365298 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365302 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365307 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365309 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365312 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365316 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365321 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365324 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365327 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 365330 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365335 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365340 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 365345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365348 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365350 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365353 */   GIR_RootConstrainSelectedInstOperands,
     /* 365354 */   // GIR_Coverage, 5925,
     /* 365354 */   GIR_EraseRootFromParent_Done,
     /* 365355 */ // Label 7217: @365355
     /* 365355 */ GIM_Try, /*On fail goto*//*Label 7218*/ GIMT_Encode4(365495), // Rule ID 5928 //
     /* 365360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365370 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365374 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365378 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365381 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365388 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365392 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365394 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 365401 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 365401 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 365404 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 365408 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365413 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365418 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365423 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365428 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365433 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365435 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365438 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365442 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365447 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365449 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365452 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365456 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365461 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365464 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365467 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 365470 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365475 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365480 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365485 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365488 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365490 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365493 */   GIR_RootConstrainSelectedInstOperands,
     /* 365494 */   // GIR_Coverage, 5928,
     /* 365494 */   GIR_EraseRootFromParent_Done,
     /* 365495 */ // Label 7218: @365495
     /* 365495 */ GIM_Try, /*On fail goto*//*Label 7219*/ GIMT_Encode4(365635), // Rule ID 5929 //
     /* 365500 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365503 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365510 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365514 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365518 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365521 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365528 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365532 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365534 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 365541 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 365541 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 365544 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 365548 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365553 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365558 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 365563 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 365568 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365573 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365575 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365578 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365582 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365587 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365589 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365592 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365596 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365601 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365604 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365607 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 365610 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365615 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365620 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 365625 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365628 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365630 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365633 */   GIR_RootConstrainSelectedInstOperands,
     /* 365634 */   // GIR_Coverage, 5929,
     /* 365634 */   GIR_EraseRootFromParent_Done,
     /* 365635 */ // Label 7219: @365635
     /* 365635 */ GIM_Try, /*On fail goto*//*Label 7220*/ GIMT_Encode4(365770), // Rule ID 5926 //
     /* 365640 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365650 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365654 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365658 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365661 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 365668 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365672 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365674 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 365681 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
     /* 365681 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 365684 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 365688 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365693 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365698 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365703 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365708 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365710 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365713 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365717 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365722 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365724 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365727 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365731 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365736 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365739 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365742 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 365745 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365750 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365755 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 365760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365765 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365768 */   GIR_RootConstrainSelectedInstOperands,
     /* 365769 */   // GIR_Coverage, 5926,
     /* 365769 */   GIR_EraseRootFromParent_Done,
     /* 365770 */ // Label 7220: @365770
     /* 365770 */ GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(365905), // Rule ID 5927 //
     /* 365775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365778 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365781 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365785 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365789 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365793 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365796 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 365803 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365807 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365809 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 365816 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
     /* 365816 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 365819 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 365823 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365828 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365833 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365838 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365843 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365845 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365848 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365852 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365857 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 365866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365871 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 365874 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 365877 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 365880 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365885 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365890 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 365895 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 365898 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 365900 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 365903 */   GIR_RootConstrainSelectedInstOperands,
     /* 365904 */   // GIR_Coverage, 5927,
     /* 365904 */   GIR_EraseRootFromParent_Done,
     /* 365905 */ // Label 7221: @365905
     /* 365905 */ GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(366040), // Rule ID 5930 //
     /* 365910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 365913 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 365916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 365920 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 365924 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 365928 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 365931 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 365938 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 365942 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 365944 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 365951 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
     /* 365951 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 365954 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 365958 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365963 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 365968 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 365973 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 365978 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 365980 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 365983 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 365987 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 365992 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 365994 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 365997 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 366001 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366006 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366009 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366012 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 366015 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366020 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366025 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 366030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 366033 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366035 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366038 */   GIR_RootConstrainSelectedInstOperands,
     /* 366039 */   // GIR_Coverage, 5930,
     /* 366039 */   GIR_EraseRootFromParent_Done,
     /* 366040 */ // Label 7222: @366040
     /* 366040 */ GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(366175), // Rule ID 5931 //
     /* 366045 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366048 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366055 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366059 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 366063 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366066 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 366073 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 366077 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366079 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 366086 */   // (uint_to_fp:{ *:[f32] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i32:{ *:[f32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
     /* 366086 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 366089 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 366093 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366098 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366103 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 366108 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 366113 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 366115 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 366118 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 366122 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366127 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 366129 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 366132 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 366136 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366141 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366144 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366147 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 366150 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366155 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366160 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 366165 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 366168 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366170 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366173 */   GIR_RootConstrainSelectedInstOperands,
     /* 366174 */   // GIR_Coverage, 5931,
     /* 366174 */   GIR_EraseRootFromParent_Done,
     /* 366175 */ // Label 7223: @366175
     /* 366175 */ GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(366255), // Rule ID 4829 //
     /* 366180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 366183 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 366186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366190 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366194 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366198 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 366202 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366206 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366211 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 366215 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366217 */   // (uint_to_fp:{ *:[f32] } (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFSDr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 366217 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 366220 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366224 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366229 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 366235 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366240 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFSDr),
     /* 366248 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366250 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366253 */   GIR_RootConstrainSelectedInstOperands,
     /* 366254 */   // GIR_Coverage, 4829,
     /* 366254 */   GIR_EraseRootFromParent_Done,
     /* 366255 */ // Label 7224: @366255
     /* 366255 */ GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(366335), // Rule ID 5915 //
     /* 366260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366263 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366270 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366274 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 366278 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 366282 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 366286 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366291 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 366295 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366297 */   // (uint_to_fp:{ *:[f32] } (vector_extract:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFv1i32:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } FPR128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 366297 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 366300 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 366304 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366309 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 366315 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366320 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 366325 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 366328 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366330 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366333 */   GIR_RootConstrainSelectedInstOperands,
     /* 366334 */   // GIR_Coverage, 5915,
     /* 366334 */   GIR_EraseRootFromParent_Done,
     /* 366335 */ // Label 7225: @366335
     /* 366335 */ GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(366394), // Rule ID 5897 //
     /* 366340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366343 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366346 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366350 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366354 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 366358 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 366362 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 366364 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366366 */   // (uint_to_fp:{ *:[f32] } (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$Rn)<<P:Predicate_any_fp_to_uint_oneuse>>)  =>  (UCVTFv1i32:{ *:[f32] } (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn))
     /* 366366 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 366369 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 366373 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366378 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366382 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 366384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 366387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366389 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366392 */   GIR_RootConstrainSelectedInstOperands,
     /* 366393 */   // GIR_Coverage, 5897,
     /* 366393 */   GIR_EraseRootFromParent_Done,
     /* 366394 */ // Label 7226: @366394
     /* 366394 */ GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(366439), // Rule ID 5335 //
     /* 366399 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 366402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 366405 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366409 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366413 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 366417 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 366421 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366426 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366428 */   // (uint_to_fp:{ *:[f32] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (UCVTFSDr:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 366428 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFSDr),
     /* 366431 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366433 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366437 */   GIR_RootConstrainSelectedInstOperands,
     /* 366438 */   // GIR_Coverage, 5335,
     /* 366438 */   GIR_EraseRootFromParent_Done,
     /* 366439 */ // Label 7227: @366439
     /* 366439 */ GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(366481), // Rule ID 5337 //
     /* 366444 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366447 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366451 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366455 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 366459 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 366463 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366468 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366470 */   // (uint_to_fp:{ *:[f32] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 366470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 366473 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366475 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 366479 */   GIR_RootConstrainSelectedInstOperands,
     /* 366480 */   // GIR_Coverage, 5337,
     /* 366480 */   GIR_EraseRootFromParent_Done,
     /* 366481 */ // Label 7228: @366481
     /* 366481 */ GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(366511), // Rule ID 511 //
     /* 366486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 366489 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366496 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 366500 */   // (uint_to_fp:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWSri:{ *:[f32] } GPR32:{ *:[i32] }:$Rn)
     /* 366500 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWSri),
     /* 366505 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 366509 */   GIR_RootConstrainSelectedInstOperands,
     /* 366510 */   // GIR_Coverage, 511,
     /* 366510 */   GIR_Done,
     /* 366511 */ // Label 7229: @366511
     /* 366511 */ GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(366541), // Rule ID 517 //
     /* 366516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 366519 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 366522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366526 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 366530 */   // (uint_to_fp:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXSri:{ *:[f32] } GPR64:{ *:[i64] }:$Rn)
     /* 366530 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXSri),
     /* 366535 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 366539 */   GIR_RootConstrainSelectedInstOperands,
     /* 366540 */   // GIR_Coverage, 517,
     /* 366540 */   GIR_Done,
     /* 366541 */ // Label 7230: @366541
     /* 366541 */ GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(366571), // Rule ID 547 //
     /* 366546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 366549 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 366552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366556 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366560 */   // (uint_to_fp:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)  =>  (UCVTFSDr:{ *:[f32] } FPR64:{ *:[i64] }:$Rn)
     /* 366560 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFSDr),
     /* 366565 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 366569 */   GIR_RootConstrainSelectedInstOperands,
     /* 366570 */   // GIR_Coverage, 547,
     /* 366570 */   GIR_Done,
     /* 366571 */ // Label 7231: @366571
     /* 366571 */ GIM_Reject,
     /* 366572 */ // Label 7195: @366572
     /* 366572 */ GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(366709), // Rule ID 5940 //
     /* 366577 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366580 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366587 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366591 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 366595 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366598 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 366602 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 366606 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366608 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 366615 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
     /* 366615 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 366618 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 366622 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366627 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366632 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 366637 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 366642 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 366647 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 366649 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 366652 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 366656 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366661 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 366663 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 366666 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 366670 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366675 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366678 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366681 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 366684 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366689 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366694 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366699 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 366702 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366704 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366707 */   GIR_RootConstrainSelectedInstOperands,
     /* 366708 */   // GIR_Coverage, 5940,
     /* 366708 */   GIR_EraseRootFromParent_Done,
     /* 366709 */ // Label 7232: @366709
     /* 366709 */ GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(366846), // Rule ID 5941 //
     /* 366714 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366717 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366720 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366724 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366728 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 366732 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366735 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 366739 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 366743 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366745 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 366752 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] }))
     /* 366752 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 366755 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 366759 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366764 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366769 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 366774 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 366779 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 366784 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 366786 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 366789 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 366793 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366798 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 366800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 366803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 366807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366812 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366815 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366818 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 366821 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366826 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366831 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 366836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 366839 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366841 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366844 */   GIR_RootConstrainSelectedInstOperands,
     /* 366845 */   // GIR_Coverage, 5941,
     /* 366845 */   GIR_EraseRootFromParent_Done,
     /* 366846 */ // Label 7233: @366846
     /* 366846 */ GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(366986), // Rule ID 5932 //
     /* 366851 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366854 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366861 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 366865 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 366869 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 366872 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 366879 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 366883 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 366885 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 366892 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 366892 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 366895 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 366899 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366904 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 366909 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 366914 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 366919 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 366924 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 366926 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 366929 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 366933 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366938 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 366940 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 366943 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 366947 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 366952 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 366955 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 366958 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 366961 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366966 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 366971 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 366976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 366979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 366981 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 366984 */   GIR_RootConstrainSelectedInstOperands,
     /* 366985 */   // GIR_Coverage, 5932,
     /* 366985 */   GIR_EraseRootFromParent_Done,
     /* 366986 */ // Label 7234: @366986
     /* 366986 */ GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(367126), // Rule ID 5933 //
     /* 366991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 366994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 366997 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367001 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367005 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367009 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367012 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 367019 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367023 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367025 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 367032 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] }))
     /* 367032 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 367035 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 367039 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367044 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367049 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 367054 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 367059 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367064 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367066 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367069 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367073 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367078 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367080 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367083 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367087 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367092 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367095 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367098 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 367101 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367106 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367111 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 367116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367121 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367124 */   GIR_RootConstrainSelectedInstOperands,
     /* 367125 */   // GIR_Coverage, 5933,
     /* 367125 */   GIR_EraseRootFromParent_Done,
     /* 367126 */ // Label 7235: @367126
     /* 367126 */ GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(367266), // Rule ID 5936 //
     /* 367131 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367134 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367141 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367145 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367149 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367152 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 367159 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367163 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367165 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 367172 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 367172 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 367175 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 367179 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367184 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367189 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 367194 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 367199 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367204 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367206 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367209 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367213 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367218 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367220 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367223 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367227 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367232 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367235 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367238 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 367241 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367246 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367251 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367256 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367259 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367261 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367264 */   GIR_RootConstrainSelectedInstOperands,
     /* 367265 */   // GIR_Coverage, 5936,
     /* 367265 */   GIR_EraseRootFromParent_Done,
     /* 367266 */ // Label 7236: @367266
     /* 367266 */ GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(367406), // Rule ID 5937 //
     /* 367271 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367274 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367277 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367281 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367285 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367289 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367292 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 367299 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367303 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367305 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 367312 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] }))
     /* 367312 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 367315 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 367319 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367324 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367329 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 367334 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 367339 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367344 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367346 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367349 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367353 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367358 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367360 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367363 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367367 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367372 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367375 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367378 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 367381 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367386 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367391 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 367396 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367399 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367401 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367404 */   GIR_RootConstrainSelectedInstOperands,
     /* 367405 */   // GIR_Coverage, 5937,
     /* 367405 */   GIR_EraseRootFromParent_Done,
     /* 367406 */ // Label 7237: @367406
     /* 367406 */ GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(367538), // Rule ID 5942 //
     /* 367411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367414 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367421 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367425 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 367429 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367432 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 367436 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367440 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367442 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 367449 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] }))
     /* 367449 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 367452 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 367456 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367461 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367466 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 367471 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367476 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367478 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367481 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367485 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367490 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367492 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367495 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367499 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367504 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367507 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367510 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 367513 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367518 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367523 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 367528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367533 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367536 */   GIR_RootConstrainSelectedInstOperands,
     /* 367537 */   // GIR_Coverage, 5942,
     /* 367537 */   GIR_EraseRootFromParent_Done,
     /* 367538 */ // Label 7238: @367538
     /* 367538 */ GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(367670), // Rule ID 5943 //
     /* 367543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367553 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367557 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 367561 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367564 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 367568 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367572 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367574 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 367581 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] }))
     /* 367581 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 367584 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 367588 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367593 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367598 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 367603 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367608 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367610 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367613 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367617 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367622 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367624 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367627 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367631 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367636 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367639 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367642 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 367645 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367650 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367655 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 367660 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367663 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367665 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367668 */   GIR_RootConstrainSelectedInstOperands,
     /* 367669 */   // GIR_Coverage, 5943,
     /* 367669 */   GIR_EraseRootFromParent_Done,
     /* 367670 */ // Label 7239: @367670
     /* 367670 */ GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(367805), // Rule ID 5934 //
     /* 367675 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367678 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367681 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367685 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367689 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367693 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367696 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 367703 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367707 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367709 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 367716 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] }))
     /* 367716 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 367719 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 367723 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367728 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367733 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 367738 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367743 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367745 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367748 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367752 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367757 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367759 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367762 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367766 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367771 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367774 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367777 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 367780 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367785 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367790 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 367795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367800 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367803 */   GIR_RootConstrainSelectedInstOperands,
     /* 367804 */   // GIR_Coverage, 5934,
     /* 367804 */   GIR_EraseRootFromParent_Done,
     /* 367805 */ // Label 7240: @367805
     /* 367805 */ GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(367940), // Rule ID 5935 //
     /* 367810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367820 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367824 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367828 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367831 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 367838 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367842 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367844 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 367851 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] }))
     /* 367851 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s8,
     /* 367854 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 367858 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367863 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 367868 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 367873 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 367878 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 367880 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 367883 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 367887 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367892 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 367894 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 367897 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 367901 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367906 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 367909 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 367912 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 367915 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367920 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367925 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 367930 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 367933 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 367935 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 367938 */   GIR_RootConstrainSelectedInstOperands,
     /* 367939 */   // GIR_Coverage, 5935,
     /* 367939 */   GIR_EraseRootFromParent_Done,
     /* 367940 */ // Label 7241: @367940
     /* 367940 */ GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(368075), // Rule ID 5938 //
     /* 367945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 367948 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 367951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 367955 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 367959 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 367963 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 367966 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 367973 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 367977 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 367979 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 367986 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] }))
     /* 367986 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 367989 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 367993 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 367998 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368003 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 368008 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 368013 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 368015 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 368018 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 368022 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368027 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 368029 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 368032 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 368036 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368041 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 368044 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 368047 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 368050 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368055 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368060 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 368065 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 368068 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368070 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368073 */   GIR_RootConstrainSelectedInstOperands,
     /* 368074 */   // GIR_Coverage, 5938,
     /* 368074 */   GIR_EraseRootFromParent_Done,
     /* 368075 */ // Label 7242: @368075
     /* 368075 */ GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(368210), // Rule ID 5939 //
     /* 368080 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 368083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368090 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368094 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXTLOAD),
     /* 368098 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 368101 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 368108 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/0,
     /* 368112 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368114 */   GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 368121 */   // (uint_to_fp:{ *:[f64] } (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>>)  =>  (UCVTFv1i64:{ *:[f64] } (INSERT_SUBREG:{ *:[f64] } (IMPLICIT_DEF:{ *:[f64] }), (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] }))
     /* 368121 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
     /* 368124 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 368128 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368133 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 368138 */   GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 368143 */   GIR_MergeMemOperands, /*InsnID*/3, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 368148 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 368150 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 368153 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 368157 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368162 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 368164 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 368167 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 368171 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368176 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 368179 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 368182 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 368185 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368190 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368195 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 368200 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 368203 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368205 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368208 */   GIR_RootConstrainSelectedInstOperands,
     /* 368209 */   // GIR_Coverage, 5939,
     /* 368209 */   GIR_EraseRootFromParent_Done,
     /* 368210 */ // Label 7243: @368210
     /* 368210 */ GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(368290), // Rule ID 4825 //
     /* 368215 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 368218 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368225 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368229 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 368233 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 368237 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 368241 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368246 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 368250 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368252 */   // (uint_to_fp:{ *:[f64] } (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFDSr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, ssub:{ *:[i32] }))
     /* 368252 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 368255 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 368259 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368264 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 368270 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368275 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368280 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 368283 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368285 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368288 */   GIR_RootConstrainSelectedInstOperands,
     /* 368289 */   // GIR_Coverage, 4825,
     /* 368289 */   GIR_EraseRootFromParent_Done,
     /* 368290 */ // Label 7244: @368290
     /* 368290 */ GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(368370), // Rule ID 5917 //
     /* 368295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 368298 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 368301 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368305 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368309 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 368313 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 368317 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 368321 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368326 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 368330 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368332 */   // (uint_to_fp:{ *:[f64] } (vector_extract:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }))  =>  (UCVTFv1i64:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] }))
     /* 368332 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 368335 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 368339 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368344 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 368350 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368355 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368360 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 368363 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368365 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368368 */   GIR_RootConstrainSelectedInstOperands,
     /* 368369 */   // GIR_Coverage, 5917,
     /* 368369 */   GIR_EraseRootFromParent_Done,
     /* 368370 */ // Label 7245: @368370
     /* 368370 */ GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(368429), // Rule ID 5893 //
     /* 368375 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsSME2p2StreamingSafe),
     /* 368378 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 368381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368385 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368389 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTOUI),
     /* 368393 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 368397 */   GIM_CheckHasOneUse, /*MI*/1,
     /* 368399 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368401 */   // (uint_to_fp:{ *:[f64] } (fp_to_uint:{ *:[i64] } f64:{ *:[f64] }:$Rn)<<P:Predicate_any_fp_to_uint_oneuse>>)  =>  (UCVTFv1i64:{ *:[f64] } (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn))
     /* 368401 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 368404 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 368408 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 368413 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368417 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 368419 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 368422 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368424 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 368427 */   GIR_RootConstrainSelectedInstOperands,
     /* 368428 */   // GIR_Coverage, 5893,
     /* 368428 */   GIR_EraseRootFromParent_Done,
     /* 368429 */ // Label 7246: @368429
     /* 368429 */ GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(368474), // Rule ID 5329 //
     /* 368434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 368437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368444 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368448 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 368452 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 368456 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368461 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368463 */   // (uint_to_fp:{ *:[f64] } (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Rn))  =>  (UCVTFDSr:{ *:[f64] } FPR32:{ *:[f32] }:$Rn)
     /* 368463 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 368466 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368468 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368472 */   GIR_RootConstrainSelectedInstOperands,
     /* 368473 */   // GIR_Coverage, 5329,
     /* 368473 */   GIR_EraseRootFromParent_Done,
     /* 368474 */ // Label 7247: @368474
     /* 368474 */ GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(368516), // Rule ID 5339 //
     /* 368479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 368482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368486 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368490 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 368494 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 368498 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368503 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368505 */   // (uint_to_fp:{ *:[f64] } (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Rn))  =>  (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 368505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 368508 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368510 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368514 */   GIR_RootConstrainSelectedInstOperands,
     /* 368515 */   // GIR_Coverage, 5339,
     /* 368515 */   GIR_EraseRootFromParent_Done,
     /* 368516 */ // Label 7248: @368516
     /* 368516 */ GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(368546), // Rule ID 513 //
     /* 368521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 368524 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368531 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 368535 */   // (uint_to_fp:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)  =>  (UCVTFUWDri:{ *:[f64] } GPR32:{ *:[i32] }:$Rn)
     /* 368535 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUWDri),
     /* 368540 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368544 */   GIR_RootConstrainSelectedInstOperands,
     /* 368545 */   // GIR_Coverage, 513,
     /* 368545 */   GIR_Done,
     /* 368546 */ // Label 7249: @368546
     /* 368546 */ GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(368576), // Rule ID 519 //
     /* 368551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 368554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 368557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 368565 */   // (uint_to_fp:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)  =>  (UCVTFUXDri:{ *:[f64] } GPR64:{ *:[i64] }:$Rn)
     /* 368565 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFUXDri),
     /* 368570 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368574 */   GIR_RootConstrainSelectedInstOperands,
     /* 368575 */   // GIR_Coverage, 519,
     /* 368575 */   GIR_Done,
     /* 368576 */ // Label 7250: @368576
     /* 368576 */ GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(368606), // Rule ID 543 //
     /* 368581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 368584 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368587 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368591 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368595 */   // (uint_to_fp:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)  =>  (UCVTFDSr:{ *:[f64] } FPR32:{ *:[i32] }:$Rn)
     /* 368595 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 368600 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368604 */   GIR_RootConstrainSelectedInstOperands,
     /* 368605 */   // GIR_Coverage, 543,
     /* 368605 */   GIR_Done,
     /* 368606 */ // Label 7251: @368606
     /* 368606 */ GIM_Reject,
     /* 368607 */ // Label 7196: @368607
     /* 368607 */ GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(368637), // Rule ID 1108 //
     /* 368612 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 368615 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 368618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368622 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368626 */   // (uint_to_fp:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)  =>  (UCVTFv2f32:{ *:[v2f32] } V64:{ *:[v2i32] }:$Rn)
     /* 368626 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f32),
     /* 368631 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368635 */   GIR_RootConstrainSelectedInstOperands,
     /* 368636 */   // GIR_Coverage, 1108,
     /* 368636 */   GIR_Done,
     /* 368637 */ // Label 7252: @368637
     /* 368637 */ GIM_Reject,
     /* 368638 */ // Label 7197: @368638
     /* 368638 */ GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(368668), // Rule ID 1112 //
     /* 368643 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 368646 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 368649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368653 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368657 */   // (uint_to_fp:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)  =>  (UCVTFv2f64:{ *:[v2f64] } V128:{ *:[v2i64] }:$Rn)
     /* 368657 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv2f64),
     /* 368662 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368666 */   GIR_RootConstrainSelectedInstOperands,
     /* 368667 */   // GIR_Coverage, 1112,
     /* 368667 */   GIR_Done,
     /* 368668 */ // Label 7253: @368668
     /* 368668 */ GIM_Reject,
     /* 368669 */ // Label 7198: @368669
     /* 368669 */ GIM_Try, /*On fail goto*//*Label 7254*/ GIMT_Encode4(368699), // Rule ID 1104 //
     /* 368674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 368677 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 368680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368684 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 368688 */   // (uint_to_fp:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)  =>  (UCVTFv4f16:{ *:[v4f16] } V64:{ *:[v4i16] }:$Rn)
     /* 368688 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f16),
     /* 368693 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368697 */   GIR_RootConstrainSelectedInstOperands,
     /* 368698 */   // GIR_Coverage, 1104,
     /* 368698 */   GIR_Done,
     /* 368699 */ // Label 7254: @368699
     /* 368699 */ GIM_Reject,
     /* 368700 */ // Label 7199: @368700
     /* 368700 */ GIM_Try, /*On fail goto*//*Label 7255*/ GIMT_Encode4(368730), // Rule ID 1110 //
     /* 368705 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 368708 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 368711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368715 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368719 */   // (uint_to_fp:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)  =>  (UCVTFv4f32:{ *:[v4f32] } V128:{ *:[v4i32] }:$Rn)
     /* 368719 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv4f32),
     /* 368724 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368728 */   GIR_RootConstrainSelectedInstOperands,
     /* 368729 */   // GIR_Coverage, 1110,
     /* 368729 */   GIR_Done,
     /* 368730 */ // Label 7255: @368730
     /* 368730 */ GIM_Reject,
     /* 368731 */ // Label 7200: @368731
     /* 368731 */ GIM_Try, /*On fail goto*//*Label 7256*/ GIMT_Encode4(368761), // Rule ID 1106 //
     /* 368736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 368739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 368742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368746 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 368750 */   // (uint_to_fp:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)  =>  (UCVTFv8f16:{ *:[v8f16] } V128:{ *:[v8i16] }:$Rn)
     /* 368750 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv8f16),
     /* 368755 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368759 */   GIR_RootConstrainSelectedInstOperands,
     /* 368760 */   // GIR_Coverage, 1106,
     /* 368760 */   GIR_Done,
     /* 368761 */ // Label 7256: @368761
     /* 368761 */ GIM_Reject,
     /* 368762 */ // Label 7201: @368762
     /* 368762 */ GIM_Reject,
     /* 368763 */ // Label 80: @368763
     /* 368763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7265*/ GIMT_Encode4(370199),
     /* 368774 */ /*GILLT_s16*//*Label 7257*/ GIMT_Encode4(368814),
     /* 368778 */ /*GILLT_s32*//*Label 7258*/ GIMT_Encode4(368841),
     /* 368782 */ /*GILLT_s64*//*Label 7259*/ GIMT_Encode4(369457), GIMT_Encode4(0),
     /* 368790 */ /*GILLT_v2s32*//*Label 7260*/ GIMT_Encode4(370073),
     /* 368794 */ /*GILLT_v2s64*//*Label 7261*/ GIMT_Encode4(370097),
     /* 368798 */ /*GILLT_v4s16*//*Label 7262*/ GIMT_Encode4(370121),
     /* 368802 */ /*GILLT_v4s32*//*Label 7263*/ GIMT_Encode4(370148), GIMT_Encode4(0),
     /* 368810 */ /*GILLT_v8s16*//*Label 7264*/ GIMT_Encode4(370172),
     /* 368814 */ // Label 7257: @368814
     /* 368814 */ GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(368840), // Rule ID 5826 //
     /* 368819 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 368822 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 368825 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 368829 */   // (fp_to_sint_sat_gi:{ *:[i16] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSv1f16:{ *:[i16] } f16:{ *:[f16] }:$Rn)
     /* 368829 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1f16),
     /* 368834 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 368838 */   GIR_RootConstrainSelectedInstOperands,
     /* 368839 */   // GIR_Coverage, 5826,
     /* 368839 */   GIR_Done,
     /* 368840 */ // Label 7266: @368840
     /* 368840 */ GIM_Reject,
     /* 368841 */ // Label 7258: @368841
     /* 368841 */ GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(368881), // Rule ID 5550 //
     /* 368846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 368849 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 368852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368856 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368860 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 368864 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 368868 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368870 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fceil:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTPSSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 368870 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSHr),
     /* 368873 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368875 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368879 */   GIR_RootConstrainSelectedInstOperands,
     /* 368880 */   // GIR_Coverage, 5550,
     /* 368880 */   GIR_EraseRootFromParent_Done,
     /* 368881 */ // Label 7267: @368881
     /* 368881 */ GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(368921), // Rule ID 5553 //
     /* 368886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 368889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 368892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368896 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368900 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 368904 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 368908 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368910 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 368910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSSDr),
     /* 368913 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368915 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368919 */   GIR_RootConstrainSelectedInstOperands,
     /* 368920 */   // GIR_Coverage, 5553,
     /* 368920 */   GIR_EraseRootFromParent_Done,
     /* 368921 */ // Label 7268: @368921
     /* 368921 */ GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(368958), // Rule ID 5554 //
     /* 368926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 368929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368933 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368937 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 368941 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 368945 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368947 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 368947 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i32),
     /* 368950 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368952 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368956 */   GIR_RootConstrainSelectedInstOperands,
     /* 368957 */   // GIR_Coverage, 5554,
     /* 368957 */   GIR_EraseRootFromParent_Done,
     /* 368958 */ // Label 7269: @368958
     /* 368958 */ GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(368998), // Rule ID 5610 //
     /* 368963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 368966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 368969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 368973 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 368977 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 368981 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 368985 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 368987 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ffloor:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTMSSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 368987 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSHr),
     /* 368990 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 368992 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 368996 */   GIR_RootConstrainSelectedInstOperands,
     /* 368997 */   // GIR_Coverage, 5610,
     /* 368997 */   GIR_EraseRootFromParent_Done,
     /* 368998 */ // Label 7270: @368998
     /* 368998 */ GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(369038), // Rule ID 5613 //
     /* 369003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369013 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369017 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 369021 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369025 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369027 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 369027 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSSDr),
     /* 369030 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369032 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369036 */   GIR_RootConstrainSelectedInstOperands,
     /* 369037 */   // GIR_Coverage, 5613,
     /* 369037 */   GIR_EraseRootFromParent_Done,
     /* 369038 */ // Label 7271: @369038
     /* 369038 */ GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(369075), // Rule ID 5614 //
     /* 369043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369050 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369054 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 369058 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369062 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369064 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 369064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i32),
     /* 369067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369069 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369073 */   GIR_RootConstrainSelectedInstOperands,
     /* 369074 */   // GIR_Coverage, 5614,
     /* 369074 */   GIR_EraseRootFromParent_Done,
     /* 369075 */ // Label 7272: @369075
     /* 369075 */ GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(369115), // Rule ID 5730 //
     /* 369080 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369090 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369094 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369098 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369102 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369104 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fround:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTASSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 369104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSHr),
     /* 369107 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369109 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369113 */   GIR_RootConstrainSelectedInstOperands,
     /* 369114 */   // GIR_Coverage, 5730,
     /* 369114 */   GIR_EraseRootFromParent_Done,
     /* 369115 */ // Label 7273: @369115
     /* 369115 */ GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(369155), // Rule ID 5733 //
     /* 369120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369126 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369130 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369134 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369138 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369142 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369144 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 369144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 369147 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369149 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369153 */   GIR_RootConstrainSelectedInstOperands,
     /* 369154 */   // GIR_Coverage, 5733,
     /* 369154 */   GIR_EraseRootFromParent_Done,
     /* 369155 */ // Label 7274: @369155
     /* 369155 */ GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(369192), // Rule ID 5734 //
     /* 369160 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369163 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369167 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369171 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369175 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369179 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369181 */   // (fp_to_sint_sat_gi:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 369181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 369184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369186 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369190 */   GIR_RootConstrainSelectedInstOperands,
     /* 369191 */   // GIR_Coverage, 5734,
     /* 369191 */   GIR_EraseRootFromParent_Done,
     /* 369192 */ // Label 7275: @369192
     /* 369192 */ GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(369232), // Rule ID 5670 //
     /* 369197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369200 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369207 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369211 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369215 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369219 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369221 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZSSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 369221 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 369224 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369226 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369230 */   GIR_RootConstrainSelectedInstOperands,
     /* 369231 */   // GIR_Coverage, 5670,
     /* 369231 */   GIR_EraseRootFromParent_Done,
     /* 369232 */ // Label 7276: @369232
     /* 369232 */ GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(369272), // Rule ID 5673 //
     /* 369237 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369240 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369243 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369247 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369251 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369255 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369259 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369261 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 369261 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 369264 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369266 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369270 */   GIR_RootConstrainSelectedInstOperands,
     /* 369271 */   // GIR_Coverage, 5673,
     /* 369271 */   GIR_EraseRootFromParent_Done,
     /* 369272 */ // Label 7277: @369272
     /* 369272 */ GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(369309), // Rule ID 5674 //
     /* 369277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369284 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369288 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369292 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369296 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369298 */   // (fp_to_sint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 369298 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 369301 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369303 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369307 */   GIR_RootConstrainSelectedInstOperands,
     /* 369308 */   // GIR_Coverage, 5674,
     /* 369308 */   GIR_EraseRootFromParent_Done,
     /* 369309 */ // Label 7278: @369309
     /* 369309 */ GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(369335), // Rule ID 5466 //
     /* 369314 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 369317 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 369324 */   // (fp_to_sint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 369324 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWHr),
     /* 369329 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369333 */   GIR_RootConstrainSelectedInstOperands,
     /* 369334 */   // GIR_Coverage, 5466,
     /* 369334 */   GIR_Done,
     /* 369335 */ // Label 7279: @369335
     /* 369335 */ GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(369358), // Rule ID 5468 //
     /* 369340 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369343 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 369347 */   // (fp_to_sint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 369347 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWSr),
     /* 369352 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369356 */   GIR_RootConstrainSelectedInstOperands,
     /* 369357 */   // GIR_Coverage, 5468,
     /* 369357 */   GIR_Done,
     /* 369358 */ // Label 7280: @369358
     /* 369358 */ GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(369381), // Rule ID 5470 //
     /* 369363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 369370 */   // (fp_to_sint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 369370 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUWDr),
     /* 369375 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369379 */   GIR_RootConstrainSelectedInstOperands,
     /* 369380 */   // GIR_Coverage, 5470,
     /* 369380 */   GIR_Done,
     /* 369381 */ // Label 7281: @369381
     /* 369381 */ GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(369407), // Rule ID 5472 //
     /* 369386 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369389 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369396 */   // (fp_to_sint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 369396 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSHr),
     /* 369401 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369405 */   GIR_RootConstrainSelectedInstOperands,
     /* 369406 */   // GIR_Coverage, 5472,
     /* 369406 */   GIR_Done,
     /* 369407 */ // Label 7282: @369407
     /* 369407 */ GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(369433), // Rule ID 5475 //
     /* 369412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369415 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369422 */   // (fp_to_sint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 369422 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSSDr),
     /* 369427 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369431 */   GIR_RootConstrainSelectedInstOperands,
     /* 369432 */   // GIR_Coverage, 5475,
     /* 369432 */   GIR_Done,
     /* 369433 */ // Label 7283: @369433
     /* 369433 */ GIM_Try, /*On fail goto*//*Label 7284*/ GIMT_Encode4(369456), // Rule ID 5476 //
     /* 369438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 369445 */   // (fp_to_sint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 369445 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i32),
     /* 369450 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369454 */   GIR_RootConstrainSelectedInstOperands,
     /* 369455 */   // GIR_Coverage, 5476,
     /* 369455 */   GIR_Done,
     /* 369456 */ // Label 7284: @369456
     /* 369456 */ GIM_Reject,
     /* 369457 */ // Label 7259: @369457
     /* 369457 */ GIM_Try, /*On fail goto*//*Label 7285*/ GIMT_Encode4(369497), // Rule ID 5551 //
     /* 369462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369472 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369476 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 369480 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369484 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369486 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fceil:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTPSDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 369486 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDHr),
     /* 369489 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369491 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369495 */   GIR_RootConstrainSelectedInstOperands,
     /* 369496 */   // GIR_Coverage, 5551,
     /* 369496 */   GIR_EraseRootFromParent_Done,
     /* 369497 */ // Label 7285: @369497
     /* 369497 */ GIM_Try, /*On fail goto*//*Label 7286*/ GIMT_Encode4(369537), // Rule ID 5552 //
     /* 369502 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369505 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369508 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369512 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369516 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 369520 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369524 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369526 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 369526 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSDSr),
     /* 369529 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369531 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369535 */   GIR_RootConstrainSelectedInstOperands,
     /* 369536 */   // GIR_Coverage, 5552,
     /* 369536 */   GIR_EraseRootFromParent_Done,
     /* 369537 */ // Label 7286: @369537
     /* 369537 */ GIM_Try, /*On fail goto*//*Label 7287*/ GIMT_Encode4(369574), // Rule ID 5555 //
     /* 369542 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369549 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369553 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 369557 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369561 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369563 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 369563 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPSv1i64),
     /* 369566 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369568 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369572 */   GIR_RootConstrainSelectedInstOperands,
     /* 369573 */   // GIR_Coverage, 5555,
     /* 369573 */   GIR_EraseRootFromParent_Done,
     /* 369574 */ // Label 7287: @369574
     /* 369574 */ GIM_Try, /*On fail goto*//*Label 7288*/ GIMT_Encode4(369614), // Rule ID 5611 //
     /* 369579 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369582 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369585 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369589 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369593 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 369597 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369601 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369603 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ffloor:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTMSDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 369603 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDHr),
     /* 369606 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369608 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369612 */   GIR_RootConstrainSelectedInstOperands,
     /* 369613 */   // GIR_Coverage, 5611,
     /* 369613 */   GIR_EraseRootFromParent_Done,
     /* 369614 */ // Label 7288: @369614
     /* 369614 */ GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(369654), // Rule ID 5612 //
     /* 369619 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369622 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369629 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369633 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 369637 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369641 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369643 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 369643 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSDSr),
     /* 369646 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369648 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369652 */   GIR_RootConstrainSelectedInstOperands,
     /* 369653 */   // GIR_Coverage, 5612,
     /* 369653 */   GIR_EraseRootFromParent_Done,
     /* 369654 */ // Label 7289: @369654
     /* 369654 */ GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(369691), // Rule ID 5615 //
     /* 369659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369666 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369670 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 369674 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369678 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369680 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 369680 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMSv1i64),
     /* 369683 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369685 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369689 */   GIR_RootConstrainSelectedInstOperands,
     /* 369690 */   // GIR_Coverage, 5615,
     /* 369690 */   GIR_EraseRootFromParent_Done,
     /* 369691 */ // Label 7290: @369691
     /* 369691 */ GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(369731), // Rule ID 5731 //
     /* 369696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369699 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369706 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369710 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369714 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369718 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369720 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fround:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTASDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 369720 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 369723 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369725 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369729 */   GIR_RootConstrainSelectedInstOperands,
     /* 369730 */   // GIR_Coverage, 5731,
     /* 369730 */   GIR_EraseRootFromParent_Done,
     /* 369731 */ // Label 7291: @369731
     /* 369731 */ GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(369771), // Rule ID 5732 //
     /* 369736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369746 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369750 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369754 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369758 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369760 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTASDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 369760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 369763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369765 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369769 */   GIR_RootConstrainSelectedInstOperands,
     /* 369770 */   // GIR_Coverage, 5732,
     /* 369770 */   GIR_EraseRootFromParent_Done,
     /* 369771 */ // Label 7292: @369771
     /* 369771 */ GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(369808), // Rule ID 5735 //
     /* 369776 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369779 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369783 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369787 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 369791 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369795 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369797 */   // (fp_to_sint_sat_gi:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTASv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 369797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 369800 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369802 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369806 */   GIR_RootConstrainSelectedInstOperands,
     /* 369807 */   // GIR_Coverage, 5735,
     /* 369807 */   GIR_EraseRootFromParent_Done,
     /* 369808 */ // Label 7293: @369808
     /* 369808 */ GIM_Try, /*On fail goto*//*Label 7294*/ GIMT_Encode4(369848), // Rule ID 5671 //
     /* 369813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369823 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369827 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369831 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 369835 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369837 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZSDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 369837 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 369840 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369842 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369846 */   GIR_RootConstrainSelectedInstOperands,
     /* 369847 */   // GIR_Coverage, 5671,
     /* 369847 */   GIR_EraseRootFromParent_Done,
     /* 369848 */ // Label 7294: @369848
     /* 369848 */ GIM_Try, /*On fail goto*//*Label 7295*/ GIMT_Encode4(369888), // Rule ID 5672 //
     /* 369853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 369856 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369863 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369867 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369871 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 369875 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369877 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 369877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 369880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369882 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369886 */   GIR_RootConstrainSelectedInstOperands,
     /* 369887 */   // GIR_Coverage, 5672,
     /* 369887 */   GIR_EraseRootFromParent_Done,
     /* 369888 */ // Label 7295: @369888
     /* 369888 */ GIM_Try, /*On fail goto*//*Label 7296*/ GIMT_Encode4(369925), // Rule ID 5675 //
     /* 369893 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 369900 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 369904 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 369908 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 369912 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 369914 */   // (fp_to_sint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 369914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 369917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 369919 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 369923 */   GIR_RootConstrainSelectedInstOperands,
     /* 369924 */   // GIR_Coverage, 5675,
     /* 369924 */   GIR_EraseRootFromParent_Done,
     /* 369925 */ // Label 7296: @369925
     /* 369925 */ GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(369951), // Rule ID 5467 //
     /* 369930 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 369933 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 369936 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 369940 */   // (fp_to_sint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 369940 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXHr),
     /* 369945 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369949 */   GIR_RootConstrainSelectedInstOperands,
     /* 369950 */   // GIR_Coverage, 5467,
     /* 369950 */   GIR_Done,
     /* 369951 */ // Label 7297: @369951
     /* 369951 */ GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(369974), // Rule ID 5469 //
     /* 369956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 369959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 369963 */   // (fp_to_sint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 369963 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXSr),
     /* 369968 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369972 */   GIR_RootConstrainSelectedInstOperands,
     /* 369973 */   // GIR_Coverage, 5469,
     /* 369973 */   GIR_Done,
     /* 369974 */ // Label 7298: @369974
     /* 369974 */ GIM_Try, /*On fail goto*//*Label 7299*/ GIMT_Encode4(369997), // Rule ID 5471 //
     /* 369979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 369982 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 369986 */   // (fp_to_sint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 369986 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSUXDr),
     /* 369991 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 369995 */   GIR_RootConstrainSelectedInstOperands,
     /* 369996 */   // GIR_Coverage, 5471,
     /* 369996 */   GIR_Done,
     /* 369997 */ // Label 7299: @369997
     /* 369997 */ GIM_Try, /*On fail goto*//*Label 7300*/ GIMT_Encode4(370023), // Rule ID 5473 //
     /* 370002 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370005 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370012 */   // (fp_to_sint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZSDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 370012 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDHr),
     /* 370017 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370021 */   GIR_RootConstrainSelectedInstOperands,
     /* 370022 */   // GIR_Coverage, 5473,
     /* 370022 */   GIR_Done,
     /* 370023 */ // Label 7300: @370023
     /* 370023 */ GIM_Try, /*On fail goto*//*Label 7301*/ GIMT_Encode4(370049), // Rule ID 5474 //
     /* 370028 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370031 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370038 */   // (fp_to_sint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZSDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 370038 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSDSr),
     /* 370043 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370047 */   GIR_RootConstrainSelectedInstOperands,
     /* 370048 */   // GIR_Coverage, 5474,
     /* 370048 */   GIR_Done,
     /* 370049 */ // Label 7301: @370049
     /* 370049 */ GIM_Try, /*On fail goto*//*Label 7302*/ GIMT_Encode4(370072), // Rule ID 5477 //
     /* 370054 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370057 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370061 */   // (fp_to_sint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZSv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 370061 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv1i64),
     /* 370066 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370070 */   GIR_RootConstrainSelectedInstOperands,
     /* 370071 */   // GIR_Coverage, 5477,
     /* 370071 */   GIR_Done,
     /* 370072 */ // Label 7302: @370072
     /* 370072 */ GIM_Reject,
     /* 370073 */ // Label 7260: @370073
     /* 370073 */ GIM_Try, /*On fail goto*//*Label 7303*/ GIMT_Encode4(370096), // Rule ID 4995 //
     /* 370078 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 370081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370085 */   // (fp_to_sint_sat_gi:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZSv2f32:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)
     /* 370085 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f32),
     /* 370090 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370094 */   GIR_RootConstrainSelectedInstOperands,
     /* 370095 */   // GIR_Coverage, 4995,
     /* 370095 */   GIR_Done,
     /* 370096 */ // Label 7303: @370096
     /* 370096 */ GIM_Reject,
     /* 370097 */ // Label 7261: @370097
     /* 370097 */ GIM_Try, /*On fail goto*//*Label 7304*/ GIMT_Encode4(370120), // Rule ID 4997 //
     /* 370102 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 370105 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370109 */   // (fp_to_sint_sat_gi:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZSv2f64:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)
     /* 370109 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv2f64),
     /* 370114 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370118 */   GIR_RootConstrainSelectedInstOperands,
     /* 370119 */   // GIR_Coverage, 4997,
     /* 370119 */   GIR_Done,
     /* 370120 */ // Label 7304: @370120
     /* 370120 */ GIM_Reject,
     /* 370121 */ // Label 7262: @370121
     /* 370121 */ GIM_Try, /*On fail goto*//*Label 7305*/ GIMT_Encode4(370147), // Rule ID 4990 //
     /* 370126 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 370129 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 370132 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370136 */   // (fp_to_sint_sat_gi:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZSv4f16:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)
     /* 370136 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f16),
     /* 370141 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370145 */   GIR_RootConstrainSelectedInstOperands,
     /* 370146 */   // GIR_Coverage, 4990,
     /* 370146 */   GIR_Done,
     /* 370147 */ // Label 7305: @370147
     /* 370147 */ GIM_Reject,
     /* 370148 */ // Label 7263: @370148
     /* 370148 */ GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(370171), // Rule ID 4996 //
     /* 370153 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 370156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370160 */   // (fp_to_sint_sat_gi:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZSv4f32:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)
     /* 370160 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv4f32),
     /* 370165 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370169 */   GIR_RootConstrainSelectedInstOperands,
     /* 370170 */   // GIR_Coverage, 4996,
     /* 370170 */   GIR_Done,
     /* 370171 */ // Label 7306: @370171
     /* 370171 */ GIM_Reject,
     /* 370172 */ // Label 7264: @370172
     /* 370172 */ GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(370198), // Rule ID 4991 //
     /* 370177 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 370180 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 370183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 370187 */   // (fp_to_sint_sat_gi:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZSv8f16:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)
     /* 370187 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZSv8f16),
     /* 370192 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370196 */   GIR_RootConstrainSelectedInstOperands,
     /* 370197 */   // GIR_Coverage, 4991,
     /* 370197 */   GIR_Done,
     /* 370198 */ // Label 7307: @370198
     /* 370198 */ GIM_Reject,
     /* 370199 */ // Label 7265: @370199
     /* 370199 */ GIM_Reject,
     /* 370200 */ // Label 81: @370200
     /* 370200 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7316*/ GIMT_Encode4(371636),
     /* 370211 */ /*GILLT_s16*//*Label 7308*/ GIMT_Encode4(370251),
     /* 370215 */ /*GILLT_s32*//*Label 7309*/ GIMT_Encode4(370278),
     /* 370219 */ /*GILLT_s64*//*Label 7310*/ GIMT_Encode4(370894), GIMT_Encode4(0),
     /* 370227 */ /*GILLT_v2s32*//*Label 7311*/ GIMT_Encode4(371510),
     /* 370231 */ /*GILLT_v2s64*//*Label 7312*/ GIMT_Encode4(371534),
     /* 370235 */ /*GILLT_v4s16*//*Label 7313*/ GIMT_Encode4(371558),
     /* 370239 */ /*GILLT_v4s32*//*Label 7314*/ GIMT_Encode4(371585), GIMT_Encode4(0),
     /* 370247 */ /*GILLT_v8s16*//*Label 7315*/ GIMT_Encode4(371609),
     /* 370251 */ // Label 7308: @370251
     /* 370251 */ GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(370277), // Rule ID 5827 //
     /* 370256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 370259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 370266 */   // (fp_to_uint_sat_gi:{ *:[i16] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUv1f16:{ *:[i16] } f16:{ *:[f16] }:$Rn)
     /* 370266 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1f16),
     /* 370271 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370275 */   GIR_RootConstrainSelectedInstOperands,
     /* 370276 */   // GIR_Coverage, 5827,
     /* 370276 */   GIR_Done,
     /* 370277 */ // Label 7317: @370277
     /* 370277 */ GIM_Reject,
     /* 370278 */ // Label 7309: @370278
     /* 370278 */ GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(370318), // Rule ID 5580 //
     /* 370283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370293 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370297 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370301 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 370305 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370307 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fceil:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTPUSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370307 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSHr),
     /* 370310 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370312 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370316 */   GIR_RootConstrainSelectedInstOperands,
     /* 370317 */   // GIR_Coverage, 5580,
     /* 370317 */   GIR_EraseRootFromParent_Done,
     /* 370318 */ // Label 7318: @370318
     /* 370318 */ GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(370358), // Rule ID 5583 //
     /* 370323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370333 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370337 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370341 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 370345 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370347 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370347 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUSDr),
     /* 370350 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370352 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370356 */   GIR_RootConstrainSelectedInstOperands,
     /* 370357 */   // GIR_Coverage, 5583,
     /* 370357 */   GIR_EraseRootFromParent_Done,
     /* 370358 */ // Label 7319: @370358
     /* 370358 */ GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(370395), // Rule ID 5584 //
     /* 370363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370370 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370374 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370378 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370382 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370384 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370384 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i32),
     /* 370387 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370389 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370393 */   GIR_RootConstrainSelectedInstOperands,
     /* 370394 */   // GIR_Coverage, 5584,
     /* 370394 */   GIR_EraseRootFromParent_Done,
     /* 370395 */ // Label 7320: @370395
     /* 370395 */ GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(370435), // Rule ID 5640 //
     /* 370400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370406 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370410 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370414 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 370418 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 370422 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370424 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ffloor:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTMUSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSHr),
     /* 370427 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370429 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370433 */   GIR_RootConstrainSelectedInstOperands,
     /* 370434 */   // GIR_Coverage, 5640,
     /* 370434 */   GIR_EraseRootFromParent_Done,
     /* 370435 */ // Label 7321: @370435
     /* 370435 */ GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(370475), // Rule ID 5643 //
     /* 370440 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370443 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370450 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370454 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 370458 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 370462 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370464 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370464 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUSDr),
     /* 370467 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370469 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370473 */   GIR_RootConstrainSelectedInstOperands,
     /* 370474 */   // GIR_Coverage, 5643,
     /* 370474 */   GIR_EraseRootFromParent_Done,
     /* 370475 */ // Label 7322: @370475
     /* 370475 */ GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(370512), // Rule ID 5644 //
     /* 370480 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370483 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370487 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370491 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 370495 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370499 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370501 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i32),
     /* 370504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370506 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370510 */   GIR_RootConstrainSelectedInstOperands,
     /* 370511 */   // GIR_Coverage, 5644,
     /* 370511 */   GIR_EraseRootFromParent_Done,
     /* 370512 */ // Label 7323: @370512
     /* 370512 */ GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(370552), // Rule ID 5760 //
     /* 370517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370520 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370523 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370527 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370531 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 370535 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 370539 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370541 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fround:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTAUSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370541 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSHr),
     /* 370544 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370546 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370550 */   GIR_RootConstrainSelectedInstOperands,
     /* 370551 */   // GIR_Coverage, 5760,
     /* 370551 */   GIR_EraseRootFromParent_Done,
     /* 370552 */ // Label 7324: @370552
     /* 370552 */ GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(370592), // Rule ID 5763 //
     /* 370557 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370567 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370571 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 370575 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 370579 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370581 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370581 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUSDr),
     /* 370584 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370586 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370590 */   GIR_RootConstrainSelectedInstOperands,
     /* 370591 */   // GIR_Coverage, 5763,
     /* 370591 */   GIR_EraseRootFromParent_Done,
     /* 370592 */ // Label 7325: @370592
     /* 370592 */ GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(370629), // Rule ID 5764 //
     /* 370597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370604 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370608 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 370612 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370616 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370618 */   // (fp_to_uint_sat_gi:{ *:[i32] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370618 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i32),
     /* 370621 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370623 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370627 */   GIR_RootConstrainSelectedInstOperands,
     /* 370628 */   // GIR_Coverage, 5764,
     /* 370628 */   GIR_EraseRootFromParent_Done,
     /* 370629 */ // Label 7326: @370629
     /* 370629 */ GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(370669), // Rule ID 5700 //
     /* 370634 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370637 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370644 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370648 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 370652 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 370656 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370658 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZUSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370658 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 370661 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370663 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370667 */   GIR_RootConstrainSelectedInstOperands,
     /* 370668 */   // GIR_Coverage, 5700,
     /* 370668 */   GIR_EraseRootFromParent_Done,
     /* 370669 */ // Label 7327: @370669
     /* 370669 */ GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(370709), // Rule ID 5703 //
     /* 370674 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370677 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370684 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370688 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 370692 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 370696 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370698 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370698 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 370701 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370703 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370707 */   GIR_RootConstrainSelectedInstOperands,
     /* 370708 */   // GIR_Coverage, 5703,
     /* 370708 */   GIR_EraseRootFromParent_Done,
     /* 370709 */ // Label 7328: @370709
     /* 370709 */ GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(370746), // Rule ID 5704 //
     /* 370714 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370721 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370725 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 370729 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370733 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370735 */   // (fp_to_uint_sat_gi:{ *:[i32] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370735 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 370738 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370740 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370744 */   GIR_RootConstrainSelectedInstOperands,
     /* 370745 */   // GIR_Coverage, 5704,
     /* 370745 */   GIR_EraseRootFromParent_Done,
     /* 370746 */ // Label 7329: @370746
     /* 370746 */ GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(370772), // Rule ID 5502 //
     /* 370751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 370754 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370761 */   // (fp_to_uint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370761 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWHr),
     /* 370766 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370770 */   GIR_RootConstrainSelectedInstOperands,
     /* 370771 */   // GIR_Coverage, 5502,
     /* 370771 */   GIR_Done,
     /* 370772 */ // Label 7330: @370772
     /* 370772 */ GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(370795), // Rule ID 5504 //
     /* 370777 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370784 */   // (fp_to_uint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370784 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWSr),
     /* 370789 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370793 */   GIR_RootConstrainSelectedInstOperands,
     /* 370794 */   // GIR_Coverage, 5504,
     /* 370794 */   GIR_Done,
     /* 370795 */ // Label 7331: @370795
     /* 370795 */ GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(370818), // Rule ID 5506 //
     /* 370800 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 370807 */   // (fp_to_uint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370807 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUWDr),
     /* 370812 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370816 */   GIR_RootConstrainSelectedInstOperands,
     /* 370817 */   // GIR_Coverage, 5506,
     /* 370817 */   GIR_Done,
     /* 370818 */ // Label 7332: @370818
     /* 370818 */ GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(370844), // Rule ID 5508 //
     /* 370823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370826 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370833 */   // (fp_to_uint_sat_gi:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 370833 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSHr),
     /* 370838 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370842 */   GIR_RootConstrainSelectedInstOperands,
     /* 370843 */   // GIR_Coverage, 5508,
     /* 370843 */   GIR_Done,
     /* 370844 */ // Label 7333: @370844
     /* 370844 */ GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(370870), // Rule ID 5511 //
     /* 370849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370859 */   // (fp_to_uint_sat_gi:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 370859 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUSDr),
     /* 370864 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370868 */   GIR_RootConstrainSelectedInstOperands,
     /* 370869 */   // GIR_Coverage, 5511,
     /* 370869 */   GIR_Done,
     /* 370870 */ // Label 7334: @370870
     /* 370870 */ GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(370893), // Rule ID 5512 //
     /* 370875 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370878 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 370882 */   // (fp_to_uint_sat_gi:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 370882 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i32),
     /* 370887 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 370891 */   GIR_RootConstrainSelectedInstOperands,
     /* 370892 */   // GIR_Coverage, 5512,
     /* 370892 */   GIR_Done,
     /* 370893 */ // Label 7335: @370893
     /* 370893 */ GIM_Reject,
     /* 370894 */ // Label 7310: @370894
     /* 370894 */ GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(370934), // Rule ID 5581 //
     /* 370899 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370902 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 370905 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370909 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370913 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370917 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 370921 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370923 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fceil:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTPUDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 370923 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDHr),
     /* 370926 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370928 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370932 */   GIR_RootConstrainSelectedInstOperands,
     /* 370933 */   // GIR_Coverage, 5581,
     /* 370933 */   GIR_EraseRootFromParent_Done,
     /* 370934 */ // Label 7336: @370934
     /* 370934 */ GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(370974), // Rule ID 5582 //
     /* 370939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 370942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 370945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370949 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370953 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370957 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 370961 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 370963 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fceil:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTPUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 370963 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUDSr),
     /* 370966 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 370968 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 370972 */   GIR_RootConstrainSelectedInstOperands,
     /* 370973 */   // GIR_Coverage, 5582,
     /* 370973 */   GIR_EraseRootFromParent_Done,
     /* 370974 */ // Label 7337: @370974
     /* 370974 */ GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(371011), // Rule ID 5585 //
     /* 370979 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 370982 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 370986 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 370990 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
     /* 370994 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 370998 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371000 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fceil:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTPUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371000 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTPUv1i64),
     /* 371003 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371005 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371009 */   GIR_RootConstrainSelectedInstOperands,
     /* 371010 */   // GIR_Coverage, 5585,
     /* 371010 */   GIR_EraseRootFromParent_Done,
     /* 371011 */ // Label 7338: @371011
     /* 371011 */ GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(371051), // Rule ID 5641 //
     /* 371016 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371019 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371022 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371026 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371030 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 371034 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 371038 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371040 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ffloor:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTMUDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 371040 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDHr),
     /* 371043 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371045 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371049 */   GIR_RootConstrainSelectedInstOperands,
     /* 371050 */   // GIR_Coverage, 5641,
     /* 371050 */   GIR_EraseRootFromParent_Done,
     /* 371051 */ // Label 7339: @371051
     /* 371051 */ GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(371091), // Rule ID 5642 //
     /* 371056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371059 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371066 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371070 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 371074 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 371078 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371080 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ffloor:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTMUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 371080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUDSr),
     /* 371083 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371085 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371089 */   GIR_RootConstrainSelectedInstOperands,
     /* 371090 */   // GIR_Coverage, 5642,
     /* 371090 */   GIR_EraseRootFromParent_Done,
     /* 371091 */ // Label 7340: @371091
     /* 371091 */ GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(371128), // Rule ID 5645 //
     /* 371096 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371103 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371107 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
     /* 371111 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 371115 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371117 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ffloor:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTMUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371117 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTMUv1i64),
     /* 371120 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371122 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371126 */   GIR_RootConstrainSelectedInstOperands,
     /* 371127 */   // GIR_Coverage, 5645,
     /* 371127 */   GIR_EraseRootFromParent_Done,
     /* 371128 */ // Label 7341: @371128
     /* 371128 */ GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(371168), // Rule ID 5761 //
     /* 371133 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371136 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371143 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371147 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 371151 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 371155 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371157 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fround:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTAUDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 371157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDHr),
     /* 371160 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371162 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371166 */   GIR_RootConstrainSelectedInstOperands,
     /* 371167 */   // GIR_Coverage, 5761,
     /* 371167 */   GIR_EraseRootFromParent_Done,
     /* 371168 */ // Label 7342: @371168
     /* 371168 */ GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(371208), // Rule ID 5762 //
     /* 371173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371183 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371187 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 371191 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 371195 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371197 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fround:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTAUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 371197 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUDSr),
     /* 371200 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371202 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371206 */   GIR_RootConstrainSelectedInstOperands,
     /* 371207 */   // GIR_Coverage, 5762,
     /* 371207 */   GIR_EraseRootFromParent_Done,
     /* 371208 */ // Label 7343: @371208
     /* 371208 */ GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(371245), // Rule ID 5765 //
     /* 371213 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371220 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371224 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
     /* 371228 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 371232 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371234 */   // (fp_to_uint_sat_gi:{ *:[i64] } (fround:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTAUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTAUv1i64),
     /* 371237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371239 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371243 */   GIR_RootConstrainSelectedInstOperands,
     /* 371244 */   // GIR_Coverage, 5765,
     /* 371244 */   GIR_EraseRootFromParent_Done,
     /* 371245 */ // Label 7344: @371245
     /* 371245 */ GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(371285), // Rule ID 5701 //
     /* 371250 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371253 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371260 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371264 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 371268 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 371272 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371274 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$Rn))  =>  (FCVTZUDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 371274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 371277 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371279 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371283 */   GIR_RootConstrainSelectedInstOperands,
     /* 371284 */   // GIR_Coverage, 5701,
     /* 371284 */   GIR_EraseRootFromParent_Done,
     /* 371285 */ // Label 7345: @371285
     /* 371285 */ GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(371325), // Rule ID 5702 //
     /* 371290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371300 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371304 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 371308 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 371312 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371314 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$Rn))  =>  (FCVTZUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 371314 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 371317 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371319 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371323 */   GIR_RootConstrainSelectedInstOperands,
     /* 371324 */   // GIR_Coverage, 5702,
     /* 371324 */   GIR_EraseRootFromParent_Done,
     /* 371325 */ // Label 7346: @371325
     /* 371325 */ GIM_Try, /*On fail goto*//*Label 7347*/ GIMT_Encode4(371362), // Rule ID 5705 //
     /* 371330 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371333 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371337 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371341 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC),
     /* 371345 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 371349 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371351 */   // (fp_to_uint_sat_gi:{ *:[i64] } (ftrunc:{ *:[f64] } f64:{ *:[f64] }:$Rn))  =>  (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371351 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 371354 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371356 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371360 */   GIR_RootConstrainSelectedInstOperands,
     /* 371361 */   // GIR_Coverage, 5705,
     /* 371361 */   GIR_EraseRootFromParent_Done,
     /* 371362 */ // Label 7347: @371362
     /* 371362 */ GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(371388), // Rule ID 5503 //
     /* 371367 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 371370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 371377 */   // (fp_to_uint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 371377 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXHr),
     /* 371382 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371386 */   GIR_RootConstrainSelectedInstOperands,
     /* 371387 */   // GIR_Coverage, 5503,
     /* 371387 */   GIR_Done,
     /* 371388 */ // Label 7348: @371388
     /* 371388 */ GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(371411), // Rule ID 5505 //
     /* 371393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371396 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 371400 */   // (fp_to_uint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 371400 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXSr),
     /* 371405 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371409 */   GIR_RootConstrainSelectedInstOperands,
     /* 371410 */   // GIR_Coverage, 5505,
     /* 371410 */   GIR_Done,
     /* 371411 */ // Label 7349: @371411
     /* 371411 */ GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(371434), // Rule ID 5507 //
     /* 371416 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 371423 */   // (fp_to_uint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371423 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUUXDr),
     /* 371428 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371432 */   GIR_RootConstrainSelectedInstOperands,
     /* 371433 */   // GIR_Coverage, 5507,
     /* 371433 */   GIR_Done,
     /* 371434 */ // Label 7350: @371434
     /* 371434 */ GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(371460), // Rule ID 5509 //
     /* 371439 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371449 */   // (fp_to_uint_sat_gi:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTZUDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 371449 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDHr),
     /* 371454 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371458 */   GIR_RootConstrainSelectedInstOperands,
     /* 371459 */   // GIR_Coverage, 5509,
     /* 371459 */   GIR_Done,
     /* 371460 */ // Label 7351: @371460
     /* 371460 */ GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(371486), // Rule ID 5510 //
     /* 371465 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 371468 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371475 */   // (fp_to_uint_sat_gi:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTZUDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 371475 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUDSr),
     /* 371480 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371484 */   GIR_RootConstrainSelectedInstOperands,
     /* 371485 */   // GIR_Coverage, 5510,
     /* 371485 */   GIR_Done,
     /* 371486 */ // Label 7352: @371486
     /* 371486 */ GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(371509), // Rule ID 5513 //
     /* 371491 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371494 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371498 */   // (fp_to_uint_sat_gi:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTZUv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 371498 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv1i64),
     /* 371503 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371507 */   GIR_RootConstrainSelectedInstOperands,
     /* 371508 */   // GIR_Coverage, 5513,
     /* 371508 */   GIR_Done,
     /* 371509 */ // Label 7353: @371509
     /* 371509 */ GIM_Reject,
     /* 371510 */ // Label 7311: @371510
     /* 371510 */ GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(371533), // Rule ID 5005 //
     /* 371515 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 371518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371522 */   // (fp_to_uint_sat_gi:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)  =>  (FCVTZUv2f32:{ *:[v2i32] } v2f32:{ *:[v2f32] }:$Rn)
     /* 371522 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f32),
     /* 371527 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371531 */   GIR_RootConstrainSelectedInstOperands,
     /* 371532 */   // GIR_Coverage, 5005,
     /* 371532 */   GIR_Done,
     /* 371533 */ // Label 7354: @371533
     /* 371533 */ GIM_Reject,
     /* 371534 */ // Label 7312: @371534
     /* 371534 */ GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(371557), // Rule ID 5007 //
     /* 371539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 371542 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 371546 */   // (fp_to_uint_sat_gi:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)  =>  (FCVTZUv2f64:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$Rn)
     /* 371546 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv2f64),
     /* 371551 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371555 */   GIR_RootConstrainSelectedInstOperands,
     /* 371556 */   // GIR_Coverage, 5007,
     /* 371556 */   GIR_Done,
     /* 371557 */ // Label 7355: @371557
     /* 371557 */ GIM_Reject,
     /* 371558 */ // Label 7313: @371558
     /* 371558 */ GIM_Try, /*On fail goto*//*Label 7356*/ GIMT_Encode4(371584), // Rule ID 5000 //
     /* 371563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 371566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 371569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371573 */   // (fp_to_uint_sat_gi:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)  =>  (FCVTZUv4f16:{ *:[v4i16] } v4f16:{ *:[v4f16] }:$Rn)
     /* 371573 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f16),
     /* 371578 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371582 */   GIR_RootConstrainSelectedInstOperands,
     /* 371583 */   // GIR_Coverage, 5000,
     /* 371583 */   GIR_Done,
     /* 371584 */ // Label 7356: @371584
     /* 371584 */ GIM_Reject,
     /* 371585 */ // Label 7314: @371585
     /* 371585 */ GIM_Try, /*On fail goto*//*Label 7357*/ GIMT_Encode4(371608), // Rule ID 5006 //
     /* 371590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 371593 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 371597 */   // (fp_to_uint_sat_gi:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)  =>  (FCVTZUv4f32:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$Rn)
     /* 371597 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv4f32),
     /* 371602 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371606 */   GIR_RootConstrainSelectedInstOperands,
     /* 371607 */   // GIR_Coverage, 5006,
     /* 371607 */   GIR_Done,
     /* 371608 */ // Label 7357: @371608
     /* 371608 */ GIM_Reject,
     /* 371609 */ // Label 7315: @371609
     /* 371609 */ GIM_Try, /*On fail goto*//*Label 7358*/ GIMT_Encode4(371635), // Rule ID 5001 //
     /* 371614 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 371617 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 371620 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 371624 */   // (fp_to_uint_sat_gi:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)  =>  (FCVTZUv8f16:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$Rn)
     /* 371624 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTZUv8f16),
     /* 371629 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 371633 */   GIR_RootConstrainSelectedInstOperands,
     /* 371634 */   // GIR_Coverage, 5001,
     /* 371634 */   GIR_Done,
     /* 371635 */ // Label 7358: @371635
     /* 371635 */ GIM_Reject,
     /* 371636 */ // Label 7316: @371636
     /* 371636 */ GIM_Reject,
     /* 371637 */ // Label 82: @371637
     /* 371637 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7367*/ GIMT_Encode4(372493),
     /* 371648 */ /*GILLT_s16*//*Label 7359*/ GIMT_Encode4(371688),
     /* 371652 */ /*GILLT_s32*//*Label 7360*/ GIMT_Encode4(371907),
     /* 371656 */ /*GILLT_s64*//*Label 7361*/ GIMT_Encode4(371981), GIMT_Encode4(0),
     /* 371664 */ /*GILLT_v2s32*//*Label 7362*/ GIMT_Encode4(372055),
     /* 371668 */ /*GILLT_v2s64*//*Label 7363*/ GIMT_Encode4(372129),
     /* 371672 */ /*GILLT_v4s16*//*Label 7364*/ GIMT_Encode4(372203),
     /* 371676 */ /*GILLT_v4s32*//*Label 7365*/ GIMT_Encode4(372311), GIMT_Encode4(0),
     /* 371684 */ /*GILLT_v8s16*//*Label 7366*/ GIMT_Encode4(372385),
     /* 371688 */ // Label 7359: @371688
     /* 371688 */ GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(371906),
     /* 371693 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 371696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 371700 */   GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(371741), // Rule ID 5258 //
     /* 371705 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 371708 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371712 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 371716 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 371720 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
     /* 371724 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371726 */     // (fabs:{ *:[f16] } (fsub:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm))  =>  (FABD16:{ *:[f16] } f16:{ *:[f16] }:$Rn, f16:{ *:[f16] }:$Rm)
     /* 371726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD16),
     /* 371729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371731 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371735 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 371739 */     GIR_RootConstrainSelectedInstOperands,
     /* 371740 */     // GIR_Coverage, 5258,
     /* 371740 */     GIR_EraseRootFromParent_Done,
     /* 371741 */   // Label 7369: @371741
     /* 371741 */   GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(371760), // Rule ID 563 //
     /* 371746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 371749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 371753 */     // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FABSHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 371753 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSHr),
     /* 371758 */     GIR_RootConstrainSelectedInstOperands,
     /* 371759 */     // GIR_Coverage, 563,
     /* 371759 */     GIR_Done,
     /* 371760 */   // Label 7370: @371760
     /* 371760 */   GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(371905), // Rule ID 7007 //
     /* 371765 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 371769 */     // (fabs:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } (ANDWri:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (INSERT_SUBREG:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), GPR32:{ *:[i32] }), (logical_imm32_XFORM:{ *:[i32] } 32767:{ *:[i32] })), FPR32:{ *:[i32] }), hsub:{ *:[i32] })
     /* 371769 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 371772 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 371776 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371781 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 371783 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
     /* 371786 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 371790 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371795 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 371798 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 371802 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 371805 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371810 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371815 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 371820 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
     /* 371823 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 371827 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371832 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 371835 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 371840 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 371843 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::ANDWri),
     /* 371847 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371852 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 371855 */     GIR_CustomRenderer, /*InsnID*/2, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderLogicalImm32), // 
     /* 371860 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 371862 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 371865 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 371869 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 371874 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 371877 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 371885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 371887 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 371894 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 371899 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371904 */     // GIR_Coverage, 7007,
     /* 371904 */     GIR_EraseRootFromParent_Done,
     /* 371905 */   // Label 7371: @371905
     /* 371905 */   GIM_Reject,
     /* 371906 */ // Label 7368: @371906
     /* 371906 */ GIM_Reject,
     /* 371907 */ // Label 7360: @371907
     /* 371907 */ GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(371980),
     /* 371912 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 371915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371919 */   GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(371960), // Rule ID 5259 //
     /* 371924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 371927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 371931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 371935 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 371939 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 371943 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 371945 */     // (fabs:{ *:[f32] } (fsub:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm))  =>  (FABD32:{ *:[f32] } f32:{ *:[f32] }:$Rn, f32:{ *:[f32] }:$Rm)
     /* 371945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD32),
     /* 371948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 371950 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 371954 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 371958 */     GIR_RootConstrainSelectedInstOperands,
     /* 371959 */     // GIR_Coverage, 5259,
     /* 371959 */     GIR_EraseRootFromParent_Done,
     /* 371960 */   // Label 7373: @371960
     /* 371960 */   GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(371979), // Rule ID 564 //
     /* 371965 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 371968 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 371972 */     // (fabs:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FABSSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 371972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSSr),
     /* 371977 */     GIR_RootConstrainSelectedInstOperands,
     /* 371978 */     // GIR_Coverage, 564,
     /* 371978 */     GIR_Done,
     /* 371979 */   // Label 7374: @371979
     /* 371979 */   GIM_Reject,
     /* 371980 */ // Label 7372: @371980
     /* 371980 */ GIM_Reject,
     /* 371981 */ // Label 7361: @371981
     /* 371981 */ GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(372054),
     /* 371986 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 371989 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 371993 */   GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(372034), // Rule ID 5260 //
     /* 371998 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 372013 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 372017 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372019 */     // (fabs:{ *:[f64] } (fsub:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm))  =>  (FABD64:{ *:[f64] } f64:{ *:[f64] }:$Rn, f64:{ *:[f64] }:$Rm)
     /* 372019 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABD64),
     /* 372022 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372024 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372028 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372032 */     GIR_RootConstrainSelectedInstOperands,
     /* 372033 */     // GIR_Coverage, 5260,
     /* 372033 */     GIR_EraseRootFromParent_Done,
     /* 372034 */   // Label 7376: @372034
     /* 372034 */   GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(372053), // Rule ID 565 //
     /* 372039 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 372042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372046 */     // (fabs:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FABSDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 372046 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSDr),
     /* 372051 */     GIR_RootConstrainSelectedInstOperands,
     /* 372052 */     // GIR_Coverage, 565,
     /* 372052 */     GIR_Done,
     /* 372053 */   // Label 7377: @372053
     /* 372053 */   GIM_Reject,
     /* 372054 */ // Label 7375: @372054
     /* 372054 */ GIM_Reject,
     /* 372055 */ // Label 7362: @372055
     /* 372055 */ GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(372128),
     /* 372060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 372063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372067 */   GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(372108), // Rule ID 5072 //
     /* 372072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372083 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 372087 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 372091 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372093 */     // (fabs:{ *:[v2f32] } (fsub:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm))  =>  (FABDv2f32:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$Rn, v2f32:{ *:[v2f32] }:$Rm)
     /* 372093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f32),
     /* 372096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372098 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372102 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372106 */     GIR_RootConstrainSelectedInstOperands,
     /* 372107 */     // GIR_Coverage, 5072,
     /* 372107 */     GIR_EraseRootFromParent_Done,
     /* 372108 */   // Label 7379: @372108
     /* 372108 */   GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(372127), // Rule ID 798 //
     /* 372113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372116 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372120 */     // (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FABSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 372120 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f32),
     /* 372125 */     GIR_RootConstrainSelectedInstOperands,
     /* 372126 */     // GIR_Coverage, 798,
     /* 372126 */     GIR_Done,
     /* 372127 */   // Label 7380: @372127
     /* 372127 */   GIM_Reject,
     /* 372128 */ // Label 7378: @372128
     /* 372128 */ GIM_Reject,
     /* 372129 */ // Label 7363: @372129
     /* 372129 */ GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(372202),
     /* 372134 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 372137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372141 */   GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(372182), // Rule ID 5074 //
     /* 372146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372153 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372157 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 372161 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 372165 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372167 */     // (fabs:{ *:[v2f64] } (fsub:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm))  =>  (FABDv2f64:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, v2f64:{ *:[v2f64] }:$Rm)
     /* 372167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv2f64),
     /* 372170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372172 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372180 */     GIR_RootConstrainSelectedInstOperands,
     /* 372181 */     // GIR_Coverage, 5074,
     /* 372181 */     GIR_EraseRootFromParent_Done,
     /* 372182 */   // Label 7382: @372182
     /* 372182 */   GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(372201), // Rule ID 800 //
     /* 372187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372194 */     // (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FABSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 372194 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv2f64),
     /* 372199 */     GIR_RootConstrainSelectedInstOperands,
     /* 372200 */     // GIR_Coverage, 800,
     /* 372200 */     GIR_Done,
     /* 372201 */   // Label 7383: @372201
     /* 372201 */   GIM_Reject,
     /* 372202 */ // Label 7381: @372202
     /* 372202 */ GIM_Reject,
     /* 372203 */ // Label 7364: @372203
     /* 372203 */ GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(372310),
     /* 372208 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 372211 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372215 */   GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(372256), // Rule ID 5075 //
     /* 372220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 372235 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 372239 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372241 */     // (fabs:{ *:[v4f16] } (fsub:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm))  =>  (FABDv4f16:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$Rn, v4f16:{ *:[v4f16] }:$Rm)
     /* 372241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f16),
     /* 372244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372254 */     GIR_RootConstrainSelectedInstOperands,
     /* 372255 */     // GIR_Coverage, 5075,
     /* 372255 */     GIR_EraseRootFromParent_Done,
     /* 372256 */   // Label 7385: @372256
     /* 372256 */   GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(372275), // Rule ID 796 //
     /* 372261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372264 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372268 */     // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FABSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 372268 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f16),
     /* 372273 */     GIR_RootConstrainSelectedInstOperands,
     /* 372274 */     // GIR_Coverage, 796,
     /* 372274 */     GIR_Done,
     /* 372275 */   // Label 7386: @372275
     /* 372275 */   GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(372309), // Rule ID 7009 //
     /* 372280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372283 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372287 */     // (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (BICv4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
     /* 372287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv4i16),
     /* 372290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372292 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372294 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
     /* 372304 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 372307 */     GIR_RootConstrainSelectedInstOperands,
     /* 372308 */     // GIR_Coverage, 7009,
     /* 372308 */     GIR_EraseRootFromParent_Done,
     /* 372309 */   // Label 7387: @372309
     /* 372309 */   GIM_Reject,
     /* 372310 */ // Label 7384: @372310
     /* 372310 */ GIM_Reject,
     /* 372311 */ // Label 7365: @372311
     /* 372311 */ GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(372384),
     /* 372316 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 372319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372323 */   GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(372364), // Rule ID 5073 //
     /* 372328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372335 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372339 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 372343 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 372347 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372349 */     // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm))  =>  (FABDv4f32:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, v4f32:{ *:[v4f32] }:$Rm)
     /* 372349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv4f32),
     /* 372352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372354 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372362 */     GIR_RootConstrainSelectedInstOperands,
     /* 372363 */     // GIR_Coverage, 5073,
     /* 372363 */     GIR_EraseRootFromParent_Done,
     /* 372364 */   // Label 7389: @372364
     /* 372364 */   GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(372383), // Rule ID 799 //
     /* 372369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372372 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372376 */     // (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FABSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 372376 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv4f32),
     /* 372381 */     GIR_RootConstrainSelectedInstOperands,
     /* 372382 */     // GIR_Coverage, 799,
     /* 372382 */     GIR_Done,
     /* 372383 */   // Label 7390: @372383
     /* 372383 */   GIM_Reject,
     /* 372384 */ // Label 7388: @372384
     /* 372384 */ GIM_Reject,
     /* 372385 */ // Label 7366: @372385
     /* 372385 */ GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(372492),
     /* 372390 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 372393 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372397 */   GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(372438), // Rule ID 5076 //
     /* 372402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 372409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 372413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 372417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 372421 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 372423 */     // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm))  =>  (FABDv8f16:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, v8f16:{ *:[v8f16] }:$Rm)
     /* 372423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FABDv8f16),
     /* 372426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372428 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 372432 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 372436 */     GIR_RootConstrainSelectedInstOperands,
     /* 372437 */     // GIR_Coverage, 5076,
     /* 372437 */     GIR_EraseRootFromParent_Done,
     /* 372438 */   // Label 7392: @372438
     /* 372438 */   GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(372457), // Rule ID 797 //
     /* 372443 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372446 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372450 */     // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FABSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 372450 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FABSv8f16),
     /* 372455 */     GIR_RootConstrainSelectedInstOperands,
     /* 372456 */     // GIR_Coverage, 797,
     /* 372456 */     GIR_Done,
     /* 372457 */   // Label 7393: @372457
     /* 372457 */   GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(372491), // Rule ID 7010 //
     /* 372462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372465 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372469 */     // (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (BICv8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, 128:{ *:[i32] }, 8:{ *:[i32] })
     /* 372469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BICv8i16),
     /* 372472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 372474 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372476 */     GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(128),
     /* 372486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
     /* 372489 */     GIR_RootConstrainSelectedInstOperands,
     /* 372490 */     // GIR_Coverage, 7010,
     /* 372490 */     GIR_EraseRootFromParent_Done,
     /* 372491 */   // Label 7394: @372491
     /* 372491 */   GIM_Reject,
     /* 372492 */ // Label 7391: @372492
     /* 372492 */ GIM_Reject,
     /* 372493 */ // Label 7367: @372493
     /* 372493 */ GIM_Reject,
     /* 372494 */ // Label 83: @372494
     /* 372494 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7403*/ GIMT_Encode4(372775),
     /* 372505 */ /*GILLT_s16*//*Label 7395*/ GIMT_Encode4(372545),
     /* 372509 */ /*GILLT_s32*//*Label 7396*/ GIMT_Encode4(372572),
     /* 372513 */ /*GILLT_s64*//*Label 7397*/ GIMT_Encode4(372596), GIMT_Encode4(0),
     /* 372521 */ /*GILLT_v2s32*//*Label 7398*/ GIMT_Encode4(372620),
     /* 372525 */ /*GILLT_v2s64*//*Label 7399*/ GIMT_Encode4(372651),
     /* 372529 */ /*GILLT_v4s16*//*Label 7400*/ GIMT_Encode4(372682),
     /* 372533 */ /*GILLT_v4s32*//*Label 7401*/ GIMT_Encode4(372713), GIMT_Encode4(0),
     /* 372541 */ /*GILLT_v8s16*//*Label 7402*/ GIMT_Encode4(372744),
     /* 372545 */ // Label 7395: @372545
     /* 372545 */ GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(372571), // Rule ID 4900 //
     /* 372550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 372553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 372556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 372560 */   // (fcanonicalize:{ *:[f16] } f16:{ *:[f16] }:$a)  =>  (FMINNMHrr:{ *:[f16] } f16:{ *:[f16] }:$a, f16:{ *:[f16] }:$a)
     /* 372560 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 372563 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372565 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372567 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372569 */   GIR_RootConstrainSelectedInstOperands,
     /* 372570 */   // GIR_Coverage, 4900,
     /* 372570 */   GIR_EraseRootFromParent_Done,
     /* 372571 */ // Label 7404: @372571
     /* 372571 */ GIM_Reject,
     /* 372572 */ // Label 7396: @372572
     /* 372572 */ GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(372595), // Rule ID 4897 //
     /* 372577 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 372580 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 372584 */   // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$a)  =>  (FMINNMSrr:{ *:[f32] } f32:{ *:[f32] }:$a, f32:{ *:[f32] }:$a)
     /* 372584 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 372587 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372589 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372591 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372593 */   GIR_RootConstrainSelectedInstOperands,
     /* 372594 */   // GIR_Coverage, 4897,
     /* 372594 */   GIR_EraseRootFromParent_Done,
     /* 372595 */ // Label 7405: @372595
     /* 372595 */ GIM_Reject,
     /* 372596 */ // Label 7397: @372596
     /* 372596 */ GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(372619), // Rule ID 4894 //
     /* 372601 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 372604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372608 */   // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$a)  =>  (FMINNMDrr:{ *:[f64] } f64:{ *:[f64] }:$a, f64:{ *:[f64] }:$a)
     /* 372608 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 372611 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372613 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372615 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 372617 */   GIR_RootConstrainSelectedInstOperands,
     /* 372618 */   // GIR_Coverage, 4894,
     /* 372618 */   GIR_EraseRootFromParent_Done,
     /* 372619 */ // Label 7406: @372619
     /* 372619 */ GIM_Reject,
     /* 372620 */ // Label 7398: @372620
     /* 372620 */ GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(372650), // Rule ID 5085 //
     /* 372625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 372631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372639 */   // (fcanonicalize:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rn)
     /* 372639 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 372642 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372644 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372646 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372648 */   GIR_RootConstrainSelectedInstOperands,
     /* 372649 */   // GIR_Coverage, 5085,
     /* 372649 */   GIR_EraseRootFromParent_Done,
     /* 372650 */ // Label 7407: @372650
     /* 372650 */ GIM_Reject,
     /* 372651 */ // Label 7399: @372651
     /* 372651 */ GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(372681), // Rule ID 5079 //
     /* 372656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 372662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372666 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372670 */   // (fcanonicalize:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn)
     /* 372670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 372673 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372675 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372677 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372679 */   GIR_RootConstrainSelectedInstOperands,
     /* 372680 */   // GIR_Coverage, 5079,
     /* 372680 */   GIR_EraseRootFromParent_Done,
     /* 372681 */ // Label 7408: @372681
     /* 372681 */ GIM_Reject,
     /* 372682 */ // Label 7400: @372682
     /* 372682 */ GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(372712), // Rule ID 5091 //
     /* 372687 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372690 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 372693 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372697 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372701 */   // (fcanonicalize:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rn)
     /* 372701 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 372704 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372706 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372708 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372710 */   GIR_RootConstrainSelectedInstOperands,
     /* 372711 */   // GIR_Coverage, 5091,
     /* 372711 */   GIR_EraseRootFromParent_Done,
     /* 372712 */ // Label 7409: @372712
     /* 372712 */ GIM_Reject,
     /* 372713 */ // Label 7401: @372713
     /* 372713 */ GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(372743), // Rule ID 5082 //
     /* 372718 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372721 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 372724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372728 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372732 */   // (fcanonicalize:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn)
     /* 372732 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 372735 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372737 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372739 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372741 */   GIR_RootConstrainSelectedInstOperands,
     /* 372742 */   // GIR_Coverage, 5082,
     /* 372742 */   GIR_EraseRootFromParent_Done,
     /* 372743 */ // Label 7410: @372743
     /* 372743 */ GIM_Reject,
     /* 372744 */ // Label 7402: @372744
     /* 372744 */ GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(372774), // Rule ID 5088 //
     /* 372749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 372752 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 372755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372759 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 372763 */   // (fcanonicalize:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn)
     /* 372763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 372766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 372768 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372770 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 372772 */   GIR_RootConstrainSelectedInstOperands,
     /* 372773 */   // GIR_Coverage, 5088,
     /* 372773 */   GIR_EraseRootFromParent_Done,
     /* 372774 */ // Label 7411: @372774
     /* 372774 */ GIM_Reject,
     /* 372775 */ // Label 7403: @372775
     /* 372775 */ GIM_Reject,
     /* 372776 */ // Label 84: @372776
     /* 372776 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7420*/ GIMT_Encode4(373153),
     /* 372787 */ /*GILLT_s16*//*Label 7412*/ GIMT_Encode4(372827),
     /* 372791 */ /*GILLT_s32*//*Label 7413*/ GIMT_Encode4(372865),
     /* 372795 */ /*GILLT_s64*//*Label 7414*/ GIMT_Encode4(372903), GIMT_Encode4(0),
     /* 372803 */ /*GILLT_v2s32*//*Label 7415*/ GIMT_Encode4(372963),
     /* 372807 */ /*GILLT_v2s64*//*Label 7416*/ GIMT_Encode4(373001),
     /* 372811 */ /*GILLT_v4s16*//*Label 7417*/ GIMT_Encode4(373039),
     /* 372815 */ /*GILLT_v4s32*//*Label 7418*/ GIMT_Encode4(373077), GIMT_Encode4(0),
     /* 372823 */ /*GILLT_v8s16*//*Label 7419*/ GIMT_Encode4(373115),
     /* 372827 */ // Label 7412: @372827
     /* 372827 */ GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(372864), // Rule ID 650 //
     /* 372832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 372835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 372838 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 372841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 372845 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 372849 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 372853 */   // (fminnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 372853 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 372858 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 372862 */   GIR_RootConstrainSelectedInstOperands,
     /* 372863 */   // GIR_Coverage, 650,
     /* 372863 */   GIR_Done,
     /* 372864 */ // Label 7421: @372864
     /* 372864 */ GIM_Reject,
     /* 372865 */ // Label 7413: @372865
     /* 372865 */ GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(372902), // Rule ID 652 //
     /* 372870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 372873 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 372876 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 372879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 372883 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 372887 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 372891 */   // (fminnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 372891 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 372896 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 372900 */   GIR_RootConstrainSelectedInstOperands,
     /* 372901 */   // GIR_Coverage, 652,
     /* 372901 */   GIR_Done,
     /* 372902 */ // Label 7422: @372902
     /* 372902 */ GIM_Reject,
     /* 372903 */ // Label 7414: @372903
     /* 372903 */ GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(372962),
     /* 372908 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 372911 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 372914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372922 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372926 */   GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(372945), // Rule ID 654 //
     /* 372931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 372934 */     // (fminnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 372934 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 372939 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 372943 */     GIR_RootConstrainSelectedInstOperands,
     /* 372944 */     // GIR_Coverage, 654,
     /* 372944 */     GIR_Done,
     /* 372945 */   // Label 7424: @372945
     /* 372945 */   GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(372961), // Rule ID 4891 //
     /* 372950 */     // (fminnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMINNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 372950 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 372955 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 372959 */     GIR_RootConstrainSelectedInstOperands,
     /* 372960 */     // GIR_Coverage, 4891,
     /* 372960 */     GIR_Done,
     /* 372961 */   // Label 7425: @372961
     /* 372961 */   GIM_Reject,
     /* 372962 */ // Label 7423: @372962
     /* 372962 */ GIM_Reject,
     /* 372963 */ // Label 7415: @372963
     /* 372963 */ GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(373000), // Rule ID 1303 //
     /* 372968 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 372971 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 372974 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 372977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372981 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372985 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 372989 */   // (fminnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 372989 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 372994 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 372998 */   GIR_RootConstrainSelectedInstOperands,
     /* 372999 */   // GIR_Coverage, 1303,
     /* 372999 */   GIR_Done,
     /* 373000 */ // Label 7426: @373000
     /* 373000 */ GIM_Reject,
     /* 373001 */ // Label 7416: @373001
     /* 373001 */ GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(373038), // Rule ID 1307 //
     /* 373006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373009 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 373012 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 373015 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373019 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373023 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373027 */   // (fminnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 373027 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 373032 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373036 */   GIR_RootConstrainSelectedInstOperands,
     /* 373037 */   // GIR_Coverage, 1307,
     /* 373037 */   GIR_Done,
     /* 373038 */ // Label 7427: @373038
     /* 373038 */ GIM_Reject,
     /* 373039 */ // Label 7417: @373039
     /* 373039 */ GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(373076), // Rule ID 1299 //
     /* 373044 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373047 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 373050 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 373053 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373057 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373061 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373065 */   // (fminnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 373065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 373070 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373074 */   GIR_RootConstrainSelectedInstOperands,
     /* 373075 */   // GIR_Coverage, 1299,
     /* 373075 */   GIR_Done,
     /* 373076 */ // Label 7428: @373076
     /* 373076 */ GIM_Reject,
     /* 373077 */ // Label 7418: @373077
     /* 373077 */ GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(373114), // Rule ID 1305 //
     /* 373082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373085 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 373088 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 373091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373095 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373099 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373103 */   // (fminnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 373103 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 373108 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373112 */   GIR_RootConstrainSelectedInstOperands,
     /* 373113 */   // GIR_Coverage, 1305,
     /* 373113 */   GIR_Done,
     /* 373114 */ // Label 7429: @373114
     /* 373114 */ GIM_Reject,
     /* 373115 */ // Label 7419: @373115
     /* 373115 */ GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(373152), // Rule ID 1301 //
     /* 373120 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373123 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 373126 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 373129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373133 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373137 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373141 */   // (fminnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 373141 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 373146 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373150 */   GIR_RootConstrainSelectedInstOperands,
     /* 373151 */   // GIR_Coverage, 1301,
     /* 373151 */   GIR_Done,
     /* 373152 */ // Label 7430: @373152
     /* 373152 */ GIM_Reject,
     /* 373153 */ // Label 7420: @373153
     /* 373153 */ GIM_Reject,
     /* 373154 */ // Label 85: @373154
     /* 373154 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7439*/ GIMT_Encode4(373531),
     /* 373165 */ /*GILLT_s16*//*Label 7431*/ GIMT_Encode4(373205),
     /* 373169 */ /*GILLT_s32*//*Label 7432*/ GIMT_Encode4(373243),
     /* 373173 */ /*GILLT_s64*//*Label 7433*/ GIMT_Encode4(373281), GIMT_Encode4(0),
     /* 373181 */ /*GILLT_v2s32*//*Label 7434*/ GIMT_Encode4(373341),
     /* 373185 */ /*GILLT_v2s64*//*Label 7435*/ GIMT_Encode4(373379),
     /* 373189 */ /*GILLT_v4s16*//*Label 7436*/ GIMT_Encode4(373417),
     /* 373193 */ /*GILLT_v4s32*//*Label 7437*/ GIMT_Encode4(373455), GIMT_Encode4(0),
     /* 373201 */ /*GILLT_v8s16*//*Label 7438*/ GIMT_Encode4(373493),
     /* 373205 */ // Label 7431: @373205
     /* 373205 */ GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(373242), // Rule ID 638 //
     /* 373210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 373213 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 373216 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 373219 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373223 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373227 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373231 */   // (fmaxnum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 373231 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMHrr),
     /* 373236 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373240 */   GIR_RootConstrainSelectedInstOperands,
     /* 373241 */   // GIR_Coverage, 638,
     /* 373241 */   GIR_Done,
     /* 373242 */ // Label 7440: @373242
     /* 373242 */ GIM_Reject,
     /* 373243 */ // Label 7432: @373243
     /* 373243 */ GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(373280), // Rule ID 640 //
     /* 373248 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 373251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 373254 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373261 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373265 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373269 */   // (fmaxnum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 373269 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMSrr),
     /* 373274 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373278 */   GIR_RootConstrainSelectedInstOperands,
     /* 373279 */   // GIR_Coverage, 640,
     /* 373279 */   GIR_Done,
     /* 373280 */ // Label 7441: @373280
     /* 373280 */ GIM_Reject,
     /* 373281 */ // Label 7433: @373281
     /* 373281 */ GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(373340),
     /* 373286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 373289 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 373292 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373296 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373300 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373304 */   GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(373323), // Rule ID 642 //
     /* 373309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 373312 */     // (fmaxnum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 373312 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 373317 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373321 */     GIR_RootConstrainSelectedInstOperands,
     /* 373322 */     // GIR_Coverage, 642,
     /* 373322 */     GIR_Done,
     /* 373323 */   // Label 7443: @373323
     /* 373323 */   GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(373339), // Rule ID 4890 //
     /* 373328 */     // (fmaxnum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMAXNMDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 373328 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 373333 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373337 */     GIR_RootConstrainSelectedInstOperands,
     /* 373338 */     // GIR_Coverage, 4890,
     /* 373338 */     GIR_Done,
     /* 373339 */   // Label 7444: @373339
     /* 373339 */   GIM_Reject,
     /* 373340 */ // Label 7442: @373340
     /* 373340 */ GIM_Reject,
     /* 373341 */ // Label 7434: @373341
     /* 373341 */ GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(373378), // Rule ID 1273 //
     /* 373346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373349 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 373352 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 373355 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373359 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373363 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373367 */   // (fmaxnum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 373367 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f32),
     /* 373372 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373376 */   GIR_RootConstrainSelectedInstOperands,
     /* 373377 */   // GIR_Coverage, 1273,
     /* 373377 */   GIR_Done,
     /* 373378 */ // Label 7445: @373378
     /* 373378 */ GIM_Reject,
     /* 373379 */ // Label 7435: @373379
     /* 373379 */ GIM_Try, /*On fail goto*//*Label 7446*/ GIMT_Encode4(373416), // Rule ID 1277 //
     /* 373384 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373387 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 373390 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 373393 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373397 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373401 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373405 */   // (fmaxnum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 373405 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f64),
     /* 373410 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373414 */   GIR_RootConstrainSelectedInstOperands,
     /* 373415 */   // GIR_Coverage, 1277,
     /* 373415 */   GIR_Done,
     /* 373416 */ // Label 7446: @373416
     /* 373416 */ GIM_Reject,
     /* 373417 */ // Label 7436: @373417
     /* 373417 */ GIM_Try, /*On fail goto*//*Label 7447*/ GIMT_Encode4(373454), // Rule ID 1269 //
     /* 373422 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373425 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 373428 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 373431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373435 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373439 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373443 */   // (fmaxnum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 373443 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f16),
     /* 373448 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373452 */   GIR_RootConstrainSelectedInstOperands,
     /* 373453 */   // GIR_Coverage, 1269,
     /* 373453 */   GIR_Done,
     /* 373454 */ // Label 7447: @373454
     /* 373454 */ GIM_Reject,
     /* 373455 */ // Label 7437: @373455
     /* 373455 */ GIM_Try, /*On fail goto*//*Label 7448*/ GIMT_Encode4(373492), // Rule ID 1275 //
     /* 373460 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373463 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 373466 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 373469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373477 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373481 */   // (fmaxnum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 373481 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f32),
     /* 373486 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373490 */   GIR_RootConstrainSelectedInstOperands,
     /* 373491 */   // GIR_Coverage, 1275,
     /* 373491 */   GIR_Done,
     /* 373492 */ // Label 7448: @373492
     /* 373492 */ GIM_Reject,
     /* 373493 */ // Label 7438: @373493
     /* 373493 */ GIM_Try, /*On fail goto*//*Label 7449*/ GIMT_Encode4(373530), // Rule ID 1271 //
     /* 373498 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373501 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 373504 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 373507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373511 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373515 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373519 */   // (fmaxnum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 373519 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv8f16),
     /* 373524 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373528 */   GIR_RootConstrainSelectedInstOperands,
     /* 373529 */   // GIR_Coverage, 1271,
     /* 373529 */   GIR_Done,
     /* 373530 */ // Label 7449: @373530
     /* 373530 */ GIM_Reject,
     /* 373531 */ // Label 7439: @373531
     /* 373531 */ GIM_Reject,
     /* 373532 */ // Label 86: @373532
     /* 373532 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7458*/ GIMT_Encode4(373881),
     /* 373543 */ /*GILLT_s16*//*Label 7450*/ GIMT_Encode4(373583),
     /* 373547 */ /*GILLT_s32*//*Label 7451*/ GIMT_Encode4(373621),
     /* 373551 */ /*GILLT_s64*//*Label 7452*/ GIMT_Encode4(373656), GIMT_Encode4(0),
     /* 373559 */ /*GILLT_v2s32*//*Label 7453*/ GIMT_Encode4(373691),
     /* 373563 */ /*GILLT_v2s64*//*Label 7454*/ GIMT_Encode4(373729),
     /* 373567 */ /*GILLT_v4s16*//*Label 7455*/ GIMT_Encode4(373767),
     /* 373571 */ /*GILLT_v4s32*//*Label 7456*/ GIMT_Encode4(373805), GIMT_Encode4(0),
     /* 373579 */ /*GILLT_v8s16*//*Label 7457*/ GIMT_Encode4(373843),
     /* 373583 */ // Label 7450: @373583
     /* 373583 */ GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(373620), // Rule ID 4898 //
     /* 373588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 373591 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 373594 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 373597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373601 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373605 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373609 */   // (fminnum_ieee:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)  =>  (FMINNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 373609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMHrr),
     /* 373614 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373618 */   GIR_RootConstrainSelectedInstOperands,
     /* 373619 */   // GIR_Coverage, 4898,
     /* 373619 */   GIR_Done,
     /* 373620 */ // Label 7459: @373620
     /* 373620 */ GIM_Reject,
     /* 373621 */ // Label 7451: @373621
     /* 373621 */ GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(373655), // Rule ID 4895 //
     /* 373626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 373629 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373636 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373640 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373644 */   // (fminnum_ieee:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)  =>  (FMINNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 373644 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMSrr),
     /* 373649 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373653 */   GIR_RootConstrainSelectedInstOperands,
     /* 373654 */   // GIR_Coverage, 4895,
     /* 373654 */   GIR_Done,
     /* 373655 */ // Label 7460: @373655
     /* 373655 */ GIM_Reject,
     /* 373656 */ // Label 7452: @373656
     /* 373656 */ GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(373690), // Rule ID 4892 //
     /* 373661 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 373664 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 373667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373671 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373675 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373679 */   // (fminnum_ieee:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)  =>  (FMINNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 373679 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMDrr),
     /* 373684 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373688 */   GIR_RootConstrainSelectedInstOperands,
     /* 373689 */   // GIR_Coverage, 4892,
     /* 373689 */   GIR_Done,
     /* 373690 */ // Label 7461: @373690
     /* 373690 */ GIM_Reject,
     /* 373691 */ // Label 7453: @373691
     /* 373691 */ GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(373728), // Rule ID 5083 //
     /* 373696 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373699 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 373702 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 373705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373709 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373713 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373717 */   // (fminnum_ieee:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 373717 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f32),
     /* 373722 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373726 */   GIR_RootConstrainSelectedInstOperands,
     /* 373727 */   // GIR_Coverage, 5083,
     /* 373727 */   GIR_Done,
     /* 373728 */ // Label 7462: @373728
     /* 373728 */ GIM_Reject,
     /* 373729 */ // Label 7454: @373729
     /* 373729 */ GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(373766), // Rule ID 5077 //
     /* 373734 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373737 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 373740 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 373743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373747 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373751 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373755 */   // (fminnum_ieee:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 373755 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv2f64),
     /* 373760 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373764 */   GIR_RootConstrainSelectedInstOperands,
     /* 373765 */   // GIR_Coverage, 5077,
     /* 373765 */   GIR_Done,
     /* 373766 */ // Label 7463: @373766
     /* 373766 */ GIM_Reject,
     /* 373767 */ // Label 7455: @373767
     /* 373767 */ GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(373804), // Rule ID 5089 //
     /* 373772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 373778 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 373781 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373785 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373789 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 373793 */   // (fminnum_ieee:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 373793 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f16),
     /* 373798 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373802 */   GIR_RootConstrainSelectedInstOperands,
     /* 373803 */   // GIR_Coverage, 5089,
     /* 373803 */   GIR_Done,
     /* 373804 */ // Label 7464: @373804
     /* 373804 */ GIM_Reject,
     /* 373805 */ // Label 7456: @373805
     /* 373805 */ GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(373842), // Rule ID 5080 //
     /* 373810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 373813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 373816 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 373819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373823 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373827 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373831 */   // (fminnum_ieee:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 373831 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv4f32),
     /* 373836 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373840 */   GIR_RootConstrainSelectedInstOperands,
     /* 373841 */   // GIR_Coverage, 5080,
     /* 373841 */   GIR_Done,
     /* 373842 */ // Label 7465: @373842
     /* 373842 */ GIM_Reject,
     /* 373843 */ // Label 7457: @373843
     /* 373843 */ GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(373880), // Rule ID 5086 //
     /* 373848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 373851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 373854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 373857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373865 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 373869 */   // (fminnum_ieee:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 373869 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMv8f16),
     /* 373874 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373878 */   GIR_RootConstrainSelectedInstOperands,
     /* 373879 */   // GIR_Coverage, 5086,
     /* 373879 */   GIR_Done,
     /* 373880 */ // Label 7466: @373880
     /* 373880 */ GIM_Reject,
     /* 373881 */ // Label 7458: @373881
     /* 373881 */ GIM_Reject,
     /* 373882 */ // Label 87: @373882
     /* 373882 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7475*/ GIMT_Encode4(374231),
     /* 373893 */ /*GILLT_s16*//*Label 7467*/ GIMT_Encode4(373933),
     /* 373897 */ /*GILLT_s32*//*Label 7468*/ GIMT_Encode4(373971),
     /* 373901 */ /*GILLT_s64*//*Label 7469*/ GIMT_Encode4(374006), GIMT_Encode4(0),
     /* 373909 */ /*GILLT_v2s32*//*Label 7470*/ GIMT_Encode4(374041),
     /* 373913 */ /*GILLT_v2s64*//*Label 7471*/ GIMT_Encode4(374079),
     /* 373917 */ /*GILLT_v4s16*//*Label 7472*/ GIMT_Encode4(374117),
     /* 373921 */ /*GILLT_v4s32*//*Label 7473*/ GIMT_Encode4(374155), GIMT_Encode4(0),
     /* 373929 */ /*GILLT_v8s16*//*Label 7474*/ GIMT_Encode4(374193),
     /* 373933 */ // Label 7467: @373933
     /* 373933 */ GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(373970), // Rule ID 4899 //
     /* 373938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 373941 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 373944 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 373947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373955 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 373959 */   // (fmaxnum_ieee:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)  =>  (FMAXNMHrr:{ *:[f16] } FPR16:{ *:[f16] }:$a, FPR16:{ *:[f16] }:$b)
     /* 373959 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMHrr),
     /* 373964 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 373968 */   GIR_RootConstrainSelectedInstOperands,
     /* 373969 */   // GIR_Coverage, 4899,
     /* 373969 */   GIR_Done,
     /* 373970 */ // Label 7476: @373970
     /* 373970 */ GIM_Reject,
     /* 373971 */ // Label 7468: @373971
     /* 373971 */ GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(374005), // Rule ID 4896 //
     /* 373976 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 373979 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 373982 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373986 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373990 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 373994 */   // (fmaxnum_ieee:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)  =>  (FMAXNMSrr:{ *:[f32] } FPR32:{ *:[f32] }:$a, FPR32:{ *:[f32] }:$b)
     /* 373994 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMSrr),
     /* 373999 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374003 */   GIR_RootConstrainSelectedInstOperands,
     /* 374004 */   // GIR_Coverage, 4896,
     /* 374004 */   GIR_Done,
     /* 374005 */ // Label 7477: @374005
     /* 374005 */ GIM_Reject,
     /* 374006 */ // Label 7469: @374006
     /* 374006 */ GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(374040), // Rule ID 4893 //
     /* 374011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 374014 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 374017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374021 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374025 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374029 */   // (fmaxnum_ieee:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)  =>  (FMAXNMDrr:{ *:[f64] } FPR64:{ *:[f64] }:$a, FPR64:{ *:[f64] }:$b)
     /* 374029 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMDrr),
     /* 374034 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374038 */   GIR_RootConstrainSelectedInstOperands,
     /* 374039 */   // GIR_Coverage, 4893,
     /* 374039 */   GIR_Done,
     /* 374040 */ // Label 7478: @374040
     /* 374040 */ GIM_Reject,
     /* 374041 */ // Label 7470: @374041
     /* 374041 */ GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(374078), // Rule ID 5084 //
     /* 374046 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374049 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 374052 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 374055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374059 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374063 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374067 */   // (fmaxnum_ieee:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXNMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 374067 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f32),
     /* 374072 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374076 */   GIR_RootConstrainSelectedInstOperands,
     /* 374077 */   // GIR_Coverage, 5084,
     /* 374077 */   GIR_Done,
     /* 374078 */ // Label 7479: @374078
     /* 374078 */ GIM_Reject,
     /* 374079 */ // Label 7471: @374079
     /* 374079 */ GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(374116), // Rule ID 5078 //
     /* 374084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 374090 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 374093 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374097 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374101 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374105 */   // (fmaxnum_ieee:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXNMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 374105 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv2f64),
     /* 374110 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374114 */   GIR_RootConstrainSelectedInstOperands,
     /* 374115 */   // GIR_Coverage, 5078,
     /* 374115 */   GIR_Done,
     /* 374116 */ // Label 7480: @374116
     /* 374116 */ GIM_Reject,
     /* 374117 */ // Label 7472: @374117
     /* 374117 */ GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(374154), // Rule ID 5090 //
     /* 374122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 374125 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 374128 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 374131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374135 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374139 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374143 */   // (fmaxnum_ieee:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXNMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 374143 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f16),
     /* 374148 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374152 */   GIR_RootConstrainSelectedInstOperands,
     /* 374153 */   // GIR_Coverage, 5090,
     /* 374153 */   GIR_Done,
     /* 374154 */ // Label 7481: @374154
     /* 374154 */ GIM_Reject,
     /* 374155 */ // Label 7473: @374155
     /* 374155 */ GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(374192), // Rule ID 5081 //
     /* 374160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 374166 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 374169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374173 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374177 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374181 */   // (fmaxnum_ieee:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXNMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 374181 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv4f32),
     /* 374186 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374190 */   GIR_RootConstrainSelectedInstOperands,
     /* 374191 */   // GIR_Coverage, 5081,
     /* 374191 */   GIR_Done,
     /* 374192 */ // Label 7482: @374192
     /* 374192 */ GIM_Reject,
     /* 374193 */ // Label 7474: @374193
     /* 374193 */ GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(374230), // Rule ID 5087 //
     /* 374198 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 374201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 374204 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 374207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374211 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374215 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374219 */   // (fmaxnum_ieee:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXNMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 374219 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMv8f16),
     /* 374224 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374228 */   GIR_RootConstrainSelectedInstOperands,
     /* 374229 */   // GIR_Coverage, 5087,
     /* 374229 */   GIR_Done,
     /* 374230 */ // Label 7483: @374230
     /* 374230 */ GIM_Reject,
     /* 374231 */ // Label 7475: @374231
     /* 374231 */ GIM_Reject,
     /* 374232 */ // Label 88: @374232
     /* 374232 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7492*/ GIMT_Encode4(374934),
     /* 374243 */ /*GILLT_s16*//*Label 7484*/ GIMT_Encode4(374283),
     /* 374247 */ /*GILLT_s32*//*Label 7485*/ GIMT_Encode4(374321),
     /* 374251 */ /*GILLT_s64*//*Label 7486*/ GIMT_Encode4(374359), GIMT_Encode4(0),
     /* 374259 */ /*GILLT_v2s32*//*Label 7487*/ GIMT_Encode4(374419),
     /* 374263 */ /*GILLT_v2s64*//*Label 7488*/ GIMT_Encode4(374522),
     /* 374267 */ /*GILLT_v4s16*//*Label 7489*/ GIMT_Encode4(374625),
     /* 374271 */ /*GILLT_v4s32*//*Label 7490*/ GIMT_Encode4(374728), GIMT_Encode4(0),
     /* 374279 */ /*GILLT_v8s16*//*Label 7491*/ GIMT_Encode4(374831),
     /* 374283 */ // Label 7484: @374283
     /* 374283 */ GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(374320), // Rule ID 656 //
     /* 374288 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 374291 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 374294 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 374297 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374301 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374305 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 374309 */   // (fminimum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMINHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 374309 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINHrr),
     /* 374314 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374318 */   GIR_RootConstrainSelectedInstOperands,
     /* 374319 */   // GIR_Coverage, 656,
     /* 374319 */   GIR_Done,
     /* 374320 */ // Label 7493: @374320
     /* 374320 */ GIM_Reject,
     /* 374321 */ // Label 7485: @374321
     /* 374321 */ GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(374358), // Rule ID 658 //
     /* 374326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 374329 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 374332 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 374335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 374339 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 374343 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 374347 */   // (fminimum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMINSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 374347 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINSrr),
     /* 374352 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374356 */   GIR_RootConstrainSelectedInstOperands,
     /* 374357 */   // GIR_Coverage, 658,
     /* 374357 */   GIR_Done,
     /* 374358 */ // Label 7494: @374358
     /* 374358 */ GIM_Reject,
     /* 374359 */ // Label 7486: @374359
     /* 374359 */ GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(374418),
     /* 374364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 374367 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 374370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374378 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374382 */   GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(374401), // Rule ID 660 //
     /* 374387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 374390 */     // (fminimum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMINDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 374390 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
     /* 374395 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374399 */     GIR_RootConstrainSelectedInstOperands,
     /* 374400 */     // GIR_Coverage, 660,
     /* 374400 */     GIR_Done,
     /* 374401 */   // Label 7496: @374401
     /* 374401 */   GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(374417), // Rule ID 4889 //
     /* 374406 */     // (fminimum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMINDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 374406 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINDrr),
     /* 374411 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374415 */     GIR_RootConstrainSelectedInstOperands,
     /* 374416 */     // GIR_Coverage, 4889,
     /* 374416 */     GIR_Done,
     /* 374417 */   // Label 7497: @374417
     /* 374417 */   GIM_Reject,
     /* 374418 */ // Label 7495: @374418
     /* 374418 */ GIM_Reject,
     /* 374419 */ // Label 7487: @374419
     /* 374419 */ GIM_Try, /*On fail goto*//*Label 7498*/ GIMT_Encode4(374521),
     /* 374424 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 374427 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 374430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374434 */   GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(374493), // Rule ID 2397 //
     /* 374439 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 374442 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374446 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374450 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 374454 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374459 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374463 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374467 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 374471 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374476 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374478 */     // (fminimum:{ *:[v2f32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FAMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 374478 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f32),
     /* 374481 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 374483 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 374487 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 374491 */     GIR_RootConstrainSelectedInstOperands,
     /* 374492 */     // GIR_Coverage, 2397,
     /* 374492 */     GIR_EraseRootFromParent_Done,
     /* 374493 */   // Label 7499: @374493
     /* 374493 */   GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(374520), // Rule ID 1318 //
     /* 374498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374501 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374509 */     // (fminimum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMINv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 374509 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f32),
     /* 374514 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374518 */     GIR_RootConstrainSelectedInstOperands,
     /* 374519 */     // GIR_Coverage, 1318,
     /* 374519 */     GIR_Done,
     /* 374520 */   // Label 7500: @374520
     /* 374520 */   GIM_Reject,
     /* 374521 */ // Label 7498: @374521
     /* 374521 */ GIM_Reject,
     /* 374522 */ // Label 7488: @374522
     /* 374522 */ GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(374624),
     /* 374527 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 374530 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 374533 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374537 */   GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(374596), // Rule ID 2403 //
     /* 374542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 374545 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374549 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374553 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 374557 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374570 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 374574 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374579 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374581 */     // (fminimum:{ *:[v2f64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FAMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 374581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv2f64),
     /* 374584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 374586 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 374590 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 374594 */     GIR_RootConstrainSelectedInstOperands,
     /* 374595 */     // GIR_Coverage, 2403,
     /* 374595 */     GIR_EraseRootFromParent_Done,
     /* 374596 */   // Label 7502: @374596
     /* 374596 */   GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(374623), // Rule ID 1322 //
     /* 374601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374604 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374608 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374612 */     // (fminimum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMINv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 374612 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv2f64),
     /* 374617 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374621 */     GIR_RootConstrainSelectedInstOperands,
     /* 374622 */     // GIR_Coverage, 1322,
     /* 374622 */     GIR_Done,
     /* 374623 */   // Label 7503: @374623
     /* 374623 */   GIM_Reject,
     /* 374624 */ // Label 7501: @374624
     /* 374624 */ GIM_Reject,
     /* 374625 */ // Label 7489: @374625
     /* 374625 */ GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(374727),
     /* 374630 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 374633 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 374636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374640 */   GIM_Try, /*On fail goto*//*Label 7505*/ GIMT_Encode4(374699), // Rule ID 2391 //
     /* 374645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 374648 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374652 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374656 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 374660 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374665 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374669 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374673 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 374677 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374682 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374684 */     // (fminimum:{ *:[v4f16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FAMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 374684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f16),
     /* 374687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 374689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 374693 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 374697 */     GIR_RootConstrainSelectedInstOperands,
     /* 374698 */     // GIR_Coverage, 2391,
     /* 374698 */     GIR_EraseRootFromParent_Done,
     /* 374699 */   // Label 7505: @374699
     /* 374699 */   GIM_Try, /*On fail goto*//*Label 7506*/ GIMT_Encode4(374726), // Rule ID 1314 //
     /* 374704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 374707 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374711 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 374715 */     // (fminimum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMINv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 374715 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f16),
     /* 374720 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374724 */     GIR_RootConstrainSelectedInstOperands,
     /* 374725 */     // GIR_Coverage, 1314,
     /* 374725 */     GIR_Done,
     /* 374726 */   // Label 7506: @374726
     /* 374726 */   GIM_Reject,
     /* 374727 */ // Label 7504: @374727
     /* 374727 */ GIM_Reject,
     /* 374728 */ // Label 7490: @374728
     /* 374728 */ GIM_Try, /*On fail goto*//*Label 7507*/ GIMT_Encode4(374830),
     /* 374733 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 374736 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 374739 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374743 */   GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(374802), // Rule ID 2400 //
     /* 374748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 374751 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374755 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374759 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 374763 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374768 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374772 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374776 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 374780 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374785 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374787 */     // (fminimum:{ *:[v4f32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FAMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 374787 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv4f32),
     /* 374790 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 374792 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 374796 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 374800 */     GIR_RootConstrainSelectedInstOperands,
     /* 374801 */     // GIR_Coverage, 2400,
     /* 374801 */     GIR_EraseRootFromParent_Done,
     /* 374802 */   // Label 7508: @374802
     /* 374802 */   GIM_Try, /*On fail goto*//*Label 7509*/ GIMT_Encode4(374829), // Rule ID 1320 //
     /* 374807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 374810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374818 */     // (fminimum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMINv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 374818 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv4f32),
     /* 374823 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374827 */     GIR_RootConstrainSelectedInstOperands,
     /* 374828 */     // GIR_Coverage, 1320,
     /* 374828 */     GIR_Done,
     /* 374829 */   // Label 7509: @374829
     /* 374829 */   GIM_Reject,
     /* 374830 */ // Label 7507: @374830
     /* 374830 */ GIM_Reject,
     /* 374831 */ // Label 7491: @374831
     /* 374831 */ GIM_Try, /*On fail goto*//*Label 7510*/ GIMT_Encode4(374933),
     /* 374836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 374839 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 374842 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374846 */   GIM_Try, /*On fail goto*//*Label 7511*/ GIMT_Encode4(374905), // Rule ID 2394 //
     /* 374851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 374854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 374858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 374866 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374871 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 374875 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 374879 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 374883 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374888 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 374890 */     // (fminimum:{ *:[v8f16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FAMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 374890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMINv8f16),
     /* 374893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 374895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 374899 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 374903 */     GIR_RootConstrainSelectedInstOperands,
     /* 374904 */     // GIR_Coverage, 2394,
     /* 374904 */     GIR_EraseRootFromParent_Done,
     /* 374905 */   // Label 7511: @374905
     /* 374905 */   GIM_Try, /*On fail goto*//*Label 7512*/ GIMT_Encode4(374932), // Rule ID 1316 //
     /* 374910 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 374913 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374917 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 374921 */     // (fminimum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMINv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 374921 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINv8f16),
     /* 374926 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 374930 */     GIR_RootConstrainSelectedInstOperands,
     /* 374931 */     // GIR_Coverage, 1316,
     /* 374931 */     GIR_Done,
     /* 374932 */   // Label 7512: @374932
     /* 374932 */   GIM_Reject,
     /* 374933 */ // Label 7510: @374933
     /* 374933 */ GIM_Reject,
     /* 374934 */ // Label 7492: @374934
     /* 374934 */ GIM_Reject,
     /* 374935 */ // Label 89: @374935
     /* 374935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 7521*/ GIMT_Encode4(375637),
     /* 374946 */ /*GILLT_s16*//*Label 7513*/ GIMT_Encode4(374986),
     /* 374950 */ /*GILLT_s32*//*Label 7514*/ GIMT_Encode4(375024),
     /* 374954 */ /*GILLT_s64*//*Label 7515*/ GIMT_Encode4(375062), GIMT_Encode4(0),
     /* 374962 */ /*GILLT_v2s32*//*Label 7516*/ GIMT_Encode4(375122),
     /* 374966 */ /*GILLT_v2s64*//*Label 7517*/ GIMT_Encode4(375225),
     /* 374970 */ /*GILLT_v4s16*//*Label 7518*/ GIMT_Encode4(375328),
     /* 374974 */ /*GILLT_v4s32*//*Label 7519*/ GIMT_Encode4(375431), GIMT_Encode4(0),
     /* 374982 */ /*GILLT_v8s16*//*Label 7520*/ GIMT_Encode4(375534),
     /* 374986 */ // Label 7513: @374986
     /* 374986 */ GIM_Try, /*On fail goto*//*Label 7522*/ GIMT_Encode4(375023), // Rule ID 644 //
     /* 374991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 374994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 374997 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 375000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375004 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375008 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 375012 */   // (fmaximum:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMAXHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 375012 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXHrr),
     /* 375017 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375021 */   GIR_RootConstrainSelectedInstOperands,
     /* 375022 */   // GIR_Coverage, 644,
     /* 375022 */   GIR_Done,
     /* 375023 */ // Label 7522: @375023
     /* 375023 */ GIM_Reject,
     /* 375024 */ // Label 7514: @375024
     /* 375024 */ GIM_Try, /*On fail goto*//*Label 7523*/ GIMT_Encode4(375061), // Rule ID 646 //
     /* 375029 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 375032 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 375035 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 375038 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 375042 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 375046 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 375050 */   // (fmaximum:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMAXSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 375050 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXSrr),
     /* 375055 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375059 */   GIR_RootConstrainSelectedInstOperands,
     /* 375060 */   // GIR_Coverage, 646,
     /* 375060 */   GIR_Done,
     /* 375061 */ // Label 7523: @375061
     /* 375061 */ GIM_Reject,
     /* 375062 */ // Label 7515: @375062
     /* 375062 */ GIM_Try, /*On fail goto*//*Label 7524*/ GIMT_Encode4(375121),
     /* 375067 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 375070 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 375073 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375077 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375081 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375085 */   GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(375104), // Rule ID 648 //
     /* 375090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 375093 */     // (fmaximum:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMAXDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 375093 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
     /* 375098 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375102 */     GIR_RootConstrainSelectedInstOperands,
     /* 375103 */     // GIR_Coverage, 648,
     /* 375103 */     GIR_Done,
     /* 375104 */   // Label 7525: @375104
     /* 375104 */   GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(375120), // Rule ID 4888 //
     /* 375109 */     // (fmaximum:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FMAXDrr:{ *:[v1f64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 375109 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXDrr),
     /* 375114 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375118 */     GIR_RootConstrainSelectedInstOperands,
     /* 375119 */     // GIR_Coverage, 4888,
     /* 375119 */     GIR_Done,
     /* 375120 */   // Label 7526: @375120
     /* 375120 */   GIM_Reject,
     /* 375121 */ // Label 7524: @375121
     /* 375121 */ GIM_Reject,
     /* 375122 */ // Label 7516: @375122
     /* 375122 */ GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(375224),
     /* 375127 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 375130 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 375133 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375137 */   GIM_Try, /*On fail goto*//*Label 7528*/ GIMT_Encode4(375196), // Rule ID 2382 //
     /* 375142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 375145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375153 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 375157 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375162 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375166 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375170 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 375174 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375179 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375181 */     // (fmaximum:{ *:[v2f32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FAMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 375181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f32),
     /* 375184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375186 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375190 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375194 */     GIR_RootConstrainSelectedInstOperands,
     /* 375195 */     // GIR_Coverage, 2382,
     /* 375195 */     GIR_EraseRootFromParent_Done,
     /* 375196 */   // Label 7528: @375196
     /* 375196 */   GIM_Try, /*On fail goto*//*Label 7529*/ GIMT_Encode4(375223), // Rule ID 1288 //
     /* 375201 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 375204 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375212 */     // (fmaximum:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMAXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 375212 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f32),
     /* 375217 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375221 */     GIR_RootConstrainSelectedInstOperands,
     /* 375222 */     // GIR_Coverage, 1288,
     /* 375222 */     GIR_Done,
     /* 375223 */   // Label 7529: @375223
     /* 375223 */   GIM_Reject,
     /* 375224 */ // Label 7527: @375224
     /* 375224 */ GIM_Reject,
     /* 375225 */ // Label 7517: @375225
     /* 375225 */ GIM_Try, /*On fail goto*//*Label 7530*/ GIMT_Encode4(375327),
     /* 375230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 375233 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 375236 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375240 */   GIM_Try, /*On fail goto*//*Label 7531*/ GIMT_Encode4(375299), // Rule ID 2388 //
     /* 375245 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 375248 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375252 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375256 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 375260 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375265 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375269 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375273 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 375277 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375282 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375284 */     // (fmaximum:{ *:[v2f64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FAMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 375284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv2f64),
     /* 375287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375289 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375293 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375297 */     GIR_RootConstrainSelectedInstOperands,
     /* 375298 */     // GIR_Coverage, 2388,
     /* 375298 */     GIR_EraseRootFromParent_Done,
     /* 375299 */   // Label 7531: @375299
     /* 375299 */   GIM_Try, /*On fail goto*//*Label 7532*/ GIMT_Encode4(375326), // Rule ID 1292 //
     /* 375304 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 375307 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375311 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375315 */     // (fmaximum:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMAXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 375315 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv2f64),
     /* 375320 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375324 */     GIR_RootConstrainSelectedInstOperands,
     /* 375325 */     // GIR_Coverage, 1292,
     /* 375325 */     GIR_Done,
     /* 375326 */   // Label 7532: @375326
     /* 375326 */   GIM_Reject,
     /* 375327 */ // Label 7530: @375327
     /* 375327 */ GIM_Reject,
     /* 375328 */ // Label 7518: @375328
     /* 375328 */ GIM_Try, /*On fail goto*//*Label 7533*/ GIMT_Encode4(375430),
     /* 375333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 375336 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 375339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375343 */   GIM_Try, /*On fail goto*//*Label 7534*/ GIMT_Encode4(375402), // Rule ID 2376 //
     /* 375348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 375351 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375355 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375359 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 375363 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375368 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375372 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375376 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 375380 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375385 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375387 */     // (fmaximum:{ *:[v4f16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FAMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 375387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f16),
     /* 375390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375392 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375400 */     GIR_RootConstrainSelectedInstOperands,
     /* 375401 */     // GIR_Coverage, 2376,
     /* 375401 */     GIR_EraseRootFromParent_Done,
     /* 375402 */   // Label 7534: @375402
     /* 375402 */   GIM_Try, /*On fail goto*//*Label 7535*/ GIMT_Encode4(375429), // Rule ID 1284 //
     /* 375407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 375410 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 375418 */     // (fmaximum:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMAXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 375418 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f16),
     /* 375423 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375427 */     GIR_RootConstrainSelectedInstOperands,
     /* 375428 */     // GIR_Coverage, 1284,
     /* 375428 */     GIR_Done,
     /* 375429 */   // Label 7535: @375429
     /* 375429 */   GIM_Reject,
     /* 375430 */ // Label 7533: @375430
     /* 375430 */ GIM_Reject,
     /* 375431 */ // Label 7519: @375431
     /* 375431 */ GIM_Try, /*On fail goto*//*Label 7536*/ GIMT_Encode4(375533),
     /* 375436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 375439 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 375442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375446 */   GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(375505), // Rule ID 2385 //
     /* 375451 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 375454 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375458 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375462 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 375466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375471 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375475 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375479 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 375483 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375488 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375490 */     // (fmaximum:{ *:[v4f32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FAMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 375490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv4f32),
     /* 375493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375503 */     GIR_RootConstrainSelectedInstOperands,
     /* 375504 */     // GIR_Coverage, 2385,
     /* 375504 */     GIR_EraseRootFromParent_Done,
     /* 375505 */   // Label 7537: @375505
     /* 375505 */   GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(375532), // Rule ID 1290 //
     /* 375510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 375513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375517 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375521 */     // (fmaximum:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMAXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 375521 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv4f32),
     /* 375526 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375530 */     GIR_RootConstrainSelectedInstOperands,
     /* 375531 */     // GIR_Coverage, 1290,
     /* 375531 */     GIR_Done,
     /* 375532 */   // Label 7538: @375532
     /* 375532 */   GIM_Reject,
     /* 375533 */ // Label 7536: @375533
     /* 375533 */ GIM_Reject,
     /* 375534 */ // Label 7520: @375534
     /* 375534 */ GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(375636),
     /* 375539 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 375542 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 375545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375549 */   GIM_Try, /*On fail goto*//*Label 7540*/ GIMT_Encode4(375608), // Rule ID 2379 //
     /* 375554 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFAMINMAX_HasNEON),
     /* 375557 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 375561 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375565 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 375569 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375574 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 375578 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 375582 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 375586 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375591 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375593 */     // (fmaximum:{ *:[v8f16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FAMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 375593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FAMAXv8f16),
     /* 375596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375598 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375606 */     GIR_RootConstrainSelectedInstOperands,
     /* 375607 */     // GIR_Coverage, 2379,
     /* 375607 */     GIR_EraseRootFromParent_Done,
     /* 375608 */   // Label 7540: @375608
     /* 375608 */   GIM_Try, /*On fail goto*//*Label 7541*/ GIMT_Encode4(375635), // Rule ID 1286 //
     /* 375613 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 375616 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 375624 */     // (fmaximum:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMAXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 375624 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXv8f16),
     /* 375629 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 375633 */     GIR_RootConstrainSelectedInstOperands,
     /* 375634 */     // GIR_Coverage, 1286,
     /* 375634 */     GIR_Done,
     /* 375635 */   // Label 7541: @375635
     /* 375635 */   GIM_Reject,
     /* 375636 */ // Label 7539: @375636
     /* 375636 */ GIM_Reject,
     /* 375637 */ // Label 7521: @375637
     /* 375637 */ GIM_Reject,
     /* 375638 */ // Label 90: @375638
     /* 375638 */ GIM_Try, /*On fail goto*//*Label 7542*/ GIMT_Encode4(376137),
     /* 375643 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 375646 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
     /* 375650 */   GIM_Try, /*On fail goto*//*Label 7543*/ GIMT_Encode4(375741), // Rule ID 7642 //
     /* 375655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 375658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375662 */     // MIs[0] Rn
     /* 375662 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 375666 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 375674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 375678 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 375682 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 375686 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /* 375690 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 375694 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 375698 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 375702 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 375706 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375711 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 375715 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 375719 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 375723 */     // MIs[3] Operand 1
     /* 375723 */     // No operand predicates
     /* 375723 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 375725 */     // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, (shl:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)))  =>  (SUBPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)
     /* 375725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBPT_shift),
     /* 375728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375730 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 375732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 375736 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // imm
     /* 375739 */     GIR_RootConstrainSelectedInstOperands,
     /* 375740 */     // GIR_Coverage, 7642,
     /* 375740 */     GIR_EraseRootFromParent_Done,
     /* 375741 */   // Label 7543: @375741
     /* 375741 */   GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(375905),
     /* 375746 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375750 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 375754 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375758 */     GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(375831), // Rule ID 16046 //
     /* 375763 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 375766 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 375770 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 375774 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 375778 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 375782 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 375786 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 375790 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 375794 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 375798 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 0,
     /* 375802 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375807 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375812 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375814 */       // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm), GPR64:{ *:[i64] }:$Rn))  =>  (MSUBPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 375814 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBPT),
     /* 375817 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375819 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 375823 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 375827 */       GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 375829 */       GIR_RootConstrainSelectedInstOperands,
     /* 375830 */       // GIR_Coverage, 16046,
     /* 375830 */       GIR_EraseRootFromParent_Done,
     /* 375831 */     // Label 7545: @375831
     /* 375831 */     GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(375904), // Rule ID 7644 //
     /* 375836 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 375839 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 375843 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 375847 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 375851 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 375855 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375860 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 375864 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 375868 */       GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 375872 */       GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 375876 */       GIM_CheckConstantInt8, /*MI*/2, /*Op*/1, 0,
     /* 375880 */       GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 375885 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 375887 */       // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64:{ *:[i64] }:$Rm)))  =>  (MSUBPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 375887 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MSUBPT),
     /* 375890 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375892 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 375896 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Rm
     /* 375900 */       GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 375902 */       GIR_RootConstrainSelectedInstOperands,
     /* 375903 */       // GIR_Coverage, 7644,
     /* 375903 */       GIR_EraseRootFromParent_Done,
     /* 375904 */     // Label 7546: @375904
     /* 375904 */     GIM_Reject,
     /* 375905 */   // Label 7544: @375905
     /* 375905 */   GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(376033),
     /* 375910 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375914 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 375918 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375922 */     GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(375973), // Rule ID 7641 //
     /* 375927 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 375930 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 375934 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 375938 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 375942 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 375946 */       GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
     /* 375950 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 375955 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 375957 */       // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (sub:{ *:[i64] } 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rm))  =>  (SUBPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, 0:{ *:[i64] })
     /* 375957 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUBPT_shift),
     /* 375960 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 375962 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 375964 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 375968 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 375971 */       GIR_RootConstrainSelectedInstOperands,
     /* 375972 */       // GIR_Coverage, 7641,
     /* 375972 */       GIR_EraseRootFromParent_Done,
     /* 375973 */     // Label 7548: @375973
     /* 375973 */     GIM_Try, /*On fail goto*//*Label 7549*/ GIMT_Encode4(376032), // Rule ID 7640 //
     /* 375978 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 375981 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 375985 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 375989 */       GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 375993 */       GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 375997 */       GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 376002 */       GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 376006 */       GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376010 */       GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
     /* 376014 */       // MIs[2] Operand 1
     /* 376014 */       // No operand predicates
     /* 376014 */       GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 376016 */       // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (shl:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm))  =>  (ADDPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_imm0_7>>:$imm)
     /* 376016 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPT_shift),
     /* 376019 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376021 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376023 */       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 376027 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 376030 */       GIR_RootConstrainSelectedInstOperands,
     /* 376031 */       // GIR_Coverage, 7640,
     /* 376031 */       GIR_EraseRootFromParent_Done,
     /* 376032 */     // Label 7549: @376032
     /* 376032 */     GIM_Reject,
     /* 376033 */   // Label 7547: @376033
     /* 376033 */   GIM_Try, /*On fail goto*//*Label 7550*/ GIMT_Encode4(376098), // Rule ID 7643 //
     /* 376038 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 376041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376045 */     // MIs[0] Ra
     /* 376045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 376049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 376061 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 376065 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 376069 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376074 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376079 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 376081 */     // (ptradd:{ *:[i64] } GPR64:{ *:[i64] }:$Ra, (mul:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm))  =>  (MADDPT:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, GPR64:{ *:[i64] }:$Ra)
     /* 376081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::MADDPT),
     /* 376084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 376090 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
     /* 376094 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ra
     /* 376096 */     GIR_RootConstrainSelectedInstOperands,
     /* 376097 */     // GIR_Coverage, 7643,
     /* 376097 */     GIR_EraseRootFromParent_Done,
     /* 376098 */   // Label 7550: @376098
     /* 376098 */   GIM_Try, /*On fail goto*//*Label 7551*/ GIMT_Encode4(376136), // Rule ID 7639 //
     /* 376103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCPA),
     /* 376106 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 376110 */     // MIs[0] Rn
     /* 376110 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 376114 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 376118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 376122 */     // (ptradd:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm)  =>  (ADDPT_shift:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64sp:{ *:[i64] }:$Rm, 0:{ *:[i64] })
     /* 376122 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ADDPT_shift),
     /* 376125 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376127 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376129 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 376131 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 376134 */     GIR_RootConstrainSelectedInstOperands,
     /* 376135 */     // GIR_Coverage, 7639,
     /* 376135 */     GIR_EraseRootFromParent_Done,
     /* 376136 */   // Label 7551: @376136
     /* 376136 */   GIM_Reject,
     /* 376137 */ // Label 7542: @376137
     /* 376137 */ GIM_Reject,
     /* 376138 */ // Label 91: @376138
     /* 376138 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7560*/ GIMT_Encode4(376541),
     /* 376149 */ /*GILLT_s32*//*Label 7552*/ GIMT_Encode4(376189),
     /* 376153 */ /*GILLT_s64*//*Label 7553*/ GIMT_Encode4(376263), GIMT_Encode4(0),
     /* 376161 */ /*GILLT_v2s32*//*Label 7554*/ GIMT_Encode4(376337), GIMT_Encode4(0),
     /* 376169 */ /*GILLT_v4s16*//*Label 7555*/ GIMT_Encode4(376371),
     /* 376173 */ /*GILLT_v4s32*//*Label 7556*/ GIMT_Encode4(376405),
     /* 376177 */ /*GILLT_v8s8*//*Label 7557*/ GIMT_Encode4(376439),
     /* 376181 */ /*GILLT_v8s16*//*Label 7558*/ GIMT_Encode4(376473),
     /* 376185 */ /*GILLT_v16s8*//*Label 7559*/ GIMT_Encode4(376507),
     /* 376189 */ // Label 7552: @376189
     /* 376189 */ GIM_Try, /*On fail goto*//*Label 7561*/ GIMT_Encode4(376262),
     /* 376194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 376197 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376204 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376208 */   GIM_Try, /*On fail goto*//*Label 7562*/ GIMT_Encode4(376242), // Rule ID 2359 //
     /* 376213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376216 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376220 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376224 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
     /* 376228 */     // MIs[1] Operand 1
     /* 376228 */     // No operand predicates
     /* 376228 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 376230 */     // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm)  =>  (SMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 376230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINWri),
     /* 376233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376235 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376237 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 376240 */     GIR_RootConstrainSelectedInstOperands,
     /* 376241 */     // GIR_Coverage, 2359,
     /* 376241 */     GIR_EraseRootFromParent_Done,
     /* 376242 */   // Label 7562: @376242
     /* 376242 */   GIM_Try, /*On fail goto*//*Label 7563*/ GIMT_Encode4(376261), // Rule ID 2358 //
     /* 376247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376254 */     // (smin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 376254 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINWrr),
     /* 376259 */     GIR_RootConstrainSelectedInstOperands,
     /* 376260 */     // GIR_Coverage, 2358,
     /* 376260 */     GIR_Done,
     /* 376261 */   // Label 7563: @376261
     /* 376261 */   GIM_Reject,
     /* 376262 */ // Label 7561: @376262
     /* 376262 */ GIM_Reject,
     /* 376263 */ // Label 7553: @376263
     /* 376263 */ GIM_Try, /*On fail goto*//*Label 7564*/ GIMT_Encode4(376336),
     /* 376268 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 376271 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 376274 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376278 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376282 */   GIM_Try, /*On fail goto*//*Label 7565*/ GIMT_Encode4(376316), // Rule ID 2361 //
     /* 376287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376290 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376294 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376298 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
     /* 376302 */     // MIs[1] Operand 1
     /* 376302 */     // No operand predicates
     /* 376302 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 376304 */     // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm)  =>  (SMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 376304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMINXri),
     /* 376307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376309 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376311 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 376314 */     GIR_RootConstrainSelectedInstOperands,
     /* 376315 */     // GIR_Coverage, 2361,
     /* 376315 */     GIR_EraseRootFromParent_Done,
     /* 376316 */   // Label 7565: @376316
     /* 376316 */   GIM_Try, /*On fail goto*//*Label 7566*/ GIMT_Encode4(376335), // Rule ID 2360 //
     /* 376321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376328 */     // (smin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 376328 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINXrr),
     /* 376333 */     GIR_RootConstrainSelectedInstOperands,
     /* 376334 */     // GIR_Coverage, 2360,
     /* 376334 */     GIR_Done,
     /* 376335 */   // Label 7566: @376335
     /* 376335 */   GIM_Reject,
     /* 376336 */ // Label 7564: @376336
     /* 376336 */ GIM_Reject,
     /* 376337 */ // Label 7554: @376337
     /* 376337 */ GIM_Try, /*On fail goto*//*Label 7567*/ GIMT_Encode4(376370), // Rule ID 1432 //
     /* 376342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376345 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 376348 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 376351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376355 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376359 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376363 */   // (smin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 376363 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv2i32),
     /* 376368 */   GIR_RootConstrainSelectedInstOperands,
     /* 376369 */   // GIR_Coverage, 1432,
     /* 376369 */   GIR_Done,
     /* 376370 */ // Label 7567: @376370
     /* 376370 */ GIM_Reject,
     /* 376371 */ // Label 7555: @376371
     /* 376371 */ GIM_Try, /*On fail goto*//*Label 7568*/ GIMT_Encode4(376404), // Rule ID 1430 //
     /* 376376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 376382 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 376385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376393 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376397 */   // (smin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 376397 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i16),
     /* 376402 */   GIR_RootConstrainSelectedInstOperands,
     /* 376403 */   // GIR_Coverage, 1430,
     /* 376403 */   GIR_Done,
     /* 376404 */ // Label 7568: @376404
     /* 376404 */ GIM_Reject,
     /* 376405 */ // Label 7556: @376405
     /* 376405 */ GIM_Try, /*On fail goto*//*Label 7569*/ GIMT_Encode4(376438), // Rule ID 1433 //
     /* 376410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376413 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 376416 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 376419 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376423 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376427 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376431 */   // (smin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 376431 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv4i32),
     /* 376436 */   GIR_RootConstrainSelectedInstOperands,
     /* 376437 */   // GIR_Coverage, 1433,
     /* 376437 */   GIR_Done,
     /* 376438 */ // Label 7569: @376438
     /* 376438 */ GIM_Reject,
     /* 376439 */ // Label 7557: @376439
     /* 376439 */ GIM_Try, /*On fail goto*//*Label 7570*/ GIMT_Encode4(376472), // Rule ID 1428 //
     /* 376444 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376447 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 376450 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 376453 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376457 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376461 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376465 */   // (smin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 376465 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i8),
     /* 376470 */   GIR_RootConstrainSelectedInstOperands,
     /* 376471 */   // GIR_Coverage, 1428,
     /* 376471 */   GIR_Done,
     /* 376472 */ // Label 7570: @376472
     /* 376472 */ GIM_Reject,
     /* 376473 */ // Label 7558: @376473
     /* 376473 */ GIM_Try, /*On fail goto*//*Label 7571*/ GIMT_Encode4(376506), // Rule ID 1431 //
     /* 376478 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376481 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376484 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 376487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376491 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376495 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376499 */   // (smin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 376499 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv8i16),
     /* 376504 */   GIR_RootConstrainSelectedInstOperands,
     /* 376505 */   // GIR_Coverage, 1431,
     /* 376505 */   GIR_Done,
     /* 376506 */ // Label 7571: @376506
     /* 376506 */ GIM_Reject,
     /* 376507 */ // Label 7559: @376507
     /* 376507 */ GIM_Try, /*On fail goto*//*Label 7572*/ GIMT_Encode4(376540), // Rule ID 1429 //
     /* 376512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376515 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 376518 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 376521 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376525 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376529 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376533 */   // (smin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 376533 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINv16i8),
     /* 376538 */   GIR_RootConstrainSelectedInstOperands,
     /* 376539 */   // GIR_Coverage, 1429,
     /* 376539 */   GIR_Done,
     /* 376540 */ // Label 7572: @376540
     /* 376540 */ GIM_Reject,
     /* 376541 */ // Label 7560: @376541
     /* 376541 */ GIM_Reject,
     /* 376542 */ // Label 92: @376542
     /* 376542 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7581*/ GIMT_Encode4(376945),
     /* 376553 */ /*GILLT_s32*//*Label 7573*/ GIMT_Encode4(376593),
     /* 376557 */ /*GILLT_s64*//*Label 7574*/ GIMT_Encode4(376667), GIMT_Encode4(0),
     /* 376565 */ /*GILLT_v2s32*//*Label 7575*/ GIMT_Encode4(376741), GIMT_Encode4(0),
     /* 376573 */ /*GILLT_v4s16*//*Label 7576*/ GIMT_Encode4(376775),
     /* 376577 */ /*GILLT_v4s32*//*Label 7577*/ GIMT_Encode4(376809),
     /* 376581 */ /*GILLT_v8s8*//*Label 7578*/ GIMT_Encode4(376843),
     /* 376585 */ /*GILLT_v8s16*//*Label 7579*/ GIMT_Encode4(376877),
     /* 376589 */ /*GILLT_v16s8*//*Label 7580*/ GIMT_Encode4(376911),
     /* 376593 */ // Label 7573: @376593
     /* 376593 */ GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(376666),
     /* 376598 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 376601 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 376604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376608 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376612 */   GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(376646), // Rule ID 2355 //
     /* 376617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376620 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376624 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376628 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_32b),
     /* 376632 */     // MIs[1] Operand 1
     /* 376632 */     // No operand predicates
     /* 376632 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 376634 */     // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_simm8_32b>>:$imm)  =>  (SMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 376634 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXWri),
     /* 376637 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376639 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376641 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 376644 */     GIR_RootConstrainSelectedInstOperands,
     /* 376645 */     // GIR_Coverage, 2355,
     /* 376645 */     GIR_EraseRootFromParent_Done,
     /* 376646 */   // Label 7583: @376646
     /* 376646 */   GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(376665), // Rule ID 2354 //
     /* 376651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376654 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 376658 */     // (smax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (SMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 376658 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXWrr),
     /* 376663 */     GIR_RootConstrainSelectedInstOperands,
     /* 376664 */     // GIR_Coverage, 2354,
     /* 376664 */     GIR_Done,
     /* 376665 */   // Label 7584: @376665
     /* 376665 */   GIM_Reject,
     /* 376666 */ // Label 7582: @376666
     /* 376666 */ GIM_Reject,
     /* 376667 */ // Label 7574: @376667
     /* 376667 */ GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(376740),
     /* 376672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 376675 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 376678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376682 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376686 */   GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(376720), // Rule ID 2357 //
     /* 376691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 376698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 376702 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8_64b),
     /* 376706 */     // MIs[1] Operand 1
     /* 376706 */     // No operand predicates
     /* 376706 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 376708 */     // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm8_64b>>:$imm)  =>  (SMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 376708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMAXXri),
     /* 376711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 376713 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 376715 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 376718 */     GIR_RootConstrainSelectedInstOperands,
     /* 376719 */     // GIR_Coverage, 2357,
     /* 376719 */     GIR_EraseRootFromParent_Done,
     /* 376720 */   // Label 7586: @376720
     /* 376720 */   GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(376739), // Rule ID 2356 //
     /* 376725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 376728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 376732 */     // (smax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (SMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 376732 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXXrr),
     /* 376737 */     GIR_RootConstrainSelectedInstOperands,
     /* 376738 */     // GIR_Coverage, 2356,
     /* 376738 */     GIR_Done,
     /* 376739 */   // Label 7587: @376739
     /* 376739 */   GIM_Reject,
     /* 376740 */ // Label 7585: @376740
     /* 376740 */ GIM_Reject,
     /* 376741 */ // Label 7575: @376741
     /* 376741 */ GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(376774), // Rule ID 1420 //
     /* 376746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376749 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 376752 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 376755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376759 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376763 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376767 */   // (smax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 376767 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv2i32),
     /* 376772 */   GIR_RootConstrainSelectedInstOperands,
     /* 376773 */   // GIR_Coverage, 1420,
     /* 376773 */   GIR_Done,
     /* 376774 */ // Label 7588: @376774
     /* 376774 */ GIM_Reject,
     /* 376775 */ // Label 7576: @376775
     /* 376775 */ GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(376808), // Rule ID 1418 //
     /* 376780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376783 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 376786 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 376789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376793 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376797 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376801 */   // (smax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 376801 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i16),
     /* 376806 */   GIR_RootConstrainSelectedInstOperands,
     /* 376807 */   // GIR_Coverage, 1418,
     /* 376807 */   GIR_Done,
     /* 376808 */ // Label 7589: @376808
     /* 376808 */ GIM_Reject,
     /* 376809 */ // Label 7577: @376809
     /* 376809 */ GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(376842), // Rule ID 1421 //
     /* 376814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376817 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 376820 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 376823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376827 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376831 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376835 */   // (smax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (SMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 376835 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv4i32),
     /* 376840 */   GIR_RootConstrainSelectedInstOperands,
     /* 376841 */   // GIR_Coverage, 1421,
     /* 376841 */   GIR_Done,
     /* 376842 */ // Label 7590: @376842
     /* 376842 */ GIM_Reject,
     /* 376843 */ // Label 7578: @376843
     /* 376843 */ GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(376876), // Rule ID 1416 //
     /* 376848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 376854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 376857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376865 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 376869 */   // (smax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 376869 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i8),
     /* 376874 */   GIR_RootConstrainSelectedInstOperands,
     /* 376875 */   // GIR_Coverage, 1416,
     /* 376875 */   GIR_Done,
     /* 376876 */ // Label 7591: @376876
     /* 376876 */ GIM_Reject,
     /* 376877 */ // Label 7579: @376877
     /* 376877 */ GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(376910), // Rule ID 1419 //
     /* 376882 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376885 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 376888 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 376891 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376895 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376899 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376903 */   // (smax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (SMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 376903 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv8i16),
     /* 376908 */   GIR_RootConstrainSelectedInstOperands,
     /* 376909 */   // GIR_Coverage, 1419,
     /* 376909 */   GIR_Done,
     /* 376910 */ // Label 7592: @376910
     /* 376910 */ GIM_Reject,
     /* 376911 */ // Label 7580: @376911
     /* 376911 */ GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(376944), // Rule ID 1417 //
     /* 376916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 376919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 376922 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 376925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376929 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376933 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 376937 */   // (smax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 376937 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXv16i8),
     /* 376942 */   GIR_RootConstrainSelectedInstOperands,
     /* 376943 */   // GIR_Coverage, 1417,
     /* 376943 */   GIR_Done,
     /* 376944 */ // Label 7593: @376944
     /* 376944 */ GIM_Reject,
     /* 376945 */ // Label 7581: @376945
     /* 376945 */ GIM_Reject,
     /* 376946 */ // Label 93: @376946
     /* 376946 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7602*/ GIMT_Encode4(377349),
     /* 376957 */ /*GILLT_s32*//*Label 7594*/ GIMT_Encode4(376997),
     /* 376961 */ /*GILLT_s64*//*Label 7595*/ GIMT_Encode4(377071), GIMT_Encode4(0),
     /* 376969 */ /*GILLT_v2s32*//*Label 7596*/ GIMT_Encode4(377145), GIMT_Encode4(0),
     /* 376977 */ /*GILLT_v4s16*//*Label 7597*/ GIMT_Encode4(377179),
     /* 376981 */ /*GILLT_v4s32*//*Label 7598*/ GIMT_Encode4(377213),
     /* 376985 */ /*GILLT_v8s8*//*Label 7599*/ GIMT_Encode4(377247),
     /* 376989 */ /*GILLT_v8s16*//*Label 7600*/ GIMT_Encode4(377281),
     /* 376993 */ /*GILLT_v16s8*//*Label 7601*/ GIMT_Encode4(377315),
     /* 376997 */ // Label 7594: @376997
     /* 376997 */ GIM_Try, /*On fail goto*//*Label 7603*/ GIMT_Encode4(377070),
     /* 377002 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 377005 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377008 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377012 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377016 */   GIM_Try, /*On fail goto*//*Label 7604*/ GIMT_Encode4(377050), // Rule ID 2367 //
     /* 377021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377032 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
     /* 377036 */     // MIs[1] Operand 1
     /* 377036 */     // No operand predicates
     /* 377036 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377038 */     // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm)  =>  (UMINWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 377038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINWri),
     /* 377041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 377043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377045 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 377048 */     GIR_RootConstrainSelectedInstOperands,
     /* 377049 */     // GIR_Coverage, 2367,
     /* 377049 */     GIR_EraseRootFromParent_Done,
     /* 377050 */   // Label 7604: @377050
     /* 377050 */   GIM_Try, /*On fail goto*//*Label 7605*/ GIMT_Encode4(377069), // Rule ID 2366 //
     /* 377055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377062 */     // (umin:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UMINWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 377062 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINWrr),
     /* 377067 */     GIR_RootConstrainSelectedInstOperands,
     /* 377068 */     // GIR_Coverage, 2366,
     /* 377068 */     GIR_Done,
     /* 377069 */   // Label 7605: @377069
     /* 377069 */   GIM_Reject,
     /* 377070 */ // Label 7603: @377070
     /* 377070 */ GIM_Reject,
     /* 377071 */ // Label 7595: @377071
     /* 377071 */ GIM_Try, /*On fail goto*//*Label 7606*/ GIMT_Encode4(377144),
     /* 377076 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 377079 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 377082 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377086 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377090 */   GIM_Try, /*On fail goto*//*Label 7607*/ GIMT_Encode4(377124), // Rule ID 2369 //
     /* 377095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377102 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377106 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
     /* 377110 */     // MIs[1] Operand 1
     /* 377110 */     // No operand predicates
     /* 377110 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377112 */     // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm)  =>  (UMINXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 377112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMINXri),
     /* 377115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 377117 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377119 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 377122 */     GIR_RootConstrainSelectedInstOperands,
     /* 377123 */     // GIR_Coverage, 2369,
     /* 377123 */     GIR_EraseRootFromParent_Done,
     /* 377124 */   // Label 7607: @377124
     /* 377124 */   GIM_Try, /*On fail goto*//*Label 7608*/ GIMT_Encode4(377143), // Rule ID 2368 //
     /* 377129 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377136 */     // (umin:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMINXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 377136 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINXrr),
     /* 377141 */     GIR_RootConstrainSelectedInstOperands,
     /* 377142 */     // GIR_Coverage, 2368,
     /* 377142 */     GIR_Done,
     /* 377143 */   // Label 7608: @377143
     /* 377143 */   GIM_Reject,
     /* 377144 */ // Label 7606: @377144
     /* 377144 */ GIM_Reject,
     /* 377145 */ // Label 7596: @377145
     /* 377145 */ GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(377178), // Rule ID 1543 //
     /* 377150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377153 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 377156 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 377159 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377163 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377167 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377171 */   // (umin:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMINv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 377171 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv2i32),
     /* 377176 */   GIR_RootConstrainSelectedInstOperands,
     /* 377177 */   // GIR_Coverage, 1543,
     /* 377177 */   GIR_Done,
     /* 377178 */ // Label 7609: @377178
     /* 377178 */ GIM_Reject,
     /* 377179 */ // Label 7597: @377179
     /* 377179 */ GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(377212), // Rule ID 1541 //
     /* 377184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 377190 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 377193 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377197 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377201 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377205 */   // (umin:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMINv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 377205 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i16),
     /* 377210 */   GIR_RootConstrainSelectedInstOperands,
     /* 377211 */   // GIR_Coverage, 1541,
     /* 377211 */   GIR_Done,
     /* 377212 */ // Label 7610: @377212
     /* 377212 */ GIM_Reject,
     /* 377213 */ // Label 7598: @377213
     /* 377213 */ GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(377246), // Rule ID 1544 //
     /* 377218 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377221 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 377224 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 377227 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377231 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377235 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377239 */   // (umin:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMINv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 377239 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv4i32),
     /* 377244 */   GIR_RootConstrainSelectedInstOperands,
     /* 377245 */   // GIR_Coverage, 1544,
     /* 377245 */   GIR_Done,
     /* 377246 */ // Label 7611: @377246
     /* 377246 */ GIM_Reject,
     /* 377247 */ // Label 7599: @377247
     /* 377247 */ GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(377280), // Rule ID 1539 //
     /* 377252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377255 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 377258 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 377261 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377265 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377269 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377273 */   // (umin:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMINv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 377273 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i8),
     /* 377278 */   GIR_RootConstrainSelectedInstOperands,
     /* 377279 */   // GIR_Coverage, 1539,
     /* 377279 */   GIR_Done,
     /* 377280 */ // Label 7612: @377280
     /* 377280 */ GIM_Reject,
     /* 377281 */ // Label 7600: @377281
     /* 377281 */ GIM_Try, /*On fail goto*//*Label 7613*/ GIMT_Encode4(377314), // Rule ID 1542 //
     /* 377286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377289 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 377292 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 377295 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377299 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377303 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377307 */   // (umin:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMINv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 377307 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv8i16),
     /* 377312 */   GIR_RootConstrainSelectedInstOperands,
     /* 377313 */   // GIR_Coverage, 1542,
     /* 377313 */   GIR_Done,
     /* 377314 */ // Label 7613: @377314
     /* 377314 */ GIM_Reject,
     /* 377315 */ // Label 7601: @377315
     /* 377315 */ GIM_Try, /*On fail goto*//*Label 7614*/ GIMT_Encode4(377348), // Rule ID 1540 //
     /* 377320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377323 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 377326 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 377329 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377333 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377337 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377341 */   // (umin:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMINv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 377341 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINv16i8),
     /* 377346 */   GIR_RootConstrainSelectedInstOperands,
     /* 377347 */   // GIR_Coverage, 1540,
     /* 377347 */   GIR_Done,
     /* 377348 */ // Label 7614: @377348
     /* 377348 */ GIM_Reject,
     /* 377349 */ // Label 7602: @377349
     /* 377349 */ GIM_Reject,
     /* 377350 */ // Label 94: @377350
     /* 377350 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7623*/ GIMT_Encode4(377753),
     /* 377361 */ /*GILLT_s32*//*Label 7615*/ GIMT_Encode4(377401),
     /* 377365 */ /*GILLT_s64*//*Label 7616*/ GIMT_Encode4(377475), GIMT_Encode4(0),
     /* 377373 */ /*GILLT_v2s32*//*Label 7617*/ GIMT_Encode4(377549), GIMT_Encode4(0),
     /* 377381 */ /*GILLT_v4s16*//*Label 7618*/ GIMT_Encode4(377583),
     /* 377385 */ /*GILLT_v4s32*//*Label 7619*/ GIMT_Encode4(377617),
     /* 377389 */ /*GILLT_v8s8*//*Label 7620*/ GIMT_Encode4(377651),
     /* 377393 */ /*GILLT_v8s16*//*Label 7621*/ GIMT_Encode4(377685),
     /* 377397 */ /*GILLT_v16s8*//*Label 7622*/ GIMT_Encode4(377719),
     /* 377401 */ // Label 7615: @377401
     /* 377401 */ GIM_Try, /*On fail goto*//*Label 7624*/ GIMT_Encode4(377474),
     /* 377406 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 377409 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 377412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377416 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377420 */   GIM_Try, /*On fail goto*//*Label 7625*/ GIMT_Encode4(377454), // Rule ID 2363 //
     /* 377425 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377428 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377432 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377436 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_32b),
     /* 377440 */     // MIs[1] Operand 1
     /* 377440 */     // No operand predicates
     /* 377440 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377442 */     // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_uimm8_32b>>:$imm)  =>  (UMAXWri:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
     /* 377442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXWri),
     /* 377445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 377447 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377449 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 377452 */     GIR_RootConstrainSelectedInstOperands,
     /* 377453 */     // GIR_Coverage, 2363,
     /* 377453 */     GIR_EraseRootFromParent_Done,
     /* 377454 */   // Label 7625: @377454
     /* 377454 */   GIM_Try, /*On fail goto*//*Label 7626*/ GIMT_Encode4(377473), // Rule ID 2362 //
     /* 377459 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377466 */     // (umax:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)  =>  (UMAXWrr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, GPR32:{ *:[i32] }:$Rm)
     /* 377466 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXWrr),
     /* 377471 */     GIR_RootConstrainSelectedInstOperands,
     /* 377472 */     // GIR_Coverage, 2362,
     /* 377472 */     GIR_Done,
     /* 377473 */   // Label 7626: @377473
     /* 377473 */   GIM_Reject,
     /* 377474 */ // Label 7624: @377474
     /* 377474 */ GIM_Reject,
     /* 377475 */ // Label 7616: @377475
     /* 377475 */ GIM_Try, /*On fail goto*//*Label 7627*/ GIMT_Encode4(377548),
     /* 377480 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 377483 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 377486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377490 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377494 */   GIM_Try, /*On fail goto*//*Label 7628*/ GIMT_Encode4(377528), // Rule ID 2365 //
     /* 377499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377502 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 377506 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 377510 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_uimm8_64b),
     /* 377514 */     // MIs[1] Operand 1
     /* 377514 */     // No operand predicates
     /* 377514 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 377516 */     // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_uimm8_64b>>:$imm)  =>  (UMAXXri:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$imm)
     /* 377516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMAXXri),
     /* 377519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 377521 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 377523 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 377526 */     GIR_RootConstrainSelectedInstOperands,
     /* 377527 */     // GIR_Coverage, 2365,
     /* 377527 */     GIR_EraseRootFromParent_Done,
     /* 377528 */   // Label 7628: @377528
     /* 377528 */   GIM_Try, /*On fail goto*//*Label 7629*/ GIMT_Encode4(377547), // Rule ID 2364 //
     /* 377533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377540 */     // (umax:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (UMAXXrr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)
     /* 377540 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXXrr),
     /* 377545 */     GIR_RootConstrainSelectedInstOperands,
     /* 377546 */     // GIR_Coverage, 2364,
     /* 377546 */     GIR_Done,
     /* 377547 */   // Label 7629: @377547
     /* 377547 */   GIM_Reject,
     /* 377548 */ // Label 7627: @377548
     /* 377548 */ GIM_Reject,
     /* 377549 */ // Label 7617: @377549
     /* 377549 */ GIM_Try, /*On fail goto*//*Label 7630*/ GIMT_Encode4(377582), // Rule ID 1531 //
     /* 377554 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377557 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 377560 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 377563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377567 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377571 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377575 */   // (umax:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMAXv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 377575 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv2i32),
     /* 377580 */   GIR_RootConstrainSelectedInstOperands,
     /* 377581 */   // GIR_Coverage, 1531,
     /* 377581 */   GIR_Done,
     /* 377582 */ // Label 7630: @377582
     /* 377582 */ GIM_Reject,
     /* 377583 */ // Label 7618: @377583
     /* 377583 */ GIM_Try, /*On fail goto*//*Label 7631*/ GIMT_Encode4(377616), // Rule ID 1529 //
     /* 377588 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377591 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 377594 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 377597 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377601 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377605 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377609 */   // (umax:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMAXv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 377609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i16),
     /* 377614 */   GIR_RootConstrainSelectedInstOperands,
     /* 377615 */   // GIR_Coverage, 1529,
     /* 377615 */   GIR_Done,
     /* 377616 */ // Label 7631: @377616
     /* 377616 */ GIM_Reject,
     /* 377617 */ // Label 7619: @377617
     /* 377617 */ GIM_Try, /*On fail goto*//*Label 7632*/ GIMT_Encode4(377650), // Rule ID 1532 //
     /* 377622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377625 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 377628 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 377631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377635 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377639 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377643 */   // (umax:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UMAXv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 377643 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv4i32),
     /* 377648 */   GIR_RootConstrainSelectedInstOperands,
     /* 377649 */   // GIR_Coverage, 1532,
     /* 377649 */   GIR_Done,
     /* 377650 */ // Label 7632: @377650
     /* 377650 */ GIM_Reject,
     /* 377651 */ // Label 7620: @377651
     /* 377651 */ GIM_Try, /*On fail goto*//*Label 7633*/ GIMT_Encode4(377684), // Rule ID 1527 //
     /* 377656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 377662 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 377665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377669 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377673 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377677 */   // (umax:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMAXv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 377677 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i8),
     /* 377682 */   GIR_RootConstrainSelectedInstOperands,
     /* 377683 */   // GIR_Coverage, 1527,
     /* 377683 */   GIR_Done,
     /* 377684 */ // Label 7633: @377684
     /* 377684 */ GIM_Reject,
     /* 377685 */ // Label 7621: @377685
     /* 377685 */ GIM_Try, /*On fail goto*//*Label 7634*/ GIMT_Encode4(377718), // Rule ID 1530 //
     /* 377690 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377693 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 377696 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 377699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377703 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377707 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377711 */   // (umax:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UMAXv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 377711 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv8i16),
     /* 377716 */   GIR_RootConstrainSelectedInstOperands,
     /* 377717 */   // GIR_Coverage, 1530,
     /* 377717 */   GIR_Done,
     /* 377718 */ // Label 7634: @377718
     /* 377718 */ GIM_Reject,
     /* 377719 */ // Label 7622: @377719
     /* 377719 */ GIM_Try, /*On fail goto*//*Label 7635*/ GIMT_Encode4(377752), // Rule ID 1528 //
     /* 377724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 377730 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 377733 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377737 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377741 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377745 */   // (umax:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UMAXv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 377745 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXv16i8),
     /* 377750 */   GIR_RootConstrainSelectedInstOperands,
     /* 377751 */   // GIR_Coverage, 1528,
     /* 377751 */   GIR_Done,
     /* 377752 */ // Label 7635: @377752
     /* 377752 */ GIM_Reject,
     /* 377753 */ // Label 7623: @377753
     /* 377753 */ GIM_Reject,
     /* 377754 */ // Label 95: @377754
     /* 377754 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 7645*/ GIMT_Encode4(378100),
     /* 377765 */ /*GILLT_s32*//*Label 7636*/ GIMT_Encode4(377805),
     /* 377769 */ /*GILLT_s64*//*Label 7637*/ GIMT_Encode4(377832), GIMT_Encode4(0),
     /* 377777 */ /*GILLT_v2s32*//*Label 7638*/ GIMT_Encode4(377911),
     /* 377781 */ /*GILLT_v2s64*//*Label 7639*/ GIMT_Encode4(377938),
     /* 377785 */ /*GILLT_v4s16*//*Label 7640*/ GIMT_Encode4(377965),
     /* 377789 */ /*GILLT_v4s32*//*Label 7641*/ GIMT_Encode4(377992),
     /* 377793 */ /*GILLT_v8s8*//*Label 7642*/ GIMT_Encode4(378019),
     /* 377797 */ /*GILLT_v8s16*//*Label 7643*/ GIMT_Encode4(378046),
     /* 377801 */ /*GILLT_v16s8*//*Label 7644*/ GIMT_Encode4(378073),
     /* 377805 */ // Label 7636: @377805
     /* 377805 */ GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(377831), // Rule ID 2348 //
     /* 377810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 377816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377820 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 377824 */   // (abs:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (ABSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 377824 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSWr),
     /* 377829 */   GIR_RootConstrainSelectedInstOperands,
     /* 377830 */   // GIR_Coverage, 2348,
     /* 377830 */   GIR_Done,
     /* 377831 */ // Label 7646: @377831
     /* 377831 */ GIM_Reject,
     /* 377832 */ // Label 7637: @377832
     /* 377832 */ GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(377910),
     /* 377837 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 377840 */   GIM_Try, /*On fail goto*//*Label 7648*/ GIMT_Encode4(377863), // Rule ID 1658 //
     /* 377845 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377848 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377852 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377856 */     // (abs:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)  =>  (ABSv1i64:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn)
     /* 377856 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
     /* 377861 */     GIR_RootConstrainSelectedInstOperands,
     /* 377862 */     // GIR_Coverage, 1658,
     /* 377862 */     GIR_Done,
     /* 377863 */   // Label 7648: @377863
     /* 377863 */   GIM_Try, /*On fail goto*//*Label 7649*/ GIMT_Encode4(377886), // Rule ID 2349 //
     /* 377868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 377871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 377879 */     // (abs:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (ABSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 377879 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSXr),
     /* 377884 */     GIR_RootConstrainSelectedInstOperands,
     /* 377885 */     // GIR_Coverage, 2349,
     /* 377885 */     GIR_Done,
     /* 377886 */   // Label 7649: @377886
     /* 377886 */   GIM_Try, /*On fail goto*//*Label 7650*/ GIMT_Encode4(377909), // Rule ID 2548 //
     /* 377891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCSSC),
     /* 377894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377898 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377902 */     // (abs:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)  =>  (ABSv1i64:{ *:[i64] } FPR64:{ *:[i64] }:$Rn)
     /* 377902 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv1i64),
     /* 377907 */     GIR_RootConstrainSelectedInstOperands,
     /* 377908 */     // GIR_Coverage, 2548,
     /* 377908 */     GIR_Done,
     /* 377909 */   // Label 7650: @377909
     /* 377909 */   GIM_Reject,
     /* 377910 */ // Label 7647: @377910
     /* 377910 */ GIM_Reject,
     /* 377911 */ // Label 7638: @377911
     /* 377911 */ GIM_Try, /*On fail goto*//*Label 7651*/ GIMT_Encode4(377937), // Rule ID 737 //
     /* 377916 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 377922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377926 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377930 */   // (abs:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (ABSv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 377930 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i32),
     /* 377935 */   GIR_RootConstrainSelectedInstOperands,
     /* 377936 */   // GIR_Coverage, 737,
     /* 377936 */   GIR_Done,
     /* 377937 */ // Label 7651: @377937
     /* 377937 */ GIM_Reject,
     /* 377938 */ // Label 7639: @377938
     /* 377938 */ GIM_Try, /*On fail goto*//*Label 7652*/ GIMT_Encode4(377964), // Rule ID 739 //
     /* 377943 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 377949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377953 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 377957 */   // (abs:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)  =>  (ABSv2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 377957 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv2i64),
     /* 377962 */   GIR_RootConstrainSelectedInstOperands,
     /* 377963 */   // GIR_Coverage, 739,
     /* 377963 */   GIR_Done,
     /* 377964 */ // Label 7652: @377964
     /* 377964 */ GIM_Reject,
     /* 377965 */ // Label 7640: @377965
     /* 377965 */ GIM_Try, /*On fail goto*//*Label 7653*/ GIMT_Encode4(377991), // Rule ID 735 //
     /* 377970 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 377973 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 377976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377980 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 377984 */   // (abs:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (ABSv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 377984 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i16),
     /* 377989 */   GIR_RootConstrainSelectedInstOperands,
     /* 377990 */   // GIR_Coverage, 735,
     /* 377990 */   GIR_Done,
     /* 377991 */ // Label 7653: @377991
     /* 377991 */ GIM_Reject,
     /* 377992 */ // Label 7641: @377992
     /* 377992 */ GIM_Try, /*On fail goto*//*Label 7654*/ GIMT_Encode4(378018), // Rule ID 738 //
     /* 377997 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 378000 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 378003 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378007 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378011 */   // (abs:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (ABSv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 378011 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv4i32),
     /* 378016 */   GIR_RootConstrainSelectedInstOperands,
     /* 378017 */   // GIR_Coverage, 738,
     /* 378017 */   GIR_Done,
     /* 378018 */ // Label 7654: @378018
     /* 378018 */ GIM_Reject,
     /* 378019 */ // Label 7642: @378019
     /* 378019 */ GIM_Try, /*On fail goto*//*Label 7655*/ GIMT_Encode4(378045), // Rule ID 733 //
     /* 378024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 378027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 378030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378034 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378038 */   // (abs:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (ABSv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 378038 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i8),
     /* 378043 */   GIR_RootConstrainSelectedInstOperands,
     /* 378044 */   // GIR_Coverage, 733,
     /* 378044 */   GIR_Done,
     /* 378045 */ // Label 7655: @378045
     /* 378045 */ GIM_Reject,
     /* 378046 */ // Label 7643: @378046
     /* 378046 */ GIM_Try, /*On fail goto*//*Label 7656*/ GIMT_Encode4(378072), // Rule ID 736 //
     /* 378051 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 378054 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 378057 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378061 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378065 */   // (abs:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (ABSv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 378065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv8i16),
     /* 378070 */   GIR_RootConstrainSelectedInstOperands,
     /* 378071 */   // GIR_Coverage, 736,
     /* 378071 */   GIR_Done,
     /* 378072 */ // Label 7656: @378072
     /* 378072 */ GIM_Reject,
     /* 378073 */ // Label 7644: @378073
     /* 378073 */ GIM_Try, /*On fail goto*//*Label 7657*/ GIMT_Encode4(378099), // Rule ID 734 //
     /* 378078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 378081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 378084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378088 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 378092 */   // (abs:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (ABSv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 378092 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ABSv16i8),
     /* 378097 */   GIR_RootConstrainSelectedInstOperands,
     /* 378098 */   // GIR_Coverage, 734,
     /* 378098 */   GIR_Done,
     /* 378099 */ // Label 7657: @378099
     /* 378099 */ GIM_Reject,
     /* 378100 */ // Label 7645: @378100
     /* 378100 */ GIM_Reject,
     /* 378101 */ // Label 96: @378101
     /* 378101 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 7660*/ GIMT_Encode4(378416),
     /* 378112 */ /*GILLT_s32*//*Label 7658*/ GIMT_Encode4(378120),
     /* 378116 */ /*GILLT_s64*//*Label 7659*/ GIMT_Encode4(378268),
     /* 378120 */ // Label 7658: @378120
     /* 378120 */ GIM_Try, /*On fail goto*//*Label 7661*/ GIMT_Encode4(378146), // Rule ID 4805 //
     /* 378125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 378128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 378131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 378135 */   // (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUWHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 378135 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWHr),
     /* 378140 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378144 */   GIR_RootConstrainSelectedInstOperands,
     /* 378145 */   // GIR_Coverage, 4805,
     /* 378145 */   GIR_Done,
     /* 378146 */ // Label 7661: @378146
     /* 378146 */ GIM_Try, /*On fail goto*//*Label 7662*/ GIMT_Encode4(378169), // Rule ID 4811 //
     /* 378151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 378154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 378158 */   // (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUWSr:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 378158 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWSr),
     /* 378163 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378167 */   GIR_RootConstrainSelectedInstOperands,
     /* 378168 */   // GIR_Coverage, 4811,
     /* 378168 */   GIR_Done,
     /* 378169 */ // Label 7662: @378169
     /* 378169 */ GIM_Try, /*On fail goto*//*Label 7663*/ GIMT_Encode4(378192), // Rule ID 4813 //
     /* 378174 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 378177 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 378181 */   // (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUWDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 378181 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUWDr),
     /* 378186 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378190 */   GIR_RootConstrainSelectedInstOperands,
     /* 378191 */   // GIR_Coverage, 4813,
     /* 378191 */   GIR_Done,
     /* 378192 */ // Label 7663: @378192
     /* 378192 */ GIM_Try, /*On fail goto*//*Label 7664*/ GIMT_Encode4(378218), // Rule ID 5772 //
     /* 378197 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378200 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 378203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 378207 */   // (lround:{ *:[i32] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASSHr:{ *:[i32] } f16:{ *:[f16] }:$Rn)
     /* 378207 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSHr),
     /* 378212 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378216 */   GIR_RootConstrainSelectedInstOperands,
     /* 378217 */   // GIR_Coverage, 5772,
     /* 378217 */   GIR_Done,
     /* 378218 */ // Label 7664: @378218
     /* 378218 */ GIM_Try, /*On fail goto*//*Label 7665*/ GIMT_Encode4(378244), // Rule ID 5773 //
     /* 378223 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 378229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 378233 */   // (lround:{ *:[i32] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASSDr:{ *:[i32] } f64:{ *:[f64] }:$Rn)
     /* 378233 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASSDr),
     /* 378238 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378242 */   GIR_RootConstrainSelectedInstOperands,
     /* 378243 */   // GIR_Coverage, 5773,
     /* 378243 */   GIR_Done,
     /* 378244 */ // Label 7665: @378244
     /* 378244 */ GIM_Try, /*On fail goto*//*Label 7666*/ GIMT_Encode4(378267), // Rule ID 5778 //
     /* 378249 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 378252 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 378256 */   // (lround:{ *:[i32] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASv1i32:{ *:[i32] } f32:{ *:[f32] }:$Rn)
     /* 378256 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i32),
     /* 378261 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378265 */   GIR_RootConstrainSelectedInstOperands,
     /* 378266 */   // GIR_Coverage, 5778,
     /* 378266 */   GIR_Done,
     /* 378267 */ // Label 7666: @378267
     /* 378267 */ GIM_Reject,
     /* 378268 */ // Label 7659: @378268
     /* 378268 */ GIM_Try, /*On fail goto*//*Label 7667*/ GIMT_Encode4(378294), // Rule ID 4807 //
     /* 378273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 378276 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 378279 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378283 */   // (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 378283 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 378288 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378292 */   GIR_RootConstrainSelectedInstOperands,
     /* 378293 */   // GIR_Coverage, 4807,
     /* 378293 */   GIR_Done,
     /* 378294 */ // Label 7667: @378294
     /* 378294 */ GIM_Try, /*On fail goto*//*Label 7668*/ GIMT_Encode4(378317), // Rule ID 4815 //
     /* 378299 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 378302 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378306 */   // (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 378306 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 378311 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378315 */   GIR_RootConstrainSelectedInstOperands,
     /* 378316 */   // GIR_Coverage, 4815,
     /* 378316 */   GIR_Done,
     /* 378317 */ // Label 7668: @378317
     /* 378317 */ GIM_Try, /*On fail goto*//*Label 7669*/ GIMT_Encode4(378340), // Rule ID 4817 //
     /* 378322 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 378325 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378329 */   // (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 378329 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 378334 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378338 */   GIR_RootConstrainSelectedInstOperands,
     /* 378339 */   // GIR_Coverage, 4817,
     /* 378339 */   GIR_Done,
     /* 378340 */ // Label 7669: @378340
     /* 378340 */ GIM_Try, /*On fail goto*//*Label 7670*/ GIMT_Encode4(378366), // Rule ID 5774 //
     /* 378345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378348 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 378351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378355 */   // (lround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 378355 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 378360 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378364 */   GIR_RootConstrainSelectedInstOperands,
     /* 378365 */   // GIR_Coverage, 5774,
     /* 378365 */   GIR_Done,
     /* 378366 */ // Label 7670: @378366
     /* 378366 */ GIM_Try, /*On fail goto*//*Label 7671*/ GIMT_Encode4(378392), // Rule ID 5776 //
     /* 378371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378374 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 378377 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378381 */   // (lround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 378381 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 378386 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378390 */   GIR_RootConstrainSelectedInstOperands,
     /* 378391 */   // GIR_Coverage, 5776,
     /* 378391 */   GIR_Done,
     /* 378392 */ // Label 7671: @378392
     /* 378392 */ GIM_Try, /*On fail goto*//*Label 7672*/ GIMT_Encode4(378415), // Rule ID 5779 //
     /* 378397 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 378400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378404 */   // (lround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 378404 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 378409 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378413 */   GIR_RootConstrainSelectedInstOperands,
     /* 378414 */   // GIR_Coverage, 5779,
     /* 378414 */   GIR_Done,
     /* 378415 */ // Label 7672: @378415
     /* 378415 */ GIM_Reject,
     /* 378416 */ // Label 7660: @378416
     /* 378416 */ GIM_Reject,
     /* 378417 */ // Label 97: @378417
     /* 378417 */ GIM_Try, /*On fail goto*//*Label 7673*/ GIMT_Encode4(378607),
     /* 378422 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 378425 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7677*/ GIMT_Encode4(378514),
     /* 378436 */   /*GILLT_s16*//*Label 7674*/ GIMT_Encode4(378448),
     /* 378440 */   /*GILLT_s32*//*Label 7675*/ GIMT_Encode4(378472),
     /* 378444 */   /*GILLT_s64*//*Label 7676*/ GIMT_Encode4(378493),
     /* 378448 */   // Label 7674: @378448
     /* 378448 */   GIM_Try, /*On fail goto*//*Label 7678*/ GIMT_Encode4(378471), // Rule ID 4809 //
     /* 378453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 378456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378460 */     // (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASUXHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 378460 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXHr),
     /* 378465 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378469 */     GIR_RootConstrainSelectedInstOperands,
     /* 378470 */     // GIR_Coverage, 4809,
     /* 378470 */     GIR_Done,
     /* 378471 */   // Label 7678: @378471
     /* 378471 */   GIM_Reject,
     /* 378472 */   // Label 7675: @378472
     /* 378472 */   GIM_Try, /*On fail goto*//*Label 7679*/ GIMT_Encode4(378492), // Rule ID 4819 //
     /* 378477 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378481 */     // (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASUXSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 378481 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXSr),
     /* 378486 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378490 */     GIR_RootConstrainSelectedInstOperands,
     /* 378491 */     // GIR_Coverage, 4819,
     /* 378491 */     GIR_Done,
     /* 378492 */   // Label 7679: @378492
     /* 378492 */   GIM_Reject,
     /* 378493 */   // Label 7676: @378493
     /* 378493 */   GIM_Try, /*On fail goto*//*Label 7680*/ GIMT_Encode4(378513), // Rule ID 4821 //
     /* 378498 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 378502 */     // (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASUXDr:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 378502 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASUXDr),
     /* 378507 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378511 */     GIR_RootConstrainSelectedInstOperands,
     /* 378512 */     // GIR_Coverage, 4821,
     /* 378512 */     GIR_Done,
     /* 378513 */   // Label 7680: @378513
     /* 378513 */   GIM_Reject,
     /* 378514 */   // Label 7677: @378514
     /* 378514 */   GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 7684*/ GIMT_Encode4(378606),
     /* 378525 */   /*GILLT_s16*//*Label 7681*/ GIMT_Encode4(378537),
     /* 378529 */   /*GILLT_s32*//*Label 7682*/ GIMT_Encode4(378561),
     /* 378533 */   /*GILLT_s64*//*Label 7683*/ GIMT_Encode4(378585),
     /* 378537 */   // Label 7681: @378537
     /* 378537 */   GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(378560), // Rule ID 5775 //
     /* 378542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378545 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378549 */     // (llround:{ *:[i64] } f16:{ *:[f16] }:$Rn)  =>  (FCVTASDHr:{ *:[i64] } f16:{ *:[f16] }:$Rn)
     /* 378549 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDHr),
     /* 378554 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378558 */     GIR_RootConstrainSelectedInstOperands,
     /* 378559 */     // GIR_Coverage, 5775,
     /* 378559 */     GIR_Done,
     /* 378560 */   // Label 7685: @378560
     /* 378560 */   GIM_Reject,
     /* 378561 */   // Label 7682: @378561
     /* 378561 */   GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(378584), // Rule ID 5777 //
     /* 378566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT),
     /* 378569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378573 */     // (llround:{ *:[i64] } f32:{ *:[f32] }:$Rn)  =>  (FCVTASDSr:{ *:[i64] } f32:{ *:[f32] }:$Rn)
     /* 378573 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASDSr),
     /* 378578 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378582 */     GIR_RootConstrainSelectedInstOperands,
     /* 378583 */     // GIR_Coverage, 5777,
     /* 378583 */     GIR_Done,
     /* 378584 */   // Label 7686: @378584
     /* 378584 */   GIM_Reject,
     /* 378585 */   // Label 7683: @378585
     /* 378585 */   GIM_Try, /*On fail goto*//*Label 7687*/ GIMT_Encode4(378605), // Rule ID 5780 //
     /* 378590 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378594 */     // (llround:{ *:[i64] } f64:{ *:[f64] }:$Rn)  =>  (FCVTASv1i64:{ *:[i64] } f64:{ *:[f64] }:$Rn)
     /* 378594 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTASv1i64),
     /* 378599 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 378603 */     GIR_RootConstrainSelectedInstOperands,
     /* 378604 */     // GIR_Coverage, 5780,
     /* 378604 */     GIR_Done,
     /* 378605 */   // Label 7687: @378605
     /* 378605 */   GIM_Reject,
     /* 378606 */   // Label 7684: @378606
     /* 378606 */   GIM_Reject,
     /* 378607 */ // Label 7673: @378607
     /* 378607 */ GIM_Reject,
     /* 378608 */ // Label 98: @378608
     /* 378608 */ GIM_Try, /*On fail goto*//*Label 7688*/ GIMT_Encode4(378623), // Rule ID 219 //
     /* 378613 */   // MIs[0] addr
     /* 378613 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
     /* 378616 */   // (br (bb:{ *:[Other] }):$addr)  =>  (B (bb:{ *:[Other] }):$addr)
     /* 378616 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::B),
     /* 378621 */   GIR_RootConstrainSelectedInstOperands,
     /* 378622 */   // GIR_Coverage, 219,
     /* 378622 */   GIR_Done,
     /* 378623 */ // Label 7688: @378623
     /* 378623 */ GIM_Reject,
     /* 378624 */ // Label 99: @378624
     /* 378624 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(21), /*)*//*default:*//*Label 7700*/ GIMT_Encode4(384171),
     /* 378635 */ /*GILLT_s64*//*Label 7689*/ GIMT_Encode4(378707), GIMT_Encode4(0),
     /* 378643 */ /*GILLT_v2s32*//*Label 7690*/ GIMT_Encode4(379285), GIMT_Encode4(0),
     /* 378651 */ /*GILLT_v4s16*//*Label 7691*/ GIMT_Encode4(379687), GIMT_Encode4(0),
     /* 378659 */ /*GILLT_v8s8*//*Label 7692*/ GIMT_Encode4(380089), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 378671 */ /*GILLT_nxv1s1*//*Label 7693*/ GIMT_Encode4(380269),
     /* 378675 */ /*GILLT_nxv2s1*//*Label 7694*/ GIMT_Encode4(382532),
     /* 378679 */ /*GILLT_nxv2s16*//*Label 7695*/ GIMT_Encode4(383387),
     /* 378683 */ /*GILLT_nxv2s32*//*Label 7696*/ GIMT_Encode4(383674), GIMT_Encode4(0),
     /* 378691 */ /*GILLT_nxv4s1*//*Label 7697*/ GIMT_Encode4(383744),
     /* 378695 */ /*GILLT_nxv4s16*//*Label 7698*/ GIMT_Encode4(384031), GIMT_Encode4(0),
     /* 378703 */ /*GILLT_nxv8s1*//*Label 7699*/ GIMT_Encode4(384101),
     /* 378707 */ // Label 7689: @378707
     /* 378707 */ GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(379284),
     /* 378712 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 378715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378719 */   GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(378807), // Rule ID 4830 //
     /* 378724 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 378727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SITOFP),
     /* 378735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 378739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 378743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
     /* 378747 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 378751 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378756 */     // MIs[0] Operand 2
     /* 378756 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 378767 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378769 */     // (extract_subvector:{ *:[v1f64] } (sint_to_fp:{ *:[v2f64] } (sext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)), 0:{ *:[i64] })  =>  (SCVTFDSr:{ *:[v1f64] } (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, ssub:{ *:[i32] }))
     /* 378769 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 378772 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 378776 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378781 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 378787 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 378792 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SCVTFDSr),
     /* 378800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 378802 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378805 */     GIR_RootConstrainSelectedInstOperands,
     /* 378806 */     // GIR_Coverage, 4830,
     /* 378806 */     GIR_EraseRootFromParent_Done,
     /* 378807 */   // Label 7702: @378807
     /* 378807 */   GIM_Try, /*On fail goto*//*Label 7703*/ GIMT_Encode4(378895), // Rule ID 4831 //
     /* 378812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRCVT_HasNEON),
     /* 378815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UITOFP),
     /* 378823 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 378827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 378831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
     /* 378835 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 378839 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378844 */     // MIs[0] Operand 2
     /* 378844 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 378855 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 378857 */     // (extract_subvector:{ *:[v1f64] } (uint_to_fp:{ *:[v2f64] } (zext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)), 0:{ *:[i64] })  =>  (UCVTFDSr:{ *:[v1f64] } (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, ssub:{ *:[i32] }))
     /* 378857 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 378860 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 378864 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 378869 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 378875 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 378880 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378885 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UCVTFDSr),
     /* 378888 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 378890 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 378893 */     GIR_RootConstrainSelectedInstOperands,
     /* 378894 */     // GIR_Coverage, 4831,
     /* 378894 */     GIR_EraseRootFromParent_Done,
     /* 378895 */   // Label 7703: @378895
     /* 378895 */   GIM_Try, /*On fail goto*//*Label 7704*/ GIMT_Encode4(378947), // Rule ID 6179 //
     /* 378900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 378908 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 378912 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 378914 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378919 */     // MIs[0] Operand 2
     /* 378919 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 378930 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 378932 */     // (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v2i32:{ *:[v1i64] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vn)
     /* 378932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 378935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 378937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 378941 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 378945 */     GIR_RootConstrainSelectedInstOperands,
     /* 378946 */     // GIR_Coverage, 6179,
     /* 378946 */     GIR_EraseRootFromParent_Done,
     /* 378947 */   // Label 7704: @378947
     /* 378947 */   GIM_Try, /*On fail goto*//*Label 7705*/ GIMT_Encode4(378999), // Rule ID 6182 //
     /* 378952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 378956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 378960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 378964 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 378966 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 378971 */     // MIs[0] Operand 2
     /* 378971 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 378982 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 378984 */     // (extract_subvector:{ *:[v1i64] } (anyext:{ *:[v2i64] } V64:{ *:[v2i32] }:$Vn)<<P:Predicate_anyext_oneuse>>, 1:{ *:[i64] })  =>  (ZIP2v2i32:{ *:[v1i64] } V64:{ *:[v2i32] }:$Vn, V64:{ *:[v2i32] }:$Vn)
     /* 378984 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 378987 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 378989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 378993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 378997 */     GIR_RootConstrainSelectedInstOperands,
     /* 378998 */     // GIR_Coverage, 6182,
     /* 378998 */     GIR_EraseRootFromParent_Done,
     /* 378999 */   // Label 7705: @378999
     /* 378999 */   GIM_Try, /*On fail goto*//*Label 7706*/ GIMT_Encode4(379067), // Rule ID 6058 //
     /* 379004 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379008 */     // MIs[0] Operand 2
     /* 379008 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 379019 */     // (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379019 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379022 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379026 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379031 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379035 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379039 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379042 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379044 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379047 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379049 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379056 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379061 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379066 */     // GIR_Coverage, 6058,
     /* 379066 */     GIR_EraseRootFromParent_Done,
     /* 379067 */   // Label 7706: @379067
     /* 379067 */   GIM_Try, /*On fail goto*//*Label 7707*/ GIMT_Encode4(379135), // Rule ID 6063 //
     /* 379072 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379076 */     // MIs[0] Operand 2
     /* 379076 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 379087 */     // (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379087 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379090 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379094 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379099 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379103 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379107 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379110 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379112 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379115 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379117 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379124 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379129 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379134 */     // GIR_Coverage, 6063,
     /* 379134 */     GIR_EraseRootFromParent_Done,
     /* 379135 */   // Label 7707: @379135
     /* 379135 */   GIM_Try, /*On fail goto*//*Label 7708*/ GIMT_Encode4(379177), // Rule ID 7538 //
     /* 379140 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379144 */     // MIs[0] Operand 2
     /* 379144 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379155 */     // (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, dsub:{ *:[i32] })
     /* 379155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379160 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 379166 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379171 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379176 */     // GIR_Coverage, 7538,
     /* 379176 */     GIR_EraseRootFromParent_Done,
     /* 379177 */   // Label 7708: @379177
     /* 379177 */   GIM_Try, /*On fail goto*//*Label 7709*/ GIMT_Encode4(379219), // Rule ID 7539 //
     /* 379182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379186 */     // MIs[0] Operand 2
     /* 379186 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379197 */     // (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] })
     /* 379197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379202 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 379208 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379213 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379218 */     // GIR_Coverage, 7539,
     /* 379218 */     GIR_EraseRootFromParent_Done,
     /* 379219 */   // Label 7709: @379219
     /* 379219 */   GIM_Try, /*On fail goto*//*Label 7710*/ GIMT_Encode4(379283), // Rule ID 7543 //
     /* 379224 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379228 */     // MIs[0] Operand 2
     /* 379228 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 379239 */     // (extract_subvector:{ *:[v1i64] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 379239 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379242 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 379246 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379251 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379255 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 379258 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379260 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379263 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379265 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379272 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379277 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379282 */     // GIR_Coverage, 7543,
     /* 379282 */     GIR_EraseRootFromParent_Done,
     /* 379283 */   // Label 7710: @379283
     /* 379283 */   GIM_Reject,
     /* 379284 */ // Label 7701: @379284
     /* 379284 */ GIM_Reject,
     /* 379285 */ // Label 7690: @379285
     /* 379285 */ GIM_Try, /*On fail goto*//*Label 7711*/ GIMT_Encode4(379686),
     /* 379290 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 379293 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379297 */   GIM_Try, /*On fail goto*//*Label 7712*/ GIMT_Encode4(379349), // Rule ID 6178 //
     /* 379302 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379306 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 379310 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 379314 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 379316 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379321 */     // MIs[0] Operand 2
     /* 379321 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379332 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 379334 */     // (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v4i16:{ *:[v2i32] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vn)
     /* 379334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 379337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 379339 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379343 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379347 */     GIR_RootConstrainSelectedInstOperands,
     /* 379348 */     // GIR_Coverage, 6178,
     /* 379348 */     GIR_EraseRootFromParent_Done,
     /* 379349 */   // Label 7712: @379349
     /* 379349 */   GIM_Try, /*On fail goto*//*Label 7713*/ GIMT_Encode4(379401), // Rule ID 6181 //
     /* 379354 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379358 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 379362 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 379366 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 379368 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379373 */     // MIs[0] Operand 2
     /* 379373 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 379384 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 379386 */     // (extract_subvector:{ *:[v2i32] } (anyext:{ *:[v4i32] } V64:{ *:[v4i16] }:$Vn)<<P:Predicate_anyext_oneuse>>, 2:{ *:[i64] })  =>  (ZIP2v4i16:{ *:[v2i32] } V64:{ *:[v4i16] }:$Vn, V64:{ *:[v4i16] }:$Vn)
     /* 379386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 379389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 379391 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379395 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379399 */     GIR_RootConstrainSelectedInstOperands,
     /* 379400 */     // GIR_Coverage, 6181,
     /* 379400 */     GIR_EraseRootFromParent_Done,
     /* 379401 */   // Label 7713: @379401
     /* 379401 */   GIM_Try, /*On fail goto*//*Label 7714*/ GIMT_Encode4(379469), // Rule ID 6048 //
     /* 379406 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379410 */     // MIs[0] Operand 2
     /* 379410 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 379421 */     // (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379421 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379424 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379428 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379433 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379437 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379441 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379444 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379451 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379458 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379463 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379468 */     // GIR_Coverage, 6048,
     /* 379468 */     GIR_EraseRootFromParent_Done,
     /* 379469 */   // Label 7714: @379469
     /* 379469 */   GIM_Try, /*On fail goto*//*Label 7715*/ GIMT_Encode4(379537), // Rule ID 6053 //
     /* 379474 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379478 */     // MIs[0] Operand 2
     /* 379478 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 379489 */     // (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379489 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379492 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379496 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379501 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379505 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379509 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379512 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379519 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379526 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379531 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379536 */     // GIR_Coverage, 6053,
     /* 379536 */     GIR_EraseRootFromParent_Done,
     /* 379537 */   // Label 7715: @379537
     /* 379537 */   GIM_Try, /*On fail goto*//*Label 7716*/ GIMT_Encode4(379579), // Rule ID 7535 //
     /* 379542 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379546 */     // MIs[0] Operand 2
     /* 379546 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379557 */     // (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] })
     /* 379557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379562 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 379568 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379573 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379578 */     // GIR_Coverage, 7535,
     /* 379578 */     GIR_EraseRootFromParent_Done,
     /* 379579 */   // Label 7716: @379579
     /* 379579 */   GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(379621), // Rule ID 7537 //
     /* 379584 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379588 */     // MIs[0] Operand 2
     /* 379588 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379599 */     // (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, dsub:{ *:[i32] })
     /* 379599 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379602 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379604 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 379610 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379615 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379620 */     // GIR_Coverage, 7537,
     /* 379620 */     GIR_EraseRootFromParent_Done,
     /* 379621 */   // Label 7717: @379621
     /* 379621 */   GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(379685), // Rule ID 7542 //
     /* 379626 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379630 */     // MIs[0] Operand 2
     /* 379630 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 379641 */     // (extract_subvector:{ *:[v2i32] } FPR128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v4i32] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 379641 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379644 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 379648 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379653 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379657 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 379660 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379667 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379674 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379679 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379684 */     // GIR_Coverage, 7542,
     /* 379684 */     GIR_EraseRootFromParent_Done,
     /* 379685 */   // Label 7718: @379685
     /* 379685 */   GIM_Reject,
     /* 379686 */ // Label 7711: @379686
     /* 379686 */ GIM_Reject,
     /* 379687 */ // Label 7691: @379687
     /* 379687 */ GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(380088),
     /* 379692 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 379695 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379699 */   GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(379751), // Rule ID 6177 //
     /* 379704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 379712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 379716 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 379718 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379723 */     // MIs[0] Operand 2
     /* 379723 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379734 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 379736 */     // (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Vn)<<P:Predicate_anyext_oneuse>>, 0:{ *:[i64] })  =>  (ZIP1v8i8:{ *:[v4i16] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vn)
     /* 379736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i8),
     /* 379739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 379741 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379745 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379749 */     GIR_RootConstrainSelectedInstOperands,
     /* 379750 */     // GIR_Coverage, 6177,
     /* 379750 */     GIR_EraseRootFromParent_Done,
     /* 379751 */   // Label 7720: @379751
     /* 379751 */   GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(379803), // Rule ID 6180 //
     /* 379756 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 379760 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
     /* 379764 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 379768 */     GIM_CheckHasOneUse, /*MI*/1,
     /* 379770 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379775 */     // MIs[0] Operand 2
     /* 379775 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 379786 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 379788 */     // (extract_subvector:{ *:[v4i16] } (anyext:{ *:[v8i16] } V64:{ *:[v8i8] }:$Vn)<<P:Predicate_anyext_oneuse>>, 4:{ *:[i64] })  =>  (ZIP2v8i8:{ *:[v4i16] } V64:{ *:[v8i8] }:$Vn, V64:{ *:[v8i8] }:$Vn)
     /* 379788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i8),
     /* 379791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 379793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
     /* 379801 */     GIR_RootConstrainSelectedInstOperands,
     /* 379802 */     // GIR_Coverage, 6180,
     /* 379802 */     GIR_EraseRootFromParent_Done,
     /* 379803 */   // Label 7721: @379803
     /* 379803 */   GIM_Try, /*On fail goto*//*Label 7722*/ GIMT_Encode4(379871), // Rule ID 6038 //
     /* 379808 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379812 */     // MIs[0] Operand 2
     /* 379812 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 379823 */     // (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379823 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379826 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379830 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379835 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379839 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379843 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379846 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379853 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379860 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379865 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379870 */     // GIR_Coverage, 6038,
     /* 379870 */     GIR_EraseRootFromParent_Done,
     /* 379871 */   // Label 7722: @379871
     /* 379871 */   GIM_Try, /*On fail goto*//*Label 7723*/ GIMT_Encode4(379939), // Rule ID 6043 //
     /* 379876 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379880 */     // MIs[0] Operand 2
     /* 379880 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 379891 */     // (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 379891 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 379894 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 379898 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 379903 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379907 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 379911 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 379914 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 379916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379921 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 379928 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379933 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379938 */     // GIR_Coverage, 6043,
     /* 379938 */     GIR_EraseRootFromParent_Done,
     /* 379939 */   // Label 7723: @379939
     /* 379939 */   GIM_Try, /*On fail goto*//*Label 7724*/ GIMT_Encode4(379981), // Rule ID 7533 //
     /* 379944 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379948 */     // MIs[0] Operand 2
     /* 379948 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 379959 */     // (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, dsub:{ *:[i32] })
     /* 379959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 379962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 379964 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 379970 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 379975 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379980 */     // GIR_Coverage, 7533,
     /* 379980 */     GIR_EraseRootFromParent_Done,
     /* 379981 */   // Label 7724: @379981
     /* 379981 */   GIM_Try, /*On fail goto*//*Label 7725*/ GIMT_Encode4(380023), // Rule ID 7536 //
     /* 379986 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 379990 */     // MIs[0] Operand 2
     /* 379990 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 380001 */     // (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })
     /* 380001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380006 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 380012 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380017 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380022 */     // GIR_Coverage, 7536,
     /* 380022 */     GIR_EraseRootFromParent_Done,
     /* 380023 */   // Label 7725: @380023
     /* 380023 */   GIM_Try, /*On fail goto*//*Label 7726*/ GIMT_Encode4(380087), // Rule ID 7541 //
     /* 380028 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380032 */     // MIs[0] Operand 2
     /* 380032 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 380043 */     // (extract_subvector:{ *:[v4i16] } FPR128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v8i16] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 380043 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 380046 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 380050 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380055 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 380059 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 380062 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380069 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 380076 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380081 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380086 */     // GIR_Coverage, 7541,
     /* 380086 */     GIR_EraseRootFromParent_Done,
     /* 380087 */   // Label 7726: @380087
     /* 380087 */   GIM_Reject,
     /* 380088 */ // Label 7719: @380088
     /* 380088 */ GIM_Reject,
     /* 380089 */ // Label 7692: @380089
     /* 380089 */ GIM_Try, /*On fail goto*//*Label 7727*/ GIMT_Encode4(380268),
     /* 380094 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 380097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380101 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380105 */   GIM_Try, /*On fail goto*//*Label 7728*/ GIMT_Encode4(380169), // Rule ID 6033 //
     /* 380110 */     // MIs[0] Operand 2
     /* 380110 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 380121 */     // (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EXTv16i8:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rn, 8:{ *:[i32] }), dsub:{ *:[i32] })
     /* 380121 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 380124 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 380128 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380133 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 380137 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 380141 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
     /* 380144 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380151 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 380158 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380163 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380168 */     // GIR_Coverage, 6033,
     /* 380168 */     GIR_EraseRootFromParent_Done,
     /* 380169 */   // Label 7728: @380169
     /* 380169 */   GIM_Try, /*On fail goto*//*Label 7729*/ GIMT_Encode4(380207), // Rule ID 7534 //
     /* 380174 */     // MIs[0] Operand 2
     /* 380174 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 380185 */     // (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, dsub:{ *:[i32] })
     /* 380185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380190 */     GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 380196 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380201 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380206 */     // GIR_Coverage, 7534,
     /* 380206 */     GIR_EraseRootFromParent_Done,
     /* 380207 */   // Label 7729: @380207
     /* 380207 */   GIM_Try, /*On fail goto*//*Label 7730*/ GIMT_Encode4(380267), // Rule ID 7540 //
     /* 380212 */     // MIs[0] Operand 2
     /* 380212 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 380223 */     // (extract_subvector:{ *:[v8i8] } FPR128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (DUPv2i64lane:{ *:[f128] } FPR128:{ *:[v16i8] }:$Rn, 1:{ *:[i64] }), dsub:{ *:[i32] })
     /* 380223 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 380226 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 380230 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380235 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 380239 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 380242 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 380247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 380249 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 380256 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 380261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 380266 */     // GIR_Coverage, 7540,
     /* 380266 */     GIR_EraseRootFromParent_Done,
     /* 380267 */   // Label 7730: @380267
     /* 380267 */   GIM_Reject,
     /* 380268 */ // Label 7727: @380268
     /* 380268 */ GIM_Reject,
     /* 380269 */ // Label 7693: @380269
     /* 380269 */ GIM_Try, /*On fail goto*//*Label 7731*/ GIMT_Encode4(380304), // Rule ID 9703 //
     /* 380274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 380280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380284 */   // MIs[0] Operand 2
     /* 380284 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 380295 */   // (extract_subvector:{ *:[nxv1i1] } nxv2i1:{ *:[nxv2i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv2i1] }:$Ps)
     /* 380295 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380298 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380300 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 380302 */   GIR_RootConstrainSelectedInstOperands,
     /* 380303 */   // GIR_Coverage, 9703,
     /* 380303 */   GIR_EraseRootFromParent_Done,
     /* 380304 */ // Label 7731: @380304
     /* 380304 */ GIM_Try, /*On fail goto*//*Label 7732*/ GIMT_Encode4(380339), // Rule ID 9704 //
     /* 380309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 380315 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380319 */   // MIs[0] Operand 2
     /* 380319 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 380330 */   // (extract_subvector:{ *:[nxv1i1] } nxv2i1:{ *:[nxv2i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv2i1] }:$Ps)
     /* 380330 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380333 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380335 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 380337 */   GIR_RootConstrainSelectedInstOperands,
     /* 380338 */   // GIR_Coverage, 9704,
     /* 380338 */   GIR_EraseRootFromParent_Done,
     /* 380339 */ // Label 7732: @380339
     /* 380339 */ GIM_Try, /*On fail goto*//*Label 7733*/ GIMT_Encode4(380393), // Rule ID 9711 //
     /* 380344 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380347 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 380350 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380354 */   // MIs[0] Operand 2
     /* 380354 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 380365 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 380365 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380368 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380372 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380377 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380381 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380383 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380386 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380388 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380391 */   GIR_RootConstrainSelectedInstOperands,
     /* 380392 */   // GIR_Coverage, 9711,
     /* 380392 */   GIR_EraseRootFromParent_Done,
     /* 380393 */ // Label 7733: @380393
     /* 380393 */ GIM_Try, /*On fail goto*//*Label 7734*/ GIMT_Encode4(380447), // Rule ID 9712 //
     /* 380398 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 380404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380408 */   // MIs[0] Operand 2
     /* 380408 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 380419 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 380419 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380422 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380426 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380431 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380435 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380440 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380442 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380445 */   GIR_RootConstrainSelectedInstOperands,
     /* 380446 */   // GIR_Coverage, 9712,
     /* 380446 */   GIR_EraseRootFromParent_Done,
     /* 380447 */ // Label 7734: @380447
     /* 380447 */ GIM_Try, /*On fail goto*//*Label 7735*/ GIMT_Encode4(380501), // Rule ID 9713 //
     /* 380452 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380455 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 380458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380462 */   // MIs[0] Operand 2
     /* 380462 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 380473 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 380473 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380476 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380480 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380485 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380489 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380496 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380499 */   GIR_RootConstrainSelectedInstOperands,
     /* 380500 */   // GIR_Coverage, 9713,
     /* 380500 */   GIR_EraseRootFromParent_Done,
     /* 380501 */ // Label 7735: @380501
     /* 380501 */ GIM_Try, /*On fail goto*//*Label 7736*/ GIMT_Encode4(380555), // Rule ID 9714 //
     /* 380506 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380509 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 380512 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380516 */   // MIs[0] Operand 2
     /* 380516 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 380527 */   // (extract_subvector:{ *:[nxv1i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv4i1] }:$Ps))
     /* 380527 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380530 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380534 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380539 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380543 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380545 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380548 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380550 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380553 */   GIR_RootConstrainSelectedInstOperands,
     /* 380554 */   // GIR_Coverage, 9714,
     /* 380554 */   GIR_EraseRootFromParent_Done,
     /* 380555 */ // Label 7736: @380555
     /* 380555 */ GIM_Try, /*On fail goto*//*Label 7737*/ GIMT_Encode4(380626), // Rule ID 9723 //
     /* 380560 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380563 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380566 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380570 */   // MIs[0] Operand 2
     /* 380570 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 380581 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380581 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380584 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380588 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380593 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380597 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380599 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380602 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380606 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380611 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380614 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380619 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380621 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380624 */   GIR_RootConstrainSelectedInstOperands,
     /* 380625 */   // GIR_Coverage, 9723,
     /* 380625 */   GIR_EraseRootFromParent_Done,
     /* 380626 */ // Label 7737: @380626
     /* 380626 */ GIM_Try, /*On fail goto*//*Label 7738*/ GIMT_Encode4(380697), // Rule ID 9724 //
     /* 380631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380634 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380641 */   // MIs[0] Operand 2
     /* 380641 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 380652 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380652 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380655 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380659 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380664 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380668 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380670 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380673 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380677 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380682 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380685 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380692 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380695 */   GIR_RootConstrainSelectedInstOperands,
     /* 380696 */   // GIR_Coverage, 9724,
     /* 380696 */   GIR_EraseRootFromParent_Done,
     /* 380697 */ // Label 7738: @380697
     /* 380697 */ GIM_Try, /*On fail goto*//*Label 7739*/ GIMT_Encode4(380768), // Rule ID 9725 //
     /* 380702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380705 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380712 */   // MIs[0] Operand 2
     /* 380712 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 380723 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380723 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380726 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380730 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380735 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380739 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380741 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380744 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380748 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380753 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380756 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380758 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380761 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380763 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380766 */   GIR_RootConstrainSelectedInstOperands,
     /* 380767 */   // GIR_Coverage, 9725,
     /* 380767 */   GIR_EraseRootFromParent_Done,
     /* 380768 */ // Label 7739: @380768
     /* 380768 */ GIM_Try, /*On fail goto*//*Label 7740*/ GIMT_Encode4(380839), // Rule ID 9726 //
     /* 380773 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380776 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380779 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380783 */   // MIs[0] Operand 2
     /* 380783 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 380794 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380794 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380797 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380801 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380806 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380810 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380812 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380815 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380819 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380824 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380827 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380829 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380832 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380834 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380837 */   GIR_RootConstrainSelectedInstOperands,
     /* 380838 */   // GIR_Coverage, 9726,
     /* 380838 */   GIR_EraseRootFromParent_Done,
     /* 380839 */ // Label 7740: @380839
     /* 380839 */ GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(380910), // Rule ID 9727 //
     /* 380844 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380847 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380854 */   // MIs[0] Operand 2
     /* 380854 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 380865 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380865 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380868 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380872 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380877 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380881 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380883 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380886 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380890 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380895 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380898 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380903 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380905 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380908 */   GIR_RootConstrainSelectedInstOperands,
     /* 380909 */   // GIR_Coverage, 9727,
     /* 380909 */   GIR_EraseRootFromParent_Done,
     /* 380910 */ // Label 7741: @380910
     /* 380910 */ GIM_Try, /*On fail goto*//*Label 7742*/ GIMT_Encode4(380981), // Rule ID 9728 //
     /* 380915 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380918 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380921 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380925 */   // MIs[0] Operand 2
     /* 380925 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(5),
     /* 380936 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 5:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 380936 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 380939 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380943 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380948 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 380952 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 380954 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 380957 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 380961 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 380966 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 380969 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 380971 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 380974 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 380976 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 380979 */   GIR_RootConstrainSelectedInstOperands,
     /* 380980 */   // GIR_Coverage, 9728,
     /* 380980 */   GIR_EraseRootFromParent_Done,
     /* 380981 */ // Label 7742: @380981
     /* 380981 */ GIM_Try, /*On fail goto*//*Label 7743*/ GIMT_Encode4(381052), // Rule ID 9729 //
     /* 380986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 380989 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 380992 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 380996 */   // MIs[0] Operand 2
     /* 380996 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 381007 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 381007 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381010 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381014 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381019 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381023 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381025 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381028 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381032 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381037 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381040 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381042 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381045 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381047 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381050 */   GIR_RootConstrainSelectedInstOperands,
     /* 381051 */   // GIR_Coverage, 9729,
     /* 381051 */   GIR_EraseRootFromParent_Done,
     /* 381052 */ // Label 7743: @381052
     /* 381052 */ GIM_Try, /*On fail goto*//*Label 7744*/ GIMT_Encode4(381123), // Rule ID 9730 //
     /* 381057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 381063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381067 */   // MIs[0] Operand 2
     /* 381067 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 381078 */   // (extract_subvector:{ *:[nxv1i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 7:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps)))
     /* 381078 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381081 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381085 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381090 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381094 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381096 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381099 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381103 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381108 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381111 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381113 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381116 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381118 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381121 */   GIR_RootConstrainSelectedInstOperands,
     /* 381122 */   // GIR_Coverage, 9730,
     /* 381122 */   GIR_EraseRootFromParent_Done,
     /* 381123 */ // Label 7744: @381123
     /* 381123 */ GIM_Try, /*On fail goto*//*Label 7745*/ GIMT_Encode4(381211), // Rule ID 9739 //
     /* 381128 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381131 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381138 */   // MIs[0] Operand 2
     /* 381138 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 381149 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381149 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381152 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381156 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381161 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381165 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381167 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381170 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381174 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381179 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381182 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381184 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381187 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381191 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381196 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381199 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381201 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381204 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381206 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381209 */   GIR_RootConstrainSelectedInstOperands,
     /* 381210 */   // GIR_Coverage, 9739,
     /* 381210 */   GIR_EraseRootFromParent_Done,
     /* 381211 */ // Label 7745: @381211
     /* 381211 */ GIM_Try, /*On fail goto*//*Label 7746*/ GIMT_Encode4(381299), // Rule ID 9740 //
     /* 381216 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381219 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381226 */   // MIs[0] Operand 2
     /* 381226 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(1),
     /* 381237 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 1:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381237 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381240 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381244 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381249 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381253 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381255 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381258 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381262 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381267 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381270 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381272 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381275 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381279 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381284 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381287 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381289 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381292 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381294 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381297 */   GIR_RootConstrainSelectedInstOperands,
     /* 381298 */   // GIR_Coverage, 9740,
     /* 381298 */   GIR_EraseRootFromParent_Done,
     /* 381299 */ // Label 7746: @381299
     /* 381299 */ GIM_Try, /*On fail goto*//*Label 7747*/ GIMT_Encode4(381387), // Rule ID 9741 //
     /* 381304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381307 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381314 */   // MIs[0] Operand 2
     /* 381314 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 381325 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381325 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381328 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381332 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381337 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381341 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381343 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381346 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381350 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381355 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381358 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381360 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381363 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381367 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381372 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381375 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381377 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381380 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381382 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381385 */   GIR_RootConstrainSelectedInstOperands,
     /* 381386 */   // GIR_Coverage, 9741,
     /* 381386 */   GIR_EraseRootFromParent_Done,
     /* 381387 */ // Label 7747: @381387
     /* 381387 */ GIM_Try, /*On fail goto*//*Label 7748*/ GIMT_Encode4(381475), // Rule ID 9742 //
     /* 381392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381402 */   // MIs[0] Operand 2
     /* 381402 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(3),
     /* 381413 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 3:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381413 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381416 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381420 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381425 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381429 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381431 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381434 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381438 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381443 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381446 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381448 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381451 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381455 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381460 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381463 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381465 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381468 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381470 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381473 */   GIR_RootConstrainSelectedInstOperands,
     /* 381474 */   // GIR_Coverage, 9742,
     /* 381474 */   GIR_EraseRootFromParent_Done,
     /* 381475 */ // Label 7748: @381475
     /* 381475 */ GIM_Try, /*On fail goto*//*Label 7749*/ GIMT_Encode4(381563), // Rule ID 9743 //
     /* 381480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381490 */   // MIs[0] Operand 2
     /* 381490 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 381501 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381501 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381504 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381508 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381513 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381517 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381519 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381522 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381526 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381531 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381534 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381536 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381539 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381543 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381548 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381551 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381553 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381556 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381558 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381561 */   GIR_RootConstrainSelectedInstOperands,
     /* 381562 */   // GIR_Coverage, 9743,
     /* 381562 */   GIR_EraseRootFromParent_Done,
     /* 381563 */ // Label 7749: @381563
     /* 381563 */ GIM_Try, /*On fail goto*//*Label 7750*/ GIMT_Encode4(381651), // Rule ID 9744 //
     /* 381568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381571 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381578 */   // MIs[0] Operand 2
     /* 381578 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(5),
     /* 381589 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 5:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381589 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381592 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381596 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381601 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381605 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381607 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381610 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381614 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381619 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381622 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381624 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381627 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381631 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381636 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381639 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381641 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381644 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381646 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381649 */   GIR_RootConstrainSelectedInstOperands,
     /* 381650 */   // GIR_Coverage, 9744,
     /* 381650 */   GIR_EraseRootFromParent_Done,
     /* 381651 */ // Label 7750: @381651
     /* 381651 */ GIM_Try, /*On fail goto*//*Label 7751*/ GIMT_Encode4(381739), // Rule ID 9745 //
     /* 381656 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381659 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381662 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381666 */   // MIs[0] Operand 2
     /* 381666 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 381677 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381677 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381680 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381684 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381689 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381693 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381695 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381698 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381702 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381707 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381710 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381712 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381715 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381719 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381724 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381727 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381729 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381732 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381734 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381737 */   GIR_RootConstrainSelectedInstOperands,
     /* 381738 */   // GIR_Coverage, 9745,
     /* 381738 */   GIR_EraseRootFromParent_Done,
     /* 381739 */ // Label 7751: @381739
     /* 381739 */ GIM_Try, /*On fail goto*//*Label 7752*/ GIMT_Encode4(381827), // Rule ID 9746 //
     /* 381744 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381747 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381750 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381754 */   // MIs[0] Operand 2
     /* 381754 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 381765 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 7:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381765 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381768 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381772 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381777 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381781 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381783 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381786 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381790 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381795 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381798 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381812 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381815 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381820 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381822 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381825 */   GIR_RootConstrainSelectedInstOperands,
     /* 381826 */   // GIR_Coverage, 9746,
     /* 381826 */   GIR_EraseRootFromParent_Done,
     /* 381827 */ // Label 7752: @381827
     /* 381827 */ GIM_Try, /*On fail goto*//*Label 7753*/ GIMT_Encode4(381915), // Rule ID 9747 //
     /* 381832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381838 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381842 */   // MIs[0] Operand 2
     /* 381842 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 381853 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381853 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381856 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381860 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381865 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381869 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381871 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381874 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381878 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381883 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381886 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381888 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381891 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381895 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381900 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381903 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381910 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 381913 */   GIR_RootConstrainSelectedInstOperands,
     /* 381914 */   // GIR_Coverage, 9747,
     /* 381914 */   GIR_EraseRootFromParent_Done,
     /* 381915 */ // Label 7753: @381915
     /* 381915 */ GIM_Try, /*On fail goto*//*Label 7754*/ GIMT_Encode4(382003), // Rule ID 9748 //
     /* 381920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 381923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 381926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 381930 */   // MIs[0] Operand 2
     /* 381930 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(9),
     /* 381941 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 9:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 381941 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 381944 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381948 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381953 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 381957 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 381959 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 381962 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381966 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381971 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 381974 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 381976 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 381979 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 381983 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 381988 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 381991 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 381993 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 381996 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 381998 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382001 */   GIR_RootConstrainSelectedInstOperands,
     /* 382002 */   // GIR_Coverage, 9748,
     /* 382002 */   GIR_EraseRootFromParent_Done,
     /* 382003 */ // Label 7754: @382003
     /* 382003 */ GIM_Try, /*On fail goto*//*Label 7755*/ GIMT_Encode4(382091), // Rule ID 9749 //
     /* 382008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382014 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382018 */   // MIs[0] Operand 2
     /* 382018 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(10),
     /* 382029 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 10:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382029 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382032 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382036 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382041 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382045 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382047 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382050 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382054 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382059 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382062 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382064 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382067 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382071 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382076 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382079 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382084 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382086 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382089 */   GIR_RootConstrainSelectedInstOperands,
     /* 382090 */   // GIR_Coverage, 9749,
     /* 382090 */   GIR_EraseRootFromParent_Done,
     /* 382091 */ // Label 7755: @382091
     /* 382091 */ GIM_Try, /*On fail goto*//*Label 7756*/ GIMT_Encode4(382179), // Rule ID 9750 //
     /* 382096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382099 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382106 */   // MIs[0] Operand 2
     /* 382106 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(11),
     /* 382117 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 11:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382117 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382120 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382124 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382129 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382133 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382135 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382138 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382142 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382147 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382150 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382152 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382155 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382159 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382164 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382167 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382169 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382172 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382174 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382177 */   GIR_RootConstrainSelectedInstOperands,
     /* 382178 */   // GIR_Coverage, 9750,
     /* 382178 */   GIR_EraseRootFromParent_Done,
     /* 382179 */ // Label 7756: @382179
     /* 382179 */ GIM_Try, /*On fail goto*//*Label 7757*/ GIMT_Encode4(382267), // Rule ID 9751 //
     /* 382184 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382194 */   // MIs[0] Operand 2
     /* 382194 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 382205 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382205 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382208 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382212 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382217 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382221 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382223 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382226 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382230 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382235 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382238 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382240 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382243 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382247 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382252 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382255 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382262 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382265 */   GIR_RootConstrainSelectedInstOperands,
     /* 382266 */   // GIR_Coverage, 9751,
     /* 382266 */   GIR_EraseRootFromParent_Done,
     /* 382267 */ // Label 7757: @382267
     /* 382267 */ GIM_Try, /*On fail goto*//*Label 7758*/ GIMT_Encode4(382355), // Rule ID 9752 //
     /* 382272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382275 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382278 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382282 */   // MIs[0] Operand 2
     /* 382282 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(13),
     /* 382293 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 13:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382293 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382296 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382300 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382305 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382309 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382311 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382314 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382318 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382323 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382326 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382328 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382331 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382335 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382340 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382343 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382345 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382348 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382350 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382353 */   GIR_RootConstrainSelectedInstOperands,
     /* 382354 */   // GIR_Coverage, 9752,
     /* 382354 */   GIR_EraseRootFromParent_Done,
     /* 382355 */ // Label 7758: @382355
     /* 382355 */ GIM_Try, /*On fail goto*//*Label 7759*/ GIMT_Encode4(382443), // Rule ID 9753 //
     /* 382360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382370 */   // MIs[0] Operand 2
     /* 382370 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(14),
     /* 382381 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 14:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382381 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382384 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382388 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382393 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382397 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382399 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382402 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382406 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382411 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382414 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382416 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382419 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382423 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382428 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382431 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382433 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382436 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382438 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382441 */   GIR_RootConstrainSelectedInstOperands,
     /* 382442 */   // GIR_Coverage, 9753,
     /* 382442 */   GIR_EraseRootFromParent_Done,
     /* 382443 */ // Label 7759: @382443
     /* 382443 */ GIM_Try, /*On fail goto*//*Label 7760*/ GIMT_Encode4(382531), // Rule ID 9754 //
     /* 382448 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382454 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382458 */   // MIs[0] Operand 2
     /* 382458 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 382469 */   // (extract_subvector:{ *:[nxv1i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 15:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))))
     /* 382469 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv1s1,
     /* 382472 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382476 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382481 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382485 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 382487 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382490 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382494 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382499 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 382502 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382504 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382507 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382511 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382516 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382519 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382521 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382524 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382526 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382529 */   GIR_RootConstrainSelectedInstOperands,
     /* 382530 */   // GIR_Coverage, 9754,
     /* 382530 */   GIR_EraseRootFromParent_Done,
     /* 382531 */ // Label 7760: @382531
     /* 382531 */ GIM_Reject,
     /* 382532 */ // Label 7694: @382532
     /* 382532 */ GIM_Try, /*On fail goto*//*Label 7761*/ GIMT_Encode4(382567), // Rule ID 9705 //
     /* 382537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 382543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382547 */   // MIs[0] Operand 2
     /* 382547 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 382558 */   // (extract_subvector:{ *:[nxv2i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } PPR:{ *:[nxv4i1] }:$Ps)
     /* 382558 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382561 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382563 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 382565 */   GIR_RootConstrainSelectedInstOperands,
     /* 382566 */   // GIR_Coverage, 9705,
     /* 382566 */   GIR_EraseRootFromParent_Done,
     /* 382567 */ // Label 7761: @382567
     /* 382567 */ GIM_Try, /*On fail goto*//*Label 7762*/ GIMT_Encode4(382602), // Rule ID 9706 //
     /* 382572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382575 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 382578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382582 */   // MIs[0] Operand 2
     /* 382582 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 382593 */   // (extract_subvector:{ *:[nxv2i1] } nxv4i1:{ *:[nxv4i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } PPR:{ *:[nxv4i1] }:$Ps)
     /* 382593 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382596 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382598 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 382600 */   GIR_RootConstrainSelectedInstOperands,
     /* 382601 */   // GIR_Coverage, 9706,
     /* 382601 */   GIR_EraseRootFromParent_Done,
     /* 382602 */ // Label 7762: @382602
     /* 382602 */ GIM_Try, /*On fail goto*//*Label 7763*/ GIMT_Encode4(382656), // Rule ID 9715 //
     /* 382607 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382610 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 382613 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382617 */   // MIs[0] Operand 2
     /* 382617 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 382628 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 382628 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382631 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382635 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382640 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382644 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382651 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382654 */   GIR_RootConstrainSelectedInstOperands,
     /* 382655 */   // GIR_Coverage, 9715,
     /* 382655 */   GIR_EraseRootFromParent_Done,
     /* 382656 */ // Label 7763: @382656
     /* 382656 */ GIM_Try, /*On fail goto*//*Label 7764*/ GIMT_Encode4(382710), // Rule ID 9716 //
     /* 382661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382664 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 382667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382671 */   // MIs[0] Operand 2
     /* 382671 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 382682 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 382682 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382685 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382689 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382694 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382698 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382700 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382703 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382705 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382708 */   GIR_RootConstrainSelectedInstOperands,
     /* 382709 */   // GIR_Coverage, 9716,
     /* 382709 */   GIR_EraseRootFromParent_Done,
     /* 382710 */ // Label 7764: @382710
     /* 382710 */ GIM_Try, /*On fail goto*//*Label 7765*/ GIMT_Encode4(382764), // Rule ID 9717 //
     /* 382715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 382721 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382725 */   // MIs[0] Operand 2
     /* 382725 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 382736 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 382736 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382739 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382743 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382748 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382752 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382754 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382757 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382759 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382762 */   GIR_RootConstrainSelectedInstOperands,
     /* 382763 */   // GIR_Coverage, 9717,
     /* 382763 */   GIR_EraseRootFromParent_Done,
     /* 382764 */ // Label 7765: @382764
     /* 382764 */ GIM_Try, /*On fail goto*//*Label 7766*/ GIMT_Encode4(382818), // Rule ID 9718 //
     /* 382769 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382772 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 382775 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382779 */   // MIs[0] Operand 2
     /* 382779 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 382790 */   // (extract_subvector:{ *:[nxv2i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv8i1] }:$Ps))
     /* 382790 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382793 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382797 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382802 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382806 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382808 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382811 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382813 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382816 */   GIR_RootConstrainSelectedInstOperands,
     /* 382817 */   // GIR_Coverage, 9718,
     /* 382817 */   GIR_EraseRootFromParent_Done,
     /* 382818 */ // Label 7766: @382818
     /* 382818 */ GIM_Try, /*On fail goto*//*Label 7767*/ GIMT_Encode4(382889), // Rule ID 9731 //
     /* 382823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382826 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382833 */   // MIs[0] Operand 2
     /* 382833 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 382844 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 382844 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382847 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382851 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382856 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382860 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382862 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382865 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382869 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382874 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382877 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382879 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382882 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382884 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382887 */   GIR_RootConstrainSelectedInstOperands,
     /* 382888 */   // GIR_Coverage, 9731,
     /* 382888 */   GIR_EraseRootFromParent_Done,
     /* 382889 */ // Label 7767: @382889
     /* 382889 */ GIM_Try, /*On fail goto*//*Label 7768*/ GIMT_Encode4(382960), // Rule ID 9732 //
     /* 382894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382904 */   // MIs[0] Operand 2
     /* 382904 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 382915 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 2:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 382915 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382918 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382922 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382927 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 382931 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 382933 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 382936 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382940 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382945 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 382948 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 382950 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 382953 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 382955 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 382958 */   GIR_RootConstrainSelectedInstOperands,
     /* 382959 */   // GIR_Coverage, 9732,
     /* 382959 */   GIR_EraseRootFromParent_Done,
     /* 382960 */ // Label 7768: @382960
     /* 382960 */ GIM_Try, /*On fail goto*//*Label 7769*/ GIMT_Encode4(383031), // Rule ID 9733 //
     /* 382965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 382968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 382971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 382975 */   // MIs[0] Operand 2
     /* 382975 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 382986 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 382986 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 382989 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 382993 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 382998 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383002 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383004 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383007 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383011 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383016 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383019 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383021 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383024 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383026 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383029 */   GIR_RootConstrainSelectedInstOperands,
     /* 383030 */   // GIR_Coverage, 9733,
     /* 383030 */   GIR_EraseRootFromParent_Done,
     /* 383031 */ // Label 7769: @383031
     /* 383031 */ GIM_Try, /*On fail goto*//*Label 7770*/ GIMT_Encode4(383102), // Rule ID 9734 //
     /* 383036 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383039 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383042 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383046 */   // MIs[0] Operand 2
     /* 383046 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 383057 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 6:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 383057 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383060 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383064 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383069 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383073 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383075 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383078 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383082 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383087 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383090 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383092 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383095 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383097 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383100 */   GIR_RootConstrainSelectedInstOperands,
     /* 383101 */   // GIR_Coverage, 9734,
     /* 383101 */   GIR_EraseRootFromParent_Done,
     /* 383102 */ // Label 7770: @383102
     /* 383102 */ GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(383173), // Rule ID 9735 //
     /* 383107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383110 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383117 */   // MIs[0] Operand 2
     /* 383117 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 383128 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 383128 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383131 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383135 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383140 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383144 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383146 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383149 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383153 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383158 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383161 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383168 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383171 */   GIR_RootConstrainSelectedInstOperands,
     /* 383172 */   // GIR_Coverage, 9735,
     /* 383172 */   GIR_EraseRootFromParent_Done,
     /* 383173 */ // Label 7771: @383173
     /* 383173 */ GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(383244), // Rule ID 9736 //
     /* 383178 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383181 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383184 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383188 */   // MIs[0] Operand 2
     /* 383188 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(10),
     /* 383199 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 10:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKLO_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 383199 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383202 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383206 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383211 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383215 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383217 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383220 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383224 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383229 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383232 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383239 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383242 */   GIR_RootConstrainSelectedInstOperands,
     /* 383243 */   // GIR_Coverage, 9736,
     /* 383243 */   GIR_EraseRootFromParent_Done,
     /* 383244 */ // Label 7772: @383244
     /* 383244 */ GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(383315), // Rule ID 9737 //
     /* 383249 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383252 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383255 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383259 */   // MIs[0] Operand 2
     /* 383259 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 383270 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 383270 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383273 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383277 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383282 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383286 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383288 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383291 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383295 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383300 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383303 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383305 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383308 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383310 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383313 */   GIR_RootConstrainSelectedInstOperands,
     /* 383314 */   // GIR_Coverage, 9737,
     /* 383314 */   GIR_EraseRootFromParent_Done,
     /* 383315 */ // Label 7773: @383315
     /* 383315 */ GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(383386), // Rule ID 9738 //
     /* 383320 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383323 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383330 */   // MIs[0] Operand 2
     /* 383330 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(14),
     /* 383341 */   // (extract_subvector:{ *:[nxv2i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 14:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv2i1] } (PUNPKHI_PP:{ *:[nxv1i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps)))
     /* 383341 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 383344 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383348 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383353 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383357 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 383359 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383362 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383366 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383371 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 383374 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383381 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383384 */   GIR_RootConstrainSelectedInstOperands,
     /* 383385 */   // GIR_Coverage, 9738,
     /* 383385 */   GIR_EraseRootFromParent_Done,
     /* 383386 */ // Label 7774: @383386
     /* 383386 */ GIM_Reject,
     /* 383387 */ // Label 7695: @383387
     /* 383387 */ GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(383422), // Rule ID 9755 //
     /* 383392 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383395 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 383398 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383402 */   // MIs[0] Operand 2
     /* 383402 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 383413 */   // (extract_subvector:{ *:[nxv2f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$Zs)
     /* 383413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 383416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383418 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 383420 */   GIR_RootConstrainSelectedInstOperands,
     /* 383421 */   // GIR_Coverage, 9755,
     /* 383421 */   GIR_EraseRootFromParent_Done,
     /* 383422 */ // Label 7775: @383422
     /* 383422 */ GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(383457), // Rule ID 9756 //
     /* 383427 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383430 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 383433 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383437 */   // MIs[0] Operand 2
     /* 383437 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 383448 */   // (extract_subvector:{ *:[nxv2f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$Zs)
     /* 383448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 383451 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383453 */   GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 383455 */   GIR_RootConstrainSelectedInstOperands,
     /* 383456 */   // GIR_Coverage, 9756,
     /* 383456 */   GIR_EraseRootFromParent_Done,
     /* 383457 */ // Label 7776: @383457
     /* 383457 */ GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(383511), // Rule ID 9761 //
     /* 383462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 383468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383472 */   // MIs[0] Operand 2
     /* 383472 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 383483 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } (UUNPKLO_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 383483 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 383486 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 383490 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383495 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 383499 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383501 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 383504 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383506 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383509 */   GIR_RootConstrainSelectedInstOperands,
     /* 383510 */   // GIR_Coverage, 9761,
     /* 383510 */   GIR_EraseRootFromParent_Done,
     /* 383511 */ // Label 7777: @383511
     /* 383511 */ GIM_Try, /*On fail goto*//*Label 7778*/ GIMT_Encode4(383565), // Rule ID 9762 //
     /* 383516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383519 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 383522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383526 */   // MIs[0] Operand 2
     /* 383526 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 383537 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } (UUNPKLO_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 383537 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 383540 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 383544 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383549 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 383553 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383555 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 383558 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383560 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383563 */   GIR_RootConstrainSelectedInstOperands,
     /* 383564 */   // GIR_Coverage, 9762,
     /* 383564 */   GIR_EraseRootFromParent_Done,
     /* 383565 */ // Label 7778: @383565
     /* 383565 */ GIM_Try, /*On fail goto*//*Label 7779*/ GIMT_Encode4(383619), // Rule ID 9763 //
     /* 383570 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383573 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 383576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383580 */   // MIs[0] Operand 2
     /* 383580 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 383591 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 4:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f16] } (UUNPKHI_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 383591 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 383594 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 383598 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383603 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 383607 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383609 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 383612 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383614 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383617 */   GIR_RootConstrainSelectedInstOperands,
     /* 383618 */   // GIR_Coverage, 9763,
     /* 383618 */   GIR_EraseRootFromParent_Done,
     /* 383619 */ // Label 7779: @383619
     /* 383619 */ GIM_Try, /*On fail goto*//*Label 7780*/ GIMT_Encode4(383673), // Rule ID 9764 //
     /* 383624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 383630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383634 */   // MIs[0] Operand 2
     /* 383634 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(6),
     /* 383645 */   // (extract_subvector:{ *:[nxv2f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 6:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f16] } (UUNPKHI_ZZ_S:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$Zs))
     /* 383645 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 383648 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 383652 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383657 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Zs
     /* 383661 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383663 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 383666 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383668 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383671 */   GIR_RootConstrainSelectedInstOperands,
     /* 383672 */   // GIR_Coverage, 9764,
     /* 383672 */   GIR_EraseRootFromParent_Done,
     /* 383673 */ // Label 7780: @383673
     /* 383673 */ GIM_Reject,
     /* 383674 */ // Label 7696: @383674
     /* 383674 */ GIM_Try, /*On fail goto*//*Label 7781*/ GIMT_Encode4(383743),
     /* 383679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 383682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 383686 */   GIM_Try, /*On fail goto*//*Label 7782*/ GIMT_Encode4(383714), // Rule ID 9759 //
     /* 383691 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383694 */     // MIs[0] Operand 2
     /* 383694 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 383705 */     // (extract_subvector:{ *:[nxv2f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_D:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$Zs)
     /* 383705 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_D),
     /* 383708 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383710 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 383712 */     GIR_RootConstrainSelectedInstOperands,
     /* 383713 */     // GIR_Coverage, 9759,
     /* 383713 */     GIR_EraseRootFromParent_Done,
     /* 383714 */   // Label 7782: @383714
     /* 383714 */   GIM_Try, /*On fail goto*//*Label 7783*/ GIMT_Encode4(383742), // Rule ID 9760 //
     /* 383719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383722 */     // MIs[0] Operand 2
     /* 383722 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(2),
     /* 383733 */     // (extract_subvector:{ *:[nxv2f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 2:{ *:[i64] })  =>  (UUNPKHI_ZZ_D:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$Zs)
     /* 383733 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_D),
     /* 383736 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 383738 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 383740 */     GIR_RootConstrainSelectedInstOperands,
     /* 383741 */     // GIR_Coverage, 9760,
     /* 383741 */     GIR_EraseRootFromParent_Done,
     /* 383742 */   // Label 7783: @383742
     /* 383742 */   GIM_Reject,
     /* 383743 */ // Label 7781: @383743
     /* 383743 */ GIM_Reject,
     /* 383744 */ // Label 7697: @383744
     /* 383744 */ GIM_Try, /*On fail goto*//*Label 7784*/ GIMT_Encode4(383779), // Rule ID 9707 //
     /* 383749 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383752 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 383755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383759 */   // MIs[0] Operand 2
     /* 383759 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 383770 */   // (extract_subvector:{ *:[nxv4i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } PPR:{ *:[nxv8i1] }:$Ps)
     /* 383770 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383773 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383775 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 383777 */   GIR_RootConstrainSelectedInstOperands,
     /* 383778 */   // GIR_Coverage, 9707,
     /* 383778 */   GIR_EraseRootFromParent_Done,
     /* 383779 */ // Label 7784: @383779
     /* 383779 */ GIM_Try, /*On fail goto*//*Label 7785*/ GIMT_Encode4(383814), // Rule ID 9708 //
     /* 383784 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383787 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 383790 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383794 */   // MIs[0] Operand 2
     /* 383794 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 383805 */   // (extract_subvector:{ *:[nxv4i1] } nxv8i1:{ *:[nxv8i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } PPR:{ *:[nxv8i1] }:$Ps)
     /* 383805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383808 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383810 */   GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 383812 */   GIR_RootConstrainSelectedInstOperands,
     /* 383813 */   // GIR_Coverage, 9708,
     /* 383813 */   GIR_EraseRootFromParent_Done,
     /* 383814 */ // Label 7785: @383814
     /* 383814 */ GIM_Try, /*On fail goto*//*Label 7786*/ GIMT_Encode4(383868), // Rule ID 9719 //
     /* 383819 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383822 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383825 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383829 */   // MIs[0] Operand 2
     /* 383829 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 383840 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 383840 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383843 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383847 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383852 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383856 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383858 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383861 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383863 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383866 */   GIR_RootConstrainSelectedInstOperands,
     /* 383867 */   // GIR_Coverage, 9719,
     /* 383867 */   GIR_EraseRootFromParent_Done,
     /* 383868 */ // Label 7786: @383868
     /* 383868 */ GIM_Try, /*On fail goto*//*Label 7787*/ GIMT_Encode4(383922), // Rule ID 9720 //
     /* 383873 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383876 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383883 */   // MIs[0] Operand 2
     /* 383883 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 383894 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 4:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } (PUNPKLO_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 383894 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383897 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383901 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383906 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383910 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383915 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383917 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383920 */   GIR_RootConstrainSelectedInstOperands,
     /* 383921 */   // GIR_Coverage, 9720,
     /* 383921 */   GIR_EraseRootFromParent_Done,
     /* 383922 */ // Label 7787: @383922
     /* 383922 */ GIM_Try, /*On fail goto*//*Label 7788*/ GIMT_Encode4(383976), // Rule ID 9721 //
     /* 383927 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383930 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383933 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383937 */   // MIs[0] Operand 2
     /* 383937 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 383948 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv4i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 383948 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 383951 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 383955 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 383960 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 383964 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 383966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 383969 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 383971 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 383974 */   GIR_RootConstrainSelectedInstOperands,
     /* 383975 */   // GIR_Coverage, 9721,
     /* 383975 */   GIR_EraseRootFromParent_Done,
     /* 383976 */ // Label 7788: @383976
     /* 383976 */ GIM_Try, /*On fail goto*//*Label 7789*/ GIMT_Encode4(384030), // Rule ID 9722 //
     /* 383981 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 383984 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 383987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 383991 */   // MIs[0] Operand 2
     /* 383991 */   GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(12),
     /* 384002 */   // (extract_subvector:{ *:[nxv4i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 12:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv4i1] } (PUNPKHI_PP:{ *:[nxv1i1] } PPR:{ *:[nxv16i1] }:$Ps))
     /* 384002 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 384005 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 384009 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384014 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Ps
     /* 384018 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384020 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 384023 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 384025 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 384028 */   GIR_RootConstrainSelectedInstOperands,
     /* 384029 */   // GIR_Coverage, 9722,
     /* 384029 */   GIR_EraseRootFromParent_Done,
     /* 384030 */ // Label 7789: @384030
     /* 384030 */ GIM_Reject,
     /* 384031 */ // Label 7698: @384031
     /* 384031 */ GIM_Try, /*On fail goto*//*Label 7790*/ GIMT_Encode4(384100),
     /* 384036 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 384039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 384043 */   GIM_Try, /*On fail goto*//*Label 7791*/ GIMT_Encode4(384071), // Rule ID 9757 //
     /* 384048 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 384051 */     // MIs[0] Operand 2
     /* 384051 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 384062 */     // (extract_subvector:{ *:[nxv4f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (UUNPKLO_ZZ_S:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$Zs)
     /* 384062 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKLO_ZZ_S),
     /* 384065 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 384067 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 384069 */     GIR_RootConstrainSelectedInstOperands,
     /* 384070 */     // GIR_Coverage, 9757,
     /* 384070 */     GIR_EraseRootFromParent_Done,
     /* 384071 */   // Label 7791: @384071
     /* 384071 */   GIM_Try, /*On fail goto*//*Label 7792*/ GIMT_Encode4(384099), // Rule ID 9758 //
     /* 384076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 384079 */     // MIs[0] Operand 2
     /* 384079 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4),
     /* 384090 */     // (extract_subvector:{ *:[nxv4f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 4:{ *:[i64] })  =>  (UUNPKHI_ZZ_S:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$Zs)
     /* 384090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UUNPKHI_ZZ_S),
     /* 384093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 384095 */     GIR_RootToRootCopy, /*OpIdx*/1, // Zs
     /* 384097 */     GIR_RootConstrainSelectedInstOperands,
     /* 384098 */     // GIR_Coverage, 9758,
     /* 384098 */     GIR_EraseRootFromParent_Done,
     /* 384099 */   // Label 7792: @384099
     /* 384099 */   GIM_Reject,
     /* 384100 */ // Label 7790: @384100
     /* 384100 */ GIM_Reject,
     /* 384101 */ // Label 7699: @384101
     /* 384101 */ GIM_Try, /*On fail goto*//*Label 7793*/ GIMT_Encode4(384170),
     /* 384106 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 384109 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 384113 */   GIM_Try, /*On fail goto*//*Label 7794*/ GIMT_Encode4(384141), // Rule ID 9709 //
     /* 384118 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 384121 */     // MIs[0] Operand 2
     /* 384121 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0),
     /* 384132 */     // (extract_subvector:{ *:[nxv8i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 0:{ *:[i64] })  =>  (PUNPKLO_PP:{ *:[nxv8i1] } PPR:{ *:[nxv16i1] }:$Ps)
     /* 384132 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKLO_PP),
     /* 384135 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 384137 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 384139 */     GIR_RootConstrainSelectedInstOperands,
     /* 384140 */     // GIR_Coverage, 9709,
     /* 384140 */     GIR_EraseRootFromParent_Done,
     /* 384141 */   // Label 7794: @384141
     /* 384141 */   GIM_Try, /*On fail goto*//*Label 7795*/ GIMT_Encode4(384169), // Rule ID 9710 //
     /* 384146 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 384149 */     // MIs[0] Operand 2
     /* 384149 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 384160 */     // (extract_subvector:{ *:[nxv8i1] } nxv16i1:{ *:[nxv16i1] }:$Ps, 8:{ *:[i64] })  =>  (PUNPKHI_PP:{ *:[nxv8i1] } PPR:{ *:[nxv16i1] }:$Ps)
     /* 384160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PUNPKHI_PP),
     /* 384163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Pd]
     /* 384165 */     GIR_RootToRootCopy, /*OpIdx*/1, // Ps
     /* 384167 */     GIR_RootConstrainSelectedInstOperands,
     /* 384168 */     // GIR_Coverage, 9710,
     /* 384168 */     GIR_EraseRootFromParent_Done,
     /* 384169 */   // Label 7795: @384169
     /* 384169 */   GIM_Reject,
     /* 384170 */ // Label 7793: @384170
     /* 384170 */ GIM_Reject,
     /* 384171 */ // Label 7700: @384171
     /* 384171 */ GIM_Reject,
     /* 384172 */ // Label 100: @384172
     /* 384172 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 7811*/ GIMT_Encode4(417108),
     /* 384183 */ /*GILLT_s64*//*Label 7796*/ GIMT_Encode4(384267), GIMT_Encode4(0),
     /* 384191 */ /*GILLT_v2s32*//*Label 7797*/ GIMT_Encode4(384977),
     /* 384195 */ /*GILLT_v2s64*//*Label 7798*/ GIMT_Encode4(388511),
     /* 384199 */ /*GILLT_v4s16*//*Label 7799*/ GIMT_Encode4(391755),
     /* 384203 */ /*GILLT_v4s32*//*Label 7800*/ GIMT_Encode4(395398),
     /* 384207 */ /*GILLT_v8s8*//*Label 7801*/ GIMT_Encode4(398469),
     /* 384211 */ /*GILLT_v8s16*//*Label 7802*/ GIMT_Encode4(401682),
     /* 384215 */ /*GILLT_v16s8*//*Label 7803*/ GIMT_Encode4(405104), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 384227 */ /*GILLT_nxv2s16*//*Label 7804*/ GIMT_Encode4(408308),
     /* 384231 */ /*GILLT_nxv2s32*//*Label 7805*/ GIMT_Encode4(408433),
     /* 384235 */ /*GILLT_nxv2s64*//*Label 7806*/ GIMT_Encode4(408558), GIMT_Encode4(0),
     /* 384243 */ /*GILLT_nxv4s16*//*Label 7807*/ GIMT_Encode4(410536),
     /* 384247 */ /*GILLT_nxv4s32*//*Label 7808*/ GIMT_Encode4(410688), GIMT_Encode4(0),
     /* 384255 */ /*GILLT_nxv8s16*//*Label 7809*/ GIMT_Encode4(412720), GIMT_Encode4(0),
     /* 384263 */ /*GILLT_nxv16s8*//*Label 7810*/ GIMT_Encode4(414988),
     /* 384267 */ // Label 7796: @384267
     /* 384267 */ GIM_Try, /*On fail goto*//*Label 7812*/ GIMT_Encode4(384976),
     /* 384272 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 384275 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 384278 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 384281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384285 */   GIM_Try, /*On fail goto*//*Label 7813*/ GIMT_Encode4(384415), // Rule ID 6335 //
     /* 384290 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384294 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 384298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 384302 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 384306 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 384310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384315 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 384319 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384323 */     // MIs[2] Operand 1
     /* 384323 */     // No operand predicates
     /* 384323 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 384327 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384331 */     // MIs[3] Operand 1
     /* 384331 */     // No operand predicates
     /* 384331 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 384333 */     // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 384333 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 384336 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384340 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384345 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 384348 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 384352 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 384355 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384360 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384365 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 384368 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 384372 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384377 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 384380 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 384383 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 384387 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 384390 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384392 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384395 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384397 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 384404 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384409 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384414 */     // GIR_Coverage, 6335,
     /* 384414 */     GIR_EraseRootFromParent_Done,
     /* 384415 */   // Label 7813: @384415
     /* 384415 */   GIM_Try, /*On fail goto*//*Label 7814*/ GIMT_Encode4(384576), // Rule ID 6336 //
     /* 384420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 384428 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 384432 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 384436 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 384440 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384445 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 384449 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384453 */     // MIs[2] Operand 1
     /* 384453 */     // No operand predicates
     /* 384453 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 384457 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384461 */     // MIs[3] Operand 1
     /* 384461 */     // No operand predicates
     /* 384461 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 384463 */     // (vector_insert:{ *:[v1f64] } V64:{ *:[v1f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 384463 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 384466 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384470 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384475 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 384478 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 384482 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 384485 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384490 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384495 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 384498 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384502 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384507 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 384510 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 384514 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 384517 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384522 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384527 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 384530 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 384534 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384539 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 384542 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 384545 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 384548 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 384551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384558 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 384565 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384570 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384575 */     // GIR_Coverage, 6336,
     /* 384575 */     GIR_EraseRootFromParent_Done,
     /* 384576 */   // Label 7814: @384576
     /* 384576 */   GIM_Try, /*On fail goto*//*Label 7815*/ GIMT_Encode4(384706), // Rule ID 6375 //
     /* 384581 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384585 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 384589 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 384593 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 384597 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 384601 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384606 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 384610 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384614 */     // MIs[2] Operand 1
     /* 384614 */     // No operand predicates
     /* 384614 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 384618 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384622 */     // MIs[3] Operand 1
     /* 384622 */     // No operand predicates
     /* 384622 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 384624 */     // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 384624 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 384627 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384631 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384636 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 384639 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 384643 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 384646 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384651 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 384659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 384663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384668 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 384671 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 384674 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 384678 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 384681 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384683 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384686 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384688 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 384695 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384700 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384705 */     // GIR_Coverage, 6375,
     /* 384705 */     GIR_EraseRootFromParent_Done,
     /* 384706 */   // Label 7815: @384706
     /* 384706 */   GIM_Try, /*On fail goto*//*Label 7816*/ GIMT_Encode4(384867), // Rule ID 6376 //
     /* 384711 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 384719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 384723 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 384727 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 384731 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384736 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 384740 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384744 */     // MIs[2] Operand 1
     /* 384744 */     // No operand predicates
     /* 384744 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 384748 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 384752 */     // MIs[3] Operand 1
     /* 384752 */     // No operand predicates
     /* 384752 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 384754 */     // (vector_insert:{ *:[v1i64] } V64:{ *:[v1i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (INSvi64lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 384754 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 384757 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384761 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384766 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 384769 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 384773 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 384776 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384781 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384786 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 384789 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 384793 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384798 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 384801 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 384805 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 384808 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384813 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384818 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 384821 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 384825 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 384830 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 384833 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 384836 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 384839 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 384842 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 384844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384849 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 384856 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384861 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 384866 */     // GIR_Coverage, 6376,
     /* 384866 */     GIR_EraseRootFromParent_Done,
     /* 384867 */   // Label 7816: @384867
     /* 384867 */   GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(384903), // Rule ID 7314 //
     /* 384872 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384876 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 384884 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384888 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 384890 */     // (vector_insert:{ *:[v1i64] } (undef:{ *:[v1i64] }), GPR64:{ *:[i64] }:$Xn, 0:{ *:[i64] })  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 384890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384895 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 384897 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384902 */     // GIR_Coverage, 7314,
     /* 384902 */     GIR_EraseRootFromParent_Done,
     /* 384903 */   // Label 7817: @384903
     /* 384903 */   GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(384939), // Rule ID 7316 //
     /* 384908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384912 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384916 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 384920 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384924 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 384926 */     // (vector_insert:{ *:[v1f64] } (undef:{ *:[v1f64] }), GPR64:{ *:[i64] }:$Xn, 0:{ *:[i64] })  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } GPR64:{ *:[i64] }:$Xn, FPR64:{ *:[i32] })
     /* 384926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 384931 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 384933 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384938 */     // GIR_Coverage, 7316,
     /* 384938 */     GIR_EraseRootFromParent_Done,
     /* 384939 */   // Label 7818: @384939
     /* 384939 */   GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(384975), // Rule ID 7318 //
     /* 384944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 384948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 384952 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384956 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 384960 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 384962 */     // (vector_insert:{ *:[v1f64] } (undef:{ *:[v1f64] }), FPR64:{ *:[f64] }:$Xn, 0:{ *:[i64] })  =>  FPR64:{ *:[v1f64] }:$Xn
     /* 384962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 384965 */     GIR_RootToRootCopy, /*OpIdx*/0, // dst
     /* 384967 */     GIR_RootToRootCopy, /*OpIdx*/2, // Xn
     /* 384969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384974 */     // GIR_Coverage, 7318,
     /* 384974 */     GIR_EraseRootFromParent_Done,
     /* 384975 */   // Label 7819: @384975
     /* 384975 */   GIM_Reject,
     /* 384976 */ // Label 7812: @384976
     /* 384976 */ GIM_Reject,
     /* 384977 */ // Label 7797: @384977
     /* 384977 */ GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(388510),
     /* 384982 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 384985 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 384988 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 384991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 384995 */   GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(385104), // Rule ID 4402 //
     /* 385000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385004 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385010 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385012 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385016 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385020 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385023 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385027 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385031 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385035 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385037 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 385044 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385044 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385047 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 385051 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385066 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385071 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385077 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385079 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385082 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385084 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385087 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385090 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385093 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385098 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385103 */     // GIR_Coverage, 4402,
     /* 385103 */     GIR_EraseRootFromParent_Done,
     /* 385104 */   // Label 7821: @385104
     /* 385104 */   GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(385213), // Rule ID 4403 //
     /* 385109 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385113 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385119 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385129 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385132 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385136 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385140 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385144 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385146 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 385153 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385153 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385156 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 385160 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385165 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385180 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385186 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385193 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385196 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385199 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385202 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385207 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385212 */     // GIR_Coverage, 4403,
     /* 385212 */     GIR_EraseRootFromParent_Done,
     /* 385213 */   // Label 7822: @385213
     /* 385213 */   GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(385322), // Rule ID 4510 //
     /* 385218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385222 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385228 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385230 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385234 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385238 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385241 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385245 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385249 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385253 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385255 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 385262 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385262 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385265 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 385269 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385274 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385289 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385295 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385297 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385300 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385302 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385305 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385308 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385311 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385316 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385321 */     // GIR_Coverage, 4510,
     /* 385321 */     GIR_EraseRootFromParent_Done,
     /* 385322 */   // Label 7823: @385322
     /* 385322 */   GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(385431), // Rule ID 4511 //
     /* 385327 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385331 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385337 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385339 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385343 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385347 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385350 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385354 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385358 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385362 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385364 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 385371 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385371 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385374 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 385378 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385383 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385398 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385404 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385414 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385420 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385425 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385430 */     // GIR_Coverage, 4511,
     /* 385430 */     GIR_EraseRootFromParent_Done,
     /* 385431 */   // Label 7824: @385431
     /* 385431 */   GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(385536), // Rule ID 4408 //
     /* 385436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385444 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385448 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385452 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385455 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385459 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385463 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385467 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385469 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 385476 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385476 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385479 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 385483 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385488 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385503 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385509 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385519 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385525 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385530 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385535 */     // GIR_Coverage, 4408,
     /* 385535 */     GIR_EraseRootFromParent_Done,
     /* 385536 */   // Label 7825: @385536
     /* 385536 */   GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(385641), // Rule ID 4410 //
     /* 385541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385549 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385553 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385557 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385560 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385564 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385568 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385572 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385574 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 385581 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385581 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385584 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 385588 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385593 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385598 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385603 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385608 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385614 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385621 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385624 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385627 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385630 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385635 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385640 */     // GIR_Coverage, 4410,
     /* 385640 */     GIR_EraseRootFromParent_Done,
     /* 385641 */   // Label 7826: @385641
     /* 385641 */   GIM_Try, /*On fail goto*//*Label 7827*/ GIMT_Encode4(385746), // Rule ID 4516 //
     /* 385646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385654 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385658 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385662 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385665 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385669 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385673 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385677 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385679 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 385686 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385686 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385689 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 385693 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385698 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385703 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385708 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385713 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385719 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385726 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385729 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385735 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385740 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385745 */     // GIR_Coverage, 4516,
     /* 385745 */     GIR_EraseRootFromParent_Done,
     /* 385746 */   // Label 7827: @385746
     /* 385746 */   GIM_Try, /*On fail goto*//*Label 7828*/ GIMT_Encode4(385851), // Rule ID 4518 //
     /* 385751 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385755 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 385759 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385763 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385767 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385770 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385774 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385778 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385782 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385784 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 385791 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 385791 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385794 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 385798 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 385813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 385818 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385824 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385831 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385834 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385837 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385840 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385845 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385850 */     // GIR_Coverage, 4518,
     /* 385850 */     GIR_EraseRootFromParent_Done,
     /* 385851 */   // Label 7828: @385851
     /* 385851 */   GIM_Try, /*On fail goto*//*Label 7829*/ GIMT_Encode4(385955), // Rule ID 4400 //
     /* 385856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385860 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385866 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385876 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385879 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385883 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385887 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385891 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385893 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 385900 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 385900 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 385903 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 385907 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 385912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 385917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 385922 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 385928 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 385930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 385933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 385935 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 385938 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 385941 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 385944 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 385949 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 385954 */     // GIR_Coverage, 4400,
     /* 385954 */     GIR_EraseRootFromParent_Done,
     /* 385955 */   // Label 7829: @385955
     /* 385955 */   GIM_Try, /*On fail goto*//*Label 7830*/ GIMT_Encode4(386059), // Rule ID 4401 //
     /* 385960 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 385964 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 385970 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 385972 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 385976 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 385980 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 385983 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 385987 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 385991 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 385995 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 385997 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 386004 */     // (vector_insert:{ *:[v2i32] } immAllZerosV:{ *:[v2i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 386004 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386007 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 386011 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386016 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386021 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386026 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386032 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386039 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386042 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386045 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386048 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386053 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386058 */     // GIR_Coverage, 4401,
     /* 386058 */     GIR_EraseRootFromParent_Done,
     /* 386059 */   // Label 7830: @386059
     /* 386059 */   GIM_Try, /*On fail goto*//*Label 7831*/ GIMT_Encode4(386163), // Rule ID 4508 //
     /* 386064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386068 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386074 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386084 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386087 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386091 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386095 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386099 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386101 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 386108 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 386108 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386111 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 386115 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386125 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386130 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386136 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386143 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386146 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386149 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386152 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386157 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386162 */     // GIR_Coverage, 4508,
     /* 386162 */     GIR_EraseRootFromParent_Done,
     /* 386163 */   // Label 7831: @386163
     /* 386163 */   GIM_Try, /*On fail goto*//*Label 7832*/ GIMT_Encode4(386267), // Rule ID 4509 //
     /* 386168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386172 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 386178 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 386180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386188 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386191 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386195 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386199 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386203 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386205 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 386212 */     // (vector_insert:{ *:[v2f32] } immAllZerosV:{ *:[v2f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 386212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 386219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386234 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386240 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386247 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386250 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386253 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386256 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386266 */     // GIR_Coverage, 4509,
     /* 386266 */     GIR_EraseRootFromParent_Done,
     /* 386267 */   // Label 7832: @386267
     /* 386267 */   GIM_Try, /*On fail goto*//*Label 7833*/ GIMT_Encode4(386367), // Rule ID 4404 //
     /* 386272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386288 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386291 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386295 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386299 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386303 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386305 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 386312 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 386312 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386315 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 386319 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386324 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386329 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386334 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386340 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386350 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386353 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386356 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386361 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386366 */     // GIR_Coverage, 4404,
     /* 386366 */     GIR_EraseRootFromParent_Done,
     /* 386367 */   // Label 7833: @386367
     /* 386367 */   GIM_Try, /*On fail goto*//*Label 7834*/ GIMT_Encode4(386467), // Rule ID 4406 //
     /* 386372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386380 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386384 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386388 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386391 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386395 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386399 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386403 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386405 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 386412 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 386412 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386415 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 386419 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386429 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386434 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386440 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386442 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386445 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386447 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386450 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386453 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386456 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386461 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386466 */     // GIR_Coverage, 4406,
     /* 386466 */     GIR_EraseRootFromParent_Done,
     /* 386467 */   // Label 7834: @386467
     /* 386467 */   GIM_Try, /*On fail goto*//*Label 7835*/ GIMT_Encode4(386567), // Rule ID 4512 //
     /* 386472 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386476 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386480 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386484 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386488 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386491 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386495 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386499 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386503 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386505 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 386512 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 386512 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386515 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 386519 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386534 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386540 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386547 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386550 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386553 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386561 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386566 */     // GIR_Coverage, 4512,
     /* 386566 */     GIR_EraseRootFromParent_Done,
     /* 386567 */   // Label 7835: @386567
     /* 386567 */   GIM_Try, /*On fail goto*//*Label 7836*/ GIMT_Encode4(386667), // Rule ID 4514 //
     /* 386572 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386576 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386580 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386584 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386588 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386591 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386595 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 386599 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386603 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386605 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 386612 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 386612 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 386615 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 386619 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386624 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 386629 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 386634 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386640 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386642 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386645 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 386650 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 386653 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 386656 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386661 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 386666 */     // GIR_Coverage, 4514,
     /* 386666 */     GIR_EraseRootFromParent_Done,
     /* 386667 */   // Label 7836: @386667
     /* 386667 */   GIM_Try, /*On fail goto*//*Label 7837*/ GIMT_Encode4(386787), // Rule ID 7088 //
     /* 386672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 386675 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386679 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386691 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386694 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386698 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 386705 */     // MIs[2] Rn
     /* 386705 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 386709 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 386714 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386718 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386720 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i16:{ *:[f128] } (IMPLICIT_DEF:{ *:[v8i16] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 386720 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 386723 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 386727 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386732 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 386734 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 386737 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 386741 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386746 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 386749 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 386752 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 386756 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386762 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386764 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 386767 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386769 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 386776 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386781 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 386786 */     // GIR_Coverage, 7088,
     /* 386786 */     GIR_EraseRootFromParent_Done,
     /* 386787 */   // Label 7837: @386787
     /* 386787 */   GIM_Try, /*On fail goto*//*Label 7838*/ GIMT_Encode4(386907), // Rule ID 7090 //
     /* 386792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 386795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 386799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 386803 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 386807 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 386811 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 386814 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 386818 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 386825 */     // MIs[2] Rn
     /* 386825 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 386829 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 386834 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 386838 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 386840 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i8:{ *:[f128] } (IMPLICIT_DEF:{ *:[v16i8] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 386840 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 386843 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 386847 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386852 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 386854 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 386857 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 386861 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386866 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 386869 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 386872 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 386876 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 386882 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 386884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 386887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 386889 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 386896 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386901 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 386906 */     // GIR_Coverage, 7090,
     /* 386906 */     GIR_EraseRootFromParent_Done,
     /* 386907 */   // Label 7838: @386907
     /* 386907 */   GIM_Try, /*On fail goto*//*Label 7839*/ GIMT_Encode4(387037), // Rule ID 6327 //
     /* 386912 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 386920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 386924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 386928 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 386932 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 386937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 386941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 386945 */     // MIs[2] Operand 1
     /* 386945 */     // No operand predicates
     /* 386945 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 386949 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 386953 */     // MIs[3] Operand 1
     /* 386953 */     // No operand predicates
     /* 386953 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 386955 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 386955 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 386958 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 386962 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386967 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 386970 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 386974 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 386977 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 386982 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 386987 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 386990 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 386994 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 386999 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387002 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 387005 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387009 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 387012 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387014 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387017 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387019 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387026 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387031 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387036 */     // GIR_Coverage, 6327,
     /* 387036 */     GIR_EraseRootFromParent_Done,
     /* 387037 */   // Label 7839: @387037
     /* 387037 */   GIM_Try, /*On fail goto*//*Label 7840*/ GIMT_Encode4(387198), // Rule ID 6328 //
     /* 387042 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387046 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387050 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 387054 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 387058 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 387062 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387067 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 387071 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387075 */     // MIs[2] Operand 1
     /* 387075 */     // No operand predicates
     /* 387075 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 387079 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387083 */     // MIs[3] Operand 1
     /* 387083 */     // No operand predicates
     /* 387083 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 387085 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 387085 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 387088 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387092 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387097 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 387100 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387104 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 387107 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387112 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387117 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 387120 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387124 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387129 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 387132 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 387136 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387139 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387144 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387149 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387152 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 387156 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387161 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387164 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 387167 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 387170 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 387173 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387180 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387187 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387192 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387197 */     // GIR_Coverage, 6328,
     /* 387197 */     GIR_EraseRootFromParent_Done,
     /* 387198 */   // Label 7840: @387198
     /* 387198 */   GIM_Try, /*On fail goto*//*Label 7841*/ GIMT_Encode4(387328), // Rule ID 6367 //
     /* 387203 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387207 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387211 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 387215 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 387219 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 387223 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387228 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 387232 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387236 */     // MIs[2] Operand 1
     /* 387236 */     // No operand predicates
     /* 387236 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 387240 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387244 */     // MIs[3] Operand 1
     /* 387244 */     // No operand predicates
     /* 387244 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 387246 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 387246 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 387249 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387253 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387258 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 387261 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 387265 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387268 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387273 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387278 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387281 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 387285 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387290 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387293 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 387296 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387300 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 387303 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387310 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387317 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387322 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387327 */     // GIR_Coverage, 6367,
     /* 387327 */     GIR_EraseRootFromParent_Done,
     /* 387328 */   // Label 7841: @387328
     /* 387328 */   GIM_Try, /*On fail goto*//*Label 7842*/ GIMT_Encode4(387489), // Rule ID 6368 //
     /* 387333 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387337 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387341 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 387345 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 387349 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 387353 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387358 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 387362 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387366 */     // MIs[2] Operand 1
     /* 387366 */     // No operand predicates
     /* 387366 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 387370 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387374 */     // MIs[3] Operand 1
     /* 387374 */     // No operand predicates
     /* 387374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 387376 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 387376 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 387379 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387383 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387388 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 387391 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387395 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 387398 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387403 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387408 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 387411 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387415 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387420 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 387423 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 387427 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387430 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387435 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 387447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387452 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387455 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 387458 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 387461 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 387464 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387471 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387478 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387483 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387488 */     // GIR_Coverage, 6368,
     /* 387488 */     GIR_EraseRootFromParent_Done,
     /* 387489 */   // Label 7842: @387489
     /* 387489 */   GIM_Try, /*On fail goto*//*Label 7843*/ GIMT_Encode4(387555), // Rule ID 6274 //
     /* 387494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387498 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 387502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 387506 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387510 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 387512 */     // (vector_insert:{ *:[v2i32] } (undef:{ *:[v2i32] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i32] } (IMPLICIT_DEF:{ *:[v2i32] }), GPR32:{ *:[i32] }:$Rn, ssub:{ *:[i32] })
     /* 387512 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
     /* 387515 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 387519 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387524 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 387529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387531 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387534 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 387536 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 387539 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387544 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 387554 */     // GIR_Coverage, 6274,
     /* 387554 */     GIR_EraseRootFromParent_Done,
     /* 387555 */   // Label 7843: @387555
     /* 387555 */   GIM_Try, /*On fail goto*//*Label 7844*/ GIMT_Encode4(387621), // Rule ID 6290 //
     /* 387560 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 387564 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 387568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 387572 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 387576 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 387578 */     // (vector_insert:{ *:[v2f32] } (undef:{ *:[v2f32] }), FPR32:{ *:[f32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] })
     /* 387578 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
     /* 387581 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 387585 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387590 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387592 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 387595 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387597 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 387600 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 387602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 387605 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387610 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387615 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 387620 */     // GIR_Coverage, 6290,
     /* 387620 */     GIR_EraseRootFromParent_Done,
     /* 387621 */   // Label 7844: @387621
     /* 387621 */   GIM_Try, /*On fail goto*//*Label 7845*/ GIMT_Encode4(387759), // Rule ID 6298 //
     /* 387626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseWzrToVecMove),
     /* 387629 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387633 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387637 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 387641 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 387645 */     // MIs[1] Operand 1
     /* 387645 */     // No operand predicates
     /* 387645 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 387649 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387653 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 387657 */     // MIs[2] Operand 1
     /* 387657 */     // No operand predicates
     /* 387657 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387659 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
     /* 387659 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 387662 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 387666 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387671 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 387673 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 387676 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 387680 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387685 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 387688 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 387692 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387695 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387700 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387705 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387710 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387713 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 387717 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387722 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387725 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
     /* 387728 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 387734 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387741 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387748 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387753 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387758 */     // GIR_Coverage, 6298,
     /* 387758 */     GIR_EraseRootFromParent_Done,
     /* 387759 */   // Label 7845: @387759
     /* 387759 */   GIM_Try, /*On fail goto*//*Label 7846*/ GIMT_Encode4(387891), // Rule ID 7097 //
     /* 387764 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387776 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387779 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 387783 */     // MIs[1] Rn
     /* 387783 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 387787 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 387792 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 387796 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387800 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 387804 */     // MIs[2] Operand 1
     /* 387804 */     // No operand predicates
     /* 387804 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387806 */     // (vector_insert:{ *:[v2i32] } VecListOne64:{ *:[v2i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2i32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 387806 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 387809 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387813 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387818 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 387821 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 387825 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387828 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387833 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387838 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387841 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 387845 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387850 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387853 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 387856 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387860 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387866 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 387868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 387871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 387873 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 387880 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387885 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387890 */     // GIR_Coverage, 7097,
     /* 387890 */     GIR_EraseRootFromParent_Done,
     /* 387891 */   // Label 7846: @387891
     /* 387891 */   GIM_Try, /*On fail goto*//*Label 7847*/ GIMT_Encode4(388023), // Rule ID 7098 //
     /* 387896 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387900 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 387904 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 387908 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 387911 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 387915 */     // MIs[1] Rn
     /* 387915 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 387919 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 387924 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 387928 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 387932 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 387936 */     // MIs[2] Operand 1
     /* 387936 */     // No operand predicates
     /* 387936 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 387938 */     // (vector_insert:{ *:[v2f32] } VecListOne64:{ *:[v2f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (LD1i32:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v2f32] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 387938 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 387941 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 387945 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387950 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 387953 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 387957 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 387960 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 387965 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 387970 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 387973 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 387977 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 387982 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 387985 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 387988 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 387992 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 387998 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 388003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388005 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 388012 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388017 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388022 */     // GIR_Coverage, 7098,
     /* 388022 */     GIR_EraseRootFromParent_Done,
     /* 388023 */   // Label 7847: @388023
     /* 388023 */   GIM_Try, /*On fail goto*//*Label 7848*/ GIMT_Encode4(388206), // Rule ID 6378 //
     /* 388028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 388032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 388036 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 388040 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 388045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 388049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 388053 */     // MIs[2] Operand 1
     /* 388053 */     // No operand predicates
     /* 388053 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388055 */     // (vector_insert:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 388055 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s128,
     /* 388058 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 388062 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388067 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 388069 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s128,
     /* 388072 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 388076 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388081 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 388084 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 388088 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/18,
     /* 388091 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388096 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388101 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 388106 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 388109 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 388113 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388118 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 388120 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 388123 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 388127 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388132 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 388135 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 388139 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 388142 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388147 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388152 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388157 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 388160 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 388164 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388169 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 388172 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immd
     /* 388175 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 388178 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 388181 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388183 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 388186 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388188 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 388195 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388200 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388205 */     // GIR_Coverage, 6378,
     /* 388205 */     GIR_EraseRootFromParent_Done,
     /* 388206 */   // Label 7848: @388206
     /* 388206 */   GIM_Try, /*On fail goto*//*Label 7849*/ GIMT_Encode4(388384), // Rule ID 6301 //
     /* 388211 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388215 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 388219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 388223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 388227 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 388231 */     // MIs[1] Operand 1
     /* 388231 */     // No operand predicates
     /* 388231 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 388233 */     // (vector_insert:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (INSvi32lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 388233 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 388236 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 388240 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388245 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 388247 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 388250 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 388254 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388259 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 388262 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 388266 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/18,
     /* 388269 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388274 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388279 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 388284 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 388287 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 388291 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388296 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 388298 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 388301 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 388305 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388310 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 388313 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 388317 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 388320 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388325 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388330 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388335 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 388338 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 388342 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388347 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 388350 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 388353 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 388356 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 388359 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 388364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388366 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 388373 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388378 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388383 */     // GIR_Coverage, 6301,
     /* 388383 */     GIR_EraseRootFromParent_Done,
     /* 388384 */   // Label 7849: @388384
     /* 388384 */   GIM_Try, /*On fail goto*//*Label 7850*/ GIMT_Encode4(388509), // Rule ID 6304 //
     /* 388389 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388393 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 388397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 388401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 388405 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 388409 */     // MIs[1] Operand 1
     /* 388409 */     // No operand predicates
     /* 388409 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 388411 */     // (vector_insert:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (INSvi32gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 388411 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
     /* 388414 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 388418 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388423 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 388425 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 388428 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 388432 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388437 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 388440 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 388444 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 388447 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388452 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388457 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388462 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 388465 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 388469 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388474 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 388477 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 388480 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 388484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 388489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388491 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 388498 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388503 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388508 */     // GIR_Coverage, 6304,
     /* 388508 */     GIR_EraseRootFromParent_Done,
     /* 388509 */   // Label 7850: @388509
     /* 388509 */   GIM_Reject,
     /* 388510 */ // Label 7820: @388510
     /* 388510 */ GIM_Reject,
     /* 388511 */ // Label 7798: @388511
     /* 388511 */ GIM_Try, /*On fail goto*//*Label 7851*/ GIMT_Encode4(391754),
     /* 388516 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 388519 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 388522 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 388525 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388529 */   GIM_Try, /*On fail goto*//*Label 7852*/ GIMT_Encode4(388638), // Rule ID 4426 //
     /* 388534 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388538 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388544 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388546 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388550 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388554 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388557 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388561 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388565 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388569 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388571 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 388578 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 388578 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 388581 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 388585 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388590 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388600 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388605 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388611 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388618 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388621 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388624 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 388627 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388632 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388637 */     // GIR_Coverage, 4426,
     /* 388637 */     GIR_EraseRootFromParent_Done,
     /* 388638 */   // Label 7852: @388638
     /* 388638 */   GIM_Try, /*On fail goto*//*Label 7853*/ GIMT_Encode4(388747), // Rule ID 4427 //
     /* 388643 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388647 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388653 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388655 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388659 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388663 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388666 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388670 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388674 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388678 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388680 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 388687 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 388687 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 388690 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 388694 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388699 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388704 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388709 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388714 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388720 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388727 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388730 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388733 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 388736 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388741 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388746 */     // GIR_Coverage, 4427,
     /* 388746 */     GIR_EraseRootFromParent_Done,
     /* 388747 */   // Label 7853: @388747
     /* 388747 */   GIM_Try, /*On fail goto*//*Label 7854*/ GIMT_Encode4(388856), // Rule ID 4534 //
     /* 388752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388756 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388762 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388764 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388768 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388772 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388775 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388779 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388783 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388787 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388789 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 388796 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 388796 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 388799 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 388803 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388808 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388813 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388818 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388823 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388829 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388836 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388839 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388842 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 388845 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388850 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388855 */     // GIR_Coverage, 4534,
     /* 388855 */     GIR_EraseRootFromParent_Done,
     /* 388856 */   // Label 7854: @388856
     /* 388856 */   GIM_Try, /*On fail goto*//*Label 7855*/ GIMT_Encode4(388965), // Rule ID 4535 //
     /* 388861 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388865 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 388871 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 388873 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388877 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388881 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388884 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388888 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388892 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 388896 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 388898 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 388905 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 388905 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 388908 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 388912 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 388917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 388922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 388927 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 388932 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 388938 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 388940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 388943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 388945 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 388948 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 388951 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 388954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 388959 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 388964 */     // GIR_Coverage, 4535,
     /* 388964 */     GIR_EraseRootFromParent_Done,
     /* 388965 */   // Label 7855: @388965
     /* 388965 */   GIM_Try, /*On fail goto*//*Label 7856*/ GIMT_Encode4(389070), // Rule ID 4432 //
     /* 388970 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 388974 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 388978 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 388982 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 388986 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 388989 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 388993 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 388997 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389001 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389003 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 389010 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 389010 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389013 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 389017 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389022 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389027 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 389032 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 389037 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389043 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389050 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389053 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389059 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389064 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389069 */     // GIR_Coverage, 4432,
     /* 389069 */     GIR_EraseRootFromParent_Done,
     /* 389070 */   // Label 7856: @389070
     /* 389070 */   GIM_Try, /*On fail goto*//*Label 7857*/ GIMT_Encode4(389175), // Rule ID 4434 //
     /* 389075 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389079 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389083 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389087 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389091 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389094 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389098 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389102 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389106 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389108 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 389115 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 389115 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389118 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 389122 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389127 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 389137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 389142 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389148 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389150 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389153 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389158 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389161 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389164 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389169 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389174 */     // GIR_Coverage, 4434,
     /* 389174 */     GIR_EraseRootFromParent_Done,
     /* 389175 */   // Label 7857: @389175
     /* 389175 */   GIM_Try, /*On fail goto*//*Label 7858*/ GIMT_Encode4(389280), // Rule ID 4540 //
     /* 389180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389188 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389192 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389196 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389199 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389203 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389207 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389211 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389213 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 389220 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 389220 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389223 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 389227 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389232 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389237 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 389242 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 389247 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389253 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389255 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389258 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389260 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389263 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389266 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389269 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389274 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389279 */     // GIR_Coverage, 4540,
     /* 389279 */     GIR_EraseRootFromParent_Done,
     /* 389280 */   // Label 7858: @389280
     /* 389280 */   GIM_Try, /*On fail goto*//*Label 7859*/ GIMT_Encode4(389385), // Rule ID 4542 //
     /* 389285 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389289 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389293 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389297 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389301 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389304 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389308 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389312 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389316 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389318 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 389325 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 389325 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389328 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 389332 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389342 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 389347 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 389352 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389358 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389360 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389363 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389365 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389368 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389371 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389374 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389379 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389384 */     // GIR_Coverage, 4542,
     /* 389384 */     GIR_EraseRootFromParent_Done,
     /* 389385 */   // Label 7859: @389385
     /* 389385 */   GIM_Try, /*On fail goto*//*Label 7860*/ GIMT_Encode4(389489), // Rule ID 4424 //
     /* 389390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389394 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 389400 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 389402 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389406 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389410 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389413 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389417 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389421 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389425 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389427 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 389434 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 389434 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389437 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 389441 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389446 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389451 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389456 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389462 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389464 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389467 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389469 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389472 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389475 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389478 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389483 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389488 */     // GIR_Coverage, 4424,
     /* 389488 */     GIR_EraseRootFromParent_Done,
     /* 389489 */   // Label 7860: @389489
     /* 389489 */   GIM_Try, /*On fail goto*//*Label 7861*/ GIMT_Encode4(389593), // Rule ID 4425 //
     /* 389494 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389498 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 389504 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 389506 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389510 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389514 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389517 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389521 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389525 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389529 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389531 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 389538 */     // (vector_insert:{ *:[v2i64] } immAllZerosV:{ *:[v2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 389538 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389541 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 389545 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389550 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389555 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389560 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389566 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389568 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389571 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389573 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389576 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389579 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389582 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389587 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389592 */     // GIR_Coverage, 4425,
     /* 389592 */     GIR_EraseRootFromParent_Done,
     /* 389593 */   // Label 7861: @389593
     /* 389593 */   GIM_Try, /*On fail goto*//*Label 7862*/ GIMT_Encode4(389697), // Rule ID 4532 //
     /* 389598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389602 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 389608 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 389610 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389614 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389618 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389621 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389625 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389629 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389633 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389635 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 389642 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 389642 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389645 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 389649 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389659 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389664 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389670 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389672 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389675 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389677 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389680 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389683 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389686 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389691 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389696 */     // GIR_Coverage, 4532,
     /* 389696 */     GIR_EraseRootFromParent_Done,
     /* 389697 */   // Label 7862: @389697
     /* 389697 */   GIM_Try, /*On fail goto*//*Label 7863*/ GIMT_Encode4(389801), // Rule ID 4533 //
     /* 389702 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389706 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 389712 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 389714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389722 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389725 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389729 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389733 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389737 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389739 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 389746 */     // (vector_insert:{ *:[v2f64] } immAllZerosV:{ *:[v2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 389746 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389749 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 389753 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389758 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389768 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389774 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389784 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389787 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389790 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389795 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389800 */     // GIR_Coverage, 4533,
     /* 389800 */     GIR_EraseRootFromParent_Done,
     /* 389801 */   // Label 7863: @389801
     /* 389801 */   GIM_Try, /*On fail goto*//*Label 7864*/ GIMT_Encode4(389901), // Rule ID 4428 //
     /* 389806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389814 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389818 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389822 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389825 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389829 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389833 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389837 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389839 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 389846 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 389846 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389849 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 389853 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389863 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389868 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389874 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389881 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389884 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389887 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389890 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389895 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 389900 */     // GIR_Coverage, 4428,
     /* 389900 */     GIR_EraseRootFromParent_Done,
     /* 389901 */   // Label 7864: @389901
     /* 389901 */   GIM_Try, /*On fail goto*//*Label 7865*/ GIMT_Encode4(390001), // Rule ID 4430 //
     /* 389906 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 389910 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 389914 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 389918 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 389922 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 389925 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 389929 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 389933 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 389937 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 389939 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 389946 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 389946 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 389949 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 389953 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 389958 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 389963 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 389968 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 389974 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 389976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 389979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 389981 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 389984 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 389987 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 389990 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 389995 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390000 */     // GIR_Coverage, 4430,
     /* 390000 */     GIR_EraseRootFromParent_Done,
     /* 390001 */   // Label 7865: @390001
     /* 390001 */   GIM_Try, /*On fail goto*//*Label 7866*/ GIMT_Encode4(390101), // Rule ID 4536 //
     /* 390006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 390010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 390014 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 390018 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 390022 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 390025 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 390029 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 390033 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 390037 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 390039 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 390046 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 390046 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 390049 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 390053 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390058 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 390063 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 390068 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 390074 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 390079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 390084 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390087 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 390090 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390095 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390100 */     // GIR_Coverage, 4536,
     /* 390100 */     GIR_EraseRootFromParent_Done,
     /* 390101 */   // Label 7866: @390101
     /* 390101 */   GIM_Try, /*On fail goto*//*Label 7867*/ GIMT_Encode4(390201), // Rule ID 4538 //
     /* 390106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 390110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 390114 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 390118 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 390122 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 390125 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 390129 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 390133 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 390137 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 390139 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 390146 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 390146 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 390149 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 390153 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390158 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 390163 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 390168 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 390174 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 390179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390181 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 390184 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390187 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 390190 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390195 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390200 */     // GIR_Coverage, 4538,
     /* 390200 */     GIR_EraseRootFromParent_Done,
     /* 390201 */   // Label 7867: @390201
     /* 390201 */   GIM_Try, /*On fail goto*//*Label 7868*/ GIMT_Encode4(390314), // Rule ID 6333 //
     /* 390206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 390210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 390214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 390218 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390222 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 390226 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 390230 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390235 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 390239 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390243 */     // MIs[3] Operand 1
     /* 390243 */     // No operand predicates
     /* 390243 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 390247 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390249 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), (DUPi64:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 390249 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 390252 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 390256 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390261 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 390265 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 390268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 390270 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 390273 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 390277 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390282 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 390287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390289 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 390295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 390298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390313 */     // GIR_Coverage, 6333,
     /* 390313 */     GIR_EraseRootFromParent_Done,
     /* 390314 */   // Label 7868: @390314
     /* 390314 */   GIM_Try, /*On fail goto*//*Label 7869*/ GIMT_Encode4(390427), // Rule ID 6373 //
     /* 390319 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 390323 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 390327 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 390331 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390335 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 390339 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 390343 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390348 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 390352 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390356 */     // MIs[3] Operand 1
     /* 390356 */     // No operand predicates
     /* 390356 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 390360 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390362 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (DUPi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 390362 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 390365 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 390369 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390374 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 390378 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 390381 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 390383 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 390386 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 390390 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390395 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 390397 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 390400 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390402 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390405 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 390408 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 390411 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390416 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390421 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390426 */     // GIR_Coverage, 6373,
     /* 390426 */     GIR_EraseRootFromParent_Done,
     /* 390427 */   // Label 7869: @390427
     /* 390427 */   GIM_Try, /*On fail goto*//*Label 7870*/ GIMT_Encode4(390505), // Rule ID 1972 //
     /* 390432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 390435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 390451 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390455 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390468 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 390472 */     // MIs[2] Operand 1
     /* 390472 */     // No operand predicates
     /* 390472 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390476 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390480 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 390484 */     // MIs[3] Operand 1
     /* 390484 */     // No operand predicates
     /* 390484 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390486 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 390486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390491 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 390493 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 390496 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 390500 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 390503 */     GIR_RootConstrainSelectedInstOperands,
     /* 390504 */     // GIR_Coverage, 1972,
     /* 390504 */     GIR_EraseRootFromParent_Done,
     /* 390505 */   // Label 7870: @390505
     /* 390505 */   GIM_Try, /*On fail goto*//*Label 7871*/ GIMT_Encode4(390600), // Rule ID 8090 //
     /* 390510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 390513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 390525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 390529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 390533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 390537 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 390540 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 390544 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 390551 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 390554 */     // MIs[2] Rn
     /* 390554 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 390558 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 390563 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390567 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390571 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 390575 */     // MIs[3] Operand 1
     /* 390575 */     // No operand predicates
     /* 390575 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390577 */     // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (bitconvert:{ *:[f64] } (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22258>>), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LDAP1:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 390577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
     /* 390580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390582 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 390584 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 390587 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 390591 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/4, /*MergeInsnID's*/0, 1, 2, 3,
     /* 390598 */     GIR_RootConstrainSelectedInstOperands,
     /* 390599 */     // GIR_Coverage, 8090,
     /* 390599 */     GIR_EraseRootFromParent_Done,
     /* 390600 */   // Label 7871: @390600
     /* 390600 */   GIM_Try, /*On fail goto*//*Label 7872*/ GIMT_Encode4(390689), // Rule ID 6330 //
     /* 390605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 390617 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390621 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390625 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390629 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 390633 */     // MIs[2] Operand 1
     /* 390633 */     // No operand predicates
     /* 390633 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390637 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390641 */     // MIs[3] Operand 1
     /* 390641 */     // No operand predicates
     /* 390641 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390643 */     // (vector_insert:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v2f64] } ZPR:{ *:[nxv2f64] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn)
     /* 390643 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 390646 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390650 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390655 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 390661 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390666 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390676 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 390678 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 390681 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390684 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 390687 */     GIR_RootConstrainSelectedInstOperands,
     /* 390688 */     // GIR_Coverage, 6330,
     /* 390688 */     GIR_EraseRootFromParent_Done,
     /* 390689 */   // Label 7872: @390689
     /* 390689 */   GIM_Try, /*On fail goto*//*Label 7873*/ GIMT_Encode4(390778), // Rule ID 6370 //
     /* 390694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390702 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 390706 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390710 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390714 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390718 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 390722 */     // MIs[2] Operand 1
     /* 390722 */     // No operand predicates
     /* 390722 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390726 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390730 */     // MIs[3] Operand 1
     /* 390730 */     // No operand predicates
     /* 390730 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390732 */     // (vector_insert:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$Immn)
     /* 390732 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 390735 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 390739 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390744 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 390750 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390755 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 390760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390765 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 390767 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 390770 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390773 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 390776 */     GIR_RootConstrainSelectedInstOperands,
     /* 390777 */     // GIR_Coverage, 6370,
     /* 390777 */     GIR_EraseRootFromParent_Done,
     /* 390778 */   // Label 7873: @390778
     /* 390778 */   GIM_Try, /*On fail goto*//*Label 7874*/ GIMT_Encode4(390845), // Rule ID 6332 //
     /* 390783 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390787 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390791 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390795 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 390799 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390803 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390808 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390812 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390816 */     // MIs[2] Operand 1
     /* 390816 */     // No operand predicates
     /* 390816 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390820 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390824 */     // MIs[3] Operand 1
     /* 390824 */     // No operand predicates
     /* 390824 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390826 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 390826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390831 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 390833 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 390836 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 390840 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 390843 */     GIR_RootConstrainSelectedInstOperands,
     /* 390844 */     // GIR_Coverage, 6332,
     /* 390844 */     GIR_EraseRootFromParent_Done,
     /* 390845 */   // Label 7874: @390845
     /* 390845 */   GIM_Try, /*On fail goto*//*Label 7875*/ GIMT_Encode4(390943), // Rule ID 6334 //
     /* 390850 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 390866 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390870 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390883 */     // MIs[2] Operand 1
     /* 390883 */     // No operand predicates
     /* 390883 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390887 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390891 */     // MIs[3] Operand 1
     /* 390891 */     // No operand predicates
     /* 390891 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390893 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (vector_extract:{ *:[f64] } V64:{ *:[v1f64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v2f64] } 0:{ *:[i64] }, V64:{ *:[v1f64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 390893 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 390896 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 390900 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 390905 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 390908 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 390912 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 390915 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390920 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 390925 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390928 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390930 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 390932 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 390935 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 390938 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 390941 */     GIR_RootConstrainSelectedInstOperands,
     /* 390942 */     // GIR_Coverage, 6334,
     /* 390942 */     GIR_EraseRootFromParent_Done,
     /* 390943 */   // Label 7875: @390943
     /* 390943 */   GIM_Try, /*On fail goto*//*Label 7876*/ GIMT_Encode4(391010), // Rule ID 6372 //
     /* 390948 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390952 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 390956 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 390960 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 390964 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 390968 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 390973 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 390977 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390981 */     // MIs[2] Operand 1
     /* 390981 */     // No operand predicates
     /* 390981 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 390985 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 390989 */     // MIs[3] Operand 1
     /* 390989 */     // No operand predicates
     /* 390989 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 390991 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 390991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 390994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 390996 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 390998 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 391001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 391005 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 391008 */     GIR_RootConstrainSelectedInstOperands,
     /* 391009 */     // GIR_Coverage, 6372,
     /* 391009 */     GIR_EraseRootFromParent_Done,
     /* 391010 */   // Label 7876: @391010
     /* 391010 */   GIM_Try, /*On fail goto*//*Label 7877*/ GIMT_Encode4(391108), // Rule ID 6374 //
     /* 391015 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391019 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391023 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 391027 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 391031 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 391035 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391040 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 391044 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391048 */     // MIs[2] Operand 1
     /* 391048 */     // No operand predicates
     /* 391048 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 391052 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391056 */     // MIs[3] Operand 1
     /* 391056 */     // No operand predicates
     /* 391056 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 391058 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (vector_extract:{ *:[i64] } V64:{ *:[v1i64] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, V64:{ *:[v1i64] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 391058 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 391061 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 391065 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391070 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 391073 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 391077 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 391080 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391085 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 391093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391095 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 391097 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 391100 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391103 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 391106 */     GIR_RootConstrainSelectedInstOperands,
     /* 391107 */     // GIR_Coverage, 6374,
     /* 391107 */     GIR_EraseRootFromParent_Done,
     /* 391108 */   // Label 7877: @391108
     /* 391108 */   GIM_Try, /*On fail goto*//*Label 7878*/ GIMT_Encode4(391174), // Rule ID 6278 //
     /* 391113 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 391117 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 391121 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391125 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 391129 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391131 */     // (vector_insert:{ *:[v2i64] } (undef:{ *:[v2i64] }), GPR64:{ *:[i64] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), GPR64:{ *:[i64] }:$Rn, dsub:{ *:[i32] })
     /* 391131 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 391134 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 391138 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391143 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391145 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 391148 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391150 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391153 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 391155 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 391158 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391163 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391168 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391173 */     // GIR_Coverage, 6278,
     /* 391173 */     GIR_EraseRootFromParent_Done,
     /* 391174 */   // Label 7878: @391174
     /* 391174 */   GIM_Try, /*On fail goto*//*Label 7879*/ GIMT_Encode4(391240), // Rule ID 6292 //
     /* 391179 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 391183 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 391187 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391191 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 391195 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391197 */     // (vector_insert:{ *:[v2f64] } (undef:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] })
     /* 391197 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 391200 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 391204 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391209 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 391214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391216 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391219 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 391221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 391224 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391229 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391234 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391239 */     // GIR_Coverage, 6292,
     /* 391239 */     GIR_EraseRootFromParent_Done,
     /* 391240 */   // Label 7879: @391240
     /* 391240 */   GIM_Try, /*On fail goto*//*Label 7880*/ GIMT_Encode4(391309), // Rule ID 7079 //
     /* 391245 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 391257 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 391260 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 391264 */     // MIs[1] Rn
     /* 391264 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 391268 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 391273 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 391277 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391281 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391285 */     // MIs[2] Operand 1
     /* 391285 */     // No operand predicates
     /* 391285 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391287 */     // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LD1i64:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 391287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
     /* 391290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391292 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 391294 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 391297 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 391301 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 391307 */     GIR_RootConstrainSelectedInstOperands,
     /* 391308 */     // GIR_Coverage, 7079,
     /* 391308 */     GIR_EraseRootFromParent_Done,
     /* 391309 */   // Label 7880: @391309
     /* 391309 */   GIM_Try, /*On fail goto*//*Label 7881*/ GIMT_Encode4(391378), // Rule ID 7080 //
     /* 391314 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391318 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391322 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 391326 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 391329 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 391333 */     // MIs[1] Rn
     /* 391333 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 391337 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 391342 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 391346 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391350 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391354 */     // MIs[2] Operand 1
     /* 391354 */     // No operand predicates
     /* 391354 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391356 */     // (vector_insert:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LD1i64:{ *:[v2f64] } VecListOne128:{ *:[v2f64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 391356 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i64),
     /* 391359 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391361 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 391363 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 391366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 391370 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 391376 */     GIR_RootConstrainSelectedInstOperands,
     /* 391377 */     // GIR_Coverage, 7080,
     /* 391377 */     GIR_EraseRootFromParent_Done,
     /* 391378 */   // Label 7881: @391378
     /* 391378 */   GIM_Try, /*On fail goto*//*Label 7882*/ GIMT_Encode4(391460), // Rule ID 8089 //
     /* 391383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasRCPC3),
     /* 391386 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 391398 */     GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Unordered,
     /* 391401 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 391405 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 391412 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::Acquire,
     /* 391415 */     // MIs[1] Rn
     /* 391415 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 391419 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 391424 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 391428 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391432 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391436 */     // MIs[2] Operand 1
     /* 391436 */     // No operand predicates
     /* 391436 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391438 */     // (vector_insert:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (atomic_load:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_atomic_load_nonext>><<P:Predicate_atomic_load_nonext_64>><<P:Predicate_anonymous_22258>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (LDAP1:{ *:[v2i64] } VecListOne128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 391438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LDAP1),
     /* 391441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391443 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 391445 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 391448 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 391452 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 391458 */     GIR_RootConstrainSelectedInstOperands,
     /* 391459 */     // GIR_Coverage, 8089,
     /* 391459 */     GIR_EraseRootFromParent_Done,
     /* 391460 */   // Label 7882: @391460
     /* 391460 */   GIM_Try, /*On fail goto*//*Label 7883*/ GIMT_Encode4(391512), // Rule ID 6299 //
     /* 391465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseWzrToVecMove),
     /* 391468 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391472 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 391476 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 391480 */     // MIs[1] Operand 1
     /* 391480 */     // No operand predicates
     /* 391480 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 391484 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391488 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391492 */     // MIs[2] Operand 1
     /* 391492 */     // No operand predicates
     /* 391492 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391494 */     // (vector_insert:{ *:[v2f64] } v2f64:{ *:[v2f64] }:$Rn, (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (INSvi64gpr:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, XZR:{ *:[i64] })
     /* 391494 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
     /* 391497 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391499 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391501 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 391504 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 391510 */     GIR_RootConstrainSelectedInstOperands,
     /* 391511 */     // GIR_Coverage, 6299,
     /* 391511 */     GIR_EraseRootFromParent_Done,
     /* 391512 */   // Label 7883: @391512
     /* 391512 */   GIM_Try, /*On fail goto*//*Label 7884*/ GIMT_Encode4(391613), // Rule ID 6379 //
     /* 391517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 391521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 391525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 391529 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391534 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 391538 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391542 */     // MIs[2] Operand 1
     /* 391542 */     // No operand predicates
     /* 391542 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391544 */     // (vector_insert:{ *:[v2i64] } v2i64:{ *:[v2i64] }:$src, (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR64:{ *:[f64] }:$Sn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 391544 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 391547 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 391551 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391556 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 391558 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 391561 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 391565 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391570 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 391573 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 391577 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 391580 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391585 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391590 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 391598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391600 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 391602 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
     /* 391605 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391608 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 391611 */     GIR_RootConstrainSelectedInstOperands,
     /* 391612 */     // GIR_Coverage, 6379,
     /* 391612 */     GIR_EraseRootFromParent_Done,
     /* 391613 */   // Label 7884: @391613
     /* 391613 */   GIM_Try, /*On fail goto*//*Label 7885*/ GIMT_Encode4(391657), // Rule ID 1968 //
     /* 391618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 391621 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391625 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 391629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 391633 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391637 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391641 */     // MIs[1] Operand 1
     /* 391641 */     // No operand predicates
     /* 391641 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391643 */     // (vector_insert:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, GPR64:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (INSvi64gpr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, (imm:{ *:[i64] }):$idx, GPR64:{ *:[i64] }:$Rn)
     /* 391643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64gpr),
     /* 391646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391648 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 391650 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 391653 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 391655 */     GIR_RootConstrainSelectedInstOperands,
     /* 391656 */     // GIR_Coverage, 1968,
     /* 391656 */     GIR_EraseRootFromParent_Done,
     /* 391657 */   // Label 7885: @391657
     /* 391657 */   GIM_Try, /*On fail goto*//*Label 7886*/ GIMT_Encode4(391753), // Rule ID 6303 //
     /* 391662 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391670 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 391674 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 391678 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 391682 */     // MIs[1] Operand 1
     /* 391682 */     // No operand predicates
     /* 391682 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 391684 */     // (vector_insert:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (INSvi64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm, (INSERT_SUBREG:{ *:[v2f64] } (IMPLICIT_DEF:{ *:[v2f64] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 391684 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
     /* 391687 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 391691 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391696 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 391698 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 391701 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 391705 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391710 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 391713 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 391717 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 391720 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391725 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 391730 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi64lane),
     /* 391738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391740 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 391742 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 391745 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391748 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 391751 */     GIR_RootConstrainSelectedInstOperands,
     /* 391752 */     // GIR_Coverage, 6303,
     /* 391752 */     GIR_EraseRootFromParent_Done,
     /* 391753 */   // Label 7886: @391753
     /* 391753 */   GIM_Reject,
     /* 391754 */ // Label 7851: @391754
     /* 391754 */ GIM_Reject,
     /* 391755 */ // Label 7799: @391755
     /* 391755 */ GIM_Try, /*On fail goto*//*Label 7887*/ GIMT_Encode4(395397),
     /* 391760 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 391763 */   GIM_Try, /*On fail goto*//*Label 7888*/ GIMT_Encode4(391889), // Rule ID 4366 //
     /* 391768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 391771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 391774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391778 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 391782 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 391788 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 391790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 391794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 391798 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 391801 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 391805 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 391812 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 391816 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 391820 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391822 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 391829 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 391829 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 391832 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 391836 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 391846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 391851 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 391856 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 391862 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391864 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 391867 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 391872 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 391875 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 391878 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391883 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 391888 */     // GIR_Coverage, 4366,
     /* 391888 */     GIR_EraseRootFromParent_Done,
     /* 391889 */   // Label 7888: @391889
     /* 391889 */   GIM_Try, /*On fail goto*//*Label 7889*/ GIMT_Encode4(392015), // Rule ID 4367 //
     /* 391894 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 391897 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 391900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 391904 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 391908 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 391914 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 391916 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 391920 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 391924 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 391927 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 391931 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 391938 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 391942 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 391946 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 391948 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 391955 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 391955 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 391958 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 391962 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 391967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 391972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 391977 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 391982 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 391988 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 391990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 391993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 391995 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 391998 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392004 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392009 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392014 */     // GIR_Coverage, 4367,
     /* 392014 */     GIR_EraseRootFromParent_Done,
     /* 392015 */   // Label 7889: @392015
     /* 392015 */   GIM_Try, /*On fail goto*//*Label 7890*/ GIMT_Encode4(392134), // Rule ID 4474 //
     /* 392020 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 392023 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392026 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392030 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392034 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 392040 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 392042 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392046 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392050 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392053 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392057 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392061 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392065 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392067 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 392074 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392074 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392077 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 392081 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392091 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392096 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392101 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392107 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392109 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392112 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392114 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392117 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392120 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392123 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392128 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392133 */     // GIR_Coverage, 4474,
     /* 392133 */     GIR_EraseRootFromParent_Done,
     /* 392134 */   // Label 7890: @392134
     /* 392134 */   GIM_Try, /*On fail goto*//*Label 7891*/ GIMT_Encode4(392253), // Rule ID 4475 //
     /* 392139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 392142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392149 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392153 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 392159 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 392161 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392165 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392169 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392172 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392176 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392180 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392184 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392186 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 392193 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392193 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392196 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 392200 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392215 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392220 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392226 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392236 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392239 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392242 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392247 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392252 */     // GIR_Coverage, 4475,
     /* 392252 */     GIR_EraseRootFromParent_Done,
     /* 392253 */   // Label 7891: @392253
     /* 392253 */   GIM_Try, /*On fail goto*//*Label 7892*/ GIMT_Encode4(392375), // Rule ID 4372 //
     /* 392258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 392261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 392276 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392280 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392284 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392287 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392291 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 392298 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392302 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392306 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392308 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 392315 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392315 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392318 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 392322 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392332 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392337 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392342 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392348 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392350 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392353 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392355 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392358 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392361 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392364 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392369 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392374 */     // GIR_Coverage, 4372,
     /* 392374 */     GIR_EraseRootFromParent_Done,
     /* 392375 */   // Label 7892: @392375
     /* 392375 */   GIM_Try, /*On fail goto*//*Label 7893*/ GIMT_Encode4(392497), // Rule ID 4374 //
     /* 392380 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 392383 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392386 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392390 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392394 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 392398 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392402 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392406 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392409 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392413 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 392420 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392424 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392428 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392430 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 392437 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392437 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392440 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 392444 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392449 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392454 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392459 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392464 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392470 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392477 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392480 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392483 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392486 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392491 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392496 */     // GIR_Coverage, 4374,
     /* 392496 */     GIR_EraseRootFromParent_Done,
     /* 392497 */   // Label 7893: @392497
     /* 392497 */   GIM_Try, /*On fail goto*//*Label 7894*/ GIMT_Encode4(392612), // Rule ID 4480 //
     /* 392502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 392505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392512 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392516 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 392520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392528 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392531 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392535 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392539 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392543 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392545 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 392552 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392552 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392555 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 392559 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392569 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392579 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392585 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392592 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392595 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392598 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392601 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392606 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392611 */     // GIR_Coverage, 4480,
     /* 392611 */     GIR_EraseRootFromParent_Done,
     /* 392612 */   // Label 7894: @392612
     /* 392612 */   GIM_Try, /*On fail goto*//*Label 7895*/ GIMT_Encode4(392727), // Rule ID 4482 //
     /* 392617 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 392620 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392623 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392627 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392631 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 392635 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392639 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392643 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392646 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392650 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392654 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392658 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392660 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 392667 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 392667 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392670 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 392674 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392684 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 392689 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 392694 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392700 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392702 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392705 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392707 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392710 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392713 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392716 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392721 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392726 */     // GIR_Coverage, 4482,
     /* 392726 */     GIR_EraseRootFromParent_Done,
     /* 392727 */   // Label 7895: @392727
     /* 392727 */   GIM_Try, /*On fail goto*//*Label 7896*/ GIMT_Encode4(392848), // Rule ID 4364 //
     /* 392732 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 392735 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392738 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392742 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392746 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 392752 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 392754 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392758 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392762 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392765 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392769 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 392776 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392780 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392784 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392786 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 392793 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 392793 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392796 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 392800 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 392815 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392821 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392837 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392842 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392847 */     // GIR_Coverage, 4364,
     /* 392847 */     GIR_EraseRootFromParent_Done,
     /* 392848 */   // Label 7896: @392848
     /* 392848 */   GIM_Try, /*On fail goto*//*Label 7897*/ GIMT_Encode4(392969), // Rule ID 4365 //
     /* 392853 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 392856 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392867 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 392873 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 392875 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 392879 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 392883 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 392886 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 392890 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 392897 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 392901 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 392905 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 392907 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 392914 */     // (vector_insert:{ *:[v4i16] } immAllZerosV:{ *:[v4i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 392914 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 392917 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 392921 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 392926 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 392931 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 392936 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 392942 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 392944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 392947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 392949 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 392952 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 392955 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 392958 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392963 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 392968 */     // GIR_Coverage, 4365,
     /* 392968 */     GIR_EraseRootFromParent_Done,
     /* 392969 */   // Label 7897: @392969
     /* 392969 */   GIM_Try, /*On fail goto*//*Label 7898*/ GIMT_Encode4(393083), // Rule ID 4472 //
     /* 392974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 392977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 392980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 392984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 392988 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 392994 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 392996 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393000 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393004 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393007 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393011 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393015 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393019 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393021 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 393028 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 393028 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393031 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 393035 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393050 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393063 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393066 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393069 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393077 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393082 */     // GIR_Coverage, 4472,
     /* 393082 */     GIR_EraseRootFromParent_Done,
     /* 393083 */   // Label 7898: @393083
     /* 393083 */   GIM_Try, /*On fail goto*//*Label 7899*/ GIMT_Encode4(393197), // Rule ID 4473 //
     /* 393088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 393091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393102 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 393108 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 393110 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393114 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393118 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393121 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393125 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393129 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393135 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 393142 */     // (vector_insert:{ *:[v4f16] } immAllZerosV:{ *:[v4f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 393142 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393145 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 393149 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393164 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393170 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393180 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393186 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393191 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393196 */     // GIR_Coverage, 4473,
     /* 393196 */     GIR_EraseRootFromParent_Done,
     /* 393197 */   // Label 7899: @393197
     /* 393197 */   GIM_Try, /*On fail goto*//*Label 7900*/ GIMT_Encode4(393314), // Rule ID 4368 //
     /* 393202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 393205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393212 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 393220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393228 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393231 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393235 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 393242 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393246 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393250 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393252 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 393259 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 393259 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393262 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 393266 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393281 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393287 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393289 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393292 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393294 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393297 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393300 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393313 */     // GIR_Coverage, 4368,
     /* 393313 */     GIR_EraseRootFromParent_Done,
     /* 393314 */   // Label 7900: @393314
     /* 393314 */   GIM_Try, /*On fail goto*//*Label 7901*/ GIMT_Encode4(393431), // Rule ID 4370 //
     /* 393319 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 393322 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393325 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393329 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393333 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 393337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393345 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393348 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393352 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 393359 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393363 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393367 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393369 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 393376 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 393376 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393379 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 393383 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393388 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393398 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393404 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393414 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393417 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393420 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393425 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393430 */     // GIR_Coverage, 4370,
     /* 393430 */     GIR_EraseRootFromParent_Done,
     /* 393431 */   // Label 7901: @393431
     /* 393431 */   GIM_Try, /*On fail goto*//*Label 7902*/ GIMT_Encode4(393541), // Rule ID 4476 //
     /* 393436 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 393439 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393442 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393446 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393450 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 393454 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393458 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393462 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393465 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393469 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393473 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393477 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393479 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 393486 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 393486 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393489 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 393493 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393508 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393514 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393521 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393524 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393530 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393535 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393540 */     // GIR_Coverage, 4476,
     /* 393540 */     GIR_EraseRootFromParent_Done,
     /* 393541 */   // Label 7902: @393541
     /* 393541 */   GIM_Try, /*On fail goto*//*Label 7903*/ GIMT_Encode4(393651), // Rule ID 4478 //
     /* 393546 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 393549 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393556 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393560 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 393564 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393568 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393572 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393575 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393579 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 393583 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393587 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393589 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 393596 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 393596 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 393599 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 393603 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393608 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 393613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 393618 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393624 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393626 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393629 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393631 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 393634 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 393637 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 393640 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393645 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 393650 */     // GIR_Coverage, 4478,
     /* 393650 */     GIR_EraseRootFromParent_Done,
     /* 393651 */   // Label 7903: @393651
     /* 393651 */   GIM_Try, /*On fail goto*//*Label 7904*/ GIMT_Encode4(393781), // Rule ID 7092 //
     /* 393656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 393659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 393662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 393673 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 393677 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 393681 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 393685 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 393688 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 393692 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 393699 */     // MIs[2] Rn
     /* 393699 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/64,
     /* 393703 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 393708 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 393712 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 393714 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (LD1i8:{ *:[f128] } (IMPLICIT_DEF:{ *:[v16i8] }), 0:{ *:[i64] }, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 393714 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 393717 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 393721 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393726 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 393728 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393731 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 393735 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393740 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393743 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 393746 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 393750 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 393756 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 393761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393763 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 393770 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393775 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393780 */     // GIR_Coverage, 7092,
     /* 393780 */     GIR_EraseRootFromParent_Done,
     /* 393781 */   // Label 7904: @393781
     /* 393781 */   GIM_Try, /*On fail goto*//*Label 7905*/ GIMT_Encode4(393921), // Rule ID 6319 //
     /* 393786 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 393789 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393792 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393796 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393800 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 393804 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393808 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 393812 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393816 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393821 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393825 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393829 */     // MIs[2] Operand 1
     /* 393829 */     // No operand predicates
     /* 393829 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 393833 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393837 */     // MIs[3] Operand 1
     /* 393837 */     // No operand predicates
     /* 393837 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 393839 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 393839 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 393842 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393846 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393851 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 393854 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 393858 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 393861 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393866 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393871 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 393874 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 393878 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393883 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 393886 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 393889 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 393893 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 393896 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 393898 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 393901 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 393903 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 393910 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393915 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 393920 */     // GIR_Coverage, 6319,
     /* 393920 */     GIR_EraseRootFromParent_Done,
     /* 393921 */   // Label 7905: @393921
     /* 393921 */   GIM_Try, /*On fail goto*//*Label 7906*/ GIMT_Encode4(394092), // Rule ID 6320 //
     /* 393926 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 393929 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 393932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393936 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393940 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 393944 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 393948 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 393952 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 393956 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 393961 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 393965 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393969 */     // MIs[2] Operand 1
     /* 393969 */     // No operand predicates
     /* 393969 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 393973 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 393977 */     // MIs[3] Operand 1
     /* 393977 */     // No operand predicates
     /* 393977 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 393979 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 393979 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 393982 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 393986 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 393991 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 393994 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 393998 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 394001 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394006 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394011 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 394014 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394018 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394023 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 394026 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 394030 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 394033 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394038 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394043 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394046 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 394050 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394055 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394058 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 394061 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 394064 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 394067 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394074 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 394081 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394086 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394091 */     // GIR_Coverage, 6320,
     /* 394091 */     GIR_EraseRootFromParent_Done,
     /* 394092 */   // Label 7906: @394092
     /* 394092 */   GIM_Try, /*On fail goto*//*Label 7907*/ GIMT_Encode4(394232), // Rule ID 6359 //
     /* 394097 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 394100 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394103 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394107 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 394115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394119 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 394123 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394132 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394136 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394140 */     // MIs[2] Operand 1
     /* 394140 */     // No operand predicates
     /* 394140 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 394144 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394148 */     // MIs[3] Operand 1
     /* 394148 */     // No operand predicates
     /* 394148 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 394150 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 394150 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 394153 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394157 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394162 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 394165 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 394169 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 394172 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394177 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394182 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394185 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 394189 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394194 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 394200 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 394204 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 394207 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394214 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 394221 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394226 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394231 */     // GIR_Coverage, 6359,
     /* 394231 */     GIR_EraseRootFromParent_Done,
     /* 394232 */   // Label 7907: @394232
     /* 394232 */   GIM_Try, /*On fail goto*//*Label 7908*/ GIMT_Encode4(394403), // Rule ID 6360 //
     /* 394237 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 394240 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394247 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394251 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 394255 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 394259 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 394263 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 394267 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394272 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 394276 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394280 */     // MIs[2] Operand 1
     /* 394280 */     // No operand predicates
     /* 394280 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 394284 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394288 */     // MIs[3] Operand 1
     /* 394288 */     // No operand predicates
     /* 394288 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 394290 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 394290 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 394293 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394297 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394302 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 394305 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 394309 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 394312 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394317 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394322 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 394325 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394329 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394334 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 394337 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 394341 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 394344 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394349 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394354 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394357 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 394361 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394366 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394369 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 394372 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 394375 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 394378 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394380 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394383 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394385 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 394392 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394397 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394402 */     // GIR_Coverage, 6360,
     /* 394402 */     GIR_EraseRootFromParent_Done,
     /* 394403 */   // Label 7908: @394403
     /* 394403 */   GIM_Try, /*On fail goto*//*Label 7909*/ GIMT_Encode4(394482), // Rule ID 6272 //
     /* 394408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 394411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394418 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394422 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 394426 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 394430 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 394434 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394436 */     // (vector_insert:{ *:[v4i16] } (undef:{ *:[v4i16] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i16] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 394436 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 394439 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394443 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394448 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 394452 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 394457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 394465 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 394471 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 394481 */     // GIR_Coverage, 6272,
     /* 394481 */     GIR_EraseRootFromParent_Done,
     /* 394482 */   // Label 7909: @394482
     /* 394482 */   GIM_Try, /*On fail goto*//*Label 7910*/ GIMT_Encode4(394558), // Rule ID 6280 //
     /* 394487 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 394490 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394493 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394497 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394501 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 394505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394509 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 394513 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394515 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 394515 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
     /* 394518 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 394522 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394527 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 394532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394534 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 394539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 394542 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394547 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394552 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394557 */     // GIR_Coverage, 6280,
     /* 394557 */     GIR_EraseRootFromParent_Done,
     /* 394558 */   // Label 7910: @394558
     /* 394558 */   GIM_Try, /*On fail goto*//*Label 7911*/ GIMT_Encode4(394634), // Rule ID 6284 //
     /* 394563 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 394566 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394573 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 394577 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 394581 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394585 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 394589 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 394591 */     // (vector_insert:{ *:[v4f16] } (undef:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 394591 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
     /* 394594 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 394598 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394603 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 394608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394610 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 394613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 394615 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 394618 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 394633 */     // GIR_Coverage, 6284,
     /* 394633 */     GIR_EraseRootFromParent_Done,
     /* 394634 */   // Label 7911: @394634
     /* 394634 */   GIM_Try, /*On fail goto*//*Label 7912*/ GIMT_Encode4(394782), // Rule ID 6296 //
     /* 394639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseWzrToVecMove),
     /* 394642 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 394645 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394648 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394652 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394656 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 394660 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 394664 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 394668 */     // MIs[1] Operand 1
     /* 394668 */     // No operand predicates
     /* 394668 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 394672 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394676 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 394680 */     // MIs[2] Operand 1
     /* 394680 */     // No operand predicates
     /* 394680 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394682 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] }), dsub:{ *:[i32] })
     /* 394682 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 394685 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 394689 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394694 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 394696 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 394699 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 394703 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394708 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 394711 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 394715 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 394718 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394723 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394728 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394733 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394736 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 394740 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394745 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394748 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // imm
     /* 394751 */     GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 394757 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394764 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 394771 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394776 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394781 */     // GIR_Coverage, 6296,
     /* 394781 */     GIR_EraseRootFromParent_Done,
     /* 394782 */   // Label 7912: @394782
     /* 394782 */   GIM_Try, /*On fail goto*//*Label 7913*/ GIMT_Encode4(394931), // Rule ID 7096 //
     /* 394787 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 394790 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394793 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394797 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394801 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 394805 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 394809 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 394812 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 394816 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 394823 */     // MIs[1] Rn
     /* 394823 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 394827 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 394832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 394836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394840 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 394844 */     // MIs[2] Operand 1
     /* 394844 */     // No operand predicates
     /* 394844 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394846 */     // (vector_insert:{ *:[v4i16] } VecListOne64:{ *:[v4i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4i16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 394846 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 394849 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394853 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394858 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 394861 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 394865 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 394868 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394873 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394878 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 394881 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 394885 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 394890 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 394893 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 394896 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 394900 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 394906 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 394908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 394911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 394913 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 394920 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394925 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 394930 */     // GIR_Coverage, 7096,
     /* 394930 */     GIR_EraseRootFromParent_Done,
     /* 394931 */   // Label 7913: @394931
     /* 394931 */   GIM_Try, /*On fail goto*//*Label 7914*/ GIMT_Encode4(395073), // Rule ID 7099 //
     /* 394936 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 394939 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 394942 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394946 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 394950 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 394954 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 394958 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 394961 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 394965 */     // MIs[1] Rn
     /* 394965 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 394969 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 394974 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 394978 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 394982 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 394986 */     // MIs[2] Operand 1
     /* 394986 */     // No operand predicates
     /* 394986 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 394988 */     // (vector_insert:{ *:[v4f16] } VecListOne64:{ *:[v4f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (LD1i16:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v4f16] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 394988 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 394991 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 394995 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395000 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 395003 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 395007 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 395010 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395015 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395020 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 395023 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 395027 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395032 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 395035 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 395038 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 395042 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395048 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395050 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 395053 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395055 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 395062 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395067 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395072 */     // GIR_Coverage, 7099,
     /* 395072 */     GIR_EraseRootFromParent_Done,
     /* 395073 */   // Label 7914: @395073
     /* 395073 */   GIM_Try, /*On fail goto*//*Label 7915*/ GIMT_Encode4(395261), // Rule ID 6294 //
     /* 395078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 395081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 395084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395088 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 395096 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 395100 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 395104 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 395108 */     // MIs[1] Operand 1
     /* 395108 */     // No operand predicates
     /* 395108 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 395110 */     // (vector_insert:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (INSvi16lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 395110 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v8s16,
     /* 395113 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 395117 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395122 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 395124 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v8s16,
     /* 395127 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 395131 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395136 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 395139 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 395143 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/9,
     /* 395146 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395151 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395156 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 395161 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 395164 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 395168 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395173 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 395175 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 395178 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 395182 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395187 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 395190 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 395194 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 395197 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395202 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395207 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 395215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 395219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395224 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 395227 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 395230 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 395233 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 395236 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 395241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395243 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 395250 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395255 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395260 */     // GIR_Coverage, 6294,
     /* 395260 */     GIR_EraseRootFromParent_Done,
     /* 395261 */   // Label 7915: @395261
     /* 395261 */   GIM_Try, /*On fail goto*//*Label 7916*/ GIMT_Encode4(395396), // Rule ID 6305 //
     /* 395266 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 395269 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 395272 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395276 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395280 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 395284 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 395288 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 395292 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 395296 */     // MIs[1] Operand 1
     /* 395296 */     // No operand predicates
     /* 395296 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 395298 */     // (vector_insert:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (INSvi16gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 395298 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v8s16,
     /* 395301 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 395305 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395310 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 395312 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 395315 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 395319 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395324 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 395327 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 395331 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 395334 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395339 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395344 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395349 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 395352 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 395356 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395361 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 395364 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 395367 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 395371 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 395376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395378 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 395385 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 395390 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395395 */     // GIR_Coverage, 6305,
     /* 395395 */     GIR_EraseRootFromParent_Done,
     /* 395396 */   // Label 7916: @395396
     /* 395396 */   GIM_Reject,
     /* 395397 */ // Label 7887: @395397
     /* 395397 */ GIM_Reject,
     /* 395398 */ // Label 7800: @395398
     /* 395398 */ GIM_Try, /*On fail goto*//*Label 7917*/ GIMT_Encode4(398468),
     /* 395403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 395406 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 395409 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 395412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395416 */   GIM_Try, /*On fail goto*//*Label 7918*/ GIMT_Encode4(395525), // Rule ID 4390 //
     /* 395421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395425 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 395431 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 395433 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395437 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395441 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395444 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395448 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395452 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395456 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395458 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 395465 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 395465 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395468 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 395472 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395477 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 395482 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 395487 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 395492 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395498 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 395503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395505 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 395508 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395511 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 395514 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395519 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 395524 */     // GIR_Coverage, 4390,
     /* 395524 */     GIR_EraseRootFromParent_Done,
     /* 395525 */   // Label 7918: @395525
     /* 395525 */   GIM_Try, /*On fail goto*//*Label 7919*/ GIMT_Encode4(395634), // Rule ID 4391 //
     /* 395530 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395534 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 395540 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 395542 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395546 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395550 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395553 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395557 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395561 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395565 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395567 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 395574 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 395574 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395577 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 395581 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395586 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 395591 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 395596 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 395601 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395607 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 395612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395614 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 395617 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 395623 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395628 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 395633 */     // GIR_Coverage, 4391,
     /* 395633 */     GIR_EraseRootFromParent_Done,
     /* 395634 */   // Label 7919: @395634
     /* 395634 */   GIM_Try, /*On fail goto*//*Label 7920*/ GIMT_Encode4(395743), // Rule ID 4498 //
     /* 395639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395643 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 395649 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 395651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395659 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395662 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395666 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395670 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395674 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395676 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 395683 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 395683 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395686 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 395690 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395695 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 395700 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 395705 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 395710 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395716 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395718 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 395721 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395723 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 395726 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395729 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 395732 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395737 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 395742 */     // GIR_Coverage, 4498,
     /* 395742 */     GIR_EraseRootFromParent_Done,
     /* 395743 */   // Label 7920: @395743
     /* 395743 */   GIM_Try, /*On fail goto*//*Label 7921*/ GIMT_Encode4(395852), // Rule ID 4499 //
     /* 395748 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395752 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 395758 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 395760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395768 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395771 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395775 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395779 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395783 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395785 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 395792 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 395792 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395795 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 395799 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395804 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 395809 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 395814 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 395819 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395825 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395827 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 395830 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395832 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 395835 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395838 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 395841 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395846 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 395851 */     // GIR_Coverage, 4499,
     /* 395851 */     GIR_EraseRootFromParent_Done,
     /* 395852 */   // Label 7921: @395852
     /* 395852 */   GIM_Try, /*On fail goto*//*Label 7922*/ GIMT_Encode4(395957), // Rule ID 4396 //
     /* 395857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 395865 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395869 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395873 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395876 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395880 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395884 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395888 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395890 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 395897 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 395897 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 395900 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 395904 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 395909 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 395914 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 395919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 395924 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 395930 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 395932 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 395935 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 395937 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 395940 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 395943 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 395946 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 395951 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 395956 */     // GIR_Coverage, 4396,
     /* 395956 */     GIR_EraseRootFromParent_Done,
     /* 395957 */   // Label 7922: @395957
     /* 395957 */   GIM_Try, /*On fail goto*//*Label 7923*/ GIMT_Encode4(396062), // Rule ID 4398 //
     /* 395962 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 395966 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 395970 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 395974 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 395978 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 395981 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 395985 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 395989 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 395993 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 395995 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 396002 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 396002 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396005 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 396009 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396014 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396019 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 396024 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 396029 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396035 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396042 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396045 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396048 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396051 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396056 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396061 */     // GIR_Coverage, 4398,
     /* 396061 */     GIR_EraseRootFromParent_Done,
     /* 396062 */   // Label 7923: @396062
     /* 396062 */   GIM_Try, /*On fail goto*//*Label 7924*/ GIMT_Encode4(396167), // Rule ID 4504 //
     /* 396067 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396071 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 396075 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396079 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396083 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396086 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396090 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396094 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396098 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396100 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 396107 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 396107 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396110 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 396114 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 396129 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 396134 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396140 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396142 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396145 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396147 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396150 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396153 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396156 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396161 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396166 */     // GIR_Coverage, 4504,
     /* 396166 */     GIR_EraseRootFromParent_Done,
     /* 396167 */   // Label 7924: @396167
     /* 396167 */   GIM_Try, /*On fail goto*//*Label 7925*/ GIMT_Encode4(396272), // Rule ID 4506 //
     /* 396172 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396176 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 396180 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396184 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396188 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396191 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396195 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396199 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396203 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396205 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 396212 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 396212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 396219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396224 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396229 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 396234 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 396239 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396245 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396252 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396255 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396261 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396266 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396271 */     // GIR_Coverage, 4506,
     /* 396271 */     GIR_EraseRootFromParent_Done,
     /* 396272 */   // Label 7925: @396272
     /* 396272 */   GIM_Try, /*On fail goto*//*Label 7926*/ GIMT_Encode4(396376), // Rule ID 4388 //
     /* 396277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396281 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 396287 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 396289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396297 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396300 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396304 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396308 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396312 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396314 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 396321 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 396321 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396324 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 396328 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396333 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396338 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396343 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396349 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396356 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396359 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396365 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396370 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396375 */     // GIR_Coverage, 4388,
     /* 396375 */     GIR_EraseRootFromParent_Done,
     /* 396376 */   // Label 7926: @396376
     /* 396376 */   GIM_Try, /*On fail goto*//*Label 7927*/ GIMT_Encode4(396480), // Rule ID 4389 //
     /* 396381 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396385 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 396391 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 396393 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396397 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396401 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396404 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396408 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396412 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396416 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396418 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 396425 */     // (vector_insert:{ *:[v4i32] } immAllZerosV:{ *:[v4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 396425 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396428 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 396432 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396437 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396442 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396447 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396453 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396455 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396458 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396460 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396463 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396469 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396474 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396479 */     // GIR_Coverage, 4389,
     /* 396479 */     GIR_EraseRootFromParent_Done,
     /* 396480 */   // Label 7927: @396480
     /* 396480 */   GIM_Try, /*On fail goto*//*Label 7928*/ GIMT_Encode4(396584), // Rule ID 4496 //
     /* 396485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396489 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 396495 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 396497 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396501 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396505 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396508 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396512 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396516 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396520 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396522 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 396529 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 396529 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396532 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 396536 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396541 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396546 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396551 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396557 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396559 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396562 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396567 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396570 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396573 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396578 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396583 */     // GIR_Coverage, 4496,
     /* 396583 */     GIR_EraseRootFromParent_Done,
     /* 396584 */   // Label 7928: @396584
     /* 396584 */   GIM_Try, /*On fail goto*//*Label 7929*/ GIMT_Encode4(396688), // Rule ID 4497 //
     /* 396589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396593 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 396599 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 396601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396609 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396612 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396616 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396620 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396624 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396626 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 396633 */     // (vector_insert:{ *:[v4f32] } immAllZerosV:{ *:[v4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 396633 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396636 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 396640 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396645 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396650 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396655 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396661 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396668 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396671 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396674 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396677 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396682 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396687 */     // GIR_Coverage, 4497,
     /* 396687 */     GIR_EraseRootFromParent_Done,
     /* 396688 */   // Label 7929: @396688
     /* 396688 */   GIM_Try, /*On fail goto*//*Label 7930*/ GIMT_Encode4(396788), // Rule ID 4392 //
     /* 396693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 396701 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396705 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396709 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396712 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396716 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396720 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396724 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396726 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 396733 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 396733 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396736 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 396740 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396745 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396750 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396755 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396761 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396763 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396766 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396768 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396771 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396777 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396782 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396787 */     // GIR_Coverage, 4392,
     /* 396787 */     GIR_EraseRootFromParent_Done,
     /* 396788 */   // Label 7930: @396788
     /* 396788 */   GIM_Try, /*On fail goto*//*Label 7931*/ GIMT_Encode4(396888), // Rule ID 4394 //
     /* 396793 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396797 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 396801 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396805 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396809 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396812 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396816 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396820 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396824 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396826 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 396833 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 396833 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396836 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 396840 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396850 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396855 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396861 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396868 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396871 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396874 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396877 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396882 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396887 */     // GIR_Coverage, 4394,
     /* 396887 */     GIR_EraseRootFromParent_Done,
     /* 396888 */   // Label 7931: @396888
     /* 396888 */   GIM_Try, /*On fail goto*//*Label 7932*/ GIMT_Encode4(396988), // Rule ID 4500 //
     /* 396893 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396897 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 396901 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 396905 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 396909 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 396912 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 396916 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 396920 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 396924 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 396926 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 396933 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 396933 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 396936 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 396940 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 396945 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 396950 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 396955 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 396961 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 396963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 396966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 396968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 396971 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 396974 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 396977 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 396982 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 396987 */     // GIR_Coverage, 4500,
     /* 396987 */     GIR_EraseRootFromParent_Done,
     /* 396988 */   // Label 7932: @396988
     /* 396988 */   GIM_Try, /*On fail goto*//*Label 7933*/ GIMT_Encode4(397088), // Rule ID 4502 //
     /* 396993 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 396997 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 397001 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 397005 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 397009 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 397012 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 397016 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 397020 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 397024 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 397026 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 397033 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 397033 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 397036 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 397040 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397045 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 397050 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 397055 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 397061 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 397063 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 397066 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 397071 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397074 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 397077 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397082 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397087 */     // GIR_Coverage, 4502,
     /* 397087 */     GIR_EraseRootFromParent_Done,
     /* 397088 */   // Label 7933: @397088
     /* 397088 */   GIM_Try, /*On fail goto*//*Label 7934*/ GIMT_Encode4(397201), // Rule ID 6325 //
     /* 397093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 397097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 397101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 397105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397109 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397113 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 397117 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397122 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 397126 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397130 */     // MIs[3] Operand 1
     /* 397130 */     // No operand predicates
     /* 397130 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 397134 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397136 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), (DUPi32:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), ssub:{ *:[i32] })
     /* 397136 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 397139 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 397143 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397148 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 397152 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 397155 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 397157 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397160 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 397164 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397169 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 397171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 397174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397176 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397179 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 397182 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 397185 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397190 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397195 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397200 */     // GIR_Coverage, 6325,
     /* 397200 */     GIR_EraseRootFromParent_Done,
     /* 397201 */   // Label 7934: @397201
     /* 397201 */   GIM_Try, /*On fail goto*//*Label 7935*/ GIMT_Encode4(397314), // Rule ID 6365 //
     /* 397206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 397210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 397214 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 397218 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397222 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397226 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 397230 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397235 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 397239 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397243 */     // MIs[3] Operand 1
     /* 397243 */     // No operand predicates
     /* 397243 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 397247 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397249 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), (DUPi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), ssub:{ *:[i32] })
     /* 397249 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 397252 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 397256 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397261 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 397265 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 397268 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 397270 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397273 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 397277 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397282 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 397284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 397287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397289 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 397295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 397298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397313 */     // GIR_Coverage, 6365,
     /* 397313 */     GIR_EraseRootFromParent_Done,
     /* 397314 */   // Label 7935: @397314
     /* 397314 */   GIM_Try, /*On fail goto*//*Label 7936*/ GIMT_Encode4(397392), // Rule ID 1971 //
     /* 397319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 397322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397334 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397338 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397342 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397347 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397351 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397355 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 397359 */     // MIs[2] Operand 1
     /* 397359 */     // No operand predicates
     /* 397359 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397363 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397367 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 397371 */     // MIs[3] Operand 1
     /* 397371 */     // No operand predicates
     /* 397371 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397373 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 397373 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397376 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397378 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 397380 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 397383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 397387 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 397390 */     GIR_RootConstrainSelectedInstOperands,
     /* 397391 */     // GIR_Coverage, 1971,
     /* 397391 */     GIR_EraseRootFromParent_Done,
     /* 397392 */   // Label 7936: @397392
     /* 397392 */   GIM_Try, /*On fail goto*//*Label 7937*/ GIMT_Encode4(397481), // Rule ID 6322 //
     /* 397397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 397409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397413 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397417 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397421 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 397425 */     // MIs[2] Operand 1
     /* 397425 */     // No operand predicates
     /* 397425 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397429 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397433 */     // MIs[3] Operand 1
     /* 397433 */     // No operand predicates
     /* 397433 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397435 */     // (vector_insert:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v4f32] } ZPR:{ *:[nxv4f32] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn)
     /* 397435 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397438 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 397442 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397447 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 397453 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397458 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 397463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397468 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 397470 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397473 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397476 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397479 */     GIR_RootConstrainSelectedInstOperands,
     /* 397480 */     // GIR_Coverage, 6322,
     /* 397480 */     GIR_EraseRootFromParent_Done,
     /* 397481 */   // Label 7937: @397481
     /* 397481 */   GIM_Try, /*On fail goto*//*Label 7938*/ GIMT_Encode4(397570), // Rule ID 6362 //
     /* 397486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 397498 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397502 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397506 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397510 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 397514 */     // MIs[2] Operand 1
     /* 397514 */     // No operand predicates
     /* 397514 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397518 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397522 */     // MIs[3] Operand 1
     /* 397522 */     // No operand predicates
     /* 397522 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397524 */     // (vector_insert:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$Immn)
     /* 397524 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397527 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 397531 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397536 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 397542 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397547 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 397552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397557 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 397559 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397562 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397565 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397568 */     GIR_RootConstrainSelectedInstOperands,
     /* 397569 */     // GIR_Coverage, 6362,
     /* 397569 */     GIR_EraseRootFromParent_Done,
     /* 397570 */   // Label 7938: @397570
     /* 397570 */   GIM_Try, /*On fail goto*//*Label 7939*/ GIMT_Encode4(397637), // Rule ID 6324 //
     /* 397575 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397579 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397583 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397587 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397591 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397595 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397600 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397604 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397608 */     // MIs[2] Operand 1
     /* 397608 */     // No operand predicates
     /* 397608 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397612 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397616 */     // MIs[3] Operand 1
     /* 397616 */     // No operand predicates
     /* 397616 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397618 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 397618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397623 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 397625 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 397632 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397635 */     GIR_RootConstrainSelectedInstOperands,
     /* 397636 */     // GIR_Coverage, 6324,
     /* 397636 */     GIR_EraseRootFromParent_Done,
     /* 397637 */   // Label 7939: @397637
     /* 397637 */   GIM_Try, /*On fail goto*//*Label 7940*/ GIMT_Encode4(397735), // Rule ID 6326 //
     /* 397642 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397646 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397650 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397654 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 397658 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397662 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397667 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397671 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397675 */     // MIs[2] Operand 1
     /* 397675 */     // No operand predicates
     /* 397675 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397679 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397683 */     // MIs[3] Operand 1
     /* 397683 */     // No operand predicates
     /* 397683 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397685 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (vector_extract:{ *:[f32] } V64:{ *:[v2f32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v4f32] } 0:{ *:[i64] }, V64:{ *:[v2f32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 397685 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397688 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 397692 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397697 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 397700 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 397704 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 397707 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397712 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397722 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 397724 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397727 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397730 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397733 */     GIR_RootConstrainSelectedInstOperands,
     /* 397734 */     // GIR_Coverage, 6326,
     /* 397734 */     GIR_EraseRootFromParent_Done,
     /* 397735 */   // Label 7940: @397735
     /* 397735 */   GIM_Try, /*On fail goto*//*Label 7941*/ GIMT_Encode4(397802), // Rule ID 6364 //
     /* 397740 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 397756 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397760 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397765 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397769 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397773 */     // MIs[2] Operand 1
     /* 397773 */     // No operand predicates
     /* 397773 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397777 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397781 */     // MIs[3] Operand 1
     /* 397781 */     // No operand predicates
     /* 397781 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397783 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 397783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397788 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 397790 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 397797 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397800 */     GIR_RootConstrainSelectedInstOperands,
     /* 397801 */     // GIR_Coverage, 6364,
     /* 397801 */     GIR_EraseRootFromParent_Done,
     /* 397802 */   // Label 7941: @397802
     /* 397802 */   GIM_Try, /*On fail goto*//*Label 7942*/ GIMT_Encode4(397900), // Rule ID 6366 //
     /* 397807 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397811 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 397815 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 397819 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 397823 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 397827 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 397836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397840 */     // MIs[2] Operand 1
     /* 397840 */     // No operand predicates
     /* 397840 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 397844 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 397848 */     // MIs[3] Operand 1
     /* 397848 */     // No operand predicates
     /* 397848 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 397850 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v2i32] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, V64:{ *:[v2i32] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 397850 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397853 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 397857 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397862 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 397865 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 397869 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 397872 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397877 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 397882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 397885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397887 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 397889 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 397892 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397895 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 397898 */     GIR_RootConstrainSelectedInstOperands,
     /* 397899 */     // GIR_Coverage, 6366,
     /* 397899 */     GIR_EraseRootFromParent_Done,
     /* 397900 */   // Label 7942: @397900
     /* 397900 */   GIM_Try, /*On fail goto*//*Label 7943*/ GIMT_Encode4(397966), // Rule ID 6276 //
     /* 397905 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 397909 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 397913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 397917 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 397921 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 397923 */     // (vector_insert:{ *:[v4i32] } (undef:{ *:[v4i32] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), GPR32:{ *:[i32] }:$Rn, ssub:{ *:[i32] })
     /* 397923 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397926 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 397930 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 397935 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 397937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 397940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 397942 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 397945 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 397947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 397950 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397955 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 397960 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 397965 */     // GIR_Coverage, 6276,
     /* 397965 */     GIR_EraseRootFromParent_Done,
     /* 397966 */   // Label 7943: @397966
     /* 397966 */   GIM_Try, /*On fail goto*//*Label 7944*/ GIMT_Encode4(398032), // Rule ID 6288 //
     /* 397971 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 397975 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 397979 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 397983 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 397987 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 397989 */     // (vector_insert:{ *:[v4f32] } (undef:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] })
     /* 397989 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 397992 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 397996 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398001 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 398003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 398006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398008 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398011 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 398013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 398016 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398021 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398026 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398031 */     // GIR_Coverage, 6288,
     /* 398031 */     GIR_EraseRootFromParent_Done,
     /* 398032 */   // Label 7944: @398032
     /* 398032 */   GIM_Try, /*On fail goto*//*Label 7945*/ GIMT_Encode4(398088), // Rule ID 6297 //
     /* 398037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseWzrToVecMove),
     /* 398040 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 398048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 398052 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 398056 */     // MIs[1] Operand 1
     /* 398056 */     // No operand predicates
     /* 398056 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 398060 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398064 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 398068 */     // MIs[2] Operand 1
     /* 398068 */     // No operand predicates
     /* 398068 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398070 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (INSvi32gpr:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, WZR:{ *:[i32] })
     /* 398070 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 398073 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398075 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 398077 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 398080 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 398086 */     GIR_RootConstrainSelectedInstOperands,
     /* 398087 */     // GIR_Coverage, 6297,
     /* 398087 */     GIR_EraseRootFromParent_Done,
     /* 398088 */   // Label 7945: @398088
     /* 398088 */   GIM_Try, /*On fail goto*//*Label 7946*/ GIMT_Encode4(398157), // Rule ID 7077 //
     /* 398093 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 398101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398105 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398108 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 398112 */     // MIs[1] Rn
     /* 398112 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 398116 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 398121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 398125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398129 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 398133 */     // MIs[2] Operand 1
     /* 398133 */     // No operand predicates
     /* 398133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398135 */     // (vector_insert:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (LD1i32:{ *:[v4i32] } VecListOne128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 398135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 398138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398140 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 398142 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 398145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 398149 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398155 */     GIR_RootConstrainSelectedInstOperands,
     /* 398156 */     // GIR_Coverage, 7077,
     /* 398156 */     GIR_EraseRootFromParent_Done,
     /* 398157 */   // Label 7946: @398157
     /* 398157 */   GIM_Try, /*On fail goto*//*Label 7947*/ GIMT_Encode4(398226), // Rule ID 7078 //
     /* 398162 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398166 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 398170 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398174 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398177 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 398181 */     // MIs[1] Rn
     /* 398181 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 398185 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 398190 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 398194 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398198 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 398202 */     // MIs[2] Operand 1
     /* 398202 */     // No operand predicates
     /* 398202 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398204 */     // (vector_insert:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (LD1i32:{ *:[v4f32] } VecListOne128:{ *:[v4f32] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 398204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i32),
     /* 398207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 398211 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 398214 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 398218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398224 */     GIR_RootConstrainSelectedInstOperands,
     /* 398225 */     // GIR_Coverage, 7078,
     /* 398225 */     GIR_EraseRootFromParent_Done,
     /* 398226 */   // Label 7947: @398226
     /* 398226 */   GIM_Try, /*On fail goto*//*Label 7948*/ GIMT_Encode4(398327), // Rule ID 6377 //
     /* 398231 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 398235 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 398239 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 398243 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398248 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 398252 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398256 */     // MIs[2] Operand 1
     /* 398256 */     // No operand predicates
     /* 398256 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398258 */     // (vector_insert:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$Sn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$src, (imm:{ *:[i64] }):$Immd, (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), FPR32:{ *:[f32] }:$Sn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 398258 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 398261 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 398265 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398270 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 398272 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 398275 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 398279 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398284 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 398287 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Sn
     /* 398291 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 398294 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398299 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398304 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398309 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 398312 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398314 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 398316 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immd
     /* 398319 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398322 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398325 */     GIR_RootConstrainSelectedInstOperands,
     /* 398326 */     // GIR_Coverage, 6377,
     /* 398326 */     GIR_EraseRootFromParent_Done,
     /* 398327 */   // Label 7948: @398327
     /* 398327 */   GIM_Try, /*On fail goto*//*Label 7949*/ GIMT_Encode4(398371), // Rule ID 1967 //
     /* 398332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 398335 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 398343 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 398347 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398351 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 398355 */     // MIs[1] Operand 1
     /* 398355 */     // No operand predicates
     /* 398355 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 398357 */     // (vector_insert:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (INSvi32gpr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 398357 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32gpr),
     /* 398360 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398362 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 398364 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 398367 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 398369 */     GIR_RootConstrainSelectedInstOperands,
     /* 398370 */     // GIR_Coverage, 1967,
     /* 398370 */     GIR_EraseRootFromParent_Done,
     /* 398371 */   // Label 7949: @398371
     /* 398371 */   GIM_Try, /*On fail goto*//*Label 7950*/ GIMT_Encode4(398467), // Rule ID 6302 //
     /* 398376 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 398388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 398392 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 398396 */     // MIs[1] Operand 1
     /* 398396 */     // No operand predicates
     /* 398396 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 398398 */     // (vector_insert:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (INSvi32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm, (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 398398 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 398401 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 398405 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398410 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 398412 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 398415 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 398419 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398424 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 398427 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 398431 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 398434 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398439 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 398444 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 398449 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi32lane),
     /* 398452 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398454 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 398456 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 398459 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398465 */     GIR_RootConstrainSelectedInstOperands,
     /* 398466 */     // GIR_Coverage, 6302,
     /* 398466 */     GIR_EraseRootFromParent_Done,
     /* 398467 */   // Label 7950: @398467
     /* 398467 */   GIM_Reject,
     /* 398468 */ // Label 7917: @398468
     /* 398468 */ GIM_Reject,
     /* 398469 */ // Label 7801: @398469
     /* 398469 */ GIM_Try, /*On fail goto*//*Label 7951*/ GIMT_Encode4(401681),
     /* 398474 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 398477 */   GIM_Try, /*On fail goto*//*Label 7952*/ GIMT_Encode4(398596), // Rule ID 4294 //
     /* 398482 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 398485 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 398488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398492 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398496 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 398502 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 398504 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398508 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398512 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398515 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 398519 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 398523 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 398527 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398529 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 398536 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 398536 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 398539 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 398543 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398548 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 398553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 398558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 398563 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398569 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 398571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 398574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398579 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 398585 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398590 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 398595 */     // GIR_Coverage, 4294,
     /* 398595 */     GIR_EraseRootFromParent_Done,
     /* 398596 */   // Label 7952: @398596
     /* 398596 */   GIM_Try, /*On fail goto*//*Label 7953*/ GIMT_Encode4(398715), // Rule ID 4295 //
     /* 398601 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 398604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 398607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398611 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398615 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 398621 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 398623 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398627 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398631 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398634 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 398638 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 398642 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 398646 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398648 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 398655 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 398655 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 398658 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 398662 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398667 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 398672 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 398677 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 398682 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398688 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 398690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 398693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398698 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398701 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 398704 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398709 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 398714 */     // GIR_Coverage, 4295,
     /* 398714 */     GIR_EraseRootFromParent_Done,
     /* 398715 */   // Label 7953: @398715
     /* 398715 */   GIM_Try, /*On fail goto*//*Label 7954*/ GIMT_Encode4(398841), // Rule ID 4330 //
     /* 398720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 398723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 398726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398734 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 398740 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 398742 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398746 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398750 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398753 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 398757 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 398764 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 398768 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 398772 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398774 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 398781 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 398781 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 398784 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 398788 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398793 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 398798 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 398803 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 398808 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398814 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 398816 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 398819 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398821 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398824 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 398830 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398835 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 398840 */     // GIR_Coverage, 4330,
     /* 398840 */     GIR_EraseRootFromParent_Done,
     /* 398841 */   // Label 7954: @398841
     /* 398841 */   GIM_Try, /*On fail goto*//*Label 7955*/ GIMT_Encode4(398967), // Rule ID 4331 //
     /* 398846 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 398849 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 398852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398856 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398860 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 398866 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 398868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398872 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398876 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 398879 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 398883 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 398890 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 398894 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 398898 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 398900 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 398907 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 398907 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 398910 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 398914 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 398919 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 398924 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 398929 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 398934 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 398940 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 398942 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 398945 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 398947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 398950 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 398953 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 398956 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398961 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 398966 */     // GIR_Coverage, 4331,
     /* 398966 */     GIR_EraseRootFromParent_Done,
     /* 398967 */   // Label 7955: @398967
     /* 398967 */   GIM_Try, /*On fail goto*//*Label 7956*/ GIMT_Encode4(399082), // Rule ID 4300 //
     /* 398972 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 398975 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 398978 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 398982 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 398986 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 398990 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 398994 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 398998 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399001 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399005 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399009 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399013 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399015 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 399022 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 399022 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399025 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 399029 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399039 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 399044 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 399049 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399055 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399065 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399068 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399071 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399076 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399081 */     // GIR_Coverage, 4300,
     /* 399081 */     GIR_EraseRootFromParent_Done,
     /* 399082 */   // Label 7956: @399082
     /* 399082 */   GIM_Try, /*On fail goto*//*Label 7957*/ GIMT_Encode4(399197), // Rule ID 4302 //
     /* 399087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 399090 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 399105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399109 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399113 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399116 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399120 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399124 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399128 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399130 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 399137 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 399137 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399140 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 399144 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399154 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 399159 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 399164 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399170 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399172 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399175 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399177 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399180 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399183 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399186 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399191 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399196 */     // GIR_Coverage, 4302,
     /* 399196 */     GIR_EraseRootFromParent_Done,
     /* 399197 */   // Label 7957: @399197
     /* 399197 */   GIM_Try, /*On fail goto*//*Label 7958*/ GIMT_Encode4(399319), // Rule ID 4336 //
     /* 399202 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 399205 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399208 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399212 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399216 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 399220 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399224 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399228 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399231 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399235 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 399242 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399246 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399250 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399252 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 399259 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 399259 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399262 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 399266 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399276 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 399281 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 399286 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399292 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399299 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399302 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399305 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399308 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399313 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399318 */     // GIR_Coverage, 4336,
     /* 399318 */     GIR_EraseRootFromParent_Done,
     /* 399319 */   // Label 7958: @399319
     /* 399319 */   GIM_Try, /*On fail goto*//*Label 7959*/ GIMT_Encode4(399441), // Rule ID 4338 //
     /* 399324 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 399327 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399330 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399334 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399338 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 399342 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399346 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399350 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399353 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399357 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 399364 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399368 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399372 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399374 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 399381 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 399381 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399384 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 399388 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399393 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399398 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 399403 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 399408 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399414 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399421 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399424 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399427 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399430 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399435 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399440 */     // GIR_Coverage, 4338,
     /* 399440 */     GIR_EraseRootFromParent_Done,
     /* 399441 */   // Label 7959: @399441
     /* 399441 */   GIM_Try, /*On fail goto*//*Label 7960*/ GIMT_Encode4(399555), // Rule ID 4292 //
     /* 399446 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 399449 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399452 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399460 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 399466 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 399468 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399472 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399476 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399479 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399483 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399487 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399491 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399493 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 399500 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 399500 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399503 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 399507 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399512 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399517 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 399522 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399528 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399535 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399538 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399541 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399544 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399549 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399554 */     // GIR_Coverage, 4292,
     /* 399554 */     GIR_EraseRootFromParent_Done,
     /* 399555 */   // Label 7960: @399555
     /* 399555 */   GIM_Try, /*On fail goto*//*Label 7961*/ GIMT_Encode4(399669), // Rule ID 4293 //
     /* 399560 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 399563 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399566 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399570 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399574 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 399580 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 399582 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399586 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399590 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399593 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399597 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399601 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399605 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399607 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 399614 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 399614 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399617 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 399621 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399626 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399631 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 399636 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399642 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399644 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399647 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399649 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399652 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399655 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399658 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399663 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399668 */     // GIR_Coverage, 4293,
     /* 399668 */     GIR_EraseRootFromParent_Done,
     /* 399669 */   // Label 7961: @399669
     /* 399669 */   GIM_Try, /*On fail goto*//*Label 7962*/ GIMT_Encode4(399790), // Rule ID 4328 //
     /* 399674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 399677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399684 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399688 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 399694 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 399696 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399700 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399704 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399707 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399711 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 399718 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399722 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399726 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399728 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 399735 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 399735 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399738 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 399742 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399747 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399752 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 399757 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399763 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399765 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399768 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399770 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399773 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399776 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399779 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399784 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399789 */     // GIR_Coverage, 4328,
     /* 399789 */     GIR_EraseRootFromParent_Done,
     /* 399790 */   // Label 7962: @399790
     /* 399790 */   GIM_Try, /*On fail goto*//*Label 7963*/ GIMT_Encode4(399911), // Rule ID 4329 //
     /* 399795 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 399798 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399801 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399805 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399809 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 399815 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 399817 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399821 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399825 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399828 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399832 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 399839 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399843 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399847 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399849 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 399856 */     // (vector_insert:{ *:[v8i8] } immAllZerosV:{ *:[v8i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 399856 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399859 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 399863 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399868 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399873 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 399878 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399884 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 399891 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 399894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 399897 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 399900 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399905 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 399910 */     // GIR_Coverage, 4329,
     /* 399910 */     GIR_EraseRootFromParent_Done,
     /* 399911 */   // Label 7963: @399911
     /* 399911 */   GIM_Try, /*On fail goto*//*Label 7964*/ GIMT_Encode4(400021), // Rule ID 4296 //
     /* 399916 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 399919 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 399922 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 399926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 399930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 399934 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 399938 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 399942 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 399945 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 399949 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 399953 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 399957 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 399959 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 399966 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 399966 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 399969 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 399973 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 399978 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 399983 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 399988 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 399994 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 399996 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 399999 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400001 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 400004 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400007 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 400010 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400015 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 400020 */     // GIR_Coverage, 4296,
     /* 400020 */     GIR_EraseRootFromParent_Done,
     /* 400021 */   // Label 7964: @400021
     /* 400021 */   GIM_Try, /*On fail goto*//*Label 7965*/ GIMT_Encode4(400131), // Rule ID 4298 //
     /* 400026 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 400029 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400032 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400036 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400040 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 400044 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 400048 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 400052 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 400055 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 400059 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 400063 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 400067 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 400069 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 400076 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 400076 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 400079 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 400083 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400088 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 400093 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 400098 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 400104 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400111 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 400114 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400117 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 400120 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400125 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 400130 */     // GIR_Coverage, 4298,
     /* 400130 */     GIR_EraseRootFromParent_Done,
     /* 400131 */   // Label 7965: @400131
     /* 400131 */   GIM_Try, /*On fail goto*//*Label 7966*/ GIMT_Encode4(400248), // Rule ID 4332 //
     /* 400136 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 400139 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 400154 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 400158 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 400162 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 400165 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 400169 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 400176 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 400180 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 400184 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 400186 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 400193 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 400193 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 400196 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 400200 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 400210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 400215 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 400221 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 400231 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 400237 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400242 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 400247 */     // GIR_Coverage, 4332,
     /* 400247 */     GIR_EraseRootFromParent_Done,
     /* 400248 */   // Label 7966: @400248
     /* 400248 */   GIM_Try, /*On fail goto*//*Label 7967*/ GIMT_Encode4(400365), // Rule ID 4334 //
     /* 400253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 400256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400263 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 400267 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 400271 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 400275 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 400279 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 400282 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 400286 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 400293 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 400297 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 400301 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 400303 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 400310 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 400310 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 400313 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 400317 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 400327 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 400332 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 400338 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400345 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 400348 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 400351 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 400354 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400359 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 400364 */     // GIR_Coverage, 4334,
     /* 400364 */     GIR_EraseRootFromParent_Done,
     /* 400365 */   // Label 7967: @400365
     /* 400365 */   GIM_Try, /*On fail goto*//*Label 7968*/ GIMT_Encode4(400505), // Rule ID 6343 //
     /* 400370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 400373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400380 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 400396 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400405 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400409 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400413 */     // MIs[2] Operand 1
     /* 400413 */     // No operand predicates
     /* 400413 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 400417 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400421 */     // MIs[3] Operand 1
     /* 400421 */     // No operand predicates
     /* 400421 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400423 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 400423 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 400426 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400430 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400435 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 400438 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 400442 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 400445 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400450 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400455 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 400458 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 400462 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400467 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 400470 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 400473 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 400477 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 400480 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400482 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400485 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400487 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 400494 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400499 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400504 */     // GIR_Coverage, 6343,
     /* 400504 */     GIR_EraseRootFromParent_Done,
     /* 400505 */   // Label 7968: @400505
     /* 400505 */   GIM_Try, /*On fail goto*//*Label 7969*/ GIMT_Encode4(400676), // Rule ID 6344 //
     /* 400510 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 400513 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400516 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400520 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400524 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400528 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400532 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 400536 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400540 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400545 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400549 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400553 */     // MIs[2] Operand 1
     /* 400553 */     // No operand predicates
     /* 400553 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 400557 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400561 */     // MIs[3] Operand 1
     /* 400561 */     // No operand predicates
     /* 400561 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400563 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 400563 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 400566 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400570 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400575 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 400578 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 400582 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 400585 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400590 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400595 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 400598 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400602 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400607 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 400610 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 400614 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 400617 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400622 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400627 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 400630 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 400634 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400639 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 400642 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 400645 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 400648 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 400651 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400653 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400656 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400658 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 400665 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400670 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400675 */     // GIR_Coverage, 6344,
     /* 400675 */     GIR_EraseRootFromParent_Done,
     /* 400676 */   // Label 7969: @400676
     /* 400676 */   GIM_Try, /*On fail goto*//*Label 7970*/ GIMT_Encode4(400816), // Rule ID 6351 //
     /* 400681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 400684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400691 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400695 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400699 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400703 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 400707 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400711 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400716 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400720 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400724 */     // MIs[2] Operand 1
     /* 400724 */     // No operand predicates
     /* 400724 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 400728 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400732 */     // MIs[3] Operand 1
     /* 400732 */     // No operand predicates
     /* 400732 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400734 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 400734 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 400737 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400741 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400746 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 400749 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 400753 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 400756 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400761 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400766 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 400769 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 400773 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400778 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 400781 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 400784 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 400788 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 400791 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400798 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 400805 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400810 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400815 */     // GIR_Coverage, 6351,
     /* 400815 */     GIR_EraseRootFromParent_Done,
     /* 400816 */   // Label 7970: @400816
     /* 400816 */   GIM_Try, /*On fail goto*//*Label 7971*/ GIMT_Encode4(400987), // Rule ID 6352 //
     /* 400821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 400824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400831 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400835 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 400839 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 400843 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 400847 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 400851 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400856 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 400860 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400864 */     // MIs[2] Operand 1
     /* 400864 */     // No operand predicates
     /* 400864 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 400868 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 400872 */     // MIs[3] Operand 1
     /* 400872 */     // No operand predicates
     /* 400872 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 400874 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$src, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn), dsub:{ *:[i32] })
     /* 400874 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 400877 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400881 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400886 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 400889 */     GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 400893 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/3,
     /* 400896 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400901 */     GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400906 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 400909 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 400913 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400918 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 400921 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 400925 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 400928 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400933 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400938 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 400941 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 400945 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 400950 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 400953 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // Immd
     /* 400956 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 400959 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // Immn
     /* 400962 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 400964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 400967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 400969 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 400976 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 400981 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 400986 */     // GIR_Coverage, 6352,
     /* 400986 */     GIR_EraseRootFromParent_Done,
     /* 400987 */   // Label 7971: @400987
     /* 400987 */   GIM_Try, /*On fail goto*//*Label 7972*/ GIMT_Encode4(401066), // Rule ID 6267 //
     /* 400992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 400995 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 400998 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401002 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401006 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 401010 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 401014 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 401018 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401020 */     // (vector_insert:{ *:[v8i8] } (undef:{ *:[v8i8] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i8] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 401020 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 401023 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401027 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401032 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 401036 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 401044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401046 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 401049 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401052 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 401055 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401060 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 401065 */     // GIR_Coverage, 6267,
     /* 401065 */     GIR_EraseRootFromParent_Done,
     /* 401066 */   // Label 7972: @401066
     /* 401066 */   GIM_Try, /*On fail goto*//*Label 7973*/ GIMT_Encode4(401208), // Rule ID 7094 //
     /* 401071 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 401074 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401077 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401081 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 401089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 401093 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 401096 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 401100 */     // MIs[1] Rn
     /* 401100 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 401104 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 401109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 401113 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401117 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 401121 */     // MIs[2] Operand 1
     /* 401121 */     // No operand predicates
     /* 401121 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401123 */     // (vector_insert:{ *:[v8i8] } VecListOne64:{ *:[v8i8] }:$Rd, (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (LD1i8:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 401123 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 401126 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 401130 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401135 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 401138 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 401142 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 401145 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401150 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401155 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 401158 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 401162 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401167 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 401170 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 401173 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 401177 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 401183 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401185 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401188 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401190 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 401197 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401202 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401207 */     // GIR_Coverage, 7094,
     /* 401207 */     GIR_EraseRootFromParent_Done,
     /* 401208 */   // Label 7973: @401208
     /* 401208 */   GIM_Try, /*On fail goto*//*Label 7974*/ GIMT_Encode4(401357), // Rule ID 7095 //
     /* 401213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 401216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401223 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 401231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 401235 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 401238 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 401242 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 401249 */     // MIs[1] Rn
     /* 401249 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 401253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 401258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 401262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401266 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 401270 */     // MIs[2] Operand 1
     /* 401270 */     // No operand predicates
     /* 401270 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401272 */     // (vector_insert:{ *:[v8i8] } VecListOne64:{ *:[v8i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (LD1i8:{ *:[f128] } (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, VecListOne64:{ *:[v8i8] }:$Rd, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn), dsub:{ *:[i32] })
     /* 401272 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 401275 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 401279 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401284 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
     /* 401287 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rd
     /* 401291 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 401294 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401299 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401304 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 401307 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 401311 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401316 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 401319 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/2, // idx
     /* 401322 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 401326 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 401332 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401339 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 401346 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401351 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401356 */     // GIR_Coverage, 7095,
     /* 401356 */     GIR_EraseRootFromParent_Done,
     /* 401357 */   // Label 7974: @401357
     /* 401357 */   GIM_Try, /*On fail goto*//*Label 7975*/ GIMT_Encode4(401492), // Rule ID 6306 //
     /* 401362 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 401365 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401368 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401372 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401376 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 401380 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 401384 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401388 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 401392 */     // MIs[1] Operand 1
     /* 401392 */     // No operand predicates
     /* 401392 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401394 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, GPR32:{ *:[i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8gpr:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, GPR32:{ *:[i32] }:$Rm), dsub:{ *:[i32] })
     /* 401394 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 401397 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 401401 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401406 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 401408 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 401411 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 401415 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401420 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 401423 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 401427 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 401430 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401435 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401440 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401445 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 401448 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
     /* 401452 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401457 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 401460 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 401463 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 401467 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401469 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401472 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401474 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 401481 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401486 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401491 */     // GIR_Coverage, 6306,
     /* 401491 */     GIR_EraseRootFromParent_Done,
     /* 401492 */   // Label 7975: @401492
     /* 401492 */   GIM_Try, /*On fail goto*//*Label 7976*/ GIMT_Encode4(401680), // Rule ID 6307 //
     /* 401497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 401500 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401503 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401507 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401511 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 401515 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 401519 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 401523 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 401527 */     // MIs[1] Operand 1
     /* 401527 */     // No operand predicates
     /* 401527 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 401529 */     // (vector_insert:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (INSvi8lane:{ *:[f128] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] }), dsub:{ *:[i32] })
     /* 401529 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v16s8,
     /* 401532 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 401536 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401541 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 401543 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /* 401546 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 401550 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401555 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 401558 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 401562 */     GIR_AddImm8, /*InsnID*/4, /*Imm*/1,
     /* 401565 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401570 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401575 */     GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 401580 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 401583 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 401587 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401592 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 401594 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 401597 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 401601 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401606 */     GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 401609 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 401613 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/3,
     /* 401616 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401621 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401626 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401631 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 401634 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 401638 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401643 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 401646 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm
     /* 401649 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 401652 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 401655 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 401660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401662 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 401669 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 401674 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401679 */     // GIR_Coverage, 6307,
     /* 401679 */     GIR_EraseRootFromParent_Done,
     /* 401680 */   // Label 7976: @401680
     /* 401680 */   GIM_Reject,
     /* 401681 */ // Label 7951: @401681
     /* 401681 */ GIM_Reject,
     /* 401682 */ // Label 7802: @401682
     /* 401682 */ GIM_Try, /*On fail goto*//*Label 7977*/ GIMT_Encode4(405103),
     /* 401687 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 401690 */   GIM_Try, /*On fail goto*//*Label 7978*/ GIMT_Encode4(401816), // Rule ID 4354 //
     /* 401695 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 401698 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401709 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 401715 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 401717 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 401721 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 401725 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 401728 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 401732 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 401739 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 401743 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 401747 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401749 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 401756 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 401756 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 401759 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 401763 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 401773 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 401778 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 401783 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 401789 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 401794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401796 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 401799 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401802 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 401805 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401810 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 401815 */     // GIR_Coverage, 4354,
     /* 401815 */     GIR_EraseRootFromParent_Done,
     /* 401816 */   // Label 7978: @401816
     /* 401816 */   GIM_Try, /*On fail goto*//*Label 7979*/ GIMT_Encode4(401942), // Rule ID 4355 //
     /* 401821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 401824 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401827 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401831 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401835 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 401841 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 401843 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 401847 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 401851 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 401854 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 401858 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 401865 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 401869 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 401873 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401875 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 401882 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 401882 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 401885 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 401889 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 401894 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 401899 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 401904 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 401909 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 401915 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 401917 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 401920 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 401922 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 401925 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 401928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 401931 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401936 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 401941 */     // GIR_Coverage, 4355,
     /* 401941 */     GIR_EraseRootFromParent_Done,
     /* 401942 */   // Label 7979: @401942
     /* 401942 */   GIM_Try, /*On fail goto*//*Label 7980*/ GIMT_Encode4(402061), // Rule ID 4462 //
     /* 401947 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 401950 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 401953 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 401957 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 401961 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 401967 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 401969 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 401973 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 401977 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 401980 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 401984 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 401988 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 401992 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 401994 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 402001 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402001 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402004 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 402008 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402013 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402018 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402023 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402028 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402034 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402041 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402044 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402047 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402050 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402055 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402060 */     // GIR_Coverage, 4462,
     /* 402060 */     GIR_EraseRootFromParent_Done,
     /* 402061 */   // Label 7980: @402061
     /* 402061 */   GIM_Try, /*On fail goto*//*Label 7981*/ GIMT_Encode4(402180), // Rule ID 4463 //
     /* 402066 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 402069 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402072 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402080 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 402086 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 402088 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402092 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402096 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402099 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402103 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402107 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402111 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402113 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 402120 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402120 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402123 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 402127 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402132 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402137 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402142 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402147 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402153 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402160 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402163 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402166 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402169 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402174 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402179 */     // GIR_Coverage, 4463,
     /* 402179 */     GIR_EraseRootFromParent_Done,
     /* 402180 */   // Label 7981: @402180
     /* 402180 */   GIM_Try, /*On fail goto*//*Label 7982*/ GIMT_Encode4(402302), // Rule ID 4360 //
     /* 402185 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 402188 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402191 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402195 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402199 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 402203 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402207 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402211 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402214 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402218 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 402225 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402229 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402233 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402235 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 402242 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402242 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402245 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 402249 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402254 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402259 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402264 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402269 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402275 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402282 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402285 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402288 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402291 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402296 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402301 */     // GIR_Coverage, 4360,
     /* 402301 */     GIR_EraseRootFromParent_Done,
     /* 402302 */   // Label 7982: @402302
     /* 402302 */   GIM_Try, /*On fail goto*//*Label 7983*/ GIMT_Encode4(402424), // Rule ID 4362 //
     /* 402307 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 402310 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402313 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402317 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402321 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 402325 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402329 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402333 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402336 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402340 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 402347 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402351 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402355 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402357 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 402364 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402364 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402367 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 402371 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402376 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402381 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402386 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402391 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402397 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402404 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402407 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402413 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402418 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402423 */     // GIR_Coverage, 4362,
     /* 402423 */     GIR_EraseRootFromParent_Done,
     /* 402424 */   // Label 7983: @402424
     /* 402424 */   GIM_Try, /*On fail goto*//*Label 7984*/ GIMT_Encode4(402539), // Rule ID 4468 //
     /* 402429 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 402432 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402435 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 402447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402455 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402458 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402462 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402466 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402470 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402472 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 402479 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402479 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402482 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 402486 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402491 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402496 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402501 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402506 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402512 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402519 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402522 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402525 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402528 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402533 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402538 */     // GIR_Coverage, 4468,
     /* 402538 */     GIR_EraseRootFromParent_Done,
     /* 402539 */   // Label 7984: @402539
     /* 402539 */   GIM_Try, /*On fail goto*//*Label 7985*/ GIMT_Encode4(402654), // Rule ID 4470 //
     /* 402544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 402547 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 402562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402570 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402573 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402577 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402581 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402585 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402587 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 402594 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 402594 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402597 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 402601 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402606 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402611 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 402616 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 402621 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402627 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402634 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402637 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402640 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402643 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402648 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402653 */     // GIR_Coverage, 4470,
     /* 402653 */     GIR_EraseRootFromParent_Done,
     /* 402654 */   // Label 7985: @402654
     /* 402654 */   GIM_Try, /*On fail goto*//*Label 7986*/ GIMT_Encode4(402775), // Rule ID 4352 //
     /* 402659 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 402662 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402665 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402669 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402673 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 402679 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 402681 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402685 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402689 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402692 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402696 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 402703 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402707 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402711 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402713 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 402720 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 402720 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402723 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 402727 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402737 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 402742 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402748 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402758 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402761 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402764 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402769 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402774 */     // GIR_Coverage, 4352,
     /* 402774 */     GIR_EraseRootFromParent_Done,
     /* 402775 */   // Label 7986: @402775
     /* 402775 */   GIM_Try, /*On fail goto*//*Label 7987*/ GIMT_Encode4(402896), // Rule ID 4353 //
     /* 402780 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 402783 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402786 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402790 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402794 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 402800 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 402802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402810 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402813 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402817 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 402824 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402828 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402832 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402834 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 402841 */     // (vector_insert:{ *:[v8i16] } immAllZerosV:{ *:[v8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 402841 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402844 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 402848 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402853 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402858 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 402863 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402869 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402876 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402879 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402882 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402885 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402890 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 402895 */     // GIR_Coverage, 4353,
     /* 402895 */     GIR_EraseRootFromParent_Done,
     /* 402896 */   // Label 7987: @402896
     /* 402896 */   GIM_Try, /*On fail goto*//*Label 7988*/ GIMT_Encode4(403010), // Rule ID 4460 //
     /* 402901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 402904 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 402907 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 402911 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 402915 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 402921 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 402923 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 402927 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 402931 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 402934 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 402938 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 402942 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 402946 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 402948 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 402955 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 402955 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 402958 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 402962 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 402967 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 402972 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 402977 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 402983 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 402985 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 402988 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 402990 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 402993 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 402996 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 402999 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403004 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403009 */     // GIR_Coverage, 4460,
     /* 403009 */     GIR_EraseRootFromParent_Done,
     /* 403010 */   // Label 7988: @403010
     /* 403010 */   GIM_Try, /*On fail goto*//*Label 7989*/ GIMT_Encode4(403124), // Rule ID 4461 //
     /* 403015 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 403018 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403021 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403025 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403029 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 403035 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 403037 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403041 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 403045 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 403048 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 403052 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 403056 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403060 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403062 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 403069 */     // (vector_insert:{ *:[v8f16] } immAllZerosV:{ *:[v8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 403069 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 403072 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 403076 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 403086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 403091 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 403097 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 403102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403107 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403110 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403113 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403118 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403123 */     // GIR_Coverage, 4461,
     /* 403123 */     GIR_EraseRootFromParent_Done,
     /* 403124 */   // Label 7989: @403124
     /* 403124 */   GIM_Try, /*On fail goto*//*Label 7990*/ GIMT_Encode4(403241), // Rule ID 4356 //
     /* 403129 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 403132 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403135 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403139 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403143 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403147 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403151 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 403155 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 403158 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 403162 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 403169 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 403173 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403177 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403179 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 403186 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 403186 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 403189 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 403193 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403198 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 403203 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 403208 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 403214 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 403219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403221 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403224 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403240 */     // GIR_Coverage, 4356,
     /* 403240 */     GIR_EraseRootFromParent_Done,
     /* 403241 */   // Label 7990: @403241
     /* 403241 */   GIM_Try, /*On fail goto*//*Label 7991*/ GIMT_Encode4(403358), // Rule ID 4358 //
     /* 403246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 403249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403260 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403264 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403268 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 403272 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 403275 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 403279 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 403286 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 403290 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403294 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403296 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 403303 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 403303 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 403306 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 403310 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403315 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 403320 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 403325 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 403331 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 403336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403341 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403344 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403347 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403352 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403357 */     // GIR_Coverage, 4358,
     /* 403357 */     GIR_EraseRootFromParent_Done,
     /* 403358 */   // Label 7991: @403358
     /* 403358 */   GIM_Try, /*On fail goto*//*Label 7992*/ GIMT_Encode4(403468), // Rule ID 4464 //
     /* 403363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 403366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403381 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403385 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 403389 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 403392 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 403396 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 403400 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403404 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403406 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 403413 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 403413 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 403416 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 403420 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403425 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 403430 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 403435 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 403441 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 403446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403451 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403454 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403457 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403462 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403467 */     // GIR_Coverage, 4464,
     /* 403467 */     GIR_EraseRootFromParent_Done,
     /* 403468 */   // Label 7992: @403468
     /* 403468 */   GIM_Try, /*On fail goto*//*Label 7993*/ GIMT_Encode4(403578), // Rule ID 4466 //
     /* 403473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 403476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403483 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403487 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403491 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403495 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 403499 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 403502 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 403506 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 403510 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403514 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 403516 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 403523 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 403523 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 403526 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 403530 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403535 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 403540 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 403545 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 403551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 403556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403558 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 403561 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403567 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403572 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403577 */     // GIR_Coverage, 4466,
     /* 403577 */     GIR_EraseRootFromParent_Done,
     /* 403578 */   // Label 7993: @403578
     /* 403578 */   GIM_Try, /*On fail goto*//*Label 7994*/ GIMT_Encode4(403701), // Rule ID 6317 //
     /* 403583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 403586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403593 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403597 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403601 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403605 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 403609 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403613 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 403617 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403622 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 403626 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403630 */     // MIs[3] Operand 1
     /* 403630 */     // No operand predicates
     /* 403630 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403634 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403636 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), (DUPi16:{ *:[i16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), hsub:{ *:[i32] })
     /* 403636 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 403639 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 403643 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403648 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 403652 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 403655 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 403657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 403660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 403664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403669 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403671 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 403674 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403676 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403679 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 403682 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403685 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403690 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403695 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403700 */     // GIR_Coverage, 6317,
     /* 403700 */     GIR_EraseRootFromParent_Done,
     /* 403701 */   // Label 7994: @403701
     /* 403701 */   GIM_Try, /*On fail goto*//*Label 7995*/ GIMT_Encode4(403824), // Rule ID 6357 //
     /* 403706 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 403709 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403712 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403716 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 403720 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 403724 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 403728 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 403732 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403736 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 403740 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403745 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 403749 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403753 */     // MIs[3] Operand 1
     /* 403753 */     // No operand predicates
     /* 403753 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 403757 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403759 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), (DUPi16:{ *:[i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), hsub:{ *:[i32] })
     /* 403759 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 403762 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 403766 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403771 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 403775 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 403778 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 403780 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 403783 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 403787 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403792 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 403794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 403797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403799 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 403802 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 403805 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 403808 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403813 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403818 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 403823 */     // GIR_Coverage, 6357,
     /* 403823 */     GIR_EraseRootFromParent_Done,
     /* 403824 */   // Label 7995: @403824
     /* 403824 */   GIM_Try, /*On fail goto*//*Label 7996*/ GIMT_Encode4(403912), // Rule ID 1970 //
     /* 403829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 403832 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 403835 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403838 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403842 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403846 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403850 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 403854 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 403858 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403862 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403867 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403871 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403875 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403879 */     // MIs[2] Operand 1
     /* 403879 */     // No operand predicates
     /* 403879 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 403883 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403887 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403891 */     // MIs[3] Operand 1
     /* 403891 */     // No operand predicates
     /* 403891 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403893 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 403893 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 403896 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403898 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 403900 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 403903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 403907 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 403910 */     GIR_RootConstrainSelectedInstOperands,
     /* 403911 */     // GIR_Coverage, 1970,
     /* 403911 */     GIR_EraseRootFromParent_Done,
     /* 403912 */   // Label 7996: @403912
     /* 403912 */   GIM_Try, /*On fail goto*//*Label 7997*/ GIMT_Encode4(404011), // Rule ID 6314 //
     /* 403917 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 403920 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 403923 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403927 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 403931 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 403935 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 403939 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 403943 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 403947 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403951 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 403955 */     // MIs[2] Operand 1
     /* 403955 */     // No operand predicates
     /* 403955 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 403959 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 403963 */     // MIs[3] Operand 1
     /* 403963 */     // No operand predicates
     /* 403963 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 403965 */     // (vector_insert:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v8f16] } ZPR:{ *:[nxv8f16] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn)
     /* 403965 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 403968 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 403972 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 403977 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 403983 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 403988 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 403993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 403996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 403998 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 404000 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404003 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404006 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404009 */     GIR_RootConstrainSelectedInstOperands,
     /* 404010 */     // GIR_Coverage, 6314,
     /* 404010 */     GIR_EraseRootFromParent_Done,
     /* 404011 */   // Label 7997: @404011
     /* 404011 */   GIM_Try, /*On fail goto*//*Label 7998*/ GIMT_Encode4(404110), // Rule ID 6354 //
     /* 404016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404026 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404030 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404034 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 404038 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404042 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 404046 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404050 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 404054 */     // MIs[2] Operand 1
     /* 404054 */     // No operand predicates
     /* 404054 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404058 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404062 */     // MIs[3] Operand 1
     /* 404062 */     // No operand predicates
     /* 404062 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404064 */     // (vector_insert:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$Immn)
     /* 404064 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 404067 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404071 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404076 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 404082 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404087 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 404092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 404095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404097 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 404099 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404102 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404105 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404108 */     GIR_RootConstrainSelectedInstOperands,
     /* 404109 */     // GIR_Coverage, 6354,
     /* 404109 */     GIR_EraseRootFromParent_Done,
     /* 404110 */   // Label 7998: @404110
     /* 404110 */   GIM_Try, /*On fail goto*//*Label 7999*/ GIMT_Encode4(404187), // Rule ID 6316 //
     /* 404115 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404118 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404121 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404125 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404129 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404133 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404137 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404141 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404145 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404150 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 404154 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404158 */     // MIs[2] Operand 1
     /* 404158 */     // No operand predicates
     /* 404158 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404162 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404166 */     // MIs[3] Operand 1
     /* 404166 */     // No operand predicates
     /* 404166 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404168 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 404168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 404171 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404173 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 404175 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404178 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404182 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404185 */     GIR_RootConstrainSelectedInstOperands,
     /* 404186 */     // GIR_Coverage, 6316,
     /* 404186 */     GIR_EraseRootFromParent_Done,
     /* 404187 */   // Label 7999: @404187
     /* 404187 */   GIM_Try, /*On fail goto*//*Label 8000*/ GIMT_Encode4(404295), // Rule ID 6318 //
     /* 404192 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404195 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404198 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404214 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 404218 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404222 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404227 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 404231 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404235 */     // MIs[2] Operand 1
     /* 404235 */     // No operand predicates
     /* 404235 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404239 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404243 */     // MIs[3] Operand 1
     /* 404243 */     // No operand predicates
     /* 404243 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404245 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (vector_extract:{ *:[f16] } V64:{ *:[v4f16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v8f16] } 0:{ *:[i64] }, V64:{ *:[v4f16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 404245 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 404248 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 404252 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404257 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 404260 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404264 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 404267 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404272 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404277 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 404280 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404282 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 404284 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404287 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404290 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404293 */     GIR_RootConstrainSelectedInstOperands,
     /* 404294 */     // GIR_Coverage, 6318,
     /* 404294 */     GIR_EraseRootFromParent_Done,
     /* 404295 */   // Label 8000: @404295
     /* 404295 */   GIM_Try, /*On fail goto*//*Label 8001*/ GIMT_Encode4(404372), // Rule ID 6356 //
     /* 404300 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404303 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404306 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404310 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404314 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404318 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404322 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 404326 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404330 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404335 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 404339 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404343 */     // MIs[2] Operand 1
     /* 404343 */     // No operand predicates
     /* 404343 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404347 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404351 */     // MIs[3] Operand 1
     /* 404351 */     // No operand predicates
     /* 404351 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404353 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 404353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 404356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404358 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 404360 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404367 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404370 */     GIR_RootConstrainSelectedInstOperands,
     /* 404371 */     // GIR_Coverage, 6356,
     /* 404371 */     GIR_EraseRootFromParent_Done,
     /* 404372 */   // Label 8001: @404372
     /* 404372 */   GIM_Try, /*On fail goto*//*Label 8002*/ GIMT_Encode4(404480), // Rule ID 6358 //
     /* 404377 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404380 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404387 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 404399 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 404403 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 404407 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404412 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 404416 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404420 */     // MIs[2] Operand 1
     /* 404420 */     // No operand predicates
     /* 404420 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 404424 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404428 */     // MIs[3] Operand 1
     /* 404428 */     // No operand predicates
     /* 404428 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 404430 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v4i16] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i64] }, V64:{ *:[v4i16] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 404430 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 404433 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 404437 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404442 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 404445 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404449 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 404452 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404457 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 404462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 404465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404467 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 404469 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 404472 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404475 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 404478 */     GIR_RootConstrainSelectedInstOperands,
     /* 404479 */     // GIR_Coverage, 6358,
     /* 404479 */     GIR_EraseRootFromParent_Done,
     /* 404480 */   // Label 8002: @404480
     /* 404480 */   GIM_Try, /*On fail goto*//*Label 8003*/ GIMT_Encode4(404559), // Rule ID 6270 //
     /* 404485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404488 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 404499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 404503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 404507 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 404511 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 404513 */     // (vector_insert:{ *:[v8i16] } (undef:{ *:[v8i16] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v8i16] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 404513 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 404516 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 404520 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404525 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 404529 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 404534 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 404537 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404539 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 404542 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404545 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 404548 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404553 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 404558 */     // GIR_Coverage, 6270,
     /* 404558 */     GIR_EraseRootFromParent_Done,
     /* 404559 */   // Label 8003: @404559
     /* 404559 */   GIM_Try, /*On fail goto*//*Label 8004*/ GIMT_Encode4(404635), // Rule ID 6282 //
     /* 404564 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404567 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404570 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404574 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 404578 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 404582 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404586 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 404590 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 404592 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 404592 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 404595 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 404599 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404604 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 404606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 404609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404611 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404614 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 404616 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 404619 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404624 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404629 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404634 */     // GIR_Coverage, 6282,
     /* 404634 */     GIR_EraseRootFromParent_Done,
     /* 404635 */   // Label 8004: @404635
     /* 404635 */   GIM_Try, /*On fail goto*//*Label 8005*/ GIMT_Encode4(404711), // Rule ID 6286 //
     /* 404640 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404643 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 404654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 404658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404662 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 404666 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 404668 */     // (vector_insert:{ *:[v8f16] } (undef:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] })
     /* 404668 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 404671 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 404675 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 404680 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 404682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 404685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404687 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 404690 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 404692 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 404695 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404700 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 404710 */     // GIR_Coverage, 6286,
     /* 404710 */     GIR_EraseRootFromParent_Done,
     /* 404711 */   // Label 8005: @404711
     /* 404711 */   GIM_Try, /*On fail goto*//*Label 8006*/ GIMT_Encode4(404777), // Rule ID 6295 //
     /* 404716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseWzrToVecMove),
     /* 404719 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404722 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404725 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404729 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404733 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404737 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 404741 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 404745 */     // MIs[1] Operand 1
     /* 404745 */     // No operand predicates
     /* 404745 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 404749 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404753 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 404757 */     // MIs[2] Operand 1
     /* 404757 */     // No operand predicates
     /* 404757 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 404759 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (INSvi16gpr:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, WZR:{ *:[i32] })
     /* 404759 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 404762 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404764 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 404766 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
     /* 404769 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AArch64::WZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 404775 */     GIR_RootConstrainSelectedInstOperands,
     /* 404776 */     // GIR_Coverage, 6295,
     /* 404776 */     GIR_EraseRootFromParent_Done,
     /* 404777 */   // Label 8006: @404777
     /* 404777 */   GIM_Try, /*On fail goto*//*Label 8007*/ GIMT_Encode4(404863), // Rule ID 7076 //
     /* 404782 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404785 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404792 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404796 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404800 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 404804 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 404807 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 404811 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 404818 */     // MIs[1] Rn
     /* 404818 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 404822 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 404827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 404831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404835 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 404839 */     // MIs[2] Operand 1
     /* 404839 */     // No operand predicates
     /* 404839 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 404841 */     // (vector_insert:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (LD1i16:{ *:[v8i16] } VecListOne128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 404841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 404844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404846 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 404848 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 404851 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404855 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 404861 */     GIR_RootConstrainSelectedInstOperands,
     /* 404862 */     // GIR_Coverage, 7076,
     /* 404862 */     GIR_EraseRootFromParent_Done,
     /* 404863 */   // Label 8007: @404863
     /* 404863 */   GIM_Try, /*On fail goto*//*Label 8008*/ GIMT_Encode4(404942), // Rule ID 7081 //
     /* 404868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 404871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404878 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404882 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 404886 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 404890 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 404893 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 404897 */     // MIs[1] Rn
     /* 404897 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 404901 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 404906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 404910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404914 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 404918 */     // MIs[2] Operand 1
     /* 404918 */     // No operand predicates
     /* 404918 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 404920 */     // (vector_insert:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (LD1i16:{ *:[v8f16] } VecListOne128:{ *:[v8f16] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 404920 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i16),
     /* 404923 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404925 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 404927 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 404930 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 404934 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 404940 */     GIR_RootConstrainSelectedInstOperands,
     /* 404941 */     // GIR_Coverage, 7081,
     /* 404941 */     GIR_EraseRootFromParent_Done,
     /* 404942 */   // Label 8008: @404942
     /* 404942 */   GIM_Try, /*On fail goto*//*Label 8009*/ GIMT_Encode4(404996), // Rule ID 1966 //
     /* 404947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 404950 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 404953 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 404956 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 404964 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 404968 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 404972 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 404976 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 404980 */     // MIs[1] Operand 1
     /* 404980 */     // No operand predicates
     /* 404980 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 404982 */     // (vector_insert:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (INSvi16gpr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 404982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16gpr),
     /* 404985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 404987 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 404989 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 404992 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 404994 */     GIR_RootConstrainSelectedInstOperands,
     /* 404995 */     // GIR_Coverage, 1966,
     /* 404995 */     GIR_EraseRootFromParent_Done,
     /* 404996 */   // Label 8009: @404996
     /* 404996 */   GIM_Try, /*On fail goto*//*Label 8010*/ GIMT_Encode4(405102), // Rule ID 6300 //
     /* 405001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 405004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405011 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405015 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405019 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 405023 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 405027 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 405031 */     // MIs[1] Operand 1
     /* 405031 */     // No operand predicates
     /* 405031 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 405033 */     // (vector_insert:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (INSvi16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm, (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), FPR16:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 405033 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 405036 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 405040 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405045 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 405047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 405050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 405054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405059 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 405062 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 405066 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 405069 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405074 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405079 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 405084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi16lane),
     /* 405087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405089 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 405091 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 405094 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405100 */     GIR_RootConstrainSelectedInstOperands,
     /* 405101 */     // GIR_Coverage, 6300,
     /* 405101 */     GIR_EraseRootFromParent_Done,
     /* 405102 */   // Label 8010: @405102
     /* 405102 */   GIM_Reject,
     /* 405103 */ // Label 7977: @405103
     /* 405103 */ GIM_Reject,
     /* 405104 */ // Label 7803: @405104
     /* 405104 */ GIM_Try, /*On fail goto*//*Label 8011*/ GIMT_Encode4(408307),
     /* 405109 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 405112 */   GIM_Try, /*On fail goto*//*Label 8012*/ GIMT_Encode4(405231), // Rule ID 4282 //
     /* 405117 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 405120 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405127 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405131 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 405137 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 405139 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405143 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405147 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405150 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405154 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405158 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405162 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405164 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 405171 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405171 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405174 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 405178 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405183 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405188 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405193 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405198 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405204 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405211 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405214 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405217 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405220 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405225 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405230 */     // GIR_Coverage, 4282,
     /* 405230 */     GIR_EraseRootFromParent_Done,
     /* 405231 */   // Label 8012: @405231
     /* 405231 */   GIM_Try, /*On fail goto*//*Label 8013*/ GIMT_Encode4(405350), // Rule ID 4283 //
     /* 405236 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 405239 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405242 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405246 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405250 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 405256 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 405258 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405262 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405266 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405269 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405273 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405277 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405281 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405283 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 405290 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405290 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405293 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 405297 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405307 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405317 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405323 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405325 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405328 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405330 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405333 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405336 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405339 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405344 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405349 */     // GIR_Coverage, 4283,
     /* 405349 */     GIR_EraseRootFromParent_Done,
     /* 405350 */   // Label 8013: @405350
     /* 405350 */   GIM_Try, /*On fail goto*//*Label 8014*/ GIMT_Encode4(405476), // Rule ID 4318 //
     /* 405355 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 405358 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405361 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405365 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405369 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 405375 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 405377 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405381 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405385 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405388 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405392 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 405399 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405403 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405407 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405409 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 405416 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405416 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405419 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 405423 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405428 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405433 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405443 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405449 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405456 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405459 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405465 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405470 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405475 */     // GIR_Coverage, 4318,
     /* 405475 */     GIR_EraseRootFromParent_Done,
     /* 405476 */   // Label 8014: @405476
     /* 405476 */   GIM_Try, /*On fail goto*//*Label 8015*/ GIMT_Encode4(405602), // Rule ID 4319 //
     /* 405481 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 405484 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405487 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405491 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405495 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 405501 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 405503 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405507 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405511 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405514 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405518 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 405525 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405529 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405533 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405535 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 405542 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405542 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405545 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 405549 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405554 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405559 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405564 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405569 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405575 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405577 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405580 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405582 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405585 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405588 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405591 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405596 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405601 */     // GIR_Coverage, 4319,
     /* 405601 */     GIR_EraseRootFromParent_Done,
     /* 405602 */   // Label 8015: @405602
     /* 405602 */   GIM_Try, /*On fail goto*//*Label 8016*/ GIMT_Encode4(405717), // Rule ID 4288 //
     /* 405607 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 405610 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405613 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 405625 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405629 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405633 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405636 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405640 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405644 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405648 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405650 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 405657 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405657 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405660 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 405664 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405669 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405674 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405679 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405684 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405690 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405700 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405703 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405706 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405711 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405716 */     // GIR_Coverage, 4288,
     /* 405716 */     GIR_EraseRootFromParent_Done,
     /* 405717 */   // Label 8016: @405717
     /* 405717 */   GIM_Try, /*On fail goto*//*Label 8017*/ GIMT_Encode4(405832), // Rule ID 4290 //
     /* 405722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 405725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405732 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405736 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 405740 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405744 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405748 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405751 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405755 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405759 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405763 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405765 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 405772 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405772 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405775 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 405779 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405789 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405794 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405799 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405805 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405807 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405810 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405812 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405815 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405821 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405826 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405831 */     // GIR_Coverage, 4290,
     /* 405831 */     GIR_EraseRootFromParent_Done,
     /* 405832 */   // Label 8017: @405832
     /* 405832 */   GIM_Try, /*On fail goto*//*Label 8018*/ GIMT_Encode4(405954), // Rule ID 4324 //
     /* 405837 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 405840 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405843 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405847 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405851 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 405855 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405859 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405863 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405866 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405870 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 405877 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 405881 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 405885 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 405887 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 405894 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 405894 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 405897 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 405901 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 405906 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 405911 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 405916 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 405921 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 405927 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 405929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 405932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 405934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 405937 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 405940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 405943 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405948 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 405953 */     // GIR_Coverage, 4324,
     /* 405953 */     GIR_EraseRootFromParent_Done,
     /* 405954 */   // Label 8018: @405954
     /* 405954 */   GIM_Try, /*On fail goto*//*Label 8019*/ GIMT_Encode4(406076), // Rule ID 4326 //
     /* 405959 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 405962 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 405965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 405969 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 405973 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 405977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 405981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 405985 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 405988 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 405992 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 405999 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406003 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406007 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406009 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 406016 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 406016 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406019 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 406023 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406028 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406033 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 406038 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 406043 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406049 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406056 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406065 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406070 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406075 */     // GIR_Coverage, 4326,
     /* 406075 */     GIR_EraseRootFromParent_Done,
     /* 406076 */   // Label 8019: @406076
     /* 406076 */   GIM_Try, /*On fail goto*//*Label 8020*/ GIMT_Encode4(406190), // Rule ID 4280 //
     /* 406081 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 406084 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406091 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406095 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 406101 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 406103 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406107 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406111 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406114 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406118 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406122 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406126 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406128 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 406135 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 406135 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406138 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 406142 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406147 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406152 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406157 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406163 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406173 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406179 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406184 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406189 */     // GIR_Coverage, 4280,
     /* 406189 */     GIR_EraseRootFromParent_Done,
     /* 406190 */   // Label 8020: @406190
     /* 406190 */   GIM_Try, /*On fail goto*//*Label 8021*/ GIMT_Encode4(406304), // Rule ID 4281 //
     /* 406195 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 406198 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406201 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406205 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406209 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 406215 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 406217 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406221 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406225 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406228 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406232 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406236 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406240 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406242 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 406249 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 406249 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406252 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 406256 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406261 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406271 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406277 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406279 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406282 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406284 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406287 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406290 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406293 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406303 */     // GIR_Coverage, 4281,
     /* 406303 */     GIR_EraseRootFromParent_Done,
     /* 406304 */   // Label 8021: @406304
     /* 406304 */   GIM_Try, /*On fail goto*//*Label 8022*/ GIMT_Encode4(406425), // Rule ID 4316 //
     /* 406309 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 406312 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406315 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406319 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406323 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 406329 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 406331 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406335 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406339 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406342 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406346 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 406353 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406357 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406361 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406363 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 406370 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 406370 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406373 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 406377 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406382 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406392 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406398 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406405 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406408 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406411 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406414 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406419 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406424 */     // GIR_Coverage, 4316,
     /* 406424 */     GIR_EraseRootFromParent_Done,
     /* 406425 */   // Label 8022: @406425
     /* 406425 */   GIM_Try, /*On fail goto*//*Label 8023*/ GIMT_Encode4(406546), // Rule ID 4317 //
     /* 406430 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 406433 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406440 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406444 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 406450 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 406452 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406456 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406460 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406463 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406467 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 406474 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406478 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406482 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406484 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 406491 */     // (vector_insert:{ *:[v16i8] } immAllZerosV:{ *:[v16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 406491 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406494 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 406498 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406503 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406508 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406513 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406519 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406529 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406535 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406540 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406545 */     // GIR_Coverage, 4317,
     /* 406545 */     GIR_EraseRootFromParent_Done,
     /* 406546 */   // Label 8023: @406546
     /* 406546 */   GIM_Try, /*On fail goto*//*Label 8024*/ GIMT_Encode4(406656), // Rule ID 4284 //
     /* 406551 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 406554 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406557 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 406569 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406573 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406577 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406580 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406584 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406588 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406592 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406594 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 406601 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 406601 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406604 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 406608 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406613 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406618 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406623 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406629 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406639 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406642 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406645 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406650 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406655 */     // GIR_Coverage, 4284,
     /* 406655 */     GIR_EraseRootFromParent_Done,
     /* 406656 */   // Label 8024: @406656
     /* 406656 */   GIM_Try, /*On fail goto*//*Label 8025*/ GIMT_Encode4(406766), // Rule ID 4286 //
     /* 406661 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 406664 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406667 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406671 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406675 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 406679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406683 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406687 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406690 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406694 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406698 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406702 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406704 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 406711 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 406711 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406714 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 406718 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406723 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406728 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406733 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406739 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406746 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406749 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406752 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406755 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406760 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406765 */     // GIR_Coverage, 4286,
     /* 406765 */     GIR_EraseRootFromParent_Done,
     /* 406766 */   // Label 8025: @406766
     /* 406766 */   GIM_Try, /*On fail goto*//*Label 8026*/ GIMT_Encode4(406883), // Rule ID 4320 //
     /* 406771 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 406774 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406777 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 406789 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406793 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406797 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406800 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406804 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 406811 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406815 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406819 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406821 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 406828 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 406828 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406831 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 406835 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406840 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406845 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406850 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406856 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406858 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406861 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406863 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406866 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406869 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406872 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406877 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406882 */     // GIR_Coverage, 4320,
     /* 406882 */     GIR_EraseRootFromParent_Done,
     /* 406883 */   // Label 8026: @406883
     /* 406883 */   GIM_Try, /*On fail goto*//*Label 8027*/ GIMT_Encode4(407000), // Rule ID 4322 //
     /* 406888 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 406891 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 406894 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 406902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 406906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 406910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 406914 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 406917 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 406921 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 406928 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 406932 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 406936 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 406938 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 406945 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 406945 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 406948 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 406952 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 406957 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 406962 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 406967 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 406973 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 406975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 406978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 406980 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 406983 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 406986 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 406989 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 406994 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 406999 */     // GIR_Coverage, 4322,
     /* 406999 */     GIR_EraseRootFromParent_Done,
     /* 407000 */   // Label 8027: @407000
     /* 407000 */   GIM_Try, /*On fail goto*//*Label 8028*/ GIMT_Encode4(407123), // Rule ID 6341 //
     /* 407005 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 407008 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407011 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407015 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407019 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 407023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 407027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407031 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 407035 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 407039 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407044 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 407048 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407052 */     // MIs[3] Operand 1
     /* 407052 */     // No operand predicates
     /* 407052 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 407056 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407058 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (DUPi8:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), bsub:{ *:[i32] })
     /* 407058 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s8,
     /* 407061 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi8),
     /* 407065 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407070 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 407074 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 407077 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 407079 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407082 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 407086 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407091 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 407093 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 407096 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407101 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 407104 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 407107 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407112 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407117 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 407122 */     // GIR_Coverage, 6341,
     /* 407122 */     GIR_EraseRootFromParent_Done,
     /* 407123 */   // Label 8028: @407123
     /* 407123 */   GIM_Try, /*On fail goto*//*Label 8029*/ GIMT_Encode4(407246), // Rule ID 6349 //
     /* 407128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407138 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407142 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 407146 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 407150 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407154 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 407158 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 407162 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407167 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 407171 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407175 */     // MIs[3] Operand 1
     /* 407175 */     // No operand predicates
     /* 407175 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 407179 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407181 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), 0:{ *:[i64] })  =>  (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (DUPi8:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), bsub:{ *:[i32] })
     /* 407181 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s8,
     /* 407184 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::DUPi8),
     /* 407188 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407193 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 407197 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/3, // Immn
     /* 407200 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 407202 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407205 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 407209 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407214 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 407216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 407219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407221 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407224 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 407227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 407230 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407235 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407240 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 407245 */     // GIR_Coverage, 6349,
     /* 407245 */     GIR_EraseRootFromParent_Done,
     /* 407246 */   // Label 8029: @407246
     /* 407246 */   GIM_Try, /*On fail goto*//*Label 8030*/ GIMT_Encode4(407334), // Rule ID 1969 //
     /* 407251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 407254 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407257 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407264 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407268 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407272 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407276 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 407280 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407284 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407297 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 407301 */     // MIs[2] Operand 1
     /* 407301 */     // No operand predicates
     /* 407301 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407305 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407309 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 407313 */     // MIs[3] Operand 1
     /* 407313 */     // No operand predicates
     /* 407313 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407315 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx2), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx2)
     /* 407315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407320 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 407322 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 407325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 407329 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx2
     /* 407332 */     GIR_RootConstrainSelectedInstOperands,
     /* 407333 */     // GIR_Coverage, 1969,
     /* 407333 */     GIR_EraseRootFromParent_Done,
     /* 407334 */   // Label 8030: @407334
     /* 407334 */   GIM_Try, /*On fail goto*//*Label 8031*/ GIMT_Encode4(407433), // Rule ID 6338 //
     /* 407339 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 407342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407345 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407349 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407353 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407357 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 407361 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407365 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407369 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407373 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 407377 */     // MIs[2] Operand 1
     /* 407377 */     // No operand predicates
     /* 407377 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407381 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407385 */     // MIs[3] Operand 1
     /* 407385 */     // No operand predicates
     /* 407385 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407387 */     // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (vector_extract:{ *:[i8] } nxv16i8:{ *:[nxv16i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn)
     /* 407387 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407390 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407394 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407399 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 407405 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407410 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 407415 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407418 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407420 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407422 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407425 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407428 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407431 */     GIR_RootConstrainSelectedInstOperands,
     /* 407432 */     // GIR_Coverage, 6338,
     /* 407432 */     GIR_EraseRootFromParent_Done,
     /* 407433 */   // Label 8031: @407433
     /* 407433 */   GIM_Try, /*On fail goto*//*Label 8032*/ GIMT_Encode4(407532), // Rule ID 6346 //
     /* 407438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407456 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 407460 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407464 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407468 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407472 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 407476 */     // MIs[2] Operand 1
     /* 407476 */     // No operand predicates
     /* 407476 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407480 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407484 */     // MIs[3] Operand 1
     /* 407484 */     // No operand predicates
     /* 407484 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407486 */     // (vector_insert:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immd, (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$Rm, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$Immn)
     /* 407486 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407489 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407493 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407498 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // Rm
     /* 407504 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407509 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 407514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407519 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 407521 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407524 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407527 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407530 */     GIR_RootConstrainSelectedInstOperands,
     /* 407531 */     // GIR_Coverage, 6346,
     /* 407531 */     GIR_EraseRootFromParent_Done,
     /* 407532 */   // Label 8032: @407532
     /* 407532 */   GIM_Try, /*On fail goto*//*Label 8033*/ GIMT_Encode4(407609), // Rule ID 6340 //
     /* 407537 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 407540 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407543 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407547 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407551 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407555 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407559 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 407563 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407567 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407572 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407576 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407580 */     // MIs[2] Operand 1
     /* 407580 */     // No operand predicates
     /* 407580 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407584 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407588 */     // MIs[3] Operand 1
     /* 407588 */     // No operand predicates
     /* 407588 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407590 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 407590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407595 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 407597 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407600 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 407604 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407607 */     GIR_RootConstrainSelectedInstOperands,
     /* 407608 */     // GIR_Coverage, 6340,
     /* 407608 */     GIR_EraseRootFromParent_Done,
     /* 407609 */   // Label 8033: @407609
     /* 407609 */   GIM_Try, /*On fail goto*//*Label 8034*/ GIMT_Encode4(407717), // Rule ID 6342 //
     /* 407614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 407617 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407624 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407628 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407632 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407636 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 407640 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407644 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 407649 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407653 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407657 */     // MIs[2] Operand 1
     /* 407657 */     // No operand predicates
     /* 407657 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407661 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407665 */     // MIs[3] Operand 1
     /* 407665 */     // No operand predicates
     /* 407665 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407667 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i8] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 407667 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407670 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 407674 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407679 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 407682 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 407686 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 407689 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407694 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 407699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407704 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 407706 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407709 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407712 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407715 */     GIR_RootConstrainSelectedInstOperands,
     /* 407716 */     // GIR_Coverage, 6342,
     /* 407716 */     GIR_EraseRootFromParent_Done,
     /* 407717 */   // Label 8034: @407717
     /* 407717 */   GIM_Try, /*On fail goto*//*Label 8035*/ GIMT_Encode4(407794), // Rule ID 6348 //
     /* 407722 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407732 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407736 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407740 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407744 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 407748 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407752 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407757 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407761 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407765 */     // MIs[2] Operand 1
     /* 407765 */     // No operand predicates
     /* 407765 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407769 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407773 */     // MIs[3] Operand 1
     /* 407773 */     // No operand predicates
     /* 407773 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407775 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$Immn)
     /* 407775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407780 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 407782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407785 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 407789 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407792 */     GIR_RootConstrainSelectedInstOperands,
     /* 407793 */     // GIR_Coverage, 6348,
     /* 407793 */     GIR_EraseRootFromParent_Done,
     /* 407794 */   // Label 8035: @407794
     /* 407794 */   GIM_Try, /*On fail goto*//*Label 8036*/ GIMT_Encode4(407902), // Rule ID 6350 //
     /* 407799 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407802 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407805 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407809 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 407817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 407821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 407825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 407829 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 407834 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 407838 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407842 */     // MIs[2] Operand 1
     /* 407842 */     // No operand predicates
     /* 407842 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 407846 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 407850 */     // MIs[3] Operand 1
     /* 407850 */     // No operand predicates
     /* 407850 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 407852 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (vector_extract:{ *:[i32] } V64:{ *:[v8i8] }:$Rn, (imm:{ *:[i64] }):$Immn), (imm:{ *:[i64] }):$Immd)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$src, (imm:{ *:[i64] }):$Immd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, V64:{ *:[v8i8] }:$Rn, dsub:{ *:[i32] }), (imm:{ *:[i64] }):$Immn)
     /* 407852 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 407855 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 407859 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407864 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 407867 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 407871 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 407874 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407879 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 407884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 407887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407889 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 407891 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Immd
     /* 407894 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407897 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // Immn
     /* 407900 */     GIR_RootConstrainSelectedInstOperands,
     /* 407901 */     // GIR_Coverage, 6350,
     /* 407901 */     GIR_EraseRootFromParent_Done,
     /* 407902 */   // Label 8036: @407902
     /* 407902 */   GIM_Try, /*On fail goto*//*Label 8037*/ GIMT_Encode4(407981), // Rule ID 6265 //
     /* 407907 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 407910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 407921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 407925 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 407929 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 407933 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 407935 */     // (vector_insert:{ *:[v16i8] } (undef:{ *:[v16i8] }), GPR32:{ *:[i32] }:$Rn, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[f32] } GPR32:{ *:[i32] }:$Rn, FPR32:{ *:[i32] }), ssub:{ *:[i32] })
     /* 407935 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 407938 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 407942 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 407947 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rn
     /* 407951 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 407959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 407961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 407964 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 407967 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 407970 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407975 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 407980 */     // GIR_Coverage, 6265,
     /* 407980 */     GIR_EraseRootFromParent_Done,
     /* 407981 */   // Label 8037: @407981
     /* 407981 */   GIM_Try, /*On fail goto*//*Label 8038*/ GIMT_Encode4(408060), // Rule ID 7074 //
     /* 407986 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 407989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 407992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 407996 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408000 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 408004 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408008 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408011 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 408015 */     // MIs[1] Rn
     /* 408015 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 408019 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 408024 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 408028 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408032 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 408036 */     // MIs[2] Operand 1
     /* 408036 */     // No operand predicates
     /* 408036 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408038 */     // (vector_insert:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (LD1i8:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 408038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 408041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 408045 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 408048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 408052 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408058 */     GIR_RootConstrainSelectedInstOperands,
     /* 408059 */     // GIR_Coverage, 7074,
     /* 408059 */     GIR_EraseRootFromParent_Done,
     /* 408060 */   // Label 8038: @408060
     /* 408060 */   GIM_Try, /*On fail goto*//*Label 8039*/ GIMT_Encode4(408146), // Rule ID 7075 //
     /* 408065 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 408068 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408071 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408079 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 408083 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408087 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408090 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 408094 */     GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 408101 */     // MIs[1] Rn
     /* 408101 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 408105 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 408110 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 408114 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408118 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 408122 */     // MIs[2] Operand 1
     /* 408122 */     // No operand predicates
     /* 408122 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408124 */     // (vector_insert:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (LD1i8:{ *:[v16i8] } VecListOne128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx, GPR64sp:{ *:[i64] }:$Rn)
     /* 408124 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1i8),
     /* 408127 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408129 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 408131 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 408134 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 408138 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408144 */     GIR_RootConstrainSelectedInstOperands,
     /* 408145 */     // GIR_Coverage, 7075,
     /* 408145 */     GIR_EraseRootFromParent_Done,
     /* 408146 */   // Label 8039: @408146
     /* 408146 */   GIM_Try, /*On fail goto*//*Label 8040*/ GIMT_Encode4(408200), // Rule ID 1965 //
     /* 408151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 408154 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 408157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408164 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408168 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 408172 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 408176 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408180 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 408184 */     // MIs[1] Operand 1
     /* 408184 */     // No operand predicates
     /* 408184 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 408186 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, GPR32:{ *:[i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (INSvi8gpr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, (imm:{ *:[i64] }):$idx, GPR32:{ *:[i32] }:$Rn)
     /* 408186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8gpr),
     /* 408189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408191 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 408193 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 408196 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 408198 */     GIR_RootConstrainSelectedInstOperands,
     /* 408199 */     // GIR_Coverage, 1965,
     /* 408199 */     GIR_EraseRootFromParent_Done,
     /* 408200 */   // Label 8040: @408200
     /* 408200 */   GIM_Try, /*On fail goto*//*Label 8041*/ GIMT_Encode4(408306), // Rule ID 6308 //
     /* 408205 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 408208 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408211 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408215 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408219 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 408223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 408227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 408231 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 408235 */     // MIs[1] Operand 1
     /* 408235 */     // No operand predicates
     /* 408235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 408237 */     // (vector_insert:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, FPR8:{ *:[i8] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm)  =>  (INSvi8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$imm, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rm, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 408237 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 408240 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 408244 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408249 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 408251 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 408254 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 408258 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408263 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 408266 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 408270 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 408273 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408278 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 408283 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 408288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::INSvi8lane),
     /* 408291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408293 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 408295 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 408298 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408301 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 408304 */     GIR_RootConstrainSelectedInstOperands,
     /* 408305 */     // GIR_Coverage, 6308,
     /* 408305 */     GIR_EraseRootFromParent_Done,
     /* 408306 */   // Label 8041: @408306
     /* 408306 */   GIM_Reject,
     /* 408307 */ // Label 8011: @408307
     /* 408307 */ GIM_Reject,
     /* 408308 */ // Label 7804: @408308
     /* 408308 */ GIM_Try, /*On fail goto*//*Label 8042*/ GIMT_Encode4(408432), // Rule ID 11978 //
     /* 408313 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 408316 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 408319 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 408322 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408325 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408329 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 408333 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 408337 */   // (vector_insert:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv2f16] } ZPR:{ *:[nxv2f16] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f16] }:$src)
     /* 408337 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 408340 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 408344 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408349 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 408353 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 408355 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 408358 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 408362 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408367 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 408370 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 408373 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 408375 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 408378 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 408382 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408387 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 408390 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 408392 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 408395 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 408399 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408404 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 408407 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 408410 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 408413 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 408416 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408418 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 408421 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 408423 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 408425 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408428 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 408430 */   GIR_RootConstrainSelectedInstOperands,
     /* 408431 */   // GIR_Coverage, 11978,
     /* 408431 */   GIR_EraseRootFromParent_Done,
     /* 408432 */ // Label 8042: @408432
     /* 408432 */ GIM_Reject,
     /* 408433 */ // Label 7805: @408433
     /* 408433 */ GIM_Try, /*On fail goto*//*Label 8043*/ GIMT_Encode4(408557), // Rule ID 11981 //
     /* 408438 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 408441 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 408444 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 408447 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408454 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 408458 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 408462 */   // (vector_insert:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_S:{ *:[nxv2f32] } ZPR:{ *:[nxv2f32] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), ?:{ *:[f32] }:$src)
     /* 408462 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 408465 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 408469 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408474 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 408478 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 408480 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 408483 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 408487 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408492 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 408495 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 408498 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 408500 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 408503 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 408507 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408512 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 408515 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 408517 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 408520 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 408524 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408529 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 408532 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 408535 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 408538 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 408541 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408543 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
     /* 408546 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 408548 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 408550 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408553 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 408555 */   GIR_RootConstrainSelectedInstOperands,
     /* 408556 */   // GIR_Coverage, 11981,
     /* 408556 */   GIR_EraseRootFromParent_Done,
     /* 408557 */ // Label 8043: @408557
     /* 408557 */ GIM_Reject,
     /* 408558 */ // Label 7806: @408558
     /* 408558 */ GIM_Try, /*On fail goto*//*Label 8044*/ GIMT_Encode4(410535),
     /* 408563 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 408566 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 408569 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 408572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408576 */   GIM_Try, /*On fail goto*//*Label 8045*/ GIMT_Encode4(408685), // Rule ID 4450 //
     /* 408581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408585 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 408591 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 408593 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408597 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408601 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408604 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 408608 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 408612 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 408616 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408618 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 408625 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 408625 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 408628 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 408632 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408637 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 408642 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 408647 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 408652 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408658 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 408663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408665 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 408668 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408671 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 408674 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408679 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 408684 */     // GIR_Coverage, 4450,
     /* 408684 */     GIR_EraseRootFromParent_Done,
     /* 408685 */   // Label 8045: @408685
     /* 408685 */   GIM_Try, /*On fail goto*//*Label 8046*/ GIMT_Encode4(408794), // Rule ID 4451 //
     /* 408690 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408694 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 408700 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 408702 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408706 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408710 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408713 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 408717 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 408721 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 408725 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408727 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 408734 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 408734 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 408737 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 408741 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408746 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 408751 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 408756 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 408761 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408767 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 408772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408774 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 408777 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408780 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 408783 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408788 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 408793 */     // GIR_Coverage, 4451,
     /* 408793 */     GIR_EraseRootFromParent_Done,
     /* 408794 */   // Label 8046: @408794
     /* 408794 */   GIM_Try, /*On fail goto*//*Label 8047*/ GIMT_Encode4(408903), // Rule ID 4558 //
     /* 408799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408803 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 408809 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 408811 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408815 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408819 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408822 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 408826 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 408830 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 408834 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408836 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 408843 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 408843 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 408846 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 408850 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408855 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 408860 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 408865 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 408870 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408876 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 408881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408883 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 408886 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408889 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 408892 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 408897 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 408902 */     // GIR_Coverage, 4558,
     /* 408902 */     GIR_EraseRootFromParent_Done,
     /* 408903 */   // Label 8047: @408903
     /* 408903 */   GIM_Try, /*On fail goto*//*Label 8048*/ GIMT_Encode4(409012), // Rule ID 4559 //
     /* 408908 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 408912 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 408918 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 408920 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 408924 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 408928 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 408931 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 408935 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 408939 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 408943 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 408945 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 408952 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 408952 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 408955 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 408959 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 408964 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 408969 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 408974 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 408979 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 408985 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 408987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 408990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 408992 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 408995 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 408998 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409001 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409006 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409011 */     // GIR_Coverage, 4559,
     /* 409011 */     GIR_EraseRootFromParent_Done,
     /* 409012 */   // Label 8048: @409012
     /* 409012 */   GIM_Try, /*On fail goto*//*Label 8049*/ GIMT_Encode4(409117), // Rule ID 4456 //
     /* 409017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409025 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409029 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409033 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409036 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409040 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409044 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409048 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409050 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 409057 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 409057 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409060 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 409064 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409069 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409074 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 409079 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 409084 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409090 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409097 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409100 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409103 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409106 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409111 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409116 */     // GIR_Coverage, 4456,
     /* 409116 */     GIR_EraseRootFromParent_Done,
     /* 409117 */   // Label 8049: @409117
     /* 409117 */   GIM_Try, /*On fail goto*//*Label 8050*/ GIMT_Encode4(409222), // Rule ID 4458 //
     /* 409122 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409126 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409130 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409134 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409138 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409141 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409145 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409149 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409153 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409155 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 409162 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 409162 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409165 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 409169 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409174 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409179 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 409184 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 409189 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409195 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409202 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409205 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409208 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409211 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409216 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409221 */     // GIR_Coverage, 4458,
     /* 409221 */     GIR_EraseRootFromParent_Done,
     /* 409222 */   // Label 8050: @409222
     /* 409222 */   GIM_Try, /*On fail goto*//*Label 8051*/ GIMT_Encode4(409327), // Rule ID 4564 //
     /* 409227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409243 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409246 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409250 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409254 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409258 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409260 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 409267 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroW:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 409267 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409270 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroW),
     /* 409274 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409279 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409284 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 409289 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 409294 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409300 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409307 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409310 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409313 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409316 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409321 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409326 */     // GIR_Coverage, 4564,
     /* 409326 */     GIR_EraseRootFromParent_Done,
     /* 409327 */   // Label 8051: @409327
     /* 409327 */   GIM_Try, /*On fail goto*//*Label 8052*/ GIMT_Encode4(409432), // Rule ID 4566 //
     /* 409332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409340 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409344 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409348 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409351 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409355 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409359 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409363 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409365 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 409372 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDroX:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend), dsub:{ *:[i32] })
     /* 409372 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409375 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDroX),
     /* 409379 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409384 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409389 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 409394 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 409399 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409405 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409407 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409410 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409412 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409415 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409418 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409421 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409426 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409431 */     // GIR_Coverage, 4566,
     /* 409431 */     GIR_EraseRootFromParent_Done,
     /* 409432 */   // Label 8052: @409432
     /* 409432 */   GIM_Try, /*On fail goto*//*Label 8053*/ GIMT_Encode4(409536), // Rule ID 4448 //
     /* 409437 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409441 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 409447 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 409449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409457 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409460 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409464 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409468 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409472 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409474 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 409481 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 409481 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409484 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 409488 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409493 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409498 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 409503 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409509 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409516 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409519 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409522 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409525 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409530 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409535 */     // GIR_Coverage, 4448,
     /* 409535 */     GIR_EraseRootFromParent_Done,
     /* 409536 */   // Label 8053: @409536
     /* 409536 */   GIM_Try, /*On fail goto*//*Label 8054*/ GIMT_Encode4(409640), // Rule ID 4449 //
     /* 409541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409545 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 409551 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 409553 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409557 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409561 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409564 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409568 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409572 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409576 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409578 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 409585 */     // (vector_insert:{ *:[nxv2i64] } immAllZerosV:{ *:[nxv2i64] }, (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 409585 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409588 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 409592 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409597 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409602 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 409607 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409613 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409615 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409618 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409620 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409623 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409626 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409629 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409634 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409639 */     // GIR_Coverage, 4449,
     /* 409639 */     GIR_EraseRootFromParent_Done,
     /* 409640 */   // Label 8054: @409640
     /* 409640 */   GIM_Try, /*On fail goto*//*Label 8055*/ GIMT_Encode4(409744), // Rule ID 4556 //
     /* 409645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409649 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 409655 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 409657 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409661 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409665 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409668 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409672 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409676 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409680 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409682 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 409689 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 409689 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409692 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 409696 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409701 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409706 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 409711 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409717 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409719 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409722 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409724 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409727 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409730 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409733 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409738 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409743 */     // GIR_Coverage, 4556,
     /* 409743 */     GIR_EraseRootFromParent_Done,
     /* 409744 */   // Label 8055: @409744
     /* 409744 */   GIM_Try, /*On fail goto*//*Label 8056*/ GIMT_Encode4(409848), // Rule ID 4557 //
     /* 409749 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409753 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 409759 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 409761 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409765 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409769 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409772 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409776 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409780 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409784 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409786 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 409793 */     // (vector_insert:{ *:[nxv2f64] } immAllZerosV:{ *:[nxv2f64] }, (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 409793 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409796 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 409800 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409805 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409810 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 409815 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409821 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409823 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409826 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409828 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409837 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409842 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409847 */     // GIR_Coverage, 4557,
     /* 409847 */     GIR_EraseRootFromParent_Done,
     /* 409848 */   // Label 8056: @409848
     /* 409848 */   GIM_Try, /*On fail goto*//*Label 8057*/ GIMT_Encode4(409948), // Rule ID 4452 //
     /* 409853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409869 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409872 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409876 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409880 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409884 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409886 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 409893 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 409893 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409896 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 409900 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 409905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 409910 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 409915 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 409921 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 409923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 409926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 409928 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 409931 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 409934 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 409937 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 409942 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 409947 */     // GIR_Coverage, 4452,
     /* 409947 */     GIR_EraseRootFromParent_Done,
     /* 409948 */   // Label 8057: @409948
     /* 409948 */   GIM_Try, /*On fail goto*//*Label 8058*/ GIMT_Encode4(410048), // Rule ID 4454 //
     /* 409953 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 409957 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 409961 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 409965 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 409969 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 409972 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 409976 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 409980 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 409984 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 409986 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 409993 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (ld:{ *:[i64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 409993 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 409996 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 410000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 410015 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 410021 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 410026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 410031 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 410037 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410042 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410047 */     // GIR_Coverage, 4454,
     /* 410047 */     GIR_EraseRootFromParent_Done,
     /* 410048 */   // Label 8058: @410048
     /* 410048 */   GIM_Try, /*On fail goto*//*Label 8059*/ GIMT_Encode4(410148), // Rule ID 4560 //
     /* 410053 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410057 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 410061 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410065 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 410069 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 410072 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 410076 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 410080 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410084 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410086 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 410093 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDRDui:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset), dsub:{ *:[i32] })
     /* 410093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 410096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRDui),
     /* 410100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 410115 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 410121 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 410126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 410131 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 410137 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410142 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410147 */     // GIR_Coverage, 4560,
     /* 410147 */     GIR_EraseRootFromParent_Done,
     /* 410148 */   // Label 8059: @410148
     /* 410148 */   GIM_Try, /*On fail goto*//*Label 8060*/ GIMT_Encode4(410248), // Rule ID 4562 //
     /* 410153 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410157 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 410161 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410165 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 410169 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 410172 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 410176 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 410180 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410184 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410186 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 410193 */     // (vector_insert:{ *:[nxv2f64] } (undef:{ *:[nxv2f64] }), (ld:{ *:[f64] } (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i64] }, (LDURDi:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), dsub:{ *:[i32] })
     /* 410193 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 410196 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURDi),
     /* 410200 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410205 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410210 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 410215 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 410221 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410223 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 410226 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410228 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 410231 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410234 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 410237 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410242 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410247 */     // GIR_Coverage, 4562,
     /* 410247 */     GIR_EraseRootFromParent_Done,
     /* 410248 */   // Label 8060: @410248
     /* 410248 */   GIM_Try, /*On fail goto*//*Label 8061*/ GIMT_Encode4(410312), // Rule ID 12040 //
     /* 410253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 410256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410260 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 410264 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410268 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 410272 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 410276 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 410280 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 410284 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 410288 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 410292 */     // MIs[3] Operand 1
     /* 410292 */     // No operand predicates
     /* 410292 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410296 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 410298 */     // (vector_insert:{ *:[nxv2i64] } (undef:{ *:[nxv2i64] }), (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$Idx)
     /* 410298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 410301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 410303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 410307 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 410310 */     GIR_RootConstrainSelectedInstOperands,
     /* 410311 */     // GIR_Coverage, 12040,
     /* 410311 */     GIR_EraseRootFromParent_Done,
     /* 410312 */   // Label 8061: @410312
     /* 410312 */   GIM_Try, /*On fail goto*//*Label 8062*/ GIMT_Encode4(410423), // Rule ID 11977 //
     /* 410317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 410320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 410324 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 410328 */     // (vector_insert:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } GPR64:{ *:[i64] }:$index)), GPR64:{ *:[i64] }:$src)
     /* 410328 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 410331 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 410335 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410340 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 410344 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 410346 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 410349 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 410353 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410358 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 410361 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 410364 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 410366 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 410369 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 410373 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410378 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 410381 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 410383 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 410386 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 410390 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410395 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 410398 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 410401 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 410404 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 410407 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410409 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_D),
     /* 410412 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 410414 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 410416 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410419 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 410421 */     GIR_RootConstrainSelectedInstOperands,
     /* 410422 */     // GIR_Coverage, 11977,
     /* 410422 */     GIR_EraseRootFromParent_Done,
     /* 410423 */   // Label 8062: @410423
     /* 410423 */   GIM_Try, /*On fail goto*//*Label 8063*/ GIMT_Encode4(410534), // Rule ID 11983 //
     /* 410428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 410431 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 410435 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 410439 */     // (vector_insert:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$vec, FPR64:{ *:[f64] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_D:{ *:[nxv2f64] } ZPR:{ *:[nxv2f64] }:$vec, (CMPEQ_PPzZZ_D:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_D:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_D:{ *:[nxv16i8] } 0:{ *:[i64] }, 1:{ *:[i64] }), (DUP_ZR_D:{ *:[nxv16i8] } ?:{ *:[i64] }:$index)), ?:{ *:[f64] }:$src)
     /* 410439 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 410442 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 410446 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410451 */     GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/3, // index
     /* 410455 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 410457 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 410460 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_D),
     /* 410464 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410469 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 410472 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 410475 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 410477 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 410480 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_D),
     /* 410484 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410489 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 410492 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 410494 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 410497 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_D),
     /* 410501 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410506 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 410509 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 410512 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 410515 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 410518 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410520 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_D),
     /* 410523 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 410525 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 410527 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410530 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 410532 */     GIR_RootConstrainSelectedInstOperands,
     /* 410533 */     // GIR_Coverage, 11983,
     /* 410533 */     GIR_EraseRootFromParent_Done,
     /* 410534 */   // Label 8063: @410534
     /* 410534 */   GIM_Reject,
     /* 410535 */ // Label 8044: @410535
     /* 410535 */ GIM_Reject,
     /* 410536 */ // Label 7807: @410536
     /* 410536 */ GIM_Try, /*On fail goto*//*Label 8064*/ GIMT_Encode4(410687), // Rule ID 11979 //
     /* 410541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 410544 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 410547 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 410550 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 410553 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410557 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 410561 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 410565 */   // (vector_insert:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv4f16] } ZPR:{ *:[nxv4f16] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
     /* 410565 */   GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 410568 */   GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 410572 */   GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410577 */   GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 410583 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 410588 */   GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 410593 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 410596 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 410600 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410605 */   GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 410608 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 410610 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 410613 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 410617 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410622 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 410625 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 410628 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 410630 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 410633 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 410637 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410642 */   GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 410645 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 410647 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 410650 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 410654 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410659 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 410662 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 410665 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 410668 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 410671 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410673 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 410676 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 410678 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 410680 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410683 */   GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 410685 */   GIR_RootConstrainSelectedInstOperands,
     /* 410686 */   // GIR_Coverage, 11979,
     /* 410686 */   GIR_EraseRootFromParent_Done,
     /* 410687 */ // Label 8064: @410687
     /* 410687 */ GIM_Reject,
     /* 410688 */ // Label 7808: @410688
     /* 410688 */ GIM_Try, /*On fail goto*//*Label 8065*/ GIMT_Encode4(412719),
     /* 410693 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 410696 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 410699 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 410702 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410706 */   GIM_Try, /*On fail goto*//*Label 8066*/ GIMT_Encode4(410815), // Rule ID 4414 //
     /* 410711 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410715 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 410721 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 410723 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410727 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 410731 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 410734 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 410738 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 410742 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410746 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410748 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 410755 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 410755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 410758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 410762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410767 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410772 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 410777 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 410782 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 410788 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410790 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 410793 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410795 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 410798 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410801 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 410804 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410809 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410814 */     // GIR_Coverage, 4414,
     /* 410814 */     GIR_EraseRootFromParent_Done,
     /* 410815 */   // Label 8066: @410815
     /* 410815 */   GIM_Try, /*On fail goto*//*Label 8067*/ GIMT_Encode4(410924), // Rule ID 4415 //
     /* 410820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410824 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 410830 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 410832 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410836 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 410840 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 410843 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 410847 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 410851 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410855 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410857 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 410864 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 410864 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 410867 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 410871 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410876 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410881 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 410886 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 410891 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 410897 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 410899 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 410902 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 410904 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 410907 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 410910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 410913 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 410918 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 410923 */     // GIR_Coverage, 4415,
     /* 410923 */     GIR_EraseRootFromParent_Done,
     /* 410924 */   // Label 8067: @410924
     /* 410924 */   GIM_Try, /*On fail goto*//*Label 8068*/ GIMT_Encode4(411033), // Rule ID 4522 //
     /* 410929 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 410933 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 410939 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 410941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 410945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 410949 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 410952 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 410956 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 410960 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 410964 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 410966 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 410973 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 410973 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 410976 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 410980 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 410985 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 410990 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 410995 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411000 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411006 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411013 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411016 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411019 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411022 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411027 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411032 */     // GIR_Coverage, 4522,
     /* 411032 */     GIR_EraseRootFromParent_Done,
     /* 411033 */   // Label 8068: @411033
     /* 411033 */   GIM_Try, /*On fail goto*//*Label 8069*/ GIMT_Encode4(411142), // Rule ID 4523 //
     /* 411038 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411042 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 411048 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 411050 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411054 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411058 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411061 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411065 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411069 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411073 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411075 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 411082 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 411082 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411085 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 411089 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411094 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411099 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 411104 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411109 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411115 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411117 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411120 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411122 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411125 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411128 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411131 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411136 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411141 */     // GIR_Coverage, 4523,
     /* 411141 */     GIR_EraseRootFromParent_Done,
     /* 411142 */   // Label 8069: @411142
     /* 411142 */   GIM_Try, /*On fail goto*//*Label 8070*/ GIMT_Encode4(411247), // Rule ID 4420 //
     /* 411147 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411151 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 411155 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411159 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411163 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411166 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411170 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411174 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411178 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411180 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 411187 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 411187 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411190 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 411194 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411199 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411204 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 411209 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411214 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411220 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411222 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411225 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411227 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411230 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411233 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411236 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411241 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411246 */     // GIR_Coverage, 4420,
     /* 411246 */     GIR_EraseRootFromParent_Done,
     /* 411247 */   // Label 8070: @411247
     /* 411247 */   GIM_Try, /*On fail goto*//*Label 8071*/ GIMT_Encode4(411352), // Rule ID 4422 //
     /* 411252 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411256 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 411260 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411264 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411268 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411271 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411275 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411279 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411283 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411285 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 411292 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 411292 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411295 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 411299 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411304 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411309 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 411314 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411319 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411325 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411327 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411330 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411332 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411335 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411338 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411341 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411346 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411351 */     // GIR_Coverage, 4422,
     /* 411351 */     GIR_EraseRootFromParent_Done,
     /* 411352 */   // Label 8071: @411352
     /* 411352 */   GIM_Try, /*On fail goto*//*Label 8072*/ GIMT_Encode4(411457), // Rule ID 4528 //
     /* 411357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 411365 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411369 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411373 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411376 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411380 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411384 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411388 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411390 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed32),
     /* 411397 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (ro_Windexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroW:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 411397 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411400 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroW),
     /* 411404 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411409 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 411419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411424 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411430 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411432 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411435 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411437 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411440 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411446 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411451 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411456 */     // GIR_Coverage, 4528,
     /* 411456 */     GIR_EraseRootFromParent_Done,
     /* 411457 */   // Label 8072: @411457
     /* 411457 */   GIM_Try, /*On fail goto*//*Label 8073*/ GIMT_Encode4(411562), // Rule ID 4530 //
     /* 411462 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411466 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 411470 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411474 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411478 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411481 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411485 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411489 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411493 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411495 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed32),
     /* 411502 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (ro_Xindexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSroX:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend32:{ *:[i32] }:$extend), ssub:{ *:[i32] })
     /* 411502 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411505 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSroX),
     /* 411509 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411514 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411519 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 411524 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 411529 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411535 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411542 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411551 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411556 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411561 */     // GIR_Coverage, 4530,
     /* 411561 */     GIR_EraseRootFromParent_Done,
     /* 411562 */   // Label 8073: @411562
     /* 411562 */   GIM_Try, /*On fail goto*//*Label 8074*/ GIMT_Encode4(411666), // Rule ID 4412 //
     /* 411567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411571 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 411577 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 411579 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411583 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411587 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411590 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411594 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411598 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411602 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411604 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 411611 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 411611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 411618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411623 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411628 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 411633 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411639 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411646 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411649 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411652 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411655 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411660 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411665 */     // GIR_Coverage, 4412,
     /* 411665 */     GIR_EraseRootFromParent_Done,
     /* 411666 */   // Label 8074: @411666
     /* 411666 */   GIM_Try, /*On fail goto*//*Label 8075*/ GIMT_Encode4(411770), // Rule ID 4413 //
     /* 411671 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411675 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 411681 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 411683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411691 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411694 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411698 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411702 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411706 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411708 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 411715 */     // (vector_insert:{ *:[nxv4i32] } immAllZerosV:{ *:[nxv4i32] }, (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 411715 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411718 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 411722 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411727 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411732 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 411737 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411743 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411745 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411748 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411750 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411753 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411756 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411759 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411764 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411769 */     // GIR_Coverage, 4413,
     /* 411769 */     GIR_EraseRootFromParent_Done,
     /* 411770 */   // Label 8075: @411770
     /* 411770 */   GIM_Try, /*On fail goto*//*Label 8076*/ GIMT_Encode4(411874), // Rule ID 4520 //
     /* 411775 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411779 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 411785 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 411787 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411791 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411795 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411798 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411802 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411806 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411810 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411812 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 411819 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 411819 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411822 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 411826 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411831 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411836 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 411841 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411847 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411849 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411852 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411857 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411860 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411863 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411868 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411873 */     // GIR_Coverage, 4520,
     /* 411873 */     GIR_EraseRootFromParent_Done,
     /* 411874 */   // Label 8076: @411874
     /* 411874 */   GIM_Try, /*On fail goto*//*Label 8077*/ GIMT_Encode4(411978), // Rule ID 4521 //
     /* 411879 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411883 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 411889 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 411891 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411895 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411899 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 411902 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 411906 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 411910 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 411914 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 411916 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 411923 */     // (vector_insert:{ *:[nxv4f32] } immAllZerosV:{ *:[nxv4f32] }, (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 411923 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 411926 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 411930 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 411935 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 411940 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 411945 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 411951 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 411953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 411956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 411958 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 411961 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 411964 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 411967 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 411972 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 411977 */     // GIR_Coverage, 4521,
     /* 411977 */     GIR_EraseRootFromParent_Done,
     /* 411978 */   // Label 8077: @411978
     /* 411978 */   GIM_Try, /*On fail goto*//*Label 8078*/ GIMT_Encode4(412078), // Rule ID 4416 //
     /* 411983 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 411987 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 411991 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 411995 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 411999 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412002 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412006 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412010 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412014 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412016 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 412023 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 412023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 412026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 412030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412035 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412040 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 412045 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412051 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412058 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412061 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412064 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 412067 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412072 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 412077 */     // GIR_Coverage, 4416,
     /* 412077 */     GIR_EraseRootFromParent_Done,
     /* 412078 */   // Label 8078: @412078
     /* 412078 */   GIM_Try, /*On fail goto*//*Label 8079*/ GIMT_Encode4(412178), // Rule ID 4418 //
     /* 412083 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412087 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 412091 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412095 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 412099 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412102 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412106 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412110 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412114 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412116 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 412123 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (ld:{ *:[i32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 412123 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 412126 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 412130 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412135 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412140 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 412145 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412151 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412158 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412161 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412164 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 412167 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412172 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 412177 */     // GIR_Coverage, 4418,
     /* 412177 */     GIR_EraseRootFromParent_Done,
     /* 412178 */   // Label 8079: @412178
     /* 412178 */   GIM_Try, /*On fail goto*//*Label 8080*/ GIMT_Encode4(412278), // Rule ID 4524 //
     /* 412183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 412191 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412195 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 412199 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412202 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412206 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412210 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412214 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412216 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed32),
     /* 412223 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (am_indexed32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDRSui:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, uimm12s4:{ *:[i64] }:$offset), ssub:{ *:[i32] })
     /* 412223 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 412226 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRSui),
     /* 412230 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412235 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412240 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 412245 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412251 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412253 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412256 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412258 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412261 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 412267 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412272 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 412277 */     // GIR_Coverage, 4524,
     /* 412277 */     GIR_EraseRootFromParent_Done,
     /* 412278 */   // Label 8080: @412278
     /* 412278 */   GIM_Try, /*On fail goto*//*Label 8081*/ GIMT_Encode4(412378), // Rule ID 4526 //
     /* 412283 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412287 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 412291 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412295 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 412299 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412302 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412306 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412310 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412314 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412316 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled32),
     /* 412323 */     // (vector_insert:{ *:[nxv4f32] } (undef:{ *:[nxv4f32] }), (ld:{ *:[f32] } (am_unscaled32:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i64] }, (LDURSi:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), ssub:{ *:[i32] })
     /* 412323 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 412326 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURSi),
     /* 412330 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412335 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412340 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 412345 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412351 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412358 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412361 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412364 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 412367 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412372 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 412377 */     // GIR_Coverage, 4526,
     /* 412377 */     GIR_EraseRootFromParent_Done,
     /* 412378 */   // Label 8081: @412378
     /* 412378 */   GIM_Try, /*On fail goto*//*Label 8082*/ GIMT_Encode4(412442), // Rule ID 12038 //
     /* 412383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 412386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412390 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 412394 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412398 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 412402 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 412406 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 412410 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 412414 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 412418 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 412422 */     // MIs[3] Operand 1
     /* 412422 */     // No operand predicates
     /* 412422 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412426 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 412428 */     // (vector_insert:{ *:[nxv4i32] } (undef:{ *:[nxv4i32] }), (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$Idx)
     /* 412428 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 412431 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 412433 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 412437 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 412440 */     GIR_RootConstrainSelectedInstOperands,
     /* 412441 */     // GIR_Coverage, 12038,
     /* 412441 */     GIR_EraseRootFromParent_Done,
     /* 412442 */   // Label 8082: @412442
     /* 412442 */   GIM_Try, /*On fail goto*//*Label 8083*/ GIMT_Encode4(412580), // Rule ID 11976 //
     /* 412447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 412450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 412454 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 412458 */     // (vector_insert:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 412458 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 412461 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412465 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412470 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 412476 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 412481 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 412486 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 412489 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 412493 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412498 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 412501 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 412503 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 412506 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 412510 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412515 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 412518 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 412521 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 412523 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 412526 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 412530 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412535 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 412538 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 412540 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 412543 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 412547 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412552 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 412555 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 412558 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 412561 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 412564 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_S),
     /* 412569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 412571 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 412573 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412576 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 412578 */     GIR_RootConstrainSelectedInstOperands,
     /* 412579 */     // GIR_Coverage, 11976,
     /* 412579 */     GIR_EraseRootFromParent_Done,
     /* 412580 */   // Label 8083: @412580
     /* 412580 */   GIM_Try, /*On fail goto*//*Label 8084*/ GIMT_Encode4(412718), // Rule ID 11982 //
     /* 412585 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 412588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 412592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 412596 */     // (vector_insert:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$vec, FPR32:{ *:[f32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_S:{ *:[nxv4f32] } ZPR:{ *:[nxv4f32] }:$vec, (CMPEQ_PPzZZ_S:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_S:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_S:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_S:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f32] }:$src)
     /* 412596 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 412599 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 412603 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412608 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 412614 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 412619 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 412624 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 412627 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 412631 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412636 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 412639 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 412641 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 412644 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_S),
     /* 412648 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412653 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 412656 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 412659 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 412661 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 412664 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_S),
     /* 412668 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412673 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 412676 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 412678 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 412681 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_S),
     /* 412685 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412690 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 412693 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 412696 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 412699 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 412702 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412704 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_S),
     /* 412707 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 412709 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 412711 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412714 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 412716 */     GIR_RootConstrainSelectedInstOperands,
     /* 412717 */     // GIR_Coverage, 11982,
     /* 412717 */     GIR_EraseRootFromParent_Done,
     /* 412718 */   // Label 8084: @412718
     /* 412718 */   GIM_Reject,
     /* 412719 */ // Label 8065: @412719
     /* 412719 */ GIM_Reject,
     /* 412720 */ // Label 7809: @412720
     /* 412720 */ GIM_Try, /*On fail goto*//*Label 8085*/ GIMT_Encode4(414987),
     /* 412725 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 412728 */   GIM_Try, /*On fail goto*//*Label 8086*/ GIMT_Encode4(412854), // Rule ID 4378 //
     /* 412733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 412736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 412739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412743 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412747 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 412753 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 412755 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412759 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 412763 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412766 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412770 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 412777 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412781 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412785 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412787 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 412794 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 412794 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 412797 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 412801 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412806 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412811 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 412816 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 412821 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412827 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412834 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412837 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412840 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 412843 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412848 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 412853 */     // GIR_Coverage, 4378,
     /* 412853 */     GIR_EraseRootFromParent_Done,
     /* 412854 */   // Label 8086: @412854
     /* 412854 */   GIM_Try, /*On fail goto*//*Label 8087*/ GIMT_Encode4(412980), // Rule ID 4379 //
     /* 412859 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 412862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 412865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412869 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412873 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 412879 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 412881 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 412885 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 412889 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 412892 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 412896 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 412903 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 412907 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 412911 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 412913 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 412920 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 412920 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 412923 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 412927 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 412932 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 412937 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 412942 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 412947 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 412953 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 412955 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 412958 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 412960 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 412963 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 412966 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 412969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 412979 */     // GIR_Coverage, 4379,
     /* 412979 */     GIR_EraseRootFromParent_Done,
     /* 412980 */   // Label 8087: @412980
     /* 412980 */   GIM_Try, /*On fail goto*//*Label 8088*/ GIMT_Encode4(413099), // Rule ID 4486 //
     /* 412985 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 412988 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 412991 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 412995 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 412999 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 413005 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 413007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413015 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413018 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413022 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413026 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413030 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413032 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 413039 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413039 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413042 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 413046 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413051 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413056 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413061 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413066 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413072 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413074 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413077 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413079 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413082 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413085 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413088 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413093 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413098 */     // GIR_Coverage, 4486,
     /* 413098 */     GIR_EraseRootFromParent_Done,
     /* 413099 */   // Label 8088: @413099
     /* 413099 */   GIM_Try, /*On fail goto*//*Label 8089*/ GIMT_Encode4(413218), // Rule ID 4487 //
     /* 413104 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 413107 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413110 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413114 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413118 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 413124 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 413126 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413130 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413134 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413137 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413141 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413145 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413149 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413151 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 413158 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413158 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413161 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 413165 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413170 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413175 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413180 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413185 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413191 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413198 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413201 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413204 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413207 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413212 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413217 */     // GIR_Coverage, 4487,
     /* 413217 */     GIR_EraseRootFromParent_Done,
     /* 413218 */   // Label 8089: @413218
     /* 413218 */   GIM_Try, /*On fail goto*//*Label 8090*/ GIMT_Encode4(413340), // Rule ID 4384 //
     /* 413223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 413226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413233 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413237 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 413241 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413245 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413249 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413252 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413256 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 413263 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413267 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413271 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413273 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 413280 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413280 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413283 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 413287 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413292 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413297 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413302 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413307 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413313 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413315 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413318 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413320 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413323 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413326 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413329 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413334 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413339 */     // GIR_Coverage, 4384,
     /* 413339 */     GIR_EraseRootFromParent_Done,
     /* 413340 */   // Label 8090: @413340
     /* 413340 */   GIM_Try, /*On fail goto*//*Label 8091*/ GIMT_Encode4(413462), // Rule ID 4386 //
     /* 413345 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 413348 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413351 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 413363 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413367 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413371 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413374 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413378 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 413385 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413389 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413393 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413395 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 413402 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413402 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413405 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 413409 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413414 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413419 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413424 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413429 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413435 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413437 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413440 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413442 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413445 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413448 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413451 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413456 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413461 */     // GIR_Coverage, 4386,
     /* 413461 */     GIR_EraseRootFromParent_Done,
     /* 413462 */   // Label 8091: @413462
     /* 413462 */   GIM_Try, /*On fail goto*//*Label 8092*/ GIMT_Encode4(413577), // Rule ID 4492 //
     /* 413467 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 413470 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 413485 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413489 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413493 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413496 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413500 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413504 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413508 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413510 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed16),
     /* 413517 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (ro_Windexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroW:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413517 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413520 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroW),
     /* 413524 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413529 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413534 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413539 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413544 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413550 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413557 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413560 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413563 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413566 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413571 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413576 */     // GIR_Coverage, 4492,
     /* 413576 */     GIR_EraseRootFromParent_Done,
     /* 413577 */   // Label 8092: @413577
     /* 413577 */   GIM_Try, /*On fail goto*//*Label 8093*/ GIMT_Encode4(413692), // Rule ID 4494 //
     /* 413582 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 413585 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413588 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413592 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413596 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 413600 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413604 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413608 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413611 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413615 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413619 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413623 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413625 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed16),
     /* 413632 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (ro_Xindexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHroX:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend16:{ *:[i32] }:$extend), hsub:{ *:[i32] })
     /* 413632 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413635 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHroX),
     /* 413639 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413644 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413649 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 413654 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 413659 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413665 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413667 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413670 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413672 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413675 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413678 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413681 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413686 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413691 */     // GIR_Coverage, 4494,
     /* 413691 */     GIR_EraseRootFromParent_Done,
     /* 413692 */   // Label 8093: @413692
     /* 413692 */   GIM_Try, /*On fail goto*//*Label 8094*/ GIMT_Encode4(413813), // Rule ID 4376 //
     /* 413697 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 413700 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413703 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413707 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413711 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 413717 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 413719 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413723 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413727 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413730 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413734 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 413741 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413745 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413749 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413751 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 413758 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 413758 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413761 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 413765 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413770 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413775 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 413780 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413786 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413788 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413791 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413793 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413796 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413799 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413802 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413807 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413812 */     // GIR_Coverage, 4376,
     /* 413812 */     GIR_EraseRootFromParent_Done,
     /* 413813 */   // Label 8094: @413813
     /* 413813 */   GIM_Try, /*On fail goto*//*Label 8095*/ GIMT_Encode4(413934), // Rule ID 4377 //
     /* 413818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 413821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413832 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 413838 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 413840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413844 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413848 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413851 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413855 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 413862 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413866 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413870 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413872 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 413879 */     // (vector_insert:{ *:[nxv8i16] } immAllZerosV:{ *:[nxv8i16] }, (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 413879 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413882 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 413886 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 413891 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 413896 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 413901 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 413907 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 413909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 413912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 413914 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 413917 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 413920 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 413923 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413928 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 413933 */     // GIR_Coverage, 4377,
     /* 413933 */     GIR_EraseRootFromParent_Done,
     /* 413934 */   // Label 8095: @413934
     /* 413934 */   GIM_Try, /*On fail goto*//*Label 8096*/ GIMT_Encode4(414048), // Rule ID 4484 //
     /* 413939 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 413942 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 413945 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 413949 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 413953 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 413959 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 413961 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 413965 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 413969 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 413972 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 413976 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 413980 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 413984 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 413986 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 413993 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 413993 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 413996 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 414000 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414005 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414010 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414015 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414021 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414023 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414026 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414028 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414031 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414034 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414037 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414042 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414047 */     // GIR_Coverage, 4484,
     /* 414047 */     GIR_EraseRootFromParent_Done,
     /* 414048 */   // Label 8096: @414048
     /* 414048 */   GIM_Try, /*On fail goto*//*Label 8097*/ GIMT_Encode4(414162), // Rule ID 4485 //
     /* 414053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 414056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414067 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 414073 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 414075 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414079 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 414083 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 414086 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 414090 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 414094 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414098 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414100 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 414107 */     // (vector_insert:{ *:[nxv8f16] } immAllZerosV:{ *:[nxv8f16] }, (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 414107 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 414110 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 414114 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414119 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414124 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414129 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414135 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414142 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414145 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414148 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414151 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414156 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414161 */     // GIR_Coverage, 4485,
     /* 414161 */     GIR_EraseRootFromParent_Done,
     /* 414162 */   // Label 8097: @414162
     /* 414162 */   GIM_Try, /*On fail goto*//*Label 8098*/ GIMT_Encode4(414279), // Rule ID 4380 //
     /* 414167 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 414170 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414173 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414177 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414181 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 414185 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414189 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 414193 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 414196 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 414200 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 414207 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 414211 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414215 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414217 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 414224 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 414224 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 414227 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 414231 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414236 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414241 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414246 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414252 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414259 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414262 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414265 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414268 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414273 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414278 */     // GIR_Coverage, 4380,
     /* 414278 */     GIR_EraseRootFromParent_Done,
     /* 414279 */   // Label 8098: @414279
     /* 414279 */   GIM_Try, /*On fail goto*//*Label 8099*/ GIMT_Encode4(414396), // Rule ID 4382 //
     /* 414284 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 414287 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414290 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414294 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414298 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 414302 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414306 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 414310 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 414313 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 414317 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 414324 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 414328 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414332 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414334 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 414341 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (ld:{ *:[i32] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 414341 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 414344 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 414348 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414353 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414358 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414363 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414369 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414376 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414379 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414382 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414385 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414390 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414395 */     // GIR_Coverage, 4382,
     /* 414395 */     GIR_EraseRootFromParent_Done,
     /* 414396 */   // Label 8099: @414396
     /* 414396 */   GIM_Try, /*On fail goto*//*Label 8100*/ GIMT_Encode4(414506), // Rule ID 4488 //
     /* 414401 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 414404 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414407 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414411 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414415 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 414419 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414423 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 414427 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 414430 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 414434 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 414438 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414442 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414444 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed16),
     /* 414451 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (am_indexed16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDRHui:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, uimm12s2:{ *:[i64] }:$offset), hsub:{ *:[i32] })
     /* 414451 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 414454 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRHui),
     /* 414458 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414463 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414468 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414473 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414479 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414486 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414489 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414492 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414495 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414500 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414505 */     // GIR_Coverage, 4488,
     /* 414505 */     GIR_EraseRootFromParent_Done,
     /* 414506 */   // Label 8100: @414506
     /* 414506 */   GIM_Try, /*On fail goto*//*Label 8101*/ GIMT_Encode4(414616), // Rule ID 4490 //
     /* 414511 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 414514 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414517 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 414529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 414537 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 414540 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 414544 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 414548 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414552 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 414554 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled16),
     /* 414561 */     // (vector_insert:{ *:[nxv8f16] } (undef:{ *:[nxv8f16] }), (ld:{ *:[f16] } (am_unscaled16:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i64] }, (LDURHi:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), hsub:{ *:[i32] })
     /* 414561 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 414564 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURHi),
     /* 414568 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414573 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 414578 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 414583 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 414589 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414591 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 414594 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 414596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 414599 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414602 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 414605 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414610 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414615 */     // GIR_Coverage, 4490,
     /* 414615 */     GIR_EraseRootFromParent_Done,
     /* 414616 */   // Label 8101: @414616
     /* 414616 */   GIM_Try, /*On fail goto*//*Label 8102*/ GIMT_Encode4(414690), // Rule ID 12036 //
     /* 414621 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 414624 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 414627 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414630 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414634 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 414638 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 414642 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 414646 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 414650 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 414654 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 414658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 414662 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 414666 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 414670 */     // MIs[3] Operand 1
     /* 414670 */     // No operand predicates
     /* 414670 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 414674 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 414676 */     // (vector_insert:{ *:[nxv8i16] } (undef:{ *:[nxv8i16] }), (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$Idx)
     /* 414676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 414679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 414681 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 414685 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 414688 */     GIR_RootConstrainSelectedInstOperands,
     /* 414689 */     // GIR_Coverage, 12036,
     /* 414689 */     GIR_EraseRootFromParent_Done,
     /* 414690 */   // Label 8102: @414690
     /* 414690 */   GIM_Try, /*On fail goto*//*Label 8103*/ GIMT_Encode4(414838), // Rule ID 11975 //
     /* 414695 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 414698 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 414701 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414704 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 414712 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 414716 */     // (vector_insert:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 414716 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 414719 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 414723 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414728 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 414734 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 414739 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 414744 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 414747 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 414751 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414756 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 414759 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 414761 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 414764 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
     /* 414768 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414773 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 414776 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 414779 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 414781 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 414784 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 414788 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414793 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 414796 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 414798 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 414801 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
     /* 414805 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414810 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 414813 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 414816 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 414819 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 414822 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414824 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_H),
     /* 414827 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 414829 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 414831 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414834 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 414836 */     GIR_RootConstrainSelectedInstOperands,
     /* 414837 */     // GIR_Coverage, 11975,
     /* 414837 */     GIR_EraseRootFromParent_Done,
     /* 414838 */   // Label 8103: @414838
     /* 414838 */   GIM_Try, /*On fail goto*//*Label 8104*/ GIMT_Encode4(414986), // Rule ID 11980 //
     /* 414843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 414846 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 414849 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 414852 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 414856 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 414860 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 414864 */     // (vector_insert:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$vec, FPR16:{ *:[f16] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmV_H:{ *:[nxv8f16] } ZPR:{ *:[nxv8f16] }:$vec, (CMPEQ_PPzZZ_H:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_H:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_H:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_H:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), ?:{ *:[f16] }:$src)
     /* 414864 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 414867 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 414871 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414876 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 414882 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 414887 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 414892 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 414895 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 414899 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414904 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 414907 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 414909 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 414912 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_H),
     /* 414916 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414921 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 414924 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 414927 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 414929 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 414932 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_H),
     /* 414936 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414941 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 414944 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 414946 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 414949 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_H),
     /* 414953 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 414958 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 414961 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 414964 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 414967 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 414970 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 414972 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmV_H),
     /* 414975 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 414977 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 414979 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 414982 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 414984 */     GIR_RootConstrainSelectedInstOperands,
     /* 414985 */     // GIR_Coverage, 11980,
     /* 414985 */     GIR_EraseRootFromParent_Done,
     /* 414986 */   // Label 8104: @414986
     /* 414986 */   GIM_Reject,
     /* 414987 */ // Label 8085: @414987
     /* 414987 */ GIM_Reject,
     /* 414988 */ // Label 7810: @414988
     /* 414988 */ GIM_Try, /*On fail goto*//*Label 8105*/ GIMT_Encode4(417107),
     /* 414993 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 414996 */   GIM_Try, /*On fail goto*//*Label 8106*/ GIMT_Encode4(415115), // Rule ID 4306 //
     /* 415001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 415004 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415007 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415011 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415015 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 415021 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 415023 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415027 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415031 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415034 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415038 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415042 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415046 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415048 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 415055 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415055 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415058 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 415062 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415067 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415072 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415077 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415082 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415088 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415090 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415093 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415095 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415101 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415104 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415109 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415114 */     // GIR_Coverage, 4306,
     /* 415114 */     GIR_EraseRootFromParent_Done,
     /* 415115 */   // Label 8106: @415115
     /* 415115 */   GIM_Try, /*On fail goto*//*Label 8107*/ GIMT_Encode4(415234), // Rule ID 4307 //
     /* 415120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 415123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415130 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415134 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 415140 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 415142 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415146 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415150 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415153 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415157 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415161 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415165 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415167 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 415174 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415174 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415177 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 415181 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415186 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415191 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415196 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415201 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415207 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415214 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415217 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415220 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415223 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415228 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415233 */     // GIR_Coverage, 4307,
     /* 415233 */     GIR_EraseRootFromParent_Done,
     /* 415234 */   // Label 8107: @415234
     /* 415234 */   GIM_Try, /*On fail goto*//*Label 8108*/ GIMT_Encode4(415360), // Rule ID 4342 //
     /* 415239 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 415242 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415253 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 415259 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 415261 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415265 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415269 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415272 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415276 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 415283 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415287 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415291 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415293 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 415300 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415300 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415303 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 415307 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415312 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415317 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415322 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415327 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415333 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415340 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415343 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415346 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415349 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415354 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415359 */     // GIR_Coverage, 4342,
     /* 415359 */     GIR_EraseRootFromParent_Done,
     /* 415360 */   // Label 8108: @415360
     /* 415360 */   GIM_Try, /*On fail goto*//*Label 8109*/ GIMT_Encode4(415486), // Rule ID 4343 //
     /* 415365 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 415368 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415371 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415375 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415379 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 415385 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 415387 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415391 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415395 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415398 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415402 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 415409 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415413 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415417 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415419 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 415426 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415426 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415429 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 415433 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415438 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415443 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415448 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415453 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415459 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415466 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415469 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415472 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415475 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415480 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415485 */     // GIR_Coverage, 4343,
     /* 415485 */     GIR_EraseRootFromParent_Done,
     /* 415486 */   // Label 8109: @415486
     /* 415486 */   GIM_Try, /*On fail goto*//*Label 8110*/ GIMT_Encode4(415601), // Rule ID 4312 //
     /* 415491 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 415494 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415497 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 415509 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415513 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415517 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415520 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415524 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415528 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415532 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415534 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 415541 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415541 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415544 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 415548 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415553 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415568 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415574 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415581 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415584 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415587 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415590 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415595 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415600 */     // GIR_Coverage, 4312,
     /* 415600 */     GIR_EraseRootFromParent_Done,
     /* 415601 */   // Label 8110: @415601
     /* 415601 */   GIM_Try, /*On fail goto*//*Label 8111*/ GIMT_Encode4(415716), // Rule ID 4314 //
     /* 415606 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 415609 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415612 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415616 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415620 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 415624 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415628 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415632 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415635 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415639 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415643 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415647 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415649 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 415656 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 415663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415668 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415673 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415678 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415683 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415689 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415696 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415699 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415702 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415705 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415710 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415715 */     // GIR_Coverage, 4314,
     /* 415715 */     GIR_EraseRootFromParent_Done,
     /* 415716 */   // Label 8111: @415716
     /* 415716 */   GIM_Try, /*On fail goto*//*Label 8112*/ GIMT_Encode4(415838), // Rule ID 4348 //
     /* 415721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 415724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415731 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415735 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 415739 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415743 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415747 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415750 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415754 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 415761 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415765 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415769 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415771 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed8),
     /* 415778 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (ro_Windexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroW:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415778 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415781 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroW),
     /* 415785 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415790 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415795 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415800 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415805 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415811 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415813 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415816 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415818 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415821 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415824 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415827 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415832 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415837 */     // GIR_Coverage, 4348,
     /* 415837 */     GIR_EraseRootFromParent_Done,
     /* 415838 */   // Label 8112: @415838
     /* 415838 */   GIM_Try, /*On fail goto*//*Label 8113*/ GIMT_Encode4(415960), // Rule ID 4350 //
     /* 415843 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 415846 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415849 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 415861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415869 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415872 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 415876 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 415883 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 415887 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 415891 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 415893 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed8),
     /* 415900 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (ro_Xindexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBroX:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend8:{ *:[i32] }:$extend), bsub:{ *:[i32] })
     /* 415900 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 415903 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBroX),
     /* 415907 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 415912 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 415917 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 415922 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 415927 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 415933 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 415935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 415938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 415940 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 415943 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 415946 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 415949 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415954 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 415959 */     // GIR_Coverage, 4350,
     /* 415959 */     GIR_EraseRootFromParent_Done,
     /* 415960 */   // Label 8113: @415960
     /* 415960 */   GIM_Try, /*On fail goto*//*Label 8114*/ GIMT_Encode4(416074), // Rule ID 4304 //
     /* 415965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 415968 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 415971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 415975 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 415979 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 415985 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 415987 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 415991 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 415995 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 415998 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416002 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416006 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416010 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416012 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 416019 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 416019 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416022 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 416026 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416031 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416036 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416041 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416047 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416054 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416057 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416060 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416063 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416068 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416073 */     // GIR_Coverage, 4304,
     /* 416073 */     GIR_EraseRootFromParent_Done,
     /* 416074 */   // Label 8114: @416074
     /* 416074 */   GIM_Try, /*On fail goto*//*Label 8115*/ GIMT_Encode4(416188), // Rule ID 4305 //
     /* 416079 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 416082 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416093 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 416099 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 416101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416109 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416112 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416116 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416120 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416124 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416126 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 416133 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 416133 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416136 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 416140 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416145 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416150 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416155 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416161 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416171 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416174 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416177 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416182 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416187 */     // GIR_Coverage, 4305,
     /* 416187 */     GIR_EraseRootFromParent_Done,
     /* 416188 */   // Label 8115: @416188
     /* 416188 */   GIM_Try, /*On fail goto*//*Label 8116*/ GIMT_Encode4(416309), // Rule ID 4340 //
     /* 416193 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416196 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416199 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416203 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416207 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 416213 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 416215 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416219 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416223 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416226 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416230 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 416237 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416241 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416245 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416247 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 416254 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 416254 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416257 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 416261 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416266 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416271 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416276 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416282 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416284 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416287 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416289 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416292 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416295 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416298 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416303 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416308 */     // GIR_Coverage, 4340,
     /* 416308 */     GIR_EraseRootFromParent_Done,
     /* 416309 */   // Label 8116: @416309
     /* 416309 */   GIM_Try, /*On fail goto*//*Label 8117*/ GIMT_Encode4(416430), // Rule ID 4341 //
     /* 416314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416317 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416328 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 416334 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 416336 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416340 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416344 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416347 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416351 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 416358 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416362 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416366 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416368 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 416375 */     // (vector_insert:{ *:[nxv16i8] } immAllZerosV:{ *:[nxv16i8] }, (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 416375 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416378 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 416382 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416387 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416392 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416397 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416403 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416405 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416408 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416410 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416413 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416416 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416419 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416424 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416429 */     // GIR_Coverage, 4341,
     /* 416429 */     GIR_EraseRootFromParent_Done,
     /* 416430 */   // Label 8117: @416430
     /* 416430 */   GIM_Try, /*On fail goto*//*Label 8118*/ GIMT_Encode4(416540), // Rule ID 4308 //
     /* 416435 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 416438 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416441 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416445 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416449 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 416453 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416457 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416461 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416464 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416468 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416472 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416476 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416478 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 416485 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 416485 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416488 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 416492 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416497 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416502 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416507 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416513 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416520 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416523 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416529 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416534 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416539 */     // GIR_Coverage, 4308,
     /* 416539 */     GIR_EraseRootFromParent_Done,
     /* 416540 */   // Label 8118: @416540
     /* 416540 */   GIM_Try, /*On fail goto*//*Label 8119*/ GIMT_Encode4(416650), // Rule ID 4310 //
     /* 416545 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s8,
     /* 416548 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416551 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416555 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416559 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 416563 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416567 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416571 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416574 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416578 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416582 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416586 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416588 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 416595 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i8] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 416595 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416598 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 416602 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416607 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416612 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416617 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416623 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416630 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416633 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416636 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416639 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416644 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416649 */     // GIR_Coverage, 4310,
     /* 416649 */     GIR_EraseRootFromParent_Done,
     /* 416650 */   // Label 8119: @416650
     /* 416650 */   GIM_Try, /*On fail goto*//*Label 8120*/ GIMT_Encode4(416767), // Rule ID 4344 //
     /* 416655 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416658 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416661 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416665 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416669 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 416673 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416677 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416681 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416684 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416688 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 416695 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416699 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416703 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416705 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed8),
     /* 416712 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (am_indexed8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDRBui:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, uimm12s1:{ *:[i64] }:$offset), bsub:{ *:[i32] })
     /* 416712 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416715 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDRBui),
     /* 416719 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416724 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416729 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416734 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416740 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416747 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416750 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416753 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416756 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416761 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416766 */     // GIR_Coverage, 4344,
     /* 416766 */     GIR_EraseRootFromParent_Done,
     /* 416767 */   // Label 8120: @416767
     /* 416767 */   GIM_Try, /*On fail goto*//*Label 8121*/ GIMT_Encode4(416884), // Rule ID 4346 //
     /* 416772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416775 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416778 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416782 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416786 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 416790 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416794 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 416798 */     GIM_CheckAtomicOrdering, /*MI*/2, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 416801 */     GIM_CheckMemorySizeLessThanLLT, /*MI*/2, /*MMO*/0, /*OpIdx*/0,
     /* 416805 */     GIM_CheckMemorySizeEqualTo, /*MI*/2, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 416812 */     GIM_CheckPointerToAny, /*MI*/2, /*Op*/1, /*SizeInBits*/0,
     /* 416816 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416820 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 416822 */     GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled8),
     /* 416829 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (ld:{ *:[i32] } (am_unscaled8:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>, 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i64] }, (LDURBi:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset), bsub:{ *:[i32] })
     /* 416829 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
     /* 416832 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::LDURBi),
     /* 416836 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416841 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 416846 */     GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 416851 */     GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/3, /*MergeInsnID's*/0, 1, 2,
     /* 416857 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 416859 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 416862 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 416864 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 416867 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 416870 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 416873 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416878 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 416883 */     // GIR_Coverage, 4346,
     /* 416883 */     GIR_EraseRootFromParent_Done,
     /* 416884 */   // Label 8121: @416884
     /* 416884 */   GIM_Try, /*On fail goto*//*Label 8122*/ GIMT_Encode4(416958), // Rule ID 12034 //
     /* 416889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 416892 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416895 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 416906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
     /* 416910 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 416914 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 416918 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 416922 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 416926 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 416930 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 416934 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 416938 */     // MIs[3] Operand 1
     /* 416938 */     // No operand predicates
     /* 416938 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 416942 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 416944 */     // (vector_insert:{ *:[nxv16i8] } (undef:{ *:[nxv16i8] }), (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$Idx), 0:{ *:[i64] })  =>  (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$Idx)
     /* 416944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 416947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 416949 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // vec
     /* 416953 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // Idx
     /* 416956 */     GIR_RootConstrainSelectedInstOperands,
     /* 416957 */     // GIR_Coverage, 12034,
     /* 416957 */     GIR_EraseRootFromParent_Done,
     /* 416958 */   // Label 8122: @416958
     /* 416958 */   GIM_Try, /*On fail goto*//*Label 8123*/ GIMT_Encode4(417106), // Rule ID 11974 //
     /* 416963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 416966 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 416969 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 416972 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 416976 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 416980 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 416984 */     // (vector_insert:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR32:{ *:[i32] }:$src, GPR64:{ *:[i64] }:$index)  =>  (CPY_ZPmR_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (CMPEQ_PPzZZ_B:{ *:[nxv1i1] }:{ *:[i32] } (PTRUE_B:{ *:[nxv1i1] } 31:{ *:[i32] }), (INDEX_II_B:{ *:[nxv16i8] } 0:{ *:[i32] }, 1:{ *:[i32] }), (DUP_ZR_B:{ *:[nxv16i8] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$index, sub_32:{ *:[i32] }))), GPR32:{ *:[i32] }:$src)
     /* 416984 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
     /* 416987 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 416991 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 416996 */     GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/3, /*SubRegIdx*/GIMT_Encode2(20), // index
     /* 417002 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 417007 */     GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 417012 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_nxv16s8,
     /* 417015 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_B),
     /* 417019 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417024 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 417027 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 417029 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_nxv16s8,
     /* 417032 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::INDEX_II_B),
     /* 417036 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417041 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
     /* 417044 */     GIR_AddImm8, /*InsnID*/3, /*Imm*/1,
     /* 417047 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 417049 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv1s1,
     /* 417052 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::PTRUE_B),
     /* 417056 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417061 */     GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
     /* 417064 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 417066 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 417069 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::CMPEQ_PPzZZ_B),
     /* 417073 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417078 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 417081 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 417084 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
     /* 417087 */     GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 417090 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CPY_ZPmR_B),
     /* 417095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 417097 */     GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 417099 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417102 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 417104 */     GIR_RootConstrainSelectedInstOperands,
     /* 417105 */     // GIR_Coverage, 11974,
     /* 417105 */     GIR_EraseRootFromParent_Done,
     /* 417106 */   // Label 8123: @417106
     /* 417106 */   GIM_Reject,
     /* 417107 */ // Label 8105: @417107
     /* 417107 */ GIM_Reject,
     /* 417108 */ // Label 7811: @417108
     /* 417108 */ GIM_Reject,
     /* 417109 */ // Label 101: @417109
     /* 417109 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8127*/ GIMT_Encode4(420026),
     /* 417120 */ /*GILLT_s16*//*Label 8124*/ GIMT_Encode4(417132),
     /* 417124 */ /*GILLT_s32*//*Label 8125*/ GIMT_Encode4(417766),
     /* 417128 */ /*GILLT_s64*//*Label 8126*/ GIMT_Encode4(419359),
     /* 417132 */ // Label 8124: @417132
     /* 417132 */ GIM_Try, /*On fail goto*//*Label 8128*/ GIMT_Encode4(417176), // Rule ID 12027 //
     /* 417137 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417140 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 417143 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417150 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417154 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$Zs, hsub:{ *:[i32] })
     /* 417154 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417157 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417159 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 417165 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417170 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417175 */   // GIR_Coverage, 12027,
     /* 417175 */   GIR_EraseRootFromParent_Done,
     /* 417176 */ // Label 8128: @417176
     /* 417176 */ GIM_Try, /*On fail goto*//*Label 8129*/ GIMT_Encode4(417220), // Rule ID 12028 //
     /* 417181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417184 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 417187 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417194 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417198 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$Zs, hsub:{ *:[i32] })
     /* 417198 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417201 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417203 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 417209 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417214 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417219 */   // GIR_Coverage, 12028,
     /* 417219 */   GIR_EraseRootFromParent_Done,
     /* 417220 */ // Label 8129: @417220
     /* 417220 */ GIM_Try, /*On fail goto*//*Label 8130*/ GIMT_Encode4(417264), // Rule ID 12029 //
     /* 417225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417228 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 417231 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417234 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417238 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417242 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$Zs, hsub:{ *:[i32] })
     /* 417242 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417245 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417247 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Zs
     /* 417253 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417258 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417263 */   // GIR_Coverage, 12029,
     /* 417263 */   GIR_EraseRootFromParent_Done,
     /* 417264 */ // Label 8130: @417264
     /* 417264 */ GIM_Try, /*On fail goto*//*Label 8131*/ GIMT_Encode4(417309), // Rule ID 6402 //
     /* 417269 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 417272 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417275 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417279 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417283 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417287 */   // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] })
     /* 417287 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417290 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417292 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 417298 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417303 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417308 */   // GIR_Coverage, 6402,
     /* 417308 */   GIR_EraseRootFromParent_Done,
     /* 417309 */ // Label 8131: @417309
     /* 417309 */ GIM_Try, /*On fail goto*//*Label 8132*/ GIMT_Encode4(417354), // Rule ID 6405 //
     /* 417314 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 417317 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417320 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417324 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417328 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417332 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417336 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 417340 */   // MIs[1] Operand 1
     /* 417340 */   // No operand predicates
     /* 417340 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417342 */   // (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPi16:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 417342 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi16),
     /* 417345 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417347 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 417349 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 417352 */   GIR_RootConstrainSelectedInstOperands,
     /* 417353 */   // GIR_Coverage, 6405,
     /* 417353 */   GIR_EraseRootFromParent_Done,
     /* 417354 */ // Label 8132: @417354
     /* 417354 */ GIM_Try, /*On fail goto*//*Label 8133*/ GIMT_Encode4(417430), // Rule ID 11998 //
     /* 417359 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417362 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 417365 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417368 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417372 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417376 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417380 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 417384 */   // MIs[1] Operand 1
     /* 417384 */   // No operand predicates
     /* 417384 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417386 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), hsub:{ *:[i32] })
     /* 417386 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 417389 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 417393 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417398 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 417402 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 417405 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417407 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417410 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417412 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 417419 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417424 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417429 */   // GIR_Coverage, 11998,
     /* 417429 */   GIR_EraseRootFromParent_Done,
     /* 417430 */ // Label 8133: @417430
     /* 417430 */ GIM_Try, /*On fail goto*//*Label 8134*/ GIMT_Encode4(417506), // Rule ID 11999 //
     /* 417435 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417438 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 417441 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417444 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417448 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417452 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417456 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 417460 */   // MIs[1] Operand 1
     /* 417460 */   // No operand predicates
     /* 417460 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417462 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), hsub:{ *:[i32] })
     /* 417462 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 417465 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 417469 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417474 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 417478 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 417481 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417483 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417486 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417488 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 417495 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417500 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417505 */   // GIR_Coverage, 11999,
     /* 417505 */   GIR_EraseRootFromParent_Done,
     /* 417506 */ // Label 8134: @417506
     /* 417506 */ GIM_Try, /*On fail goto*//*Label 8135*/ GIMT_Encode4(417582), // Rule ID 12000 //
     /* 417511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417514 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 417517 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417524 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 417528 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 417532 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 417536 */   // MIs[1] Operand 1
     /* 417536 */   // No operand predicates
     /* 417536 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 417538 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f16] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), hsub:{ *:[i32] })
     /* 417538 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 417541 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 417545 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417550 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 417554 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 417557 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417559 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417562 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417564 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::hsub),
     /* 417571 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417576 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417581 */   // GIR_Coverage, 12000,
     /* 417581 */   GIR_EraseRootFromParent_Done,
     /* 417582 */ // Label 8135: @417582
     /* 417582 */ GIM_Try, /*On fail goto*//*Label 8136*/ GIMT_Encode4(417643), // Rule ID 11988 //
     /* 417587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 417593 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417596 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417600 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 417604 */   // (vector_extract:{ *:[f16] } nxv8f16:{ *:[nxv8f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8f16] }:$vec)
     /* 417604 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 417607 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 417611 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417616 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 417622 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 417626 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 417629 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417631 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 417634 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 417636 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417639 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 417641 */   GIR_RootConstrainSelectedInstOperands,
     /* 417642 */   // GIR_Coverage, 11988,
     /* 417642 */   GIR_EraseRootFromParent_Done,
     /* 417643 */ // Label 8136: @417643
     /* 417643 */ GIM_Try, /*On fail goto*//*Label 8137*/ GIMT_Encode4(417704), // Rule ID 11989 //
     /* 417648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 417654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417661 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 417665 */   // (vector_extract:{ *:[f16] } nxv4f16:{ *:[nxv4f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f16] }:$vec)
     /* 417665 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 417668 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 417672 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417677 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 417683 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 417687 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 417690 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417692 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 417695 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 417697 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417700 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 417702 */   GIR_RootConstrainSelectedInstOperands,
     /* 417703 */   // GIR_Coverage, 11989,
     /* 417703 */   GIR_EraseRootFromParent_Done,
     /* 417704 */ // Label 8137: @417704
     /* 417704 */ GIM_Try, /*On fail goto*//*Label 8138*/ GIMT_Encode4(417765), // Rule ID 11990 //
     /* 417709 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417712 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 417715 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417718 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 417722 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 417726 */   // (vector_extract:{ *:[f16] } nxv2f16:{ *:[nxv2f16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_H:{ *:[f16] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f16] }:$vec)
     /* 417726 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 417729 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 417733 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 417738 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 417744 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 417748 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 417751 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 417753 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_H),
     /* 417756 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 417758 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 417761 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 417763 */   GIR_RootConstrainSelectedInstOperands,
     /* 417764 */   // GIR_Coverage, 11990,
     /* 417764 */   GIR_EraseRootFromParent_Done,
     /* 417765 */ // Label 8138: @417765
     /* 417765 */ GIM_Reject,
     /* 417766 */ // Label 8125: @417766
     /* 417766 */ GIM_Try, /*On fail goto*//*Label 8139*/ GIMT_Encode4(417811), // Rule ID 7607 //
     /* 417771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 417774 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417781 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417785 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417789 */   // (extractelt:{ *:[i32] } V128:{ *:[v4i32] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4i32] }:$V, ssub:{ *:[i32] })
     /* 417789 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417792 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417794 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // V
     /* 417800 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417805 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 417810 */   // GIR_Coverage, 7607,
     /* 417810 */   GIR_EraseRootFromParent_Done,
     /* 417811 */ // Label 8139: @417811
     /* 417811 */ GIM_Try, /*On fail goto*//*Label 8140*/ GIMT_Encode4(417856), // Rule ID 7608 //
     /* 417816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 417819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417830 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417834 */   // (extractelt:{ *:[i32] } V64:{ *:[v2i32] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } V64:{ *:[v2i32] }:$V, ssub:{ *:[i32] })
     /* 417834 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417837 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417839 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // V
     /* 417845 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417850 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 417855 */   // GIR_Coverage, 7608,
     /* 417855 */   GIR_EraseRootFromParent_Done,
     /* 417856 */ // Label 8140: @417856
     /* 417856 */ GIM_Try, /*On fail goto*//*Label 8141*/ GIMT_Encode4(417900), // Rule ID 12023 //
     /* 417861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 417867 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417870 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417874 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417878 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$Zs, ssub:{ *:[i32] })
     /* 417878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417883 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 417889 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417894 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417899 */   // GIR_Coverage, 12023,
     /* 417899 */   GIR_EraseRootFromParent_Done,
     /* 417900 */ // Label 8141: @417900
     /* 417900 */ GIM_Try, /*On fail goto*//*Label 8142*/ GIMT_Encode4(417944), // Rule ID 12024 //
     /* 417905 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417908 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 417911 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417918 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417922 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$Zs, ssub:{ *:[i32] })
     /* 417922 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417925 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417927 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 417933 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417938 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417943 */   // GIR_Coverage, 12024,
     /* 417943 */   GIR_EraseRootFromParent_Done,
     /* 417944 */ // Label 8142: @417944
     /* 417944 */ GIM_Try, /*On fail goto*//*Label 8143*/ GIMT_Encode4(417988), // Rule ID 12025 //
     /* 417949 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417952 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 417955 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 417958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417962 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 417966 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$Zs, ssub:{ *:[i32] })
     /* 417966 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 417969 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 417971 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 417977 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 417982 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 417987 */   // GIR_Coverage, 12025,
     /* 417987 */   GIR_EraseRootFromParent_Done,
     /* 417988 */ // Label 8143: @417988
     /* 417988 */ GIM_Try, /*On fail goto*//*Label 8144*/ GIMT_Encode4(418032), // Rule ID 12030 //
     /* 417993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 417996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 417999 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418006 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 418010 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$Zs, ssub:{ *:[i32] })
     /* 418010 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418013 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418015 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 418021 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418026 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418031 */   // GIR_Coverage, 12030,
     /* 418031 */   GIR_EraseRootFromParent_Done,
     /* 418032 */ // Label 8144: @418032
     /* 418032 */ GIM_Try, /*On fail goto*//*Label 8145*/ GIMT_Encode4(418076), // Rule ID 12031 //
     /* 418037 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 418043 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418050 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 418054 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$Zs, ssub:{ *:[i32] })
     /* 418054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418059 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Zs
     /* 418065 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418070 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418075 */   // GIR_Coverage, 12031,
     /* 418075 */   GIR_EraseRootFromParent_Done,
     /* 418076 */ // Label 8145: @418076
     /* 418076 */ GIM_Try, /*On fail goto*//*Label 8146*/ GIMT_Encode4(418121), // Rule ID 6401 //
     /* 418081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418084 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418091 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418095 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 418099 */   // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] })
     /* 418099 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418102 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418104 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 418110 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418115 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418120 */   // GIR_Coverage, 6401,
     /* 418120 */   GIR_EraseRootFromParent_Done,
     /* 418121 */ // Label 8146: @418121
     /* 418121 */ GIM_Try, /*On fail goto*//*Label 8147*/ GIMT_Encode4(418194), // Rule ID 12004 //
     /* 418126 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418129 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 418132 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418139 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418143 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418147 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 418151 */   // MIs[1] Operand 1
     /* 418151 */   // No operand predicates
     /* 418151 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418153 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)  =>  (UMOVvi8:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v16i8] } ZPR:{ *:[nxv16i8] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$index)
     /* 418153 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 418156 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418160 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418165 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 418171 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418176 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418181 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /* 418184 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418186 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418189 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 418192 */   GIR_RootConstrainSelectedInstOperands,
     /* 418193 */   // GIR_Coverage, 12004,
     /* 418193 */   GIR_EraseRootFromParent_Done,
     /* 418194 */ // Label 8147: @418194
     /* 418194 */ GIM_Try, /*On fail goto*//*Label 8148*/ GIMT_Encode4(418267), // Rule ID 12005 //
     /* 418199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418202 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 418205 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418212 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418216 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418220 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 418224 */   // MIs[1] Operand 1
     /* 418224 */   // No operand predicates
     /* 418224 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418226 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)  =>  (UMOVvi16:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v8i16] } ZPR:{ *:[nxv8i16] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$index)
     /* 418226 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 418229 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418233 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418238 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 418244 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418249 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /* 418257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418259 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418262 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 418265 */   GIR_RootConstrainSelectedInstOperands,
     /* 418266 */   // GIR_Coverage, 12005,
     /* 418266 */   GIR_EraseRootFromParent_Done,
     /* 418267 */ // Label 8148: @418267
     /* 418267 */ GIM_Try, /*On fail goto*//*Label 8149*/ GIMT_Encode4(418340), // Rule ID 12006 //
     /* 418272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418275 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 418278 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418281 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418285 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418289 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418293 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418297 */   // MIs[1] Operand 1
     /* 418297 */   // No operand predicates
     /* 418297 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418299 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)  =>  (UMOVvi32:{ *:[i32] } (EXTRACT_SUBREG:{ *:[v4i32] } ZPR:{ *:[nxv4i32] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$index)
     /* 418299 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 418302 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418306 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418311 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 418317 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418322 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418327 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
     /* 418330 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418332 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 418335 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 418338 */   GIR_RootConstrainSelectedInstOperands,
     /* 418339 */   // GIR_Coverage, 12006,
     /* 418339 */   GIR_EraseRootFromParent_Done,
     /* 418340 */ // Label 8149: @418340
     /* 418340 */ GIM_Try, /*On fail goto*//*Label 8150*/ GIMT_Encode4(418388), // Rule ID 1957 //
     /* 418345 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 418348 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 418351 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418354 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418358 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418362 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418366 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418370 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 418374 */   // MIs[1] Operand 1
     /* 418374 */   // No operand predicates
     /* 418374 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418376 */   // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi8_idx0:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418376 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8_idx0),
     /* 418379 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418381 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418383 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418386 */   GIR_RootConstrainSelectedInstOperands,
     /* 418387 */   // GIR_Coverage, 1957,
     /* 418387 */   GIR_EraseRootFromParent_Done,
     /* 418388 */ // Label 8150: @418388
     /* 418388 */ GIM_Try, /*On fail goto*//*Label 8151*/ GIMT_Encode4(418436), // Rule ID 1958 //
     /* 418393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 418396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 418399 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418406 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418410 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418414 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418418 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 418422 */   // MIs[1] Operand 1
     /* 418422 */   // No operand predicates
     /* 418422 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418424 */   // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi16_idx0:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418424 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16_idx0),
     /* 418427 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418429 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418431 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418434 */   GIR_RootConstrainSelectedInstOperands,
     /* 418435 */   // GIR_Coverage, 1958,
     /* 418435 */   GIR_EraseRootFromParent_Done,
     /* 418436 */ // Label 8151: @418436
     /* 418436 */ GIM_Try, /*On fail goto*//*Label 8152*/ GIMT_Encode4(418484), // Rule ID 1959 //
     /* 418441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 418444 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418447 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418454 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418458 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418462 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418466 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 418470 */   // MIs[1] Operand 1
     /* 418470 */   // No operand predicates
     /* 418470 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418472 */   // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi32_idx0:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418472 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32_idx0),
     /* 418475 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418477 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418479 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418482 */   GIR_RootConstrainSelectedInstOperands,
     /* 418483 */   // GIR_Coverage, 1959,
     /* 418483 */   GIR_EraseRootFromParent_Done,
     /* 418484 */ // Label 8152: @418484
     /* 418484 */ GIM_Try, /*On fail goto*//*Label 8153*/ GIMT_Encode4(418532), // Rule ID 1961 //
     /* 418489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 418495 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418498 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418502 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418506 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418510 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418514 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 418518 */   // MIs[1] Operand 1
     /* 418518 */   // No operand predicates
     /* 418518 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418520 */   // (vector_extract:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (UMOVvi8:{ *:[i32] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi8),
     /* 418523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418525 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418527 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418530 */   GIR_RootConstrainSelectedInstOperands,
     /* 418531 */   // GIR_Coverage, 1961,
     /* 418531 */   GIR_EraseRootFromParent_Done,
     /* 418532 */ // Label 8153: @418532
     /* 418532 */ GIM_Try, /*On fail goto*//*Label 8154*/ GIMT_Encode4(418580), // Rule ID 1962 //
     /* 418537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 418543 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418550 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418554 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418558 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418562 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 418566 */   // MIs[1] Operand 1
     /* 418566 */   // No operand predicates
     /* 418566 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418568 */   // (vector_extract:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (UMOVvi16:{ *:[i32] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi16),
     /* 418571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418573 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418575 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418578 */   GIR_RootConstrainSelectedInstOperands,
     /* 418579 */   // GIR_Coverage, 1962,
     /* 418579 */   GIR_EraseRootFromParent_Done,
     /* 418580 */ // Label 8154: @418580
     /* 418580 */ GIM_Try, /*On fail goto*//*Label 8155*/ GIMT_Encode4(418628), // Rule ID 1963 //
     /* 418585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 418588 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418591 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 418598 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418602 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418606 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418610 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418614 */   // MIs[1] Operand 1
     /* 418614 */   // No operand predicates
     /* 418614 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418616 */   // (vector_extract:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (UMOVvi32:{ *:[i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 418616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi32),
     /* 418619 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 418621 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418623 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418626 */   GIR_RootConstrainSelectedInstOperands,
     /* 418627 */   // GIR_Coverage, 1963,
     /* 418627 */   GIR_EraseRootFromParent_Done,
     /* 418628 */ // Label 8155: @418628
     /* 418628 */ GIM_Try, /*On fail goto*//*Label 8156*/ GIMT_Encode4(418673), // Rule ID 6404 //
     /* 418633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 418636 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418639 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418643 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 418647 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418651 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418655 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 418659 */   // MIs[1] Operand 1
     /* 418659 */   // No operand predicates
     /* 418659 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418661 */   // (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPi32:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 418661 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi32),
     /* 418664 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418666 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 418668 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 418671 */   GIR_RootConstrainSelectedInstOperands,
     /* 418672 */   // GIR_Coverage, 6404,
     /* 418672 */   GIR_EraseRootFromParent_Done,
     /* 418673 */ // Label 8156: @418673
     /* 418673 */ GIM_Try, /*On fail goto*//*Label 8157*/ GIMT_Encode4(418749), // Rule ID 11994 //
     /* 418678 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418681 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 418684 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418691 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418695 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418699 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 418703 */   // MIs[1] Operand 1
     /* 418703 */   // No operand predicates
     /* 418703 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418705 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index), ssub:{ *:[i32] })
     /* 418705 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 418708 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 418712 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418717 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 418721 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 418724 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 418726 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418729 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418731 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 418738 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418743 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418748 */   // GIR_Coverage, 11994,
     /* 418748 */   GIR_EraseRootFromParent_Done,
     /* 418749 */ // Label 8157: @418749
     /* 418749 */ GIM_Try, /*On fail goto*//*Label 8158*/ GIMT_Encode4(418825), // Rule ID 11995 //
     /* 418754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418757 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 418760 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418763 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418767 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418771 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418775 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 418779 */   // MIs[1] Operand 1
     /* 418779 */   // No operand predicates
     /* 418779 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418781 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_H:{ *:[nxv16i8] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index), ssub:{ *:[i32] })
     /* 418781 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 418784 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 418788 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418793 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 418797 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 418800 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 418802 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418805 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418807 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 418814 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418819 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418824 */   // GIR_Coverage, 11995,
     /* 418824 */   GIR_EraseRootFromParent_Done,
     /* 418825 */ // Label 8158: @418825
     /* 418825 */ GIM_Try, /*On fail goto*//*Label 8159*/ GIMT_Encode4(418901), // Rule ID 11996 //
     /* 418830 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418833 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 418836 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418843 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418847 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418851 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 418855 */   // MIs[1] Operand 1
     /* 418855 */   // No operand predicates
     /* 418855 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418857 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
     /* 418857 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 418860 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 418864 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418869 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 418873 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 418876 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 418878 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418881 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418883 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 418890 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418895 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418900 */   // GIR_Coverage, 11996,
     /* 418900 */   GIR_EraseRootFromParent_Done,
     /* 418901 */ // Label 8159: @418901
     /* 418901 */ GIM_Try, /*On fail goto*//*Label 8160*/ GIMT_Encode4(418977), // Rule ID 12001 //
     /* 418906 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418909 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 418912 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418919 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418923 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 418927 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 418931 */   // MIs[1] Operand 1
     /* 418931 */   // No operand predicates
     /* 418931 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 418933 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_S:{ *:[nxv16i8] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index), ssub:{ *:[i32] })
     /* 418933 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 418936 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 418940 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 418945 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 418949 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 418952 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 418954 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 418957 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 418959 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 418966 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418971 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 418976 */   // GIR_Coverage, 12001,
     /* 418976 */   GIR_EraseRootFromParent_Done,
     /* 418977 */ // Label 8160: @418977
     /* 418977 */ GIM_Try, /*On fail goto*//*Label 8161*/ GIMT_Encode4(419053), // Rule ID 12002 //
     /* 418982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 418985 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 418988 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 418991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 418995 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 418999 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419003 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 419007 */   // MIs[1] Operand 1
     /* 419007 */   // No operand predicates
     /* 419007 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419009 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f32] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), ssub:{ *:[i32] })
     /* 419009 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 419012 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 419016 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419021 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 419025 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 419028 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419030 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419033 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419035 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 419042 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 419047 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419052 */   // GIR_Coverage, 12002,
     /* 419052 */   GIR_EraseRootFromParent_Done,
     /* 419053 */ // Label 8161: @419053
     /* 419053 */ GIM_Try, /*On fail goto*//*Label 8162*/ GIMT_Encode4(419114), // Rule ID 11984 //
     /* 419058 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419061 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 419064 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419067 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 419071 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419075 */   // (vector_extract:{ *:[i32] } nxv16i8:{ *:[nxv16i8] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_B:{ *:[i32] } (WHILELS_PXX_B:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv16i8] }:$vec)
     /* 419075 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419078 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_B),
     /* 419082 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419087 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419093 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419097 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419100 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_B),
     /* 419105 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419107 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419110 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419112 */   GIR_RootConstrainSelectedInstOperands,
     /* 419113 */   // GIR_Coverage, 11984,
     /* 419113 */   GIR_EraseRootFromParent_Done,
     /* 419114 */ // Label 8162: @419114
     /* 419114 */ GIM_Try, /*On fail goto*//*Label 8163*/ GIMT_Encode4(419175), // Rule ID 11985 //
     /* 419119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419122 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 419125 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 419132 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419136 */   // (vector_extract:{ *:[i32] } nxv8i16:{ *:[nxv8i16] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_H:{ *:[i32] } (WHILELS_PXX_H:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv8i16] }:$vec)
     /* 419136 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419139 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_H),
     /* 419143 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419148 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419154 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419158 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419161 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419163 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_H),
     /* 419166 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419168 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419171 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419173 */   GIR_RootConstrainSelectedInstOperands,
     /* 419174 */   // GIR_Coverage, 11985,
     /* 419174 */   GIR_EraseRootFromParent_Done,
     /* 419175 */ // Label 8163: @419175
     /* 419175 */ GIM_Try, /*On fail goto*//*Label 8164*/ GIMT_Encode4(419236), // Rule ID 11986 //
     /* 419180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419183 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 419186 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 419193 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419197 */   // (vector_extract:{ *:[i32] } nxv4i32:{ *:[nxv4i32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_S:{ *:[i32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4i32] }:$vec)
     /* 419197 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419200 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 419204 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419209 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419215 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419219 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419222 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419224 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_S),
     /* 419227 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419229 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419232 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419234 */   GIR_RootConstrainSelectedInstOperands,
     /* 419235 */   // GIR_Coverage, 11986,
     /* 419235 */   GIR_EraseRootFromParent_Done,
     /* 419236 */ // Label 8164: @419236
     /* 419236 */ GIM_Try, /*On fail goto*//*Label 8165*/ GIMT_Encode4(419297), // Rule ID 11991 //
     /* 419241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419244 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 419247 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419250 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 419254 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419258 */   // (vector_extract:{ *:[f32] } nxv4f32:{ *:[nxv4f32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_S:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv4f32] }:$vec)
     /* 419258 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419261 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_S),
     /* 419265 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419270 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419276 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419280 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419283 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
     /* 419288 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 419290 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419293 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419295 */   GIR_RootConstrainSelectedInstOperands,
     /* 419296 */   // GIR_Coverage, 11991,
     /* 419296 */   GIR_EraseRootFromParent_Done,
     /* 419297 */ // Label 8165: @419297
     /* 419297 */ GIM_Try, /*On fail goto*//*Label 8166*/ GIMT_Encode4(419358), // Rule ID 11992 //
     /* 419302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419305 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 419308 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419311 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 419315 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419319 */   // (vector_extract:{ *:[f32] } nxv2f32:{ *:[nxv2f32] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_S:{ *:[f32] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f32] }:$vec)
     /* 419319 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419322 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 419326 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419331 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419337 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419341 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419344 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_S),
     /* 419349 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 419351 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419354 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419356 */   GIR_RootConstrainSelectedInstOperands,
     /* 419357 */   // GIR_Coverage, 11992,
     /* 419357 */   GIR_EraseRootFromParent_Done,
     /* 419358 */ // Label 8166: @419358
     /* 419358 */ GIM_Reject,
     /* 419359 */ // Label 8126: @419359
     /* 419359 */ GIM_Try, /*On fail goto*//*Label 8167*/ GIMT_Encode4(419404), // Rule ID 7606 //
     /* 419364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 419367 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419378 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 419382 */   // (extractelt:{ *:[i64] } V128:{ *:[v2i64] }:$V, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2i64] }:$V, dsub:{ *:[i32] })
     /* 419382 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419385 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419387 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // V
     /* 419393 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419398 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419403 */   // GIR_Coverage, 7606,
     /* 419403 */   GIR_EraseRootFromParent_Done,
     /* 419404 */ // Label 8167: @419404
     /* 419404 */ GIM_Try, /*On fail goto*//*Label 8168*/ GIMT_Encode4(419448), // Rule ID 12026 //
     /* 419409 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419412 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419415 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419418 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419422 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 419426 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$Zs, dsub:{ *:[i32] })
     /* 419426 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419429 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419431 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Zs
     /* 419437 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419442 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419447 */   // GIR_Coverage, 12026,
     /* 419447 */   GIR_EraseRootFromParent_Done,
     /* 419448 */ // Label 8168: @419448
     /* 419448 */ GIM_Try, /*On fail goto*//*Label 8169*/ GIMT_Encode4(419492), // Rule ID 12032 //
     /* 419453 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419456 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419459 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419462 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419466 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 419470 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$Zs, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$Zs, dsub:{ *:[i32] })
     /* 419470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419473 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419475 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Zs
     /* 419481 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419486 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419491 */   // GIR_Coverage, 12032,
     /* 419491 */   GIR_EraseRootFromParent_Done,
     /* 419492 */ // Label 8169: @419492
     /* 419492 */ GIM_Try, /*On fail goto*//*Label 8170*/ GIMT_Encode4(419537), // Rule ID 6400 //
     /* 419497 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 419500 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419503 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419507 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419511 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 419515 */   // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })  =>  (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] })
     /* 419515 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419518 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419520 */   GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 419526 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419531 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419536 */   // GIR_Coverage, 6400,
     /* 419536 */   GIR_EraseRootFromParent_Done,
     /* 419537 */ // Label 8170: @419537
     /* 419537 */ GIM_Try, /*On fail goto*//*Label 8171*/ GIMT_Encode4(419610), // Rule ID 12007 //
     /* 419542 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 419545 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419548 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419551 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419555 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419559 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419563 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 419567 */   // MIs[1] Operand 1
     /* 419567 */   // No operand predicates
     /* 419567 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419569 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index)  =>  (UMOVvi64:{ *:[i64] } (EXTRACT_SUBREG:{ *:[v2i64] } ZPR:{ *:[nxv2i64] }:$vec, zsub:{ *:[i32] }), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$index)
     /* 419569 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 419572 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419576 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419581 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(43), // vec
     /* 419587 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419592 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419597 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
     /* 419600 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419602 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419605 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // index
     /* 419608 */   GIR_RootConstrainSelectedInstOperands,
     /* 419609 */   // GIR_Coverage, 12007,
     /* 419609 */   GIR_EraseRootFromParent_Done,
     /* 419610 */ // Label 8171: @419610
     /* 419610 */ GIM_Try, /*On fail goto*//*Label 8172*/ GIMT_Encode4(419658), // Rule ID 1960 //
     /* 419615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 419618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 419621 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419624 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419628 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419632 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419636 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419640 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndex0),
     /* 419644 */   // MIs[1] Operand 1
     /* 419644 */   // No operand predicates
     /* 419644 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419646 */   // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndex0>>:$idx)  =>  (UMOVvi64_idx0:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 419646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64_idx0),
     /* 419649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419651 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419653 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 419656 */   GIR_RootConstrainSelectedInstOperands,
     /* 419657 */   // GIR_Coverage, 1960,
     /* 419657 */   GIR_EraseRootFromParent_Done,
     /* 419658 */ // Label 8172: @419658
     /* 419658 */ GIM_Try, /*On fail goto*//*Label 8173*/ GIMT_Encode4(419706), // Rule ID 1964 //
     /* 419663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 419666 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 419669 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419676 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419680 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419684 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419688 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 419692 */   // MIs[1] Operand 1
     /* 419692 */   // No operand predicates
     /* 419692 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419694 */   // (vector_extract:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (UMOVvi64:{ *:[i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 419694 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMOVvi64),
     /* 419697 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419699 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419701 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 419704 */   GIR_RootConstrainSelectedInstOperands,
     /* 419705 */   // GIR_Coverage, 1964,
     /* 419705 */   GIR_EraseRootFromParent_Done,
     /* 419706 */ // Label 8173: @419706
     /* 419706 */ GIM_Try, /*On fail goto*//*Label 8174*/ GIMT_Encode4(419751), // Rule ID 6403 //
     /* 419711 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 419714 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419717 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419721 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 419725 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419729 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419733 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 419737 */   // MIs[1] Operand 1
     /* 419737 */   // No operand predicates
     /* 419737 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419739 */   // (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (DUPi64:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 419739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPi64),
     /* 419742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419744 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 419746 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 419749 */   GIR_RootConstrainSelectedInstOperands,
     /* 419750 */   // GIR_Coverage, 6403,
     /* 419750 */   GIR_EraseRootFromParent_Done,
     /* 419751 */ // Label 8174: @419751
     /* 419751 */ GIM_Try, /*On fail goto*//*Label 8175*/ GIMT_Encode4(419827), // Rule ID 11997 //
     /* 419756 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419759 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419762 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419769 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419773 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419777 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 419781 */   // MIs[1] Operand 1
     /* 419781 */   // No operand predicates
     /* 419781 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419783 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[i64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
     /* 419783 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 419786 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 419790 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419795 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 419799 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 419802 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419804 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419807 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419809 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 419816 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419821 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419826 */   // GIR_Coverage, 11997,
     /* 419826 */   GIR_EraseRootFromParent_Done,
     /* 419827 */ // Label 8175: @419827
     /* 419827 */ GIM_Try, /*On fail goto*//*Label 8176*/ GIMT_Encode4(419903), // Rule ID 12003 //
     /* 419832 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419838 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419841 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419845 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 419849 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 419853 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 419857 */   // MIs[1] Operand 1
     /* 419857 */   // No operand predicates
     /* 419857 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 419859 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)  =>  (EXTRACT_SUBREG:{ *:[f64] } (DUP_ZZI_D:{ *:[nxv16i8] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index), dsub:{ *:[i32] })
     /* 419859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 419862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 419866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419871 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // vec
     /* 419875 */   GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // index
     /* 419878 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419880 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 419883 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 419885 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 419892 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419897 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 419902 */   // GIR_Coverage, 12003,
     /* 419902 */   GIR_EraseRootFromParent_Done,
     /* 419903 */ // Label 8176: @419903
     /* 419903 */ GIM_Try, /*On fail goto*//*Label 8177*/ GIMT_Encode4(419964), // Rule ID 11987 //
     /* 419908 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419914 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419917 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419921 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419925 */   // (vector_extract:{ *:[i64] } nxv2i64:{ *:[nxv2i64] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_RPZ_D:{ *:[i64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2i64] }:$vec)
     /* 419925 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419928 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 419932 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419937 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 419943 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 419947 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 419950 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 419952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_RPZ_D),
     /* 419955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 419957 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 419960 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 419962 */   GIR_RootConstrainSelectedInstOperands,
     /* 419963 */   // GIR_Coverage, 11987,
     /* 419963 */   GIR_EraseRootFromParent_Done,
     /* 419964 */ // Label 8177: @419964
     /* 419964 */ GIM_Try, /*On fail goto*//*Label 8178*/ GIMT_Encode4(420025), // Rule ID 11993 //
     /* 419969 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 419972 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 419975 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 419978 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 419982 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 419986 */   // (vector_extract:{ *:[f64] } nxv2f64:{ *:[nxv2f64] }:$vec, GPR64:{ *:[i64] }:$index)  =>  (LASTB_VPZ_D:{ *:[f64] } (WHILELS_PXX_D:{ *:[nxv1i1] }:{ *:[i32] } XZR:{ *:[i64] }, GPR64:{ *:[i64] }:$index), ZPR:{ *:[nxv2f64] }:$vec)
     /* 419986 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv1s1,
     /* 419989 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::WHILELS_PXX_D),
     /* 419993 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 419998 */   GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AArch64::XZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 420004 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // index
     /* 420008 */   GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AArch64::NZCV*/0,
     /* 420011 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420013 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LASTB_VPZ_D),
     /* 420016 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
     /* 420018 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420021 */   GIR_RootToRootCopy, /*OpIdx*/1, // vec
     /* 420023 */   GIR_RootConstrainSelectedInstOperands,
     /* 420024 */   // GIR_Coverage, 11993,
     /* 420024 */   GIR_EraseRootFromParent_Done,
     /* 420025 */ // Label 8178: @420025
     /* 420025 */ GIM_Reject,
     /* 420026 */ // Label 8127: @420026
     /* 420026 */ GIM_Reject,
     /* 420027 */ // Label 102: @420027
     /* 420027 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(14), GIMT_Encode2(24), /*)*//*default:*//*Label 8186*/ GIMT_Encode4(422346),
     /* 420038 */ /*GILLT_nxv2s16*//*Label 8179*/ GIMT_Encode4(420078),
     /* 420042 */ /*GILLT_nxv2s32*//*Label 8180*/ GIMT_Encode4(420437),
     /* 420046 */ /*GILLT_nxv2s64*//*Label 8181*/ GIMT_Encode4(420739), GIMT_Encode4(0),
     /* 420054 */ /*GILLT_nxv4s16*//*Label 8182*/ GIMT_Encode4(421114),
     /* 420058 */ /*GILLT_nxv4s32*//*Label 8183*/ GIMT_Encode4(421416), GIMT_Encode4(0),
     /* 420066 */ /*GILLT_nxv8s16*//*Label 8184*/ GIMT_Encode4(421791), GIMT_Encode4(0),
     /* 420074 */ /*GILLT_nxv16s8*//*Label 8185*/ GIMT_Encode4(422202),
     /* 420078 */ // Label 8179: @420078
     /* 420078 */ GIM_Try, /*On fail goto*//*Label 8187*/ GIMT_Encode4(420436),
     /* 420083 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 420086 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420090 */   GIM_Try, /*On fail goto*//*Label 8188*/ GIMT_Encode4(420154), // Rule ID 6634 //
     /* 420095 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420098 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420102 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420106 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 420110 */     // MIs[1] Operand 1
     /* 420110 */     // No operand predicates
     /* 420110 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420112 */     // (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 420112 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 420115 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 420119 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420124 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420127 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420134 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420137 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420140 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 420143 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420148 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420153 */     // GIR_Coverage, 6634,
     /* 420153 */     GIR_EraseRootFromParent_Done,
     /* 420154 */   // Label 8188: @420154
     /* 420154 */   GIM_Try, /*On fail goto*//*Label 8189*/ GIMT_Encode4(420211), // Rule ID 2714 //
     /* 420159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420162 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420166 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420170 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 420174 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420178 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420183 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420187 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420191 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 420195 */     // MIs[2] Operand 1
     /* 420195 */     // No operand predicates
     /* 420195 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420197 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv2f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 420197 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 420200 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420206 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420209 */     GIR_RootConstrainSelectedInstOperands,
     /* 420210 */     // GIR_Coverage, 2714,
     /* 420210 */     GIR_EraseRootFromParent_Done,
     /* 420211 */   // Label 8189: @420211
     /* 420211 */   GIM_Try, /*On fail goto*//*Label 8190*/ GIMT_Encode4(420268), // Rule ID 2716 //
     /* 420216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420219 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420223 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420227 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 420231 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420235 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420240 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420244 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420248 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 420252 */     // MIs[2] Operand 1
     /* 420252 */     // No operand predicates
     /* 420252 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420254 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f16] } ZPR:{ *:[nxv2f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 420254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 420257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420259 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420263 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420266 */     GIR_RootConstrainSelectedInstOperands,
     /* 420267 */     // GIR_Coverage, 2716,
     /* 420267 */     GIR_EraseRootFromParent_Done,
     /* 420268 */   // Label 8190: @420268
     /* 420268 */   GIM_Try, /*On fail goto*//*Label 8191*/ GIMT_Encode4(420325), // Rule ID 9045 //
     /* 420273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420280 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420284 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 420288 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420292 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420297 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420301 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420305 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 420309 */     // MIs[2] Operand 1
     /* 420309 */     // No operand predicates
     /* 420309 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420311 */     // (splat_vector:{ *:[nxv2f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv2f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 420311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 420314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420320 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420323 */     GIR_RootConstrainSelectedInstOperands,
     /* 420324 */     // GIR_Coverage, 9045,
     /* 420324 */     GIR_EraseRootFromParent_Done,
     /* 420325 */   // Label 8191: @420325
     /* 420325 */   GIM_Try, /*On fail goto*//*Label 8192*/ GIMT_Encode4(420359), // Rule ID 9088 //
     /* 420330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420333 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420337 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420341 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 420345 */     // MIs[1] Operand 1
     /* 420345 */     // No operand predicates
     /* 420345 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420347 */     // (splat_vector:{ *:[nxv2f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv2f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 420347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 420350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420352 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 420357 */     GIR_RootConstrainSelectedInstOperands,
     /* 420358 */     // GIR_Coverage, 9088,
     /* 420358 */     GIR_EraseRootFromParent_Done,
     /* 420359 */   // Label 8192: @420359
     /* 420359 */   GIM_Try, /*On fail goto*//*Label 8193*/ GIMT_Encode4(420435), // Rule ID 9066 //
     /* 420364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420367 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420371 */     // (splat_vector:{ *:[nxv2f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv2f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 420371 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 420374 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 420378 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420383 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 420385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 420388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 420392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420397 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 420400 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 420404 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 420407 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420412 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420417 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 420422 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 420425 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420427 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420430 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420433 */     GIR_RootConstrainSelectedInstOperands,
     /* 420434 */     // GIR_Coverage, 9066,
     /* 420434 */     GIR_EraseRootFromParent_Done,
     /* 420435 */   // Label 8193: @420435
     /* 420435 */   GIM_Reject,
     /* 420436 */ // Label 8187: @420436
     /* 420436 */ GIM_Reject,
     /* 420437 */ // Label 8180: @420437
     /* 420437 */ GIM_Try, /*On fail goto*//*Label 8194*/ GIMT_Encode4(420738),
     /* 420442 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 420445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420449 */   GIM_Try, /*On fail goto*//*Label 8195*/ GIMT_Encode4(420513), // Rule ID 6632 //
     /* 420454 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420457 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420461 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420465 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 420469 */     // MIs[1] Operand 1
     /* 420469 */     // No operand predicates
     /* 420469 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420471 */     // (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 420471 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 420474 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 420478 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420483 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420486 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420488 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420491 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420493 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420496 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420499 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 420502 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420507 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420512 */     // GIR_Coverage, 6632,
     /* 420512 */     GIR_EraseRootFromParent_Done,
     /* 420513 */   // Label 8195: @420513
     /* 420513 */   GIM_Try, /*On fail goto*//*Label 8196*/ GIMT_Encode4(420570), // Rule ID 9054 //
     /* 420518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420529 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 420533 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420542 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420546 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420550 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 420554 */     // MIs[2] Operand 1
     /* 420554 */     // No operand predicates
     /* 420554 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420556 */     // (splat_vector:{ *:[nxv2f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv2f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 420556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 420559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420561 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420565 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420568 */     GIR_RootConstrainSelectedInstOperands,
     /* 420569 */     // GIR_Coverage, 9054,
     /* 420569 */     GIR_EraseRootFromParent_Done,
     /* 420570 */   // Label 8196: @420570
     /* 420570 */   GIM_Try, /*On fail goto*//*Label 8197*/ GIMT_Encode4(420627), // Rule ID 9063 //
     /* 420575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 420590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420594 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420607 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 420611 */     // MIs[2] Operand 1
     /* 420611 */     // No operand predicates
     /* 420611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420613 */     // (splat_vector:{ *:[nxv2f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f32] } ZPR:{ *:[nxv2f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 420613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 420616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420622 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420625 */     GIR_RootConstrainSelectedInstOperands,
     /* 420626 */     // GIR_Coverage, 9063,
     /* 420626 */     GIR_EraseRootFromParent_Done,
     /* 420627 */   // Label 8197: @420627
     /* 420627 */   GIM_Try, /*On fail goto*//*Label 8198*/ GIMT_Encode4(420661), // Rule ID 9090 //
     /* 420632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420635 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420639 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420643 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 420647 */     // MIs[1] Operand 1
     /* 420647 */     // No operand predicates
     /* 420647 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420649 */     // (splat_vector:{ *:[nxv2f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8)  =>  (FDUP_ZI_S:{ *:[nxv2f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 420649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_S),
     /* 420652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420654 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 420659 */     GIR_RootConstrainSelectedInstOperands,
     /* 420660 */     // GIR_Coverage, 9090,
     /* 420660 */     GIR_EraseRootFromParent_Done,
     /* 420661 */   // Label 8198: @420661
     /* 420661 */   GIM_Try, /*On fail goto*//*Label 8199*/ GIMT_Encode4(420737), // Rule ID 9068 //
     /* 420666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420669 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420673 */     // (splat_vector:{ *:[nxv2f32] } FPR32:{ *:[f32] }:$src)  =>  (DUP_ZZI_S:{ *:[nxv2f32] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR32:{ *:[f32] }:$src, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 420673 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 420676 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 420680 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420685 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 420687 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 420690 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 420694 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420699 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 420702 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 420706 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 420709 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420714 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420719 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 420724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 420727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420729 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420732 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420735 */     GIR_RootConstrainSelectedInstOperands,
     /* 420736 */     // GIR_Coverage, 9068,
     /* 420736 */     GIR_EraseRootFromParent_Done,
     /* 420737 */   // Label 8199: @420737
     /* 420737 */   GIM_Reject,
     /* 420738 */ // Label 8194: @420738
     /* 420738 */ GIM_Reject,
     /* 420739 */ // Label 8181: @420739
     /* 420739 */ GIM_Try, /*On fail goto*//*Label 8200*/ GIMT_Encode4(421113),
     /* 420744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 420747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420751 */   GIM_Try, /*On fail goto*//*Label 8201*/ GIMT_Encode4(420805), // Rule ID 6627 //
     /* 420756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420759 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 420763 */     // (splat_vector:{ *:[nxv2i64] } 0:{ *:[i64] })  =>  (SUBREG_TO_REG:{ *:[nxv2i64] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 420763 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 420766 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 420770 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420775 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420778 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420785 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420788 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420791 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 420794 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420799 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420804 */     // GIR_Coverage, 6627,
     /* 420804 */     GIR_EraseRootFromParent_Done,
     /* 420805 */   // Label 8201: @420805
     /* 420805 */   GIM_Try, /*On fail goto*//*Label 8202*/ GIMT_Encode4(420869), // Rule ID 6631 //
     /* 420810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 420813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420821 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 420825 */     // MIs[1] Operand 1
     /* 420825 */     // No operand predicates
     /* 420825 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 420827 */     // (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv2f64] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 420827 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 420830 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 420834 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 420839 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 420842 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 420844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 420847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 420849 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 420852 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 420855 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 420858 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420863 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 420868 */     // GIR_Coverage, 6631,
     /* 420868 */     GIR_EraseRootFromParent_Done,
     /* 420869 */   // Label 8202: @420869
     /* 420869 */   GIM_Try, /*On fail goto*//*Label 8203*/ GIMT_Encode4(420926), // Rule ID 2711 //
     /* 420874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420877 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420881 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420885 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 420889 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420893 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420898 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420902 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420906 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 420910 */     // MIs[2] Operand 1
     /* 420910 */     // No operand predicates
     /* 420910 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420912 */     // (splat_vector:{ *:[nxv2i64] } (vector_extract:{ *:[i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2i64] } ZPR:{ *:[nxv2i64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 420912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 420915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420924 */     GIR_RootConstrainSelectedInstOperands,
     /* 420925 */     // GIR_Coverage, 2711,
     /* 420925 */     GIR_EraseRootFromParent_Done,
     /* 420926 */   // Label 8203: @420926
     /* 420926 */   GIM_Try, /*On fail goto*//*Label 8204*/ GIMT_Encode4(420983), // Rule ID 9060 //
     /* 420931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 420942 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 420946 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 420950 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 420955 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 420959 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 420963 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_d),
     /* 420967 */     // MIs[2] Operand 1
     /* 420967 */     // No operand predicates
     /* 420967 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 420969 */     // (splat_vector:{ *:[nxv2f64] } (vector_extract:{ *:[f64] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index))  =>  (DUP_ZZI_D:{ *:[nxv2f64] } ZPR:{ *:[nxv2f64] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_d>>:$index)
     /* 420969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 420972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 420974 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 420978 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 420981 */     GIR_RootConstrainSelectedInstOperands,
     /* 420982 */     // GIR_Coverage, 9060,
     /* 420982 */     GIR_EraseRootFromParent_Done,
     /* 420983 */   // Label 8204: @420983
     /* 420983 */   GIM_Try, /*On fail goto*//*Label 8205*/ GIMT_Encode4(421017), // Rule ID 9091 //
     /* 420988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 420991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 420995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 420999 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm64),
     /* 421003 */     // MIs[1] Operand 1
     /* 421003 */     // No operand predicates
     /* 421003 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421005 */     // (splat_vector:{ *:[nxv2f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>><<X:fpimm64XForm>>:$imm8)  =>  (FDUP_ZI_D:{ *:[nxv2f64] } (fpimm64XForm:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm64>>:$imm8))
     /* 421005 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_D),
     /* 421008 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421010 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm64), // imm8
     /* 421015 */     GIR_RootConstrainSelectedInstOperands,
     /* 421016 */     // GIR_Coverage, 9091,
     /* 421016 */     GIR_EraseRootFromParent_Done,
     /* 421017 */   // Label 8205: @421017
     /* 421017 */   GIM_Try, /*On fail goto*//*Label 8206*/ GIMT_Encode4(421036), // Rule ID 2424 //
     /* 421022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421025 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 421029 */     // (splat_vector:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$Rn)  =>  (DUP_ZR_D:{ *:[nxv2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 421029 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_D),
     /* 421034 */     GIR_RootConstrainSelectedInstOperands,
     /* 421035 */     // GIR_Coverage, 2424,
     /* 421035 */     GIR_Done,
     /* 421036 */   // Label 8206: @421036
     /* 421036 */   GIM_Try, /*On fail goto*//*Label 8207*/ GIMT_Encode4(421112), // Rule ID 9069 //
     /* 421041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421044 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421048 */     // (splat_vector:{ *:[nxv2f64] } FPR64:{ *:[f64] }:$src)  =>  (DUP_ZZI_D:{ *:[nxv2f64] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR64:{ *:[f64] }:$src, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 421048 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 421051 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 421055 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421060 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 421062 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 421065 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 421069 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421074 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 421077 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 421081 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 421084 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421089 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421094 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 421099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_D),
     /* 421102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421104 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421107 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421110 */     GIR_RootConstrainSelectedInstOperands,
     /* 421111 */     // GIR_Coverage, 9069,
     /* 421111 */     GIR_EraseRootFromParent_Done,
     /* 421112 */   // Label 8207: @421112
     /* 421112 */   GIM_Reject,
     /* 421113 */ // Label 8200: @421113
     /* 421113 */ GIM_Reject,
     /* 421114 */ // Label 8182: @421114
     /* 421114 */ GIM_Try, /*On fail goto*//*Label 8208*/ GIMT_Encode4(421415),
     /* 421119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 421122 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421126 */   GIM_Try, /*On fail goto*//*Label 8209*/ GIMT_Encode4(421190), // Rule ID 6635 //
     /* 421131 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421134 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421138 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 421142 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 421146 */     // MIs[1] Operand 1
     /* 421146 */     // No operand predicates
     /* 421146 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421148 */     // (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv4f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 421148 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 421151 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 421155 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421160 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 421163 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 421165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 421168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 421170 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421173 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421176 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 421179 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421184 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421189 */     // GIR_Coverage, 6635,
     /* 421189 */     GIR_EraseRootFromParent_Done,
     /* 421190 */   // Label 8209: @421190
     /* 421190 */   GIM_Try, /*On fail goto*//*Label 8210*/ GIMT_Encode4(421247), // Rule ID 2715 //
     /* 421195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 421206 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 421210 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 421214 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421219 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 421223 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 421227 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 421231 */     // MIs[2] Operand 1
     /* 421231 */     // No operand predicates
     /* 421231 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 421233 */     // (splat_vector:{ *:[nxv4f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4f16] } ZPR:{ *:[nxv4f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 421233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 421236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 421242 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 421245 */     GIR_RootConstrainSelectedInstOperands,
     /* 421246 */     // GIR_Coverage, 2715,
     /* 421246 */     GIR_EraseRootFromParent_Done,
     /* 421247 */   // Label 8210: @421247
     /* 421247 */   GIM_Try, /*On fail goto*//*Label 8211*/ GIMT_Encode4(421304), // Rule ID 9048 //
     /* 421252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421255 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421259 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 421263 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 421267 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 421271 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421276 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 421280 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 421284 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 421288 */     // MIs[2] Operand 1
     /* 421288 */     // No operand predicates
     /* 421288 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 421290 */     // (splat_vector:{ *:[nxv4f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv4f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 421290 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 421293 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 421299 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 421302 */     GIR_RootConstrainSelectedInstOperands,
     /* 421303 */     // GIR_Coverage, 9048,
     /* 421303 */     GIR_EraseRootFromParent_Done,
     /* 421304 */   // Label 8211: @421304
     /* 421304 */   GIM_Try, /*On fail goto*//*Label 8212*/ GIMT_Encode4(421338), // Rule ID 9087 //
     /* 421309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421312 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421316 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 421320 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 421324 */     // MIs[1] Operand 1
     /* 421324 */     // No operand predicates
     /* 421324 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421326 */     // (splat_vector:{ *:[nxv4f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv4f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 421326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 421329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421331 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 421336 */     GIR_RootConstrainSelectedInstOperands,
     /* 421337 */     // GIR_Coverage, 9087,
     /* 421337 */     GIR_EraseRootFromParent_Done,
     /* 421338 */   // Label 8212: @421338
     /* 421338 */   GIM_Try, /*On fail goto*//*Label 8213*/ GIMT_Encode4(421414), // Rule ID 9065 //
     /* 421343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421346 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421350 */     // (splat_vector:{ *:[nxv4f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv4f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 421350 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 421353 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 421357 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421362 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 421364 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 421367 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 421371 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421376 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 421379 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 421383 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 421386 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421391 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421396 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 421401 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 421404 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421406 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421409 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421412 */     GIR_RootConstrainSelectedInstOperands,
     /* 421413 */     // GIR_Coverage, 9065,
     /* 421413 */     GIR_EraseRootFromParent_Done,
     /* 421414 */   // Label 8213: @421414
     /* 421414 */   GIM_Reject,
     /* 421415 */ // Label 8208: @421415
     /* 421415 */ GIM_Reject,
     /* 421416 */ // Label 8183: @421416
     /* 421416 */ GIM_Try, /*On fail goto*//*Label 8214*/ GIMT_Encode4(421790),
     /* 421421 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 421424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421428 */   GIM_Try, /*On fail goto*//*Label 8215*/ GIMT_Encode4(421482), // Rule ID 6628 //
     /* 421433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421436 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 421440 */     // (splat_vector:{ *:[nxv4i32] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv4i32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 421440 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 421443 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 421447 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421452 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 421455 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 421457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 421460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 421462 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421465 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 421471 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421476 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421481 */     // GIR_Coverage, 6628,
     /* 421481 */     GIR_EraseRootFromParent_Done,
     /* 421482 */   // Label 8215: @421482
     /* 421482 */   GIM_Try, /*On fail goto*//*Label 8216*/ GIMT_Encode4(421546), // Rule ID 6633 //
     /* 421487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421490 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421494 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 421498 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 421502 */     // MIs[1] Operand 1
     /* 421502 */     // No operand predicates
     /* 421502 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421504 */     // (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv4f32] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 421504 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 421507 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 421511 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421516 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 421519 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 421521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 421524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 421526 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421529 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421532 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 421535 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421540 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421545 */     // GIR_Coverage, 6633,
     /* 421545 */     GIR_EraseRootFromParent_Done,
     /* 421546 */   // Label 8216: @421546
     /* 421546 */   GIM_Try, /*On fail goto*//*Label 8217*/ GIMT_Encode4(421603), // Rule ID 2708 //
     /* 421551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421554 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421558 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 421562 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 421566 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 421570 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421575 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 421579 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 421583 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 421587 */     // MIs[2] Operand 1
     /* 421587 */     // No operand predicates
     /* 421587 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 421589 */     // (splat_vector:{ *:[nxv4i32] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4i32] } ZPR:{ *:[nxv4i32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 421589 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 421592 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421594 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 421598 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 421601 */     GIR_RootConstrainSelectedInstOperands,
     /* 421602 */     // GIR_Coverage, 2708,
     /* 421602 */     GIR_EraseRootFromParent_Done,
     /* 421603 */   // Label 8217: @421603
     /* 421603 */   GIM_Try, /*On fail goto*//*Label 8218*/ GIMT_Encode4(421660), // Rule ID 9057 //
     /* 421608 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421611 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421615 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 421619 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 421623 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 421627 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421632 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 421636 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 421640 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_s),
     /* 421644 */     // MIs[2] Operand 1
     /* 421644 */     // No operand predicates
     /* 421644 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 421646 */     // (splat_vector:{ *:[nxv4f32] } (vector_extract:{ *:[f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index))  =>  (DUP_ZZI_S:{ *:[nxv4f32] } ZPR:{ *:[nxv4f32] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_s>>:$index)
     /* 421646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 421649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421651 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 421655 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 421658 */     GIR_RootConstrainSelectedInstOperands,
     /* 421659 */     // GIR_Coverage, 9057,
     /* 421659 */     GIR_EraseRootFromParent_Done,
     /* 421660 */   // Label 8218: @421660
     /* 421660 */   GIM_Try, /*On fail goto*//*Label 8219*/ GIMT_Encode4(421694), // Rule ID 9089 //
     /* 421665 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 421676 */     GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm32),
     /* 421680 */     // MIs[1] Operand 1
     /* 421680 */     // No operand predicates
     /* 421680 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421682 */     // (splat_vector:{ *:[nxv4f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>><<X:fpimm32XForm>>:$imm8)  =>  (FDUP_ZI_S:{ *:[nxv4f32] } (fpimm32XForm:{ *:[f32] } (fpimm:{ *:[f32] })<<P:Predicate_fpimm32>>:$imm8))
     /* 421682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_S),
     /* 421685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421687 */     GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm32), // imm8
     /* 421692 */     GIR_RootConstrainSelectedInstOperands,
     /* 421693 */     // GIR_Coverage, 9089,
     /* 421693 */     GIR_EraseRootFromParent_Done,
     /* 421694 */   // Label 8219: @421694
     /* 421694 */   GIM_Try, /*On fail goto*//*Label 8220*/ GIMT_Encode4(421713), // Rule ID 2423 //
     /* 421699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421702 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 421706 */     // (splat_vector:{ *:[nxv4i32] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_S:{ *:[nxv4i32] } GPR32sp:{ *:[i32] }:$Rn)
     /* 421706 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_S),
     /* 421711 */     GIR_RootConstrainSelectedInstOperands,
     /* 421712 */     // GIR_Coverage, 2423,
     /* 421712 */     GIR_Done,
     /* 421713 */   // Label 8220: @421713
     /* 421713 */   GIM_Try, /*On fail goto*//*Label 8221*/ GIMT_Encode4(421789), // Rule ID 9067 //
     /* 421718 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421721 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421725 */     // (splat_vector:{ *:[nxv4f32] } FPR32:{ *:[f32] }:$src)  =>  (DUP_ZZI_S:{ *:[nxv4f32] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR32:{ *:[f32] }:$src, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 421725 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 421728 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 421732 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421737 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 421739 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 421742 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 421746 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421751 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 421754 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 421758 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 421761 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421766 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421771 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 421776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_S),
     /* 421779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421781 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421784 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421787 */     GIR_RootConstrainSelectedInstOperands,
     /* 421788 */     // GIR_Coverage, 9067,
     /* 421788 */     GIR_EraseRootFromParent_Done,
     /* 421789 */   // Label 8221: @421789
     /* 421789 */   GIM_Reject,
     /* 421790 */ // Label 8214: @421790
     /* 421790 */ GIM_Reject,
     /* 421791 */ // Label 8184: @421791
     /* 421791 */ GIM_Try, /*On fail goto*//*Label 8222*/ GIMT_Encode4(421852), // Rule ID 6629 //
     /* 421796 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 421802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421806 */   GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 421810 */   // (splat_vector:{ *:[nxv8i16] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv8i16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 421810 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 421813 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 421817 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421822 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 421825 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 421827 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 421830 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 421832 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421835 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421838 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 421841 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421846 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421851 */   // GIR_Coverage, 6629,
     /* 421851 */   GIR_EraseRootFromParent_Done,
     /* 421852 */ // Label 8222: @421852
     /* 421852 */ GIM_Try, /*On fail goto*//*Label 8223*/ GIMT_Encode4(421923), // Rule ID 6636 //
     /* 421857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 421860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 421863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421867 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421871 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 421875 */   GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm0),
     /* 421879 */   // MIs[1] Operand 1
     /* 421879 */   // No operand predicates
     /* 421879 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 421881 */   // (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm0>>)  =>  (SUBREG_TO_REG:{ *:[nxv8f16] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 421881 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 421884 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 421888 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 421893 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 421896 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 421898 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 421901 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 421903 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 421906 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 421909 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 421912 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421917 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 421922 */   // GIR_Coverage, 6636,
     /* 421922 */   GIR_EraseRootFromParent_Done,
     /* 421923 */ // Label 8223: @421923
     /* 421923 */ GIM_Try, /*On fail goto*//*Label 8224*/ GIMT_Encode4(421987), // Rule ID 2705 //
     /* 421928 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421931 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 421934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421938 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 421942 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 421946 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 421950 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 421954 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 421959 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 421963 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 421967 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 421971 */   // MIs[2] Operand 1
     /* 421971 */   // No operand predicates
     /* 421971 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 421973 */   // (splat_vector:{ *:[nxv8i16] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv8i16] } ZPR:{ *:[nxv8i16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 421973 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 421976 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 421978 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 421982 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 421985 */   GIR_RootConstrainSelectedInstOperands,
     /* 421986 */   // GIR_Coverage, 2705,
     /* 421986 */   GIR_EraseRootFromParent_Done,
     /* 421987 */ // Label 8224: @421987
     /* 421987 */ GIM_Try, /*On fail goto*//*Label 8225*/ GIMT_Encode4(422051), // Rule ID 9051 //
     /* 421992 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 421995 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 421998 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422002 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422006 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 422010 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 422014 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 422018 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422023 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 422027 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 422031 */   GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_h),
     /* 422035 */   // MIs[2] Operand 1
     /* 422035 */   // No operand predicates
     /* 422035 */   GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 422037 */   // (splat_vector:{ *:[nxv8f16] } (vector_extract:{ *:[f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index))  =>  (DUP_ZZI_H:{ *:[nxv8f16] } ZPR:{ *:[nxv8f16] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_h>>:$index)
     /* 422037 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 422040 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 422042 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 422046 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 422049 */   GIR_RootConstrainSelectedInstOperands,
     /* 422050 */   // GIR_Coverage, 9051,
     /* 422050 */   GIR_EraseRootFromParent_Done,
     /* 422051 */ // Label 8225: @422051
     /* 422051 */ GIM_Try, /*On fail goto*//*Label 8226*/ GIMT_Encode4(422092), // Rule ID 9086 //
     /* 422056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 422059 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 422062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422066 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422070 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
     /* 422074 */   GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm16),
     /* 422078 */   // MIs[1] Operand 1
     /* 422078 */   // No operand predicates
     /* 422078 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 422080 */   // (splat_vector:{ *:[nxv8f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>><<X:fpimm16XForm>>:$imm8)  =>  (FDUP_ZI_H:{ *:[nxv8f16] } (fpimm16XForm:{ *:[f16] } (fpimm:{ *:[f16] })<<P:Predicate_fpimm16>>:$imm8))
     /* 422080 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FDUP_ZI_H),
     /* 422083 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 422085 */   GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPImm16), // imm8
     /* 422090 */   GIR_RootConstrainSelectedInstOperands,
     /* 422091 */   // GIR_Coverage, 9086,
     /* 422091 */   GIR_EraseRootFromParent_Done,
     /* 422092 */ // Label 8226: @422092
     /* 422092 */ GIM_Try, /*On fail goto*//*Label 8227*/ GIMT_Encode4(422118), // Rule ID 2422 //
     /* 422097 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 422100 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 422103 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422107 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 422111 */   // (splat_vector:{ *:[nxv8i16] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_H:{ *:[nxv8i16] } GPR32sp:{ *:[i32] }:$Rn)
     /* 422111 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_H),
     /* 422116 */   GIR_RootConstrainSelectedInstOperands,
     /* 422117 */   // GIR_Coverage, 2422,
     /* 422117 */   GIR_Done,
     /* 422118 */ // Label 8227: @422118
     /* 422118 */ GIM_Try, /*On fail goto*//*Label 8228*/ GIMT_Encode4(422201), // Rule ID 9064 //
     /* 422123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 422126 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 422129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422133 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422137 */   // (splat_vector:{ *:[nxv8f16] } FPR16:{ *:[f16] }:$src)  =>  (DUP_ZZI_H:{ *:[nxv8f16] } (INSERT_SUBREG:{ *:[nxv16i8] } (IMPLICIT_DEF:{ *:[nxv16i8] }), FPR16:{ *:[f16] }:$src, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 422137 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_nxv16s8,
     /* 422140 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 422144 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422149 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 422151 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_nxv16s8,
     /* 422154 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 422158 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422163 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 422166 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 422170 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 422173 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422178 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422183 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 422188 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_H),
     /* 422191 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 422193 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 422196 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 422199 */   GIR_RootConstrainSelectedInstOperands,
     /* 422200 */   // GIR_Coverage, 9064,
     /* 422200 */   GIR_EraseRootFromParent_Done,
     /* 422201 */ // Label 8228: @422201
     /* 422201 */ GIM_Reject,
     /* 422202 */ // Label 8185: @422202
     /* 422202 */ GIM_Try, /*On fail goto*//*Label 8229*/ GIMT_Encode4(422345),
     /* 422207 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 422210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422214 */   GIM_Try, /*On fail goto*//*Label 8230*/ GIMT_Encode4(422268), // Rule ID 6630 //
     /* 422219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 422222 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /* 422226 */     // (splat_vector:{ *:[nxv16i8] } 0:{ *:[i32] })  =>  (SUBREG_TO_REG:{ *:[nxv16i8] } 0:{ *:[i32] }, (MOVIv2d_ns:{ *:[f128] } 0:{ *:[i32] }), zsub:{ *:[i32] })
     /* 422226 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 422229 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::MOVIv2d_ns),
     /* 422233 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422238 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 422241 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 422243 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 422246 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 422248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 422251 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 422254 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/43,
     /* 422257 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422262 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 422267 */     // GIR_Coverage, 6630,
     /* 422267 */     GIR_EraseRootFromParent_Done,
     /* 422268 */   // Label 8230: @422268
     /* 422268 */   GIM_Try, /*On fail goto*//*Label 8231*/ GIMT_Encode4(422325), // Rule ID 2702 //
     /* 422273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 422276 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422280 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 422284 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 422288 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 422292 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 422297 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 422301 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 422305 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_sve_elm_idx_extdup_b),
     /* 422309 */     // MIs[2] Operand 1
     /* 422309 */     // No operand predicates
     /* 422309 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 422311 */     // (splat_vector:{ *:[nxv16i8] } (vector_extract:{ *:[i32] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index))  =>  (DUP_ZZI_B:{ *:[nxv16i8] } ZPR:{ *:[nxv16i8] }:$vec, (imm:{ *:[i64] })<<P:Predicate_sve_elm_idx_extdup_b>>:$index)
     /* 422311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZZI_B),
     /* 422314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zd]
     /* 422316 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
     /* 422320 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // index
     /* 422323 */     GIR_RootConstrainSelectedInstOperands,
     /* 422324 */     // GIR_Coverage, 2702,
     /* 422324 */     GIR_EraseRootFromParent_Done,
     /* 422325 */   // Label 8231: @422325
     /* 422325 */   GIM_Try, /*On fail goto*//*Label 8232*/ GIMT_Encode4(422344), // Rule ID 2421 //
     /* 422330 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 422333 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32spRegClassID),
     /* 422337 */     // (splat_vector:{ *:[nxv16i8] } GPR32sp:{ *:[i32] }:$Rn)  =>  (DUP_ZR_B:{ *:[nxv16i8] } GPR32sp:{ *:[i32] }:$Rn)
     /* 422337 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUP_ZR_B),
     /* 422342 */     GIR_RootConstrainSelectedInstOperands,
     /* 422343 */     // GIR_Coverage, 2421,
     /* 422343 */     GIR_Done,
     /* 422344 */   // Label 8232: @422344
     /* 422344 */   GIM_Reject,
     /* 422345 */ // Label 8229: @422345
     /* 422345 */ GIM_Reject,
     /* 422346 */ // Label 8186: @422346
     /* 422346 */ GIM_Reject,
     /* 422347 */ // Label 103: @422347
     /* 422347 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(4), /*)*//*default:*//*Label 8235*/ GIMT_Encode4(422498),
     /* 422358 */ /*GILLT_s32*//*Label 8233*/ GIMT_Encode4(422366),
     /* 422362 */ /*GILLT_s64*//*Label 8234*/ GIMT_Encode4(422432),
     /* 422366 */ // Label 8233: @422366
     /* 422366 */ GIM_Try, /*On fail goto*//*Label 8236*/ GIMT_Encode4(422431),
     /* 422371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 422374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422382 */   GIM_Try, /*On fail goto*//*Label 8237*/ GIMT_Encode4(422397), // Rule ID 2352 //
     /* 422387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 422390 */     // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CTZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 422390 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZWr),
     /* 422395 */     GIR_RootConstrainSelectedInstOperands,
     /* 422396 */     // GIR_Coverage, 2352,
     /* 422396 */     GIR_Done,
     /* 422397 */   // Label 8237: @422397
     /* 422397 */   GIM_Try, /*On fail goto*//*Label 8238*/ GIMT_Encode4(422430), // Rule ID 4103 //
     /* 422402 */     // (cttz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CLZWr:{ *:[i32] } (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn))
     /* 422402 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 422405 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
     /* 422409 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422414 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 422418 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 422420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
     /* 422423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422425 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 422428 */     GIR_RootConstrainSelectedInstOperands,
     /* 422429 */     // GIR_Coverage, 4103,
     /* 422429 */     GIR_EraseRootFromParent_Done,
     /* 422430 */   // Label 8238: @422430
     /* 422430 */   GIM_Reject,
     /* 422431 */ // Label 8236: @422431
     /* 422431 */ GIM_Reject,
     /* 422432 */ // Label 8234: @422432
     /* 422432 */ GIM_Try, /*On fail goto*//*Label 8239*/ GIMT_Encode4(422497),
     /* 422437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 422440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 422444 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 422448 */   GIM_Try, /*On fail goto*//*Label 8240*/ GIMT_Encode4(422463), // Rule ID 2353 //
     /* 422453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 422456 */     // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CTZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 422456 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CTZXr),
     /* 422461 */     GIR_RootConstrainSelectedInstOperands,
     /* 422462 */     // GIR_Coverage, 2353,
     /* 422462 */     GIR_Done,
     /* 422463 */   // Label 8240: @422463
     /* 422463 */   GIM_Try, /*On fail goto*//*Label 8241*/ GIMT_Encode4(422496), // Rule ID 4104 //
     /* 422468 */     // (cttz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CLZXr:{ *:[i64] } (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn))
     /* 422468 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 422471 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
     /* 422475 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 422480 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 422484 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 422486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
     /* 422489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422491 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 422494 */     GIR_RootConstrainSelectedInstOperands,
     /* 422495 */     // GIR_Coverage, 4104,
     /* 422495 */     GIR_EraseRootFromParent_Done,
     /* 422496 */   // Label 8241: @422496
     /* 422496 */   GIM_Reject,
     /* 422497 */ // Label 8239: @422497
     /* 422497 */ GIM_Reject,
     /* 422498 */ // Label 8235: @422498
     /* 422498 */ GIM_Reject,
     /* 422499 */ // Label 104: @422499
     /* 422499 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 8250*/ GIMT_Encode4(423172),
     /* 422510 */ /*GILLT_s32*//*Label 8242*/ GIMT_Encode4(422550),
     /* 422514 */ /*GILLT_s64*//*Label 8243*/ GIMT_Encode4(422780), GIMT_Encode4(0),
     /* 422522 */ /*GILLT_v2s32*//*Label 8244*/ GIMT_Encode4(423010), GIMT_Encode4(0),
     /* 422530 */ /*GILLT_v4s16*//*Label 8245*/ GIMT_Encode4(423037),
     /* 422534 */ /*GILLT_v4s32*//*Label 8246*/ GIMT_Encode4(423064),
     /* 422538 */ /*GILLT_v8s8*//*Label 8247*/ GIMT_Encode4(423091),
     /* 422542 */ /*GILLT_v8s16*//*Label 8248*/ GIMT_Encode4(423118),
     /* 422546 */ /*GILLT_v16s8*//*Label 8249*/ GIMT_Encode4(423145),
     /* 422550 */ // Label 8242: @422550
     /* 422550 */ GIM_Try, /*On fail goto*//*Label 8251*/ GIMT_Encode4(422779),
     /* 422555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 422558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422562 */   GIM_Try, /*On fail goto*//*Label 8252*/ GIMT_Encode4(422662), // Rule ID 4105 //
     /* 422567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 422575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 422579 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 422583 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 422587 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 422591 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 422595 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 422599 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 422603 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 422607 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 422611 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 422615 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 422619 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
     /* 422623 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 422627 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422632 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
     /* 422636 */     // MIs[3] Rn
     /* 422636 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /* 422641 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 422645 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 422649 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 422651 */     // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] }), GPR32:{ *:[i32] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i32] }))  =>  (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 422651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
     /* 422654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422656 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /* 422660 */     GIR_RootConstrainSelectedInstOperands,
     /* 422661 */     // GIR_Coverage, 4105,
     /* 422661 */     GIR_EraseRootFromParent_Done,
     /* 422662 */   // Label 8252: @422662
     /* 422662 */   GIM_Try, /*On fail goto*//*Label 8253*/ GIMT_Encode4(422762), // Rule ID 14853 //
     /* 422667 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422671 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 422675 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 422679 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 422683 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 422687 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 422691 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 422695 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 422699 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 422703 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 422707 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 422711 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
     /* 422715 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422720 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 422724 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 422728 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 422732 */     // MIs[4] Rn
     /* 422732 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 422737 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 31,
     /* 422741 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 422745 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 422749 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 422751 */     // (ctlz:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, (sra:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 31:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i32] }))  =>  (CLSWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 422751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSWr),
     /* 422754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422756 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 422760 */     GIR_RootConstrainSelectedInstOperands,
     /* 422761 */     // GIR_Coverage, 14853,
     /* 422761 */     GIR_EraseRootFromParent_Done,
     /* 422762 */   // Label 8253: @422762
     /* 422762 */   GIM_Try, /*On fail goto*//*Label 8254*/ GIMT_Encode4(422778), // Rule ID 174 //
     /* 422767 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 422771 */     // (ctlz:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CLZWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 422771 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZWr),
     /* 422776 */     GIR_RootConstrainSelectedInstOperands,
     /* 422777 */     // GIR_Coverage, 174,
     /* 422777 */     GIR_Done,
     /* 422778 */   // Label 8254: @422778
     /* 422778 */   GIM_Reject,
     /* 422779 */ // Label 8251: @422779
     /* 422779 */ GIM_Reject,
     /* 422780 */ // Label 8243: @422780
     /* 422780 */ GIM_Try, /*On fail goto*//*Label 8255*/ GIMT_Encode4(423009),
     /* 422785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 422788 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 422792 */   GIM_Try, /*On fail goto*//*Label 8256*/ GIMT_Encode4(422892), // Rule ID 4106 //
     /* 422797 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422801 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 422805 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 422809 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 422813 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 422817 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 422821 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 422825 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 422829 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 422833 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 422837 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 422841 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 422845 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 422849 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s64,
     /* 422853 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 422857 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 422862 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
     /* 422866 */     // MIs[3] Rn
     /* 422866 */     GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/4, /*OtherOpIdx*/1,
     /* 422871 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 422875 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 422879 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 422881 */     // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] }), GPR64:{ *:[i64] }:$Rn), 1:{ *:[i64] }), 1:{ *:[i64] }))  =>  (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 422881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
     /* 422884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
     /* 422890 */     GIR_RootConstrainSelectedInstOperands,
     /* 422891 */     // GIR_Coverage, 4106,
     /* 422891 */     GIR_EraseRootFromParent_Done,
     /* 422892 */   // Label 8256: @422892
     /* 422892 */   GIM_Try, /*On fail goto*//*Label 8257*/ GIMT_Encode4(422992), // Rule ID 14854 //
     /* 422897 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 422901 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /* 422905 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 422909 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 422913 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 422917 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 422921 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 422925 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 422929 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 422933 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 422937 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 422941 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 422945 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 422950 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 422954 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 422958 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 422962 */     // MIs[4] Rn
     /* 422962 */     GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
     /* 422967 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 63,
     /* 422971 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 422975 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 422979 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 422981 */     // (ctlz:{ *:[i64] } (or:{ *:[i64] } (shl:{ *:[i64] } (xor:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, (sra:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 63:{ *:[i64] })), 1:{ *:[i64] }), 1:{ *:[i64] }))  =>  (CLSXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 422981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CLSXr),
     /* 422984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 422986 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 422990 */     GIR_RootConstrainSelectedInstOperands,
     /* 422991 */     // GIR_Coverage, 14854,
     /* 422991 */     GIR_EraseRootFromParent_Done,
     /* 422992 */   // Label 8257: @422992
     /* 422992 */   GIM_Try, /*On fail goto*//*Label 8258*/ GIMT_Encode4(423008), // Rule ID 175 //
     /* 422997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423001 */     // (ctlz:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CLZXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 423001 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZXr),
     /* 423006 */     GIR_RootConstrainSelectedInstOperands,
     /* 423007 */     // GIR_Coverage, 175,
     /* 423007 */     GIR_Done,
     /* 423008 */   // Label 8258: @423008
     /* 423008 */   GIM_Reject,
     /* 423009 */ // Label 8255: @423009
     /* 423009 */ GIM_Reject,
     /* 423010 */ // Label 8244: @423010
     /* 423010 */ GIM_Try, /*On fail goto*//*Label 8259*/ GIMT_Encode4(423036), // Rule ID 750 //
     /* 423015 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423021 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423025 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423029 */   // (ctlz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (CLZv2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 423029 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv2i32),
     /* 423034 */   GIR_RootConstrainSelectedInstOperands,
     /* 423035 */   // GIR_Coverage, 750,
     /* 423035 */   GIR_Done,
     /* 423036 */ // Label 8259: @423036
     /* 423036 */ GIM_Reject,
     /* 423037 */ // Label 8245: @423037
     /* 423037 */ GIM_Try, /*On fail goto*//*Label 8260*/ GIMT_Encode4(423063), // Rule ID 748 //
     /* 423042 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 423048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423052 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423056 */   // (ctlz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (CLZv4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 423056 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i16),
     /* 423061 */   GIR_RootConstrainSelectedInstOperands,
     /* 423062 */   // GIR_Coverage, 748,
     /* 423062 */   GIR_Done,
     /* 423063 */ // Label 8260: @423063
     /* 423063 */ GIM_Reject,
     /* 423064 */ // Label 8246: @423064
     /* 423064 */ GIM_Try, /*On fail goto*//*Label 8261*/ GIMT_Encode4(423090), // Rule ID 751 //
     /* 423069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 423075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423079 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423083 */   // (ctlz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (CLZv4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 423083 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv4i32),
     /* 423088 */   GIR_RootConstrainSelectedInstOperands,
     /* 423089 */   // GIR_Coverage, 751,
     /* 423089 */   GIR_Done,
     /* 423090 */ // Label 8261: @423090
     /* 423090 */ GIM_Reject,
     /* 423091 */ // Label 8247: @423091
     /* 423091 */ GIM_Try, /*On fail goto*//*Label 8262*/ GIMT_Encode4(423117), // Rule ID 746 //
     /* 423096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423099 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423102 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423106 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423110 */   // (ctlz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (CLZv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 423110 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i8),
     /* 423115 */   GIR_RootConstrainSelectedInstOperands,
     /* 423116 */   // GIR_Coverage, 746,
     /* 423116 */   GIR_Done,
     /* 423117 */ // Label 8262: @423117
     /* 423117 */ GIM_Reject,
     /* 423118 */ // Label 8248: @423118
     /* 423118 */ GIM_Try, /*On fail goto*//*Label 8263*/ GIMT_Encode4(423144), // Rule ID 749 //
     /* 423123 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423126 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 423129 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423133 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423137 */   // (ctlz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (CLZv8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 423137 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv8i16),
     /* 423142 */   GIR_RootConstrainSelectedInstOperands,
     /* 423143 */   // GIR_Coverage, 749,
     /* 423143 */   GIR_Done,
     /* 423144 */ // Label 8263: @423144
     /* 423144 */ GIM_Reject,
     /* 423145 */ // Label 8249: @423145
     /* 423145 */ GIM_Try, /*On fail goto*//*Label 8264*/ GIMT_Encode4(423171), // Rule ID 747 //
     /* 423150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423153 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423160 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423164 */   // (ctlz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (CLZv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 423164 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CLZv16i8),
     /* 423169 */   GIR_RootConstrainSelectedInstOperands,
     /* 423170 */   // GIR_Coverage, 747,
     /* 423170 */   GIR_Done,
     /* 423171 */ // Label 8264: @423171
     /* 423171 */ GIM_Reject,
     /* 423172 */ // Label 8250: @423172
     /* 423172 */ GIM_Reject,
     /* 423173 */ // Label 105: @423173
     /* 423173 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 8269*/ GIMT_Encode4(423332),
     /* 423184 */ /*GILLT_s32*//*Label 8265*/ GIMT_Encode4(423224),
     /* 423188 */ /*GILLT_s64*//*Label 8266*/ GIMT_Encode4(423251), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 423212 */ /*GILLT_v8s8*//*Label 8267*/ GIMT_Encode4(423278), GIMT_Encode4(0),
     /* 423220 */ /*GILLT_v16s8*//*Label 8268*/ GIMT_Encode4(423305),
     /* 423224 */ // Label 8265: @423224
     /* 423224 */ GIM_Try, /*On fail goto*//*Label 8270*/ GIMT_Encode4(423250), // Rule ID 2350 //
     /* 423229 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 423232 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 423235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423239 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423243 */   // (ctpop:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (CNTWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 423243 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTWr),
     /* 423248 */   GIR_RootConstrainSelectedInstOperands,
     /* 423249 */   // GIR_Coverage, 2350,
     /* 423249 */   GIR_Done,
     /* 423250 */ // Label 8270: @423250
     /* 423250 */ GIM_Reject,
     /* 423251 */ // Label 8266: @423251
     /* 423251 */ GIM_Try, /*On fail goto*//*Label 8271*/ GIMT_Encode4(423277), // Rule ID 2351 //
     /* 423256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCSSC),
     /* 423259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 423262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423266 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423270 */   // (ctpop:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (CNTXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 423270 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTXr),
     /* 423275 */   GIR_RootConstrainSelectedInstOperands,
     /* 423276 */   // GIR_Coverage, 2351,
     /* 423276 */   GIR_Done,
     /* 423277 */ // Label 8271: @423277
     /* 423277 */ GIM_Reject,
     /* 423278 */ // Label 8267: @423278
     /* 423278 */ GIM_Try, /*On fail goto*//*Label 8272*/ GIMT_Encode4(423304), // Rule ID 794 //
     /* 423283 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423293 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423297 */   // (ctpop:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (CNTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 423297 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv8i8),
     /* 423302 */   GIR_RootConstrainSelectedInstOperands,
     /* 423303 */   // GIR_Coverage, 794,
     /* 423303 */   GIR_Done,
     /* 423304 */ // Label 8272: @423304
     /* 423304 */ GIM_Reject,
     /* 423305 */ // Label 8268: @423305
     /* 423305 */ GIM_Try, /*On fail goto*//*Label 8273*/ GIMT_Encode4(423331), // Rule ID 795 //
     /* 423310 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423316 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423320 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423324 */   // (ctpop:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (CNTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 423324 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::CNTv16i8),
     /* 423329 */   GIR_RootConstrainSelectedInstOperands,
     /* 423330 */   // GIR_Coverage, 795,
     /* 423330 */   GIR_Done,
     /* 423331 */ // Label 8273: @423331
     /* 423331 */ GIM_Reject,
     /* 423332 */ // Label 8269: @423332
     /* 423332 */ GIM_Reject,
     /* 423333 */ // Label 106: @423333
     /* 423333 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 8281*/ GIMT_Encode4(423646),
     /* 423344 */ /*GILLT_s32*//*Label 8274*/ GIMT_Encode4(423380),
     /* 423348 */ /*GILLT_s64*//*Label 8275*/ GIMT_Encode4(423453), GIMT_Encode4(0),
     /* 423356 */ /*GILLT_v2s32*//*Label 8276*/ GIMT_Encode4(423526),
     /* 423360 */ /*GILLT_v2s64*//*Label 8277*/ GIMT_Encode4(423550),
     /* 423364 */ /*GILLT_v4s16*//*Label 8278*/ GIMT_Encode4(423574),
     /* 423368 */ /*GILLT_v4s32*//*Label 8279*/ GIMT_Encode4(423598), GIMT_Encode4(0),
     /* 423376 */ /*GILLT_v8s16*//*Label 8280*/ GIMT_Encode4(423622),
     /* 423380 */ // Label 8274: @423380
     /* 423380 */ GIM_Try, /*On fail goto*//*Label 8282*/ GIMT_Encode4(423452),
     /* 423385 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 423388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423392 */   GIM_Try, /*On fail goto*//*Label 8283*/ GIMT_Encode4(423435), // Rule ID 4107 //
     /* 423397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 423401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
     /* 423405 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 423409 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 423413 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423418 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
     /* 423422 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 423424 */     // (bswap:{ *:[i32] } (rotr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn, 16:{ *:[i64] }))  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 423424 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 423427 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 423429 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 423433 */     GIR_RootConstrainSelectedInstOperands,
     /* 423434 */     // GIR_Coverage, 4107,
     /* 423434 */     GIR_EraseRootFromParent_Done,
     /* 423435 */   // Label 8283: @423435
     /* 423435 */   GIM_Try, /*On fail goto*//*Label 8284*/ GIMT_Encode4(423451), // Rule ID 179 //
     /* 423440 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423444 */     // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (REVWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 423444 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVWr),
     /* 423449 */     GIR_RootConstrainSelectedInstOperands,
     /* 423450 */     // GIR_Coverage, 179,
     /* 423450 */     GIR_Done,
     /* 423451 */   // Label 8284: @423451
     /* 423451 */   GIM_Reject,
     /* 423452 */ // Label 8282: @423452
     /* 423452 */ GIM_Reject,
     /* 423453 */ // Label 8275: @423453
     /* 423453 */ GIM_Try, /*On fail goto*//*Label 8285*/ GIMT_Encode4(423525),
     /* 423458 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 423461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423465 */   GIM_Try, /*On fail goto*//*Label 8286*/ GIMT_Encode4(423508), // Rule ID 4108 //
     /* 423470 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 423474 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ROTR),
     /* 423478 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 423482 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 423486 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423491 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 32,
     /* 423495 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 423497 */     // (bswap:{ *:[i64] } (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn, 32:{ *:[i64] }))  =>  (REV32Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 423497 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::REV32Xr),
     /* 423500 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 423502 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 423506 */     GIR_RootConstrainSelectedInstOperands,
     /* 423507 */     // GIR_Coverage, 4108,
     /* 423507 */     GIR_EraseRootFromParent_Done,
     /* 423508 */   // Label 8286: @423508
     /* 423508 */   GIM_Try, /*On fail goto*//*Label 8287*/ GIMT_Encode4(423524), // Rule ID 180 //
     /* 423513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423517 */     // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (REVXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 423517 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REVXr),
     /* 423522 */     GIR_RootConstrainSelectedInstOperands,
     /* 423523 */     // GIR_Coverage, 180,
     /* 423523 */     GIR_Done,
     /* 423524 */   // Label 8287: @423524
     /* 423524 */   GIM_Reject,
     /* 423525 */ // Label 8285: @423525
     /* 423525 */ GIM_Reject,
     /* 423526 */ // Label 8276: @423526
     /* 423526 */ GIM_Try, /*On fail goto*//*Label 8288*/ GIMT_Encode4(423549), // Rule ID 5059 //
     /* 423531 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423534 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423538 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423542 */   // (bswap:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (REV32v8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 423542 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 423547 */   GIR_RootConstrainSelectedInstOperands,
     /* 423548 */   // GIR_Coverage, 5059,
     /* 423548 */   GIR_Done,
     /* 423549 */ // Label 8288: @423549
     /* 423549 */ GIM_Reject,
     /* 423550 */ // Label 8277: @423550
     /* 423550 */ GIM_Try, /*On fail goto*//*Label 8289*/ GIMT_Encode4(423573), // Rule ID 5061 //
     /* 423555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 423558 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423562 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423566 */   // (bswap:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)  =>  (REV64v16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 423566 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 423571 */   GIR_RootConstrainSelectedInstOperands,
     /* 423572 */   // GIR_Coverage, 5061,
     /* 423572 */   GIR_Done,
     /* 423573 */ // Label 8289: @423573
     /* 423573 */ GIM_Reject,
     /* 423574 */ // Label 8278: @423574
     /* 423574 */ GIM_Try, /*On fail goto*//*Label 8290*/ GIMT_Encode4(423597), // Rule ID 5057 //
     /* 423579 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 423582 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423586 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423590 */   // (bswap:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV16v8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 423590 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 423595 */   GIR_RootConstrainSelectedInstOperands,
     /* 423596 */   // GIR_Coverage, 5057,
     /* 423596 */   GIR_Done,
     /* 423597 */ // Label 8290: @423597
     /* 423597 */ GIM_Reject,
     /* 423598 */ // Label 8279: @423598
     /* 423598 */ GIM_Try, /*On fail goto*//*Label 8291*/ GIMT_Encode4(423621), // Rule ID 5060 //
     /* 423603 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 423606 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423610 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423614 */   // (bswap:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (REV32v16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 423614 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 423619 */   GIR_RootConstrainSelectedInstOperands,
     /* 423620 */   // GIR_Coverage, 5060,
     /* 423620 */   GIR_Done,
     /* 423621 */ // Label 8291: @423621
     /* 423621 */ GIM_Reject,
     /* 423622 */ // Label 8280: @423622
     /* 423622 */ GIM_Try, /*On fail goto*//*Label 8292*/ GIMT_Encode4(423645), // Rule ID 5058 //
     /* 423627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 423630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423634 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423638 */   // (bswap:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV16v16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 423638 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 423643 */   GIR_RootConstrainSelectedInstOperands,
     /* 423644 */   // GIR_Coverage, 5058,
     /* 423644 */   GIR_Done,
     /* 423645 */ // Label 8292: @423645
     /* 423645 */ GIM_Reject,
     /* 423646 */ // Label 8281: @423646
     /* 423646 */ GIM_Reject,
     /* 423647 */ // Label 107: @423647
     /* 423647 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 8297*/ GIMT_Encode4(423800),
     /* 423658 */ /*GILLT_s32*//*Label 8293*/ GIMT_Encode4(423698),
     /* 423662 */ /*GILLT_s64*//*Label 8294*/ GIMT_Encode4(423722), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 423686 */ /*GILLT_v8s8*//*Label 8295*/ GIMT_Encode4(423746), GIMT_Encode4(0),
     /* 423694 */ /*GILLT_v16s8*//*Label 8296*/ GIMT_Encode4(423773),
     /* 423698 */ // Label 8293: @423698
     /* 423698 */ GIM_Try, /*On fail goto*//*Label 8298*/ GIMT_Encode4(423721), // Rule ID 176 //
     /* 423703 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 423706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423710 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 423714 */   // (bitreverse:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (RBITWr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 423714 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITWr),
     /* 423719 */   GIR_RootConstrainSelectedInstOperands,
     /* 423720 */   // GIR_Coverage, 176,
     /* 423720 */   GIR_Done,
     /* 423721 */ // Label 8298: @423721
     /* 423721 */ GIM_Reject,
     /* 423722 */ // Label 8294: @423722
     /* 423722 */ GIM_Try, /*On fail goto*//*Label 8299*/ GIMT_Encode4(423745), // Rule ID 177 //
     /* 423727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 423730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423734 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 423738 */   // (bitreverse:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (RBITXr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 423738 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITXr),
     /* 423743 */   GIR_RootConstrainSelectedInstOperands,
     /* 423744 */   // GIR_Coverage, 177,
     /* 423744 */   GIR_Done,
     /* 423745 */ // Label 8299: @423745
     /* 423745 */ GIM_Reject,
     /* 423746 */ // Label 8295: @423746
     /* 423746 */ GIM_Try, /*On fail goto*//*Label 8300*/ GIMT_Encode4(423772), // Rule ID 1004 //
     /* 423751 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423754 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 423757 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423761 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423765 */   // (bitreverse:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (RBITv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 423765 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv8i8),
     /* 423770 */   GIR_RootConstrainSelectedInstOperands,
     /* 423771 */   // GIR_Coverage, 1004,
     /* 423771 */   GIR_Done,
     /* 423772 */ // Label 8300: @423772
     /* 423772 */ GIM_Reject,
     /* 423773 */ // Label 8296: @423773
     /* 423773 */ GIM_Try, /*On fail goto*//*Label 8301*/ GIMT_Encode4(423799), // Rule ID 1005 //
     /* 423778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423781 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 423784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423788 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423792 */   // (bitreverse:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (RBITv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 423792 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::RBITv16i8),
     /* 423797 */   GIR_RootConstrainSelectedInstOperands,
     /* 423798 */   // GIR_Coverage, 1005,
     /* 423798 */   GIR_Done,
     /* 423799 */ // Label 8301: @423799
     /* 423799 */ GIM_Reject,
     /* 423800 */ // Label 8297: @423800
     /* 423800 */ GIM_Reject,
     /* 423801 */ // Label 108: @423801
     /* 423801 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8310*/ GIMT_Encode4(424291),
     /* 423812 */ /*GILLT_s16*//*Label 8302*/ GIMT_Encode4(423852),
     /* 423816 */ /*GILLT_s32*//*Label 8303*/ GIMT_Encode4(423883),
     /* 423820 */ /*GILLT_s64*//*Label 8304*/ GIMT_Encode4(423914), GIMT_Encode4(0),
     /* 423828 */ /*GILLT_v2s32*//*Label 8305*/ GIMT_Encode4(423945),
     /* 423832 */ /*GILLT_v2s64*//*Label 8306*/ GIMT_Encode4(423976),
     /* 423836 */ /*GILLT_v4s16*//*Label 8307*/ GIMT_Encode4(424007),
     /* 423840 */ /*GILLT_v4s32*//*Label 8308*/ GIMT_Encode4(424038), GIMT_Encode4(0),
     /* 423848 */ /*GILLT_v8s16*//*Label 8309*/ GIMT_Encode4(424069),
     /* 423852 */ // Label 8302: @423852
     /* 423852 */ GIM_Try, /*On fail goto*//*Label 8311*/ GIMT_Encode4(423882), // Rule ID 594 //
     /* 423857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 423860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 423863 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423867 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 423871 */   // (fceil:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTPHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 423871 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPHr),
     /* 423876 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 423880 */   GIR_RootConstrainSelectedInstOperands,
     /* 423881 */   // GIR_Coverage, 594,
     /* 423881 */   GIR_Done,
     /* 423882 */ // Label 8311: @423882
     /* 423882 */ GIM_Reject,
     /* 423883 */ // Label 8303: @423883
     /* 423883 */ GIM_Try, /*On fail goto*//*Label 8312*/ GIMT_Encode4(423913), // Rule ID 596 //
     /* 423888 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 423891 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 423894 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423898 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 423902 */   // (fceil:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTPSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 423902 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPSr),
     /* 423907 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 423911 */   GIR_RootConstrainSelectedInstOperands,
     /* 423912 */   // GIR_Coverage, 596,
     /* 423912 */   GIR_Done,
     /* 423913 */ // Label 8312: @423913
     /* 423913 */ GIM_Reject,
     /* 423914 */ // Label 8304: @423914
     /* 423914 */ GIM_Try, /*On fail goto*//*Label 8313*/ GIMT_Encode4(423944), // Rule ID 598 //
     /* 423919 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 423922 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 423925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423929 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423933 */   // (fceil:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTPDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 423933 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPDr),
     /* 423938 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 423942 */   GIR_RootConstrainSelectedInstOperands,
     /* 423943 */   // GIR_Coverage, 598,
     /* 423943 */   GIR_Done,
     /* 423944 */ // Label 8313: @423944
     /* 423944 */ GIM_Reject,
     /* 423945 */ // Label 8305: @423945
     /* 423945 */ GIM_Try, /*On fail goto*//*Label 8314*/ GIMT_Encode4(423975), // Rule ID 943 //
     /* 423950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423953 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 423956 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423960 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 423964 */   // (fceil:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTPv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 423964 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f32),
     /* 423969 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 423973 */   GIR_RootConstrainSelectedInstOperands,
     /* 423974 */   // GIR_Coverage, 943,
     /* 423974 */   GIR_Done,
     /* 423975 */ // Label 8314: @423975
     /* 423975 */ GIM_Reject,
     /* 423976 */ // Label 8306: @423976
     /* 423976 */ GIM_Try, /*On fail goto*//*Label 8315*/ GIMT_Encode4(424006), // Rule ID 947 //
     /* 423981 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 423984 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 423987 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423991 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 423995 */   // (fceil:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTPv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 423995 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv2f64),
     /* 424000 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424004 */   GIR_RootConstrainSelectedInstOperands,
     /* 424005 */   // GIR_Coverage, 947,
     /* 424005 */   GIR_Done,
     /* 424006 */ // Label 8315: @424006
     /* 424006 */ GIM_Reject,
     /* 424007 */ // Label 8307: @424007
     /* 424007 */ GIM_Try, /*On fail goto*//*Label 8316*/ GIMT_Encode4(424037), // Rule ID 939 //
     /* 424012 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 424018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424026 */   // (fceil:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTPv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 424026 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f16),
     /* 424031 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424035 */   GIR_RootConstrainSelectedInstOperands,
     /* 424036 */   // GIR_Coverage, 939,
     /* 424036 */   GIR_Done,
     /* 424037 */ // Label 8316: @424037
     /* 424037 */ GIM_Reject,
     /* 424038 */ // Label 8308: @424038
     /* 424038 */ GIM_Try, /*On fail goto*//*Label 8317*/ GIMT_Encode4(424068), // Rule ID 945 //
     /* 424043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424046 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 424049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424053 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424057 */   // (fceil:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTPv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 424057 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 424062 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424066 */   GIR_RootConstrainSelectedInstOperands,
     /* 424067 */   // GIR_Coverage, 945,
     /* 424067 */   GIR_Done,
     /* 424068 */ // Label 8317: @424068
     /* 424068 */ GIM_Reject,
     /* 424069 */ // Label 8309: @424069
     /* 424069 */ GIM_Try, /*On fail goto*//*Label 8318*/ GIMT_Encode4(424290),
     /* 424074 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 424077 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424081 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424085 */   GIM_Try, /*On fail goto*//*Label 8319*/ GIMT_Encode4(424104), // Rule ID 941 //
     /* 424090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424093 */     // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTPv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 424093 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv8f16),
     /* 424098 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424102 */     GIR_RootConstrainSelectedInstOperands,
     /* 424103 */     // GIR_Coverage, 941,
     /* 424103 */     GIR_Done,
     /* 424104 */   // Label 8319: @424104
     /* 424104 */   GIM_Try, /*On fail goto*//*Label 8320*/ GIMT_Encode4(424289), // Rule ID 7646 //
     /* 424109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 424112 */     // (fceil:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTPv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTPv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 424112 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 424115 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 424119 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424124 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 424128 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 424130 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 424133 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 424137 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424142 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 424145 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 424147 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 424150 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 424154 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424159 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 424165 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424170 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424175 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 424178 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 424182 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424187 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 424190 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 424192 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 424195 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTPv4f32),
     /* 424199 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424204 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 424207 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 424209 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 424212 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 424216 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424221 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 424224 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 424226 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 424229 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 424233 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424238 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 424240 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 424243 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 424247 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424252 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 424255 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 424258 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 424261 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424266 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424271 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 424279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 424281 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 424284 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 424287 */     GIR_RootConstrainSelectedInstOperands,
     /* 424288 */     // GIR_Coverage, 7646,
     /* 424288 */     GIR_EraseRootFromParent_Done,
     /* 424289 */   // Label 8320: @424289
     /* 424289 */   GIM_Reject,
     /* 424290 */ // Label 8318: @424290
     /* 424290 */ GIM_Reject,
     /* 424291 */ // Label 8310: @424291
     /* 424291 */ GIM_Reject,
     /* 424292 */ // Label 109: @424292
     /* 424292 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8329*/ GIMT_Encode4(424591),
     /* 424303 */ /*GILLT_s16*//*Label 8321*/ GIMT_Encode4(424343),
     /* 424307 */ /*GILLT_s32*//*Label 8322*/ GIMT_Encode4(424374),
     /* 424311 */ /*GILLT_s64*//*Label 8323*/ GIMT_Encode4(424405), GIMT_Encode4(0),
     /* 424319 */ /*GILLT_v2s32*//*Label 8324*/ GIMT_Encode4(424436),
     /* 424323 */ /*GILLT_v2s64*//*Label 8325*/ GIMT_Encode4(424467),
     /* 424327 */ /*GILLT_v4s16*//*Label 8326*/ GIMT_Encode4(424498),
     /* 424331 */ /*GILLT_v4s32*//*Label 8327*/ GIMT_Encode4(424529), GIMT_Encode4(0),
     /* 424339 */ /*GILLT_v8s16*//*Label 8328*/ GIMT_Encode4(424560),
     /* 424343 */ // Label 8321: @424343
     /* 424343 */ GIM_Try, /*On fail goto*//*Label 8330*/ GIMT_Encode4(424373), // Rule ID 612 //
     /* 424348 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 424351 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 424354 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 424358 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 424362 */   // (fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 424362 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
     /* 424367 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424371 */   GIR_RootConstrainSelectedInstOperands,
     /* 424372 */   // GIR_Coverage, 612,
     /* 424372 */   GIR_Done,
     /* 424373 */ // Label 8330: @424373
     /* 424373 */ GIM_Reject,
     /* 424374 */ // Label 8322: @424374
     /* 424374 */ GIM_Try, /*On fail goto*//*Label 8331*/ GIMT_Encode4(424404), // Rule ID 614 //
     /* 424379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 424382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 424385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 424389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 424393 */   // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 424393 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
     /* 424398 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424402 */   GIR_RootConstrainSelectedInstOperands,
     /* 424403 */   // GIR_Coverage, 614,
     /* 424403 */   GIR_Done,
     /* 424404 */ // Label 8331: @424404
     /* 424404 */ GIM_Reject,
     /* 424405 */ // Label 8323: @424405
     /* 424405 */ GIM_Try, /*On fail goto*//*Label 8332*/ GIMT_Encode4(424435), // Rule ID 616 //
     /* 424410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 424413 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 424416 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424420 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424424 */   // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 424424 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
     /* 424429 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424433 */   GIR_RootConstrainSelectedInstOperands,
     /* 424434 */   // GIR_Coverage, 616,
     /* 424434 */   GIR_Done,
     /* 424435 */ // Label 8332: @424435
     /* 424435 */ GIM_Reject,
     /* 424436 */ // Label 8324: @424436
     /* 424436 */ GIM_Try, /*On fail goto*//*Label 8333*/ GIMT_Encode4(424466), // Rule ID 990 //
     /* 424441 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424444 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 424447 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424451 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424455 */   // (fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 424455 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
     /* 424460 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424464 */   GIR_RootConstrainSelectedInstOperands,
     /* 424465 */   // GIR_Coverage, 990,
     /* 424465 */   GIR_Done,
     /* 424466 */ // Label 8333: @424466
     /* 424466 */ GIM_Reject,
     /* 424467 */ // Label 8325: @424467
     /* 424467 */ GIM_Try, /*On fail goto*//*Label 8334*/ GIMT_Encode4(424497), // Rule ID 994 //
     /* 424472 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424475 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 424478 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424482 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424486 */   // (fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 424486 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
     /* 424491 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424495 */   GIR_RootConstrainSelectedInstOperands,
     /* 424496 */   // GIR_Coverage, 994,
     /* 424496 */   GIR_Done,
     /* 424497 */ // Label 8334: @424497
     /* 424497 */ GIM_Reject,
     /* 424498 */ // Label 8326: @424498
     /* 424498 */ GIM_Try, /*On fail goto*//*Label 8335*/ GIMT_Encode4(424528), // Rule ID 986 //
     /* 424503 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424506 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 424509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424513 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424517 */   // (fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 424517 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
     /* 424522 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424526 */   GIR_RootConstrainSelectedInstOperands,
     /* 424527 */   // GIR_Coverage, 986,
     /* 424527 */   GIR_Done,
     /* 424528 */ // Label 8335: @424528
     /* 424528 */ GIM_Reject,
     /* 424529 */ // Label 8327: @424529
     /* 424529 */ GIM_Try, /*On fail goto*//*Label 8336*/ GIMT_Encode4(424559), // Rule ID 992 //
     /* 424534 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424537 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 424540 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424544 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424548 */   // (fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 424548 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
     /* 424553 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424557 */   GIR_RootConstrainSelectedInstOperands,
     /* 424558 */   // GIR_Coverage, 992,
     /* 424558 */   GIR_Done,
     /* 424559 */ // Label 8336: @424559
     /* 424559 */ GIM_Reject,
     /* 424560 */ // Label 8328: @424560
     /* 424560 */ GIM_Try, /*On fail goto*//*Label 8337*/ GIMT_Encode4(424590), // Rule ID 988 //
     /* 424565 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 424571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424575 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424579 */   // (fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 424579 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
     /* 424584 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424588 */   GIR_RootConstrainSelectedInstOperands,
     /* 424589 */   // GIR_Coverage, 988,
     /* 424589 */   GIR_Done,
     /* 424590 */ // Label 8337: @424590
     /* 424590 */ GIM_Reject,
     /* 424591 */ // Label 8329: @424591
     /* 424591 */ GIM_Reject,
     /* 424592 */ // Label 110: @424592
     /* 424592 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8346*/ GIMT_Encode4(425082),
     /* 424603 */ /*GILLT_s16*//*Label 8338*/ GIMT_Encode4(424643),
     /* 424607 */ /*GILLT_s32*//*Label 8339*/ GIMT_Encode4(424674),
     /* 424611 */ /*GILLT_s64*//*Label 8340*/ GIMT_Encode4(424705), GIMT_Encode4(0),
     /* 424619 */ /*GILLT_v2s32*//*Label 8341*/ GIMT_Encode4(424736),
     /* 424623 */ /*GILLT_v2s64*//*Label 8342*/ GIMT_Encode4(424767),
     /* 424627 */ /*GILLT_v4s16*//*Label 8343*/ GIMT_Encode4(424798),
     /* 424631 */ /*GILLT_v4s32*//*Label 8344*/ GIMT_Encode4(424829), GIMT_Encode4(0),
     /* 424639 */ /*GILLT_v8s16*//*Label 8345*/ GIMT_Encode4(424860),
     /* 424643 */ // Label 8338: @424643
     /* 424643 */ GIM_Try, /*On fail goto*//*Label 8347*/ GIMT_Encode4(424673), // Rule ID 582 //
     /* 424648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 424651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 424654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 424658 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 424662 */   // (ffloor:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTMHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 424662 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMHr),
     /* 424667 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424671 */   GIR_RootConstrainSelectedInstOperands,
     /* 424672 */   // GIR_Coverage, 582,
     /* 424672 */   GIR_Done,
     /* 424673 */ // Label 8347: @424673
     /* 424673 */ GIM_Reject,
     /* 424674 */ // Label 8339: @424674
     /* 424674 */ GIM_Try, /*On fail goto*//*Label 8348*/ GIMT_Encode4(424704), // Rule ID 584 //
     /* 424679 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 424682 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 424685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 424689 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 424693 */   // (ffloor:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTMSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 424693 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMSr),
     /* 424698 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424702 */   GIR_RootConstrainSelectedInstOperands,
     /* 424703 */   // GIR_Coverage, 584,
     /* 424703 */   GIR_Done,
     /* 424704 */ // Label 8348: @424704
     /* 424704 */ GIM_Reject,
     /* 424705 */ // Label 8340: @424705
     /* 424705 */ GIM_Try, /*On fail goto*//*Label 8349*/ GIMT_Encode4(424735), // Rule ID 586 //
     /* 424710 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 424713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 424716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424720 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424724 */   // (ffloor:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTMDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 424724 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMDr),
     /* 424729 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424733 */   GIR_RootConstrainSelectedInstOperands,
     /* 424734 */   // GIR_Coverage, 586,
     /* 424734 */   GIR_Done,
     /* 424735 */ // Label 8349: @424735
     /* 424735 */ GIM_Reject,
     /* 424736 */ // Label 8341: @424736
     /* 424736 */ GIM_Try, /*On fail goto*//*Label 8350*/ GIMT_Encode4(424766), // Rule ID 923 //
     /* 424741 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424744 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 424747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424751 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424755 */   // (ffloor:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTMv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 424755 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f32),
     /* 424760 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424764 */   GIR_RootConstrainSelectedInstOperands,
     /* 424765 */   // GIR_Coverage, 923,
     /* 424765 */   GIR_Done,
     /* 424766 */ // Label 8350: @424766
     /* 424766 */ GIM_Reject,
     /* 424767 */ // Label 8342: @424767
     /* 424767 */ GIM_Try, /*On fail goto*//*Label 8351*/ GIMT_Encode4(424797), // Rule ID 927 //
     /* 424772 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424775 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 424778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424782 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424786 */   // (ffloor:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTMv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 424786 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv2f64),
     /* 424791 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424795 */   GIR_RootConstrainSelectedInstOperands,
     /* 424796 */   // GIR_Coverage, 927,
     /* 424796 */   GIR_Done,
     /* 424797 */ // Label 8351: @424797
     /* 424797 */ GIM_Reject,
     /* 424798 */ // Label 8343: @424798
     /* 424798 */ GIM_Try, /*On fail goto*//*Label 8352*/ GIMT_Encode4(424828), // Rule ID 919 //
     /* 424803 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424806 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 424809 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424813 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424817 */   // (ffloor:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTMv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 424817 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f16),
     /* 424822 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424826 */   GIR_RootConstrainSelectedInstOperands,
     /* 424827 */   // GIR_Coverage, 919,
     /* 424827 */   GIR_Done,
     /* 424828 */ // Label 8352: @424828
     /* 424828 */ GIM_Reject,
     /* 424829 */ // Label 8344: @424829
     /* 424829 */ GIM_Try, /*On fail goto*//*Label 8353*/ GIMT_Encode4(424859), // Rule ID 925 //
     /* 424834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 424837 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 424840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424844 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424848 */   // (ffloor:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTMv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 424848 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 424853 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424857 */   GIR_RootConstrainSelectedInstOperands,
     /* 424858 */   // GIR_Coverage, 925,
     /* 424858 */   GIR_Done,
     /* 424859 */ // Label 8353: @424859
     /* 424859 */ GIM_Reject,
     /* 424860 */ // Label 8345: @424860
     /* 424860 */ GIM_Try, /*On fail goto*//*Label 8354*/ GIMT_Encode4(425081),
     /* 424865 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 424868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424872 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424876 */   GIM_Try, /*On fail goto*//*Label 8355*/ GIMT_Encode4(424895), // Rule ID 921 //
     /* 424881 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 424884 */     // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTMv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 424884 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv8f16),
     /* 424889 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 424893 */     GIR_RootConstrainSelectedInstOperands,
     /* 424894 */     // GIR_Coverage, 921,
     /* 424894 */     GIR_Done,
     /* 424895 */   // Label 8355: @424895
     /* 424895 */   GIM_Try, /*On fail goto*//*Label 8356*/ GIMT_Encode4(425080), // Rule ID 7648 //
     /* 424900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 424903 */     // (ffloor:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTMv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTMv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 424903 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 424906 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 424910 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424915 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 424919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 424921 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 424924 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 424928 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424933 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 424936 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 424938 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 424941 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 424945 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424950 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 424956 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 424961 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 424966 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 424969 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 424973 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424978 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 424981 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 424983 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 424986 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTMv4f32),
     /* 424990 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 424995 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 424998 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 425000 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 425003 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 425007 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425012 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 425015 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 425017 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 425020 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425024 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425029 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425031 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 425034 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425038 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425043 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425046 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 425049 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 425052 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425057 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425062 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 425070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 425072 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 425075 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 425078 */     GIR_RootConstrainSelectedInstOperands,
     /* 425079 */     // GIR_Coverage, 7648,
     /* 425079 */     GIR_EraseRootFromParent_Done,
     /* 425080 */   // Label 8356: @425080
     /* 425080 */   GIM_Reject,
     /* 425081 */ // Label 8354: @425081
     /* 425081 */ GIM_Reject,
     /* 425082 */ // Label 8346: @425082
     /* 425082 */ GIM_Reject,
     /* 425083 */ // Label 111: @425083
     /* 425083 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8365*/ GIMT_Encode4(425573),
     /* 425094 */ /*GILLT_s16*//*Label 8357*/ GIMT_Encode4(425134),
     /* 425098 */ /*GILLT_s32*//*Label 8358*/ GIMT_Encode4(425165),
     /* 425102 */ /*GILLT_s64*//*Label 8359*/ GIMT_Encode4(425196), GIMT_Encode4(0),
     /* 425110 */ /*GILLT_v2s32*//*Label 8360*/ GIMT_Encode4(425227),
     /* 425114 */ /*GILLT_v2s64*//*Label 8361*/ GIMT_Encode4(425258),
     /* 425118 */ /*GILLT_v4s16*//*Label 8362*/ GIMT_Encode4(425289),
     /* 425122 */ /*GILLT_v4s32*//*Label 8363*/ GIMT_Encode4(425320), GIMT_Encode4(0),
     /* 425130 */ /*GILLT_v8s16*//*Label 8364*/ GIMT_Encode4(425351),
     /* 425134 */ // Label 8357: @425134
     /* 425134 */ GIM_Try, /*On fail goto*//*Label 8366*/ GIMT_Encode4(425164), // Rule ID 600 //
     /* 425139 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 425142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 425145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425149 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425153 */   // (frint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTXHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 425153 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXHr),
     /* 425158 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425162 */   GIR_RootConstrainSelectedInstOperands,
     /* 425163 */   // GIR_Coverage, 600,
     /* 425163 */   GIR_Done,
     /* 425164 */ // Label 8366: @425164
     /* 425164 */ GIM_Reject,
     /* 425165 */ // Label 8358: @425165
     /* 425165 */ GIM_Try, /*On fail goto*//*Label 8367*/ GIMT_Encode4(425195), // Rule ID 602 //
     /* 425170 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 425173 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425176 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425180 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425184 */   // (frint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTXSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 425184 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXSr),
     /* 425189 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425193 */   GIR_RootConstrainSelectedInstOperands,
     /* 425194 */   // GIR_Coverage, 602,
     /* 425194 */   GIR_Done,
     /* 425195 */ // Label 8367: @425195
     /* 425195 */ GIM_Reject,
     /* 425196 */ // Label 8359: @425196
     /* 425196 */ GIM_Try, /*On fail goto*//*Label 8368*/ GIMT_Encode4(425226), // Rule ID 604 //
     /* 425201 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 425204 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 425207 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425211 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425215 */   // (frint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTXDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 425215 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXDr),
     /* 425220 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425224 */   GIR_RootConstrainSelectedInstOperands,
     /* 425225 */   // GIR_Coverage, 604,
     /* 425225 */   GIR_Done,
     /* 425226 */ // Label 8368: @425226
     /* 425226 */ GIM_Reject,
     /* 425227 */ // Label 8360: @425227
     /* 425227 */ GIM_Try, /*On fail goto*//*Label 8369*/ GIMT_Encode4(425257), // Rule ID 953 //
     /* 425232 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425235 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 425238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425242 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425246 */   // (frint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTXv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 425246 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f32),
     /* 425251 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425255 */   GIR_RootConstrainSelectedInstOperands,
     /* 425256 */   // GIR_Coverage, 953,
     /* 425256 */   GIR_Done,
     /* 425257 */ // Label 8369: @425257
     /* 425257 */ GIM_Reject,
     /* 425258 */ // Label 8361: @425258
     /* 425258 */ GIM_Try, /*On fail goto*//*Label 8370*/ GIMT_Encode4(425288), // Rule ID 957 //
     /* 425263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425266 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 425269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425273 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425277 */   // (frint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTXv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 425277 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv2f64),
     /* 425282 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425286 */   GIR_RootConstrainSelectedInstOperands,
     /* 425287 */   // GIR_Coverage, 957,
     /* 425287 */   GIR_Done,
     /* 425288 */ // Label 8370: @425288
     /* 425288 */ GIM_Reject,
     /* 425289 */ // Label 8362: @425289
     /* 425289 */ GIM_Try, /*On fail goto*//*Label 8371*/ GIMT_Encode4(425319), // Rule ID 949 //
     /* 425294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 425297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 425300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425308 */   // (frint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTXv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 425308 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f16),
     /* 425313 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425317 */   GIR_RootConstrainSelectedInstOperands,
     /* 425318 */   // GIR_Coverage, 949,
     /* 425318 */   GIR_Done,
     /* 425319 */ // Label 8371: @425319
     /* 425319 */ GIM_Reject,
     /* 425320 */ // Label 8363: @425320
     /* 425320 */ GIM_Try, /*On fail goto*//*Label 8372*/ GIMT_Encode4(425350), // Rule ID 955 //
     /* 425325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 425331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425335 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425339 */   // (frint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTXv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 425339 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 425344 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425348 */   GIR_RootConstrainSelectedInstOperands,
     /* 425349 */   // GIR_Coverage, 955,
     /* 425349 */   GIR_Done,
     /* 425350 */ // Label 8372: @425350
     /* 425350 */ GIM_Reject,
     /* 425351 */ // Label 8364: @425351
     /* 425351 */ GIM_Try, /*On fail goto*//*Label 8373*/ GIMT_Encode4(425572),
     /* 425356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 425359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425363 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425367 */   GIM_Try, /*On fail goto*//*Label 8374*/ GIMT_Encode4(425386), // Rule ID 951 //
     /* 425372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 425375 */     // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTXv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 425375 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv8f16),
     /* 425380 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425384 */     GIR_RootConstrainSelectedInstOperands,
     /* 425385 */     // GIR_Coverage, 951,
     /* 425385 */     GIR_Done,
     /* 425386 */   // Label 8374: @425386
     /* 425386 */   GIM_Try, /*On fail goto*//*Label 8375*/ GIMT_Encode4(425571), // Rule ID 7656 //
     /* 425391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 425394 */     // (frint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTXv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTXv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 425394 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 425397 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 425401 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425406 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 425410 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 425412 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 425415 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 425419 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425424 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 425427 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 425429 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 425432 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 425436 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425441 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 425447 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425452 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425457 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 425460 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 425464 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425469 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 425472 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 425474 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 425477 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTXv4f32),
     /* 425481 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425486 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 425489 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 425491 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 425494 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 425498 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425503 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 425506 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 425508 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 425511 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 425515 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425520 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 425522 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 425525 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 425529 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425534 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 425537 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 425540 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 425543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425548 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425553 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425558 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 425561 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 425563 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 425566 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 425569 */     GIR_RootConstrainSelectedInstOperands,
     /* 425570 */     // GIR_Coverage, 7656,
     /* 425570 */     GIR_EraseRootFromParent_Done,
     /* 425571 */   // Label 8375: @425571
     /* 425571 */   GIM_Reject,
     /* 425572 */ // Label 8373: @425572
     /* 425572 */ GIM_Reject,
     /* 425573 */ // Label 8365: @425573
     /* 425573 */ GIM_Reject,
     /* 425574 */ // Label 112: @425574
     /* 425574 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8384*/ GIMT_Encode4(426064),
     /* 425585 */ /*GILLT_s16*//*Label 8376*/ GIMT_Encode4(425625),
     /* 425589 */ /*GILLT_s32*//*Label 8377*/ GIMT_Encode4(425656),
     /* 425593 */ /*GILLT_s64*//*Label 8378*/ GIMT_Encode4(425687), GIMT_Encode4(0),
     /* 425601 */ /*GILLT_v2s32*//*Label 8379*/ GIMT_Encode4(425718),
     /* 425605 */ /*GILLT_v2s64*//*Label 8380*/ GIMT_Encode4(425749),
     /* 425609 */ /*GILLT_v4s16*//*Label 8381*/ GIMT_Encode4(425780),
     /* 425613 */ /*GILLT_v4s32*//*Label 8382*/ GIMT_Encode4(425811), GIMT_Encode4(0),
     /* 425621 */ /*GILLT_v8s16*//*Label 8383*/ GIMT_Encode4(425842),
     /* 425625 */ // Label 8376: @425625
     /* 425625 */ GIM_Try, /*On fail goto*//*Label 8385*/ GIMT_Encode4(425655), // Rule ID 576 //
     /* 425630 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 425633 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 425636 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425640 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 425644 */   // (fnearbyint:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FRINTIHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 425644 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIHr),
     /* 425649 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425653 */   GIR_RootConstrainSelectedInstOperands,
     /* 425654 */   // GIR_Coverage, 576,
     /* 425654 */   GIR_Done,
     /* 425655 */ // Label 8385: @425655
     /* 425655 */ GIM_Reject,
     /* 425656 */ // Label 8377: @425656
     /* 425656 */ GIM_Try, /*On fail goto*//*Label 8386*/ GIMT_Encode4(425686), // Rule ID 578 //
     /* 425661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 425664 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 425667 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425671 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 425675 */   // (fnearbyint:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FRINTISr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 425675 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTISr),
     /* 425680 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425684 */   GIR_RootConstrainSelectedInstOperands,
     /* 425685 */   // GIR_Coverage, 578,
     /* 425685 */   GIR_Done,
     /* 425686 */ // Label 8386: @425686
     /* 425686 */ GIM_Reject,
     /* 425687 */ // Label 8378: @425687
     /* 425687 */ GIM_Try, /*On fail goto*//*Label 8387*/ GIMT_Encode4(425717), // Rule ID 580 //
     /* 425692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 425695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 425698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425702 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425706 */   // (fnearbyint:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FRINTIDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 425706 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIDr),
     /* 425711 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425715 */   GIR_RootConstrainSelectedInstOperands,
     /* 425716 */   // GIR_Coverage, 580,
     /* 425716 */   GIR_Done,
     /* 425717 */ // Label 8387: @425717
     /* 425717 */ GIM_Reject,
     /* 425718 */ // Label 8379: @425718
     /* 425718 */ GIM_Try, /*On fail goto*//*Label 8388*/ GIMT_Encode4(425748), // Rule ID 913 //
     /* 425723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 425729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425733 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425737 */   // (fnearbyint:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FRINTIv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 425737 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f32),
     /* 425742 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425746 */   GIR_RootConstrainSelectedInstOperands,
     /* 425747 */   // GIR_Coverage, 913,
     /* 425747 */   GIR_Done,
     /* 425748 */ // Label 8388: @425748
     /* 425748 */ GIM_Reject,
     /* 425749 */ // Label 8380: @425749
     /* 425749 */ GIM_Try, /*On fail goto*//*Label 8389*/ GIMT_Encode4(425779), // Rule ID 917 //
     /* 425754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425757 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 425760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425764 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425768 */   // (fnearbyint:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FRINTIv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 425768 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv2f64),
     /* 425773 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425777 */   GIR_RootConstrainSelectedInstOperands,
     /* 425778 */   // GIR_Coverage, 917,
     /* 425778 */   GIR_Done,
     /* 425779 */ // Label 8389: @425779
     /* 425779 */ GIM_Reject,
     /* 425780 */ // Label 8381: @425780
     /* 425780 */ GIM_Try, /*On fail goto*//*Label 8390*/ GIMT_Encode4(425810), // Rule ID 909 //
     /* 425785 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 425788 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 425791 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425795 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425799 */   // (fnearbyint:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FRINTIv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 425799 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f16),
     /* 425804 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425808 */   GIR_RootConstrainSelectedInstOperands,
     /* 425809 */   // GIR_Coverage, 909,
     /* 425809 */   GIR_Done,
     /* 425810 */ // Label 8390: @425810
     /* 425810 */ GIM_Reject,
     /* 425811 */ // Label 8382: @425811
     /* 425811 */ GIM_Try, /*On fail goto*//*Label 8391*/ GIMT_Encode4(425841), // Rule ID 915 //
     /* 425816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 425819 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 425822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425830 */   // (fnearbyint:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FRINTIv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 425830 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 425835 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425839 */   GIR_RootConstrainSelectedInstOperands,
     /* 425840 */   // GIR_Coverage, 915,
     /* 425840 */   GIR_Done,
     /* 425841 */ // Label 8391: @425841
     /* 425841 */ GIM_Reject,
     /* 425842 */ // Label 8383: @425842
     /* 425842 */ GIM_Try, /*On fail goto*//*Label 8392*/ GIMT_Encode4(426063),
     /* 425847 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 425850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425854 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425858 */   GIM_Try, /*On fail goto*//*Label 8393*/ GIMT_Encode4(425877), // Rule ID 911 //
     /* 425863 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 425866 */     // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FRINTIv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 425866 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv8f16),
     /* 425871 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 425875 */     GIR_RootConstrainSelectedInstOperands,
     /* 425876 */     // GIR_Coverage, 911,
     /* 425876 */     GIR_Done,
     /* 425877 */   // Label 8393: @425877
     /* 425877 */   GIM_Try, /*On fail goto*//*Label 8394*/ GIMT_Encode4(426062), // Rule ID 7650 //
     /* 425882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 425885 */     // (fnearbyint:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FRINTIv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FRINTIv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn)))
     /* 425885 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s32,
     /* 425888 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 425892 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425897 */     GIR_Copy, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 425901 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
     /* 425903 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 425906 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 425910 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425915 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 425918 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 425920 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 425923 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 425927 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425932 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 425938 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 425943 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 425948 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 425951 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 425955 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425960 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 425963 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 425965 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 425968 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FRINTIv4f32),
     /* 425972 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425977 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 425980 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 425982 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 425985 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 425989 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 425994 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 425997 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 425999 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 426002 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 426006 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426011 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 426013 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 426016 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 426020 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426025 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 426028 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 426031 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 426034 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426039 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426044 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 426052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 426054 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426057 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
     /* 426060 */     GIR_RootConstrainSelectedInstOperands,
     /* 426061 */     // GIR_Coverage, 7650,
     /* 426061 */     GIR_EraseRootFromParent_Done,
     /* 426062 */   // Label 8394: @426062
     /* 426062 */   GIM_Reject,
     /* 426063 */ // Label 8392: @426063
     /* 426063 */ GIM_Reject,
     /* 426064 */ // Label 8384: @426064
     /* 426064 */ GIM_Reject,
     /* 426065 */ // Label 113: @426065
     /* 426065 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8403*/ GIMT_Encode4(427190),
     /* 426076 */ /*GILLT_s16*//*Label 8395*/ GIMT_Encode4(426116),
     /* 426080 */ /*GILLT_s32*//*Label 8396*/ GIMT_Encode4(426342),
     /* 426084 */ /*GILLT_s64*//*Label 8397*/ GIMT_Encode4(426568), GIMT_Encode4(0),
     /* 426092 */ /*GILLT_v2s32*//*Label 8398*/ GIMT_Encode4(426740),
     /* 426096 */ /*GILLT_v2s64*//*Label 8399*/ GIMT_Encode4(426778),
     /* 426100 */ /*GILLT_v4s16*//*Label 8400*/ GIMT_Encode4(426816),
     /* 426104 */ /*GILLT_v4s32*//*Label 8401*/ GIMT_Encode4(426854), GIMT_Encode4(0),
     /* 426112 */ /*GILLT_v8s16*//*Label 8402*/ GIMT_Encode4(426892),
     /* 426116 */ // Label 8395: @426116
     /* 426116 */ GIM_Try, /*On fail goto*//*Label 8404*/ GIMT_Encode4(426341),
     /* 426121 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 426124 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 426127 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 426131 */   GIM_Try, /*On fail goto*//*Label 8405*/ GIMT_Encode4(426222), // Rule ID 7563 //
     /* 426136 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426140 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426144 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 426148 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426152 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426157 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 426161 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426165 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426169 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426173 */     // MIs[2] Rn
     /* 426173 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426178 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 426182 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426184 */     // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 426184 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 426187 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 426191 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426196 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 426202 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426207 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 426215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426217 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426220 */     GIR_RootConstrainSelectedInstOperands,
     /* 426221 */     // GIR_Coverage, 7563,
     /* 426221 */     GIR_EraseRootFromParent_Done,
     /* 426222 */   // Label 8405: @426222
     /* 426222 */   GIM_Try, /*On fail goto*//*Label 8406*/ GIMT_Encode4(426313), // Rule ID 15000 //
     /* 426227 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426231 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426235 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 426239 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426243 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426248 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 426252 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426256 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426260 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426264 */     // MIs[2] Rn
     /* 426264 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426269 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 426273 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426275 */     // (strict_fadd:{ *:[f16] } (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f16] } FPR128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] }))
     /* 426275 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 426278 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 426282 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426287 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 426293 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426298 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426303 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 426306 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426308 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426311 */     GIR_RootConstrainSelectedInstOperands,
     /* 426312 */     // GIR_Coverage, 15000,
     /* 426312 */     GIR_EraseRootFromParent_Done,
     /* 426313 */   // Label 8406: @426313
     /* 426313 */   GIM_Try, /*On fail goto*//*Label 8407*/ GIMT_Encode4(426340), // Rule ID 625 //
     /* 426318 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 426321 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 426325 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 426329 */     // (strict_fadd:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FADDHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 426329 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDHrr),
     /* 426334 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426338 */     GIR_RootConstrainSelectedInstOperands,
     /* 426339 */     // GIR_Coverage, 625,
     /* 426339 */     GIR_Done,
     /* 426340 */   // Label 8407: @426340
     /* 426340 */   GIM_Reject,
     /* 426341 */ // Label 8404: @426341
     /* 426341 */ GIM_Reject,
     /* 426342 */ // Label 8396: @426342
     /* 426342 */ GIM_Try, /*On fail goto*//*Label 8408*/ GIMT_Encode4(426567),
     /* 426347 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 426350 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 426353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 426357 */   GIM_Try, /*On fail goto*//*Label 8409*/ GIMT_Encode4(426448), // Rule ID 7561 //
     /* 426362 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426366 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426370 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 426374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426383 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 426387 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426391 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426395 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426399 */     // MIs[2] Rn
     /* 426399 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426404 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 426408 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426410 */     // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 426410 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 426413 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 426417 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426422 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 426428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426433 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 426441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426443 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426446 */     GIR_RootConstrainSelectedInstOperands,
     /* 426447 */     // GIR_Coverage, 7561,
     /* 426447 */     GIR_EraseRootFromParent_Done,
     /* 426448 */   // Label 8409: @426448
     /* 426448 */   GIM_Try, /*On fail goto*//*Label 8410*/ GIMT_Encode4(426539), // Rule ID 14998 //
     /* 426453 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426457 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426461 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 426465 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426469 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426474 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 426478 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426482 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426486 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426490 */     // MIs[2] Rn
     /* 426490 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426495 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 426499 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426501 */     // (strict_fadd:{ *:[f32] } (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f32] } FPR128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } FPR128:{ *:[v4f32] }:$Rn, dsub:{ *:[i32] }))
     /* 426501 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 426504 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 426508 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426513 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 426519 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426524 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426529 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 426532 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426534 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 426537 */     GIR_RootConstrainSelectedInstOperands,
     /* 426538 */     // GIR_Coverage, 14998,
     /* 426538 */     GIR_EraseRootFromParent_Done,
     /* 426539 */   // Label 8410: @426539
     /* 426539 */   GIM_Try, /*On fail goto*//*Label 8411*/ GIMT_Encode4(426566), // Rule ID 627 //
     /* 426544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 426547 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 426551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 426555 */     // (strict_fadd:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FADDSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 426555 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDSrr),
     /* 426560 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426564 */     GIR_RootConstrainSelectedInstOperands,
     /* 426565 */     // GIR_Coverage, 627,
     /* 426565 */     GIR_Done,
     /* 426566 */   // Label 8411: @426566
     /* 426566 */   GIM_Reject,
     /* 426567 */ // Label 8408: @426567
     /* 426567 */ GIM_Reject,
     /* 426568 */ // Label 8397: @426568
     /* 426568 */ GIM_Try, /*On fail goto*//*Label 8412*/ GIMT_Encode4(426739),
     /* 426573 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 426576 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 426579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426583 */   GIM_Try, /*On fail goto*//*Label 8413*/ GIMT_Encode4(426647), // Rule ID 7559 //
     /* 426588 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426592 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426596 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 426600 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426604 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426609 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 426613 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426617 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426621 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426625 */     // MIs[2] Rn
     /* 426625 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426630 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 1,
     /* 426634 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426636 */     // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 426636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 426639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426641 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426645 */     GIR_RootConstrainSelectedInstOperands,
     /* 426646 */     // GIR_Coverage, 7559,
     /* 426646 */     GIR_EraseRootFromParent_Done,
     /* 426647 */   // Label 8413: @426647
     /* 426647 */   GIM_Try, /*On fail goto*//*Label 8414*/ GIMT_Encode4(426711), // Rule ID 14996 //
     /* 426652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 426656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 426664 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 426668 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426673 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
     /* 426677 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 426681 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 426685 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 426689 */     // MIs[2] Rn
     /* 426689 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 426694 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 426698 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 426700 */     // (strict_fadd:{ *:[f64] } (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (vector_extract:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FADDPv2i64p:{ *:[f64] } FPR128:{ *:[v2f64] }:$Rn)
     /* 426700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 426703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 426705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 426709 */     GIR_RootConstrainSelectedInstOperands,
     /* 426710 */     // GIR_Coverage, 14996,
     /* 426710 */     GIR_EraseRootFromParent_Done,
     /* 426711 */   // Label 8414: @426711
     /* 426711 */   GIM_Try, /*On fail goto*//*Label 8415*/ GIMT_Encode4(426738), // Rule ID 629 //
     /* 426716 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 426719 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426727 */     // (strict_fadd:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FADDDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 426727 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDDrr),
     /* 426732 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426736 */     GIR_RootConstrainSelectedInstOperands,
     /* 426737 */     // GIR_Coverage, 629,
     /* 426737 */     GIR_Done,
     /* 426738 */   // Label 8415: @426738
     /* 426738 */   GIM_Reject,
     /* 426739 */ // Label 8412: @426739
     /* 426739 */ GIM_Reject,
     /* 426740 */ // Label 8398: @426740
     /* 426740 */ GIM_Try, /*On fail goto*//*Label 8416*/ GIMT_Encode4(426777), // Rule ID 1232 //
     /* 426745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426748 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 426751 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 426754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426758 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426762 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426766 */   // (strict_fadd:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FADDv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 426766 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f32),
     /* 426771 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426775 */   GIR_RootConstrainSelectedInstOperands,
     /* 426776 */   // GIR_Coverage, 1232,
     /* 426776 */   GIR_Done,
     /* 426777 */ // Label 8416: @426777
     /* 426777 */ GIM_Reject,
     /* 426778 */ // Label 8399: @426778
     /* 426778 */ GIM_Try, /*On fail goto*//*Label 8417*/ GIMT_Encode4(426815), // Rule ID 1236 //
     /* 426783 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 426789 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 426792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426796 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426800 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426804 */   // (strict_fadd:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FADDv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 426804 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv2f64),
     /* 426809 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426813 */   GIR_RootConstrainSelectedInstOperands,
     /* 426814 */   // GIR_Coverage, 1236,
     /* 426814 */   GIR_Done,
     /* 426815 */ // Label 8417: @426815
     /* 426815 */ GIM_Reject,
     /* 426816 */ // Label 8400: @426816
     /* 426816 */ GIM_Try, /*On fail goto*//*Label 8418*/ GIMT_Encode4(426853), // Rule ID 1228 //
     /* 426821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 426824 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 426827 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 426830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426834 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426838 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 426842 */   // (strict_fadd:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FADDv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 426842 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f16),
     /* 426847 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426851 */   GIR_RootConstrainSelectedInstOperands,
     /* 426852 */   // GIR_Coverage, 1228,
     /* 426852 */   GIR_Done,
     /* 426853 */ // Label 8418: @426853
     /* 426853 */ GIM_Reject,
     /* 426854 */ // Label 8401: @426854
     /* 426854 */ GIM_Try, /*On fail goto*//*Label 8419*/ GIMT_Encode4(426891), // Rule ID 1234 //
     /* 426859 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 426862 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 426865 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 426868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426872 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426876 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426880 */   // (strict_fadd:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FADDv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 426880 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 426885 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426889 */   GIR_RootConstrainSelectedInstOperands,
     /* 426890 */   // GIR_Coverage, 1234,
     /* 426890 */   GIR_Done,
     /* 426891 */ // Label 8419: @426891
     /* 426891 */ GIM_Reject,
     /* 426892 */ // Label 8402: @426892
     /* 426892 */ GIM_Try, /*On fail goto*//*Label 8420*/ GIMT_Encode4(427189),
     /* 426897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 426900 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 426903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426907 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426911 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 426915 */   GIM_Try, /*On fail goto*//*Label 8421*/ GIMT_Encode4(426934), // Rule ID 1230 //
     /* 426920 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 426923 */     // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FADDv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 426923 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDv8f16),
     /* 426928 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 426932 */     GIR_RootConstrainSelectedInstOperands,
     /* 426933 */     // GIR_Coverage, 1230,
     /* 426933 */     GIR_Done,
     /* 426934 */   // Label 8421: @426934
     /* 426934 */   GIM_Try, /*On fail goto*//*Label 8422*/ GIMT_Encode4(427188), // Rule ID 7659 //
     /* 426939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 426942 */     // (strict_fadd:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FADDv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FADDv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 426942 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 426945 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 426949 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426954 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 426958 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 426960 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 426963 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 426967 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426972 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 426976 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 426978 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 426981 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 426985 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 426990 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 426993 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 426996 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 426998 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 427001 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427005 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427010 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 427016 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427021 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427026 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 427029 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 427033 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427038 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 427041 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 427043 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 427046 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427050 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427055 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 427061 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427066 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427071 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 427074 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 427078 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427083 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 427086 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 427088 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 427091 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FADDv4f32),
     /* 427095 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427100 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 427103 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 427106 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 427108 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 427111 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 427115 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427120 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 427123 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 427125 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 427128 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 427132 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427137 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 427139 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 427142 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 427146 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427151 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 427154 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 427157 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 427160 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427165 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427170 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 427178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 427180 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 427183 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 427186 */     GIR_RootConstrainSelectedInstOperands,
     /* 427187 */     // GIR_Coverage, 7659,
     /* 427187 */     GIR_EraseRootFromParent_Done,
     /* 427188 */   // Label 8422: @427188
     /* 427188 */   GIM_Reject,
     /* 427189 */ // Label 8420: @427189
     /* 427189 */ GIM_Reject,
     /* 427190 */ // Label 8403: @427190
     /* 427190 */ GIM_Reject,
     /* 427191 */ // Label 114: @427191
     /* 427191 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8431*/ GIMT_Encode4(427806),
     /* 427202 */ /*GILLT_s16*//*Label 8423*/ GIMT_Encode4(427242),
     /* 427206 */ /*GILLT_s32*//*Label 8424*/ GIMT_Encode4(427280),
     /* 427210 */ /*GILLT_s64*//*Label 8425*/ GIMT_Encode4(427318), GIMT_Encode4(0),
     /* 427218 */ /*GILLT_v2s32*//*Label 8426*/ GIMT_Encode4(427356),
     /* 427222 */ /*GILLT_v2s64*//*Label 8427*/ GIMT_Encode4(427394),
     /* 427226 */ /*GILLT_v4s16*//*Label 8428*/ GIMT_Encode4(427432),
     /* 427230 */ /*GILLT_v4s32*//*Label 8429*/ GIMT_Encode4(427470), GIMT_Encode4(0),
     /* 427238 */ /*GILLT_v8s16*//*Label 8430*/ GIMT_Encode4(427508),
     /* 427242 */ // Label 8423: @427242
     /* 427242 */ GIM_Try, /*On fail goto*//*Label 8432*/ GIMT_Encode4(427279), // Rule ID 673 //
     /* 427247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 427250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 427253 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 427256 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 427260 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 427264 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 427268 */   // (strict_fsub:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FSUBHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 427268 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBHrr),
     /* 427273 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427277 */   GIR_RootConstrainSelectedInstOperands,
     /* 427278 */   // GIR_Coverage, 673,
     /* 427278 */   GIR_Done,
     /* 427279 */ // Label 8432: @427279
     /* 427279 */ GIM_Reject,
     /* 427280 */ // Label 8424: @427280
     /* 427280 */ GIM_Try, /*On fail goto*//*Label 8433*/ GIMT_Encode4(427317), // Rule ID 675 //
     /* 427285 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 427288 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 427291 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 427294 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 427298 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 427302 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 427306 */   // (strict_fsub:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FSUBSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 427306 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBSrr),
     /* 427311 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427315 */   GIR_RootConstrainSelectedInstOperands,
     /* 427316 */   // GIR_Coverage, 675,
     /* 427316 */   GIR_Done,
     /* 427317 */ // Label 8433: @427317
     /* 427317 */ GIM_Reject,
     /* 427318 */ // Label 8425: @427318
     /* 427318 */ GIM_Try, /*On fail goto*//*Label 8434*/ GIMT_Encode4(427355), // Rule ID 677 //
     /* 427323 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 427326 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 427329 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 427332 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427336 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427340 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427344 */   // (strict_fsub:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FSUBDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 427344 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBDrr),
     /* 427349 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427353 */   GIR_RootConstrainSelectedInstOperands,
     /* 427354 */   // GIR_Coverage, 677,
     /* 427354 */   GIR_Done,
     /* 427355 */ // Label 8434: @427355
     /* 427355 */ GIM_Reject,
     /* 427356 */ // Label 8426: @427356
     /* 427356 */ GIM_Try, /*On fail goto*//*Label 8435*/ GIMT_Encode4(427393), // Rule ID 1372 //
     /* 427361 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427364 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 427367 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 427370 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427374 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427378 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427382 */   // (strict_fsub:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FSUBv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 427382 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f32),
     /* 427387 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427391 */   GIR_RootConstrainSelectedInstOperands,
     /* 427392 */   // GIR_Coverage, 1372,
     /* 427392 */   GIR_Done,
     /* 427393 */ // Label 8435: @427393
     /* 427393 */ GIM_Reject,
     /* 427394 */ // Label 8427: @427394
     /* 427394 */ GIM_Try, /*On fail goto*//*Label 8436*/ GIMT_Encode4(427431), // Rule ID 1376 //
     /* 427399 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427402 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 427405 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 427408 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427412 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427416 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427420 */   // (strict_fsub:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FSUBv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 427420 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv2f64),
     /* 427425 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427429 */   GIR_RootConstrainSelectedInstOperands,
     /* 427430 */   // GIR_Coverage, 1376,
     /* 427430 */   GIR_Done,
     /* 427431 */ // Label 8436: @427431
     /* 427431 */ GIM_Reject,
     /* 427432 */ // Label 8428: @427432
     /* 427432 */ GIM_Try, /*On fail goto*//*Label 8437*/ GIMT_Encode4(427469), // Rule ID 1368 //
     /* 427437 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 427440 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 427443 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 427446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427450 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427454 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427458 */   // (strict_fsub:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FSUBv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 427458 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f16),
     /* 427463 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427467 */   GIR_RootConstrainSelectedInstOperands,
     /* 427468 */   // GIR_Coverage, 1368,
     /* 427468 */   GIR_Done,
     /* 427469 */ // Label 8437: @427469
     /* 427469 */ GIM_Reject,
     /* 427470 */ // Label 8429: @427470
     /* 427470 */ GIM_Try, /*On fail goto*//*Label 8438*/ GIMT_Encode4(427507), // Rule ID 1374 //
     /* 427475 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 427478 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 427481 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 427484 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427488 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427492 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427496 */   // (strict_fsub:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FSUBv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 427496 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 427501 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427505 */   GIR_RootConstrainSelectedInstOperands,
     /* 427506 */   // GIR_Coverage, 1374,
     /* 427506 */   GIR_Done,
     /* 427507 */ // Label 8438: @427507
     /* 427507 */ GIM_Reject,
     /* 427508 */ // Label 8430: @427508
     /* 427508 */ GIM_Try, /*On fail goto*//*Label 8439*/ GIMT_Encode4(427805),
     /* 427513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 427516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 427519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427523 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427527 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427531 */   GIM_Try, /*On fail goto*//*Label 8440*/ GIMT_Encode4(427550), // Rule ID 1370 //
     /* 427536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 427539 */     // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FSUBv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 427539 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSUBv8f16),
     /* 427544 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 427548 */     GIR_RootConstrainSelectedInstOperands,
     /* 427549 */     // GIR_Coverage, 1370,
     /* 427549 */     GIR_Done,
     /* 427550 */   // Label 8440: @427550
     /* 427550 */   GIM_Try, /*On fail goto*//*Label 8441*/ GIMT_Encode4(427804), // Rule ID 7665 //
     /* 427555 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 427558 */     // (strict_fsub:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FSUBv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FSUBv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 427558 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 427561 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 427565 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427570 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 427574 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 427576 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 427579 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 427583 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427588 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 427592 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 427594 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 427597 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 427601 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427606 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 427609 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 427612 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 427614 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 427617 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427621 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427626 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 427632 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427637 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427642 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 427645 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 427649 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427654 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 427657 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 427659 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 427662 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427666 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427671 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 427677 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427682 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427687 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 427690 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 427694 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427699 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 427702 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 427704 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 427707 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FSUBv4f32),
     /* 427711 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427716 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 427719 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 427722 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 427724 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 427727 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 427731 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427736 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 427739 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 427741 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 427744 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 427748 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427753 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 427755 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 427758 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 427762 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427767 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 427770 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 427773 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 427776 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427781 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427786 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 427791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 427794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 427796 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 427799 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 427802 */     GIR_RootConstrainSelectedInstOperands,
     /* 427803 */     // GIR_Coverage, 7665,
     /* 427803 */     GIR_EraseRootFromParent_Done,
     /* 427804 */   // Label 8441: @427804
     /* 427804 */   GIM_Reject,
     /* 427805 */ // Label 8439: @427805
     /* 427805 */ GIM_Reject,
     /* 427806 */ // Label 8431: @427806
     /* 427806 */ GIM_Reject,
     /* 427807 */ // Label 115: @427807
     /* 427807 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8450*/ GIMT_Encode4(431528),
     /* 427818 */ /*GILLT_s16*//*Label 8442*/ GIMT_Encode4(427858),
     /* 427822 */ /*GILLT_s32*//*Label 8443*/ GIMT_Encode4(428412),
     /* 427826 */ /*GILLT_s64*//*Label 8444*/ GIMT_Encode4(428960), GIMT_Encode4(0),
     /* 427834 */ /*GILLT_v2s32*//*Label 8445*/ GIMT_Encode4(429508),
     /* 427838 */ /*GILLT_v2s64*//*Label 8446*/ GIMT_Encode4(430038),
     /* 427842 */ /*GILLT_v4s16*//*Label 8447*/ GIMT_Encode4(430396),
     /* 427846 */ /*GILLT_v4s32*//*Label 8448*/ GIMT_Encode4(430738), GIMT_Encode4(0),
     /* 427854 */ /*GILLT_v8s16*//*Label 8449*/ GIMT_Encode4(431096),
     /* 427858 */ // Label 8442: @427858
     /* 427858 */ GIM_Try, /*On fail goto*//*Label 8451*/ GIMT_Encode4(428411),
     /* 427863 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 427866 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 427869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 427873 */   GIM_Try, /*On fail goto*//*Label 8452*/ GIMT_Encode4(427986), // Rule ID 6874 //
     /* 427878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 427881 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427885 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 427889 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 427893 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 427897 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427902 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 427906 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 427910 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 427914 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 427918 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 427922 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427927 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 427931 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 427935 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 427939 */     // MIs[3] Operand 1
     /* 427939 */     // No operand predicates
     /* 427939 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 427941 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 427941 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 427944 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 427948 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 427953 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 427959 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 427964 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 427969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 427972 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 427974 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 427977 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 427981 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 427984 */     GIR_RootConstrainSelectedInstOperands,
     /* 427985 */     // GIR_Coverage, 6874,
     /* 427985 */     GIR_EraseRootFromParent_Done,
     /* 427986 */   // Label 8452: @427986
     /* 427986 */   GIM_Try, /*On fail goto*//*Label 8453*/ GIMT_Encode4(428099), // Rule ID 14977 //
     /* 427991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 427994 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 427998 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428002 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428006 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428010 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428015 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428019 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428023 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 428027 */     // MIs[2] Operand 1
     /* 428027 */     // No operand predicates
     /* 428027 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 428031 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428035 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428039 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 428043 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428048 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 428052 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428054 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i16_indexed:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 428054 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 428057 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428061 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428066 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 428072 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428077 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428082 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 428085 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428087 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428090 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428094 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428097 */     GIR_RootConstrainSelectedInstOperands,
     /* 428098 */     // GIR_Coverage, 14977,
     /* 428098 */     GIR_EraseRootFromParent_Done,
     /* 428099 */   // Label 8453: @428099
     /* 428099 */   GIM_Try, /*On fail goto*//*Label 8454*/ GIMT_Encode4(428178), // Rule ID 14866 //
     /* 428104 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 428107 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428111 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428115 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428119 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428123 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428128 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 428132 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428136 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428138 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rn)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 428138 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 428141 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428145 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428150 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 428156 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428161 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 428169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428171 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 428173 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428176 */     GIR_RootConstrainSelectedInstOperands,
     /* 428177 */     // GIR_Coverage, 14866,
     /* 428177 */     GIR_EraseRootFromParent_Done,
     /* 428178 */   // Label 8454: @428178
     /* 428178 */   GIM_Try, /*On fail goto*//*Label 8455*/ GIMT_Encode4(428257), // Rule ID 4879 //
     /* 428183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 428186 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 428194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428198 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428202 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428206 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428211 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 428215 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428217 */     // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }))  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }))
     /* 428217 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 428220 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428224 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428229 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 428235 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428240 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428245 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 428248 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428250 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428252 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428255 */     GIR_RootConstrainSelectedInstOperands,
     /* 428256 */     // GIR_Coverage, 4879,
     /* 428256 */     GIR_EraseRootFromParent_Done,
     /* 428257 */   // Label 8455: @428257
     /* 428257 */   GIM_Try, /*On fail goto*//*Label 8456*/ GIMT_Encode4(428320), // Rule ID 14501 //
     /* 428262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 428265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428277 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428281 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 428286 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428290 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428294 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 428298 */     // MIs[2] Operand 1
     /* 428298 */     // No operand predicates
     /* 428298 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428302 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 428304 */     // (strict_fmul:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16Op:{ *:[f16] }:$Rn)  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 428304 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 428307 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428309 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 428311 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428315 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428318 */     GIR_RootConstrainSelectedInstOperands,
     /* 428319 */     // GIR_Coverage, 14501,
     /* 428319 */     GIR_EraseRootFromParent_Done,
     /* 428320 */   // Label 8456: @428320
     /* 428320 */   GIM_Try, /*On fail goto*//*Label 8457*/ GIMT_Encode4(428383), // Rule ID 2042 //
     /* 428325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 428328 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 428336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 428344 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428348 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 428353 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428357 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428361 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 428365 */     // MIs[2] Operand 1
     /* 428365 */     // No operand predicates
     /* 428365 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 428367 */     // (strict_fmul:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv1i16_indexed:{ *:[f16] } FPR16Op:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 428367 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i16_indexed),
     /* 428370 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428372 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428374 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428378 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428381 */     GIR_RootConstrainSelectedInstOperands,
     /* 428382 */     // GIR_Coverage, 2042,
     /* 428382 */     GIR_EraseRootFromParent_Done,
     /* 428383 */   // Label 8457: @428383
     /* 428383 */   GIM_Try, /*On fail goto*//*Label 8458*/ GIMT_Encode4(428410), // Rule ID 661 //
     /* 428388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 428391 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428395 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 428399 */     // (strict_fmul:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FMULHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 428399 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULHrr),
     /* 428404 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 428408 */     GIR_RootConstrainSelectedInstOperands,
     /* 428409 */     // GIR_Coverage, 661,
     /* 428409 */     GIR_Done,
     /* 428410 */   // Label 8458: @428410
     /* 428410 */   GIM_Reject,
     /* 428411 */ // Label 8451: @428411
     /* 428411 */ GIM_Reject,
     /* 428412 */ // Label 8443: @428412
     /* 428412 */ GIM_Try, /*On fail goto*//*Label 8459*/ GIMT_Encode4(428959),
     /* 428417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 428420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 428423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428427 */   GIM_Try, /*On fail goto*//*Label 8460*/ GIMT_Encode4(428540), // Rule ID 6876 //
     /* 428432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428435 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428439 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428443 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428447 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428451 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428456 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 428460 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 428464 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428468 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428472 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 428476 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428481 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 428485 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428489 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 428493 */     // MIs[3] Operand 1
     /* 428493 */     // No operand predicates
     /* 428493 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428495 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 428495 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 428498 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428502 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428507 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 428513 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428518 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428523 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 428526 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428528 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 428535 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 428538 */     GIR_RootConstrainSelectedInstOperands,
     /* 428539 */     // GIR_Coverage, 6876,
     /* 428539 */     GIR_EraseRootFromParent_Done,
     /* 428540 */   // Label 8460: @428540
     /* 428540 */   GIM_Try, /*On fail goto*//*Label 8461*/ GIMT_Encode4(428653), // Rule ID 14979 //
     /* 428545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428548 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428552 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428556 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428560 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428564 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428569 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428573 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428577 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 428581 */     // MIs[2] Operand 1
     /* 428581 */     // No operand predicates
     /* 428581 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 428585 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428589 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428593 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 428597 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428602 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 428606 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 428608 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i32_indexed:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 428608 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 428611 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428615 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428620 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 428626 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428631 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 428639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428641 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428648 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428651 */     GIR_RootConstrainSelectedInstOperands,
     /* 428652 */     // GIR_Coverage, 14979,
     /* 428652 */     GIR_EraseRootFromParent_Done,
     /* 428653 */   // Label 8461: @428653
     /* 428653 */   GIM_Try, /*On fail goto*//*Label 8462*/ GIMT_Encode4(428729), // Rule ID 14868 //
     /* 428658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428670 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428674 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428679 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 428683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428687 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428689 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rn)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 428689 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 428692 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428696 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428701 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 428707 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428712 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 428720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428722 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 428724 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428727 */     GIR_RootConstrainSelectedInstOperands,
     /* 428728 */     // GIR_Coverage, 14868,
     /* 428728 */     GIR_EraseRootFromParent_Done,
     /* 428729 */   // Label 8462: @428729
     /* 428729 */   GIM_Try, /*On fail goto*//*Label 8463*/ GIMT_Encode4(428805), // Rule ID 4881 //
     /* 428734 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 428742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428750 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428754 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428759 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 428763 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 428765 */     // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }))  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }))
     /* 428765 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 428768 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 428772 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 428777 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 428783 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428788 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 428796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428798 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428800 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 428803 */     GIR_RootConstrainSelectedInstOperands,
     /* 428804 */     // GIR_Coverage, 4881,
     /* 428804 */     GIR_EraseRootFromParent_Done,
     /* 428805 */   // Label 8463: @428805
     /* 428805 */   GIM_Try, /*On fail goto*//*Label 8464*/ GIMT_Encode4(428868), // Rule ID 14503 //
     /* 428810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428813 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428817 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428821 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428825 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428829 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428834 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428838 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428842 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 428846 */     // MIs[2] Operand 1
     /* 428846 */     // No operand predicates
     /* 428846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428850 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 428852 */     // (strict_fmul:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32Op:{ *:[f32] }:$Rn)  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 428852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 428855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428857 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 428859 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428863 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428866 */     GIR_RootConstrainSelectedInstOperands,
     /* 428867 */     // GIR_Coverage, 14503,
     /* 428867 */     GIR_EraseRootFromParent_Done,
     /* 428868 */   // Label 8464: @428868
     /* 428868 */   GIM_Try, /*On fail goto*//*Label 8465*/ GIMT_Encode4(428931), // Rule ID 2044 //
     /* 428873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428876 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 428884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428888 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 428892 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428896 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 428901 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 428905 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 428909 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 428913 */     // MIs[2] Operand 1
     /* 428913 */     // No operand predicates
     /* 428913 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 428915 */     // (strict_fmul:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv1i32_indexed:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 428915 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i32_indexed),
     /* 428918 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 428920 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 428922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 428926 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 428929 */     GIR_RootConstrainSelectedInstOperands,
     /* 428930 */     // GIR_Coverage, 2044,
     /* 428930 */     GIR_EraseRootFromParent_Done,
     /* 428931 */   // Label 8465: @428931
     /* 428931 */   GIM_Try, /*On fail goto*//*Label 8466*/ GIMT_Encode4(428958), // Rule ID 663 //
     /* 428936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 428939 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428943 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 428947 */     // (strict_fmul:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FMULSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 428947 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULSrr),
     /* 428952 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 428956 */     GIR_RootConstrainSelectedInstOperands,
     /* 428957 */     // GIR_Coverage, 663,
     /* 428957 */     GIR_Done,
     /* 428958 */   // Label 8466: @428958
     /* 428958 */   GIM_Reject,
     /* 428959 */ // Label 8459: @428959
     /* 428959 */ GIM_Reject,
     /* 428960 */ // Label 8444: @428960
     /* 428960 */ GIM_Try, /*On fail goto*//*Label 8467*/ GIMT_Encode4(429507),
     /* 428965 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 428968 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 428971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 428975 */   GIM_Try, /*On fail goto*//*Label 8468*/ GIMT_Encode4(429088), // Rule ID 6878 //
     /* 428980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 428983 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 428987 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 428991 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 428995 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 428999 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429004 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 429008 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 429012 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429016 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429020 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 429024 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429029 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 429033 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429037 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 429041 */     // MIs[3] Operand 1
     /* 429041 */     // No operand predicates
     /* 429041 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 429043 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 429043 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 429046 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 429050 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429055 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 429061 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429066 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 429074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429076 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 429079 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 429083 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 429086 */     GIR_RootConstrainSelectedInstOperands,
     /* 429087 */     // GIR_Coverage, 6878,
     /* 429087 */     GIR_EraseRootFromParent_Done,
     /* 429088 */   // Label 8468: @429088
     /* 429088 */   GIM_Try, /*On fail goto*//*Label 8469*/ GIMT_Encode4(429201), // Rule ID 14981 //
     /* 429093 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429096 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429100 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429104 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429108 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429112 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429117 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 429121 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429125 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 429129 */     // MIs[2] Operand 1
     /* 429129 */     // No operand predicates
     /* 429129 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 429133 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429137 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429141 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 429145 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429150 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 429154 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 429156 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }))  =>  (FMULv1i64_indexed:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 429156 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 429159 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 429163 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429168 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 429174 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429179 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 429187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429189 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 429192 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429196 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 429199 */     GIR_RootConstrainSelectedInstOperands,
     /* 429200 */     // GIR_Coverage, 14981,
     /* 429200 */     GIR_EraseRootFromParent_Done,
     /* 429201 */   // Label 8469: @429201
     /* 429201 */   GIM_Try, /*On fail goto*//*Label 8470*/ GIMT_Encode4(429277), // Rule ID 14870 //
     /* 429206 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429210 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429214 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429218 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429222 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429227 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 429231 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429235 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429237 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rn)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 429237 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 429240 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 429244 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429249 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 429255 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429260 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 429268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429270 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429272 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 429275 */     GIR_RootConstrainSelectedInstOperands,
     /* 429276 */     // GIR_Coverage, 14870,
     /* 429276 */     GIR_EraseRootFromParent_Done,
     /* 429277 */   // Label 8470: @429277
     /* 429277 */   GIM_Try, /*On fail goto*//*Label 8471*/ GIMT_Encode4(429353), // Rule ID 4883 //
     /* 429282 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429286 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429290 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429294 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429298 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429302 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429307 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 429311 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429313 */     // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }))  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }))
     /* 429313 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 429316 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 429320 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429325 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 429331 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429336 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 429344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429346 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429348 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 429351 */     GIR_RootConstrainSelectedInstOperands,
     /* 429352 */     // GIR_Coverage, 4883,
     /* 429352 */     GIR_EraseRootFromParent_Done,
     /* 429353 */   // Label 8471: @429353
     /* 429353 */   GIM_Try, /*On fail goto*//*Label 8472*/ GIMT_Encode4(429416), // Rule ID 14505 //
     /* 429358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429369 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429373 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429377 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429382 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 429386 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429390 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 429394 */     // MIs[2] Operand 1
     /* 429394 */     // No operand predicates
     /* 429394 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429398 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 429400 */     // (strict_fmul:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64Op:{ *:[f64] }:$Rn)  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 429403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429405 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429407 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429411 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 429414 */     GIR_RootConstrainSelectedInstOperands,
     /* 429415 */     // GIR_Coverage, 14505,
     /* 429415 */     GIR_EraseRootFromParent_Done,
     /* 429416 */   // Label 8472: @429416
     /* 429416 */   GIM_Try, /*On fail goto*//*Label 8473*/ GIMT_Encode4(429479), // Rule ID 2046 //
     /* 429421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429424 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429428 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429432 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 429436 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 429440 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429444 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429449 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 429453 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429457 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 429461 */     // MIs[2] Operand 1
     /* 429461 */     // No operand predicates
     /* 429461 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 429463 */     // (strict_fmul:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv1i64_indexed:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429463 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv1i64_indexed),
     /* 429466 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429468 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429474 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 429477 */     GIR_RootConstrainSelectedInstOperands,
     /* 429478 */     // GIR_Coverage, 2046,
     /* 429478 */     GIR_EraseRootFromParent_Done,
     /* 429479 */   // Label 8473: @429479
     /* 429479 */   GIM_Try, /*On fail goto*//*Label 8474*/ GIMT_Encode4(429506), // Rule ID 665 //
     /* 429484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 429487 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429491 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429495 */     // (strict_fmul:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FMULDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 429495 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULDrr),
     /* 429500 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 429504 */     GIR_RootConstrainSelectedInstOperands,
     /* 429505 */     // GIR_Coverage, 665,
     /* 429505 */     GIR_Done,
     /* 429506 */   // Label 8474: @429506
     /* 429506 */   GIM_Reject,
     /* 429507 */ // Label 8467: @429507
     /* 429507 */ GIM_Reject,
     /* 429508 */ // Label 8445: @429508
     /* 429508 */ GIM_Try, /*On fail goto*//*Label 8475*/ GIMT_Encode4(430037),
     /* 429513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 429516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 429519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429523 */   GIM_Try, /*On fail goto*//*Label 8476*/ GIMT_Encode4(429609), // Rule ID 14493 //
     /* 429528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429531 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429535 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 429539 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429543 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 429547 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 429551 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429555 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 429559 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429564 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 429568 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429572 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 429576 */     // MIs[3] Operand 1
     /* 429576 */     // No operand predicates
     /* 429576 */     // MIs[1] Operand 2
     /* 429576 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 429587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429591 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 429593 */     // (strict_fmul:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429598 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429600 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 429604 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 429607 */     GIR_RootConstrainSelectedInstOperands,
     /* 429608 */     // GIR_Coverage, 14493,
     /* 429608 */     GIR_EraseRootFromParent_Done,
     /* 429609 */   // Label 8476: @429609
     /* 429609 */   GIM_Try, /*On fail goto*//*Label 8477*/ GIMT_Encode4(429695), // Rule ID 2034 //
     /* 429614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429617 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429621 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429625 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 429629 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429633 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 429637 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 429641 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429645 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 429649 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429654 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 429658 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429662 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 429666 */     // MIs[3] Operand 1
     /* 429666 */     // No operand predicates
     /* 429666 */     // MIs[1] Operand 2
     /* 429666 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 429677 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 429679 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (extract_subvector:{ *:[v2f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429679 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429682 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429684 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 429690 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 429693 */     GIR_RootConstrainSelectedInstOperands,
     /* 429694 */     // GIR_Coverage, 2034,
     /* 429694 */     GIR_EraseRootFromParent_Done,
     /* 429695 */   // Label 8477: @429695
     /* 429695 */   GIM_Try, /*On fail goto*//*Label 8478*/ GIMT_Encode4(429758), // Rule ID 14494 //
     /* 429700 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429703 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429707 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 429711 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429715 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429719 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429724 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 429728 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429732 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 429736 */     // MIs[2] Operand 1
     /* 429736 */     // No operand predicates
     /* 429736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429740 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 429742 */     // (strict_fmul:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429753 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 429756 */     GIR_RootConstrainSelectedInstOperands,
     /* 429757 */     // GIR_Coverage, 14494,
     /* 429757 */     GIR_EraseRootFromParent_Done,
     /* 429758 */   // Label 8478: @429758
     /* 429758 */   GIM_Try, /*On fail goto*//*Label 8479*/ GIMT_Encode4(429821), // Rule ID 2035 //
     /* 429763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 429766 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429770 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429774 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 429778 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 429782 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 429786 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429791 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 429795 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 429799 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 429803 */     // MIs[2] Operand 1
     /* 429803 */     // No operand predicates
     /* 429803 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 429805 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 429805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429810 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 429812 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429816 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 429819 */     GIR_RootConstrainSelectedInstOperands,
     /* 429820 */     // GIR_Coverage, 2035,
     /* 429820 */     GIR_EraseRootFromParent_Done,
     /* 429821 */   // Label 8479: @429821
     /* 429821 */   GIM_Try, /*On fail goto*//*Label 8480*/ GIMT_Encode4(429915), // Rule ID 14983 //
     /* 429826 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 429830 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 429834 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 429838 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429843 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429847 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429849 */     // (strict_fmul:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn)  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 429849 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 429852 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 429856 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429861 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 429863 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 429866 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 429870 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429875 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 429878 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429882 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 429885 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429890 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429895 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429905 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 429907 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 429910 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 429913 */     GIR_RootConstrainSelectedInstOperands,
     /* 429914 */     // GIR_Coverage, 14983,
     /* 429914 */     GIR_EraseRootFromParent_Done,
     /* 429915 */   // Label 8480: @429915
     /* 429915 */   GIM_Try, /*On fail goto*//*Label 8481*/ GIMT_Encode4(430009), // Rule ID 6880 //
     /* 429920 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 429924 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 429928 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 429932 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 429936 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429941 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 429943 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 429943 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 429946 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 429950 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429955 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 429957 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 429960 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 429964 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 429969 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 429972 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 429976 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 429979 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429984 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 429989 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 429994 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i32_indexed),
     /* 429997 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 429999 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430001 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 430004 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 430007 */     GIR_RootConstrainSelectedInstOperands,
     /* 430008 */     // GIR_Coverage, 6880,
     /* 430008 */     GIR_EraseRootFromParent_Done,
     /* 430009 */   // Label 8481: @430009
     /* 430009 */   GIM_Try, /*On fail goto*//*Label 8482*/ GIMT_Encode4(430036), // Rule ID 1352 //
     /* 430014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430017 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430021 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430025 */     // (strict_fmul:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FMULv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 430025 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f32),
     /* 430030 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430034 */     GIR_RootConstrainSelectedInstOperands,
     /* 430035 */     // GIR_Coverage, 1352,
     /* 430035 */     GIR_Done,
     /* 430036 */   // Label 8482: @430036
     /* 430036 */   GIM_Reject,
     /* 430037 */ // Label 8475: @430037
     /* 430037 */ GIM_Reject,
     /* 430038 */ // Label 8446: @430038
     /* 430038 */ GIM_Try, /*On fail goto*//*Label 8483*/ GIMT_Encode4(430395),
     /* 430043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430046 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 430049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430053 */   GIM_Try, /*On fail goto*//*Label 8484*/ GIMT_Encode4(430116), // Rule ID 14499 //
     /* 430058 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430061 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430065 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 430069 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430073 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430077 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430082 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430086 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430090 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 430094 */     // MIs[2] Operand 1
     /* 430094 */     // No operand predicates
     /* 430094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430098 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430100 */     // (strict_fmul:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 430103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430105 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430107 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430111 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430114 */     GIR_RootConstrainSelectedInstOperands,
     /* 430115 */     // GIR_Coverage, 14499,
     /* 430115 */     GIR_EraseRootFromParent_Done,
     /* 430116 */   // Label 8484: @430116
     /* 430116 */   GIM_Try, /*On fail goto*//*Label 8485*/ GIMT_Encode4(430179), // Rule ID 2040 //
     /* 430121 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430124 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430128 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430132 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 430136 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 430140 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430144 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430149 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430153 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430157 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 430161 */     // MIs[2] Operand 1
     /* 430161 */     // No operand predicates
     /* 430161 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430163 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 430166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430168 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430170 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430174 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430177 */     GIR_RootConstrainSelectedInstOperands,
     /* 430178 */     // GIR_Coverage, 2040,
     /* 430178 */     GIR_EraseRootFromParent_Done,
     /* 430179 */   // Label 8485: @430179
     /* 430179 */   GIM_Try, /*On fail goto*//*Label 8486*/ GIMT_Encode4(430273), // Rule ID 14987 //
     /* 430184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 430192 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 430196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430201 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430205 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430207 */     // (strict_fmul:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn)  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 430207 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 430210 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 430214 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430219 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 430221 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 430224 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 430228 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430233 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 430236 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430240 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 430243 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430248 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430253 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 430261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430263 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430265 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 430268 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 430271 */     GIR_RootConstrainSelectedInstOperands,
     /* 430272 */     // GIR_Coverage, 14987,
     /* 430272 */     GIR_EraseRootFromParent_Done,
     /* 430273 */   // Label 8486: @430273
     /* 430273 */   GIM_Try, /*On fail goto*//*Label 8487*/ GIMT_Encode4(430367), // Rule ID 6884 //
     /* 430278 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 430290 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 430294 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430301 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rm))  =>  (FMULv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 430301 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 430304 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 430308 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430313 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 430315 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 430318 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 430322 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430327 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 430330 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430334 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 430337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430342 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430347 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv2i64_indexed),
     /* 430355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430357 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430359 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 430362 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 430365 */     GIR_RootConstrainSelectedInstOperands,
     /* 430366 */     // GIR_Coverage, 6884,
     /* 430366 */     GIR_EraseRootFromParent_Done,
     /* 430367 */   // Label 8487: @430367
     /* 430367 */   GIM_Try, /*On fail goto*//*Label 8488*/ GIMT_Encode4(430394), // Rule ID 1356 //
     /* 430372 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430375 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430383 */     // (strict_fmul:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FMULv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 430383 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv2f64),
     /* 430388 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430392 */     GIR_RootConstrainSelectedInstOperands,
     /* 430393 */     // GIR_Coverage, 1356,
     /* 430393 */     GIR_Done,
     /* 430394 */   // Label 8488: @430394
     /* 430394 */   GIM_Reject,
     /* 430395 */ // Label 8483: @430395
     /* 430395 */ GIM_Reject,
     /* 430396 */ // Label 8447: @430396
     /* 430396 */ GIM_Try, /*On fail goto*//*Label 8489*/ GIMT_Encode4(430737),
     /* 430401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 430404 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 430407 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430411 */   GIM_Try, /*On fail goto*//*Label 8490*/ GIMT_Encode4(430497), // Rule ID 14487 //
     /* 430416 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430419 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430423 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 430427 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430431 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 430435 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 430439 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430443 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 430447 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 430452 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 430456 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430460 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 430464 */     // MIs[3] Operand 1
     /* 430464 */     // No operand predicates
     /* 430464 */     // MIs[1] Operand 2
     /* 430464 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 430475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430479 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 430481 */     // (strict_fmul:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 430484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430486 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430492 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 430495 */     GIR_RootConstrainSelectedInstOperands,
     /* 430496 */     // GIR_Coverage, 14487,
     /* 430496 */     GIR_EraseRootFromParent_Done,
     /* 430497 */   // Label 8490: @430497
     /* 430497 */   GIM_Try, /*On fail goto*//*Label 8491*/ GIMT_Encode4(430583), // Rule ID 2028 //
     /* 430502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430505 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430509 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430513 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 430517 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430521 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 430525 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 430529 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430533 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 430537 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 430542 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 430546 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430550 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 430554 */     // MIs[3] Operand 1
     /* 430554 */     // No operand predicates
     /* 430554 */     // MIs[1] Operand 2
     /* 430554 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 430565 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 430567 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (extract_subvector:{ *:[v4f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 430570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430572 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430574 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 430578 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 430581 */     GIR_RootConstrainSelectedInstOperands,
     /* 430582 */     // GIR_Coverage, 2028,
     /* 430582 */     GIR_EraseRootFromParent_Done,
     /* 430583 */   // Label 8491: @430583
     /* 430583 */   GIM_Try, /*On fail goto*//*Label 8492*/ GIMT_Encode4(430646), // Rule ID 14488 //
     /* 430588 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430591 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430595 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 430599 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430603 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430607 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 430612 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430616 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430620 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 430624 */     // MIs[2] Operand 1
     /* 430624 */     // No operand predicates
     /* 430624 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430628 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430630 */     // (strict_fmul:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn)  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 430633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430635 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430637 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430641 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430644 */     GIR_RootConstrainSelectedInstOperands,
     /* 430645 */     // GIR_Coverage, 14488,
     /* 430645 */     GIR_EraseRootFromParent_Done,
     /* 430646 */   // Label 8492: @430646
     /* 430646 */   GIM_Try, /*On fail goto*//*Label 8493*/ GIMT_Encode4(430709), // Rule ID 2029 //
     /* 430651 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430654 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430658 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430662 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 430666 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 430670 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430674 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 430679 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430683 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430687 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 430691 */     // MIs[2] Operand 1
     /* 430691 */     // No operand predicates
     /* 430691 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430693 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i16_indexed),
     /* 430696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430698 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430700 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430704 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430707 */     GIR_RootConstrainSelectedInstOperands,
     /* 430708 */     // GIR_Coverage, 2029,
     /* 430708 */     GIR_EraseRootFromParent_Done,
     /* 430709 */   // Label 8493: @430709
     /* 430709 */   GIM_Try, /*On fail goto*//*Label 8494*/ GIMT_Encode4(430736), // Rule ID 1348 //
     /* 430714 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 430717 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430721 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 430725 */     // (strict_fmul:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FMULv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 430725 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f16),
     /* 430730 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 430734 */     GIR_RootConstrainSelectedInstOperands,
     /* 430735 */     // GIR_Coverage, 1348,
     /* 430735 */     GIR_Done,
     /* 430736 */   // Label 8494: @430736
     /* 430736 */   GIM_Reject,
     /* 430737 */ // Label 8489: @430737
     /* 430737 */ GIM_Reject,
     /* 430738 */ // Label 8448: @430738
     /* 430738 */ GIM_Try, /*On fail goto*//*Label 8495*/ GIMT_Encode4(431095),
     /* 430743 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430746 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 430749 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430753 */   GIM_Try, /*On fail goto*//*Label 8496*/ GIMT_Encode4(430816), // Rule ID 14497 //
     /* 430758 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430761 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430765 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 430769 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430773 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430777 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430782 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430786 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430790 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 430794 */     // MIs[2] Operand 1
     /* 430794 */     // No operand predicates
     /* 430794 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430798 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430800 */     // (strict_fmul:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430800 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 430803 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430805 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430807 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430811 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430814 */     GIR_RootConstrainSelectedInstOperands,
     /* 430815 */     // GIR_Coverage, 14497,
     /* 430815 */     GIR_EraseRootFromParent_Done,
     /* 430816 */   // Label 8496: @430816
     /* 430816 */   GIM_Try, /*On fail goto*//*Label 8497*/ GIMT_Encode4(430879), // Rule ID 2038 //
     /* 430821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 430824 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430828 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430832 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 430836 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 430840 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 430844 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430849 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 430853 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 430857 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 430861 */     // MIs[2] Operand 1
     /* 430861 */     // No operand predicates
     /* 430861 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 430863 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 430863 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 430866 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430868 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 430870 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430874 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 430877 */     GIR_RootConstrainSelectedInstOperands,
     /* 430878 */     // GIR_Coverage, 2038,
     /* 430878 */     GIR_EraseRootFromParent_Done,
     /* 430879 */   // Label 8497: @430879
     /* 430879 */   GIM_Try, /*On fail goto*//*Label 8498*/ GIMT_Encode4(430973), // Rule ID 14985 //
     /* 430884 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 430888 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 430892 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 430896 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430901 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430905 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 430907 */     // (strict_fmul:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn)  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 430907 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 430910 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 430914 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430919 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 430921 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 430924 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 430928 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 430933 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 430936 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 430940 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 430943 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430948 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430953 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430958 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 430961 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 430963 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 430965 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 430968 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 430971 */     GIR_RootConstrainSelectedInstOperands,
     /* 430972 */     // GIR_Coverage, 14985,
     /* 430972 */     GIR_EraseRootFromParent_Done,
     /* 430973 */   // Label 8498: @430973
     /* 430973 */   GIM_Try, /*On fail goto*//*Label 8499*/ GIMT_Encode4(431067), // Rule ID 6882 //
     /* 430978 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 430982 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 430986 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 430990 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 430994 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 430999 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 431001 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rm))  =>  (FMULv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 431001 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 431004 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 431008 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431013 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 431015 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 431018 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 431022 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431027 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 431030 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 431034 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 431037 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431042 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431047 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 431052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv4i32_indexed),
     /* 431055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431057 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 431062 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 431065 */     GIR_RootConstrainSelectedInstOperands,
     /* 431066 */     // GIR_Coverage, 6882,
     /* 431066 */     GIR_EraseRootFromParent_Done,
     /* 431067 */   // Label 8499: @431067
     /* 431067 */   GIM_Try, /*On fail goto*//*Label 8500*/ GIMT_Encode4(431094), // Rule ID 1354 //
     /* 431072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431075 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431079 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431083 */     // (strict_fmul:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FMULv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 431083 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 431088 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431092 */     GIR_RootConstrainSelectedInstOperands,
     /* 431093 */     // GIR_Coverage, 1354,
     /* 431093 */     GIR_Done,
     /* 431094 */   // Label 8500: @431094
     /* 431094 */   GIM_Reject,
     /* 431095 */ // Label 8495: @431095
     /* 431095 */ GIM_Reject,
     /* 431096 */ // Label 8449: @431096
     /* 431096 */ GIM_Try, /*On fail goto*//*Label 8501*/ GIMT_Encode4(431527),
     /* 431101 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431104 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 431107 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431111 */   GIM_Try, /*On fail goto*//*Label 8502*/ GIMT_Encode4(431174), // Rule ID 14491 //
     /* 431116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 431123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 431127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431131 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 431135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 431140 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 431144 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 431148 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 431152 */     // MIs[2] Operand 1
     /* 431152 */     // No operand predicates
     /* 431152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431156 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431158 */     // (strict_fmul:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn)  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 431158 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 431161 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431163 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 431165 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 431169 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 431172 */     GIR_RootConstrainSelectedInstOperands,
     /* 431173 */     // GIR_Coverage, 14491,
     /* 431173 */     GIR_EraseRootFromParent_Done,
     /* 431174 */   // Label 8502: @431174
     /* 431174 */   GIM_Try, /*On fail goto*//*Label 8503*/ GIMT_Encode4(431237), // Rule ID 2032 //
     /* 431179 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431182 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 431190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 431194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431198 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 431202 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 431207 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 431211 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 431215 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 431219 */     // MIs[2] Operand 1
     /* 431219 */     // No operand predicates
     /* 431219 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 431221 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (FMULv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 431221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMULv8i16_indexed),
     /* 431224 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 431226 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 431228 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 431232 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 431235 */     GIR_RootConstrainSelectedInstOperands,
     /* 431236 */     // GIR_Coverage, 2032,
     /* 431236 */     GIR_EraseRootFromParent_Done,
     /* 431237 */   // Label 8503: @431237
     /* 431237 */   GIM_Try, /*On fail goto*//*Label 8504*/ GIMT_Encode4(431264), // Rule ID 1350 //
     /* 431242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431245 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431249 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431253 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FMULv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 431253 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMULv8f16),
     /* 431258 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431262 */     GIR_RootConstrainSelectedInstOperands,
     /* 431263 */     // GIR_Coverage, 1350,
     /* 431263 */     GIR_Done,
     /* 431264 */   // Label 8504: @431264
     /* 431264 */   GIM_Try, /*On fail goto*//*Label 8505*/ GIMT_Encode4(431526), // Rule ID 7663 //
     /* 431269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 431272 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431276 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431280 */     // (strict_fmul:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FMULv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FMULv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 431280 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 431283 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 431287 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431292 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 431296 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 431298 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 431301 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 431305 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431310 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 431314 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 431316 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 431319 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 431323 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431328 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 431331 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 431334 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 431336 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 431339 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 431343 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431348 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 431354 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431359 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431364 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 431367 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 431371 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431376 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 431379 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 431381 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 431384 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 431388 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431393 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 431399 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431404 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431409 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 431412 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 431416 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431421 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 431424 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 431426 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 431429 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FMULv4f32),
     /* 431433 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431438 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 431441 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 431444 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 431446 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 431449 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 431453 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431458 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 431461 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 431463 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 431466 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 431470 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431475 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 431477 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 431480 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 431484 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431489 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 431492 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 431495 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 431498 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431503 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431508 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 431516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 431518 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 431521 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 431524 */     GIR_RootConstrainSelectedInstOperands,
     /* 431525 */     // GIR_Coverage, 7663,
     /* 431525 */     GIR_EraseRootFromParent_Done,
     /* 431526 */   // Label 8505: @431526
     /* 431526 */   GIM_Reject,
     /* 431527 */ // Label 8501: @431527
     /* 431527 */ GIM_Reject,
     /* 431528 */ // Label 8450: @431528
     /* 431528 */ GIM_Reject,
     /* 431529 */ // Label 116: @431529
     /* 431529 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8514*/ GIMT_Encode4(432144),
     /* 431540 */ /*GILLT_s16*//*Label 8506*/ GIMT_Encode4(431580),
     /* 431544 */ /*GILLT_s32*//*Label 8507*/ GIMT_Encode4(431618),
     /* 431548 */ /*GILLT_s64*//*Label 8508*/ GIMT_Encode4(431656), GIMT_Encode4(0),
     /* 431556 */ /*GILLT_v2s32*//*Label 8509*/ GIMT_Encode4(431694),
     /* 431560 */ /*GILLT_v2s64*//*Label 8510*/ GIMT_Encode4(431732),
     /* 431564 */ /*GILLT_v4s16*//*Label 8511*/ GIMT_Encode4(431770),
     /* 431568 */ /*GILLT_v4s32*//*Label 8512*/ GIMT_Encode4(431808), GIMT_Encode4(0),
     /* 431576 */ /*GILLT_v8s16*//*Label 8513*/ GIMT_Encode4(431846),
     /* 431580 */ // Label 8506: @431580
     /* 431580 */ GIM_Try, /*On fail goto*//*Label 8515*/ GIMT_Encode4(431617), // Rule ID 631 //
     /* 431585 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 431588 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 431591 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 431594 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 431598 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 431602 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 431606 */   // (strict_fdiv:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)  =>  (FDIVHrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm)
     /* 431606 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVHrr),
     /* 431611 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431615 */   GIR_RootConstrainSelectedInstOperands,
     /* 431616 */   // GIR_Coverage, 631,
     /* 431616 */   GIR_Done,
     /* 431617 */ // Label 8515: @431617
     /* 431617 */ GIM_Reject,
     /* 431618 */ // Label 8507: @431618
     /* 431618 */ GIM_Try, /*On fail goto*//*Label 8516*/ GIMT_Encode4(431655), // Rule ID 633 //
     /* 431623 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 431626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 431629 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 431632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 431636 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 431640 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 431644 */   // (strict_fdiv:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FDIVSrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 431644 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVSrr),
     /* 431649 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431653 */   GIR_RootConstrainSelectedInstOperands,
     /* 431654 */   // GIR_Coverage, 633,
     /* 431654 */   GIR_Done,
     /* 431655 */ // Label 8516: @431655
     /* 431655 */ GIM_Reject,
     /* 431656 */ // Label 8508: @431656
     /* 431656 */ GIM_Try, /*On fail goto*//*Label 8517*/ GIMT_Encode4(431693), // Rule ID 635 //
     /* 431661 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 431664 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 431667 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 431670 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431674 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431678 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431682 */   // (strict_fdiv:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FDIVDrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 431682 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVDrr),
     /* 431687 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431691 */   GIR_RootConstrainSelectedInstOperands,
     /* 431692 */   // GIR_Coverage, 635,
     /* 431692 */   GIR_Done,
     /* 431693 */ // Label 8517: @431693
     /* 431693 */ GIM_Reject,
     /* 431694 */ // Label 8509: @431694
     /* 431694 */ GIM_Try, /*On fail goto*//*Label 8518*/ GIMT_Encode4(431731), // Rule ID 1257 //
     /* 431699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 431705 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 431708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431712 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431716 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431720 */   // (strict_fdiv:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FDIVv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 431720 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f32),
     /* 431725 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431729 */   GIR_RootConstrainSelectedInstOperands,
     /* 431730 */   // GIR_Coverage, 1257,
     /* 431730 */   GIR_Done,
     /* 431731 */ // Label 8518: @431731
     /* 431731 */ GIM_Reject,
     /* 431732 */ // Label 8510: @431732
     /* 431732 */ GIM_Try, /*On fail goto*//*Label 8519*/ GIMT_Encode4(431769), // Rule ID 1261 //
     /* 431737 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 431743 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 431746 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431750 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431754 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431758 */   // (strict_fdiv:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FDIVv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 431758 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv2f64),
     /* 431763 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431767 */   GIR_RootConstrainSelectedInstOperands,
     /* 431768 */   // GIR_Coverage, 1261,
     /* 431768 */   GIR_Done,
     /* 431769 */ // Label 8519: @431769
     /* 431769 */ GIM_Reject,
     /* 431770 */ // Label 8511: @431770
     /* 431770 */ GIM_Try, /*On fail goto*//*Label 8520*/ GIMT_Encode4(431807), // Rule ID 1253 //
     /* 431775 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431778 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 431781 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 431784 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431788 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431792 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431796 */   // (strict_fdiv:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FDIVv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 431796 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f16),
     /* 431801 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431805 */   GIR_RootConstrainSelectedInstOperands,
     /* 431806 */   // GIR_Coverage, 1253,
     /* 431806 */   GIR_Done,
     /* 431807 */ // Label 8520: @431807
     /* 431807 */ GIM_Reject,
     /* 431808 */ // Label 8512: @431808
     /* 431808 */ GIM_Try, /*On fail goto*//*Label 8521*/ GIMT_Encode4(431845), // Rule ID 1259 //
     /* 431813 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 431816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 431819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 431822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431830 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431834 */   // (strict_fdiv:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FDIVv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 431834 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 431839 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431843 */   GIR_RootConstrainSelectedInstOperands,
     /* 431844 */   // GIR_Coverage, 1259,
     /* 431844 */   GIR_Done,
     /* 431845 */ // Label 8521: @431845
     /* 431845 */ GIM_Reject,
     /* 431846 */ // Label 8513: @431846
     /* 431846 */ GIM_Try, /*On fail goto*//*Label 8522*/ GIMT_Encode4(432143),
     /* 431851 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 431854 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 431857 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431861 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431865 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431869 */   GIM_Try, /*On fail goto*//*Label 8523*/ GIMT_Encode4(431888), // Rule ID 1255 //
     /* 431874 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 431877 */     // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FDIVv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 431877 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FDIVv8f16),
     /* 431882 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 431886 */     GIR_RootConstrainSelectedInstOperands,
     /* 431887 */     // GIR_Coverage, 1255,
     /* 431887 */     GIR_Done,
     /* 431888 */   // Label 8523: @431888
     /* 431888 */   GIM_Try, /*On fail goto*//*Label 8524*/ GIMT_Encode4(432142), // Rule ID 7661 //
     /* 431893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoFullFP16),
     /* 431896 */     // (strict_fdiv:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCVTNv8i16:{ *:[v8f16] } (INSERT_SUBREG:{ *:[f128] } (IMPLICIT_DEF:{ *:[f128] }), (FCVTNv4i16:{ *:[v4f16] } (FDIVv4f32:{ *:[v4f32] } (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rn, dsub:{ *:[i32] })), (FCVTLv4i16:{ *:[v4f32] } (EXTRACT_SUBREG:{ *:[v4i16] } V128:{ *:[v8f16] }:$Rm, dsub:{ *:[i32] })))), dsub:{ *:[i32] }), (FDIVv4f32:{ *:[v4f32] } (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rn), (FCVTLv8i16:{ *:[v4f32] } V128:{ *:[v8f16] }:$Rm)))
     /* 431896 */     GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v4s32,
     /* 431899 */     GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 431903 */     GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431908 */     GIR_Copy, /*NewInsnID*/11, /*OldInsnID*/0, /*OpIdx*/2, // Rm
     /* 431912 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
     /* 431914 */     GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v4s32,
     /* 431917 */     GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv8i16),
     /* 431921 */     GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431926 */     GIR_Copy, /*NewInsnID*/10, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 431930 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
     /* 431932 */     GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v4s32,
     /* 431935 */     GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 431939 */     GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431944 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
     /* 431947 */     GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
     /* 431950 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
     /* 431952 */     GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
     /* 431955 */     GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 431959 */     GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431964 */     GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 431970 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 431975 */     GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 431980 */     GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s32,
     /* 431983 */     GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 431987 */     GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 431992 */     GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
     /* 431995 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
     /* 431997 */     GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
     /* 432000 */     GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432004 */     GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432009 */     GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 432015 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432020 */     GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432025 */     GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s32,
     /* 432028 */     GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AArch64::FCVTLv4i16),
     /* 432032 */     GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432037 */     GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
     /* 432040 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
     /* 432042 */     GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s32,
     /* 432045 */     GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AArch64::FDIVv4f32),
     /* 432049 */     GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432054 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
     /* 432057 */     GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/6,
     /* 432060 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 432062 */     GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
     /* 432065 */     GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv4i16),
     /* 432069 */     GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432074 */     GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 432077 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 432079 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 432082 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 432086 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432091 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 432093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 432096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 432100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432105 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 432108 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
     /* 432111 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 432114 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432119 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432124 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 432129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCVTNv8i16),
     /* 432132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432134 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432137 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
     /* 432140 */     GIR_RootConstrainSelectedInstOperands,
     /* 432141 */     // GIR_Coverage, 7661,
     /* 432141 */     GIR_EraseRootFromParent_Done,
     /* 432142 */   // Label 8524: @432142
     /* 432142 */   GIM_Reject,
     /* 432143 */ // Label 8522: @432143
     /* 432143 */ GIM_Reject,
     /* 432144 */ // Label 8514: @432144
     /* 432144 */ GIM_Reject,
     /* 432145 */ // Label 117: @432145
     /* 432145 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8533*/ GIMT_Encode4(447751),
     /* 432156 */ /*GILLT_s16*//*Label 8525*/ GIMT_Encode4(432196),
     /* 432160 */ /*GILLT_s32*//*Label 8526*/ GIMT_Encode4(434970),
     /* 432164 */ /*GILLT_s64*//*Label 8527*/ GIMT_Encode4(437900), GIMT_Encode4(0),
     /* 432172 */ /*GILLT_v2s32*//*Label 8528*/ GIMT_Encode4(440830),
     /* 432176 */ /*GILLT_v2s64*//*Label 8529*/ GIMT_Encode4(442351),
     /* 432180 */ /*GILLT_v4s16*//*Label 8530*/ GIMT_Encode4(443872),
     /* 432184 */ /*GILLT_v4s32*//*Label 8531*/ GIMT_Encode4(445051), GIMT_Encode4(0),
     /* 432192 */ /*GILLT_v8s16*//*Label 8532*/ GIMT_Encode4(446572),
     /* 432196 */ // Label 8525: @432196
     /* 432196 */ GIM_Try, /*On fail goto*//*Label 8534*/ GIMT_Encode4(434969),
     /* 432201 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 432204 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
     /* 432207 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
     /* 432210 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432214 */   GIM_Try, /*On fail goto*//*Label 8535*/ GIMT_Encode4(432364), // Rule ID 4941 //
     /* 432219 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 432222 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432226 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432230 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432234 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 432238 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432243 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 432247 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 432251 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432255 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432259 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 432263 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432268 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 432272 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 432276 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432280 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 432284 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432289 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 432291 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 432291 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 432294 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432298 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432303 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 432309 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432314 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432319 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432322 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432326 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432331 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 432337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432342 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 432350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 432352 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432355 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 432358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 432362 */     GIR_RootConstrainSelectedInstOperands,
     /* 432363 */     // GIR_Coverage, 4941,
     /* 432363 */     GIR_EraseRootFromParent_Done,
     /* 432364 */   // Label 8535: @432364
     /* 432364 */   GIM_Try, /*On fail goto*//*Label 8536*/ GIMT_Encode4(432511), // Rule ID 4905 //
     /* 432369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 432372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432380 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432384 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 432388 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432393 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 432397 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 432401 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432405 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 432409 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 432413 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432417 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432421 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 432425 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432430 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 432434 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432438 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 432440 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 432440 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 432443 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432447 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432452 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 432458 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432463 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432468 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432471 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432475 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432480 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 432486 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432491 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 432499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 432501 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432504 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 432507 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 432509 */     GIR_RootConstrainSelectedInstOperands,
     /* 432510 */     // GIR_Coverage, 4905,
     /* 432510 */     GIR_EraseRootFromParent_Done,
     /* 432511 */   // Label 8536: @432511
     /* 432511 */   GIM_Try, /*On fail goto*//*Label 8537*/ GIMT_Encode4(432658), // Rule ID 14879 //
     /* 432516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 432519 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432523 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432527 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 432531 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 432535 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432539 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432543 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 432547 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432552 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 432556 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 432560 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432564 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432568 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 432572 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432577 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 432581 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432585 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 432587 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 432587 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 432590 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432594 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432599 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 432605 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432610 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432615 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432618 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432622 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432627 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 432633 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432638 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432643 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 432646 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 432648 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432651 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 432654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 432656 */     GIR_RootConstrainSelectedInstOperands,
     /* 432657 */     // GIR_Coverage, 14879,
     /* 432657 */     GIR_EraseRootFromParent_Done,
     /* 432658 */   // Label 8537: @432658
     /* 432658 */   GIM_Try, /*On fail goto*//*Label 8538*/ GIMT_Encode4(432789), // Rule ID 6712 //
     /* 432663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 432666 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432670 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432674 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432678 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 432682 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432687 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 432691 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 432695 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432699 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 432703 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 432707 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432711 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432715 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 432719 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 432724 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 432728 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 432732 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 432736 */     // MIs[4] Operand 1
     /* 432736 */     // No operand predicates
     /* 432736 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432740 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 432742 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 432742 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432745 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432749 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432754 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 432760 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432765 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 432773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 432777 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432780 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 432784 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 432787 */     GIR_RootConstrainSelectedInstOperands,
     /* 432788 */     // GIR_Coverage, 6712,
     /* 432788 */     GIR_EraseRootFromParent_Done,
     /* 432789 */   // Label 8538: @432789
     /* 432789 */   GIM_Try, /*On fail goto*//*Label 8539*/ GIMT_Encode4(432920), // Rule ID 6744 //
     /* 432794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 432797 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432801 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432805 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432809 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 432813 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 432818 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 432822 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 432826 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 432830 */     // MIs[2] Operand 1
     /* 432830 */     // No operand predicates
     /* 432830 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 432834 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432838 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 432842 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 432846 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432850 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432854 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 432858 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432863 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 432867 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432871 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 432873 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 432873 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 432876 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 432880 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 432885 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 432891 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 432896 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 432904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 432906 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 432908 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 432911 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 432915 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 432918 */     GIR_RootConstrainSelectedInstOperands,
     /* 432919 */     // GIR_Coverage, 6744,
     /* 432919 */     GIR_EraseRootFromParent_Done,
     /* 432920 */   // Label 8539: @432920
     /* 432920 */   GIM_Try, /*On fail goto*//*Label 8540*/ GIMT_Encode4(433051), // Rule ID 6808 //
     /* 432925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 432928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 432932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 432936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 432940 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 432944 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432948 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432952 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 432956 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 432961 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 432965 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 432969 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 432973 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 432977 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 432981 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 432986 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 432990 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 432994 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 432998 */     // MIs[4] Operand 1
     /* 432998 */     // No operand predicates
     /* 432998 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433002 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 433004 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 433004 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433007 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433011 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433016 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433022 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433027 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433032 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 433035 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433037 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 433039 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433042 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 433046 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 433049 */     GIR_RootConstrainSelectedInstOperands,
     /* 433050 */     // GIR_Coverage, 6808,
     /* 433050 */     GIR_EraseRootFromParent_Done,
     /* 433051 */   // Label 8540: @433051
     /* 433051 */   GIM_Try, /*On fail goto*//*Label 8541*/ GIMT_Encode4(433182), // Rule ID 6776 //
     /* 433056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 433059 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433063 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433067 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 433071 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433075 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433079 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433083 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433087 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 433092 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433096 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433100 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 433104 */     // MIs[3] Operand 1
     /* 433104 */     // No operand predicates
     /* 433104 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 433108 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433112 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433116 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 433120 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433125 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 433129 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433133 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 433135 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 433135 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433138 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433142 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433147 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433153 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433158 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433163 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 433166 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433168 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 433170 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433173 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433177 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433180 */     GIR_RootConstrainSelectedInstOperands,
     /* 433181 */     // GIR_Coverage, 6776,
     /* 433181 */     GIR_EraseRootFromParent_Done,
     /* 433182 */   // Label 8541: @433182
     /* 433182 */   GIM_Try, /*On fail goto*//*Label 8542*/ GIMT_Encode4(433317), // Rule ID 2492 //
     /* 433187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433194 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433198 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433202 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433206 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433211 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 433215 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 433219 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433223 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433227 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433231 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433236 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 433240 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433244 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 433246 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 433246 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
     /* 433249 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433253 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433258 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 433264 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433269 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433274 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433277 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433281 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433286 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433292 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433297 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 433305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433307 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433310 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 433313 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 433315 */     GIR_RootConstrainSelectedInstOperands,
     /* 433316 */     // GIR_Coverage, 2492,
     /* 433316 */     GIR_EraseRootFromParent_Done,
     /* 433317 */   // Label 8542: @433317
     /* 433317 */   GIM_Try, /*On fail goto*//*Label 8543*/ GIMT_Encode4(433436), // Rule ID 6680 //
     /* 433322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 433325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433337 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433346 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 433350 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 433354 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433358 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433362 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433366 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 433371 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 433375 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433379 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 433383 */     // MIs[3] Operand 1
     /* 433383 */     // No operand predicates
     /* 433383 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433387 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433389 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 433389 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433392 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433396 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433401 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433407 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433412 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 433420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433422 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 433424 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433431 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 433434 */     GIR_RootConstrainSelectedInstOperands,
     /* 433435 */     // GIR_Coverage, 6680,
     /* 433435 */     GIR_EraseRootFromParent_Done,
     /* 433436 */   // Label 8543: @433436
     /* 433436 */   GIM_Try, /*On fail goto*//*Label 8544*/ GIMT_Encode4(433555), // Rule ID 2571 //
     /* 433441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 433444 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433448 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433452 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433456 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433460 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 433465 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 433469 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 433473 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 433477 */     // MIs[2] Operand 1
     /* 433477 */     // No operand predicates
     /* 433477 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 433481 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433485 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433489 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 433493 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433498 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 433502 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433506 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 433508 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (vector_extract:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 433508 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433511 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433515 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433520 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433531 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 433539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 433541 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 433543 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 433550 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 433553 */     GIR_RootConstrainSelectedInstOperands,
     /* 433554 */     // GIR_Coverage, 2571,
     /* 433554 */     GIR_EraseRootFromParent_Done,
     /* 433555 */   // Label 8544: @433555
     /* 433555 */   GIM_Try, /*On fail goto*//*Label 8545*/ GIMT_Encode4(433655), // Rule ID 4903 //
     /* 433560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433563 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433567 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433571 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433575 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433584 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 433588 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 433592 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433596 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 433600 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433605 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433609 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 433611 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 433611 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433614 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433618 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433623 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433629 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433634 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433639 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 433642 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433644 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433647 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 433651 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 433653 */     GIR_RootConstrainSelectedInstOperands,
     /* 433654 */     // GIR_Coverage, 4903,
     /* 433654 */     GIR_EraseRootFromParent_Done,
     /* 433655 */   // Label 8545: @433655
     /* 433655 */   GIM_Try, /*On fail goto*//*Label 8546*/ GIMT_Encode4(433755), // Rule ID 4939 //
     /* 433660 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433663 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433667 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433671 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433675 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433679 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433684 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 433688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433692 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 433696 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433700 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 433704 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433709 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 433711 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 433711 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433714 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433718 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433723 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433729 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433734 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433739 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 433742 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433744 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433747 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 433749 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 433753 */     GIR_RootConstrainSelectedInstOperands,
     /* 433754 */     // GIR_Coverage, 4939,
     /* 433754 */     GIR_EraseRootFromParent_Done,
     /* 433755 */   // Label 8546: @433755
     /* 433755 */   GIM_Try, /*On fail goto*//*Label 8547*/ GIMT_Encode4(433852), // Rule ID 14875 //
     /* 433760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 433775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 433779 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433783 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433787 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433791 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433796 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 433800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433804 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433808 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 433810 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 433810 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433813 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433817 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433822 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 433828 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433833 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433838 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 433841 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433843 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 433845 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433848 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 433850 */     GIR_RootConstrainSelectedInstOperands,
     /* 433851 */     // GIR_Coverage, 14875,
     /* 433851 */     GIR_EraseRootFromParent_Done,
     /* 433852 */   // Label 8547: @433852
     /* 433852 */   GIM_Try, /*On fail goto*//*Label 8548*/ GIMT_Encode4(433952), // Rule ID 14877 //
     /* 433857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433860 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 433864 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433868 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 433872 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433877 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 433881 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433885 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433889 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 433893 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433898 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 433902 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433906 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 433908 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 433908 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 433911 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 433915 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 433920 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 433926 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433931 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 433939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 433941 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 433944 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 433948 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 433950 */     GIR_RootConstrainSelectedInstOperands,
     /* 433951 */     // GIR_Coverage, 14877,
     /* 433951 */     GIR_EraseRootFromParent_Done,
     /* 433952 */   // Label 8548: @433952
     /* 433952 */   GIM_Try, /*On fail goto*//*Label 8549*/ GIMT_Encode4(434052), // Rule ID 4937 //
     /* 433957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 433960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 433964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 433968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 433972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 433976 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 433980 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 433985 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 433989 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 433993 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 433997 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 434001 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434006 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434008 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 434008 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 434011 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 434015 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 434020 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 434026 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434031 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 434039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434041 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434043 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 434046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 434050 */     GIR_RootConstrainSelectedInstOperands,
     /* 434051 */     // GIR_Coverage, 4937,
     /* 434051 */     GIR_EraseRootFromParent_Done,
     /* 434052 */   // Label 8549: @434052
     /* 434052 */   GIM_Try, /*On fail goto*//*Label 8550*/ GIMT_Encode4(434149), // Rule ID 4901 //
     /* 434057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434060 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434076 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434080 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434084 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434088 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434092 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434097 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 434101 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434105 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434107 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] })), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 434107 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 434110 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 434114 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 434119 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 434125 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434130 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 434138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434140 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434142 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 434145 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 434147 */     GIR_RootConstrainSelectedInstOperands,
     /* 434148 */     // GIR_Coverage, 4901,
     /* 434148 */     GIR_EraseRootFromParent_Done,
     /* 434149 */   // Label 8550: @434149
     /* 434149 */   GIM_Try, /*On fail goto*//*Label 8551*/ GIMT_Encode4(434233), // Rule ID 6742 //
     /* 434154 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434157 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434161 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434165 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434169 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434173 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434178 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434182 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434186 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434190 */     // MIs[2] Operand 1
     /* 434190 */     // No operand predicates
     /* 434190 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 434194 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434198 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s16,
     /* 434202 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434207 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434211 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434213 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 434216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434218 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 434224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434228 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434231 */     GIR_RootConstrainSelectedInstOperands,
     /* 434232 */     // GIR_Coverage, 6742,
     /* 434232 */     GIR_EraseRootFromParent_Done,
     /* 434233 */   // Label 8551: @434233
     /* 434233 */   GIM_Try, /*On fail goto*//*Label 8552*/ GIMT_Encode4(434314), // Rule ID 6774 //
     /* 434238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434241 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434245 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434249 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434253 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434257 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434261 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434265 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434269 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434274 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434278 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434282 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434286 */     // MIs[3] Operand 1
     /* 434286 */     // No operand predicates
     /* 434286 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434290 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434294 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434296 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 434299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434301 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434303 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434305 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434309 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434312 */     GIR_RootConstrainSelectedInstOperands,
     /* 434313 */     // GIR_Coverage, 6774,
     /* 434313 */     GIR_EraseRootFromParent_Done,
     /* 434314 */   // Label 8552: @434314
     /* 434314 */   GIM_Try, /*On fail goto*//*Label 8553*/ GIMT_Encode4(434398), // Rule ID 6806 //
     /* 434319 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434322 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434326 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434330 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434334 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434339 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 434343 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434347 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434351 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434355 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434360 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434364 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434368 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434372 */     // MIs[3] Operand 1
     /* 434372 */     // No operand predicates
     /* 434372 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434376 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434378 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rn), (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434378 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 434381 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434383 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434385 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 434389 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434393 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434396 */     GIR_RootConstrainSelectedInstOperands,
     /* 434397 */     // GIR_Coverage, 6806,
     /* 434397 */     GIR_EraseRootFromParent_Done,
     /* 434398 */   // Label 8553: @434398
     /* 434398 */   GIM_Try, /*On fail goto*//*Label 8554*/ GIMT_Encode4(434479), // Rule ID 6710 //
     /* 434403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434406 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434410 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434414 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434418 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434422 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 434426 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434430 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434434 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 434438 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434443 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 434447 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434451 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434455 */     // MIs[3] Operand 1
     /* 434455 */     // No operand predicates
     /* 434455 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434459 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 434461 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), FPR16:{ *:[f16] }:$Rd)  =>  (FMLSv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i16_indexed),
     /* 434464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434466 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434468 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 434474 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 434477 */     GIR_RootConstrainSelectedInstOperands,
     /* 434478 */     // GIR_Coverage, 6710,
     /* 434478 */     GIR_EraseRootFromParent_Done,
     /* 434479 */   // Label 8554: @434479
     /* 434479 */   GIM_Try, /*On fail goto*//*Label 8555*/ GIMT_Encode4(434564), // Rule ID 2490 //
     /* 434484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434487 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434491 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434495 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434499 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434503 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434508 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 434512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434516 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434520 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 434522 */     // (strict_fma:{ *:[f16] } (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rn, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 434522 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 434525 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 434529 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 434534 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rn
     /* 434540 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434545 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434550 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 434553 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434555 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 434558 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 434560 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 434562 */     GIR_RootConstrainSelectedInstOperands,
     /* 434563 */     // GIR_Coverage, 2490,
     /* 434563 */     GIR_EraseRootFromParent_Done,
     /* 434564 */   // Label 8555: @434564
     /* 434564 */   GIM_Try, /*On fail goto*//*Label 8556*/ GIMT_Encode4(434649), // Rule ID 2488 //
     /* 434569 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434572 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434576 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434580 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434584 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434588 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434592 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434597 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 434601 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434605 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 434607 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (extractelt:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, 0:{ *:[i64] }), FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (EXTRACT_SUBREG:{ *:[f16] } V128:{ *:[v8f16] }:$Rm, hsub:{ *:[i32] }), FPR16:{ *:[f16] }:$Ra)
     /* 434607 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 434610 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 434614 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 434619 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(9), // Rm
     /* 434625 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434630 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 434635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 434638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434640 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434642 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 434645 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 434647 */     GIR_RootConstrainSelectedInstOperands,
     /* 434648 */     // GIR_Coverage, 2488,
     /* 434648 */     GIR_EraseRootFromParent_Done,
     /* 434649 */   // Label 8556: @434649
     /* 434649 */   GIM_Try, /*On fail goto*//*Label 8557*/ GIMT_Encode4(434718), // Rule ID 2569 //
     /* 434654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434678 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434682 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434686 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434690 */     // MIs[2] Operand 1
     /* 434690 */     // No operand predicates
     /* 434690 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434694 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434698 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434700 */     // (strict_fma:{ *:[f16] } (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434700 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 434703 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434705 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434707 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434713 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434716 */     GIR_RootConstrainSelectedInstOperands,
     /* 434717 */     // GIR_Coverage, 2569,
     /* 434717 */     GIR_EraseRootFromParent_Done,
     /* 434718 */   // Label 8557: @434718
     /* 434718 */   GIM_Try, /*On fail goto*//*Label 8558*/ GIMT_Encode4(434787), // Rule ID 6678 //
     /* 434723 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 434726 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 434738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 434742 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 434746 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 434751 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 434755 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 434759 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 434763 */     // MIs[2] Operand 1
     /* 434763 */     // No operand predicates
     /* 434763 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434767 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 434769 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (vector_extract:{ *:[f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), FPR16:{ *:[f16] }:$Rd)  =>  (FMLAv1i16_indexed:{ *:[f16] } FPR16:{ *:[f16] }:$Rd, FPR16:{ *:[f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 434769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i16_indexed),
     /* 434772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 434774 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 434776 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 434785 */     GIR_RootConstrainSelectedInstOperands,
     /* 434786 */     // GIR_Coverage, 6678,
     /* 434786 */     GIR_EraseRootFromParent_Done,
     /* 434787 */   // Label 8558: @434787
     /* 434787 */   GIM_Try, /*On fail goto*//*Label 8559*/ GIMT_Encode4(434837), // Rule ID 14361 //
     /* 434792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 434799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434803 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434807 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434812 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434816 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434820 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 434822 */     // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 434822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 434825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434827 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 434829 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434833 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 434835 */     GIR_RootConstrainSelectedInstOperands,
     /* 434836 */     // GIR_Coverage, 14361,
     /* 434836 */     GIR_EraseRootFromParent_Done,
     /* 434837 */   // Label 8559: @434837
     /* 434837 */   GIM_Try, /*On fail goto*//*Label 8560*/ GIMT_Encode4(434887), // Rule ID 685 //
     /* 434842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434849 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 434853 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434857 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434861 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434866 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434870 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 434872 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Rm), FPR16:{ *:[f16] }:$Ra)  =>  (FMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 434872 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBHrrr),
     /* 434875 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434877 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 434883 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 434885 */     GIR_RootConstrainSelectedInstOperands,
     /* 434886 */     // GIR_Coverage, 685,
     /* 434886 */     GIR_EraseRootFromParent_Done,
     /* 434887 */   // Label 8560: @434887
     /* 434887 */   GIM_Try, /*On fail goto*//*Label 8561*/ GIMT_Encode4(434937), // Rule ID 697 //
     /* 434892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434895 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434899 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434903 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 434907 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 434911 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 434915 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434920 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 434922 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, (fneg:{ *:[f16] } FPR16:{ *:[f16] }:$Ra))  =>  (FNMSUBHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 434922 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBHrrr),
     /* 434925 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 434927 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 434929 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 434931 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 434935 */     GIR_RootConstrainSelectedInstOperands,
     /* 434936 */     // GIR_Coverage, 697,
     /* 434936 */     GIR_EraseRootFromParent_Done,
     /* 434937 */   // Label 8561: @434937
     /* 434937 */   GIM_Try, /*On fail goto*//*Label 8562*/ GIMT_Encode4(434968), // Rule ID 679 //
     /* 434942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 434945 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434949 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434953 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 434957 */     // (strict_fma:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)  =>  (FMADDHrrr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn, FPR16:{ *:[f16] }:$Rm, FPR16:{ *:[f16] }:$Ra)
     /* 434957 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDHrrr),
     /* 434962 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 434966 */     GIR_RootConstrainSelectedInstOperands,
     /* 434967 */     // GIR_Coverage, 679,
     /* 434967 */     GIR_Done,
     /* 434968 */   // Label 8562: @434968
     /* 434968 */   GIM_Reject,
     /* 434969 */ // Label 8534: @434969
     /* 434969 */ GIM_Reject,
     /* 434970 */ // Label 8526: @434970
     /* 434970 */ GIM_Try, /*On fail goto*//*Label 8563*/ GIMT_Encode4(437899),
     /* 434975 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 434978 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 434981 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 434984 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 434988 */   GIM_Try, /*On fail goto*//*Label 8564*/ GIMT_Encode4(435138), // Rule ID 4947 //
     /* 434993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 434996 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435000 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435004 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435008 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 435012 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435017 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 435021 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 435025 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435029 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435033 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 435037 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435042 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 435046 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 435050 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435054 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 435058 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435063 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 435065 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 435065 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 435068 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435072 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435077 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 435083 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435088 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435105 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435111 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435116 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 435124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 435126 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435129 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 435132 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 435136 */     GIR_RootConstrainSelectedInstOperands,
     /* 435137 */     // GIR_Coverage, 4947,
     /* 435137 */     GIR_EraseRootFromParent_Done,
     /* 435138 */   // Label 8564: @435138
     /* 435138 */   GIM_Try, /*On fail goto*//*Label 8565*/ GIMT_Encode4(435285), // Rule ID 4911 //
     /* 435143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 435146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435154 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435158 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 435162 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435167 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 435171 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 435175 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435179 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 435183 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 435187 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435191 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435195 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 435199 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435204 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 435208 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435212 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 435214 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 435214 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 435217 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435221 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435226 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 435232 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435237 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435242 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435245 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435249 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435254 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435260 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435265 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 435273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 435275 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435278 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 435281 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 435283 */     GIR_RootConstrainSelectedInstOperands,
     /* 435284 */     // GIR_Coverage, 4911,
     /* 435284 */     GIR_EraseRootFromParent_Done,
     /* 435285 */   // Label 8565: @435285
     /* 435285 */   GIM_Try, /*On fail goto*//*Label 8566*/ GIMT_Encode4(435432), // Rule ID 14885 //
     /* 435290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 435293 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435297 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435301 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 435305 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 435309 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435313 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435317 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 435321 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435326 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 435330 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 435334 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435338 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435342 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 435346 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435351 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 435355 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435359 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 435361 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 435361 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 435364 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435368 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435373 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 435379 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435384 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435389 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435392 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435396 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435401 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435407 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435412 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 435420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 435422 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435425 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 435428 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 435430 */     GIR_RootConstrainSelectedInstOperands,
     /* 435431 */     // GIR_Coverage, 14885,
     /* 435431 */     GIR_EraseRootFromParent_Done,
     /* 435432 */   // Label 8566: @435432
     /* 435432 */   GIM_Try, /*On fail goto*//*Label 8567*/ GIMT_Encode4(435563), // Rule ID 6728 //
     /* 435437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435440 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435444 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435448 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435452 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 435456 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435461 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 435465 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 435469 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435473 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 435477 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 435481 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435485 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435489 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 435493 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435498 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 435502 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 435506 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 435510 */     // MIs[4] Operand 1
     /* 435510 */     // No operand predicates
     /* 435510 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435514 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 435516 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 435516 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435519 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435523 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435528 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435534 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435539 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 435547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 435549 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 435551 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435554 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 435558 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 435561 */     GIR_RootConstrainSelectedInstOperands,
     /* 435562 */     // GIR_Coverage, 6728,
     /* 435562 */     GIR_EraseRootFromParent_Done,
     /* 435563 */   // Label 8567: @435563
     /* 435563 */   GIM_Try, /*On fail goto*//*Label 8568*/ GIMT_Encode4(435694), // Rule ID 6760 //
     /* 435568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435583 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 435587 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435592 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 435596 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 435600 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 435604 */     // MIs[2] Operand 1
     /* 435604 */     // No operand predicates
     /* 435604 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 435608 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435612 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 435616 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 435620 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435624 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435628 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 435632 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435637 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 435641 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435645 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 435647 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 435647 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435650 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435654 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435659 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435665 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435670 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 435678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 435680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 435682 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435685 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 435689 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 435692 */     GIR_RootConstrainSelectedInstOperands,
     /* 435693 */     // GIR_Coverage, 6760,
     /* 435693 */     GIR_EraseRootFromParent_Done,
     /* 435694 */   // Label 8568: @435694
     /* 435694 */   GIM_Try, /*On fail goto*//*Label 8569*/ GIMT_Encode4(435825), // Rule ID 6824 //
     /* 435699 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435702 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435706 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435710 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 435714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 435718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435722 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435726 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 435730 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435735 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 435739 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 435743 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435747 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435751 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 435755 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435760 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 435764 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 435768 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 435772 */     // MIs[4] Operand 1
     /* 435772 */     // No operand predicates
     /* 435772 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435776 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 435778 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 435778 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435781 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435785 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435790 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435796 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435801 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 435809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 435811 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 435813 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435816 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 435820 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 435823 */     GIR_RootConstrainSelectedInstOperands,
     /* 435824 */     // GIR_Coverage, 6824,
     /* 435824 */     GIR_EraseRootFromParent_Done,
     /* 435825 */   // Label 8569: @435825
     /* 435825 */   GIM_Try, /*On fail goto*//*Label 8570*/ GIMT_Encode4(435956), // Rule ID 6792 //
     /* 435830 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 435833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 435841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 435845 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 435849 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435853 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435857 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 435861 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435866 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 435870 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 435874 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 435878 */     // MIs[3] Operand 1
     /* 435878 */     // No operand predicates
     /* 435878 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 435882 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435886 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435890 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 435894 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435899 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 435903 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435907 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 435909 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 435909 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 435912 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 435916 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 435921 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 435927 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 435932 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 435940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 435942 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 435944 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 435947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 435951 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 435954 */     GIR_RootConstrainSelectedInstOperands,
     /* 435955 */     // GIR_Coverage, 6792,
     /* 435955 */     GIR_EraseRootFromParent_Done,
     /* 435956 */   // Label 8570: @435956
     /* 435956 */   GIM_Try, /*On fail goto*//*Label 8571*/ GIMT_Encode4(436091), // Rule ID 2498 //
     /* 435961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 435964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 435968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 435976 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 435980 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 435985 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 435989 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 435993 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 435997 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436001 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 436005 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436010 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 436014 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436018 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436020 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 436020 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 436023 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436027 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436032 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 436038 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436043 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436048 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436051 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436055 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436060 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436066 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436071 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436076 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 436079 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436081 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436084 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 436087 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 436089 */     GIR_RootConstrainSelectedInstOperands,
     /* 436090 */     // GIR_Coverage, 2498,
     /* 436090 */     GIR_EraseRootFromParent_Done,
     /* 436091 */   // Label 8571: @436091
     /* 436091 */   GIM_Try, /*On fail goto*//*Label 8572*/ GIMT_Encode4(436210), // Rule ID 6696 //
     /* 436096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436107 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436111 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436115 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436120 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 436124 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 436128 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436132 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436136 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 436140 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436145 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 436149 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 436153 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 436157 */     // MIs[3] Operand 1
     /* 436157 */     // No operand predicates
     /* 436157 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436161 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 436163 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 436163 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436166 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436170 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436175 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436181 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436186 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 436194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436196 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 436198 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436201 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 436205 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 436208 */     GIR_RootConstrainSelectedInstOperands,
     /* 436209 */     // GIR_Coverage, 6696,
     /* 436209 */     GIR_EraseRootFromParent_Done,
     /* 436210 */   // Label 8572: @436210
     /* 436210 */   GIM_Try, /*On fail goto*//*Label 8573*/ GIMT_Encode4(436329), // Rule ID 2587 //
     /* 436215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 436218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436234 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436239 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 436243 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 436247 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 436251 */     // MIs[2] Operand 1
     /* 436251 */     // No operand predicates
     /* 436251 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 436255 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436259 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436263 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 436267 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436272 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 436276 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436280 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 436282 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, (EXTRACT_SUBREG:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 436282 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436285 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436289 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436294 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436300 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436305 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 436313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 436317 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436320 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 436324 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 436327 */     GIR_RootConstrainSelectedInstOperands,
     /* 436328 */     // GIR_Coverage, 2587,
     /* 436328 */     GIR_EraseRootFromParent_Done,
     /* 436329 */   // Label 8573: @436329
     /* 436329 */   GIM_Try, /*On fail goto*//*Label 8574*/ GIMT_Encode4(436429), // Rule ID 4909 //
     /* 436334 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436337 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436341 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436345 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436349 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436353 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436358 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 436362 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 436366 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436370 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 436374 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436383 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436385 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 436385 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436388 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436392 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436397 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436403 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436408 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 436416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436418 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 436425 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 436427 */     GIR_RootConstrainSelectedInstOperands,
     /* 436428 */     // GIR_Coverage, 4909,
     /* 436428 */     GIR_EraseRootFromParent_Done,
     /* 436429 */   // Label 8574: @436429
     /* 436429 */   GIM_Try, /*On fail goto*//*Label 8575*/ GIMT_Encode4(436529), // Rule ID 4945 //
     /* 436434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436437 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436441 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436445 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436449 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436453 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436458 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 436462 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436466 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 436470 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436474 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 436478 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436483 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436485 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 436485 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436488 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436492 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436497 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436503 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436508 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 436516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436518 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436521 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 436523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 436527 */     GIR_RootConstrainSelectedInstOperands,
     /* 436528 */     // GIR_Coverage, 4945,
     /* 436528 */     GIR_EraseRootFromParent_Done,
     /* 436529 */   // Label 8575: @436529
     /* 436529 */   GIM_Try, /*On fail goto*//*Label 8576*/ GIMT_Encode4(436626), // Rule ID 14881 //
     /* 436534 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436537 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436541 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436545 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 436549 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 436553 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436557 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436561 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 436565 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436570 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 436574 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436578 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436582 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436584 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 436584 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436587 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436591 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436596 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 436602 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436607 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436612 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 436615 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436617 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 436619 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436622 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 436624 */     GIR_RootConstrainSelectedInstOperands,
     /* 436625 */     // GIR_Coverage, 14881,
     /* 436625 */     GIR_EraseRootFromParent_Done,
     /* 436626 */   // Label 8576: @436626
     /* 436626 */   GIM_Try, /*On fail goto*//*Label 8577*/ GIMT_Encode4(436726), // Rule ID 14883 //
     /* 436631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436634 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436638 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436642 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 436646 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436651 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 436655 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436659 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436663 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 436667 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436672 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 436676 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436680 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436682 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 436682 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436685 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436689 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436694 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 436700 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436705 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 436713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436715 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 436722 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 436724 */     GIR_RootConstrainSelectedInstOperands,
     /* 436725 */     // GIR_Coverage, 14883,
     /* 436725 */     GIR_EraseRootFromParent_Done,
     /* 436726 */   // Label 8577: @436726
     /* 436726 */   GIM_Try, /*On fail goto*//*Label 8578*/ GIMT_Encode4(436826), // Rule ID 4943 //
     /* 436731 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436734 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436738 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 436742 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436746 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436750 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436754 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436759 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 436763 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 436767 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436771 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 436775 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436780 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436782 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 436782 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436785 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436789 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436794 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 436800 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436805 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436810 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 436813 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436815 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 436817 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436820 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 436824 */     GIR_RootConstrainSelectedInstOperands,
     /* 436825 */     // GIR_Coverage, 4943,
     /* 436825 */     GIR_EraseRootFromParent_Done,
     /* 436826 */   // Label 8578: @436826
     /* 436826 */   GIM_Try, /*On fail goto*//*Label 8579*/ GIMT_Encode4(436923), // Rule ID 4907 //
     /* 436831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 436834 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436838 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 436842 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436846 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 436850 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 436854 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436858 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436862 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 436866 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436871 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 436875 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436879 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 436881 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] })), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 436881 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 436884 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 436888 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 436893 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 436899 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436904 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436909 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 436912 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 436914 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 436916 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 436919 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 436921 */     GIR_RootConstrainSelectedInstOperands,
     /* 436922 */     // GIR_Coverage, 4907,
     /* 436922 */     GIR_EraseRootFromParent_Done,
     /* 436923 */   // Label 8579: @436923
     /* 436923 */   GIM_Try, /*On fail goto*//*Label 8580*/ GIMT_Encode4(437001), // Rule ID 6846 //
     /* 436928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 436932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 436936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436940 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 436944 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 436948 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 436952 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 436956 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 436961 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 436965 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 436969 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 436973 */     // MIs[3] Operand 1
     /* 436973 */     // No operand predicates
     /* 436973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436977 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 436981 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 436983 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 436983 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 436986 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 436988 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 436990 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 436992 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 436996 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 436999 */     GIR_RootConstrainSelectedInstOperands,
     /* 437000 */     // GIR_Coverage, 6846,
     /* 437000 */     GIR_EraseRootFromParent_Done,
     /* 437001 */   // Label 8580: @437001
     /* 437001 */   GIM_Try, /*On fail goto*//*Label 8581*/ GIMT_Encode4(437085), // Rule ID 6758 //
     /* 437006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437009 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437013 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437017 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437021 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437025 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437030 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 437034 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437038 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437042 */     // MIs[2] Operand 1
     /* 437042 */     // No operand predicates
     /* 437042 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 437046 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437050 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
     /* 437054 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437059 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437063 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437065 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 437068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437070 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437072 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 437076 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 437080 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 437083 */     GIR_RootConstrainSelectedInstOperands,
     /* 437084 */     // GIR_Coverage, 6758,
     /* 437084 */     GIR_EraseRootFromParent_Done,
     /* 437085 */   // Label 8581: @437085
     /* 437085 */   GIM_Try, /*On fail goto*//*Label 8582*/ GIMT_Encode4(437166), // Rule ID 6790 //
     /* 437090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 437109 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437113 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437117 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437121 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437126 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 437130 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437134 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437138 */     // MIs[3] Operand 1
     /* 437138 */     // No operand predicates
     /* 437138 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437142 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437146 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437148 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 437151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437153 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437155 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 437157 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437161 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437164 */     GIR_RootConstrainSelectedInstOperands,
     /* 437165 */     // GIR_Coverage, 6790,
     /* 437165 */     GIR_EraseRootFromParent_Done,
     /* 437166 */   // Label 8582: @437166
     /* 437166 */   GIM_Try, /*On fail goto*//*Label 8583*/ GIMT_Encode4(437250), // Rule ID 6822 //
     /* 437171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437174 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437178 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437182 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437186 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437191 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 437195 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437199 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437203 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437207 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437212 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 437216 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437220 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437224 */     // MIs[3] Operand 1
     /* 437224 */     // No operand predicates
     /* 437224 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437228 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437230 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rn), (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437230 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 437233 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437235 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437237 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 437241 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437245 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437248 */     GIR_RootConstrainSelectedInstOperands,
     /* 437249 */     // GIR_Coverage, 6822,
     /* 437249 */     GIR_EraseRootFromParent_Done,
     /* 437250 */   // Label 8583: @437250
     /* 437250 */   GIM_Try, /*On fail goto*//*Label 8584*/ GIMT_Encode4(437328), // Rule ID 6868 //
     /* 437255 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 437263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437275 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 437279 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437283 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437287 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437292 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 437296 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437300 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437304 */     // MIs[3] Operand 1
     /* 437304 */     // No operand predicates
     /* 437304 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437308 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437310 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 437313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437315 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437317 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437319 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437323 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437326 */     GIR_RootConstrainSelectedInstOperands,
     /* 437327 */     // GIR_Coverage, 6868,
     /* 437327 */     GIR_EraseRootFromParent_Done,
     /* 437328 */   // Label 8584: @437328
     /* 437328 */   GIM_Try, /*On fail goto*//*Label 8585*/ GIMT_Encode4(437409), // Rule ID 6726 //
     /* 437333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437336 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437340 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 437344 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437348 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437352 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 437356 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437360 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437364 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437368 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437373 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 437377 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437381 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437385 */     // MIs[3] Operand 1
     /* 437385 */     // No operand predicates
     /* 437385 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437389 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437391 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), FPR32:{ *:[f32] }:$Rd)  =>  (FMLSv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i32_indexed),
     /* 437394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437396 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437398 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 437404 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 437407 */     GIR_RootConstrainSelectedInstOperands,
     /* 437408 */     // GIR_Coverage, 6726,
     /* 437408 */     GIR_EraseRootFromParent_Done,
     /* 437409 */   // Label 8585: @437409
     /* 437409 */   GIM_Try, /*On fail goto*//*Label 8586*/ GIMT_Encode4(437494), // Rule ID 2496 //
     /* 437414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437417 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437421 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437425 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437429 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437433 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437438 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 437442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437450 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437452 */     // (strict_fma:{ *:[f32] } (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rn, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 437452 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 437455 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 437459 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437464 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rn
     /* 437470 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437475 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 437483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 437485 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437488 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 437490 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 437492 */     GIR_RootConstrainSelectedInstOperands,
     /* 437493 */     // GIR_Coverage, 2496,
     /* 437493 */     GIR_EraseRootFromParent_Done,
     /* 437494 */   // Label 8586: @437494
     /* 437494 */   GIM_Try, /*On fail goto*//*Label 8587*/ GIMT_Encode4(437579), // Rule ID 2494 //
     /* 437499 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437502 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437506 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 437510 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437514 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437518 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437522 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437527 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 437531 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437535 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437537 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (extractelt:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, 0:{ *:[i64] }), FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (EXTRACT_SUBREG:{ *:[i32] } V128:{ *:[v4f32] }:$Rm, ssub:{ *:[i32] }), FPR32:{ *:[f32] }:$Ra)
     /* 437537 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 437540 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 437544 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 437549 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(18), // Rm
     /* 437555 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437560 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 437568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 437570 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437572 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 437575 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 437577 */     GIR_RootConstrainSelectedInstOperands,
     /* 437578 */     // GIR_Coverage, 2494,
     /* 437578 */     GIR_EraseRootFromParent_Done,
     /* 437579 */   // Label 8587: @437579
     /* 437579 */   GIM_Try, /*On fail goto*//*Label 8588*/ GIMT_Encode4(437648), // Rule ID 2585 //
     /* 437584 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437587 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437591 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437595 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437599 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437603 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437608 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 437612 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437616 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437620 */     // MIs[2] Operand 1
     /* 437620 */     // No operand predicates
     /* 437620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437624 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437628 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 437630 */     // (strict_fma:{ *:[f32] } (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437630 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 437633 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437635 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437637 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 437639 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 437643 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 437646 */     GIR_RootConstrainSelectedInstOperands,
     /* 437647 */     // GIR_Coverage, 2585,
     /* 437647 */     GIR_EraseRootFromParent_Done,
     /* 437648 */   // Label 8588: @437648
     /* 437648 */   GIM_Try, /*On fail goto*//*Label 8589*/ GIMT_Encode4(437717), // Rule ID 6694 //
     /* 437653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 437656 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437660 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 437664 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437668 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 437672 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437676 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437681 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 437685 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 437689 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 437693 */     // MIs[2] Operand 1
     /* 437693 */     // No operand predicates
     /* 437693 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437697 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 437699 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (vector_extract:{ *:[f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR32:{ *:[f32] }:$Rd)  =>  (FMLAv1i32_indexed:{ *:[f32] } FPR32:{ *:[f32] }:$Rd, FPR32:{ *:[f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 437699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i32_indexed),
     /* 437702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 437704 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 437706 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437708 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 437712 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 437715 */     GIR_RootConstrainSelectedInstOperands,
     /* 437716 */     // GIR_Coverage, 6694,
     /* 437716 */     GIR_EraseRootFromParent_Done,
     /* 437717 */   // Label 8589: @437717
     /* 437717 */   GIM_Try, /*On fail goto*//*Label 8590*/ GIMT_Encode4(437767), // Rule ID 14363 //
     /* 437722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437725 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437729 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437733 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437737 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437742 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437746 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437750 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437752 */     // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 437752 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 437755 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 437757 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 437759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 437763 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 437765 */     GIR_RootConstrainSelectedInstOperands,
     /* 437766 */     // GIR_Coverage, 14363,
     /* 437766 */     GIR_EraseRootFromParent_Done,
     /* 437767 */   // Label 8590: @437767
     /* 437767 */   GIM_Try, /*On fail goto*//*Label 8591*/ GIMT_Encode4(437817), // Rule ID 687 //
     /* 437772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437775 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437779 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 437783 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437787 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437791 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437796 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437800 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437802 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Rm), FPR32:{ *:[f32] }:$Ra)  =>  (FMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 437802 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBSrrr),
     /* 437805 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 437807 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437809 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 437813 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 437815 */     GIR_RootConstrainSelectedInstOperands,
     /* 437816 */     // GIR_Coverage, 687,
     /* 437816 */     GIR_EraseRootFromParent_Done,
     /* 437817 */   // Label 8591: @437817
     /* 437817 */   GIM_Try, /*On fail goto*//*Label 8592*/ GIMT_Encode4(437867), // Rule ID 699 //
     /* 437822 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437825 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437829 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437833 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 437837 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437841 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 437845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437850 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 437852 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$Ra))  =>  (FNMSUBSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 437852 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBSrrr),
     /* 437855 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 437857 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 437859 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 437861 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 437865 */     GIR_RootConstrainSelectedInstOperands,
     /* 437866 */     // GIR_Coverage, 699,
     /* 437866 */     GIR_EraseRootFromParent_Done,
     /* 437867 */   // Label 8592: @437867
     /* 437867 */   GIM_Try, /*On fail goto*//*Label 8593*/ GIMT_Encode4(437898), // Rule ID 681 //
     /* 437872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437883 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 437887 */     // (strict_fma:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)  =>  (FMADDSrrr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm, FPR32:{ *:[f32] }:$Ra)
     /* 437887 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDSrrr),
     /* 437892 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 437896 */     GIR_RootConstrainSelectedInstOperands,
     /* 437897 */     // GIR_Coverage, 681,
     /* 437897 */     GIR_Done,
     /* 437898 */   // Label 8593: @437898
     /* 437898 */   GIM_Reject,
     /* 437899 */ // Label 8563: @437899
     /* 437899 */ GIM_Reject,
     /* 437900 */ // Label 8527: @437900
     /* 437900 */ GIM_Try, /*On fail goto*//*Label 8594*/ GIMT_Encode4(440829),
     /* 437905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 437908 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 437911 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 437914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437918 */   GIM_Try, /*On fail goto*//*Label 8595*/ GIMT_Encode4(438068), // Rule ID 4953 //
     /* 437923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 437926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 437930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437934 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 437938 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 437942 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437947 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 437951 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 437955 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 437959 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 437963 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 437967 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 437972 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 437976 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 437980 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 437984 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 437988 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 437993 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 437995 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 437995 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 437998 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438002 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438007 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 438013 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438018 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438023 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438026 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438030 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438035 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438041 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438046 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 438054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438056 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438059 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 438062 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Ra
     /* 438066 */     GIR_RootConstrainSelectedInstOperands,
     /* 438067 */     // GIR_Coverage, 4953,
     /* 438067 */     GIR_EraseRootFromParent_Done,
     /* 438068 */   // Label 8595: @438068
     /* 438068 */   GIM_Try, /*On fail goto*//*Label 8596*/ GIMT_Encode4(438215), // Rule ID 4917 //
     /* 438073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 438076 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438080 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438084 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438088 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438092 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438097 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 438101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 438105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438109 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 438113 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 438117 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438121 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438125 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 438129 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438134 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 438138 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438142 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438144 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 438144 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 438147 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438151 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438156 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 438162 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438167 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438172 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438175 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438179 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438184 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438190 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438195 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 438203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438205 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438208 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 438211 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 438213 */     GIR_RootConstrainSelectedInstOperands,
     /* 438214 */     // GIR_Coverage, 4917,
     /* 438214 */     GIR_EraseRootFromParent_Done,
     /* 438215 */   // Label 8596: @438215
     /* 438215 */   GIM_Try, /*On fail goto*//*Label 8597*/ GIMT_Encode4(438362), // Rule ID 14891 //
     /* 438220 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 438223 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438227 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438231 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 438235 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438239 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438243 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438247 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438251 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438256 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 438260 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 438264 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438268 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438272 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 438276 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438281 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 438285 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438289 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 438291 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 438291 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 438294 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438298 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438303 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 438309 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438314 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438319 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438322 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438326 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438331 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438337 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438342 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 438350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 438352 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438355 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 438358 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 438360 */     GIR_RootConstrainSelectedInstOperands,
     /* 438361 */     // GIR_Coverage, 14891,
     /* 438361 */     GIR_EraseRootFromParent_Done,
     /* 438362 */   // Label 8597: @438362
     /* 438362 */   GIM_Try, /*On fail goto*//*Label 8598*/ GIMT_Encode4(438493), // Rule ID 6732 //
     /* 438367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438374 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438378 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438382 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438391 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 438395 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 438399 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438403 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 438407 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 438411 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438415 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438419 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 438423 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438428 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 438432 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438436 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 438440 */     // MIs[4] Operand 1
     /* 438440 */     // No operand predicates
     /* 438440 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438444 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 438446 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 438446 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438449 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438453 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438458 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438464 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438469 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438474 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 438477 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 438479 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 438481 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438484 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 438488 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 438491 */     GIR_RootConstrainSelectedInstOperands,
     /* 438492 */     // GIR_Coverage, 6732,
     /* 438492 */     GIR_EraseRootFromParent_Done,
     /* 438493 */   // Label 8598: @438493
     /* 438493 */   GIM_Try, /*On fail goto*//*Label 8599*/ GIMT_Encode4(438624), // Rule ID 6764 //
     /* 438498 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438501 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438505 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438509 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438513 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438517 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438522 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 438526 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438530 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 438534 */     // MIs[2] Operand 1
     /* 438534 */     // No operand predicates
     /* 438534 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 438538 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438542 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 438546 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
     /* 438550 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438554 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438558 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 438562 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438567 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 438571 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438575 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 438577 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 438577 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438580 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438584 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438589 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438595 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438600 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438605 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 438608 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 438610 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 438612 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 438619 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 438622 */     GIR_RootConstrainSelectedInstOperands,
     /* 438623 */     // GIR_Coverage, 6764,
     /* 438623 */     GIR_EraseRootFromParent_Done,
     /* 438624 */   // Label 8599: @438624
     /* 438624 */   GIM_Try, /*On fail goto*//*Label 8600*/ GIMT_Encode4(438755), // Rule ID 6828 //
     /* 438629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438632 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438636 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438640 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 438644 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438648 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438652 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438656 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438660 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438665 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 438669 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 438673 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438677 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438681 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 438685 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438690 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 438694 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438698 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 438702 */     // MIs[4] Operand 1
     /* 438702 */     // No operand predicates
     /* 438702 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438706 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 438708 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] })), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 438708 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438711 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438715 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438720 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438726 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438731 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 438739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 438741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 438743 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
     /* 438750 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // idx
     /* 438753 */     GIR_RootConstrainSelectedInstOperands,
     /* 438754 */     // GIR_Coverage, 6828,
     /* 438754 */     GIR_EraseRootFromParent_Done,
     /* 438755 */   // Label 8600: @438755
     /* 438755 */   GIM_Try, /*On fail goto*//*Label 8601*/ GIMT_Encode4(438886), // Rule ID 6796 //
     /* 438760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 438763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 438771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 438775 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 438779 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438783 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438787 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438791 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438796 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 438800 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 438804 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 438808 */     // MIs[3] Operand 1
     /* 438808 */     // No operand predicates
     /* 438808 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
     /* 438812 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438816 */     GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438820 */     GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s64,
     /* 438824 */     GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438829 */     GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 0,
     /* 438833 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438837 */     GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 438839 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 438839 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438842 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438846 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438851 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/4, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438857 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438862 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 438870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 438872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 438874 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 438877 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 438881 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 438884 */     GIR_RootConstrainSelectedInstOperands,
     /* 438885 */     // GIR_Coverage, 6796,
     /* 438885 */     GIR_EraseRootFromParent_Done,
     /* 438886 */   // Label 8601: @438886
     /* 438886 */   GIM_Try, /*On fail goto*//*Label 8602*/ GIMT_Encode4(439021), // Rule ID 2504 //
     /* 438891 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 438894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 438898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438906 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 438910 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438915 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 438919 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 438923 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 438927 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 438931 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 438935 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438940 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 438944 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438948 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 438950 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 438950 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 438953 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438957 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438962 */     GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 438968 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 438973 */     GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 438978 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 438981 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 438985 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 438990 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 438996 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439001 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 439009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439011 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439014 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 439017 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 439019 */     GIR_RootConstrainSelectedInstOperands,
     /* 439020 */     // GIR_Coverage, 2504,
     /* 439020 */     GIR_EraseRootFromParent_Done,
     /* 439021 */   // Label 8602: @439021
     /* 439021 */   GIM_Try, /*On fail goto*//*Label 8603*/ GIMT_Encode4(439140), // Rule ID 6700 //
     /* 439026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439029 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439033 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439037 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439041 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439045 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439050 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 439054 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 439058 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439062 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439066 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 439070 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439075 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 439079 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439083 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 439087 */     // MIs[3] Operand 1
     /* 439087 */     // No operand predicates
     /* 439087 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439091 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 439093 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 439093 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439096 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439100 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439105 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 439111 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439116 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 439124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 439126 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 439128 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 439135 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 439138 */     GIR_RootConstrainSelectedInstOperands,
     /* 439139 */     // GIR_Coverage, 6700,
     /* 439139 */     GIR_EraseRootFromParent_Done,
     /* 439140 */   // Label 8603: @439140
     /* 439140 */   GIM_Try, /*On fail goto*//*Label 8604*/ GIMT_Encode4(439259), // Rule ID 2591 //
     /* 439145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439160 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439164 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439169 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 439173 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439177 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 439181 */     // MIs[2] Operand 1
     /* 439181 */     // No operand predicates
     /* 439181 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 439185 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439189 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439193 */     GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 439197 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439202 */     GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 0,
     /* 439206 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439210 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 439212 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, (EXTRACT_SUBREG:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 439212 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439215 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439219 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439224 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 439230 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439235 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 439243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 439245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 439247 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439250 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 439254 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 439257 */     GIR_RootConstrainSelectedInstOperands,
     /* 439258 */     // GIR_Coverage, 2591,
     /* 439258 */     GIR_EraseRootFromParent_Done,
     /* 439259 */   // Label 8604: @439259
     /* 439259 */   GIM_Try, /*On fail goto*//*Label 8605*/ GIMT_Encode4(439359), // Rule ID 4915 //
     /* 439264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439267 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439271 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439275 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439279 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439283 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439288 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 439292 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 439296 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439300 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 439304 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439309 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439313 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439315 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 439315 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439318 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439322 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439327 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 439333 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439338 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 439346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439348 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439351 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 439355 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 439357 */     GIR_RootConstrainSelectedInstOperands,
     /* 439358 */     // GIR_Coverage, 4915,
     /* 439358 */     GIR_EraseRootFromParent_Done,
     /* 439359 */   // Label 8605: @439359
     /* 439359 */   GIM_Try, /*On fail goto*//*Label 8606*/ GIMT_Encode4(439459), // Rule ID 4951 //
     /* 439364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439379 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439383 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439388 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 439392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439396 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 439400 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439404 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 439408 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439413 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439415 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 439415 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439418 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439422 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439427 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 439433 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439438 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439443 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 439446 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439448 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439451 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 439453 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 439457 */     GIR_RootConstrainSelectedInstOperands,
     /* 439458 */     // GIR_Coverage, 4951,
     /* 439458 */     GIR_EraseRootFromParent_Done,
     /* 439459 */   // Label 8606: @439459
     /* 439459 */   GIM_Try, /*On fail goto*//*Label 8607*/ GIMT_Encode4(439556), // Rule ID 14887 //
     /* 439464 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439467 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439471 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439475 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 439479 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 439483 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439487 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439491 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 439495 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439500 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 439504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439508 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439512 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439514 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 439514 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439517 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439521 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439526 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 439532 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439537 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 439545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439547 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 439549 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439552 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 439554 */     GIR_RootConstrainSelectedInstOperands,
     /* 439555 */     // GIR_Coverage, 14887,
     /* 439555 */     GIR_EraseRootFromParent_Done,
     /* 439556 */   // Label 8607: @439556
     /* 439556 */   GIM_Try, /*On fail goto*//*Label 8608*/ GIMT_Encode4(439656), // Rule ID 14889 //
     /* 439561 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439564 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439568 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439572 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 439576 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439581 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 439585 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439589 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439593 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 439597 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439602 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 439606 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439610 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439612 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 439612 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439615 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439619 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439624 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 439630 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439635 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 439643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439645 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439648 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 439652 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 439654 */     GIR_RootConstrainSelectedInstOperands,
     /* 439655 */     // GIR_Coverage, 14889,
     /* 439655 */     GIR_EraseRootFromParent_Done,
     /* 439656 */   // Label 8608: @439656
     /* 439656 */   GIM_Try, /*On fail goto*//*Label 8609*/ GIMT_Encode4(439756), // Rule ID 4949 //
     /* 439661 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439664 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439668 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 439672 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439676 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439680 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439684 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439689 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 439693 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
     /* 439697 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439701 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 439705 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439710 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439712 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 439712 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439715 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439719 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439724 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 439730 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439735 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 439743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439745 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 439747 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ra
     /* 439754 */     GIR_RootConstrainSelectedInstOperands,
     /* 439755 */     // GIR_Coverage, 4949,
     /* 439755 */     GIR_EraseRootFromParent_Done,
     /* 439756 */   // Label 8609: @439756
     /* 439756 */   GIM_Try, /*On fail goto*//*Label 8610*/ GIMT_Encode4(439853), // Rule ID 4913 //
     /* 439761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 439764 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 439772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439776 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 439780 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 439784 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439788 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439792 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 439796 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439801 */     GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 0,
     /* 439805 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439809 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 439811 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] })), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 439811 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 439814 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 439818 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 439823 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 439829 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439834 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439839 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 439842 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 439844 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 439846 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 439849 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 439851 */     GIR_RootConstrainSelectedInstOperands,
     /* 439852 */     // GIR_Coverage, 4913,
     /* 439852 */     GIR_EraseRootFromParent_Done,
     /* 439853 */   // Label 8610: @439853
     /* 439853 */   GIM_Try, /*On fail goto*//*Label 8611*/ GIMT_Encode4(439931), // Rule ID 6850 //
     /* 439858 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439862 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439866 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439870 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439874 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 439878 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439882 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439886 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439891 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 439895 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439899 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 439903 */     // MIs[3] Operand 1
     /* 439903 */     // No operand predicates
     /* 439903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439907 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439911 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 439913 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 439913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 439916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 439918 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 439920 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 439922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 439926 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 439929 */     GIR_RootConstrainSelectedInstOperands,
     /* 439930 */     // GIR_Coverage, 6850,
     /* 439930 */     GIR_EraseRootFromParent_Done,
     /* 439931 */   // Label 8611: @439931
     /* 439931 */   GIM_Try, /*On fail goto*//*Label 8612*/ GIMT_Encode4(440015), // Rule ID 6762 //
     /* 439936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 439939 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 439943 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 439947 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 439951 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 439955 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 439960 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 439964 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 439968 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 439972 */     // MIs[2] Operand 1
     /* 439972 */     // No operand predicates
     /* 439972 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 439976 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 439980 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 439984 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439989 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 439993 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 439995 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 439995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 439998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440000 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 440006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 440010 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 440013 */     GIR_RootConstrainSelectedInstOperands,
     /* 440014 */     // GIR_Coverage, 6762,
     /* 440014 */     GIR_EraseRootFromParent_Done,
     /* 440015 */   // Label 8612: @440015
     /* 440015 */   GIM_Try, /*On fail goto*//*Label 8613*/ GIMT_Encode4(440096), // Rule ID 6794 //
     /* 440020 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440023 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440027 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440031 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440035 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 440039 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440043 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440047 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 440051 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440056 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 440060 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440064 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 440068 */     // MIs[3] Operand 1
     /* 440068 */     // No operand predicates
     /* 440068 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440072 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440076 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440078 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 440078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 440081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440083 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440085 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 440087 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 440091 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 440094 */     GIR_RootConstrainSelectedInstOperands,
     /* 440095 */     // GIR_Coverage, 6794,
     /* 440095 */     GIR_EraseRootFromParent_Done,
     /* 440096 */   // Label 8613: @440096
     /* 440096 */   GIM_Try, /*On fail goto*//*Label 8614*/ GIMT_Encode4(440180), // Rule ID 6826 //
     /* 440101 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440104 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440108 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440112 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440116 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 440125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440129 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440133 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 440137 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440142 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 440146 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440150 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 440154 */     // MIs[3] Operand 1
     /* 440154 */     // No operand predicates
     /* 440154 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440158 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440160 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rn), (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 440160 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 440163 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440165 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440167 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 440171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 440175 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 440178 */     GIR_RootConstrainSelectedInstOperands,
     /* 440179 */     // GIR_Coverage, 6826,
     /* 440179 */     GIR_EraseRootFromParent_Done,
     /* 440180 */   // Label 8614: @440180
     /* 440180 */   GIM_Try, /*On fail goto*//*Label 8615*/ GIMT_Encode4(440258), // Rule ID 6872 //
     /* 440185 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440189 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440193 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440197 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440201 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440205 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 440209 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440213 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440217 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440222 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 440226 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440230 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 440234 */     // MIs[3] Operand 1
     /* 440234 */     // No operand predicates
     /* 440234 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440238 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440240 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 440240 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 440243 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440245 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440247 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440249 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 440253 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 440256 */     GIR_RootConstrainSelectedInstOperands,
     /* 440257 */     // GIR_Coverage, 6872,
     /* 440257 */     GIR_EraseRootFromParent_Done,
     /* 440258 */   // Label 8615: @440258
     /* 440258 */   GIM_Try, /*On fail goto*//*Label 8616*/ GIMT_Encode4(440339), // Rule ID 6730 //
     /* 440263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440266 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440270 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440274 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440278 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440282 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 440286 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440290 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440294 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 440298 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440303 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 440307 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440311 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 440315 */     // MIs[3] Operand 1
     /* 440315 */     // No operand predicates
     /* 440315 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440319 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440321 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), FPR64:{ *:[f64] }:$Rd)  =>  (FMLSv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 440321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv1i64_indexed),
     /* 440324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440326 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440328 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440330 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 440334 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 440337 */     GIR_RootConstrainSelectedInstOperands,
     /* 440338 */     // GIR_Coverage, 6730,
     /* 440338 */     GIR_EraseRootFromParent_Done,
     /* 440339 */   // Label 8616: @440339
     /* 440339 */   GIM_Try, /*On fail goto*//*Label 8617*/ GIMT_Encode4(440424), // Rule ID 2502 //
     /* 440344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440347 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440351 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440355 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440359 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440363 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440368 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 440372 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440376 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440380 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440382 */     // (strict_fma:{ *:[f64] } (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rn, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 440382 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 440385 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 440389 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 440394 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rn
     /* 440400 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440405 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 440413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440415 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 440418 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 440420 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 440422 */     GIR_RootConstrainSelectedInstOperands,
     /* 440423 */     // GIR_Coverage, 2502,
     /* 440423 */     GIR_EraseRootFromParent_Done,
     /* 440424 */   // Label 8617: @440424
     /* 440424 */   GIM_Try, /*On fail goto*//*Label 8618*/ GIMT_Encode4(440509), // Rule ID 2500 //
     /* 440429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440432 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440436 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440440 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440444 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440448 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440452 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440457 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 0,
     /* 440461 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440465 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440467 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (extractelt:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, 0:{ *:[i64] }), FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (EXTRACT_SUBREG:{ *:[i64] } V128:{ *:[v2f64] }:$Rm, dsub:{ *:[i32] }), FPR64:{ *:[f64] }:$Ra)
     /* 440467 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 440470 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 440474 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 440479 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // Rm
     /* 440485 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440490 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 440498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440500 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440502 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 440505 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 440507 */     GIR_RootConstrainSelectedInstOperands,
     /* 440508 */     // GIR_Coverage, 2500,
     /* 440508 */     GIR_EraseRootFromParent_Done,
     /* 440509 */   // Label 8618: @440509
     /* 440509 */   GIM_Try, /*On fail goto*//*Label 8619*/ GIMT_Encode4(440578), // Rule ID 2589 //
     /* 440514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440517 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440521 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440525 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440529 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440533 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440538 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 440542 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440546 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 440550 */     // MIs[2] Operand 1
     /* 440550 */     // No operand predicates
     /* 440550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440554 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440558 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 440560 */     // (strict_fma:{ *:[f64] } (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 440560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 440563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440565 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440567 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 440569 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 440573 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 440576 */     GIR_RootConstrainSelectedInstOperands,
     /* 440577 */     // GIR_Coverage, 2589,
     /* 440577 */     GIR_EraseRootFromParent_Done,
     /* 440578 */   // Label 8619: @440578
     /* 440578 */   GIM_Try, /*On fail goto*//*Label 8620*/ GIMT_Encode4(440647), // Rule ID 6698 //
     /* 440583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440586 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440590 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440594 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_VECTOR_ELT),
     /* 440598 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 440602 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440606 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440611 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 440615 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440619 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 440623 */     // MIs[2] Operand 1
     /* 440623 */     // No operand predicates
     /* 440623 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440627 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 440629 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (vector_extract:{ *:[f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), FPR64:{ *:[f64] }:$Rd)  =>  (FMLAv1i64_indexed:{ *:[f64] } FPR64:{ *:[f64] }:$Rd, FPR64:{ *:[f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)
     /* 440629 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv1i64_indexed),
     /* 440632 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440634 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440636 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 440642 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 440645 */     GIR_RootConstrainSelectedInstOperands,
     /* 440646 */     // GIR_Coverage, 6698,
     /* 440646 */     GIR_EraseRootFromParent_Done,
     /* 440647 */   // Label 8620: @440647
     /* 440647 */   GIM_Try, /*On fail goto*//*Label 8621*/ GIMT_Encode4(440697), // Rule ID 14365 //
     /* 440652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440663 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440667 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440672 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440676 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440680 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440682 */     // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 440682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 440685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440687 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 440689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 440693 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 440695 */     GIR_RootConstrainSelectedInstOperands,
     /* 440696 */     // GIR_Coverage, 14365,
     /* 440696 */     GIR_EraseRootFromParent_Done,
     /* 440697 */   // Label 8621: @440697
     /* 440697 */   GIM_Try, /*On fail goto*//*Label 8622*/ GIMT_Encode4(440747), // Rule ID 689 //
     /* 440702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440705 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 440713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440721 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440726 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440730 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440732 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Rm), FPR64:{ *:[f64] }:$Ra)  =>  (FMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 440732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMSUBDrrr),
     /* 440735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440737 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440739 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 440743 */     GIR_RootToRootCopy, /*OpIdx*/3, // Ra
     /* 440745 */     GIR_RootConstrainSelectedInstOperands,
     /* 440746 */     // GIR_Coverage, 689,
     /* 440746 */     GIR_EraseRootFromParent_Done,
     /* 440747 */   // Label 8622: @440747
     /* 440747 */   GIM_Try, /*On fail goto*//*Label 8623*/ GIMT_Encode4(440797), // Rule ID 701 //
     /* 440752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440755 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440759 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 440767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 440775 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440780 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 440782 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$Ra))  =>  (FNMSUBDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 440782 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FNMSUBDrrr),
     /* 440785 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 440787 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 440789 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 440791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ra
     /* 440795 */     GIR_RootConstrainSelectedInstOperands,
     /* 440796 */     // GIR_Coverage, 701,
     /* 440796 */     GIR_EraseRootFromParent_Done,
     /* 440797 */   // Label 8623: @440797
     /* 440797 */   GIM_Try, /*On fail goto*//*Label 8624*/ GIMT_Encode4(440828), // Rule ID 683 //
     /* 440802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 440805 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440809 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440817 */     // (strict_fma:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)  =>  (FMADDDrrr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm, FPR64:{ *:[f64] }:$Ra)
     /* 440817 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMADDDrrr),
     /* 440822 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 440826 */     GIR_RootConstrainSelectedInstOperands,
     /* 440827 */     // GIR_Coverage, 683,
     /* 440827 */     GIR_Done,
     /* 440828 */   // Label 8624: @440828
     /* 440828 */   GIM_Reject,
     /* 440829 */ // Label 8594: @440829
     /* 440829 */ GIM_Reject,
     /* 440830 */ // Label 8528: @440830
     /* 440830 */ GIM_Try, /*On fail goto*//*Label 8625*/ GIMT_Encode4(442350),
     /* 440835 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 440838 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 440841 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 440844 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440848 */   GIM_Try, /*On fail goto*//*Label 8626*/ GIMT_Encode4(440926), // Rule ID 6830 //
     /* 440853 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440857 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 440861 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 440865 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440869 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 440873 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440877 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 440881 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440886 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 440890 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440894 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 440898 */     // MIs[3] Operand 1
     /* 440898 */     // No operand predicates
     /* 440898 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440902 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440906 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440908 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 440908 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 440911 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440913 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440915 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 440917 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 440921 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 440924 */     GIR_RootConstrainSelectedInstOperands,
     /* 440925 */     // GIR_Coverage, 6830,
     /* 440925 */     GIR_EraseRootFromParent_Done,
     /* 440926 */   // Label 8626: @440926
     /* 440926 */   GIM_Try, /*On fail goto*//*Label 8627*/ GIMT_Encode4(441010), // Rule ID 6746 //
     /* 440931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 440934 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 440938 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 440942 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 440946 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 440950 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 440955 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 440959 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 440963 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 440967 */     // MIs[2] Operand 1
     /* 440967 */     // No operand predicates
     /* 440967 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 440971 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 440975 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 440979 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440984 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 440988 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 440990 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 440990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 440993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 440995 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 440997 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 441001 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 441005 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 441008 */     GIR_RootConstrainSelectedInstOperands,
     /* 441009 */     // GIR_Coverage, 6746,
     /* 441009 */     GIR_EraseRootFromParent_Done,
     /* 441010 */   // Label 8627: @441010
     /* 441010 */   GIM_Try, /*On fail goto*//*Label 8628*/ GIMT_Encode4(441091), // Rule ID 6778 //
     /* 441015 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441018 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441022 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441026 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441030 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441034 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441038 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441042 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 441046 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441051 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 441055 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441059 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441063 */     // MIs[3] Operand 1
     /* 441063 */     // No operand predicates
     /* 441063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441071 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 441073 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441078 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441080 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 441082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441086 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 441089 */     GIR_RootConstrainSelectedInstOperands,
     /* 441090 */     // GIR_Coverage, 6778,
     /* 441090 */     GIR_EraseRootFromParent_Done,
     /* 441091 */   // Label 8628: @441091
     /* 441091 */   GIM_Try, /*On fail goto*//*Label 8629*/ GIMT_Encode4(441175), // Rule ID 6810 //
     /* 441096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441107 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441111 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441116 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 441120 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441124 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441128 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 441132 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441137 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 441141 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441145 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441149 */     // MIs[3] Operand 1
     /* 441149 */     // No operand predicates
     /* 441149 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441153 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 441155 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441160 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 441166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441170 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 441173 */     GIR_RootConstrainSelectedInstOperands,
     /* 441174 */     // GIR_Coverage, 6810,
     /* 441174 */     GIR_EraseRootFromParent_Done,
     /* 441175 */   // Label 8629: @441175
     /* 441175 */   GIM_Try, /*On fail goto*//*Label 8630*/ GIMT_Encode4(441253), // Rule ID 6852 //
     /* 441180 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441192 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441196 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 441200 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441204 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441208 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441212 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441217 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 441221 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441225 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441229 */     // MIs[3] Operand 1
     /* 441229 */     // No operand predicates
     /* 441229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441233 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 441235 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441235 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441238 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441240 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441242 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441244 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441248 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 441251 */     GIR_RootConstrainSelectedInstOperands,
     /* 441252 */     // GIR_Coverage, 6852,
     /* 441252 */     GIR_EraseRootFromParent_Done,
     /* 441253 */   // Label 8630: @441253
     /* 441253 */   GIM_Try, /*On fail goto*//*Label 8631*/ GIMT_Encode4(441334), // Rule ID 6714 //
     /* 441258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441261 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441265 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441269 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441273 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441277 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441281 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441285 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441289 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 441293 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441298 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 441302 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441306 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441310 */     // MIs[3] Operand 1
     /* 441310 */     // No operand predicates
     /* 441310 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441314 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 441316 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441321 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441323 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441325 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441329 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 441332 */     GIR_RootConstrainSelectedInstOperands,
     /* 441333 */     // GIR_Coverage, 6714,
     /* 441333 */     GIR_EraseRootFromParent_Done,
     /* 441334 */   // Label 8631: @441334
     /* 441334 */   GIM_Try, /*On fail goto*//*Label 8632*/ GIMT_Encode4(441403), // Rule ID 2573 //
     /* 441339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441342 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441346 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441350 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441354 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 441358 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441363 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 441367 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441371 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441375 */     // MIs[2] Operand 1
     /* 441375 */     // No operand predicates
     /* 441375 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441383 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441385 */     // (strict_fma:{ *:[v2f32] } (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 441388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441390 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441392 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 441394 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 441398 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 441401 */     GIR_RootConstrainSelectedInstOperands,
     /* 441402 */     // GIR_Coverage, 2573,
     /* 441402 */     GIR_EraseRootFromParent_Done,
     /* 441403 */   // Label 8632: @441403
     /* 441403 */   GIM_Try, /*On fail goto*//*Label 8633*/ GIMT_Encode4(441472), // Rule ID 6682 //
     /* 441408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441411 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441415 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441419 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 441423 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 441427 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 441431 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441436 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 441440 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 441444 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 441448 */     // MIs[2] Operand 1
     /* 441448 */     // No operand predicates
     /* 441448 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441452 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441454 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 441454 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 441457 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441459 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441461 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 441467 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 441470 */     GIR_RootConstrainSelectedInstOperands,
     /* 441471 */     // GIR_Coverage, 6682,
     /* 441471 */     GIR_EraseRootFromParent_Done,
     /* 441472 */   // Label 8633: @441472
     /* 441472 */   GIM_Try, /*On fail goto*//*Label 8634*/ GIMT_Encode4(441565), // Rule ID 6834 //
     /* 441477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 441485 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 441489 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441493 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441497 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 441501 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441506 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441510 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441514 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441516 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441516 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 441519 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 441523 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 441528 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 441531 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441535 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 441538 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441543 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441548 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441551 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441553 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441555 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 441557 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 441560 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 441563 */     GIR_RootConstrainSelectedInstOperands,
     /* 441564 */     // GIR_Coverage, 6834,
     /* 441564 */     GIR_EraseRootFromParent_Done,
     /* 441565 */   // Label 8634: @441565
     /* 441565 */   GIM_Try, /*On fail goto*//*Label 8635*/ GIMT_Encode4(441664), // Rule ID 6748 //
     /* 441570 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441573 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441577 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 441581 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 441585 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441590 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 441594 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441598 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441602 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441607 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441611 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441613 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441613 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 441616 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 441620 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 441625 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 441628 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 441632 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 441635 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441640 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441650 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441652 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 441656 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 441659 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 441662 */     GIR_RootConstrainSelectedInstOperands,
     /* 441663 */     // GIR_Coverage, 6748,
     /* 441663 */     GIR_EraseRootFromParent_Done,
     /* 441664 */   // Label 8635: @441664
     /* 441664 */   GIM_Try, /*On fail goto*//*Label 8636*/ GIMT_Encode4(441760), // Rule ID 6780 //
     /* 441669 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441672 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441676 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441680 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441684 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441688 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 441692 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 441696 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441701 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441705 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441709 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441711 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441711 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 441714 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 441718 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 441723 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 441726 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441730 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 441733 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441738 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441748 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441750 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 441752 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 441755 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 441758 */     GIR_RootConstrainSelectedInstOperands,
     /* 441759 */     // GIR_Coverage, 6780,
     /* 441759 */     GIR_EraseRootFromParent_Done,
     /* 441760 */   // Label 8636: @441760
     /* 441760 */   GIM_Try, /*On fail goto*//*Label 8637*/ GIMT_Encode4(441859), // Rule ID 6812 //
     /* 441765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 441772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441776 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441780 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441785 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 441789 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 441793 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 441797 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441802 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441806 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441808 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441808 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 441811 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 441815 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 441820 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 441823 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441827 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 441830 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441835 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441845 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441847 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 441851 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 441854 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 441857 */     GIR_RootConstrainSelectedInstOperands,
     /* 441858 */     // GIR_Coverage, 6812,
     /* 441858 */     GIR_EraseRootFromParent_Done,
     /* 441859 */   // Label 8637: @441859
     /* 441859 */   GIM_Try, /*On fail goto*//*Label 8638*/ GIMT_Encode4(441952), // Rule ID 6856 //
     /* 441864 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441868 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441872 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 441876 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 441880 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441884 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441888 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 441892 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441901 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441903 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441903 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 441906 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 441910 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 441915 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 441918 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 441922 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 441925 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 441930 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441935 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 441938 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 441940 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 441942 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 441944 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 441947 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 441950 */     GIR_RootConstrainSelectedInstOperands,
     /* 441951 */     // GIR_Coverage, 6856,
     /* 441951 */     GIR_EraseRootFromParent_Done,
     /* 441952 */   // Label 8638: @441952
     /* 441952 */   GIM_Try, /*On fail goto*//*Label 8639*/ GIMT_Encode4(442048), // Rule ID 6716 //
     /* 441957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 441960 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 441968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 441972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 441976 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 441980 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 441984 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 441988 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 441993 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 441997 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 441999 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm)), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 441999 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 442002 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 442006 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 442011 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 442014 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442018 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 442021 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442026 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 442031 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i32_indexed),
     /* 442034 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442036 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442038 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442040 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 442043 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 442046 */     GIR_RootConstrainSelectedInstOperands,
     /* 442047 */     // GIR_Coverage, 6716,
     /* 442047 */     GIR_EraseRootFromParent_Done,
     /* 442048 */   // Label 8639: @442048
     /* 442048 */   GIM_Try, /*On fail goto*//*Label 8640*/ GIMT_Encode4(442132), // Rule ID 2575 //
     /* 442053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 442064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 442068 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 442073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442077 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442081 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 442083 */     // (strict_fma:{ *:[v2f32] } (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 442083 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 442086 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 442090 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 442095 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 442098 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442102 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 442105 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442110 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 442115 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 442118 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442120 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442122 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442124 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 442127 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 442130 */     GIR_RootConstrainSelectedInstOperands,
     /* 442131 */     // GIR_Coverage, 2575,
     /* 442131 */     GIR_EraseRootFromParent_Done,
     /* 442132 */   // Label 8640: @442132
     /* 442132 */   GIM_Try, /*On fail goto*//*Label 8641*/ GIMT_Encode4(442182), // Rule ID 14395 //
     /* 442137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442140 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442144 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442148 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 442152 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442157 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442161 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442165 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 442167 */     // (strict_fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 442167 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 442170 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442172 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442174 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442176 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442180 */     GIR_RootConstrainSelectedInstOperands,
     /* 442181 */     // GIR_Coverage, 14395,
     /* 442181 */     GIR_EraseRootFromParent_Done,
     /* 442182 */   // Label 8641: @442182
     /* 442182 */   GIM_Try, /*On fail goto*//*Label 8642*/ GIMT_Encode4(442266), // Rule ID 6684 //
     /* 442187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442194 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 442198 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 442202 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 442206 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 442211 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442215 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 442217 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (AArch64dup:{ *:[v2f32] } FPR32Op:{ *:[f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2i32_indexed:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 442217 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 442220 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 442224 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 442229 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 442232 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442236 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 442239 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442244 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 442249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i32_indexed),
     /* 442252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442254 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442256 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442258 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 442261 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 442264 */     GIR_RootConstrainSelectedInstOperands,
     /* 442265 */     // GIR_Coverage, 6684,
     /* 442265 */     GIR_EraseRootFromParent_Done,
     /* 442266 */   // Label 8642: @442266
     /* 442266 */   GIM_Try, /*On fail goto*//*Label 8643*/ GIMT_Encode4(442316), // Rule ID 1337 //
     /* 442271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 442282 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442286 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 442290 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442295 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 442301 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, (fneg:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm), V64:{ *:[v2f32] }:$Rd)  =>  (FMLSv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 442301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f32),
     /* 442304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442306 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442308 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442310 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442314 */     GIR_RootConstrainSelectedInstOperands,
     /* 442315 */     // GIR_Coverage, 1337,
     /* 442315 */     GIR_EraseRootFromParent_Done,
     /* 442316 */   // Label 8643: @442316
     /* 442316 */   GIM_Try, /*On fail goto*//*Label 8644*/ GIMT_Encode4(442349), // Rule ID 1327 //
     /* 442321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442324 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 442336 */     // (strict_fma:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rd)  =>  (FMLAv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rd, V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 442336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f32),
     /* 442339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442345 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 442347 */     GIR_RootConstrainSelectedInstOperands,
     /* 442348 */     // GIR_Coverage, 1327,
     /* 442348 */     GIR_EraseRootFromParent_Done,
     /* 442349 */   // Label 8644: @442349
     /* 442349 */   GIM_Reject,
     /* 442350 */ // Label 8625: @442350
     /* 442350 */ GIM_Reject,
     /* 442351 */ // Label 8529: @442351
     /* 442351 */ GIM_Try, /*On fail goto*//*Label 8645*/ GIMT_Encode4(443871),
     /* 442356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442359 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 442362 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 442365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442369 */   GIM_Try, /*On fail goto*//*Label 8646*/ GIMT_Encode4(442447), // Rule ID 6842 //
     /* 442374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442386 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 442390 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 442394 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442398 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442402 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442407 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 442411 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442415 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442419 */     // MIs[3] Operand 1
     /* 442419 */     // No operand predicates
     /* 442419 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442423 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442427 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442429 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442434 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442436 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442442 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 442445 */     GIR_RootConstrainSelectedInstOperands,
     /* 442446 */     // GIR_Coverage, 6842,
     /* 442446 */     GIR_EraseRootFromParent_Done,
     /* 442447 */   // Label 8646: @442447
     /* 442447 */   GIM_Try, /*On fail goto*//*Label 8647*/ GIMT_Encode4(442531), // Rule ID 6754 //
     /* 442452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442455 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442459 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442463 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442467 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 442471 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442476 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 442480 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442484 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442488 */     // MIs[2] Operand 1
     /* 442488 */     // No operand predicates
     /* 442488 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 442492 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442496 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442500 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442505 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442509 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442511 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442516 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 442522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442526 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 442529 */     GIR_RootConstrainSelectedInstOperands,
     /* 442530 */     // GIR_Coverage, 6754,
     /* 442530 */     GIR_EraseRootFromParent_Done,
     /* 442531 */   // Label 8647: @442531
     /* 442531 */   GIM_Try, /*On fail goto*//*Label 8648*/ GIMT_Encode4(442612), // Rule ID 6786 //
     /* 442536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442539 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442543 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442547 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442551 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 442555 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442559 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442563 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 442567 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442572 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 442576 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442580 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442584 */     // MIs[3] Operand 1
     /* 442584 */     // No operand predicates
     /* 442584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442588 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442592 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442594 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442599 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442601 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442607 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 442610 */     GIR_RootConstrainSelectedInstOperands,
     /* 442611 */     // GIR_Coverage, 6786,
     /* 442611 */     GIR_EraseRootFromParent_Done,
     /* 442612 */   // Label 8648: @442612
     /* 442612 */   GIM_Try, /*On fail goto*//*Label 8649*/ GIMT_Encode4(442696), // Rule ID 6818 //
     /* 442617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442620 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442624 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442628 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442632 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442637 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 442641 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442645 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442649 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 442653 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442658 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 442662 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442666 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442670 */     // MIs[3] Operand 1
     /* 442670 */     // No operand predicates
     /* 442670 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442674 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442676 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442681 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 442687 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442691 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 442694 */     GIR_RootConstrainSelectedInstOperands,
     /* 442695 */     // GIR_Coverage, 6818,
     /* 442695 */     GIR_EraseRootFromParent_Done,
     /* 442696 */   // Label 8649: @442696
     /* 442696 */   GIM_Try, /*On fail goto*//*Label 8650*/ GIMT_Encode4(442774), // Rule ID 6864 //
     /* 442701 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 442709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 442721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 442725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442729 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442733 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442738 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 442742 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442746 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442750 */     // MIs[3] Operand 1
     /* 442750 */     // No operand predicates
     /* 442750 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442754 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442756 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442761 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442763 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442769 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 442772 */     GIR_RootConstrainSelectedInstOperands,
     /* 442773 */     // GIR_Coverage, 6864,
     /* 442773 */     GIR_EraseRootFromParent_Done,
     /* 442774 */   // Label 8650: @442774
     /* 442774 */   GIM_Try, /*On fail goto*//*Label 8651*/ GIMT_Encode4(442855), // Rule ID 6722 //
     /* 442779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442782 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442786 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 442790 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 442794 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442798 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 442802 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442806 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442810 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 442814 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442819 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 442823 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442827 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442831 */     // MIs[3] Operand 1
     /* 442831 */     // No operand predicates
     /* 442831 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442835 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 442837 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442837 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 442840 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442842 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442844 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442846 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 442850 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 442853 */     GIR_RootConstrainSelectedInstOperands,
     /* 442854 */     // GIR_Coverage, 6722,
     /* 442854 */     GIR_EraseRootFromParent_Done,
     /* 442855 */   // Label 8651: @442855
     /* 442855 */   GIM_Try, /*On fail goto*//*Label 8652*/ GIMT_Encode4(442924), // Rule ID 2581 //
     /* 442860 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442863 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 442867 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442871 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442875 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 442879 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442884 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 442888 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442892 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442896 */     // MIs[2] Operand 1
     /* 442896 */     // No operand predicates
     /* 442896 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442900 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442904 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 442906 */     // (strict_fma:{ *:[v2f64] } (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 442909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442911 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442913 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 442915 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442919 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 442922 */     GIR_RootConstrainSelectedInstOperands,
     /* 442923 */     // GIR_Coverage, 2581,
     /* 442923 */     GIR_EraseRootFromParent_Done,
     /* 442924 */   // Label 8652: @442924
     /* 442924 */   GIM_Try, /*On fail goto*//*Label 8653*/ GIMT_Encode4(442993), // Rule ID 6690 //
     /* 442929 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 442932 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442936 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 442940 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE64),
     /* 442944 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 442948 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 442952 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442957 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 442961 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 442965 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 442969 */     // MIs[2] Operand 1
     /* 442969 */     // No operand predicates
     /* 442969 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 442973 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 442975 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 442975 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 442978 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 442980 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 442982 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 442984 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 442988 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 442991 */     GIR_RootConstrainSelectedInstOperands,
     /* 442992 */     // GIR_Coverage, 6690,
     /* 442992 */     GIR_EraseRootFromParent_Done,
     /* 442993 */   // Label 8653: @442993
     /* 442993 */   GIM_Try, /*On fail goto*//*Label 8654*/ GIMT_Encode4(443086), // Rule ID 6844 //
     /* 442998 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443002 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 443006 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 443010 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 443014 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443018 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 443022 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443027 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443031 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443035 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443037 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443037 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443040 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443044 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443049 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443052 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 443056 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443059 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443064 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443069 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443072 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443074 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443076 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 443078 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443081 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443084 */     GIR_RootConstrainSelectedInstOperands,
     /* 443085 */     // GIR_Coverage, 6844,
     /* 443085 */     GIR_EraseRootFromParent_Done,
     /* 443086 */   // Label 8654: @443086
     /* 443086 */   GIM_Try, /*On fail goto*//*Label 8655*/ GIMT_Encode4(443185), // Rule ID 6756 //
     /* 443091 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443094 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443098 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 443102 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 443106 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443111 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 443115 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443119 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443123 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443128 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443132 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443134 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443134 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443137 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443141 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443146 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443149 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443153 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443156 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443161 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443171 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443173 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 443177 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443180 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443183 */     GIR_RootConstrainSelectedInstOperands,
     /* 443184 */     // GIR_Coverage, 6756,
     /* 443184 */     GIR_EraseRootFromParent_Done,
     /* 443185 */   // Label 8655: @443185
     /* 443185 */   GIM_Try, /*On fail goto*//*Label 8656*/ GIMT_Encode4(443281), // Rule ID 6788 //
     /* 443190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443193 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443197 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443201 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443205 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 443209 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 443213 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 443217 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443222 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443226 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443230 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443232 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443232 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443235 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443239 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443244 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443247 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 443251 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443254 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443259 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443269 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443271 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 443273 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443276 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443279 */     GIR_RootConstrainSelectedInstOperands,
     /* 443280 */     // GIR_Coverage, 6788,
     /* 443280 */     GIR_EraseRootFromParent_Done,
     /* 443281 */   // Label 8656: @443281
     /* 443281 */   GIM_Try, /*On fail goto*//*Label 8657*/ GIMT_Encode4(443380), // Rule ID 6820 //
     /* 443286 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443289 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443293 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443297 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443301 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443306 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 443310 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 443314 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 443318 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443323 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443327 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443329 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443329 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443332 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443336 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443341 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443344 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 443348 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443351 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443356 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443366 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443368 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 443372 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443375 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443378 */     GIR_RootConstrainSelectedInstOperands,
     /* 443379 */     // GIR_Coverage, 6820,
     /* 443379 */     GIR_EraseRootFromParent_Done,
     /* 443380 */   // Label 8657: @443380
     /* 443380 */   GIM_Try, /*On fail goto*//*Label 8658*/ GIMT_Encode4(443473), // Rule ID 6866 //
     /* 443385 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 443393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 443397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 443401 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 443405 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443409 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 443413 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443418 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443422 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443424 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } (fneg:{ *:[f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443424 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443427 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443431 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443436 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443439 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 443443 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443446 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443451 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443463 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 443465 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443471 */     GIR_RootConstrainSelectedInstOperands,
     /* 443472 */     // GIR_Coverage, 6866,
     /* 443472 */     GIR_EraseRootFromParent_Done,
     /* 443473 */   // Label 8658: @443473
     /* 443473 */   GIM_Try, /*On fail goto*//*Label 8659*/ GIMT_Encode4(443569), // Rule ID 6724 //
     /* 443478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443481 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443485 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 443489 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443493 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443497 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 443501 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 443505 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 443509 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443514 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443518 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 443520 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm)), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443520 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443523 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443527 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443532 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443535 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 443539 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443542 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443547 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2i64_indexed),
     /* 443555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443557 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443559 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 443561 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443564 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443567 */     GIR_RootConstrainSelectedInstOperands,
     /* 443568 */     // GIR_Coverage, 6724,
     /* 443568 */     GIR_EraseRootFromParent_Done,
     /* 443569 */   // Label 8659: @443569
     /* 443569 */   GIM_Try, /*On fail goto*//*Label 8660*/ GIMT_Encode4(443653), // Rule ID 2583 //
     /* 443574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 443585 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 443589 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443594 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443598 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443602 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 443604 */     // (strict_fma:{ *:[v2f64] } (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443604 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443607 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443611 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443616 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443619 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443623 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443626 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443631 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 443639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443641 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443643 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 443645 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443648 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443651 */     GIR_RootConstrainSelectedInstOperands,
     /* 443652 */     // GIR_Coverage, 2583,
     /* 443652 */     GIR_EraseRootFromParent_Done,
     /* 443653 */   // Label 8660: @443653
     /* 443653 */   GIM_Try, /*On fail goto*//*Label 8661*/ GIMT_Encode4(443703), // Rule ID 14399 //
     /* 443658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443678 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443682 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443686 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 443688 */     // (strict_fma:{ *:[v2f64] } (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 443688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 443691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443693 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443695 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 443697 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443701 */     GIR_RootConstrainSelectedInstOperands,
     /* 443702 */     // GIR_Coverage, 14399,
     /* 443702 */     GIR_EraseRootFromParent_Done,
     /* 443703 */   // Label 8661: @443703
     /* 443703 */   GIM_Try, /*On fail goto*//*Label 8662*/ GIMT_Encode4(443787), // Rule ID 6692 //
     /* 443708 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443711 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443715 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 443719 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 443723 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 443727 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443732 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443736 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 443738 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (AArch64dup:{ *:[v2f64] } FPR64Op:{ *:[f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2i64_indexed:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR64Op:{ *:[f64] }:$Rm, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 443738 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 443741 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 443745 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 443750 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 443753 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443757 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 443760 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443765 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2i64_indexed),
     /* 443773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443775 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443777 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 443779 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 443782 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 443785 */     GIR_RootConstrainSelectedInstOperands,
     /* 443786 */     // GIR_Coverage, 6692,
     /* 443786 */     GIR_EraseRootFromParent_Done,
     /* 443787 */   // Label 8662: @443787
     /* 443787 */   GIM_Try, /*On fail goto*//*Label 8663*/ GIMT_Encode4(443837), // Rule ID 1341 //
     /* 443792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443795 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 443803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 443811 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443816 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443820 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 443822 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (fneg:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm), V128:{ *:[v2f64] }:$Rd)  =>  (FMLSv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 443822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv2f64),
     /* 443825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443827 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443829 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 443831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443835 */     GIR_RootConstrainSelectedInstOperands,
     /* 443836 */     // GIR_Coverage, 1341,
     /* 443836 */     GIR_EraseRootFromParent_Done,
     /* 443837 */   // Label 8663: @443837
     /* 443837 */   GIM_Try, /*On fail goto*//*Label 8664*/ GIMT_Encode4(443870), // Rule ID 1331 //
     /* 443842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 443845 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443849 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443853 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 443857 */     // (strict_fma:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rd)  =>  (FMLAv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rd, V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 443857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv2f64),
     /* 443860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443862 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443864 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 443866 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 443868 */     GIR_RootConstrainSelectedInstOperands,
     /* 443869 */     // GIR_Coverage, 1331,
     /* 443869 */     GIR_EraseRootFromParent_Done,
     /* 443870 */   // Label 8664: @443870
     /* 443870 */   GIM_Reject,
     /* 443871 */ // Label 8645: @443871
     /* 443871 */ GIM_Reject,
     /* 443872 */ // Label 8530: @443872
     /* 443872 */ GIM_Try, /*On fail goto*//*Label 8665*/ GIMT_Encode4(445050),
     /* 443877 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 443880 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 443883 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 443886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443890 */   GIM_Try, /*On fail goto*//*Label 8666*/ GIMT_Encode4(443974), // Rule ID 6738 //
     /* 443895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 443898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 443906 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 443910 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 443914 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 443919 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 443923 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 443927 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 443931 */     // MIs[2] Operand 1
     /* 443931 */     // No operand predicates
     /* 443931 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 443935 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443939 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 443943 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443948 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 443952 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 443954 */     // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 443954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 443957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 443959 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 443961 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 443965 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 443969 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 443972 */     GIR_RootConstrainSelectedInstOperands,
     /* 443973 */     // GIR_Coverage, 6738,
     /* 443973 */     GIR_EraseRootFromParent_Done,
     /* 443974 */   // Label 8666: @443974
     /* 443974 */   GIM_Try, /*On fail goto*//*Label 8667*/ GIMT_Encode4(444055), // Rule ID 6770 //
     /* 443979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 443982 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 443986 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 443990 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 443994 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 443998 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 444002 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 444006 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 444010 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 444015 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 444019 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 444023 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 444027 */     // MIs[3] Operand 1
     /* 444027 */     // No operand predicates
     /* 444027 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444031 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444035 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 444037 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 444037 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444040 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444042 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444044 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 444046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444050 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 444053 */     GIR_RootConstrainSelectedInstOperands,
     /* 444054 */     // GIR_Coverage, 6770,
     /* 444054 */     GIR_EraseRootFromParent_Done,
     /* 444055 */   // Label 8667: @444055
     /* 444055 */   GIM_Try, /*On fail goto*//*Label 8668*/ GIMT_Encode4(444139), // Rule ID 6802 //
     /* 444060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444063 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444067 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444071 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444075 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444080 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 444084 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 444088 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 444092 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 444096 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 444101 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 444105 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 444109 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 444113 */     // MIs[3] Operand 1
     /* 444113 */     // No operand predicates
     /* 444113 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444117 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 444119 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 444119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444124 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 444130 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444134 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 444137 */     GIR_RootConstrainSelectedInstOperands,
     /* 444138 */     // GIR_Coverage, 6802,
     /* 444138 */     GIR_EraseRootFromParent_Done,
     /* 444139 */   // Label 8668: @444139
     /* 444139 */   GIM_Try, /*On fail goto*//*Label 8669*/ GIMT_Encode4(444220), // Rule ID 6706 //
     /* 444144 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444147 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444151 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 444155 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444159 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444163 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 444167 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 444171 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 444175 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 444179 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 444184 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 444188 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 444192 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 444196 */     // MIs[3] Operand 1
     /* 444196 */     // No operand predicates
     /* 444196 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444200 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 444202 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 444202 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444205 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444207 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 444211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444215 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 444218 */     GIR_RootConstrainSelectedInstOperands,
     /* 444219 */     // GIR_Coverage, 6706,
     /* 444219 */     GIR_EraseRootFromParent_Done,
     /* 444220 */   // Label 8669: @444220
     /* 444220 */   GIM_Try, /*On fail goto*//*Label 8670*/ GIMT_Encode4(444289), // Rule ID 2565 //
     /* 444225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 444236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 444240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 444244 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 444249 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 444253 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 444257 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 444261 */     // MIs[2] Operand 1
     /* 444261 */     // No operand predicates
     /* 444261 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444265 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444269 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444271 */     // (strict_fma:{ *:[v4f16] } (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 444271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 444274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444276 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444278 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 444280 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444284 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 444287 */     GIR_RootConstrainSelectedInstOperands,
     /* 444288 */     // GIR_Coverage, 2565,
     /* 444288 */     GIR_EraseRootFromParent_Done,
     /* 444289 */   // Label 8670: @444289
     /* 444289 */   GIM_Try, /*On fail goto*//*Label 8671*/ GIMT_Encode4(444358), // Rule ID 6674 //
     /* 444294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444297 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444301 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 444305 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 444309 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 444313 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 444317 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 444322 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 444326 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 444330 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 444334 */     // MIs[2] Operand 1
     /* 444334 */     // No operand predicates
     /* 444334 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444338 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444340 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64duplane16:{ *:[v4f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 444340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 444343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444345 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444347 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 444349 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444353 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 444356 */     GIR_RootConstrainSelectedInstOperands,
     /* 444357 */     // GIR_Coverage, 6674,
     /* 444357 */     GIR_EraseRootFromParent_Done,
     /* 444358 */   // Label 8671: @444358
     /* 444358 */   GIM_Try, /*On fail goto*//*Label 8672*/ GIMT_Encode4(444457), // Rule ID 6740 //
     /* 444363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444366 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444370 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 444374 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 444378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444383 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 444387 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444391 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444395 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444400 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444404 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444406 */     // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444406 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444409 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444413 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444418 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444421 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444425 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444428 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444433 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444443 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444445 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 444449 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444452 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444455 */     GIR_RootConstrainSelectedInstOperands,
     /* 444456 */     // GIR_Coverage, 6740,
     /* 444456 */     GIR_EraseRootFromParent_Done,
     /* 444457 */   // Label 8672: @444457
     /* 444457 */   GIM_Try, /*On fail goto*//*Label 8673*/ GIMT_Encode4(444553), // Rule ID 6772 //
     /* 444462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444465 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444469 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444473 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444477 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 444481 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 444485 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 444489 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444494 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444498 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444502 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444504 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444504 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444507 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444511 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444516 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444519 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444523 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444526 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444531 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444541 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444543 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 444545 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444548 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444551 */     GIR_RootConstrainSelectedInstOperands,
     /* 444552 */     // GIR_Coverage, 6772,
     /* 444552 */     GIR_EraseRootFromParent_Done,
     /* 444553 */   // Label 8673: @444553
     /* 444553 */   GIM_Try, /*On fail goto*//*Label 8674*/ GIMT_Encode4(444652), // Rule ID 6804 //
     /* 444558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444561 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444565 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444569 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444573 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444578 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 444582 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 444586 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 444590 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444595 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444599 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444601 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444601 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444604 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444608 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444613 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444616 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444620 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444623 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444628 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444638 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 444644 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444647 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444650 */     GIR_RootConstrainSelectedInstOperands,
     /* 444651 */     // GIR_Coverage, 6804,
     /* 444651 */     GIR_EraseRootFromParent_Done,
     /* 444652 */   // Label 8674: @444652
     /* 444652 */   GIM_Try, /*On fail goto*//*Label 8675*/ GIMT_Encode4(444748), // Rule ID 6708 //
     /* 444657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444660 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 444668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444676 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 444680 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 444684 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 444688 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444693 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444697 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 444699 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444699 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444702 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444706 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444711 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444714 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 444718 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444721 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444726 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i16_indexed),
     /* 444734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444736 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444738 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 444740 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444743 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444746 */     GIR_RootConstrainSelectedInstOperands,
     /* 444747 */     // GIR_Coverage, 6708,
     /* 444747 */     GIR_EraseRootFromParent_Done,
     /* 444748 */   // Label 8675: @444748
     /* 444748 */   GIM_Try, /*On fail goto*//*Label 8676*/ GIMT_Encode4(444832), // Rule ID 2567 //
     /* 444753 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444756 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444760 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 444764 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 444768 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444777 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444781 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 444783 */     // (strict_fma:{ *:[v4f16] } (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444783 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444786 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444790 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444795 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444798 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444802 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444805 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444810 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444815 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 444818 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444820 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444822 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 444824 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444827 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444830 */     GIR_RootConstrainSelectedInstOperands,
     /* 444831 */     // GIR_Coverage, 2567,
     /* 444831 */     GIR_EraseRootFromParent_Done,
     /* 444832 */   // Label 8676: @444832
     /* 444832 */   GIM_Try, /*On fail goto*//*Label 8677*/ GIMT_Encode4(444882), // Rule ID 14391 //
     /* 444837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444840 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 444844 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444848 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444852 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444857 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444861 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444865 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 444867 */     // (strict_fma:{ *:[v4f16] } (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 444867 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 444870 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444872 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444874 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 444876 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444880 */     GIR_RootConstrainSelectedInstOperands,
     /* 444881 */     // GIR_Coverage, 14391,
     /* 444881 */     GIR_EraseRootFromParent_Done,
     /* 444882 */   // Label 8677: @444882
     /* 444882 */   GIM_Try, /*On fail goto*//*Label 8678*/ GIMT_Encode4(444966), // Rule ID 6676 //
     /* 444887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444890 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444894 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 444898 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 444902 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 444906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444911 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444915 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 444917 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (AArch64dup:{ *:[v4f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4i16_indexed:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 444917 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 444920 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 444924 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 444929 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 444932 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 444936 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 444939 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 444944 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 444949 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i16_indexed),
     /* 444952 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 444954 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 444956 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 444958 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 444961 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 444964 */     GIR_RootConstrainSelectedInstOperands,
     /* 444965 */     // GIR_Coverage, 6676,
     /* 444965 */     GIR_EraseRootFromParent_Done,
     /* 444966 */   // Label 8678: @444966
     /* 444966 */   GIM_Try, /*On fail goto*//*Label 8679*/ GIMT_Encode4(445016), // Rule ID 1333 //
     /* 444971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 444974 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444978 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 444982 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 444986 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 444990 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444995 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 444999 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 445001 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, (fneg:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm), V64:{ *:[v4f16] }:$Rd)  =>  (FMLSv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 445001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f16),
     /* 445004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445006 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445008 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 445010 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 445014 */     GIR_RootConstrainSelectedInstOperands,
     /* 445015 */     // GIR_Coverage, 1333,
     /* 445015 */     GIR_EraseRootFromParent_Done,
     /* 445016 */   // Label 8679: @445016
     /* 445016 */   GIM_Try, /*On fail goto*//*Label 8680*/ GIMT_Encode4(445049), // Rule ID 1323 //
     /* 445021 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 445024 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 445028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 445032 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 445036 */     // (strict_fma:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rd)  =>  (FMLAv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 445036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f16),
     /* 445039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445041 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445043 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445045 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 445047 */     GIR_RootConstrainSelectedInstOperands,
     /* 445048 */     // GIR_Coverage, 1323,
     /* 445048 */     GIR_EraseRootFromParent_Done,
     /* 445049 */   // Label 8680: @445049
     /* 445049 */   GIM_Reject,
     /* 445050 */ // Label 8665: @445050
     /* 445050 */ GIM_Reject,
     /* 445051 */ // Label 8531: @445051
     /* 445051 */ GIM_Try, /*On fail goto*//*Label 8681*/ GIMT_Encode4(446571),
     /* 445056 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445059 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 445062 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 445065 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445069 */   GIM_Try, /*On fail goto*//*Label 8682*/ GIMT_Encode4(445147), // Rule ID 6836 //
     /* 445074 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445078 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445082 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445086 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 445090 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445094 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445098 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445102 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445107 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 445111 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445115 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445119 */     // MIs[3] Operand 1
     /* 445119 */     // No operand predicates
     /* 445119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445123 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445127 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445129 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445134 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445136 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445138 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445142 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 445145 */     GIR_RootConstrainSelectedInstOperands,
     /* 445146 */     // GIR_Coverage, 6836,
     /* 445146 */     GIR_EraseRootFromParent_Done,
     /* 445147 */   // Label 8682: @445147
     /* 445147 */   GIM_Try, /*On fail goto*//*Label 8683*/ GIMT_Encode4(445231), // Rule ID 6750 //
     /* 445152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445155 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445159 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445163 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445167 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 445171 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445176 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 445180 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445184 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445188 */     // MIs[2] Operand 1
     /* 445188 */     // No operand predicates
     /* 445188 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 445192 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445196 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445200 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445205 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445209 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445211 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445216 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445218 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 445222 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 445226 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 445229 */     GIR_RootConstrainSelectedInstOperands,
     /* 445230 */     // GIR_Coverage, 6750,
     /* 445230 */     GIR_EraseRootFromParent_Done,
     /* 445231 */   // Label 8683: @445231
     /* 445231 */   GIM_Try, /*On fail goto*//*Label 8684*/ GIMT_Encode4(445312), // Rule ID 6782 //
     /* 445236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445243 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445247 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445251 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445255 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445259 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445263 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 445267 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445272 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 445276 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445280 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445284 */     // MIs[3] Operand 1
     /* 445284 */     // No operand predicates
     /* 445284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445292 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445294 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445299 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445301 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445307 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 445310 */     GIR_RootConstrainSelectedInstOperands,
     /* 445311 */     // GIR_Coverage, 6782,
     /* 445311 */     GIR_EraseRootFromParent_Done,
     /* 445312 */   // Label 8684: @445312
     /* 445312 */   GIM_Try, /*On fail goto*//*Label 8685*/ GIMT_Encode4(445396), // Rule ID 6814 //
     /* 445317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445328 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445332 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445337 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 445341 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445345 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445349 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 445353 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445358 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 445362 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445366 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445370 */     // MIs[3] Operand 1
     /* 445370 */     // No operand predicates
     /* 445370 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445374 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445376 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445381 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 445387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445391 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 445394 */     GIR_RootConstrainSelectedInstOperands,
     /* 445395 */     // GIR_Coverage, 6814,
     /* 445395 */     GIR_EraseRootFromParent_Done,
     /* 445396 */   // Label 8685: @445396
     /* 445396 */   GIM_Try, /*On fail goto*//*Label 8686*/ GIMT_Encode4(445474), // Rule ID 6858 //
     /* 445401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445405 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 445409 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445413 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445417 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 445421 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445425 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445429 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445433 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445438 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
     /* 445442 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445446 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445450 */     // MIs[3] Operand 1
     /* 445450 */     // No operand predicates
     /* 445450 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445454 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445456 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445456 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445459 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445461 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445463 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 445465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445469 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 445472 */     GIR_RootConstrainSelectedInstOperands,
     /* 445473 */     // GIR_Coverage, 6858,
     /* 445473 */     GIR_EraseRootFromParent_Done,
     /* 445474 */   // Label 8686: @445474
     /* 445474 */   GIM_Try, /*On fail goto*//*Label 8687*/ GIMT_Encode4(445555), // Rule ID 6718 //
     /* 445479 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445482 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445486 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 445490 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445494 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445498 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445502 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445506 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445510 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 445514 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445519 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 445523 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445527 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445531 */     // MIs[3] Operand 1
     /* 445531 */     // No operand predicates
     /* 445531 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445535 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 445537 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445537 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445540 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445542 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445544 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 445546 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445550 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 445553 */     GIR_RootConstrainSelectedInstOperands,
     /* 445554 */     // GIR_Coverage, 6718,
     /* 445554 */     GIR_EraseRootFromParent_Done,
     /* 445555 */   // Label 8687: @445555
     /* 445555 */   GIM_Try, /*On fail goto*//*Label 8688*/ GIMT_Encode4(445624), // Rule ID 2577 //
     /* 445560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445563 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445567 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445571 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445575 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 445579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445584 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 445588 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445592 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445596 */     // MIs[2] Operand 1
     /* 445596 */     // No operand predicates
     /* 445596 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445600 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445604 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 445606 */     // (strict_fma:{ *:[v4f32] } (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 445609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445611 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445613 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 445619 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 445622 */     GIR_RootConstrainSelectedInstOperands,
     /* 445623 */     // GIR_Coverage, 2577,
     /* 445623 */     GIR_EraseRootFromParent_Done,
     /* 445624 */   // Label 8688: @445624
     /* 445624 */   GIM_Try, /*On fail goto*//*Label 8689*/ GIMT_Encode4(445693), // Rule ID 6686 //
     /* 445629 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445632 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 445640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 445644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 445652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445657 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 445661 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 445665 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 445669 */     // MIs[2] Operand 1
     /* 445669 */     // No operand predicates
     /* 445669 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445673 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 445675 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)
     /* 445675 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 445678 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445680 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445682 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 445684 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 445688 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 445691 */     GIR_RootConstrainSelectedInstOperands,
     /* 445692 */     // GIR_Coverage, 6686,
     /* 445692 */     GIR_EraseRootFromParent_Done,
     /* 445693 */   // Label 8689: @445693
     /* 445693 */   GIM_Try, /*On fail goto*//*Label 8690*/ GIMT_Encode4(445786), // Rule ID 6840 //
     /* 445698 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445702 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 445706 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 445710 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445714 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445718 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 445722 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445731 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445735 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 445737 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 445737 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 445740 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 445744 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 445749 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 445752 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445756 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 445759 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445764 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445774 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445778 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 445781 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 445784 */     GIR_RootConstrainSelectedInstOperands,
     /* 445785 */     // GIR_Coverage, 6840,
     /* 445785 */     GIR_EraseRootFromParent_Done,
     /* 445786 */   // Label 8690: @445786
     /* 445786 */   GIM_Try, /*On fail goto*//*Label 8691*/ GIMT_Encode4(445885), // Rule ID 6752 //
     /* 445791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445794 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445798 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 445802 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 445806 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445811 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 445815 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445819 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445823 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445828 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445832 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 445834 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 445834 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 445837 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 445841 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 445846 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 445849 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 445853 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 445856 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445861 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445871 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445873 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 445877 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 445880 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 445883 */     GIR_RootConstrainSelectedInstOperands,
     /* 445884 */     // GIR_Coverage, 6752,
     /* 445884 */     GIR_EraseRootFromParent_Done,
     /* 445885 */   // Label 8691: @445885
     /* 445885 */   GIM_Try, /*On fail goto*//*Label 8692*/ GIMT_Encode4(445981), // Rule ID 6784 //
     /* 445890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445893 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445897 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445901 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 445905 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 445909 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 445913 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 445917 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445922 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445926 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445930 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 445932 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 445932 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 445935 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 445939 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 445944 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 445947 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 445951 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 445954 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 445959 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 445964 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 445967 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 445969 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 445971 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 445973 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 445976 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 445979 */     GIR_RootConstrainSelectedInstOperands,
     /* 445980 */     // GIR_Coverage, 6784,
     /* 445980 */     GIR_EraseRootFromParent_Done,
     /* 445981 */   // Label 8692: @445981
     /* 445981 */   GIM_Try, /*On fail goto*//*Label 8693*/ GIMT_Encode4(446080), // Rule ID 6816 //
     /* 445986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 445989 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 445993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 445997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 446001 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446006 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 446010 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 446014 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 446018 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446023 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446027 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 446029 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 446029 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 446032 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 446036 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 446041 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 446044 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446048 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 446051 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446056 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 446064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446066 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446068 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 446072 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 446075 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 446078 */     GIR_RootConstrainSelectedInstOperands,
     /* 446079 */     // GIR_Coverage, 6816,
     /* 446079 */     GIR_EraseRootFromParent_Done,
     /* 446080 */   // Label 8693: @446080
     /* 446080 */   GIM_Try, /*On fail goto*//*Label 8694*/ GIMT_Encode4(446173), // Rule ID 6862 //
     /* 446085 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446089 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 446093 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 446097 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 446101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 446105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446109 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 446113 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446118 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446122 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 446124 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } (fneg:{ *:[f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 446124 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 446127 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 446131 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 446136 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 446139 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446143 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 446146 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446151 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 446159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446161 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446163 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 446165 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 446168 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 446171 */     GIR_RootConstrainSelectedInstOperands,
     /* 446172 */     // GIR_Coverage, 6862,
     /* 446172 */     GIR_EraseRootFromParent_Done,
     /* 446173 */   // Label 8694: @446173
     /* 446173 */   GIM_Try, /*On fail goto*//*Label 8695*/ GIMT_Encode4(446269), // Rule ID 6720 //
     /* 446178 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446185 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 446189 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446193 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 446197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 446201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 446205 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 446209 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446214 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446218 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 446220 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm)), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 446220 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 446223 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 446227 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 446232 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 446235 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446239 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 446242 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446247 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446252 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4i32_indexed),
     /* 446255 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446257 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446259 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 446261 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 446264 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 446267 */     GIR_RootConstrainSelectedInstOperands,
     /* 446268 */     // GIR_Coverage, 6720,
     /* 446268 */     GIR_EraseRootFromParent_Done,
     /* 446269 */   // Label 8695: @446269
     /* 446269 */   GIM_Try, /*On fail goto*//*Label 8696*/ GIMT_Encode4(446353), // Rule ID 2579 //
     /* 446274 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446277 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446281 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 446285 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 446289 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446298 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446302 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 446304 */     // (strict_fma:{ *:[v4f32] } (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 446304 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 446307 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 446311 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 446316 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 446319 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446323 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 446326 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446331 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 446339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446341 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446343 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 446345 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 446348 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 446351 */     GIR_RootConstrainSelectedInstOperands,
     /* 446352 */     // GIR_Coverage, 2579,
     /* 446352 */     GIR_EraseRootFromParent_Done,
     /* 446353 */   // Label 8696: @446353
     /* 446353 */   GIM_Try, /*On fail goto*//*Label 8697*/ GIMT_Encode4(446403), // Rule ID 14397 //
     /* 446358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446361 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446365 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446369 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 446373 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446382 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446386 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 446388 */     // (strict_fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 446388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 446391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446393 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446395 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 446397 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446401 */     GIR_RootConstrainSelectedInstOperands,
     /* 446402 */     // GIR_Coverage, 14397,
     /* 446402 */     GIR_EraseRootFromParent_Done,
     /* 446403 */   // Label 8697: @446403
     /* 446403 */   GIM_Try, /*On fail goto*//*Label 8698*/ GIMT_Encode4(446487), // Rule ID 6688 //
     /* 446408 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446411 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446415 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 446419 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 446423 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 446427 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446432 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446436 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 446438 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (AArch64dup:{ *:[v4f32] } FPR32Op:{ *:[f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4i32_indexed:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, (SUBREG_TO_REG:{ *:[f128] } 0:{ *:[i32] }, FPR32Op:{ *:[f32] }:$Rm, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 446438 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 446441 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 446445 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 446450 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 446453 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446457 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 446460 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446465 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 446470 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4i32_indexed),
     /* 446473 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446475 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446477 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 446479 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 446482 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 446485 */     GIR_RootConstrainSelectedInstOperands,
     /* 446486 */     // GIR_Coverage, 6688,
     /* 446486 */     GIR_EraseRootFromParent_Done,
     /* 446487 */   // Label 8698: @446487
     /* 446487 */   GIM_Try, /*On fail goto*//*Label 8699*/ GIMT_Encode4(446537), // Rule ID 1339 //
     /* 446492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446495 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446499 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 446503 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446507 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 446511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446516 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446520 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 446522 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (fneg:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm), V128:{ *:[v4f32] }:$Rd)  =>  (FMLSv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 446522 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv4f32),
     /* 446525 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446527 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446529 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 446531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446535 */     GIR_RootConstrainSelectedInstOperands,
     /* 446536 */     // GIR_Coverage, 1339,
     /* 446536 */     GIR_EraseRootFromParent_Done,
     /* 446537 */   // Label 8699: @446537
     /* 446537 */   GIM_Try, /*On fail goto*//*Label 8700*/ GIMT_Encode4(446570), // Rule ID 1329 //
     /* 446542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 446545 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446549 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446553 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446557 */     // (strict_fma:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rd)  =>  (FMLAv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rd, V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 446557 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv4f32),
     /* 446560 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446562 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446564 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 446566 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 446568 */     GIR_RootConstrainSelectedInstOperands,
     /* 446569 */     // GIR_Coverage, 1329,
     /* 446569 */     GIR_EraseRootFromParent_Done,
     /* 446570 */   // Label 8700: @446570
     /* 446570 */   GIM_Reject,
     /* 446571 */ // Label 8681: @446571
     /* 446571 */ GIM_Reject,
     /* 446572 */ // Label 8532: @446572
     /* 446572 */ GIM_Try, /*On fail goto*//*Label 8701*/ GIMT_Encode4(447750),
     /* 446577 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446580 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 446583 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 446586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446590 */   GIM_Try, /*On fail goto*//*Label 8702*/ GIMT_Encode4(446674), // Rule ID 6734 //
     /* 446595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446598 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446602 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 446606 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446610 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 446614 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 446619 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 446623 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 446627 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 446631 */     // MIs[2] Operand 1
     /* 446631 */     // No operand predicates
     /* 446631 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
     /* 446635 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446639 */     GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446643 */     GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446648 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446652 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 446654 */     // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 446654 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 446657 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446659 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446661 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
     /* 446665 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446669 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 446672 */     GIR_RootConstrainSelectedInstOperands,
     /* 446673 */     // GIR_Coverage, 6734,
     /* 446673 */     GIR_EraseRootFromParent_Done,
     /* 446674 */   // Label 8702: @446674
     /* 446674 */   GIM_Try, /*On fail goto*//*Label 8703*/ GIMT_Encode4(446755), // Rule ID 6766 //
     /* 446679 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446682 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446686 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446690 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446694 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 446698 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 446702 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446706 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 446710 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 446715 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 446719 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 446723 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 446727 */     // MIs[3] Operand 1
     /* 446727 */     // No operand predicates
     /* 446727 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446731 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446735 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 446737 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 446737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 446740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446742 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446744 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 446746 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446750 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 446753 */     GIR_RootConstrainSelectedInstOperands,
     /* 446754 */     // GIR_Coverage, 6766,
     /* 446754 */     GIR_EraseRootFromParent_Done,
     /* 446755 */   // Label 8703: @446755
     /* 446755 */   GIM_Try, /*On fail goto*//*Label 8704*/ GIMT_Encode4(446839), // Rule ID 6798 //
     /* 446760 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446763 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446767 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446771 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446775 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446780 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 446784 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 446788 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446792 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 446796 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 446801 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 446805 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 446809 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 446813 */     // MIs[3] Operand 1
     /* 446813 */     // No operand predicates
     /* 446813 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446817 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 446819 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 446819 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 446822 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446824 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446826 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 446830 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446834 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 446837 */     GIR_RootConstrainSelectedInstOperands,
     /* 446838 */     // GIR_Coverage, 6798,
     /* 446838 */     GIR_EraseRootFromParent_Done,
     /* 446839 */   // Label 8704: @446839
     /* 446839 */   GIM_Try, /*On fail goto*//*Label 8705*/ GIMT_Encode4(446920), // Rule ID 6702 //
     /* 446844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446847 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446851 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 446855 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 446859 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446863 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 446867 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 446871 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446875 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 446879 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 446884 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 446888 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 446892 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 446896 */     // MIs[3] Operand 1
     /* 446896 */     // No operand predicates
     /* 446896 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446900 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 446902 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 446902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 446905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446907 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446909 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 446911 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 446915 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 446918 */     GIR_RootConstrainSelectedInstOperands,
     /* 446919 */     // GIR_Coverage, 6702,
     /* 446919 */     GIR_EraseRootFromParent_Done,
     /* 446920 */   // Label 8705: @446920
     /* 446920 */   GIM_Try, /*On fail goto*//*Label 8706*/ GIMT_Encode4(446989), // Rule ID 2561 //
     /* 446925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446928 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 446932 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 446936 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 446940 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 446944 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 446949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 446953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 446957 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 446961 */     // MIs[2] Operand 1
     /* 446961 */     // No operand predicates
     /* 446961 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446965 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 446969 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 446971 */     // (strict_fma:{ *:[v8f16] } (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 446971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 446974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 446976 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 446978 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 446980 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 446984 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 446987 */     GIR_RootConstrainSelectedInstOperands,
     /* 446988 */     // GIR_Coverage, 2561,
     /* 446988 */     GIR_EraseRootFromParent_Done,
     /* 446989 */   // Label 8706: @446989
     /* 446989 */   GIM_Try, /*On fail goto*//*Label 8707*/ GIMT_Encode4(447058), // Rule ID 6670 //
     /* 446994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 446997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 447005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 447009 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447013 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 447017 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 447022 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 447026 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 447030 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 447034 */     // MIs[2] Operand 1
     /* 447034 */     // No operand predicates
     /* 447034 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447038 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 447040 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64duplane16:{ *:[v8f16] } V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128_lo:{ *:[v8f16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)
     /* 447040 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 447043 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447045 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447047 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 447049 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447053 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 447056 */     GIR_RootConstrainSelectedInstOperands,
     /* 447057 */     // GIR_Coverage, 6670,
     /* 447057 */     GIR_EraseRootFromParent_Done,
     /* 447058 */   // Label 8707: @447058
     /* 447058 */   GIM_Try, /*On fail goto*//*Label 8708*/ GIMT_Encode4(447157), // Rule ID 6736 //
     /* 447063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 447070 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 447074 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 447078 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447083 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 447087 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447091 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447095 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447100 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447104 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 447106 */     // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447106 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447109 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447113 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447118 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447121 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447125 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447128 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447133 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 447141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447143 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447145 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
     /* 447149 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447152 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447155 */     GIR_RootConstrainSelectedInstOperands,
     /* 447156 */     // GIR_Coverage, 6736,
     /* 447156 */     GIR_EraseRootFromParent_Done,
     /* 447157 */   // Label 8708: @447157
     /* 447157 */   GIM_Try, /*On fail goto*//*Label 8709*/ GIMT_Encode4(447253), // Rule ID 6768 //
     /* 447162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447165 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 447169 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447173 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 447181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 447185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 447189 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447194 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447198 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447202 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 447204 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447204 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447207 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447211 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447216 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447219 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 447223 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447226 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447231 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 447239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447241 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447243 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 447245 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447248 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447251 */     GIR_RootConstrainSelectedInstOperands,
     /* 447252 */     // GIR_Coverage, 6768,
     /* 447252 */     GIR_EraseRootFromParent_Done,
     /* 447253 */   // Label 8709: @447253
     /* 447253 */   GIM_Try, /*On fail goto*//*Label 8710*/ GIMT_Encode4(447352), // Rule ID 6800 //
     /* 447258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447261 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 447265 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447269 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447273 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447278 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 447282 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 447286 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 447290 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447295 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447299 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 447301 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447301 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447304 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447308 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447313 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447316 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 447320 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447323 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447328 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 447336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447338 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447340 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 447344 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447347 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447350 */     GIR_RootConstrainSelectedInstOperands,
     /* 447351 */     // GIR_Coverage, 6800,
     /* 447351 */     GIR_EraseRootFromParent_Done,
     /* 447352 */   // Label 8710: @447352
     /* 447352 */   GIM_Try, /*On fail goto*//*Label 8711*/ GIMT_Encode4(447448), // Rule ID 6704 //
     /* 447357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447360 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447364 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 447368 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447372 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447376 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 447380 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUP),
     /* 447384 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
     /* 447388 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447393 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447397 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 447399 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm)), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447399 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447402 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447406 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447411 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447414 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 447418 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447421 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447426 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8i16_indexed),
     /* 447434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447436 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447438 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 447440 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447443 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447446 */     GIR_RootConstrainSelectedInstOperands,
     /* 447447 */     // GIR_Coverage, 6704,
     /* 447447 */     GIR_EraseRootFromParent_Done,
     /* 447448 */   // Label 8711: @447448
     /* 447448 */   GIM_Try, /*On fail goto*//*Label 8712*/ GIMT_Encode4(447532), // Rule ID 2563 //
     /* 447453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447456 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 447460 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 447464 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 447468 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447481 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 447483 */     // (strict_fma:{ *:[v8f16] } (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447483 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447486 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447490 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447495 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447498 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447502 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447505 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447510 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 447518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447520 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447522 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 447524 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447527 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447530 */     GIR_RootConstrainSelectedInstOperands,
     /* 447531 */     // GIR_Coverage, 2563,
     /* 447531 */     GIR_EraseRootFromParent_Done,
     /* 447532 */   // Label 8712: @447532
     /* 447532 */   GIM_Try, /*On fail goto*//*Label 8713*/ GIMT_Encode4(447582), // Rule ID 14393 //
     /* 447537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447540 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 447544 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447548 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447552 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447557 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447561 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447565 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 447567 */     // (strict_fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 447567 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 447570 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447572 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447574 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 447576 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447580 */     GIR_RootConstrainSelectedInstOperands,
     /* 447581 */     // GIR_Coverage, 14393,
     /* 447581 */     GIR_EraseRootFromParent_Done,
     /* 447582 */   // Label 8713: @447582
     /* 447582 */   GIM_Try, /*On fail goto*//*Label 8714*/ GIMT_Encode4(447666), // Rule ID 6672 //
     /* 447587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447590 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447594 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 447598 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUP),
     /* 447602 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
     /* 447606 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447611 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447615 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 447617 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (AArch64dup:{ *:[v8f16] } FPR16Op_lo:{ *:[f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8i16_indexed:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i32] }, FPR16Op_lo:{ *:[f16] }:$Rm, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 447617 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 447620 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 447624 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 447629 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 447632 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447636 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 447639 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447644 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16_loRegClassID),
     /* 447649 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8i16_indexed),
     /* 447652 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447654 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447656 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 447658 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 447661 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 447664 */     GIR_RootConstrainSelectedInstOperands,
     /* 447665 */     // GIR_Coverage, 6672,
     /* 447665 */     GIR_EraseRootFromParent_Done,
     /* 447666 */   // Label 8714: @447666
     /* 447666 */   GIM_Try, /*On fail goto*//*Label 8715*/ GIMT_Encode4(447716), // Rule ID 1335 //
     /* 447671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 447682 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
     /* 447686 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 447690 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447695 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447699 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 447701 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (fneg:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm), V128:{ *:[v8f16] }:$Rd)  =>  (FMLSv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 447701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLSv8f16),
     /* 447704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447706 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447708 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 447710 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 447714 */     GIR_RootConstrainSelectedInstOperands,
     /* 447715 */     // GIR_Coverage, 1335,
     /* 447715 */     GIR_EraseRootFromParent_Done,
     /* 447716 */   // Label 8715: @447716
     /* 447716 */   GIM_Try, /*On fail goto*//*Label 8716*/ GIMT_Encode4(447749), // Rule ID 1325 //
     /* 447721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447724 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447732 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447736 */     // (strict_fma:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rd)  =>  (FMLAv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rd, V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 447736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FMLAv8f16),
     /* 447739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 447741 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rd
     /* 447743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 447745 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rm
     /* 447747 */     GIR_RootConstrainSelectedInstOperands,
     /* 447748 */     // GIR_Coverage, 1325,
     /* 447748 */     GIR_EraseRootFromParent_Done,
     /* 447749 */   // Label 8716: @447749
     /* 447749 */   GIM_Reject,
     /* 447750 */ // Label 8701: @447750
     /* 447750 */ GIM_Reject,
     /* 447751 */ // Label 8533: @447751
     /* 447751 */ GIM_Reject,
     /* 447752 */ // Label 118: @447752
     /* 447752 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(11), /*)*//*default:*//*Label 8725*/ GIMT_Encode4(448051),
     /* 447763 */ /*GILLT_s16*//*Label 8717*/ GIMT_Encode4(447803),
     /* 447767 */ /*GILLT_s32*//*Label 8718*/ GIMT_Encode4(447834),
     /* 447771 */ /*GILLT_s64*//*Label 8719*/ GIMT_Encode4(447865), GIMT_Encode4(0),
     /* 447779 */ /*GILLT_v2s32*//*Label 8720*/ GIMT_Encode4(447896),
     /* 447783 */ /*GILLT_v2s64*//*Label 8721*/ GIMT_Encode4(447927),
     /* 447787 */ /*GILLT_v4s16*//*Label 8722*/ GIMT_Encode4(447958),
     /* 447791 */ /*GILLT_v4s32*//*Label 8723*/ GIMT_Encode4(447989), GIMT_Encode4(0),
     /* 447799 */ /*GILLT_v8s16*//*Label 8724*/ GIMT_Encode4(448020),
     /* 447803 */ // Label 8717: @447803
     /* 447803 */ GIM_Try, /*On fail goto*//*Label 8726*/ GIMT_Encode4(447833), // Rule ID 611 //
     /* 447808 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 447811 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 447814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 447818 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 447822 */   // (strict_fsqrt:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (FSQRTHr:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 447822 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTHr),
     /* 447827 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447831 */   GIR_RootConstrainSelectedInstOperands,
     /* 447832 */   // GIR_Coverage, 611,
     /* 447832 */   GIR_Done,
     /* 447833 */ // Label 8726: @447833
     /* 447833 */ GIM_Reject,
     /* 447834 */ // Label 8718: @447834
     /* 447834 */ GIM_Try, /*On fail goto*//*Label 8727*/ GIMT_Encode4(447864), // Rule ID 613 //
     /* 447839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 447842 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 447845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 447849 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 447853 */   // (strict_fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (FSQRTSr:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 447853 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTSr),
     /* 447858 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447862 */   GIR_RootConstrainSelectedInstOperands,
     /* 447863 */   // GIR_Coverage, 613,
     /* 447863 */   GIR_Done,
     /* 447864 */ // Label 8727: @447864
     /* 447864 */ GIM_Reject,
     /* 447865 */ // Label 8719: @447865
     /* 447865 */ GIM_Try, /*On fail goto*//*Label 8728*/ GIMT_Encode4(447895), // Rule ID 615 //
     /* 447870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
     /* 447873 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 447876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447880 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447884 */   // (strict_fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (FSQRTDr:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 447884 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTDr),
     /* 447889 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447893 */   GIR_RootConstrainSelectedInstOperands,
     /* 447894 */   // GIR_Coverage, 615,
     /* 447894 */   GIR_Done,
     /* 447895 */ // Label 8728: @447895
     /* 447895 */ GIM_Reject,
     /* 447896 */ // Label 8720: @447896
     /* 447896 */ GIM_Try, /*On fail goto*//*Label 8729*/ GIMT_Encode4(447926), // Rule ID 989 //
     /* 447901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 447904 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 447907 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447911 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447915 */   // (strict_fsqrt:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FSQRTv2f32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 447915 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f32),
     /* 447920 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447924 */   GIR_RootConstrainSelectedInstOperands,
     /* 447925 */   // GIR_Coverage, 989,
     /* 447925 */   GIR_Done,
     /* 447926 */ // Label 8729: @447926
     /* 447926 */ GIM_Reject,
     /* 447927 */ // Label 8721: @447927
     /* 447927 */ GIM_Try, /*On fail goto*//*Label 8730*/ GIMT_Encode4(447957), // Rule ID 993 //
     /* 447932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 447935 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 447938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447942 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 447946 */   // (strict_fsqrt:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FSQRTv2f64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn)
     /* 447946 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv2f64),
     /* 447951 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447955 */   GIR_RootConstrainSelectedInstOperands,
     /* 447956 */   // GIR_Coverage, 993,
     /* 447956 */   GIR_Done,
     /* 447957 */ // Label 8730: @447957
     /* 447957 */ GIM_Reject,
     /* 447958 */ // Label 8722: @447958
     /* 447958 */ GIM_Try, /*On fail goto*//*Label 8731*/ GIMT_Encode4(447988), // Rule ID 985 //
     /* 447963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 447966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 447969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447973 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 447977 */   // (strict_fsqrt:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FSQRTv4f16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 447977 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f16),
     /* 447982 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 447986 */   GIR_RootConstrainSelectedInstOperands,
     /* 447987 */   // GIR_Coverage, 985,
     /* 447987 */   GIR_Done,
     /* 447988 */ // Label 8731: @447988
     /* 447988 */ GIM_Reject,
     /* 447989 */ // Label 8723: @447989
     /* 447989 */ GIM_Try, /*On fail goto*//*Label 8732*/ GIMT_Encode4(448019), // Rule ID 991 //
     /* 447994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 447997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 448000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448004 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448008 */   // (strict_fsqrt:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FSQRTv4f32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 448008 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv4f32),
     /* 448013 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448017 */   GIR_RootConstrainSelectedInstOperands,
     /* 448018 */   // GIR_Coverage, 991,
     /* 448018 */   GIR_Done,
     /* 448019 */ // Label 8732: @448019
     /* 448019 */ GIM_Reject,
     /* 448020 */ // Label 8724: @448020
     /* 448020 */ GIM_Try, /*On fail goto*//*Label 8733*/ GIMT_Encode4(448050), // Rule ID 987 //
     /* 448025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448035 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448039 */   // (strict_fsqrt:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FSQRTv8f16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 448039 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FSQRTv8f16),
     /* 448044 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448048 */   GIR_RootConstrainSelectedInstOperands,
     /* 448049 */   // GIR_Coverage, 987,
     /* 448049 */   GIR_Done,
     /* 448050 */ // Label 8733: @448050
     /* 448050 */ GIM_Reject,
     /* 448051 */ // Label 8725: @448051
     /* 448051 */ GIM_Reject,
     /* 448052 */ // Label 119: @448052
     /* 448052 */ GIM_Try, /*On fail goto*//*Label 8734*/ GIMT_Encode4(448065), // Rule ID 7164 //
     /* 448057 */   // (trap)  =>  (BRK 1:{ *:[i32] })
     /* 448057 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 448060 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 448063 */   GIR_RootConstrainSelectedInstOperands,
     /* 448064 */   // GIR_Coverage, 7164,
     /* 448064 */   GIR_EraseRootFromParent_Done,
     /* 448065 */ // Label 8734: @448065
     /* 448065 */ GIM_Reject,
     /* 448066 */ // Label 120: @448066
     /* 448066 */ GIM_Try, /*On fail goto*//*Label 8735*/ GIMT_Encode4(448086), // Rule ID 7165 //
     /* 448071 */   // (debugtrap)  =>  (BRK 61440:{ *:[i32] })
     /* 448071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 448074 */   GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(61440),
     /* 448084 */   GIR_RootConstrainSelectedInstOperands,
     /* 448085 */   // GIR_Coverage, 7165,
     /* 448085 */   GIR_EraseRootFromParent_Done,
     /* 448086 */ // Label 8735: @448086
     /* 448086 */ GIM_Reject,
     /* 448087 */ // Label 121: @448087
     /* 448087 */ GIM_Try, /*On fail goto*//*Label 8736*/ GIMT_Encode4(448111), // Rule ID 7166 //
     /* 448092 */   // MIs[0] kind
     /* 448092 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 448095 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_ubsan_trap_imm),
     /* 448100 */   // (ubsantrap (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>><<X:ubsan_trap_xform>>:$kind)  =>  (BRK (ubsan_trap_xform:{ *:[i32] } (timm:{ *:[i32] })<<P:Predicate_ubsan_trap_imm>>:$kind))
     /* 448100 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BRK),
     /* 448103 */   GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, /*OperandRenderer*/GIMT_Encode2(GICR_renderUbsanTrap), // kind
     /* 448109 */   GIR_RootConstrainSelectedInstOperands,
     /* 448110 */   // GIR_Coverage, 7166,
     /* 448110 */   GIR_EraseRootFromParent_Done,
     /* 448111 */ // Label 8736: @448111
     /* 448111 */ GIM_Reject,
     /* 448112 */ // Label 122: @448112
     /* 448112 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8740*/ GIMT_Encode4(448421),
     /* 448123 */ /*GILLT_s16*//*Label 8737*/ GIMT_Encode4(448135),
     /* 448127 */ /*GILLT_s32*//*Label 8738*/ GIMT_Encode4(448288),
     /* 448131 */ /*GILLT_s64*//*Label 8739*/ GIMT_Encode4(448393),
     /* 448135 */ // Label 8737: @448135
     /* 448135 */ GIM_Try, /*On fail goto*//*Label 8741*/ GIMT_Encode4(448236), // Rule ID 6205 //
     /* 448140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 448143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448146 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448150 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448154 */   // (vecreduce_fadd:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FADDPv2i16p:{ *:[f16] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv8f16:{ *:[f128] } (FADDPv8f16:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn), V128:{ *:[v8f16] }:$Rn), dsub:{ *:[i32] }))
     /* 448154 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s128,
     /* 448157 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 448161 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448166 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448170 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448174 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 448176 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 448179 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv8f16),
     /* 448183 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448188 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 448191 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448195 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 448197 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 448200 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 448204 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448209 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 448216 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448221 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448226 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 448229 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 448231 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 448234 */   GIR_RootConstrainSelectedInstOperands,
     /* 448235 */   // GIR_Coverage, 6205,
     /* 448235 */   GIR_EraseRootFromParent_Done,
     /* 448236 */ // Label 8741: @448236
     /* 448236 */ GIM_Try, /*On fail goto*//*Label 8742*/ GIMT_Encode4(448287), // Rule ID 6206 //
     /* 448241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
     /* 448244 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 448247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448251 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448255 */   // (vecreduce_fadd:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FADDPv2i16p:{ *:[f16] } (FADDPv4f16:{ *:[i64] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rn))
     /* 448255 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 448258 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f16),
     /* 448262 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448267 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448271 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448275 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 448277 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i16p),
     /* 448280 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 448282 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 448285 */   GIR_RootConstrainSelectedInstOperands,
     /* 448286 */   // GIR_Coverage, 6206,
     /* 448286 */   GIR_EraseRootFromParent_Done,
     /* 448287 */ // Label 8742: @448287
     /* 448287 */ GIM_Reject,
     /* 448288 */ // Label 8738: @448288
     /* 448288 */ GIM_Try, /*On fail goto*//*Label 8743*/ GIMT_Encode4(448365), // Rule ID 6207 //
     /* 448293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 448296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448300 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448304 */   // (vecreduce_fadd:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } (EXTRACT_SUBREG:{ *:[i64] } (FADDPv4f32:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn), dsub:{ *:[i32] }))
     /* 448304 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s128,
     /* 448307 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::FADDPv4f32),
     /* 448311 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448316 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448320 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 448324 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 448326 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 448329 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 448333 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 448338 */   GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 448345 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448350 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448355 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 448358 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 448360 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 448363 */   GIR_RootConstrainSelectedInstOperands,
     /* 448364 */   // GIR_Coverage, 6207,
     /* 448364 */   GIR_EraseRootFromParent_Done,
     /* 448365 */ // Label 8743: @448365
     /* 448365 */ GIM_Try, /*On fail goto*//*Label 8744*/ GIMT_Encode4(448392), // Rule ID 6208 //
     /* 448370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 448373 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448377 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448381 */   // (vecreduce_fadd:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FADDPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 448381 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i32p),
     /* 448386 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448390 */   GIR_RootConstrainSelectedInstOperands,
     /* 448391 */   // GIR_Coverage, 6208,
     /* 448391 */   GIR_Done,
     /* 448392 */ // Label 8744: @448392
     /* 448392 */ GIM_Reject,
     /* 448393 */ // Label 8739: @448393
     /* 448393 */ GIM_Try, /*On fail goto*//*Label 8745*/ GIMT_Encode4(448420), // Rule ID 6209 //
     /* 448398 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 448401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448409 */   // (vecreduce_fadd:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FADDPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 448409 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FADDPv2i64p),
     /* 448414 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448418 */   GIR_RootConstrainSelectedInstOperands,
     /* 448419 */   // GIR_Coverage, 6209,
     /* 448419 */   GIR_Done,
     /* 448420 */ // Label 8745: @448420
     /* 448420 */ GIM_Reject,
     /* 448421 */ // Label 8740: @448421
     /* 448421 */ GIM_Reject,
     /* 448422 */ // Label 123: @448422
     /* 448422 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8749*/ GIMT_Encode4(448592),
     /* 448433 */ /*GILLT_s16*//*Label 8746*/ GIMT_Encode4(448445),
     /* 448437 */ /*GILLT_s32*//*Label 8747*/ GIMT_Encode4(448506),
     /* 448441 */ /*GILLT_s64*//*Label 8748*/ GIMT_Encode4(448564),
     /* 448445 */ // Label 8746: @448445
     /* 448445 */ GIM_Try, /*On fail goto*//*Label 8750*/ GIMT_Encode4(448475), // Rule ID 1973 //
     /* 448450 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448453 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 448456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448460 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448464 */   // (vecreduce_fmax:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMAXNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 448464 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i16v),
     /* 448469 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448473 */   GIR_RootConstrainSelectedInstOperands,
     /* 448474 */   // GIR_Coverage, 1973,
     /* 448474 */   GIR_Done,
     /* 448475 */ // Label 8750: @448475
     /* 448475 */ GIM_Try, /*On fail goto*//*Label 8751*/ GIMT_Encode4(448505), // Rule ID 1975 //
     /* 448480 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448490 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448494 */   // (vecreduce_fmax:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMAXNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 448494 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv8i16v),
     /* 448499 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448503 */   GIR_RootConstrainSelectedInstOperands,
     /* 448504 */   // GIR_Coverage, 1975,
     /* 448504 */   GIR_Done,
     /* 448505 */ // Label 8751: @448505
     /* 448505 */ GIM_Reject,
     /* 448506 */ // Label 8747: @448506
     /* 448506 */ GIM_Try, /*On fail goto*//*Label 8752*/ GIMT_Encode4(448536), // Rule ID 1977 //
     /* 448511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 448514 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 448517 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448521 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448525 */   // (vecreduce_fmax:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMAXNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 448525 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMVv4i32v),
     /* 448530 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448534 */   GIR_RootConstrainSelectedInstOperands,
     /* 448535 */   // GIR_Coverage, 1977,
     /* 448535 */   GIR_Done,
     /* 448536 */ // Label 8752: @448536
     /* 448536 */ GIM_Try, /*On fail goto*//*Label 8753*/ GIMT_Encode4(448563), // Rule ID 6215 //
     /* 448541 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 448544 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448548 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448552 */   // (vecreduce_fmax:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMAXNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 448552 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i32p),
     /* 448557 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448561 */   GIR_RootConstrainSelectedInstOperands,
     /* 448562 */   // GIR_Coverage, 6215,
     /* 448562 */   GIR_Done,
     /* 448563 */ // Label 8753: @448563
     /* 448563 */ GIM_Reject,
     /* 448564 */ // Label 8748: @448564
     /* 448564 */ GIM_Try, /*On fail goto*//*Label 8754*/ GIMT_Encode4(448591), // Rule ID 6217 //
     /* 448569 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 448572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448576 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448580 */   // (vecreduce_fmax:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMAXNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 448580 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXNMPv2i64p),
     /* 448585 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448589 */   GIR_RootConstrainSelectedInstOperands,
     /* 448590 */   // GIR_Coverage, 6217,
     /* 448590 */   GIR_Done,
     /* 448591 */ // Label 8754: @448591
     /* 448591 */ GIM_Reject,
     /* 448592 */ // Label 8749: @448592
     /* 448592 */ GIM_Reject,
     /* 448593 */ // Label 124: @448593
     /* 448593 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8758*/ GIMT_Encode4(448763),
     /* 448604 */ /*GILLT_s16*//*Label 8755*/ GIMT_Encode4(448616),
     /* 448608 */ /*GILLT_s32*//*Label 8756*/ GIMT_Encode4(448677),
     /* 448612 */ /*GILLT_s64*//*Label 8757*/ GIMT_Encode4(448735),
     /* 448616 */ // Label 8755: @448616
     /* 448616 */ GIM_Try, /*On fail goto*//*Label 8759*/ GIMT_Encode4(448646), // Rule ID 1985 //
     /* 448621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 448627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448631 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448635 */   // (vecreduce_fmin:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINNMVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 448635 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i16v),
     /* 448640 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448644 */   GIR_RootConstrainSelectedInstOperands,
     /* 448645 */   // GIR_Coverage, 1985,
     /* 448645 */   GIR_Done,
     /* 448646 */ // Label 8759: @448646
     /* 448646 */ GIM_Try, /*On fail goto*//*Label 8760*/ GIMT_Encode4(448676), // Rule ID 1987 //
     /* 448651 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448654 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448661 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448665 */   // (vecreduce_fmin:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINNMVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 448665 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv8i16v),
     /* 448670 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448674 */   GIR_RootConstrainSelectedInstOperands,
     /* 448675 */   // GIR_Coverage, 1987,
     /* 448675 */   GIR_Done,
     /* 448676 */ // Label 8760: @448676
     /* 448676 */ GIM_Reject,
     /* 448677 */ // Label 8756: @448677
     /* 448677 */ GIM_Try, /*On fail goto*//*Label 8761*/ GIMT_Encode4(448707), // Rule ID 1989 //
     /* 448682 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 448685 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 448688 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448692 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448696 */   // (vecreduce_fmin:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINNMVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 448696 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMVv4i32v),
     /* 448701 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448705 */   GIR_RootConstrainSelectedInstOperands,
     /* 448706 */   // GIR_Coverage, 1989,
     /* 448706 */   GIR_Done,
     /* 448707 */ // Label 8761: @448707
     /* 448707 */ GIM_Try, /*On fail goto*//*Label 8762*/ GIMT_Encode4(448734), // Rule ID 6223 //
     /* 448712 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 448715 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448719 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448723 */   // (vecreduce_fmin:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINNMPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 448723 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i32p),
     /* 448728 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448732 */   GIR_RootConstrainSelectedInstOperands,
     /* 448733 */   // GIR_Coverage, 6223,
     /* 448733 */   GIR_Done,
     /* 448734 */ // Label 8762: @448734
     /* 448734 */ GIM_Reject,
     /* 448735 */ // Label 8757: @448735
     /* 448735 */ GIM_Try, /*On fail goto*//*Label 8763*/ GIMT_Encode4(448762), // Rule ID 6225 //
     /* 448740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 448743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448747 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448751 */   // (vecreduce_fmin:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINNMPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 448751 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINNMPv2i64p),
     /* 448756 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448760 */   GIR_RootConstrainSelectedInstOperands,
     /* 448761 */   // GIR_Coverage, 6225,
     /* 448761 */   GIR_Done,
     /* 448762 */ // Label 8763: @448762
     /* 448762 */ GIM_Reject,
     /* 448763 */ // Label 8758: @448763
     /* 448763 */ GIM_Reject,
     /* 448764 */ // Label 125: @448764
     /* 448764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8767*/ GIMT_Encode4(448934),
     /* 448775 */ /*GILLT_s16*//*Label 8764*/ GIMT_Encode4(448787),
     /* 448779 */ /*GILLT_s32*//*Label 8765*/ GIMT_Encode4(448848),
     /* 448783 */ /*GILLT_s64*//*Label 8766*/ GIMT_Encode4(448906),
     /* 448787 */ // Label 8764: @448787
     /* 448787 */ GIM_Try, /*On fail goto*//*Label 8768*/ GIMT_Encode4(448817), // Rule ID 1979 //
     /* 448792 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448795 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 448798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448802 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448806 */   // (vecreduce_fmaximum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMAXVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 448806 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i16v),
     /* 448811 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448815 */   GIR_RootConstrainSelectedInstOperands,
     /* 448816 */   // GIR_Coverage, 1979,
     /* 448816 */   GIR_Done,
     /* 448817 */ // Label 8768: @448817
     /* 448817 */ GIM_Try, /*On fail goto*//*Label 8769*/ GIMT_Encode4(448847), // Rule ID 1981 //
     /* 448822 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448825 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448828 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448832 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448836 */   // (vecreduce_fmaximum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMAXVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 448836 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv8i16v),
     /* 448841 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448845 */   GIR_RootConstrainSelectedInstOperands,
     /* 448846 */   // GIR_Coverage, 1981,
     /* 448846 */   GIR_Done,
     /* 448847 */ // Label 8769: @448847
     /* 448847 */ GIM_Reject,
     /* 448848 */ // Label 8765: @448848
     /* 448848 */ GIM_Try, /*On fail goto*//*Label 8770*/ GIMT_Encode4(448878), // Rule ID 1983 //
     /* 448853 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 448856 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 448859 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448863 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448867 */   // (vecreduce_fmaximum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMAXVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 448867 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXVv4i32v),
     /* 448872 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448876 */   GIR_RootConstrainSelectedInstOperands,
     /* 448877 */   // GIR_Coverage, 1983,
     /* 448877 */   GIR_Done,
     /* 448878 */ // Label 8770: @448878
     /* 448878 */ GIM_Try, /*On fail goto*//*Label 8771*/ GIMT_Encode4(448905), // Rule ID 6219 //
     /* 448883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 448886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 448890 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448894 */   // (vecreduce_fmaximum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMAXPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 448894 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i32p),
     /* 448899 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448903 */   GIR_RootConstrainSelectedInstOperands,
     /* 448904 */   // GIR_Coverage, 6219,
     /* 448904 */   GIR_Done,
     /* 448905 */ // Label 8771: @448905
     /* 448905 */ GIM_Reject,
     /* 448906 */ // Label 8766: @448906
     /* 448906 */ GIM_Try, /*On fail goto*//*Label 8772*/ GIMT_Encode4(448933), // Rule ID 6221 //
     /* 448911 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 448914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 448922 */   // (vecreduce_fmaximum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMAXPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 448922 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMAXPv2i64p),
     /* 448927 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448931 */   GIR_RootConstrainSelectedInstOperands,
     /* 448932 */   // GIR_Coverage, 6221,
     /* 448932 */   GIR_Done,
     /* 448933 */ // Label 8772: @448933
     /* 448933 */ GIM_Reject,
     /* 448934 */ // Label 8767: @448934
     /* 448934 */ GIM_Reject,
     /* 448935 */ // Label 126: @448935
     /* 448935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 8776*/ GIMT_Encode4(449105),
     /* 448946 */ /*GILLT_s16*//*Label 8773*/ GIMT_Encode4(448958),
     /* 448950 */ /*GILLT_s32*//*Label 8774*/ GIMT_Encode4(449019),
     /* 448954 */ /*GILLT_s64*//*Label 8775*/ GIMT_Encode4(449077),
     /* 448958 */ // Label 8773: @448958
     /* 448958 */ GIM_Try, /*On fail goto*//*Label 8777*/ GIMT_Encode4(448988), // Rule ID 1991 //
     /* 448963 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 448969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 448973 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 448977 */   // (vecreduce_fminimum:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)  =>  (FMINVv4i16v:{ *:[f16] } V64:{ *:[v4f16] }:$Rn)
     /* 448977 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i16v),
     /* 448982 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 448986 */   GIR_RootConstrainSelectedInstOperands,
     /* 448987 */   // GIR_Coverage, 1991,
     /* 448987 */   GIR_Done,
     /* 448988 */ // Label 8777: @448988
     /* 448988 */ GIM_Try, /*On fail goto*//*Label 8778*/ GIMT_Encode4(449018), // Rule ID 1993 //
     /* 448993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 448996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 448999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449003 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449007 */   // (vecreduce_fminimum:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)  =>  (FMINVv8i16v:{ *:[f16] } V128:{ *:[v8f16] }:$Rn)
     /* 449007 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv8i16v),
     /* 449012 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 449016 */   GIR_RootConstrainSelectedInstOperands,
     /* 449017 */   // GIR_Coverage, 1993,
     /* 449017 */   GIR_Done,
     /* 449018 */ // Label 8778: @449018
     /* 449018 */ GIM_Reject,
     /* 449019 */ // Label 8774: @449019
     /* 449019 */ GIM_Try, /*On fail goto*//*Label 8779*/ GIMT_Encode4(449049), // Rule ID 1995 //
     /* 449024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 449027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 449030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449034 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449038 */   // (vecreduce_fminimum:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)  =>  (FMINVv4i32v:{ *:[f32] } V128:{ *:[v4f32] }:$Rn)
     /* 449038 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINVv4i32v),
     /* 449043 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 449047 */   GIR_RootConstrainSelectedInstOperands,
     /* 449048 */   // GIR_Coverage, 1995,
     /* 449048 */   GIR_Done,
     /* 449049 */ // Label 8779: @449049
     /* 449049 */ GIM_Try, /*On fail goto*//*Label 8780*/ GIMT_Encode4(449076), // Rule ID 6227 //
     /* 449054 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449057 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449061 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449065 */   // (vecreduce_fminimum:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)  =>  (FMINPv2i32p:{ *:[f32] } V64:{ *:[v2f32] }:$Rn)
     /* 449065 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i32p),
     /* 449070 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 449074 */   GIR_RootConstrainSelectedInstOperands,
     /* 449075 */   // GIR_Coverage, 6227,
     /* 449075 */   GIR_Done,
     /* 449076 */ // Label 8780: @449076
     /* 449076 */ GIM_Reject,
     /* 449077 */ // Label 8775: @449077
     /* 449077 */ GIM_Try, /*On fail goto*//*Label 8781*/ GIMT_Encode4(449104), // Rule ID 6229 //
     /* 449082 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 449085 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449089 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449093 */   // (vecreduce_fminimum:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)  =>  (FMINPv2i64p:{ *:[f64] } V128:{ *:[v2f64] }:$Rn)
     /* 449093 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FMINPv2i64p),
     /* 449098 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 449102 */   GIR_RootConstrainSelectedInstOperands,
     /* 449103 */   // GIR_Coverage, 6229,
     /* 449103 */   GIR_Done,
     /* 449104 */ // Label 8781: @449104
     /* 449104 */ GIM_Reject,
     /* 449105 */ // Label 8776: @449105
     /* 449105 */ GIM_Reject,
     /* 449106 */ // Label 127: @449106
     /* 449106 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(4), /*)*//*default:*//*Label 8786*/ GIMT_Encode4(450234),
     /* 449117 */ /*GILLT_s8*//*Label 8782*/ GIMT_Encode4(449133),
     /* 449121 */ /*GILLT_s16*//*Label 8783*/ GIMT_Encode4(449180),
     /* 449125 */ /*GILLT_s32*//*Label 8784*/ GIMT_Encode4(449595),
     /* 449129 */ /*GILLT_s64*//*Label 8785*/ GIMT_Encode4(450048),
     /* 449133 */ // Label 8782: @449133
     /* 449133 */ GIM_Try, /*On fail goto*//*Label 8787*/ GIMT_Encode4(449156), // Rule ID 6514 //
     /* 449138 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 449141 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 449145 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449149 */   // (vecreduce_add:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)  =>  (ADDVv8i8v:{ *:[i8] } V64:{ *:[v8i8] }:$Rn)
     /* 449149 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i8v),
     /* 449154 */   GIR_RootConstrainSelectedInstOperands,
     /* 449155 */   // GIR_Coverage, 6514,
     /* 449155 */   GIR_Done,
     /* 449156 */ // Label 8787: @449156
     /* 449156 */ GIM_Try, /*On fail goto*//*Label 8788*/ GIMT_Encode4(449179), // Rule ID 6515 //
     /* 449161 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 449164 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 449168 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449172 */   // (vecreduce_add:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)  =>  (ADDVv16i8v:{ *:[i8] } V128:{ *:[v16i8] }:$Rn)
     /* 449172 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv16i8v),
     /* 449177 */   GIR_RootConstrainSelectedInstOperands,
     /* 449178 */   // GIR_Coverage, 6515,
     /* 449178 */   GIR_Done,
     /* 449179 */ // Label 8788: @449179
     /* 449179 */ GIM_Reject,
     /* 449180 */ // Label 8783: @449180
     /* 449180 */ GIM_Try, /*On fail goto*//*Label 8789*/ GIMT_Encode4(449230), // Rule ID 6461 //
     /* 449185 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449188 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449192 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449196 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449200 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449203 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 449208 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 449212 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449217 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449219 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 449219 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 449222 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449224 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449228 */   GIR_RootConstrainSelectedInstOperands,
     /* 449229 */   // GIR_Coverage, 6461,
     /* 449229 */   GIR_EraseRootFromParent_Done,
     /* 449230 */ // Label 8789: @449230
     /* 449230 */ GIM_Try, /*On fail goto*//*Label 8790*/ GIMT_Encode4(449280), // Rule ID 6463 //
     /* 449235 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449238 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449242 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449246 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449250 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449253 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 449258 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 449262 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449267 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449269 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 449269 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 449272 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449274 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449278 */   GIR_RootConstrainSelectedInstOperands,
     /* 449279 */   // GIR_Coverage, 6463,
     /* 449279 */   GIR_EraseRootFromParent_Done,
     /* 449280 */ // Label 8790: @449280
     /* 449280 */ GIM_Try, /*On fail goto*//*Label 8791*/ GIMT_Encode4(449330), // Rule ID 6471 //
     /* 449285 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449292 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449296 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449300 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449303 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 449308 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 449312 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449317 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449319 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v4i16] } 685:{ *:[iPTR] }, V64:{ *:[v8i8] }:$Rn))  =>  (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 449319 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 449322 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449324 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449328 */   GIR_RootConstrainSelectedInstOperands,
     /* 449329 */   // GIR_Coverage, 6471,
     /* 449329 */   GIR_EraseRootFromParent_Done,
     /* 449330 */ // Label 8791: @449330
     /* 449330 */ GIM_Try, /*On fail goto*//*Label 8792*/ GIMT_Encode4(449380), // Rule ID 6473 //
     /* 449335 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449338 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449342 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449346 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449350 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449353 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 449358 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 449362 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449367 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449369 */   // (vecreduce_add:{ *:[i16] } (intrinsic_wo_chain:{ *:[v8i16] } 685:{ *:[iPTR] }, V128:{ *:[v16i8] }:$Rn))  =>  (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 449369 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 449372 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449374 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449378 */   GIR_RootConstrainSelectedInstOperands,
     /* 449379 */   // GIR_Coverage, 6473,
     /* 449379 */   GIR_EraseRootFromParent_Done,
     /* 449380 */ // Label 8792: @449380
     /* 449380 */ GIM_Try, /*On fail goto*//*Label 8793*/ GIMT_Encode4(449422), // Rule ID 6470 //
     /* 449385 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449392 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449396 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 449400 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 449404 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449409 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449411 */   // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 449411 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 449414 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449416 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449420 */   GIR_RootConstrainSelectedInstOperands,
     /* 449421 */   // GIR_Coverage, 6470,
     /* 449421 */   GIR_EraseRootFromParent_Done,
     /* 449422 */ // Label 8793: @449422
     /* 449422 */ GIM_Try, /*On fail goto*//*Label 8794*/ GIMT_Encode4(449464), // Rule ID 6472 //
     /* 449427 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449430 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449434 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449438 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 449442 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 449446 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449451 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449453 */   // (vecreduce_add:{ *:[i16] } (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 449453 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 449456 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449458 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449462 */   GIR_RootConstrainSelectedInstOperands,
     /* 449463 */   // GIR_Coverage, 6472,
     /* 449463 */   GIR_EraseRootFromParent_Done,
     /* 449464 */ // Label 8794: @449464
     /* 449464 */ GIM_Try, /*On fail goto*//*Label 8795*/ GIMT_Encode4(449506), // Rule ID 6460 //
     /* 449469 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449472 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449476 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449480 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 449484 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 449488 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449493 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449495 */   // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn))  =>  (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn)
     /* 449495 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 449498 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449500 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449504 */   GIR_RootConstrainSelectedInstOperands,
     /* 449505 */   // GIR_Coverage, 6460,
     /* 449505 */   GIR_EraseRootFromParent_Done,
     /* 449506 */ // Label 8795: @449506
     /* 449506 */ GIM_Try, /*On fail goto*//*Label 8796*/ GIMT_Encode4(449548), // Rule ID 6462 //
     /* 449511 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449514 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449518 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449522 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 449526 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 449530 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449535 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449537 */   // (vecreduce_add:{ *:[i16] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn))  =>  (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn)
     /* 449537 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 449540 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449542 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449546 */   GIR_RootConstrainSelectedInstOperands,
     /* 449547 */   // GIR_Coverage, 6462,
     /* 449547 */   GIR_EraseRootFromParent_Done,
     /* 449548 */ // Label 8796: @449548
     /* 449548 */ GIM_Try, /*On fail goto*//*Label 8797*/ GIMT_Encode4(449571), // Rule ID 6516 //
     /* 449553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449560 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449564 */   // (vecreduce_add:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)  =>  (ADDVv4i16v:{ *:[i16] } V64:{ *:[v4i16] }:$Rn)
     /* 449564 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i16v),
     /* 449569 */   GIR_RootConstrainSelectedInstOperands,
     /* 449570 */   // GIR_Coverage, 6516,
     /* 449570 */   GIR_Done,
     /* 449571 */ // Label 8797: @449571
     /* 449571 */ GIM_Try, /*On fail goto*//*Label 8798*/ GIMT_Encode4(449594), // Rule ID 6517 //
     /* 449576 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 449583 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449587 */   // (vecreduce_add:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)  =>  (ADDVv8i16v:{ *:[i16] } V128:{ *:[v8i16] }:$Rn)
     /* 449587 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv8i16v),
     /* 449592 */   GIR_RootConstrainSelectedInstOperands,
     /* 449593 */   // GIR_Coverage, 6517,
     /* 449593 */   GIR_Done,
     /* 449594 */ // Label 8798: @449594
     /* 449594 */ GIM_Reject,
     /* 449595 */ // Label 8784: @449595
     /* 449595 */ GIM_Try, /*On fail goto*//*Label 8799*/ GIMT_Encode4(449645), // Rule ID 6465 //
     /* 449600 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 449603 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449607 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449611 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449615 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449618 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 449623 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 449627 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449632 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449634 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 449634 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 449637 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449639 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449643 */   GIR_RootConstrainSelectedInstOperands,
     /* 449644 */   // GIR_Coverage, 6465,
     /* 449644 */   GIR_EraseRootFromParent_Done,
     /* 449645 */ // Label 8799: @449645
     /* 449645 */ GIM_Try, /*On fail goto*//*Label 8800*/ GIMT_Encode4(449695), // Rule ID 6467 //
     /* 449650 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449653 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449657 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449661 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449665 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449668 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 449673 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 449677 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449682 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449684 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 750:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 449684 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 449687 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449689 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449693 */   GIR_RootConstrainSelectedInstOperands,
     /* 449694 */   // GIR_Coverage, 6467,
     /* 449694 */   GIR_EraseRootFromParent_Done,
     /* 449695 */ // Label 8800: @449695
     /* 449695 */ GIM_Try, /*On fail goto*//*Label 8801*/ GIMT_Encode4(449745), // Rule ID 6475 //
     /* 449700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 449703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449707 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449711 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449715 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449718 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 449723 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 449727 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449732 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449734 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v4i32] } 685:{ *:[iPTR] }, V128:{ *:[v8i16] }:$Rn))  =>  (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 449734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 449737 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449739 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449743 */   GIR_RootConstrainSelectedInstOperands,
     /* 449744 */   // GIR_Coverage, 6475,
     /* 449744 */   GIR_EraseRootFromParent_Done,
     /* 449745 */ // Label 8801: @449745
     /* 449745 */ GIM_Try, /*On fail goto*//*Label 8802*/ GIMT_Encode4(449795), // Rule ID 6477 //
     /* 449750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449757 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449761 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 449765 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 449768 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 449773 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 449777 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449782 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449784 */   // (vecreduce_add:{ *:[i32] } (intrinsic_wo_chain:{ *:[v2i32] } 685:{ *:[iPTR] }, V64:{ *:[v4i16] }:$Rn))  =>  (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 449784 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 449787 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449789 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 449793 */   GIR_RootConstrainSelectedInstOperands,
     /* 449794 */   // GIR_Coverage, 6477,
     /* 449794 */   GIR_EraseRootFromParent_Done,
     /* 449795 */ // Label 8802: @449795
     /* 449795 */ GIM_Try, /*On fail goto*//*Label 8803*/ GIMT_Encode4(449837), // Rule ID 6474 //
     /* 449800 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 449803 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449807 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449811 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 449815 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449819 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449824 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449826 */   // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 449826 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 449829 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449831 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449835 */   GIR_RootConstrainSelectedInstOperands,
     /* 449836 */   // GIR_Coverage, 6474,
     /* 449836 */   GIR_EraseRootFromParent_Done,
     /* 449837 */ // Label 8803: @449837
     /* 449837 */ GIM_Try, /*On fail goto*//*Label 8804*/ GIMT_Encode4(449879), // Rule ID 6476 //
     /* 449842 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449849 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449853 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 449857 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449861 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449866 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449868 */   // (vecreduce_add:{ *:[i32] } (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 449868 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 449871 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449873 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449877 */   GIR_RootConstrainSelectedInstOperands,
     /* 449878 */   // GIR_Coverage, 6476,
     /* 449878 */   GIR_EraseRootFromParent_Done,
     /* 449879 */ // Label 8804: @449879
     /* 449879 */ GIM_Try, /*On fail goto*//*Label 8805*/ GIMT_Encode4(449921), // Rule ID 6464 //
     /* 449884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 449887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449891 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449895 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 449899 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 449903 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 449908 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449910 */   // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn))  =>  (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn)
     /* 449910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 449913 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449915 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449919 */   GIR_RootConstrainSelectedInstOperands,
     /* 449920 */   // GIR_Coverage, 6464,
     /* 449920 */   GIR_EraseRootFromParent_Done,
     /* 449921 */ // Label 8805: @449921
     /* 449921 */ GIM_Try, /*On fail goto*//*Label 8806*/ GIMT_Encode4(449963), // Rule ID 6466 //
     /* 449926 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449933 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 449937 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 449941 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 449945 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449950 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 449952 */   // (vecreduce_add:{ *:[i32] } (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn))  =>  (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn)
     /* 449952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 449955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 449957 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 449961 */   GIR_RootConstrainSelectedInstOperands,
     /* 449962 */   // GIR_Coverage, 6466,
     /* 449962 */   GIR_EraseRootFromParent_Done,
     /* 449963 */ // Label 8806: @449963
     /* 449963 */ GIM_Try, /*On fail goto*//*Label 8807*/ GIMT_Encode4(450024), // Rule ID 6518 //
     /* 449968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 449971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 449975 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 449979 */   // (vecreduce_add:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (ADDPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 449979 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 449982 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i32),
     /* 449986 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 449991 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 449995 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 449999 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 450001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 450004 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 450006 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 450013 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450018 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450023 */   // GIR_Coverage, 6518,
     /* 450023 */   GIR_EraseRootFromParent_Done,
     /* 450024 */ // Label 8807: @450024
     /* 450024 */ GIM_Try, /*On fail goto*//*Label 8808*/ GIMT_Encode4(450047), // Rule ID 6519 //
     /* 450029 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450032 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450036 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450040 */   // (vecreduce_add:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (ADDVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 450040 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDVv4i32v),
     /* 450045 */   GIR_RootConstrainSelectedInstOperands,
     /* 450046 */   // GIR_Coverage, 6519,
     /* 450046 */   GIR_Done,
     /* 450047 */ // Label 8808: @450047
     /* 450047 */ GIM_Reject,
     /* 450048 */ // Label 8785: @450048
     /* 450048 */ GIM_Try, /*On fail goto*//*Label 8809*/ GIMT_Encode4(450233),
     /* 450053 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 450056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450060 */   GIM_Try, /*On fail goto*//*Label 8810*/ GIMT_Encode4(450103), // Rule ID 6469 //
     /* 450065 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 450069 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 450073 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 450076 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 450081 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 450085 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450090 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 450092 */     // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 750:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 450092 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 450095 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 450097 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 450101 */     GIR_RootConstrainSelectedInstOperands,
     /* 450102 */     // GIR_Coverage, 6469,
     /* 450102 */     GIR_EraseRootFromParent_Done,
     /* 450103 */   // Label 8810: @450103
     /* 450103 */   GIM_Try, /*On fail goto*//*Label 8811*/ GIMT_Encode4(450146), // Rule ID 6479 //
     /* 450108 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 450112 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 450116 */     GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 450119 */     GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_saddlp),
     /* 450124 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 450128 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450133 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 450135 */     // (vecreduce_add:{ *:[i64] } (intrinsic_wo_chain:{ *:[v2i64] } 685:{ *:[iPTR] }, V128:{ *:[v4i32] }:$Rn))  =>  (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 450135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 450138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 450140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
     /* 450144 */     GIR_RootConstrainSelectedInstOperands,
     /* 450145 */     // GIR_Coverage, 6479,
     /* 450145 */     GIR_EraseRootFromParent_Done,
     /* 450146 */   // Label 8811: @450146
     /* 450146 */   GIM_Try, /*On fail goto*//*Label 8812*/ GIMT_Encode4(450181), // Rule ID 6478 //
     /* 450151 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 450155 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_SADDLP),
     /* 450159 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450163 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450168 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 450170 */     // (vecreduce_add:{ *:[i64] } (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 450170 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 450173 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 450175 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 450179 */     GIR_RootConstrainSelectedInstOperands,
     /* 450180 */     // GIR_Coverage, 6478,
     /* 450180 */     GIR_EraseRootFromParent_Done,
     /* 450181 */   // Label 8812: @450181
     /* 450181 */   GIM_Try, /*On fail goto*//*Label 8813*/ GIMT_Encode4(450216), // Rule ID 6468 //
     /* 450186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 450190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 450194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450198 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450203 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 450205 */     // (vecreduce_add:{ *:[i64] } (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn))  =>  (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn)
     /* 450205 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 450208 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 450210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 450214 */     GIR_RootConstrainSelectedInstOperands,
     /* 450215 */     // GIR_Coverage, 6468,
     /* 450215 */     GIR_EraseRootFromParent_Done,
     /* 450216 */   // Label 8813: @450216
     /* 450216 */   GIM_Try, /*On fail goto*//*Label 8814*/ GIMT_Encode4(450232), // Rule ID 6520 //
     /* 450221 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450225 */     // (vecreduce_add:{ *:[i64] } V128:{ *:[v2i64] }:$Rn)  =>  (ADDPv2i64p:{ *:[i64] } V128:{ *:[v2i64] }:$Rn)
     /* 450225 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ADDPv2i64p),
     /* 450230 */     GIR_RootConstrainSelectedInstOperands,
     /* 450231 */     // GIR_Coverage, 6520,
     /* 450231 */     GIR_Done,
     /* 450232 */   // Label 8814: @450232
     /* 450232 */   GIM_Reject,
     /* 450233 */ // Label 8809: @450233
     /* 450233 */ GIM_Reject,
     /* 450234 */ // Label 8786: @450234
     /* 450234 */ GIM_Reject,
     /* 450235 */ // Label 128: @450235
     /* 450235 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8818*/ GIMT_Encode4(450437),
     /* 450246 */ /*GILLT_s8*//*Label 8815*/ GIMT_Encode4(450258),
     /* 450250 */ /*GILLT_s16*//*Label 8816*/ GIMT_Encode4(450305),
     /* 450254 */ /*GILLT_s32*//*Label 8817*/ GIMT_Encode4(450352),
     /* 450258 */ // Label 8815: @450258
     /* 450258 */ GIM_Try, /*On fail goto*//*Label 8819*/ GIMT_Encode4(450281), // Rule ID 6611 //
     /* 450263 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 450266 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450270 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450274 */   // (vecreduce_smax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (SMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 450274 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i8v),
     /* 450279 */   GIR_RootConstrainSelectedInstOperands,
     /* 450280 */   // GIR_Coverage, 6611,
     /* 450280 */   GIR_Done,
     /* 450281 */ // Label 8819: @450281
     /* 450281 */ GIM_Try, /*On fail goto*//*Label 8820*/ GIMT_Encode4(450304), // Rule ID 6612 //
     /* 450286 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 450289 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450293 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450297 */   // (vecreduce_smax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (SMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 450297 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv16i8v),
     /* 450302 */   GIR_RootConstrainSelectedInstOperands,
     /* 450303 */   // GIR_Coverage, 6612,
     /* 450303 */   GIR_Done,
     /* 450304 */ // Label 8820: @450304
     /* 450304 */ GIM_Reject,
     /* 450305 */ // Label 8816: @450305
     /* 450305 */ GIM_Try, /*On fail goto*//*Label 8821*/ GIMT_Encode4(450328), // Rule ID 6613 //
     /* 450310 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 450313 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450317 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450321 */   // (vecreduce_smax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (SMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 450321 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i16v),
     /* 450326 */   GIR_RootConstrainSelectedInstOperands,
     /* 450327 */   // GIR_Coverage, 6613,
     /* 450327 */   GIR_Done,
     /* 450328 */ // Label 8821: @450328
     /* 450328 */ GIM_Try, /*On fail goto*//*Label 8822*/ GIMT_Encode4(450351), // Rule ID 6614 //
     /* 450333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 450336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450340 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450344 */   // (vecreduce_smax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (SMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 450344 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv8i16v),
     /* 450349 */   GIR_RootConstrainSelectedInstOperands,
     /* 450350 */   // GIR_Coverage, 6614,
     /* 450350 */   GIR_Done,
     /* 450351 */ // Label 8822: @450351
     /* 450351 */ GIM_Reject,
     /* 450352 */ // Label 8817: @450352
     /* 450352 */ GIM_Try, /*On fail goto*//*Label 8823*/ GIMT_Encode4(450375), // Rule ID 6615 //
     /* 450357 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450360 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450364 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450368 */   // (vecreduce_smax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (SMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 450368 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMAXVv4i32v),
     /* 450373 */   GIR_RootConstrainSelectedInstOperands,
     /* 450374 */   // GIR_Coverage, 6615,
     /* 450374 */   GIR_Done,
     /* 450375 */ // Label 8823: @450375
     /* 450375 */ GIM_Try, /*On fail goto*//*Label 8824*/ GIMT_Encode4(450436), // Rule ID 6616 //
     /* 450380 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 450383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450387 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450391 */   // (vecreduce_smax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (SMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 450391 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 450394 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMAXPv2i32),
     /* 450398 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 450403 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450407 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450411 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 450413 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 450416 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 450418 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 450425 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450430 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450435 */   // GIR_Coverage, 6616,
     /* 450435 */   GIR_EraseRootFromParent_Done,
     /* 450436 */ // Label 8824: @450436
     /* 450436 */ GIM_Reject,
     /* 450437 */ // Label 8818: @450437
     /* 450437 */ GIM_Reject,
     /* 450438 */ // Label 129: @450438
     /* 450438 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8828*/ GIMT_Encode4(450640),
     /* 450449 */ /*GILLT_s8*//*Label 8825*/ GIMT_Encode4(450461),
     /* 450453 */ /*GILLT_s16*//*Label 8826*/ GIMT_Encode4(450508),
     /* 450457 */ /*GILLT_s32*//*Label 8827*/ GIMT_Encode4(450555),
     /* 450461 */ // Label 8825: @450461
     /* 450461 */ GIM_Try, /*On fail goto*//*Label 8829*/ GIMT_Encode4(450484), // Rule ID 6605 //
     /* 450466 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 450469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450473 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450477 */   // (vecreduce_smin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (SMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 450477 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i8v),
     /* 450482 */   GIR_RootConstrainSelectedInstOperands,
     /* 450483 */   // GIR_Coverage, 6605,
     /* 450483 */   GIR_Done,
     /* 450484 */ // Label 8829: @450484
     /* 450484 */ GIM_Try, /*On fail goto*//*Label 8830*/ GIMT_Encode4(450507), // Rule ID 6606 //
     /* 450489 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 450492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450496 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450500 */   // (vecreduce_smin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (SMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 450500 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv16i8v),
     /* 450505 */   GIR_RootConstrainSelectedInstOperands,
     /* 450506 */   // GIR_Coverage, 6606,
     /* 450506 */   GIR_Done,
     /* 450507 */ // Label 8830: @450507
     /* 450507 */ GIM_Reject,
     /* 450508 */ // Label 8826: @450508
     /* 450508 */ GIM_Try, /*On fail goto*//*Label 8831*/ GIMT_Encode4(450531), // Rule ID 6607 //
     /* 450513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 450516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450520 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450524 */   // (vecreduce_smin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (SMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 450524 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i16v),
     /* 450529 */   GIR_RootConstrainSelectedInstOperands,
     /* 450530 */   // GIR_Coverage, 6607,
     /* 450530 */   GIR_Done,
     /* 450531 */ // Label 8831: @450531
     /* 450531 */ GIM_Try, /*On fail goto*//*Label 8832*/ GIMT_Encode4(450554), // Rule ID 6608 //
     /* 450536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 450539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450543 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450547 */   // (vecreduce_smin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (SMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 450547 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv8i16v),
     /* 450552 */   GIR_RootConstrainSelectedInstOperands,
     /* 450553 */   // GIR_Coverage, 6608,
     /* 450553 */   GIR_Done,
     /* 450554 */ // Label 8832: @450554
     /* 450554 */ GIM_Reject,
     /* 450555 */ // Label 8827: @450555
     /* 450555 */ GIM_Try, /*On fail goto*//*Label 8833*/ GIMT_Encode4(450578), // Rule ID 6609 //
     /* 450560 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450563 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450567 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450571 */   // (vecreduce_smin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (SMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 450571 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMINVv4i32v),
     /* 450576 */   GIR_RootConstrainSelectedInstOperands,
     /* 450577 */   // GIR_Coverage, 6609,
     /* 450577 */   GIR_Done,
     /* 450578 */ // Label 8833: @450578
     /* 450578 */ GIM_Try, /*On fail goto*//*Label 8834*/ GIMT_Encode4(450639), // Rule ID 6610 //
     /* 450583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 450586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450590 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450594 */   // (vecreduce_smin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (SMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 450594 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 450597 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SMINPv2i32),
     /* 450601 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 450606 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450610 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450614 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 450616 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 450619 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 450621 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 450628 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450633 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450638 */   // GIR_Coverage, 6610,
     /* 450638 */   GIR_EraseRootFromParent_Done,
     /* 450639 */ // Label 8834: @450639
     /* 450639 */ GIM_Reject,
     /* 450640 */ // Label 8828: @450640
     /* 450640 */ GIM_Reject,
     /* 450641 */ // Label 130: @450641
     /* 450641 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8838*/ GIMT_Encode4(450843),
     /* 450652 */ /*GILLT_s8*//*Label 8835*/ GIMT_Encode4(450664),
     /* 450656 */ /*GILLT_s16*//*Label 8836*/ GIMT_Encode4(450711),
     /* 450660 */ /*GILLT_s32*//*Label 8837*/ GIMT_Encode4(450758),
     /* 450664 */ // Label 8835: @450664
     /* 450664 */ GIM_Try, /*On fail goto*//*Label 8839*/ GIMT_Encode4(450687), // Rule ID 6599 //
     /* 450669 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 450672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450676 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450680 */   // (vecreduce_umax:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (UMAXVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 450680 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i8v),
     /* 450685 */   GIR_RootConstrainSelectedInstOperands,
     /* 450686 */   // GIR_Coverage, 6599,
     /* 450686 */   GIR_Done,
     /* 450687 */ // Label 8839: @450687
     /* 450687 */ GIM_Try, /*On fail goto*//*Label 8840*/ GIMT_Encode4(450710), // Rule ID 6600 //
     /* 450692 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 450695 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450699 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450703 */   // (vecreduce_umax:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (UMAXVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 450703 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv16i8v),
     /* 450708 */   GIR_RootConstrainSelectedInstOperands,
     /* 450709 */   // GIR_Coverage, 6600,
     /* 450709 */   GIR_Done,
     /* 450710 */ // Label 8840: @450710
     /* 450710 */ GIM_Reject,
     /* 450711 */ // Label 8836: @450711
     /* 450711 */ GIM_Try, /*On fail goto*//*Label 8841*/ GIMT_Encode4(450734), // Rule ID 6601 //
     /* 450716 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 450719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450723 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450727 */   // (vecreduce_umax:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (UMAXVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 450727 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i16v),
     /* 450732 */   GIR_RootConstrainSelectedInstOperands,
     /* 450733 */   // GIR_Coverage, 6601,
     /* 450733 */   GIR_Done,
     /* 450734 */ // Label 8841: @450734
     /* 450734 */ GIM_Try, /*On fail goto*//*Label 8842*/ GIMT_Encode4(450757), // Rule ID 6602 //
     /* 450739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 450742 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450746 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450750 */   // (vecreduce_umax:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (UMAXVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 450750 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv8i16v),
     /* 450755 */   GIR_RootConstrainSelectedInstOperands,
     /* 450756 */   // GIR_Coverage, 6602,
     /* 450756 */   GIR_Done,
     /* 450757 */ // Label 8842: @450757
     /* 450757 */ GIM_Reject,
     /* 450758 */ // Label 8837: @450758
     /* 450758 */ GIM_Try, /*On fail goto*//*Label 8843*/ GIMT_Encode4(450781), // Rule ID 6603 //
     /* 450763 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450770 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450774 */   // (vecreduce_umax:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (UMAXVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 450774 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMAXVv4i32v),
     /* 450779 */   GIR_RootConstrainSelectedInstOperands,
     /* 450780 */   // GIR_Coverage, 6603,
     /* 450780 */   GIR_Done,
     /* 450781 */ // Label 8843: @450781
     /* 450781 */ GIM_Try, /*On fail goto*//*Label 8844*/ GIMT_Encode4(450842), // Rule ID 6604 //
     /* 450786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 450789 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450793 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450797 */   // (vecreduce_umax:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (UMAXPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 450797 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 450800 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMAXPv2i32),
     /* 450804 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 450809 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450813 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 450817 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 450819 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 450822 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 450824 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 450831 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450836 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450841 */   // GIR_Coverage, 6604,
     /* 450841 */   GIR_EraseRootFromParent_Done,
     /* 450842 */ // Label 8844: @450842
     /* 450842 */ GIM_Reject,
     /* 450843 */ // Label 8838: @450843
     /* 450843 */ GIM_Reject,
     /* 450844 */ // Label 131: @450844
     /* 450844 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 8848*/ GIMT_Encode4(451046),
     /* 450855 */ /*GILLT_s8*//*Label 8845*/ GIMT_Encode4(450867),
     /* 450859 */ /*GILLT_s16*//*Label 8846*/ GIMT_Encode4(450914),
     /* 450863 */ /*GILLT_s32*//*Label 8847*/ GIMT_Encode4(450961),
     /* 450867 */ // Label 8845: @450867
     /* 450867 */ GIM_Try, /*On fail goto*//*Label 8849*/ GIMT_Encode4(450890), // Rule ID 6593 //
     /* 450872 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 450875 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450879 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450883 */   // (vecreduce_umin:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)  =>  (UMINVv8i8v:{ *:[i8] } FPR64:{ *:[v8i8] }:$Rn)
     /* 450883 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i8v),
     /* 450888 */   GIR_RootConstrainSelectedInstOperands,
     /* 450889 */   // GIR_Coverage, 6593,
     /* 450889 */   GIR_Done,
     /* 450890 */ // Label 8849: @450890
     /* 450890 */ GIM_Try, /*On fail goto*//*Label 8850*/ GIMT_Encode4(450913), // Rule ID 6594 //
     /* 450895 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 450898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 450902 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450906 */   // (vecreduce_umin:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)  =>  (UMINVv16i8v:{ *:[i8] } FPR128:{ *:[v16i8] }:$Rn)
     /* 450906 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv16i8v),
     /* 450911 */   GIR_RootConstrainSelectedInstOperands,
     /* 450912 */   // GIR_Coverage, 6594,
     /* 450912 */   GIR_Done,
     /* 450913 */ // Label 8850: @450913
     /* 450913 */ GIM_Reject,
     /* 450914 */ // Label 8846: @450914
     /* 450914 */ GIM_Try, /*On fail goto*//*Label 8851*/ GIMT_Encode4(450937), // Rule ID 6595 //
     /* 450919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 450922 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450926 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 450930 */   // (vecreduce_umin:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)  =>  (UMINVv4i16v:{ *:[i16] } FPR64:{ *:[v4i16] }:$Rn)
     /* 450930 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i16v),
     /* 450935 */   GIR_RootConstrainSelectedInstOperands,
     /* 450936 */   // GIR_Coverage, 6595,
     /* 450936 */   GIR_Done,
     /* 450937 */ // Label 8851: @450937
     /* 450937 */ GIM_Try, /*On fail goto*//*Label 8852*/ GIMT_Encode4(450960), // Rule ID 6596 //
     /* 450942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 450945 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 450949 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450953 */   // (vecreduce_umin:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)  =>  (UMINVv8i16v:{ *:[i16] } FPR128:{ *:[v8i16] }:$Rn)
     /* 450953 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv8i16v),
     /* 450958 */   GIR_RootConstrainSelectedInstOperands,
     /* 450959 */   // GIR_Coverage, 6596,
     /* 450959 */   GIR_Done,
     /* 450960 */ // Label 8852: @450960
     /* 450960 */ GIM_Reject,
     /* 450961 */ // Label 8847: @450961
     /* 450961 */ GIM_Try, /*On fail goto*//*Label 8853*/ GIMT_Encode4(450984), // Rule ID 6597 //
     /* 450966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 450969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450973 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 450977 */   // (vecreduce_umin:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)  =>  (UMINVv4i32v:{ *:[i32] } V128:{ *:[v4i32] }:$Rn)
     /* 450977 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMINVv4i32v),
     /* 450982 */   GIR_RootConstrainSelectedInstOperands,
     /* 450983 */   // GIR_Coverage, 6597,
     /* 450983 */   GIR_Done,
     /* 450984 */ // Label 8853: @450984
     /* 450984 */ GIM_Try, /*On fail goto*//*Label 8854*/ GIMT_Encode4(451045), // Rule ID 6598 //
     /* 450989 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 450992 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 450996 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451000 */   // (vecreduce_umin:{ *:[i32] } V64:{ *:[v2i32] }:$Rn)  =>  (EXTRACT_SUBREG:{ *:[i32] } (UMINPv2i32:{ *:[i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rn), ssub:{ *:[i32] })
     /* 451000 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 451003 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UMINPv2i32),
     /* 451007 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 451012 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 451016 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 451020 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 451022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 451025 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 451027 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::ssub),
     /* 451034 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 451039 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451044 */   // GIR_Coverage, 6598,
     /* 451044 */   GIR_EraseRootFromParent_Done,
     /* 451045 */ // Label 8854: @451045
     /* 451045 */ GIM_Reject,
     /* 451046 */ // Label 8848: @451046
     /* 451046 */ GIM_Reject,
     /* 451047 */ // Label 132: @451047
     /* 451047 */ GIM_Try, /*On fail goto*//*Label 8855*/ GIMT_Encode4(451186),
     /* 451052 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 451055 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 451059 */   GIM_Try, /*On fail goto*//*Label 8856*/ GIMT_Encode4(451093), // Rule ID 251 //
     /* 451064 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Windexed64),
     /* 451071 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Windexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend))  =>  (PRFMroW (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR32:{ *:[i32] }:$Rm, ro_Wextend64:{ *:[i32] }:$extend)
     /* 451071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroW),
     /* 451074 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 451076 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 451081 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 451086 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 451091 */     GIR_RootConstrainSelectedInstOperands,
     /* 451092 */     // GIR_Coverage, 251,
     /* 451092 */     GIR_EraseRootFromParent_Done,
     /* 451093 */   // Label 8856: @451093
     /* 451093 */   GIM_Try, /*On fail goto*//*Label 8857*/ GIMT_Encode4(451127), // Rule ID 252 //
     /* 451098 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ro_Xindexed64),
     /* 451105 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (ro_Xindexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend))  =>  (PRFMroX (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm, ro_Xextend64:{ *:[i32] }:$extend)
     /* 451105 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMroX),
     /* 451108 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 451110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 451115 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // Rm
     /* 451120 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // extend
     /* 451125 */     GIR_RootConstrainSelectedInstOperands,
     /* 451126 */     // GIR_Coverage, 252,
     /* 451126 */     GIR_EraseRootFromParent_Done,
     /* 451127 */   // Label 8857: @451127
     /* 451127 */   GIM_Try, /*On fail goto*//*Label 8858*/ GIMT_Encode4(451156), // Rule ID 267 //
     /* 451132 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_indexed64),
     /* 451139 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_indexed64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset))  =>  (PRFMui (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, uimm12s8:{ *:[i64] }:$offset)
     /* 451139 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFMui),
     /* 451142 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 451144 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 451149 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 451154 */     GIR_RootConstrainSelectedInstOperands,
     /* 451155 */     // GIR_Coverage, 267,
     /* 451155 */     GIR_EraseRootFromParent_Done,
     /* 451156 */   // Label 8858: @451156
     /* 451156 */   GIM_Try, /*On fail goto*//*Label 8859*/ GIMT_Encode4(451185), // Rule ID 288 //
     /* 451161 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_am_unscaled64),
     /* 451168 */     // (AArch64Prefetch (timm:{ *:[i32] }):$Rt, (am_unscaled64:{ *:[iPTR] } GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_simm9>>:$offset))  =>  (PRFUMi (timm:{ *:[i32] }):$Rt, GPR64sp:{ *:[i64] }:$Rn, (imm:{ *:[i64] }):$offset)
     /* 451168 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PRFUMi),
     /* 451171 */     GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 451173 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 451178 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
     /* 451183 */     GIR_RootConstrainSelectedInstOperands,
     /* 451184 */     // GIR_Coverage, 288,
     /* 451184 */     GIR_EraseRootFromParent_Done,
     /* 451185 */   // Label 8859: @451185
     /* 451185 */   GIM_Reject,
     /* 451186 */ // Label 8855: @451186
     /* 451186 */ GIM_Reject,
     /* 451187 */ // Label 133: @451187
     /* 451187 */ GIM_Try, /*On fail goto*//*Label 8860*/ GIMT_Encode4(451226), // Rule ID 7630 //
     /* 451192 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 451195 */   // MIs[0] Rt
     /* 451195 */   GIM_CheckIsImm, /*MI*/0, /*Op*/0,
     /* 451198 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_rprfop),
     /* 451203 */   // MIs[0] Rn
     /* 451203 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
     /* 451207 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 451211 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 451215 */   // (AArch64RangePrefetch (timm:{ *:[i32] })<<P:Predicate_rprfop>>:$Rt, GPR64sp:{ *:[i64] }:$Rn, GPR64:{ *:[i64] }:$Rm)  =>  (RPRFM (timm:{ *:[i32] })<<P:Predicate_rprfop>>:$Rt, GPR64:{ *:[i64] }:$Rm, GPR64sp:{ *:[i64] }:$Rn)
     /* 451215 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::RPRFM),
     /* 451218 */   GIR_RootToRootCopy, /*OpIdx*/0, // Rt
     /* 451220 */   GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 451222 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 451224 */   GIR_RootConstrainSelectedInstOperands,
     /* 451225 */   // GIR_Coverage, 7630,
     /* 451225 */   GIR_EraseRootFromParent_Done,
     /* 451226 */ // Label 8860: @451226
     /* 451226 */ GIM_Reject,
     /* 451227 */ // Label 134: @451227
     /* 451227 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 8873*/ GIMT_Encode4(452214),
     /* 451238 */ /*GILLT_s64*//*Label 8861*/ GIMT_Encode4(451322), GIMT_Encode4(0),
     /* 451246 */ /*GILLT_v2s32*//*Label 8862*/ GIMT_Encode4(451360),
     /* 451250 */ /*GILLT_v2s64*//*Label 8863*/ GIMT_Encode4(451398),
     /* 451254 */ /*GILLT_v4s16*//*Label 8864*/ GIMT_Encode4(451436),
     /* 451258 */ /*GILLT_v4s32*//*Label 8865*/ GIMT_Encode4(451474),
     /* 451262 */ /*GILLT_v8s8*//*Label 8866*/ GIMT_Encode4(451512),
     /* 451266 */ /*GILLT_v8s16*//*Label 8867*/ GIMT_Encode4(451550),
     /* 451270 */ /*GILLT_v16s8*//*Label 8868*/ GIMT_Encode4(451588), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 451290 */ /*GILLT_nxv2s64*//*Label 8869*/ GIMT_Encode4(451626), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 451302 */ /*GILLT_nxv4s32*//*Label 8870*/ GIMT_Encode4(451773), GIMT_Encode4(0),
     /* 451310 */ /*GILLT_nxv8s16*//*Label 8871*/ GIMT_Encode4(451920), GIMT_Encode4(0),
     /* 451318 */ /*GILLT_nxv16s8*//*Label 8872*/ GIMT_Encode4(452067),
     /* 451322 */ // Label 8861: @451322
     /* 451322 */ GIM_Try, /*On fail goto*//*Label 8874*/ GIMT_Encode4(451359), // Rule ID 5119 //
     /* 451327 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 451330 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 451333 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 451336 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451340 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451344 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451348 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451352 */   // (AArch64bsp:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)  =>  (BSPv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rd, V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)
     /* 451352 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 451357 */   GIR_RootConstrainSelectedInstOperands,
     /* 451358 */   // GIR_Coverage, 5119,
     /* 451358 */   GIR_Done,
     /* 451359 */ // Label 8874: @451359
     /* 451359 */ GIM_Reject,
     /* 451360 */ // Label 8862: @451360
     /* 451360 */ GIM_Try, /*On fail goto*//*Label 8875*/ GIMT_Encode4(451397), // Rule ID 5118 //
     /* 451365 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 451368 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 451371 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
     /* 451374 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451378 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451382 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451386 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451390 */   // (AArch64bsp:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (BSPv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 451390 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 451395 */   GIR_RootConstrainSelectedInstOperands,
     /* 451396 */   // GIR_Coverage, 5118,
     /* 451396 */   GIR_Done,
     /* 451397 */ // Label 8875: @451397
     /* 451397 */ GIM_Reject,
     /* 451398 */ // Label 8863: @451398
     /* 451398 */ GIM_Try, /*On fail goto*//*Label 8876*/ GIMT_Encode4(451435), // Rule ID 5123 //
     /* 451403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 451406 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 451409 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 451412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451416 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451420 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451424 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451428 */   // (AArch64bsp:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (BSPv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 451428 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 451433 */   GIR_RootConstrainSelectedInstOperands,
     /* 451434 */   // GIR_Coverage, 5123,
     /* 451434 */   GIR_Done,
     /* 451435 */ // Label 8876: @451435
     /* 451435 */ GIM_Reject,
     /* 451436 */ // Label 8864: @451436
     /* 451436 */ GIM_Try, /*On fail goto*//*Label 8877*/ GIMT_Encode4(451473), // Rule ID 5117 //
     /* 451441 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 451444 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 451447 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
     /* 451450 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451454 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451458 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451462 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451466 */   // (AArch64bsp:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (BSPv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 451466 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 451471 */   GIR_RootConstrainSelectedInstOperands,
     /* 451472 */   // GIR_Coverage, 5117,
     /* 451472 */   GIR_Done,
     /* 451473 */ // Label 8877: @451473
     /* 451473 */ GIM_Reject,
     /* 451474 */ // Label 8865: @451474
     /* 451474 */ GIM_Try, /*On fail goto*//*Label 8878*/ GIMT_Encode4(451511), // Rule ID 5122 //
     /* 451479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 451482 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 451485 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 451488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451492 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451496 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451500 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451504 */   // (AArch64bsp:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (BSPv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 451504 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 451509 */   GIR_RootConstrainSelectedInstOperands,
     /* 451510 */   // GIR_Coverage, 5122,
     /* 451510 */   GIR_Done,
     /* 451511 */ // Label 8878: @451511
     /* 451511 */ GIM_Reject,
     /* 451512 */ // Label 8866: @451512
     /* 451512 */ GIM_Try, /*On fail goto*//*Label 8879*/ GIMT_Encode4(451549), // Rule ID 5116 //
     /* 451517 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 451520 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 451523 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 451526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451534 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451538 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 451542 */   // (AArch64bsp:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (BSPv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 451542 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv8i8),
     /* 451547 */   GIR_RootConstrainSelectedInstOperands,
     /* 451548 */   // GIR_Coverage, 5116,
     /* 451548 */   GIR_Done,
     /* 451549 */ // Label 8879: @451549
     /* 451549 */ GIM_Reject,
     /* 451550 */ // Label 8867: @451550
     /* 451550 */ GIM_Try, /*On fail goto*//*Label 8880*/ GIMT_Encode4(451587), // Rule ID 5121 //
     /* 451555 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 451558 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 451561 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 451564 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451568 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451572 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451576 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451580 */   // (AArch64bsp:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (BSPv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 451580 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 451585 */   GIR_RootConstrainSelectedInstOperands,
     /* 451586 */   // GIR_Coverage, 5121,
     /* 451586 */   GIR_Done,
     /* 451587 */ // Label 8880: @451587
     /* 451587 */ GIM_Reject,
     /* 451588 */ // Label 8868: @451588
     /* 451588 */ GIM_Try, /*On fail goto*//*Label 8881*/ GIMT_Encode4(451625), // Rule ID 5120 //
     /* 451593 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 451596 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 451599 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 451602 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451606 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451610 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451614 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 451618 */   // (AArch64bsp:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (BSPv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 451618 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::BSPv16i8),
     /* 451623 */   GIR_RootConstrainSelectedInstOperands,
     /* 451624 */   // GIR_Coverage, 5120,
     /* 451624 */   GIR_Done,
     /* 451625 */ // Label 8881: @451625
     /* 451625 */ GIM_Reject,
     /* 451626 */ // Label 8869: @451626
     /* 451626 */ GIM_Try, /*On fail goto*//*Label 8882*/ GIMT_Encode4(451772),
     /* 451631 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 451634 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 451637 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv2s64,
     /* 451640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 451644 */   GIM_Try, /*On fail goto*//*Label 8883*/ GIMT_Encode4(451697), // Rule ID 12757 //
     /* 451649 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 451656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 451660 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 451664 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 451668 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 451672 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 451678 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 451680 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 451682 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, immAllOnesV:{ *:[nxv2i64] }), nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 451682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 451685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451687 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 451691 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 451693 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451695 */     GIR_RootConstrainSelectedInstOperands,
     /* 451696 */     // GIR_Coverage, 12757,
     /* 451696 */     GIR_EraseRootFromParent_Done,
     /* 451697 */   // Label 8883: @451697
     /* 451697 */   GIM_Try, /*On fail goto*//*Label 8884*/ GIMT_Encode4(451750), // Rule ID 12784 //
     /* 451702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 451709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 451713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 451717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 451721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 451725 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 451731 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 451733 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 451735 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, (xor:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op2, immAllOnesV:{ *:[nxv2i64] }))  =>  (BSL2N_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 451735 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 451738 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451740 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 451742 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 451746 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451748 */     GIR_RootConstrainSelectedInstOperands,
     /* 451749 */     // GIR_Coverage, 12784,
     /* 451749 */     GIR_EraseRootFromParent_Done,
     /* 451750 */   // Label 8884: @451750
     /* 451750 */   GIM_Try, /*On fail goto*//*Label 8885*/ GIMT_Encode4(451771), // Rule ID 12733 //
     /* 451755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451758 */     // (AArch64bsp:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op3, nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, ?:{ *:[nxv2i64] }:$Op3)
     /* 451758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 451761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451763 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 451765 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 451767 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451769 */     GIR_RootConstrainSelectedInstOperands,
     /* 451770 */     // GIR_Coverage, 12733,
     /* 451770 */     GIR_EraseRootFromParent_Done,
     /* 451771 */   // Label 8885: @451771
     /* 451771 */   GIM_Reject,
     /* 451772 */ // Label 8882: @451772
     /* 451772 */ GIM_Reject,
     /* 451773 */ // Label 8870: @451773
     /* 451773 */ GIM_Try, /*On fail goto*//*Label 8886*/ GIMT_Encode4(451919),
     /* 451778 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 451781 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 451784 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv4s32,
     /* 451787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 451791 */   GIM_Try, /*On fail goto*//*Label 8887*/ GIMT_Encode4(451844), // Rule ID 12755 //
     /* 451796 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 451803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 451807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 451811 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 451815 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 451819 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 451825 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 451827 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 451829 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, immAllOnesV:{ *:[nxv4i32] }), nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 451829 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 451832 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451834 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 451838 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 451840 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451842 */     GIR_RootConstrainSelectedInstOperands,
     /* 451843 */     // GIR_Coverage, 12755,
     /* 451843 */     GIR_EraseRootFromParent_Done,
     /* 451844 */   // Label 8887: @451844
     /* 451844 */   GIM_Try, /*On fail goto*//*Label 8888*/ GIMT_Encode4(451897), // Rule ID 12781 //
     /* 451849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 451856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 451860 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 451864 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 451868 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 451872 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 451878 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 451880 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 451882 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, (xor:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op2, immAllOnesV:{ *:[nxv4i32] }))  =>  (BSL2N_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 451882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 451885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451887 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 451889 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 451893 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451895 */     GIR_RootConstrainSelectedInstOperands,
     /* 451896 */     // GIR_Coverage, 12781,
     /* 451896 */     GIR_EraseRootFromParent_Done,
     /* 451897 */   // Label 8888: @451897
     /* 451897 */   GIM_Try, /*On fail goto*//*Label 8889*/ GIMT_Encode4(451918), // Rule ID 12731 //
     /* 451902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451905 */     // (AArch64bsp:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op3, nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, ?:{ *:[nxv4i32] }:$Op3)
     /* 451905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 451908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451910 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 451912 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 451914 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451916 */     GIR_RootConstrainSelectedInstOperands,
     /* 451917 */     // GIR_Coverage, 12731,
     /* 451917 */     GIR_EraseRootFromParent_Done,
     /* 451918 */   // Label 8889: @451918
     /* 451918 */   GIM_Reject,
     /* 451919 */ // Label 8886: @451919
     /* 451919 */ GIM_Reject,
     /* 451920 */ // Label 8871: @451920
     /* 451920 */ GIM_Try, /*On fail goto*//*Label 8890*/ GIMT_Encode4(452066),
     /* 451925 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 451928 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 451931 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 451934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 451938 */   GIM_Try, /*On fail goto*//*Label 8891*/ GIMT_Encode4(451991), // Rule ID 12753 //
     /* 451943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451946 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 451950 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 451954 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 451958 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 451962 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 451966 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 451972 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 451974 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 451976 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, immAllOnesV:{ *:[nxv8i16] }), nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 451976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 451979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 451981 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 451985 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 451987 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 451989 */     GIR_RootConstrainSelectedInstOperands,
     /* 451990 */     // GIR_Coverage, 12753,
     /* 451990 */     GIR_EraseRootFromParent_Done,
     /* 451991 */   // Label 8891: @451991
     /* 451991 */   GIM_Try, /*On fail goto*//*Label 8892*/ GIMT_Encode4(452044), // Rule ID 12778 //
     /* 451996 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 451999 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 452003 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 452007 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 452011 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 452015 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 452019 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 452025 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 452027 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 452029 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, (xor:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op2, immAllOnesV:{ *:[nxv8i16] }))  =>  (BSL2N_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 452029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 452032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 452034 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 452036 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 452040 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 452042 */     GIR_RootConstrainSelectedInstOperands,
     /* 452043 */     // GIR_Coverage, 12778,
     /* 452043 */     GIR_EraseRootFromParent_Done,
     /* 452044 */   // Label 8892: @452044
     /* 452044 */   GIM_Try, /*On fail goto*//*Label 8893*/ GIMT_Encode4(452065), // Rule ID 12729 //
     /* 452049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 452052 */     // (AArch64bsp:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op3, nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 452052 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 452055 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 452057 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 452059 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 452061 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 452063 */     GIR_RootConstrainSelectedInstOperands,
     /* 452064 */     // GIR_Coverage, 12729,
     /* 452064 */     GIR_EraseRootFromParent_Done,
     /* 452065 */   // Label 8893: @452065
     /* 452065 */   GIM_Reject,
     /* 452066 */ // Label 8890: @452066
     /* 452066 */ GIM_Reject,
     /* 452067 */ // Label 8872: @452067
     /* 452067 */ GIM_Try, /*On fail goto*//*Label 8894*/ GIMT_Encode4(452213),
     /* 452072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 452075 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 452078 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 452081 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 452085 */   GIM_Try, /*On fail goto*//*Label 8895*/ GIMT_Encode4(452138), // Rule ID 12751 //
     /* 452090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 452093 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 452097 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 452101 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 452105 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 452109 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 452113 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 452119 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 452121 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 452123 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, immAllOnesV:{ *:[nxv16i8] }), nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BSL1N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 452123 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL1N_ZZZZ),
     /* 452126 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 452128 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op1
     /* 452132 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 452134 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 452136 */     GIR_RootConstrainSelectedInstOperands,
     /* 452137 */     // GIR_Coverage, 12751,
     /* 452137 */     GIR_EraseRootFromParent_Done,
     /* 452138 */   // Label 8895: @452138
     /* 452138 */   GIM_Try, /*On fail goto*//*Label 8896*/ GIMT_Encode4(452191), // Rule ID 12775 //
     /* 452143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 452146 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 452150 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 452154 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 452158 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 452162 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 452166 */     GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 452172 */     GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
     /* 452174 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 452176 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, (xor:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op2, immAllOnesV:{ *:[nxv16i8] }))  =>  (BSL2N_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 452176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL2N_ZZZZ),
     /* 452179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 452181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 452183 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Op2
     /* 452187 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 452189 */     GIR_RootConstrainSelectedInstOperands,
     /* 452190 */     // GIR_Coverage, 12775,
     /* 452190 */     GIR_EraseRootFromParent_Done,
     /* 452191 */   // Label 8896: @452191
     /* 452191 */   GIM_Try, /*On fail goto*//*Label 8897*/ GIMT_Encode4(452212), // Rule ID 12727 //
     /* 452196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 452199 */     // (AArch64bsp:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op3, nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (BSL_ZZZZ:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 452199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::BSL_ZZZZ),
     /* 452202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 452204 */     GIR_RootToRootCopy, /*OpIdx*/2, // Op1
     /* 452206 */     GIR_RootToRootCopy, /*OpIdx*/3, // Op2
     /* 452208 */     GIR_RootToRootCopy, /*OpIdx*/1, // Op3
     /* 452210 */     GIR_RootConstrainSelectedInstOperands,
     /* 452211 */     // GIR_Coverage, 12727,
     /* 452211 */     GIR_EraseRootFromParent_Done,
     /* 452212 */   // Label 8897: @452212
     /* 452212 */   GIM_Reject,
     /* 452213 */ // Label 8894: @452213
     /* 452213 */ GIM_Reject,
     /* 452214 */ // Label 8873: @452214
     /* 452214 */ GIM_Reject,
     /* 452215 */ // Label 135: @452215
     /* 452215 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 8906*/ GIMT_Encode4(454194),
     /* 452226 */ /*GILLT_s64*//*Label 8898*/ GIMT_Encode4(452262), GIMT_Encode4(0),
     /* 452234 */ /*GILLT_v2s32*//*Label 8899*/ GIMT_Encode4(452457),
     /* 452238 */ /*GILLT_v2s64*//*Label 8900*/ GIMT_Encode4(452704),
     /* 452242 */ /*GILLT_v4s16*//*Label 8901*/ GIMT_Encode4(452951),
     /* 452246 */ /*GILLT_v4s32*//*Label 8902*/ GIMT_Encode4(453227),
     /* 452250 */ /*GILLT_v8s8*//*Label 8903*/ GIMT_Encode4(453474),
     /* 452254 */ /*GILLT_v8s16*//*Label 8904*/ GIMT_Encode4(453696),
     /* 452258 */ /*GILLT_v16s8*//*Label 8905*/ GIMT_Encode4(453972),
     /* 452262 */ // Label 8898: @452262
     /* 452262 */ GIM_Try, /*On fail goto*//*Label 8907*/ GIMT_Encode4(452456),
     /* 452267 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 452270 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452274 */   GIM_Try, /*On fail goto*//*Label 8908*/ GIMT_Encode4(452321), // Rule ID 7060 //
     /* 452279 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452283 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452287 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452290 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452294 */     // MIs[1] Rn
     /* 452294 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452298 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452303 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452305 */     // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452305 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 452308 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452310 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452314 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452319 */     GIR_RootConstrainSelectedInstOperands,
     /* 452320 */     // GIR_Coverage, 7060,
     /* 452320 */     GIR_EraseRootFromParent_Done,
     /* 452321 */   // Label 8908: @452321
     /* 452321 */   GIM_Try, /*On fail goto*//*Label 8909*/ GIMT_Encode4(452368), // Rule ID 7071 //
     /* 452326 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452330 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452334 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452337 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452341 */     // MIs[1] Rn
     /* 452341 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452345 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452350 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452352 */     // (AArch64dup:{ *:[v1f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1f64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 452355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452357 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452361 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452366 */     GIR_RootConstrainSelectedInstOperands,
     /* 452367 */     // GIR_Coverage, 7071,
     /* 452367 */     GIR_EraseRootFromParent_Done,
     /* 452368 */   // Label 8909: @452368
     /* 452368 */   GIM_Try, /*On fail goto*//*Label 8910*/ GIMT_Encode4(452415), // Rule ID 14262 //
     /* 452373 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452377 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452381 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452384 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452388 */     // MIs[1] Rn
     /* 452388 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452397 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452399 */     // (AArch64dup:{ *:[v1i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv1d:{ *:[v1i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv1d),
     /* 452402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452408 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452413 */     GIR_RootConstrainSelectedInstOperands,
     /* 452414 */     // GIR_Coverage, 14262,
     /* 452414 */     GIR_EraseRootFromParent_Done,
     /* 452415 */   // Label 8910: @452415
     /* 452415 */   GIM_Try, /*On fail goto*//*Label 8911*/ GIMT_Encode4(452435), // Rule ID 6231 //
     /* 452420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 452424 */     // (AArch64dup:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[v1i64] } GPR64:{ *:[i64] }:$Rn, FPR64:{ *:[i32] })
     /* 452424 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 452429 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452434 */     // GIR_Coverage, 6231,
     /* 452434 */     GIR_Done,
     /* 452435 */   // Label 8911: @452435
     /* 452435 */   GIM_Try, /*On fail goto*//*Label 8912*/ GIMT_Encode4(452455), // Rule ID 6232 //
     /* 452440 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452444 */     // (AArch64dup:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn)  =>  (COPY_TO_REGCLASS:{ *:[v1f64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[i32] })
     /* 452444 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 452449 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452454 */     // GIR_Coverage, 6232,
     /* 452454 */     GIR_Done,
     /* 452455 */   // Label 8912: @452455
     /* 452455 */   GIM_Reject,
     /* 452456 */ // Label 8907: @452456
     /* 452456 */ GIM_Reject,
     /* 452457 */ // Label 8899: @452457
     /* 452457 */ GIM_Try, /*On fail goto*//*Label 8913*/ GIMT_Encode4(452703),
     /* 452462 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 452465 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452469 */   GIM_Try, /*On fail goto*//*Label 8914*/ GIMT_Encode4(452516), // Rule ID 7057 //
     /* 452474 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452478 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452482 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452485 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452489 */     // MIs[1] Rn
     /* 452489 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452493 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452498 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452500 */     // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 452503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452505 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452509 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452514 */     GIR_RootConstrainSelectedInstOperands,
     /* 452515 */     // GIR_Coverage, 7057,
     /* 452515 */     GIR_EraseRootFromParent_Done,
     /* 452516 */   // Label 8914: @452516
     /* 452516 */   GIM_Try, /*On fail goto*//*Label 8915*/ GIMT_Encode4(452563), // Rule ID 7068 //
     /* 452521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452529 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452532 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452536 */     // MIs[1] Rn
     /* 452536 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452540 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452545 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452547 */     // (AArch64dup:{ *:[v2f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2f32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452547 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 452550 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452552 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452556 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452561 */     GIR_RootConstrainSelectedInstOperands,
     /* 452562 */     // GIR_Coverage, 7068,
     /* 452562 */     GIR_EraseRootFromParent_Done,
     /* 452563 */   // Label 8915: @452563
     /* 452563 */   GIM_Try, /*On fail goto*//*Label 8916*/ GIMT_Encode4(452610), // Rule ID 14259 //
     /* 452568 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452572 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452576 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452579 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452583 */     // MIs[1] Rn
     /* 452583 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452587 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452592 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452594 */     // (AArch64dup:{ *:[v2i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2s:{ *:[v2i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2s),
     /* 452597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452599 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452603 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452608 */     GIR_RootConstrainSelectedInstOperands,
     /* 452609 */     // GIR_Coverage, 14259,
     /* 452609 */     GIR_EraseRootFromParent_Done,
     /* 452610 */   // Label 8916: @452610
     /* 452610 */   GIM_Try, /*On fail goto*//*Label 8917*/ GIMT_Encode4(452629), // Rule ID 1947 //
     /* 452615 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 452618 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 452622 */     // (AArch64dup:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv2i32gpr:{ *:[v2i32] } GPR32:{ *:[i32] }:$Rn)
     /* 452622 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32gpr),
     /* 452627 */     GIR_RootConstrainSelectedInstOperands,
     /* 452628 */     // GIR_Coverage, 1947,
     /* 452628 */     GIR_Done,
     /* 452629 */   // Label 8917: @452629
     /* 452629 */   GIM_Try, /*On fail goto*//*Label 8918*/ GIMT_Encode4(452702), // Rule ID 6233 //
     /* 452634 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 452638 */     // (AArch64dup:{ *:[v2f32] } FPR32:{ *:[f32] }:$Rn)  =>  (DUPv2i32lane:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 452638 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 452641 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 452645 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 452650 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 452652 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 452655 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 452659 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 452664 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 452667 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 452671 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 452674 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 452679 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 452684 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 452689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 452692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 452694 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 452697 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 452700 */     GIR_RootConstrainSelectedInstOperands,
     /* 452701 */     // GIR_Coverage, 6233,
     /* 452701 */     GIR_EraseRootFromParent_Done,
     /* 452702 */   // Label 8918: @452702
     /* 452702 */   GIM_Reject,
     /* 452703 */ // Label 8913: @452703
     /* 452703 */ GIM_Reject,
     /* 452704 */ // Label 8900: @452704
     /* 452704 */ GIM_Try, /*On fail goto*//*Label 8919*/ GIMT_Encode4(452950),
     /* 452709 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 452712 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 452716 */   GIM_Try, /*On fail goto*//*Label 8920*/ GIMT_Encode4(452763), // Rule ID 7059 //
     /* 452721 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452725 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452729 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452732 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452736 */     // MIs[1] Rn
     /* 452736 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452740 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452745 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452747 */     // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452747 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 452750 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452752 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452761 */     GIR_RootConstrainSelectedInstOperands,
     /* 452762 */     // GIR_Coverage, 7059,
     /* 452762 */     GIR_EraseRootFromParent_Done,
     /* 452763 */   // Label 8920: @452763
     /* 452763 */   GIM_Try, /*On fail goto*//*Label 8921*/ GIMT_Encode4(452810), // Rule ID 7070 //
     /* 452768 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452772 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452776 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452779 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452783 */     // MIs[1] Rn
     /* 452783 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452787 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452792 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452794 */     // (AArch64dup:{ *:[v2f64] } (ld:{ *:[f64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2f64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452794 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 452797 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452799 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452803 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452808 */     GIR_RootConstrainSelectedInstOperands,
     /* 452809 */     // GIR_Coverage, 7070,
     /* 452809 */     GIR_EraseRootFromParent_Done,
     /* 452810 */   // Label 8921: @452810
     /* 452810 */   GIM_Try, /*On fail goto*//*Label 8922*/ GIMT_Encode4(452857), // Rule ID 14261 //
     /* 452815 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452819 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452823 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452826 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452830 */     // MIs[1] Rn
     /* 452830 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452834 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452839 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452841 */     // (AArch64dup:{ *:[v2i64] } (ld:{ *:[i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 452844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 452846 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 452850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 452855 */     GIR_RootConstrainSelectedInstOperands,
     /* 452856 */     // GIR_Coverage, 14261,
     /* 452856 */     GIR_EraseRootFromParent_Done,
     /* 452857 */   // Label 8922: @452857
     /* 452857 */   GIM_Try, /*On fail goto*//*Label 8923*/ GIMT_Encode4(452876), // Rule ID 1949 //
     /* 452862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 452865 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 452869 */     // (AArch64dup:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn)  =>  (DUPv2i64gpr:{ *:[v2i64] } GPR64:{ *:[i64] }:$Rn)
     /* 452869 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64gpr),
     /* 452874 */     GIR_RootConstrainSelectedInstOperands,
     /* 452875 */     // GIR_Coverage, 1949,
     /* 452875 */     GIR_Done,
     /* 452876 */   // Label 8923: @452876
     /* 452876 */   GIM_Try, /*On fail goto*//*Label 8924*/ GIMT_Encode4(452949), // Rule ID 6235 //
     /* 452881 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452885 */     // (AArch64dup:{ *:[v2f64] } FPR64:{ *:[f64] }:$Rn)  =>  (DUPv2i64lane:{ *:[v2f64] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR64:{ *:[f64] }:$Rn, dsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 452885 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 452888 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 452892 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 452897 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 452899 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 452902 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 452906 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 452911 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 452914 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 452918 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
     /* 452921 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 452926 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 452931 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 452939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 452941 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 452944 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 452947 */     GIR_RootConstrainSelectedInstOperands,
     /* 452948 */     // GIR_Coverage, 6235,
     /* 452948 */     GIR_EraseRootFromParent_Done,
     /* 452949 */   // Label 8924: @452949
     /* 452949 */   GIM_Reject,
     /* 452950 */ // Label 8919: @452950
     /* 452950 */ GIM_Reject,
     /* 452951 */ // Label 8901: @452951
     /* 452951 */ GIM_Try, /*On fail goto*//*Label 8925*/ GIMT_Encode4(453012), // Rule ID 7055 //
     /* 452956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 452959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 452963 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 452967 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 452971 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 452974 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 452978 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 452985 */   // MIs[1] Rn
     /* 452985 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 452989 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 452994 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 452996 */   // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>)  =>  (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 452996 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 452999 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453001 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453005 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453010 */   GIR_RootConstrainSelectedInstOperands,
     /* 453011 */   // GIR_Coverage, 7055,
     /* 453011 */   GIR_EraseRootFromParent_Done,
     /* 453012 */ // Label 8925: @453012
     /* 453012 */ GIM_Try, /*On fail goto*//*Label 8926*/ GIMT_Encode4(453066), // Rule ID 7072 //
     /* 453017 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453024 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453028 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453032 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453035 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453039 */   // MIs[1] Rn
     /* 453039 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453043 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453048 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453050 */   // (AArch64dup:{ *:[v4f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4h:{ *:[v4f16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453050 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 453053 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453055 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453059 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453064 */   GIR_RootConstrainSelectedInstOperands,
     /* 453065 */   // GIR_Coverage, 7072,
     /* 453065 */   GIR_EraseRootFromParent_Done,
     /* 453066 */ // Label 8926: @453066
     /* 453066 */ GIM_Try, /*On fail goto*//*Label 8927*/ GIMT_Encode4(453120), // Rule ID 14257 //
     /* 453071 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453078 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453082 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453086 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453089 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453093 */   // MIs[1] Rn
     /* 453093 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453097 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453102 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453104 */   // (AArch64dup:{ *:[v4i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4h:{ *:[v4i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453104 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4h),
     /* 453107 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453109 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453113 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453118 */   GIR_RootConstrainSelectedInstOperands,
     /* 453119 */   // GIR_Coverage, 14257,
     /* 453119 */   GIR_EraseRootFromParent_Done,
     /* 453120 */ // Label 8927: @453120
     /* 453120 */ GIM_Try, /*On fail goto*//*Label 8928*/ GIMT_Encode4(453146), // Rule ID 1945 //
     /* 453125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 453128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453135 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 453139 */   // (AArch64dup:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv4i16gpr:{ *:[v4i16] } GPR32:{ *:[i32] }:$Rn)
     /* 453139 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16gpr),
     /* 453144 */   GIR_RootConstrainSelectedInstOperands,
     /* 453145 */   // GIR_Coverage, 1945,
     /* 453145 */   GIR_Done,
     /* 453146 */ // Label 8928: @453146
     /* 453146 */ GIM_Try, /*On fail goto*//*Label 8929*/ GIMT_Encode4(453226), // Rule ID 6236 //
     /* 453151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 453162 */   // (AArch64dup:{ *:[v4f16] } FPR16:{ *:[f16] }:$Rn)  =>  (DUPv4i16lane:{ *:[v4f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 453162 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 453165 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 453169 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453174 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 453176 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 453179 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 453183 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453188 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 453191 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 453195 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 453198 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453203 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453208 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 453213 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 453216 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 453218 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 453221 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 453224 */   GIR_RootConstrainSelectedInstOperands,
     /* 453225 */   // GIR_Coverage, 6236,
     /* 453225 */   GIR_EraseRootFromParent_Done,
     /* 453226 */ // Label 8929: @453226
     /* 453226 */ GIM_Reject,
     /* 453227 */ // Label 8902: @453227
     /* 453227 */ GIM_Try, /*On fail goto*//*Label 8930*/ GIMT_Encode4(453473),
     /* 453232 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453239 */   GIM_Try, /*On fail goto*//*Label 8931*/ GIMT_Encode4(453286), // Rule ID 7058 //
     /* 453244 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453248 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453252 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453255 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453259 */     // MIs[1] Rn
     /* 453259 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453263 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453268 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453270 */     // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453270 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 453273 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453275 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453279 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453284 */     GIR_RootConstrainSelectedInstOperands,
     /* 453285 */     // GIR_Coverage, 7058,
     /* 453285 */     GIR_EraseRootFromParent_Done,
     /* 453286 */   // Label 8931: @453286
     /* 453286 */   GIM_Try, /*On fail goto*//*Label 8932*/ GIMT_Encode4(453333), // Rule ID 7069 //
     /* 453291 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453295 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453299 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453302 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453306 */     // MIs[1] Rn
     /* 453306 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453310 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453315 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453317 */     // (AArch64dup:{ *:[v4f32] } (ld:{ *:[f32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4f32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453317 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 453320 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453326 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453331 */     GIR_RootConstrainSelectedInstOperands,
     /* 453332 */     // GIR_Coverage, 7069,
     /* 453332 */     GIR_EraseRootFromParent_Done,
     /* 453333 */   // Label 8932: @453333
     /* 453333 */   GIM_Try, /*On fail goto*//*Label 8933*/ GIMT_Encode4(453380), // Rule ID 14260 //
     /* 453338 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453342 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453346 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453349 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453353 */     // MIs[1] Rn
     /* 453353 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453357 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453362 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453364 */     // (AArch64dup:{ *:[v4i32] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 453367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453373 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453378 */     GIR_RootConstrainSelectedInstOperands,
     /* 453379 */     // GIR_Coverage, 14260,
     /* 453379 */     GIR_EraseRootFromParent_Done,
     /* 453380 */   // Label 8933: @453380
     /* 453380 */   GIM_Try, /*On fail goto*//*Label 8934*/ GIMT_Encode4(453399), // Rule ID 1948 //
     /* 453385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 453388 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 453392 */     // (AArch64dup:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv4i32gpr:{ *:[v4i32] } GPR32:{ *:[i32] }:$Rn)
     /* 453392 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32gpr),
     /* 453397 */     GIR_RootConstrainSelectedInstOperands,
     /* 453398 */     // GIR_Coverage, 1948,
     /* 453398 */     GIR_Done,
     /* 453399 */   // Label 8934: @453399
     /* 453399 */   GIM_Try, /*On fail goto*//*Label 8935*/ GIMT_Encode4(453472), // Rule ID 6234 //
     /* 453404 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 453408 */     // (AArch64dup:{ *:[v4f32] } FPR32:{ *:[f32] }:$Rn)  =>  (DUPv4i32lane:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), FPR32:{ *:[f32] }:$Rn, ssub:{ *:[i32] }), 0:{ *:[i64] })
     /* 453408 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 453411 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 453415 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453420 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 453422 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 453425 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 453429 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453434 */     GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 453437 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 453441 */     GIR_AddImm8, /*InsnID*/1, /*Imm*/18,
     /* 453444 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453449 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453454 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 453459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 453462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 453464 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 453467 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 453470 */     GIR_RootConstrainSelectedInstOperands,
     /* 453471 */     // GIR_Coverage, 6234,
     /* 453471 */     GIR_EraseRootFromParent_Done,
     /* 453472 */   // Label 8935: @453472
     /* 453472 */   GIM_Reject,
     /* 453473 */ // Label 8930: @453473
     /* 453473 */ GIM_Reject,
     /* 453474 */ // Label 8903: @453474
     /* 453474 */ GIM_Try, /*On fail goto*//*Label 8936*/ GIMT_Encode4(453535), // Rule ID 7053 //
     /* 453479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453486 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453490 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453494 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453497 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453501 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 453508 */   // MIs[1] Rn
     /* 453508 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453512 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453517 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453519 */   // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>)  =>  (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453519 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
     /* 453522 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453524 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453528 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453533 */   GIR_RootConstrainSelectedInstOperands,
     /* 453534 */   // GIR_Coverage, 7053,
     /* 453534 */   GIR_EraseRootFromParent_Done,
     /* 453535 */ // Label 8936: @453535
     /* 453535 */ GIM_Try, /*On fail goto*//*Label 8937*/ GIMT_Encode4(453589), // Rule ID 14255 //
     /* 453540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 453543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453547 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453551 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453555 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453558 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453562 */   // MIs[1] Rn
     /* 453562 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453566 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453571 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453573 */   // (AArch64dup:{ *:[v8i8] } (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8b:{ *:[v8i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453573 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8b),
     /* 453576 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453578 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453582 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453587 */   GIR_RootConstrainSelectedInstOperands,
     /* 453588 */   // GIR_Coverage, 14255,
     /* 453588 */   GIR_EraseRootFromParent_Done,
     /* 453589 */ // Label 8937: @453589
     /* 453589 */ GIM_Try, /*On fail goto*//*Label 8938*/ GIMT_Encode4(453615), // Rule ID 1943 //
     /* 453594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 453597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453604 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 453608 */   // (AArch64dup:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv8i8gpr:{ *:[v8i8] } GPR32:{ *:[i32] }:$Rn)
     /* 453608 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8gpr),
     /* 453613 */   GIR_RootConstrainSelectedInstOperands,
     /* 453614 */   // GIR_Coverage, 1943,
     /* 453614 */   GIR_Done,
     /* 453615 */ // Label 8938: @453615
     /* 453615 */ GIM_Try, /*On fail goto*//*Label 8939*/ GIMT_Encode4(453695), // Rule ID 6238 //
     /* 453620 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 453623 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 453627 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 453631 */   // (AArch64dup:{ *:[v8i8] } FPR8:{ *:[i8] }:$Rn)  =>  (DUPv8i8lane:{ *:[v8i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rn, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 453631 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 453634 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 453638 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453643 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 453645 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 453648 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 453652 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453657 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 453660 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 453664 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 453667 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453672 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453677 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 453682 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8lane),
     /* 453685 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 453687 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 453690 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 453693 */   GIR_RootConstrainSelectedInstOperands,
     /* 453694 */   // GIR_Coverage, 6238,
     /* 453694 */   GIR_EraseRootFromParent_Done,
     /* 453695 */ // Label 8939: @453695
     /* 453695 */ GIM_Reject,
     /* 453696 */ // Label 8904: @453696
     /* 453696 */ GIM_Try, /*On fail goto*//*Label 8940*/ GIMT_Encode4(453757), // Rule ID 7056 //
     /* 453701 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453708 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453712 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453716 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453719 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453723 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 453730 */   // MIs[1] Rn
     /* 453730 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453734 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453739 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453741 */   // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>>)  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 453744 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453746 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453750 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453755 */   GIR_RootConstrainSelectedInstOperands,
     /* 453756 */   // GIR_Coverage, 7056,
     /* 453756 */   GIR_EraseRootFromParent_Done,
     /* 453757 */ // Label 8940: @453757
     /* 453757 */ GIM_Try, /*On fail goto*//*Label 8941*/ GIMT_Encode4(453811), // Rule ID 7073 //
     /* 453762 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453765 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453769 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453773 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453777 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453780 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453784 */   // MIs[1] Rn
     /* 453784 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453788 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453793 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453795 */   // (AArch64dup:{ *:[v8f16] } (ld:{ *:[f16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8h:{ *:[v8f16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453795 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 453798 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453800 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453804 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453809 */   GIR_RootConstrainSelectedInstOperands,
     /* 453810 */   // GIR_Coverage, 7073,
     /* 453810 */   GIR_EraseRootFromParent_Done,
     /* 453811 */ // Label 8941: @453811
     /* 453811 */ GIM_Try, /*On fail goto*//*Label 8942*/ GIMT_Encode4(453865), // Rule ID 14258 //
     /* 453816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453819 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453823 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453827 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453831 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453834 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453838 */   // MIs[1] Rn
     /* 453838 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 453842 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 453847 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 453849 */   // (AArch64dup:{ *:[v8i16] } (ld:{ *:[i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 453849 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 453852 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 453854 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 453858 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 453863 */   GIR_RootConstrainSelectedInstOperands,
     /* 453864 */   // GIR_Coverage, 14258,
     /* 453864 */   GIR_EraseRootFromParent_Done,
     /* 453865 */ // Label 8942: @453865
     /* 453865 */ GIM_Try, /*On fail goto*//*Label 8943*/ GIMT_Encode4(453891), // Rule ID 1946 //
     /* 453870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 453873 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453876 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453880 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 453884 */   // (AArch64dup:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv8i16gpr:{ *:[v8i16] } GPR32:{ *:[i32] }:$Rn)
     /* 453884 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16gpr),
     /* 453889 */   GIR_RootConstrainSelectedInstOperands,
     /* 453890 */   // GIR_Coverage, 1946,
     /* 453890 */   GIR_Done,
     /* 453891 */ // Label 8943: @453891
     /* 453891 */ GIM_Try, /*On fail goto*//*Label 8944*/ GIMT_Encode4(453971), // Rule ID 6237 //
     /* 453896 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 453899 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453903 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 453907 */   // (AArch64dup:{ *:[v8f16] } FPR16:{ *:[f16] }:$Rn)  =>  (DUPv8i16lane:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), FPR16:{ *:[f16] }:$Rn, hsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 453907 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 453910 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 453914 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453919 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 453921 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 453924 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 453928 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 453933 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 453936 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 453940 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/9,
     /* 453943 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453948 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453953 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 453958 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 453961 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 453963 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 453966 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 453969 */   GIR_RootConstrainSelectedInstOperands,
     /* 453970 */   // GIR_Coverage, 6237,
     /* 453970 */   GIR_EraseRootFromParent_Done,
     /* 453971 */ // Label 8944: @453971
     /* 453971 */ GIM_Reject,
     /* 453972 */ // Label 8905: @453972
     /* 453972 */ GIM_Try, /*On fail goto*//*Label 8945*/ GIMT_Encode4(454033), // Rule ID 7054 //
     /* 453977 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 453980 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 453984 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 453988 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 453992 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 453995 */   GIM_CheckMemorySizeLessThanLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 453999 */   GIM_CheckMemorySizeEqualTo, /*MI*/1, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 454006 */   // MIs[1] Rn
     /* 454006 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454010 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454015 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454017 */   // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>>)  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454017 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 454020 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454022 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454026 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454031 */   GIR_RootConstrainSelectedInstOperands,
     /* 454032 */   // GIR_Coverage, 7054,
     /* 454032 */   GIR_EraseRootFromParent_Done,
     /* 454033 */ // Label 8945: @454033
     /* 454033 */ GIM_Try, /*On fail goto*//*Label 8946*/ GIMT_Encode4(454087), // Rule ID 14256 //
     /* 454038 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 454041 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454045 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 454049 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 454053 */   GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 454056 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 454060 */   // MIs[1] Rn
     /* 454060 */   GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454064 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454069 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454071 */   // (AArch64dup:{ *:[v16i8] } (ld:{ *:[i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>)  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454071 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 454074 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454076 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454080 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454085 */   GIR_RootConstrainSelectedInstOperands,
     /* 454086 */   // GIR_Coverage, 14256,
     /* 454086 */   GIR_EraseRootFromParent_Done,
     /* 454087 */ // Label 8946: @454087
     /* 454087 */ GIM_Try, /*On fail goto*//*Label 8947*/ GIMT_Encode4(454113), // Rule ID 1944 //
     /* 454092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454095 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 454098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454102 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 454106 */   // (AArch64dup:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn)  =>  (DUPv16i8gpr:{ *:[v16i8] } GPR32:{ *:[i32] }:$Rn)
     /* 454106 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8gpr),
     /* 454111 */   GIR_RootConstrainSelectedInstOperands,
     /* 454112 */   // GIR_Coverage, 1944,
     /* 454112 */   GIR_Done,
     /* 454113 */ // Label 8947: @454113
     /* 454113 */ GIM_Try, /*On fail goto*//*Label 8948*/ GIMT_Encode4(454193), // Rule ID 6239 //
     /* 454118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8,
     /* 454121 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454125 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 454129 */   // (AArch64dup:{ *:[v16i8] } FPR8:{ *:[i8] }:$Rn)  =>  (DUPv16i8lane:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), FPR8:{ *:[i8] }:$Rn, bsub:{ *:[i32] }), 0:{ *:[i64] })
     /* 454129 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 454132 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 454136 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 454141 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 454143 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 454146 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 454150 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 454155 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 454158 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 454162 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
     /* 454165 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454170 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454175 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(AArch64::FPR8RegClassID),
     /* 454180 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8lane),
     /* 454183 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454185 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 454188 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 454191 */   GIR_RootConstrainSelectedInstOperands,
     /* 454192 */   // GIR_Coverage, 6239,
     /* 454192 */   GIR_EraseRootFromParent_Done,
     /* 454193 */ // Label 8948: @454193
     /* 454193 */ GIM_Reject,
     /* 454194 */ // Label 8906: @454194
     /* 454194 */ GIM_Reject,
     /* 454195 */ // Label 136: @454195
     /* 454195 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 8951*/ GIMT_Encode4(454449),
     /* 454206 */ /*GILLT_v4s16*//*Label 8949*/ GIMT_Encode4(454222), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 454218 */ /*GILLT_v8s16*//*Label 8950*/ GIMT_Encode4(454308),
     /* 454222 */ // Label 8949: @454222
     /* 454222 */ GIM_Try, /*On fail goto*//*Label 8952*/ GIMT_Encode4(454307),
     /* 454227 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 454230 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 454237 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454241 */   GIM_Try, /*On fail goto*//*Label 8953*/ GIMT_Encode4(454275), // Rule ID 1953 //
     /* 454246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454257 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 454261 */     // MIs[1] Operand 1
     /* 454261 */     // No operand predicates
     /* 454261 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454263 */     // (AArch64duplane16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPv4i16lane:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454263 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 454266 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454268 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454270 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454273 */     GIR_RootConstrainSelectedInstOperands,
     /* 454274 */     // GIR_Coverage, 1953,
     /* 454274 */     GIR_EraseRootFromParent_Done,
     /* 454275 */   // Label 8953: @454275
     /* 454275 */   GIM_Try, /*On fail goto*//*Label 8954*/ GIMT_Encode4(454306), // Rule ID 6240 //
     /* 454280 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454284 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454288 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 454292 */     // MIs[1] Operand 1
     /* 454292 */     // No operand predicates
     /* 454292 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454294 */     // (AArch64duplane16:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (DUPv4i16lane:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
     /* 454294 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i16lane),
     /* 454297 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454299 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454301 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 454304 */     GIR_RootConstrainSelectedInstOperands,
     /* 454305 */     // GIR_Coverage, 6240,
     /* 454305 */     GIR_EraseRootFromParent_Done,
     /* 454306 */   // Label 8954: @454306
     /* 454306 */   GIM_Reject,
     /* 454307 */ // Label 8952: @454307
     /* 454307 */ GIM_Reject,
     /* 454308 */ // Label 8950: @454308
     /* 454308 */ GIM_Try, /*On fail goto*//*Label 8955*/ GIMT_Encode4(454448),
     /* 454313 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 454316 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454319 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454323 */   GIM_Try, /*On fail goto*//*Label 8956*/ GIMT_Encode4(454374), // Rule ID 7064 //
     /* 454328 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 454332 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 454336 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 454339 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 454343 */     // MIs[1] Rn
     /* 454343 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454347 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454352 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 454356 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454358 */     // (AArch64duplane16:{ *:[v8i16] } (ld:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv8h:{ *:[v8i16] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454358 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv8h),
     /* 454361 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454363 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454367 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454372 */     GIR_RootConstrainSelectedInstOperands,
     /* 454373 */     // GIR_Coverage, 7064,
     /* 454373 */     GIR_EraseRootFromParent_Done,
     /* 454374 */   // Label 8956: @454374
     /* 454374 */   GIM_Try, /*On fail goto*//*Label 8957*/ GIMT_Encode4(454412), // Rule ID 1954 //
     /* 454379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454382 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454390 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454394 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 454398 */     // MIs[1] Operand 1
     /* 454398 */     // No operand predicates
     /* 454398 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454400 */     // (AArch64duplane16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx)  =>  (DUPv8i16lane:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 454403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454405 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454407 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454410 */     GIR_RootConstrainSelectedInstOperands,
     /* 454411 */     // GIR_Coverage, 1954,
     /* 454411 */     GIR_EraseRootFromParent_Done,
     /* 454412 */   // Label 8957: @454412
     /* 454412 */   GIM_Try, /*On fail goto*//*Label 8958*/ GIMT_Encode4(454447), // Rule ID 6241 //
     /* 454417 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454421 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454425 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454429 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 454433 */     // MIs[1] Operand 1
     /* 454433 */     // No operand predicates
     /* 454433 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454435 */     // (AArch64duplane16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)  =>  (DUPv8i16lane:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$imm)
     /* 454435 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i16lane),
     /* 454438 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454440 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454442 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 454445 */     GIR_RootConstrainSelectedInstOperands,
     /* 454446 */     // GIR_Coverage, 6241,
     /* 454446 */     GIR_EraseRootFromParent_Done,
     /* 454447 */   // Label 8958: @454447
     /* 454447 */   GIM_Reject,
     /* 454448 */ // Label 8955: @454448
     /* 454448 */ GIM_Reject,
     /* 454449 */ // Label 8951: @454449
     /* 454449 */ GIM_Reject,
     /* 454450 */ // Label 137: @454450
     /* 454450 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(9), /*)*//*default:*//*Label 8961*/ GIMT_Encode4(454704),
     /* 454461 */ /*GILLT_v2s32*//*Label 8959*/ GIMT_Encode4(454477), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 454473 */ /*GILLT_v4s32*//*Label 8960*/ GIMT_Encode4(454563),
     /* 454477 */ // Label 8959: @454477
     /* 454477 */ GIM_Try, /*On fail goto*//*Label 8962*/ GIMT_Encode4(454562),
     /* 454482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 454485 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454488 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 454492 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454496 */   GIM_Try, /*On fail goto*//*Label 8963*/ GIMT_Encode4(454530), // Rule ID 1951 //
     /* 454501 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454512 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 454516 */     // MIs[1] Operand 1
     /* 454516 */     // No operand predicates
     /* 454516 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454518 */     // (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPv2i32lane:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 454521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454523 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454525 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454528 */     GIR_RootConstrainSelectedInstOperands,
     /* 454529 */     // GIR_Coverage, 1951,
     /* 454529 */     GIR_EraseRootFromParent_Done,
     /* 454530 */   // Label 8963: @454530
     /* 454530 */   GIM_Try, /*On fail goto*//*Label 8964*/ GIMT_Encode4(454561), // Rule ID 6242 //
     /* 454535 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454539 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454543 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 454547 */     // MIs[1] Operand 1
     /* 454547 */     // No operand predicates
     /* 454547 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454549 */     // (AArch64duplane32:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (DUPv2i32lane:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
     /* 454549 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i32lane),
     /* 454552 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454554 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454556 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 454559 */     GIR_RootConstrainSelectedInstOperands,
     /* 454560 */     // GIR_Coverage, 6242,
     /* 454560 */     GIR_EraseRootFromParent_Done,
     /* 454561 */   // Label 8964: @454561
     /* 454561 */   GIM_Reject,
     /* 454562 */ // Label 8962: @454562
     /* 454562 */ GIM_Reject,
     /* 454563 */ // Label 8960: @454563
     /* 454563 */ GIM_Try, /*On fail goto*//*Label 8965*/ GIMT_Encode4(454703),
     /* 454568 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 454571 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454574 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454578 */   GIM_Try, /*On fail goto*//*Label 8966*/ GIMT_Encode4(454629), // Rule ID 7066 //
     /* 454583 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 454587 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 454591 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 454594 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 454598 */     // MIs[1] Rn
     /* 454598 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454602 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454607 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 454611 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454613 */     // (AArch64duplane32:{ *:[v4i32] } (ld:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv4s:{ *:[v4i32] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454613 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv4s),
     /* 454616 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454618 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454622 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454627 */     GIR_RootConstrainSelectedInstOperands,
     /* 454628 */     // GIR_Coverage, 7066,
     /* 454628 */     GIR_EraseRootFromParent_Done,
     /* 454629 */   // Label 8966: @454629
     /* 454629 */   GIM_Try, /*On fail goto*//*Label 8967*/ GIMT_Encode4(454667), // Rule ID 1952 //
     /* 454634 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454637 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454641 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454645 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454649 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 454653 */     // MIs[1] Operand 1
     /* 454653 */     // No operand predicates
     /* 454653 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454655 */     // (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)  =>  (DUPv4i32lane:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 454658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454660 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454662 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454665 */     GIR_RootConstrainSelectedInstOperands,
     /* 454666 */     // GIR_Coverage, 1952,
     /* 454666 */     GIR_EraseRootFromParent_Done,
     /* 454667 */   // Label 8967: @454667
     /* 454667 */   GIM_Try, /*On fail goto*//*Label 8968*/ GIMT_Encode4(454702), // Rule ID 6243 //
     /* 454672 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454676 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454680 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454684 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 454688 */     // MIs[1] Operand 1
     /* 454688 */     // No operand predicates
     /* 454688 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454690 */     // (AArch64duplane32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)  =>  (DUPv4i32lane:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$imm)
     /* 454690 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv4i32lane),
     /* 454693 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454695 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454697 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 454700 */     GIR_RootConstrainSelectedInstOperands,
     /* 454701 */     // GIR_Coverage, 6243,
     /* 454701 */     GIR_EraseRootFromParent_Done,
     /* 454702 */   // Label 8968: @454702
     /* 454702 */   GIM_Reject,
     /* 454703 */ // Label 8965: @454703
     /* 454703 */ GIM_Reject,
     /* 454704 */ // Label 8961: @454704
     /* 454704 */ GIM_Reject,
     /* 454705 */ // Label 138: @454705
     /* 454705 */ GIM_Try, /*On fail goto*//*Label 8969*/ GIMT_Encode4(454850),
     /* 454710 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 454713 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 454716 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454719 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454723 */   GIM_Try, /*On fail goto*//*Label 8970*/ GIMT_Encode4(454774), // Rule ID 7067 //
     /* 454728 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 454732 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 454736 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 454739 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 454743 */     // MIs[1] Rn
     /* 454743 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454747 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454752 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 454756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454758 */     // (AArch64duplane64:{ *:[v2i64] } (ld:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv2d:{ *:[v2i64] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv2d),
     /* 454761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454767 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454772 */     GIR_RootConstrainSelectedInstOperands,
     /* 454773 */     // GIR_Coverage, 7067,
     /* 454773 */     GIR_EraseRootFromParent_Done,
     /* 454774 */   // Label 8970: @454774
     /* 454774 */   GIM_Try, /*On fail goto*//*Label 8971*/ GIMT_Encode4(454849),
     /* 454779 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454783 */     GIM_Try, /*On fail goto*//*Label 8972*/ GIMT_Encode4(454817), // Rule ID 1950 //
     /* 454788 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454791 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454795 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454799 */       GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 454803 */       // MIs[1] Operand 1
     /* 454803 */       // No operand predicates
     /* 454803 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454805 */       // (AArch64duplane64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$idx)  =>  (DUPv2i64lane:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454805 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 454808 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454810 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454812 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454815 */       GIR_RootConstrainSelectedInstOperands,
     /* 454816 */       // GIR_Coverage, 1950,
     /* 454816 */       GIR_EraseRootFromParent_Done,
     /* 454817 */     // Label 8972: @454817
     /* 454817 */     GIM_Try, /*On fail goto*//*Label 8973*/ GIMT_Encode4(454848), // Rule ID 6244 //
     /* 454822 */       GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454826 */       GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454830 */       GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexD),
     /* 454834 */       // MIs[1] Operand 1
     /* 454834 */       // No operand predicates
     /* 454834 */       GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454836 */       // (AArch64duplane64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)  =>  (DUPv2i64lane:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexD>>:$imm)
     /* 454836 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv2i64lane),
     /* 454839 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454841 */       GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454843 */       GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 454846 */       GIR_RootConstrainSelectedInstOperands,
     /* 454847 */       // GIR_Coverage, 6244,
     /* 454847 */       GIR_EraseRootFromParent_Done,
     /* 454848 */     // Label 8973: @454848
     /* 454848 */     GIM_Reject,
     /* 454849 */   // Label 8971: @454849
     /* 454849 */   GIM_Reject,
     /* 454850 */ // Label 8969: @454850
     /* 454850 */ GIM_Reject,
     /* 454851 */ // Label 139: @454851
     /* 454851 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 8976*/ GIMT_Encode4(455029),
     /* 454862 */ /*GILLT_v8s8*//*Label 8974*/ GIMT_Encode4(454874), GIMT_Encode4(0),
     /* 454870 */ /*GILLT_v16s8*//*Label 8975*/ GIMT_Encode4(454923),
     /* 454874 */ // Label 8974: @454874
     /* 454874 */ GIM_Try, /*On fail goto*//*Label 8977*/ GIMT_Encode4(454922), // Rule ID 1955 //
     /* 454879 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454882 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 454885 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454888 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 454892 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454896 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 454900 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 454904 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 454908 */   // MIs[1] Operand 1
     /* 454908 */   // No operand predicates
     /* 454908 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454910 */   // (AArch64duplane8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (DUPv8i8lane:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 454910 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv8i8lane),
     /* 454913 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 454915 */   GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 454917 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 454920 */   GIR_RootConstrainSelectedInstOperands,
     /* 454921 */   // GIR_Coverage, 1955,
     /* 454921 */   GIR_EraseRootFromParent_Done,
     /* 454922 */ // Label 8977: @454922
     /* 454922 */ GIM_Reject,
     /* 454923 */ // Label 8975: @454923
     /* 454923 */ GIM_Try, /*On fail goto*//*Label 8978*/ GIMT_Encode4(455028),
     /* 454928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 454931 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 454934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 454938 */   GIM_Try, /*On fail goto*//*Label 8979*/ GIMT_Encode4(454989), // Rule ID 7062 //
     /* 454943 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 454947 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LOAD),
     /* 454951 */     GIM_CheckAtomicOrdering, /*MI*/1, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 454954 */     GIM_CheckMemorySizeEqualToLLT, /*MI*/1, /*MMO*/0, /*OpIdx*/0,
     /* 454958 */     // MIs[1] Rn
     /* 454958 */     GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/64,
     /* 454962 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64spRegClassID),
     /* 454967 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
     /* 454971 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 454973 */     // (AArch64duplane8:{ *:[v16i8] } (ld:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_load>>, 0:{ *:[i64] })  =>  (LD1Rv16b:{ *:[v16i8] } GPR64sp:{ *:[i64] }:$Rn)
     /* 454973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::LD1Rv16b),
     /* 454976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vt]
     /* 454978 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 454982 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 454987 */     GIR_RootConstrainSelectedInstOperands,
     /* 454988 */     // GIR_Coverage, 7062,
     /* 454988 */     GIR_EraseRootFromParent_Done,
     /* 454989 */   // Label 8979: @454989
     /* 454989 */   GIM_Try, /*On fail goto*//*Label 8980*/ GIMT_Encode4(455027), // Rule ID 1956 //
     /* 454994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 454997 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455001 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 455005 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455009 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexB),
     /* 455013 */     // MIs[1] Operand 1
     /* 455013 */     // No operand predicates
     /* 455013 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455015 */     // (AArch64duplane8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] })<<P:Predicate_VectorIndexB>>:$idx)  =>  (DUPv16i8lane:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i64] }):$idx)
     /* 455015 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::DUPv16i8lane),
     /* 455018 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455020 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455022 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 455025 */     GIR_RootConstrainSelectedInstOperands,
     /* 455026 */     // GIR_Coverage, 1956,
     /* 455026 */     GIR_EraseRootFromParent_Done,
     /* 455027 */   // Label 8980: @455027
     /* 455027 */   GIM_Reject,
     /* 455028 */ // Label 8978: @455028
     /* 455028 */ GIM_Reject,
     /* 455029 */ // Label 8976: @455029
     /* 455029 */ GIM_Reject,
     /* 455030 */ // Label 140: @455030
     /* 455030 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 8990*/ GIMT_Encode4(456679),
     /* 455041 */ /*GILLT_s64*//*Label 8981*/ GIMT_Encode4(455125), GIMT_Encode4(0),
     /* 455049 */ /*GILLT_v2s32*//*Label 8982*/ GIMT_Encode4(455446),
     /* 455053 */ /*GILLT_v2s64*//*Label 8983*/ GIMT_Encode4(455767),
     /* 455057 */ /*GILLT_v4s16*//*Label 8984*/ GIMT_Encode4(455850),
     /* 455061 */ /*GILLT_v4s32*//*Label 8985*/ GIMT_Encode4(456171),
     /* 455065 */ /*GILLT_v8s8*//*Label 8986*/ GIMT_Encode4(456254),
     /* 455069 */ /*GILLT_v8s16*//*Label 8987*/ GIMT_Encode4(456463),
     /* 455073 */ /*GILLT_v16s8*//*Label 8988*/ GIMT_Encode4(456546), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 455121 */ /*GILLT_nxv16s8*//*Label 8989*/ GIMT_Encode4(456632),
     /* 455125 */ // Label 8981: @455125
     /* 455125 */ GIM_Try, /*On fail goto*//*Label 8991*/ GIMT_Encode4(455445),
     /* 455130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 455133 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 455136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455140 */   GIM_Try, /*On fail goto*//*Label 8992*/ GIMT_Encode4(455255), // Rule ID 6059 //
     /* 455145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455153 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 455157 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455162 */     // MIs[1] Operand 2
     /* 455162 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 455173 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 455177 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455181 */     // MIs[2] Rn
     /* 455181 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 455186 */     // MIs[2] Operand 2
     /* 455186 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(1),
     /* 455197 */     // MIs[0] imm
     /* 455197 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 455201 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455205 */     // MIs[3] Operand 1
     /* 455205 */     // No operand predicates
     /* 455205 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 455207 */     // (AArch64ext:{ *:[v1i64] } (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v1i64] } V128:{ *:[v2i64] }:$Rn, 1:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v1i64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 455207 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 455210 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455214 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 455219 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455223 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455227 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 455230 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 455232 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 455235 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 455237 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 455244 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455249 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455254 */     // GIR_Coverage, 6059,
     /* 455254 */     GIR_EraseRootFromParent_Done,
     /* 455255 */   // Label 8992: @455255
     /* 455255 */   GIM_Try, /*On fail goto*//*Label 8993*/ GIMT_Encode4(455370), // Rule ID 6064 //
     /* 455260 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455264 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455268 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 455272 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455277 */     // MIs[1] Operand 2
     /* 455277 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 455288 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 455292 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455296 */     // MIs[2] Rn
     /* 455296 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 455301 */     // MIs[2] Operand 2
     /* 455301 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(1),
     /* 455312 */     // MIs[0] imm
     /* 455312 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 455316 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455320 */     // MIs[3] Operand 1
     /* 455320 */     // No operand predicates
     /* 455320 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 455322 */     // (AArch64ext:{ *:[v1f64] } (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v1f64] } V128:{ *:[v2f64] }:$Rn, 1:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v1f64] } (EXTv16i8:{ *:[f128] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 455322 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 455325 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455329 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 455334 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455338 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455342 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 455345 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 455347 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 455350 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 455352 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 455359 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455364 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455369 */     // GIR_Coverage, 6064,
     /* 455369 */     GIR_EraseRootFromParent_Done,
     /* 455370 */   // Label 8993: @455370
     /* 455370 */   GIM_Try, /*On fail goto*//*Label 8994*/ GIMT_Encode4(455407), // Rule ID 6056 //
     /* 455375 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455383 */     // MIs[0] imm
     /* 455383 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455387 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455391 */     // MIs[1] Operand 1
     /* 455391 */     // No operand predicates
     /* 455391 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455393 */     // (AArch64ext:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 455396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455398 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455400 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455402 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455405 */     GIR_RootConstrainSelectedInstOperands,
     /* 455406 */     // GIR_Coverage, 6056,
     /* 455406 */     GIR_EraseRootFromParent_Done,
     /* 455407 */   // Label 8994: @455407
     /* 455407 */   GIM_Try, /*On fail goto*//*Label 8995*/ GIMT_Encode4(455444), // Rule ID 6061 //
     /* 455412 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455416 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455420 */     // MIs[0] imm
     /* 455420 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455424 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455428 */     // MIs[1] Operand 1
     /* 455428 */     // No operand predicates
     /* 455428 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455430 */     // (AArch64ext:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v1f64] } V64:{ *:[v1f64] }:$Rn, V64:{ *:[v1f64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455430 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 455433 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455435 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455437 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455439 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455442 */     GIR_RootConstrainSelectedInstOperands,
     /* 455443 */     // GIR_Coverage, 6061,
     /* 455443 */     GIR_EraseRootFromParent_Done,
     /* 455444 */   // Label 8995: @455444
     /* 455444 */   GIM_Reject,
     /* 455445 */ // Label 8991: @455445
     /* 455445 */ GIM_Reject,
     /* 455446 */ // Label 8982: @455446
     /* 455446 */ GIM_Try, /*On fail goto*//*Label 8996*/ GIMT_Encode4(455766),
     /* 455451 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 455454 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 455457 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455461 */   GIM_Try, /*On fail goto*//*Label 8997*/ GIMT_Encode4(455576), // Rule ID 6049 //
     /* 455466 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455470 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455474 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 455478 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455483 */     // MIs[1] Operand 2
     /* 455483 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 455494 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 455498 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455502 */     // MIs[2] Rn
     /* 455502 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 455507 */     // MIs[2] Operand 2
     /* 455507 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 455518 */     // MIs[0] imm
     /* 455518 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 455522 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455526 */     // MIs[3] Operand 1
     /* 455526 */     // No operand predicates
     /* 455526 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 455528 */     // (AArch64ext:{ *:[v2i32] } (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn, 2:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v2i32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 455528 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 455531 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455535 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 455540 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455544 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455548 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 455551 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 455553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 455556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 455558 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 455565 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455570 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455575 */     // GIR_Coverage, 6049,
     /* 455575 */     GIR_EraseRootFromParent_Done,
     /* 455576 */   // Label 8997: @455576
     /* 455576 */   GIM_Try, /*On fail goto*//*Label 8998*/ GIMT_Encode4(455691), // Rule ID 6054 //
     /* 455581 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455585 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455589 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 455593 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455598 */     // MIs[1] Operand 2
     /* 455598 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 455609 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 455613 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455617 */     // MIs[2] Rn
     /* 455617 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 455622 */     // MIs[2] Operand 2
     /* 455622 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2),
     /* 455633 */     // MIs[0] imm
     /* 455633 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 455637 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455641 */     // MIs[3] Operand 1
     /* 455641 */     // No operand predicates
     /* 455641 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 455643 */     // (AArch64ext:{ *:[v2f32] } (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v2f32] } V128:{ *:[v4f32] }:$Rn, 2:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v2f32] } (EXTv16i8:{ *:[f128] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 455643 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 455646 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455650 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 455655 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455659 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455663 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 455666 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 455668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 455671 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 455673 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 455680 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455685 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455690 */     // GIR_Coverage, 6054,
     /* 455690 */     GIR_EraseRootFromParent_Done,
     /* 455691 */   // Label 8998: @455691
     /* 455691 */   GIM_Try, /*On fail goto*//*Label 8999*/ GIMT_Encode4(455728), // Rule ID 6046 //
     /* 455696 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455700 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455704 */     // MIs[0] imm
     /* 455704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455712 */     // MIs[1] Operand 1
     /* 455712 */     // No operand predicates
     /* 455712 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455714 */     // (AArch64ext:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455714 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 455717 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455719 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455721 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455723 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455726 */     GIR_RootConstrainSelectedInstOperands,
     /* 455727 */     // GIR_Coverage, 6046,
     /* 455727 */     GIR_EraseRootFromParent_Done,
     /* 455728 */   // Label 8999: @455728
     /* 455728 */   GIM_Try, /*On fail goto*//*Label 9000*/ GIMT_Encode4(455765), // Rule ID 6051 //
     /* 455733 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455741 */     // MIs[0] imm
     /* 455741 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455745 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455749 */     // MIs[1] Operand 1
     /* 455749 */     // No operand predicates
     /* 455749 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455751 */     // (AArch64ext:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 455754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455756 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455758 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455760 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455763 */     GIR_RootConstrainSelectedInstOperands,
     /* 455764 */     // GIR_Coverage, 6051,
     /* 455764 */     GIR_EraseRootFromParent_Done,
     /* 455765 */   // Label 9000: @455765
     /* 455765 */   GIM_Reject,
     /* 455766 */ // Label 8996: @455766
     /* 455766 */ GIM_Reject,
     /* 455767 */ // Label 8983: @455767
     /* 455767 */ GIM_Try, /*On fail goto*//*Label 9001*/ GIMT_Encode4(455849),
     /* 455772 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 455775 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 455778 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455782 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455786 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455790 */   GIM_Try, /*On fail goto*//*Label 9002*/ GIMT_Encode4(455819), // Rule ID 6057 //
     /* 455795 */     // MIs[0] imm
     /* 455795 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455799 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455803 */     // MIs[1] Operand 1
     /* 455803 */     // No operand predicates
     /* 455803 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455805 */     // (AArch64ext:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455805 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455808 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455810 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455812 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455814 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455817 */     GIR_RootConstrainSelectedInstOperands,
     /* 455818 */     // GIR_Coverage, 6057,
     /* 455818 */     GIR_EraseRootFromParent_Done,
     /* 455819 */   // Label 9002: @455819
     /* 455819 */   GIM_Try, /*On fail goto*//*Label 9003*/ GIMT_Encode4(455848), // Rule ID 6062 //
     /* 455824 */     // MIs[0] imm
     /* 455824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 455828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455832 */     // MIs[1] Operand 1
     /* 455832 */     // No operand predicates
     /* 455832 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 455834 */     // (AArch64ext:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 455834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 455839 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 455841 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 455843 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 455846 */     GIR_RootConstrainSelectedInstOperands,
     /* 455847 */     // GIR_Coverage, 6062,
     /* 455847 */     GIR_EraseRootFromParent_Done,
     /* 455848 */   // Label 9003: @455848
     /* 455848 */   GIM_Reject,
     /* 455849 */ // Label 9001: @455849
     /* 455849 */ GIM_Reject,
     /* 455850 */ // Label 8984: @455850
     /* 455850 */ GIM_Try, /*On fail goto*//*Label 9004*/ GIMT_Encode4(456170),
     /* 455855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 455858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 455861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455865 */   GIM_Try, /*On fail goto*//*Label 9005*/ GIMT_Encode4(455980), // Rule ID 6039 //
     /* 455870 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455874 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455878 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 455882 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455887 */     // MIs[1] Operand 2
     /* 455887 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 455898 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 455902 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455906 */     // MIs[2] Rn
     /* 455906 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 455911 */     // MIs[2] Operand 2
     /* 455911 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 455922 */     // MIs[0] imm
     /* 455922 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 455926 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 455930 */     // MIs[3] Operand 1
     /* 455930 */     // No operand predicates
     /* 455930 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 455932 */     // (AArch64ext:{ *:[v4i16] } (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn, 4:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v4i16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 455932 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 455935 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 455939 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 455944 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455948 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 455952 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 455955 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 455957 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 455960 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 455962 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 455969 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 455974 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 455979 */     // GIR_Coverage, 6039,
     /* 455979 */     GIR_EraseRootFromParent_Done,
     /* 455980 */   // Label 9005: @455980
     /* 455980 */   GIM_Try, /*On fail goto*//*Label 9006*/ GIMT_Encode4(456095), // Rule ID 6044 //
     /* 455985 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 455989 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 455993 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 455997 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456002 */     // MIs[1] Operand 2
     /* 456002 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 456013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 456017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 456021 */     // MIs[2] Rn
     /* 456021 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 456026 */     // MIs[2] Operand 2
     /* 456026 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4),
     /* 456037 */     // MIs[0] imm
     /* 456037 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 456041 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456045 */     // MIs[3] Operand 1
     /* 456045 */     // No operand predicates
     /* 456045 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 456047 */     // (AArch64ext:{ *:[v4f16] } (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v4f16] } V128:{ *:[v8f16] }:$Rn, 4:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v4f16] } (EXTv16i8:{ *:[f128] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 456047 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 456050 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456054 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 456059 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 456063 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 456067 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 456070 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 456072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 456075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 456077 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 456084 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456089 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456094 */     // GIR_Coverage, 6044,
     /* 456094 */     GIR_EraseRootFromParent_Done,
     /* 456095 */   // Label 9006: @456095
     /* 456095 */   GIM_Try, /*On fail goto*//*Label 9007*/ GIMT_Encode4(456132), // Rule ID 6036 //
     /* 456100 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456108 */     // MIs[0] imm
     /* 456108 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456112 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456116 */     // MIs[1] Operand 1
     /* 456116 */     // No operand predicates
     /* 456116 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456118 */     // (AArch64ext:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456118 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 456121 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456123 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456125 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456127 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456130 */     GIR_RootConstrainSelectedInstOperands,
     /* 456131 */     // GIR_Coverage, 6036,
     /* 456131 */     GIR_EraseRootFromParent_Done,
     /* 456132 */   // Label 9007: @456132
     /* 456132 */   GIM_Try, /*On fail goto*//*Label 9008*/ GIMT_Encode4(456169), // Rule ID 6041 //
     /* 456137 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456141 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456145 */     // MIs[0] imm
     /* 456145 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456149 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456153 */     // MIs[1] Operand 1
     /* 456153 */     // No operand predicates
     /* 456153 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456155 */     // (AArch64ext:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456155 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 456158 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456160 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456162 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456164 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456167 */     GIR_RootConstrainSelectedInstOperands,
     /* 456168 */     // GIR_Coverage, 6041,
     /* 456168 */     GIR_EraseRootFromParent_Done,
     /* 456169 */   // Label 9008: @456169
     /* 456169 */   GIM_Reject,
     /* 456170 */ // Label 9004: @456170
     /* 456170 */ GIM_Reject,
     /* 456171 */ // Label 8985: @456171
     /* 456171 */ GIM_Try, /*On fail goto*//*Label 9009*/ GIMT_Encode4(456253),
     /* 456176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 456179 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 456182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456186 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456190 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456194 */   GIM_Try, /*On fail goto*//*Label 9010*/ GIMT_Encode4(456223), // Rule ID 6047 //
     /* 456199 */     // MIs[0] imm
     /* 456199 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456203 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456207 */     // MIs[1] Operand 1
     /* 456207 */     // No operand predicates
     /* 456207 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456209 */     // (AArch64ext:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456214 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456216 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456218 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456221 */     GIR_RootConstrainSelectedInstOperands,
     /* 456222 */     // GIR_Coverage, 6047,
     /* 456222 */     GIR_EraseRootFromParent_Done,
     /* 456223 */   // Label 9010: @456223
     /* 456223 */   GIM_Try, /*On fail goto*//*Label 9011*/ GIMT_Encode4(456252), // Rule ID 6052 //
     /* 456228 */     // MIs[0] imm
     /* 456228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456236 */     // MIs[1] Operand 1
     /* 456236 */     // No operand predicates
     /* 456236 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456238 */     // (AArch64ext:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456238 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456241 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456243 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456245 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456247 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456250 */     GIR_RootConstrainSelectedInstOperands,
     /* 456251 */     // GIR_Coverage, 6052,
     /* 456251 */     GIR_EraseRootFromParent_Done,
     /* 456252 */   // Label 9011: @456252
     /* 456252 */   GIM_Reject,
     /* 456253 */ // Label 9009: @456253
     /* 456253 */ GIM_Reject,
     /* 456254 */ // Label 8986: @456254
     /* 456254 */ GIM_Try, /*On fail goto*//*Label 9012*/ GIMT_Encode4(456462),
     /* 456259 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 456262 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 456265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456269 */   GIM_Try, /*On fail goto*//*Label 9013*/ GIMT_Encode4(456384), // Rule ID 6034 //
     /* 456274 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 456278 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 456282 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 456286 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456291 */     // MIs[1] Operand 2
     /* 456291 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 456302 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 456306 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 456310 */     // MIs[2] Rn
     /* 456310 */     GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
     /* 456315 */     // MIs[2] Operand 2
     /* 456315 */     GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
     /* 456326 */     // MIs[0] imm
     /* 456326 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
     /* 456330 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456334 */     // MIs[3] Operand 1
     /* 456334 */     // No operand predicates
     /* 456334 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 456336 */     // (AArch64ext:{ *:[v8i8] } (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 0:{ *:[i64] }), (extract_subvector:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn, 8:{ *:[i64] }), (imm:{ *:[i32] }):$imm)  =>  (EXTRACT_SUBREG:{ *:[v8i8] } (EXTv16i8:{ *:[f128] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rn, (imm:{ *:[i32] }):$imm), dsub:{ *:[i32] })
     /* 456336 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s128,
     /* 456339 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456343 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 456348 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 456352 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 456356 */     GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/3, // imm
     /* 456359 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 456361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 456364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 456366 */     GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AArch64::dsub),
     /* 456373 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456378 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456383 */     // GIR_Coverage, 6034,
     /* 456383 */     GIR_EraseRootFromParent_Done,
     /* 456384 */   // Label 9013: @456384
     /* 456384 */   GIM_Try, /*On fail goto*//*Label 9014*/ GIMT_Encode4(456424), // Rule ID 1899 //
     /* 456389 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456392 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456400 */     // MIs[0] imm
     /* 456400 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456404 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456408 */     // MIs[1] Operand 1
     /* 456408 */     // No operand predicates
     /* 456408 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456410 */     // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 456413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456415 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456417 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456419 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456422 */     GIR_RootConstrainSelectedInstOperands,
     /* 456423 */     // GIR_Coverage, 1899,
     /* 456423 */     GIR_EraseRootFromParent_Done,
     /* 456424 */   // Label 9014: @456424
     /* 456424 */   GIM_Try, /*On fail goto*//*Label 9015*/ GIMT_Encode4(456461), // Rule ID 6031 //
     /* 456429 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456433 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456437 */     // MIs[0] imm
     /* 456437 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456441 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456445 */     // MIs[1] Operand 1
     /* 456445 */     // No operand predicates
     /* 456445 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456447 */     // (AArch64ext:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv8i8),
     /* 456450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456452 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456454 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456456 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456459 */     GIR_RootConstrainSelectedInstOperands,
     /* 456460 */     // GIR_Coverage, 6031,
     /* 456460 */     GIR_EraseRootFromParent_Done,
     /* 456461 */   // Label 9015: @456461
     /* 456461 */   GIM_Reject,
     /* 456462 */ // Label 9012: @456462
     /* 456462 */ GIM_Reject,
     /* 456463 */ // Label 8987: @456463
     /* 456463 */ GIM_Try, /*On fail goto*//*Label 9016*/ GIMT_Encode4(456545),
     /* 456468 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 456471 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 456474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456478 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456482 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456486 */   GIM_Try, /*On fail goto*//*Label 9017*/ GIMT_Encode4(456515), // Rule ID 6037 //
     /* 456491 */     // MIs[0] imm
     /* 456491 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456495 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456499 */     // MIs[1] Operand 1
     /* 456499 */     // No operand predicates
     /* 456499 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456501 */     // (AArch64ext:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456506 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456508 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456510 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456513 */     GIR_RootConstrainSelectedInstOperands,
     /* 456514 */     // GIR_Coverage, 6037,
     /* 456514 */     GIR_EraseRootFromParent_Done,
     /* 456515 */   // Label 9017: @456515
     /* 456515 */   GIM_Try, /*On fail goto*//*Label 9018*/ GIMT_Encode4(456544), // Rule ID 6042 //
     /* 456520 */     // MIs[0] imm
     /* 456520 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456524 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456528 */     // MIs[1] Operand 1
     /* 456528 */     // No operand predicates
     /* 456528 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456530 */     // (AArch64ext:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456535 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456537 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456539 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456542 */     GIR_RootConstrainSelectedInstOperands,
     /* 456543 */     // GIR_Coverage, 6042,
     /* 456543 */     GIR_EraseRootFromParent_Done,
     /* 456544 */   // Label 9018: @456544
     /* 456544 */   GIM_Reject,
     /* 456545 */ // Label 9016: @456545
     /* 456545 */ GIM_Reject,
     /* 456546 */ // Label 8988: @456546
     /* 456546 */ GIM_Try, /*On fail goto*//*Label 9019*/ GIMT_Encode4(456631),
     /* 456551 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 456554 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 456557 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456561 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456565 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456569 */   GIM_Try, /*On fail goto*//*Label 9020*/ GIMT_Encode4(456601), // Rule ID 1900 //
     /* 456574 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456577 */     // MIs[0] imm
     /* 456577 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456581 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456585 */     // MIs[1] Operand 1
     /* 456585 */     // No operand predicates
     /* 456585 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456587 */     // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456587 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456590 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456592 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456594 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456596 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456599 */     GIR_RootConstrainSelectedInstOperands,
     /* 456600 */     // GIR_Coverage, 1900,
     /* 456600 */     GIR_EraseRootFromParent_Done,
     /* 456601 */   // Label 9020: @456601
     /* 456601 */   GIM_Try, /*On fail goto*//*Label 9021*/ GIMT_Encode4(456630), // Rule ID 6032 //
     /* 456606 */     // MIs[0] imm
     /* 456606 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456610 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456614 */     // MIs[1] Operand 1
     /* 456614 */     // No operand predicates
     /* 456614 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456616 */     // (AArch64ext:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)  =>  (EXTv16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm, (imm:{ *:[i32] }):$imm)
     /* 456616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXTv16i8),
     /* 456619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456621 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456623 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rm
     /* 456625 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 456628 */     GIR_RootConstrainSelectedInstOperands,
     /* 456629 */     // GIR_Coverage, 6032,
     /* 456629 */     GIR_EraseRootFromParent_Done,
     /* 456630 */   // Label 9021: @456630
     /* 456630 */   GIM_Reject,
     /* 456631 */ // Label 9019: @456631
     /* 456631 */ GIM_Reject,
     /* 456632 */ // Label 8989: @456632
     /* 456632 */ GIM_Try, /*On fail goto*//*Label 9022*/ GIMT_Encode4(456678), // Rule ID 2772 //
     /* 456637 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 456640 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 456643 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 456646 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 456650 */   // MIs[0] Op3
     /* 456650 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 456654 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 456658 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
     /* 456662 */   // MIs[1] Operand 1
     /* 456662 */   // No operand predicates
     /* 456662 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456664 */   // (AArch64ext:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3)  =>  (EXT_ZZI:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$Op3)
     /* 456664 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::EXT_ZZI),
     /* 456667 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Zdn]
     /* 456669 */   GIR_RootToRootCopy, /*OpIdx*/1, // Op1
     /* 456671 */   GIR_RootToRootCopy, /*OpIdx*/2, // Op2
     /* 456673 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // Op3
     /* 456676 */   GIR_RootConstrainSelectedInstOperands,
     /* 456677 */   // GIR_Coverage, 2772,
     /* 456677 */   GIR_EraseRootFromParent_Done,
     /* 456678 */ // Label 9022: @456678
     /* 456678 */ GIM_Reject,
     /* 456679 */ // Label 8990: @456679
     /* 456679 */ GIM_Reject,
     /* 456680 */ // Label 141: @456680
     /* 456680 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 9030*/ GIMT_Encode4(457238),
     /* 456691 */ /*GILLT_s32*//*Label 9023*/ GIMT_Encode4(456727),
     /* 456695 */ /*GILLT_s64*//*Label 9024*/ GIMT_Encode4(456765), GIMT_Encode4(0),
     /* 456703 */ /*GILLT_v2s32*//*Label 9025*/ GIMT_Encode4(456863),
     /* 456707 */ /*GILLT_v2s64*//*Label 9026*/ GIMT_Encode4(456938),
     /* 456711 */ /*GILLT_v4s16*//*Label 9027*/ GIMT_Encode4(457013),
     /* 456715 */ /*GILLT_v4s32*//*Label 9028*/ GIMT_Encode4(457088), GIMT_Encode4(0),
     /* 456723 */ /*GILLT_v8s16*//*Label 9029*/ GIMT_Encode4(457163),
     /* 456727 */ // Label 9023: @456727
     /* 456727 */ GIM_Try, /*On fail goto*//*Label 9031*/ GIMT_Encode4(456764), // Rule ID 1628 //
     /* 456732 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456735 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 456738 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 456741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 456745 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 456749 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 456753 */   // (AArch64fcmeq:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMEQ32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 456753 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ32),
     /* 456758 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 456762 */   GIR_RootConstrainSelectedInstOperands,
     /* 456763 */   // GIR_Coverage, 1628,
     /* 456763 */   GIR_Done,
     /* 456764 */ // Label 9031: @456764
     /* 456764 */ GIM_Reject,
     /* 456765 */ // Label 9024: @456765
     /* 456765 */ GIM_Try, /*On fail goto*//*Label 9032*/ GIMT_Encode4(456862),
     /* 456770 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 456773 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 456776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456784 */   GIM_Try, /*On fail goto*//*Label 9033*/ GIMT_Encode4(456815), // Rule ID 2547 //
     /* 456789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456792 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 456796 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 456802 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 456804 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456806 */     // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMEQv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 456806 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv1i64rz),
     /* 456809 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456811 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456813 */     GIR_RootConstrainSelectedInstOperands,
     /* 456814 */     // GIR_Coverage, 2547,
     /* 456814 */     GIR_EraseRootFromParent_Done,
     /* 456815 */   // Label 9033: @456815
     /* 456815 */   GIM_Try, /*On fail goto*//*Label 9034*/ GIMT_Encode4(456838), // Rule ID 1627 //
     /* 456820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456823 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456827 */     // (AArch64fcmeq:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMEQ64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 456827 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
     /* 456832 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 456836 */     GIR_RootConstrainSelectedInstOperands,
     /* 456837 */     // GIR_Coverage, 1627,
     /* 456837 */     GIR_Done,
     /* 456838 */   // Label 9034: @456838
     /* 456838 */   GIM_Try, /*On fail goto*//*Label 9035*/ GIMT_Encode4(456861), // Rule ID 5262 //
     /* 456843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456846 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456850 */     // (AArch64fcmeq:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMEQ64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 456850 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQ64),
     /* 456855 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 456859 */     GIR_RootConstrainSelectedInstOperands,
     /* 456860 */     // GIR_Coverage, 5262,
     /* 456860 */     GIR_Done,
     /* 456861 */   // Label 9035: @456861
     /* 456861 */   GIM_Reject,
     /* 456862 */ // Label 9032: @456862
     /* 456862 */ GIM_Reject,
     /* 456863 */ // Label 9025: @456863
     /* 456863 */ GIM_Try, /*On fail goto*//*Label 9036*/ GIMT_Encode4(456937),
     /* 456868 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 456871 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 456874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456878 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456882 */   GIM_Try, /*On fail goto*//*Label 9037*/ GIMT_Encode4(456913), // Rule ID 803 //
     /* 456887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456890 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 456894 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 456900 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 456902 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456904 */     // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMEQv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 456904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i32rz),
     /* 456907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456909 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456911 */     GIR_RootConstrainSelectedInstOperands,
     /* 456912 */     // GIR_Coverage, 803,
     /* 456912 */     GIR_EraseRootFromParent_Done,
     /* 456913 */   // Label 9037: @456913
     /* 456913 */   GIM_Try, /*On fail goto*//*Label 9038*/ GIMT_Encode4(456936), // Rule ID 1240 //
     /* 456918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 456925 */     // (AArch64fcmeq:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMEQv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 456925 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f32),
     /* 456930 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 456934 */     GIR_RootConstrainSelectedInstOperands,
     /* 456935 */     // GIR_Coverage, 1240,
     /* 456935 */     GIR_Done,
     /* 456936 */   // Label 9038: @456936
     /* 456936 */   GIM_Reject,
     /* 456937 */ // Label 9036: @456937
     /* 456937 */ GIM_Reject,
     /* 456938 */ // Label 9026: @456938
     /* 456938 */ GIM_Try, /*On fail goto*//*Label 9039*/ GIMT_Encode4(457012),
     /* 456943 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 456946 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 456949 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456953 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 456957 */   GIM_Try, /*On fail goto*//*Label 9040*/ GIMT_Encode4(456988), // Rule ID 805 //
     /* 456962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456965 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 456969 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 456975 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 456977 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 456979 */     // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMEQv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 456979 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2i64rz),
     /* 456982 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 456984 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 456986 */     GIR_RootConstrainSelectedInstOperands,
     /* 456987 */     // GIR_Coverage, 805,
     /* 456987 */     GIR_EraseRootFromParent_Done,
     /* 456988 */   // Label 9040: @456988
     /* 456988 */   GIM_Try, /*On fail goto*//*Label 9041*/ GIMT_Encode4(457011), // Rule ID 1242 //
     /* 456993 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 456996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457000 */     // (AArch64fcmeq:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMEQv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 457000 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv2f64),
     /* 457005 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457009 */     GIR_RootConstrainSelectedInstOperands,
     /* 457010 */     // GIR_Coverage, 1242,
     /* 457010 */     GIR_Done,
     /* 457011 */   // Label 9041: @457011
     /* 457011 */   GIM_Reject,
     /* 457012 */ // Label 9039: @457012
     /* 457012 */ GIM_Reject,
     /* 457013 */ // Label 9027: @457013
     /* 457013 */ GIM_Try, /*On fail goto*//*Label 9042*/ GIMT_Encode4(457087),
     /* 457018 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 457021 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 457024 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457028 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457032 */   GIM_Try, /*On fail goto*//*Label 9043*/ GIMT_Encode4(457063), // Rule ID 801 //
     /* 457037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457040 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457044 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457050 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457052 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457054 */     // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMEQv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 457054 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i16rz),
     /* 457057 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457059 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457061 */     GIR_RootConstrainSelectedInstOperands,
     /* 457062 */     // GIR_Coverage, 801,
     /* 457062 */     GIR_EraseRootFromParent_Done,
     /* 457063 */   // Label 9043: @457063
     /* 457063 */   GIM_Try, /*On fail goto*//*Label 9044*/ GIMT_Encode4(457086), // Rule ID 1238 //
     /* 457068 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457071 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457075 */     // (AArch64fcmeq:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMEQv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 457075 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f16),
     /* 457080 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457084 */     GIR_RootConstrainSelectedInstOperands,
     /* 457085 */     // GIR_Coverage, 1238,
     /* 457085 */     GIR_Done,
     /* 457086 */   // Label 9044: @457086
     /* 457086 */   GIM_Reject,
     /* 457087 */ // Label 9042: @457087
     /* 457087 */ GIM_Reject,
     /* 457088 */ // Label 9028: @457088
     /* 457088 */ GIM_Try, /*On fail goto*//*Label 9045*/ GIMT_Encode4(457162),
     /* 457093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 457096 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 457099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457103 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457107 */   GIM_Try, /*On fail goto*//*Label 9046*/ GIMT_Encode4(457138), // Rule ID 804 //
     /* 457112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457115 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457119 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457125 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457127 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457129 */     // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMEQv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 457129 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4i32rz),
     /* 457132 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457134 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457136 */     GIR_RootConstrainSelectedInstOperands,
     /* 457137 */     // GIR_Coverage, 804,
     /* 457137 */     GIR_EraseRootFromParent_Done,
     /* 457138 */   // Label 9046: @457138
     /* 457138 */   GIM_Try, /*On fail goto*//*Label 9047*/ GIMT_Encode4(457161), // Rule ID 1241 //
     /* 457143 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457146 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457150 */     // (AArch64fcmeq:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMEQv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 457150 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv4f32),
     /* 457155 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457159 */     GIR_RootConstrainSelectedInstOperands,
     /* 457160 */     // GIR_Coverage, 1241,
     /* 457160 */     GIR_Done,
     /* 457161 */   // Label 9047: @457161
     /* 457161 */   GIM_Reject,
     /* 457162 */ // Label 9045: @457162
     /* 457162 */ GIM_Reject,
     /* 457163 */ // Label 9029: @457163
     /* 457163 */ GIM_Try, /*On fail goto*//*Label 9048*/ GIMT_Encode4(457237),
     /* 457168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 457171 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 457174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457178 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457182 */   GIM_Try, /*On fail goto*//*Label 9049*/ GIMT_Encode4(457213), // Rule ID 802 //
     /* 457187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457190 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457194 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457200 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457202 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457204 */     // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMEQv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 457204 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8i16rz),
     /* 457207 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457209 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457211 */     GIR_RootConstrainSelectedInstOperands,
     /* 457212 */     // GIR_Coverage, 802,
     /* 457212 */     GIR_EraseRootFromParent_Done,
     /* 457213 */   // Label 9049: @457213
     /* 457213 */   GIM_Try, /*On fail goto*//*Label 9050*/ GIMT_Encode4(457236), // Rule ID 1239 //
     /* 457218 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457221 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457225 */     // (AArch64fcmeq:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMEQv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 457225 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMEQv8f16),
     /* 457230 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457234 */     GIR_RootConstrainSelectedInstOperands,
     /* 457235 */     // GIR_Coverage, 1239,
     /* 457235 */     GIR_Done,
     /* 457236 */   // Label 9050: @457236
     /* 457236 */   GIM_Reject,
     /* 457237 */ // Label 9048: @457237
     /* 457237 */ GIM_Reject,
     /* 457238 */ // Label 9030: @457238
     /* 457238 */ GIM_Reject,
     /* 457239 */ // Label 142: @457239
     /* 457239 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 9058*/ GIMT_Encode4(458330),
     /* 457250 */ /*GILLT_s32*//*Label 9051*/ GIMT_Encode4(457286),
     /* 457254 */ /*GILLT_s64*//*Label 9052*/ GIMT_Encode4(457324), GIMT_Encode4(0),
     /* 457262 */ /*GILLT_v2s32*//*Label 9053*/ GIMT_Encode4(457465),
     /* 457266 */ /*GILLT_v2s64*//*Label 9054*/ GIMT_Encode4(457638),
     /* 457270 */ /*GILLT_v4s16*//*Label 9055*/ GIMT_Encode4(457811),
     /* 457274 */ /*GILLT_v4s32*//*Label 9056*/ GIMT_Encode4(457984), GIMT_Encode4(0),
     /* 457282 */ /*GILLT_v8s16*//*Label 9057*/ GIMT_Encode4(458157),
     /* 457286 */ // Label 9051: @457286
     /* 457286 */ GIM_Try, /*On fail goto*//*Label 9059*/ GIMT_Encode4(457323), // Rule ID 1630 //
     /* 457291 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457294 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 457297 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 457300 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 457304 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 457308 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 457312 */   // (AArch64fcmge:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMGE32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 457312 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE32),
     /* 457317 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457321 */   GIR_RootConstrainSelectedInstOperands,
     /* 457322 */   // GIR_Coverage, 1630,
     /* 457322 */   GIR_Done,
     /* 457323 */ // Label 9059: @457323
     /* 457323 */ GIM_Reject,
     /* 457324 */ // Label 9052: @457324
     /* 457324 */ GIM_Try, /*On fail goto*//*Label 9060*/ GIMT_Encode4(457464),
     /* 457329 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 457332 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 457335 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457339 */   GIM_Try, /*On fail goto*//*Label 9061*/ GIMT_Encode4(457374), // Rule ID 5311 //
     /* 457344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457347 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457351 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457357 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457359 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457363 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457365 */     // (AArch64fcmge:{ *:[v1i64] } immAllZerosV:{ *:[v1f64] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCMLEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 457365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv1i64rz),
     /* 457368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457370 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 457372 */     GIR_RootConstrainSelectedInstOperands,
     /* 457373 */     // GIR_Coverage, 5311,
     /* 457373 */     GIR_EraseRootFromParent_Done,
     /* 457374 */   // Label 9061: @457374
     /* 457374 */   GIM_Try, /*On fail goto*//*Label 9062*/ GIMT_Encode4(457409), // Rule ID 5309 //
     /* 457379 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457382 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457386 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457390 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457396 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457398 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457400 */     // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMGEv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 457400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv1i64rz),
     /* 457403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457405 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457407 */     GIR_RootConstrainSelectedInstOperands,
     /* 457408 */     // GIR_Coverage, 5309,
     /* 457408 */     GIR_EraseRootFromParent_Done,
     /* 457409 */   // Label 9062: @457409
     /* 457409 */   GIM_Try, /*On fail goto*//*Label 9063*/ GIMT_Encode4(457436), // Rule ID 1629 //
     /* 457414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457417 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457421 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457425 */     // (AArch64fcmge:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMGE64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 457425 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
     /* 457430 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457434 */     GIR_RootConstrainSelectedInstOperands,
     /* 457435 */     // GIR_Coverage, 1629,
     /* 457435 */     GIR_Done,
     /* 457436 */   // Label 9063: @457436
     /* 457436 */   GIM_Try, /*On fail goto*//*Label 9064*/ GIMT_Encode4(457463), // Rule ID 5263 //
     /* 457441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457444 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457448 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457452 */     // (AArch64fcmge:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMGE64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 457452 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGE64),
     /* 457457 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457461 */     GIR_RootConstrainSelectedInstOperands,
     /* 457462 */     // GIR_Coverage, 5263,
     /* 457462 */     GIR_Done,
     /* 457463 */   // Label 9064: @457463
     /* 457463 */   GIM_Reject,
     /* 457464 */ // Label 9060: @457464
     /* 457464 */ GIM_Reject,
     /* 457465 */ // Label 9053: @457465
     /* 457465 */ GIM_Try, /*On fail goto*//*Label 9065*/ GIMT_Encode4(457637),
     /* 457470 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 457473 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 457476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457480 */   GIM_Try, /*On fail goto*//*Label 9066*/ GIMT_Encode4(457539), // Rule ID 1202 //
     /* 457485 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457488 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457492 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457496 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 457500 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457505 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 457509 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457513 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 457517 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457522 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 457524 */     // (AArch64fcmge:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FACGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 457524 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f32),
     /* 457527 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457529 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 457533 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 457537 */     GIR_RootConstrainSelectedInstOperands,
     /* 457538 */     // GIR_Coverage, 1202,
     /* 457538 */     GIR_EraseRootFromParent_Done,
     /* 457539 */   // Label 9066: @457539
     /* 457539 */   GIM_Try, /*On fail goto*//*Label 9067*/ GIMT_Encode4(457574), // Rule ID 818 //
     /* 457544 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457547 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457551 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457557 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457559 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457563 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457565 */     // (AArch64fcmge:{ *:[v2i32] } immAllZerosV:{ *:[v2f32] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCMLEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 457565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i32rz),
     /* 457568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457570 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 457572 */     GIR_RootConstrainSelectedInstOperands,
     /* 457573 */     // GIR_Coverage, 818,
     /* 457573 */     GIR_EraseRootFromParent_Done,
     /* 457574 */   // Label 9067: @457574
     /* 457574 */   GIM_Try, /*On fail goto*//*Label 9068*/ GIMT_Encode4(457609), // Rule ID 808 //
     /* 457579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457582 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457586 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457590 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457596 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457598 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457600 */     // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMGEv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 457600 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i32rz),
     /* 457603 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457605 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457607 */     GIR_RootConstrainSelectedInstOperands,
     /* 457608 */     // GIR_Coverage, 808,
     /* 457608 */     GIR_EraseRootFromParent_Done,
     /* 457609 */   // Label 9068: @457609
     /* 457609 */   GIM_Try, /*On fail goto*//*Label 9069*/ GIMT_Encode4(457636), // Rule ID 1245 //
     /* 457614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457617 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457625 */     // (AArch64fcmge:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMGEv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 457625 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f32),
     /* 457630 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457634 */     GIR_RootConstrainSelectedInstOperands,
     /* 457635 */     // GIR_Coverage, 1245,
     /* 457635 */     GIR_Done,
     /* 457636 */   // Label 9069: @457636
     /* 457636 */   GIM_Reject,
     /* 457637 */ // Label 9065: @457637
     /* 457637 */ GIM_Reject,
     /* 457638 */ // Label 9054: @457638
     /* 457638 */ GIM_Try, /*On fail goto*//*Label 9070*/ GIMT_Encode4(457810),
     /* 457643 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 457646 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 457649 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457653 */   GIM_Try, /*On fail goto*//*Label 9071*/ GIMT_Encode4(457712), // Rule ID 1206 //
     /* 457658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457661 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457665 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457669 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 457673 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457678 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 457682 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457686 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 457690 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457695 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 457697 */     // (AArch64fcmge:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FACGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 457697 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv2f64),
     /* 457700 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457702 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 457706 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 457710 */     GIR_RootConstrainSelectedInstOperands,
     /* 457711 */     // GIR_Coverage, 1206,
     /* 457711 */     GIR_EraseRootFromParent_Done,
     /* 457712 */   // Label 9071: @457712
     /* 457712 */   GIM_Try, /*On fail goto*//*Label 9072*/ GIMT_Encode4(457747), // Rule ID 820 //
     /* 457717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457720 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457724 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457730 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457732 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457736 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457738 */     // (AArch64fcmge:{ *:[v2i64] } immAllZerosV:{ *:[v2f64] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCMLEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 457738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv2i64rz),
     /* 457741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457743 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 457745 */     GIR_RootConstrainSelectedInstOperands,
     /* 457746 */     // GIR_Coverage, 820,
     /* 457746 */     GIR_EraseRootFromParent_Done,
     /* 457747 */   // Label 9072: @457747
     /* 457747 */   GIM_Try, /*On fail goto*//*Label 9073*/ GIMT_Encode4(457782), // Rule ID 810 //
     /* 457752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457755 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457759 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457763 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457769 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457771 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457773 */     // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMGEv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 457773 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2i64rz),
     /* 457776 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457778 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457780 */     GIR_RootConstrainSelectedInstOperands,
     /* 457781 */     // GIR_Coverage, 810,
     /* 457781 */     GIR_EraseRootFromParent_Done,
     /* 457782 */   // Label 9073: @457782
     /* 457782 */   GIM_Try, /*On fail goto*//*Label 9074*/ GIMT_Encode4(457809), // Rule ID 1247 //
     /* 457787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 457790 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457794 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457798 */     // (AArch64fcmge:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMGEv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 457798 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv2f64),
     /* 457803 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457807 */     GIR_RootConstrainSelectedInstOperands,
     /* 457808 */     // GIR_Coverage, 1247,
     /* 457808 */     GIR_Done,
     /* 457809 */   // Label 9074: @457809
     /* 457809 */   GIM_Reject,
     /* 457810 */ // Label 9070: @457810
     /* 457810 */ GIM_Reject,
     /* 457811 */ // Label 9055: @457811
     /* 457811 */ GIM_Try, /*On fail goto*//*Label 9075*/ GIMT_Encode4(457983),
     /* 457816 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 457819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 457822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457826 */   GIM_Try, /*On fail goto*//*Label 9076*/ GIMT_Encode4(457885), // Rule ID 1198 //
     /* 457831 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457834 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457838 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457842 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 457846 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457851 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 457855 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 457859 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 457863 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457868 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 457870 */     // (AArch64fcmge:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FACGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 457870 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f16),
     /* 457873 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 457879 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 457883 */     GIR_RootConstrainSelectedInstOperands,
     /* 457884 */     // GIR_Coverage, 1198,
     /* 457884 */     GIR_EraseRootFromParent_Done,
     /* 457885 */   // Label 9076: @457885
     /* 457885 */   GIM_Try, /*On fail goto*//*Label 9077*/ GIMT_Encode4(457920), // Rule ID 816 //
     /* 457890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457893 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 457897 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457903 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457905 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457909 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457911 */     // (AArch64fcmge:{ *:[v4i16] } immAllZerosV:{ *:[v4f16] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCMLEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 457911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i16rz),
     /* 457914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457916 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 457918 */     GIR_RootConstrainSelectedInstOperands,
     /* 457919 */     // GIR_Coverage, 816,
     /* 457919 */     GIR_EraseRootFromParent_Done,
     /* 457920 */   // Label 9077: @457920
     /* 457920 */   GIM_Try, /*On fail goto*//*Label 9078*/ GIMT_Encode4(457955), // Rule ID 806 //
     /* 457925 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457928 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457932 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 457936 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 457942 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 457944 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 457946 */     // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMGEv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 457946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i16rz),
     /* 457949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 457951 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 457953 */     GIR_RootConstrainSelectedInstOperands,
     /* 457954 */     // GIR_Coverage, 806,
     /* 457954 */     GIR_EraseRootFromParent_Done,
     /* 457955 */   // Label 9078: @457955
     /* 457955 */   GIM_Try, /*On fail goto*//*Label 9079*/ GIMT_Encode4(457982), // Rule ID 1243 //
     /* 457960 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 457963 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457967 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 457971 */     // (AArch64fcmge:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMGEv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 457971 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f16),
     /* 457976 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 457980 */     GIR_RootConstrainSelectedInstOperands,
     /* 457981 */     // GIR_Coverage, 1243,
     /* 457981 */     GIR_Done,
     /* 457982 */   // Label 9079: @457982
     /* 457982 */   GIM_Reject,
     /* 457983 */ // Label 9075: @457983
     /* 457983 */ GIM_Reject,
     /* 457984 */ // Label 9056: @457984
     /* 457984 */ GIM_Try, /*On fail goto*//*Label 9080*/ GIMT_Encode4(458156),
     /* 457989 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 457992 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 457995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 457999 */   GIM_Try, /*On fail goto*//*Label 9081*/ GIMT_Encode4(458058), // Rule ID 1204 //
     /* 458004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458007 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458011 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458015 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 458019 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458024 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 458028 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458032 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 458036 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458041 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 458043 */     // (AArch64fcmge:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FACGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 458043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv4f32),
     /* 458046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458048 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 458052 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 458056 */     GIR_RootConstrainSelectedInstOperands,
     /* 458057 */     // GIR_Coverage, 1204,
     /* 458057 */     GIR_EraseRootFromParent_Done,
     /* 458058 */   // Label 9081: @458058
     /* 458058 */   GIM_Try, /*On fail goto*//*Label 9082*/ GIMT_Encode4(458093), // Rule ID 819 //
     /* 458063 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458066 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458070 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458076 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458078 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458082 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458084 */     // (AArch64fcmge:{ *:[v4i32] } immAllZerosV:{ *:[v4f32] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCMLEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 458084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv4i32rz),
     /* 458087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458089 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 458091 */     GIR_RootConstrainSelectedInstOperands,
     /* 458092 */     // GIR_Coverage, 819,
     /* 458092 */     GIR_EraseRootFromParent_Done,
     /* 458093 */   // Label 9082: @458093
     /* 458093 */   GIM_Try, /*On fail goto*//*Label 9083*/ GIMT_Encode4(458128), // Rule ID 809 //
     /* 458098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458101 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 458109 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458115 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458117 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458119 */     // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMGEv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 458119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4i32rz),
     /* 458122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458124 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 458126 */     GIR_RootConstrainSelectedInstOperands,
     /* 458127 */     // GIR_Coverage, 809,
     /* 458127 */     GIR_EraseRootFromParent_Done,
     /* 458128 */   // Label 9083: @458128
     /* 458128 */   GIM_Try, /*On fail goto*//*Label 9084*/ GIMT_Encode4(458155), // Rule ID 1246 //
     /* 458133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458136 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458140 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458144 */     // (AArch64fcmge:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMGEv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 458144 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv4f32),
     /* 458149 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458153 */     GIR_RootConstrainSelectedInstOperands,
     /* 458154 */     // GIR_Coverage, 1246,
     /* 458154 */     GIR_Done,
     /* 458155 */   // Label 9084: @458155
     /* 458155 */   GIM_Reject,
     /* 458156 */ // Label 9080: @458156
     /* 458156 */ GIM_Reject,
     /* 458157 */ // Label 9057: @458157
     /* 458157 */ GIM_Try, /*On fail goto*//*Label 9085*/ GIMT_Encode4(458329),
     /* 458162 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 458165 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 458168 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458172 */   GIM_Try, /*On fail goto*//*Label 9086*/ GIMT_Encode4(458231), // Rule ID 1200 //
     /* 458177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 458192 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458197 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 458201 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458205 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 458209 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458214 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 458216 */     // (AArch64fcmge:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FACGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 458216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGEv8f16),
     /* 458219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458221 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 458225 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 458229 */     GIR_RootConstrainSelectedInstOperands,
     /* 458230 */     // GIR_Coverage, 1200,
     /* 458230 */     GIR_EraseRootFromParent_Done,
     /* 458231 */   // Label 9086: @458231
     /* 458231 */   GIM_Try, /*On fail goto*//*Label 9087*/ GIMT_Encode4(458266), // Rule ID 817 //
     /* 458236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458239 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458243 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458249 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458251 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458255 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458257 */     // (AArch64fcmge:{ *:[v8i16] } immAllZerosV:{ *:[v8f16] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCMLEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 458257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLEv8i16rz),
     /* 458260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458262 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 458264 */     GIR_RootConstrainSelectedInstOperands,
     /* 458265 */     // GIR_Coverage, 817,
     /* 458265 */     GIR_EraseRootFromParent_Done,
     /* 458266 */   // Label 9087: @458266
     /* 458266 */   GIM_Try, /*On fail goto*//*Label 9088*/ GIMT_Encode4(458301), // Rule ID 807 //
     /* 458271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458278 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 458282 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458288 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458290 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458292 */     // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMGEv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 458292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8i16rz),
     /* 458295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458297 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 458299 */     GIR_RootConstrainSelectedInstOperands,
     /* 458300 */     // GIR_Coverage, 807,
     /* 458300 */     GIR_EraseRootFromParent_Done,
     /* 458301 */   // Label 9088: @458301
     /* 458301 */   GIM_Try, /*On fail goto*//*Label 9089*/ GIMT_Encode4(458328), // Rule ID 1244 //
     /* 458306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458309 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458313 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458317 */     // (AArch64fcmge:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMGEv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 458317 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGEv8f16),
     /* 458322 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458326 */     GIR_RootConstrainSelectedInstOperands,
     /* 458327 */     // GIR_Coverage, 1244,
     /* 458327 */     GIR_Done,
     /* 458328 */   // Label 9089: @458328
     /* 458328 */   GIM_Reject,
     /* 458329 */ // Label 9085: @458329
     /* 458329 */ GIM_Reject,
     /* 458330 */ // Label 9058: @458330
     /* 458330 */ GIM_Reject,
     /* 458331 */ // Label 143: @458331
     /* 458331 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(11), /*)*//*default:*//*Label 9097*/ GIMT_Encode4(459422),
     /* 458342 */ /*GILLT_s32*//*Label 9090*/ GIMT_Encode4(458378),
     /* 458346 */ /*GILLT_s64*//*Label 9091*/ GIMT_Encode4(458416), GIMT_Encode4(0),
     /* 458354 */ /*GILLT_v2s32*//*Label 9092*/ GIMT_Encode4(458557),
     /* 458358 */ /*GILLT_v2s64*//*Label 9093*/ GIMT_Encode4(458730),
     /* 458362 */ /*GILLT_v4s16*//*Label 9094*/ GIMT_Encode4(458903),
     /* 458366 */ /*GILLT_v4s32*//*Label 9095*/ GIMT_Encode4(459076), GIMT_Encode4(0),
     /* 458374 */ /*GILLT_v8s16*//*Label 9096*/ GIMT_Encode4(459249),
     /* 458378 */ // Label 9090: @458378
     /* 458378 */ GIM_Try, /*On fail goto*//*Label 9098*/ GIMT_Encode4(458415), // Rule ID 1632 //
     /* 458383 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458386 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 458389 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 458392 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 458396 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 458400 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 458404 */   // (AArch64fcmgt:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)  =>  (FCMGT32:{ *:[i32] } FPR32:{ *:[f32] }:$Rn, FPR32:{ *:[f32] }:$Rm)
     /* 458404 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT32),
     /* 458409 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458413 */   GIR_RootConstrainSelectedInstOperands,
     /* 458414 */   // GIR_Coverage, 1632,
     /* 458414 */   GIR_Done,
     /* 458415 */ // Label 9098: @458415
     /* 458415 */ GIM_Reject,
     /* 458416 */ // Label 9091: @458416
     /* 458416 */ GIM_Try, /*On fail goto*//*Label 9099*/ GIMT_Encode4(458556),
     /* 458421 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 458424 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 458427 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458431 */   GIM_Try, /*On fail goto*//*Label 9100*/ GIMT_Encode4(458466), // Rule ID 5312 //
     /* 458436 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458443 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458449 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458451 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458455 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458457 */     // (AArch64fcmgt:{ *:[v1i64] } immAllZerosV:{ *:[v1f64] }, FPR64:{ *:[v1f64] }:$Rn)  =>  (FCMLTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 458457 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv1i64rz),
     /* 458460 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458462 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 458464 */     GIR_RootConstrainSelectedInstOperands,
     /* 458465 */     // GIR_Coverage, 5312,
     /* 458465 */     GIR_EraseRootFromParent_Done,
     /* 458466 */   // Label 9100: @458466
     /* 458466 */   GIM_Try, /*On fail goto*//*Label 9101*/ GIMT_Encode4(458501), // Rule ID 5310 //
     /* 458471 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458474 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458478 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 458482 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458488 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458490 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458492 */     // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, immAllZerosV:{ *:[v1f64] })  =>  (FCMGTv1i64rz:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn)
     /* 458492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv1i64rz),
     /* 458495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458497 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 458499 */     GIR_RootConstrainSelectedInstOperands,
     /* 458500 */     // GIR_Coverage, 5310,
     /* 458500 */     GIR_EraseRootFromParent_Done,
     /* 458501 */   // Label 9101: @458501
     /* 458501 */   GIM_Try, /*On fail goto*//*Label 9102*/ GIMT_Encode4(458528), // Rule ID 1631 //
     /* 458506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458509 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458513 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458517 */     // (AArch64fcmgt:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)  =>  (FCMGT64:{ *:[i64] } FPR64:{ *:[f64] }:$Rn, FPR64:{ *:[f64] }:$Rm)
     /* 458517 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
     /* 458522 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458526 */     GIR_RootConstrainSelectedInstOperands,
     /* 458527 */     // GIR_Coverage, 1631,
     /* 458527 */     GIR_Done,
     /* 458528 */   // Label 9102: @458528
     /* 458528 */   GIM_Try, /*On fail goto*//*Label 9103*/ GIMT_Encode4(458555), // Rule ID 5264 //
     /* 458533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458536 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458544 */     // (AArch64fcmgt:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)  =>  (FCMGT64:{ *:[v1i64] } FPR64:{ *:[v1f64] }:$Rn, FPR64:{ *:[v1f64] }:$Rm)
     /* 458544 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGT64),
     /* 458549 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458553 */     GIR_RootConstrainSelectedInstOperands,
     /* 458554 */     // GIR_Coverage, 5264,
     /* 458554 */     GIR_Done,
     /* 458555 */   // Label 9103: @458555
     /* 458555 */   GIM_Reject,
     /* 458556 */ // Label 9099: @458556
     /* 458556 */ GIM_Reject,
     /* 458557 */ // Label 9092: @458557
     /* 458557 */ GIM_Try, /*On fail goto*//*Label 9104*/ GIMT_Encode4(458729),
     /* 458562 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 458565 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 458568 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458572 */   GIM_Try, /*On fail goto*//*Label 9105*/ GIMT_Encode4(458631), // Rule ID 1212 //
     /* 458577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458580 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458584 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458588 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 458592 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458597 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 458601 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458605 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 458609 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458614 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 458616 */     // (AArch64fcmgt:{ *:[v2i32] } (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn), (fabs:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rm))  =>  (FACGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 458616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f32),
     /* 458619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458621 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 458625 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 458629 */     GIR_RootConstrainSelectedInstOperands,
     /* 458630 */     // GIR_Coverage, 1212,
     /* 458630 */     GIR_EraseRootFromParent_Done,
     /* 458631 */   // Label 9105: @458631
     /* 458631 */   GIM_Try, /*On fail goto*//*Label 9106*/ GIMT_Encode4(458666), // Rule ID 823 //
     /* 458636 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458639 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458643 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458649 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458651 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458655 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458657 */     // (AArch64fcmgt:{ *:[v2i32] } immAllZerosV:{ *:[v2f32] }, V64:{ *:[v2f32] }:$Rn)  =>  (FCMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 458657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i32rz),
     /* 458660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458662 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 458664 */     GIR_RootConstrainSelectedInstOperands,
     /* 458665 */     // GIR_Coverage, 823,
     /* 458665 */     GIR_EraseRootFromParent_Done,
     /* 458666 */   // Label 9106: @458666
     /* 458666 */   GIM_Try, /*On fail goto*//*Label 9107*/ GIMT_Encode4(458701), // Rule ID 813 //
     /* 458671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458674 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458678 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 458682 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458688 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458690 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458692 */     // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, immAllZerosV:{ *:[v2f32] })  =>  (FCMGTv2i32rz:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn)
     /* 458692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i32rz),
     /* 458695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458697 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 458699 */     GIR_RootConstrainSelectedInstOperands,
     /* 458700 */     // GIR_Coverage, 813,
     /* 458700 */     GIR_EraseRootFromParent_Done,
     /* 458701 */   // Label 9107: @458701
     /* 458701 */   GIM_Try, /*On fail goto*//*Label 9108*/ GIMT_Encode4(458728), // Rule ID 1250 //
     /* 458706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458709 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458717 */     // (AArch64fcmgt:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (FCMGTv2f32:{ *:[v2i32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 458717 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f32),
     /* 458722 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458726 */     GIR_RootConstrainSelectedInstOperands,
     /* 458727 */     // GIR_Coverage, 1250,
     /* 458727 */     GIR_Done,
     /* 458728 */   // Label 9108: @458728
     /* 458728 */   GIM_Reject,
     /* 458729 */ // Label 9104: @458729
     /* 458729 */ GIM_Reject,
     /* 458730 */ // Label 9093: @458730
     /* 458730 */ GIM_Try, /*On fail goto*//*Label 9109*/ GIMT_Encode4(458902),
     /* 458735 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 458738 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 458741 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458745 */   GIM_Try, /*On fail goto*//*Label 9110*/ GIMT_Encode4(458804), // Rule ID 1216 //
     /* 458750 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458753 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458757 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458761 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 458765 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458770 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 458774 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458778 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 458782 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458787 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 458789 */     // (AArch64fcmgt:{ *:[v2i64] } (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn), (fabs:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rm))  =>  (FACGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 458789 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv2f64),
     /* 458792 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458794 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 458798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 458802 */     GIR_RootConstrainSelectedInstOperands,
     /* 458803 */     // GIR_Coverage, 1216,
     /* 458803 */     GIR_EraseRootFromParent_Done,
     /* 458804 */   // Label 9110: @458804
     /* 458804 */   GIM_Try, /*On fail goto*//*Label 9111*/ GIMT_Encode4(458839), // Rule ID 825 //
     /* 458809 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458812 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458816 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458822 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458824 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458828 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458830 */     // (AArch64fcmgt:{ *:[v2i64] } immAllZerosV:{ *:[v2f64] }, V128:{ *:[v2f64] }:$Rn)  =>  (FCMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 458830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv2i64rz),
     /* 458833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458835 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 458837 */     GIR_RootConstrainSelectedInstOperands,
     /* 458838 */     // GIR_Coverage, 825,
     /* 458838 */     GIR_EraseRootFromParent_Done,
     /* 458839 */   // Label 9111: @458839
     /* 458839 */   GIM_Try, /*On fail goto*//*Label 9112*/ GIMT_Encode4(458874), // Rule ID 815 //
     /* 458844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458847 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458851 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 458855 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458861 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458863 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 458865 */     // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, immAllZerosV:{ *:[v2f64] })  =>  (FCMGTv2i64rz:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn)
     /* 458865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2i64rz),
     /* 458868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458870 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 458872 */     GIR_RootConstrainSelectedInstOperands,
     /* 458873 */     // GIR_Coverage, 815,
     /* 458873 */     GIR_EraseRootFromParent_Done,
     /* 458874 */   // Label 9112: @458874
     /* 458874 */   GIM_Try, /*On fail goto*//*Label 9113*/ GIMT_Encode4(458901), // Rule ID 1252 //
     /* 458879 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 458882 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458886 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 458890 */     // (AArch64fcmgt:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (FCMGTv2f64:{ *:[v2i64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 458890 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv2f64),
     /* 458895 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 458899 */     GIR_RootConstrainSelectedInstOperands,
     /* 458900 */     // GIR_Coverage, 1252,
     /* 458900 */     GIR_Done,
     /* 458901 */   // Label 9113: @458901
     /* 458901 */   GIM_Reject,
     /* 458902 */ // Label 9109: @458902
     /* 458902 */ GIM_Reject,
     /* 458903 */ // Label 9094: @458903
     /* 458903 */ GIM_Try, /*On fail goto*//*Label 9114*/ GIMT_Encode4(459075),
     /* 458908 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 458911 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 458914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458918 */   GIM_Try, /*On fail goto*//*Label 9115*/ GIMT_Encode4(458977), // Rule ID 1208 //
     /* 458923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458926 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458930 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458934 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 458938 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458943 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 458947 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 458951 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 458955 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 458960 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 458962 */     // (AArch64fcmgt:{ *:[v4i16] } (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn), (fabs:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rm))  =>  (FACGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 458962 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f16),
     /* 458965 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 458967 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 458971 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 458975 */     GIR_RootConstrainSelectedInstOperands,
     /* 458976 */     // GIR_Coverage, 1208,
     /* 458976 */     GIR_EraseRootFromParent_Done,
     /* 458977 */   // Label 9115: @458977
     /* 458977 */   GIM_Try, /*On fail goto*//*Label 9116*/ GIMT_Encode4(459012), // Rule ID 821 //
     /* 458982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 458985 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 458989 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 458995 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 458997 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459001 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459003 */     // (AArch64fcmgt:{ *:[v4i16] } immAllZerosV:{ *:[v4f16] }, V64:{ *:[v4f16] }:$Rn)  =>  (FCMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 459003 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i16rz),
     /* 459006 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459008 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 459010 */     GIR_RootConstrainSelectedInstOperands,
     /* 459011 */     // GIR_Coverage, 821,
     /* 459011 */     GIR_EraseRootFromParent_Done,
     /* 459012 */   // Label 9116: @459012
     /* 459012 */   GIM_Try, /*On fail goto*//*Label 9117*/ GIMT_Encode4(459047), // Rule ID 811 //
     /* 459017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459020 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 459028 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 459034 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 459036 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459038 */     // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, immAllZerosV:{ *:[v4f16] })  =>  (FCMGTv4i16rz:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn)
     /* 459038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i16rz),
     /* 459041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459043 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 459045 */     GIR_RootConstrainSelectedInstOperands,
     /* 459046 */     // GIR_Coverage, 811,
     /* 459046 */     GIR_EraseRootFromParent_Done,
     /* 459047 */   // Label 9117: @459047
     /* 459047 */   GIM_Try, /*On fail goto*//*Label 9118*/ GIMT_Encode4(459074), // Rule ID 1248 //
     /* 459052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459055 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459059 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459063 */     // (AArch64fcmgt:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (FCMGTv4f16:{ *:[v4i16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 459063 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f16),
     /* 459068 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 459072 */     GIR_RootConstrainSelectedInstOperands,
     /* 459073 */     // GIR_Coverage, 1248,
     /* 459073 */     GIR_Done,
     /* 459074 */   // Label 9118: @459074
     /* 459074 */   GIM_Reject,
     /* 459075 */ // Label 9114: @459075
     /* 459075 */ GIM_Reject,
     /* 459076 */ // Label 9095: @459076
     /* 459076 */ GIM_Try, /*On fail goto*//*Label 9119*/ GIMT_Encode4(459248),
     /* 459081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 459084 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 459087 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459091 */   GIM_Try, /*On fail goto*//*Label 9120*/ GIMT_Encode4(459150), // Rule ID 1214 //
     /* 459096 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459099 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 459103 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 459107 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 459111 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459116 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 459120 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 459124 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 459128 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459133 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 459135 */     // (AArch64fcmgt:{ *:[v4i32] } (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn), (fabs:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rm))  =>  (FACGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 459135 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv4f32),
     /* 459138 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459140 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 459144 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 459148 */     GIR_RootConstrainSelectedInstOperands,
     /* 459149 */     // GIR_Coverage, 1214,
     /* 459149 */     GIR_EraseRootFromParent_Done,
     /* 459150 */   // Label 9120: @459150
     /* 459150 */   GIM_Try, /*On fail goto*//*Label 9121*/ GIMT_Encode4(459185), // Rule ID 824 //
     /* 459155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459158 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 459162 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 459168 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 459170 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459174 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459176 */     // (AArch64fcmgt:{ *:[v4i32] } immAllZerosV:{ *:[v4f32] }, V128:{ *:[v4f32] }:$Rn)  =>  (FCMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 459176 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv4i32rz),
     /* 459179 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459181 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 459183 */     GIR_RootConstrainSelectedInstOperands,
     /* 459184 */     // GIR_Coverage, 824,
     /* 459184 */     GIR_EraseRootFromParent_Done,
     /* 459185 */   // Label 9121: @459185
     /* 459185 */   GIM_Try, /*On fail goto*//*Label 9122*/ GIMT_Encode4(459220), // Rule ID 814 //
     /* 459190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459193 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459197 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 459201 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 459207 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 459209 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459211 */     // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, immAllZerosV:{ *:[v4f32] })  =>  (FCMGTv4i32rz:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn)
     /* 459211 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4i32rz),
     /* 459214 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459216 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 459218 */     GIR_RootConstrainSelectedInstOperands,
     /* 459219 */     // GIR_Coverage, 814,
     /* 459219 */     GIR_EraseRootFromParent_Done,
     /* 459220 */   // Label 9122: @459220
     /* 459220 */   GIM_Try, /*On fail goto*//*Label 9123*/ GIMT_Encode4(459247), // Rule ID 1251 //
     /* 459225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459228 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459232 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459236 */     // (AArch64fcmgt:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (FCMGTv4f32:{ *:[v4i32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 459236 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv4f32),
     /* 459241 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 459245 */     GIR_RootConstrainSelectedInstOperands,
     /* 459246 */     // GIR_Coverage, 1251,
     /* 459246 */     GIR_Done,
     /* 459247 */   // Label 9123: @459247
     /* 459247 */   GIM_Reject,
     /* 459248 */ // Label 9119: @459248
     /* 459248 */ GIM_Reject,
     /* 459249 */ // Label 9096: @459249
     /* 459249 */ GIM_Try, /*On fail goto*//*Label 9124*/ GIMT_Encode4(459421),
     /* 459254 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 459257 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 459260 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459264 */   GIM_Try, /*On fail goto*//*Label 9125*/ GIMT_Encode4(459323), // Rule ID 1210 //
     /* 459269 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459272 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 459276 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 459280 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 459284 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459289 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
     /* 459293 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
     /* 459297 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 459301 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459306 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 459308 */     // (AArch64fcmgt:{ *:[v8i16] } (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn), (fabs:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rm))  =>  (FACGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 459308 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FACGTv8f16),
     /* 459311 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459313 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
     /* 459317 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 459321 */     GIR_RootConstrainSelectedInstOperands,
     /* 459322 */     // GIR_Coverage, 1210,
     /* 459322 */     GIR_EraseRootFromParent_Done,
     /* 459323 */   // Label 9125: @459323
     /* 459323 */   GIM_Try, /*On fail goto*//*Label 9126*/ GIMT_Encode4(459358), // Rule ID 822 //
     /* 459328 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459331 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 459335 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 459341 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 459343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459347 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459349 */     // (AArch64fcmgt:{ *:[v8i16] } immAllZerosV:{ *:[v8f16] }, V128:{ *:[v8f16] }:$Rn)  =>  (FCMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 459349 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMLTv8i16rz),
     /* 459352 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459354 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 459356 */     GIR_RootConstrainSelectedInstOperands,
     /* 459357 */     // GIR_Coverage, 822,
     /* 459357 */     GIR_EraseRootFromParent_Done,
     /* 459358 */   // Label 9126: @459358
     /* 459358 */   GIM_Try, /*On fail goto*//*Label 9127*/ GIMT_Encode4(459393), // Rule ID 812 //
     /* 459363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459366 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459370 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 459374 */     GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
     /* 459380 */     GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
     /* 459382 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 459384 */     // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, immAllZerosV:{ *:[v8f16] })  =>  (FCMGTv8i16rz:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn)
     /* 459384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8i16rz),
     /* 459387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459389 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 459391 */     GIR_RootConstrainSelectedInstOperands,
     /* 459392 */     // GIR_Coverage, 812,
     /* 459392 */     GIR_EraseRootFromParent_Done,
     /* 459393 */   // Label 9127: @459393
     /* 459393 */   GIM_Try, /*On fail goto*//*Label 9128*/ GIMT_Encode4(459420), // Rule ID 1249 //
     /* 459398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
     /* 459401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459409 */     // (AArch64fcmgt:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (FCMGTv8f16:{ *:[v8i16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 459409 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCMGTv8f16),
     /* 459414 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 459418 */     GIR_RootConstrainSelectedInstOperands,
     /* 459419 */     // GIR_Coverage, 1249,
     /* 459419 */     GIR_Done,
     /* 459420 */   // Label 9128: @459420
     /* 459420 */   GIM_Reject,
     /* 459421 */ // Label 9124: @459421
     /* 459421 */ GIM_Reject,
     /* 459422 */ // Label 9097: @459422
     /* 459422 */ GIM_Reject,
     /* 459423 */ // Label 144: @459423
     /* 459423 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(6), /*)*//*default:*//*Label 9131*/ GIMT_Encode4(459512),
     /* 459434 */ /*GILLT_s32*//*Label 9129*/ GIMT_Encode4(459450), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 459446 */ /*GILLT_v2s32*//*Label 9130*/ GIMT_Encode4(459481),
     /* 459450 */ // Label 9129: @459450
     /* 459450 */ GIM_Try, /*On fail goto*//*Label 9132*/ GIMT_Encode4(459480), // Rule ID 1684 //
     /* 459455 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459458 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 459461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 459465 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459469 */   // (AArch64fcvtxn_n:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)  =>  (FCVTXNv1i64:{ *:[f32] } FPR64:{ *:[f64] }:$Rn)
     /* 459469 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv1i64),
     /* 459474 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 459478 */   GIR_RootConstrainSelectedInstOperands,
     /* 459479 */   // GIR_Coverage, 1684,
     /* 459479 */   GIR_Done,
     /* 459480 */ // Label 9132: @459480
     /* 459480 */ GIM_Reject,
     /* 459481 */ // Label 9130: @459481
     /* 459481 */ GIM_Try, /*On fail goto*//*Label 9133*/ GIMT_Encode4(459511), // Rule ID 867 //
     /* 459486 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459489 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 459492 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459496 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459500 */   // (AArch64fcvtxn_n:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)  =>  (FCVTXNv2f32:{ *:[v2f32] } V128:{ *:[v2f64] }:$Rn)
     /* 459500 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::FCVTXNv2f32),
     /* 459505 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 459509 */   GIR_RootConstrainSelectedInstOperands,
     /* 459510 */   // GIR_Coverage, 867,
     /* 459510 */   GIR_Done,
     /* 459511 */ // Label 9133: @459511
     /* 459511 */ GIM_Reject,
     /* 459512 */ // Label 9131: @459512
     /* 459512 */ GIM_Reject,
     /* 459513 */ // Label 145: @459513
     /* 459513 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(12), /*)*//*default:*//*Label 9136*/ GIMT_Encode4(459645),
     /* 459524 */ /*GILLT_v8s16*//*Label 9134*/ GIMT_Encode4(459532),
     /* 459528 */ /*GILLT_v16s8*//*Label 9135*/ GIMT_Encode4(459611),
     /* 459532 */ // Label 9134: @459532
     /* 459532 */ GIM_Try, /*On fail goto*//*Label 9137*/ GIMT_Encode4(459610),
     /* 459537 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 459540 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 459543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459547 */   GIM_Try, /*On fail goto*//*Label 9138*/ GIMT_Encode4(459586), // Rule ID 1728 //
     /* 459552 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459555 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 459562 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 459569 */     // (AArch64pmull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (PMULLv16i8:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 459569 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::PMULLv16i8),
     /* 459572 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 459574 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 459579 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 459584 */     GIR_RootConstrainSelectedInstOperands,
     /* 459585 */     // GIR_Coverage, 1728,
     /* 459585 */     GIR_EraseRootFromParent_Done,
     /* 459586 */   // Label 9138: @459586
     /* 459586 */   GIM_Try, /*On fail goto*//*Label 9139*/ GIMT_Encode4(459609), // Rule ID 1727 //
     /* 459591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459602 */     // (AArch64pmull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (PMULLv8i8:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 459602 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::PMULLv8i8),
     /* 459607 */     GIR_RootConstrainSelectedInstOperands,
     /* 459608 */     // GIR_Coverage, 1727,
     /* 459608 */     GIR_Done,
     /* 459609 */   // Label 9139: @459609
     /* 459609 */   GIM_Reject,
     /* 459610 */ // Label 9137: @459610
     /* 459610 */ GIM_Reject,
     /* 459611 */ // Label 9135: @459611
     /* 459611 */ GIM_Try, /*On fail goto*//*Label 9140*/ GIMT_Encode4(459644), // Rule ID 1729 //
     /* 459616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES),
     /* 459619 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 459622 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 459625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459629 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459633 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459637 */   // (AArch64pmull:{ *:[v16i8] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)  =>  (PMULLv1i64:{ *:[v16i8] } V64:{ *:[v1i64] }:$Rn, V64:{ *:[v1i64] }:$Rm)
     /* 459637 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::PMULLv1i64),
     /* 459642 */   GIR_RootConstrainSelectedInstOperands,
     /* 459643 */   // GIR_Coverage, 1729,
     /* 459643 */   GIR_Done,
     /* 459644 */ // Label 9140: @459644
     /* 459644 */ GIM_Reject,
     /* 459645 */ // Label 9136: @459645
     /* 459645 */ GIM_Reject,
     /* 459646 */ // Label 146: @459646
     /* 459646 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 9145*/ GIMT_Encode4(459799),
     /* 459657 */ /*GILLT_s32*//*Label 9141*/ GIMT_Encode4(459697),
     /* 459661 */ /*GILLT_s64*//*Label 9142*/ GIMT_Encode4(459721), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 459685 */ /*GILLT_v8s8*//*Label 9143*/ GIMT_Encode4(459745), GIMT_Encode4(0),
     /* 459693 */ /*GILLT_v16s8*//*Label 9144*/ GIMT_Encode4(459772),
     /* 459697 */ // Label 9141: @459697
     /* 459697 */ GIM_Try, /*On fail goto*//*Label 9146*/ GIMT_Encode4(459720), // Rule ID 4111 //
     /* 459702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 459705 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 459709 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR32RegClassID),
     /* 459713 */   // (AArch64rev16:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)  =>  (REV16Wr:{ *:[i32] } GPR32:{ *:[i32] }:$Rn)
     /* 459713 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16Wr),
     /* 459718 */   GIR_RootConstrainSelectedInstOperands,
     /* 459719 */   // GIR_Coverage, 4111,
     /* 459719 */   GIR_Done,
     /* 459720 */ // Label 9146: @459720
     /* 459720 */ GIM_Reject,
     /* 459721 */ // Label 9142: @459721
     /* 459721 */ GIM_Try, /*On fail goto*//*Label 9147*/ GIMT_Encode4(459744), // Rule ID 4112 //
     /* 459726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 459729 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 459733 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::GPR64RegClassID),
     /* 459737 */   // (AArch64rev16:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)  =>  (REV16Xr:{ *:[i64] } GPR64:{ *:[i64] }:$Rn)
     /* 459737 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16Xr),
     /* 459742 */   GIR_RootConstrainSelectedInstOperands,
     /* 459743 */   // GIR_Coverage, 4112,
     /* 459743 */   GIR_Done,
     /* 459744 */ // Label 9147: @459744
     /* 459744 */ GIM_Reject,
     /* 459745 */ // Label 9143: @459745
     /* 459745 */ GIM_Try, /*On fail goto*//*Label 9148*/ GIMT_Encode4(459771), // Rule ID 1006 //
     /* 459750 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459753 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 459756 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459760 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459764 */   // (AArch64rev16:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV16v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 459764 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v8i8),
     /* 459769 */   GIR_RootConstrainSelectedInstOperands,
     /* 459770 */   // GIR_Coverage, 1006,
     /* 459770 */   GIR_Done,
     /* 459771 */ // Label 9148: @459771
     /* 459771 */ GIM_Reject,
     /* 459772 */ // Label 9144: @459772
     /* 459772 */ GIM_Try, /*On fail goto*//*Label 9149*/ GIMT_Encode4(459798), // Rule ID 1007 //
     /* 459777 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459780 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 459783 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459787 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459791 */   // (AArch64rev16:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV16v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 459791 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV16v16i8),
     /* 459796 */   GIR_RootConstrainSelectedInstOperands,
     /* 459797 */   // GIR_Coverage, 1007,
     /* 459797 */   GIR_Done,
     /* 459798 */ // Label 9149: @459798
     /* 459798 */ GIM_Reject,
     /* 459799 */ // Label 9145: @459799
     /* 459799 */ GIM_Reject,
     /* 459800 */ // Label 147: @459800
     /* 459800 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 9154*/ GIMT_Encode4(459975),
     /* 459811 */ /*GILLT_v4s16*//*Label 9150*/ GIMT_Encode4(459831), GIMT_Encode4(0),
     /* 459819 */ /*GILLT_v8s8*//*Label 9151*/ GIMT_Encode4(459876),
     /* 459823 */ /*GILLT_v8s16*//*Label 9152*/ GIMT_Encode4(459903),
     /* 459827 */ /*GILLT_v16s8*//*Label 9153*/ GIMT_Encode4(459948),
     /* 459831 */ // Label 9150: @459831
     /* 459831 */ GIM_Try, /*On fail goto*//*Label 9155*/ GIMT_Encode4(459875),
     /* 459836 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 459839 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459843 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459847 */   GIM_Try, /*On fail goto*//*Label 9156*/ GIMT_Encode4(459862), // Rule ID 1010 //
     /* 459852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459855 */     // (AArch64rev32:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV32v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 459855 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 459860 */     GIR_RootConstrainSelectedInstOperands,
     /* 459861 */     // GIR_Coverage, 1010,
     /* 459861 */     GIR_Done,
     /* 459862 */   // Label 9156: @459862
     /* 459862 */   GIM_Try, /*On fail goto*//*Label 9157*/ GIMT_Encode4(459874), // Rule ID 5033 //
     /* 459867 */     // (AArch64rev32:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (REV32v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 459867 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v4i16),
     /* 459872 */     GIR_RootConstrainSelectedInstOperands,
     /* 459873 */     // GIR_Coverage, 5033,
     /* 459873 */     GIR_Done,
     /* 459874 */   // Label 9157: @459874
     /* 459874 */   GIM_Reject,
     /* 459875 */ // Label 9155: @459875
     /* 459875 */ GIM_Reject,
     /* 459876 */ // Label 9151: @459876
     /* 459876 */ GIM_Try, /*On fail goto*//*Label 9158*/ GIMT_Encode4(459902), // Rule ID 1008 //
     /* 459881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 459887 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459891 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 459895 */   // (AArch64rev32:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV32v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 459895 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i8),
     /* 459900 */   GIR_RootConstrainSelectedInstOperands,
     /* 459901 */   // GIR_Coverage, 1008,
     /* 459901 */   GIR_Done,
     /* 459902 */ // Label 9158: @459902
     /* 459902 */ GIM_Reject,
     /* 459903 */ // Label 9152: @459903
     /* 459903 */ GIM_Try, /*On fail goto*//*Label 9159*/ GIMT_Encode4(459947),
     /* 459908 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 459911 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459915 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459919 */   GIM_Try, /*On fail goto*//*Label 9160*/ GIMT_Encode4(459934), // Rule ID 1011 //
     /* 459924 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459927 */     // (AArch64rev32:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV32v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 459927 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 459932 */     GIR_RootConstrainSelectedInstOperands,
     /* 459933 */     // GIR_Coverage, 1011,
     /* 459933 */     GIR_Done,
     /* 459934 */   // Label 9160: @459934
     /* 459934 */   GIM_Try, /*On fail goto*//*Label 9161*/ GIMT_Encode4(459946), // Rule ID 5035 //
     /* 459939 */     // (AArch64rev32:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (REV32v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 459939 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v8i16),
     /* 459944 */     GIR_RootConstrainSelectedInstOperands,
     /* 459945 */     // GIR_Coverage, 5035,
     /* 459945 */     GIR_Done,
     /* 459946 */   // Label 9161: @459946
     /* 459946 */   GIM_Reject,
     /* 459947 */ // Label 9159: @459947
     /* 459947 */ GIM_Reject,
     /* 459948 */ // Label 9153: @459948
     /* 459948 */ GIM_Try, /*On fail goto*//*Label 9162*/ GIMT_Encode4(459974), // Rule ID 1009 //
     /* 459953 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 459956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 459959 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459963 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 459967 */   // (AArch64rev32:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV32v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 459967 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV32v16i8),
     /* 459972 */   GIR_RootConstrainSelectedInstOperands,
     /* 459973 */   // GIR_Coverage, 1009,
     /* 459973 */   GIR_Done,
     /* 459974 */ // Label 9162: @459974
     /* 459974 */ GIM_Reject,
     /* 459975 */ // Label 9154: @459975
     /* 459975 */ GIM_Reject,
     /* 459976 */ // Label 148: @459976
     /* 459976 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(12), /*)*//*default:*//*Label 9169*/ GIMT_Encode4(460249),
     /* 459987 */ /*GILLT_v2s32*//*Label 9163*/ GIMT_Encode4(460015), GIMT_Encode4(0),
     /* 459995 */ /*GILLT_v4s16*//*Label 9164*/ GIMT_Encode4(460060),
     /* 459999 */ /*GILLT_v4s32*//*Label 9165*/ GIMT_Encode4(460105),
     /* 460003 */ /*GILLT_v8s8*//*Label 9166*/ GIMT_Encode4(460150),
     /* 460007 */ /*GILLT_v8s16*//*Label 9167*/ GIMT_Encode4(460177),
     /* 460011 */ /*GILLT_v16s8*//*Label 9168*/ GIMT_Encode4(460222),
     /* 460015 */ // Label 9163: @460015
     /* 460015 */ GIM_Try, /*On fail goto*//*Label 9170*/ GIMT_Encode4(460059),
     /* 460020 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 460023 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460027 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460031 */   GIM_Try, /*On fail goto*//*Label 9171*/ GIMT_Encode4(460046), // Rule ID 1016 //
     /* 460036 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460039 */     // (AArch64rev64:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)  =>  (REV64v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 460039 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 460044 */     GIR_RootConstrainSelectedInstOperands,
     /* 460045 */     // GIR_Coverage, 1016,
     /* 460045 */     GIR_Done,
     /* 460046 */   // Label 9171: @460046
     /* 460046 */   GIM_Try, /*On fail goto*//*Label 9172*/ GIMT_Encode4(460058), // Rule ID 5037 //
     /* 460051 */     // (AArch64rev64:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)  =>  (REV64v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn)
     /* 460051 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v2i32),
     /* 460056 */     GIR_RootConstrainSelectedInstOperands,
     /* 460057 */     // GIR_Coverage, 5037,
     /* 460057 */     GIR_Done,
     /* 460058 */   // Label 9172: @460058
     /* 460058 */   GIM_Reject,
     /* 460059 */ // Label 9170: @460059
     /* 460059 */ GIM_Reject,
     /* 460060 */ // Label 9164: @460060
     /* 460060 */ GIM_Try, /*On fail goto*//*Label 9173*/ GIMT_Encode4(460104),
     /* 460065 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 460068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460072 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460076 */   GIM_Try, /*On fail goto*//*Label 9174*/ GIMT_Encode4(460091), // Rule ID 1014 //
     /* 460081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460084 */     // (AArch64rev64:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)  =>  (REV64v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 460084 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 460089 */     GIR_RootConstrainSelectedInstOperands,
     /* 460090 */     // GIR_Coverage, 1014,
     /* 460090 */     GIR_Done,
     /* 460091 */   // Label 9174: @460091
     /* 460091 */   GIM_Try, /*On fail goto*//*Label 9175*/ GIMT_Encode4(460103), // Rule ID 5034 //
     /* 460096 */     // (AArch64rev64:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)  =>  (REV64v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn)
     /* 460096 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i16),
     /* 460101 */     GIR_RootConstrainSelectedInstOperands,
     /* 460102 */     // GIR_Coverage, 5034,
     /* 460102 */     GIR_Done,
     /* 460103 */   // Label 9175: @460103
     /* 460103 */   GIM_Reject,
     /* 460104 */ // Label 9173: @460104
     /* 460104 */ GIM_Reject,
     /* 460105 */ // Label 9165: @460105
     /* 460105 */ GIM_Try, /*On fail goto*//*Label 9176*/ GIMT_Encode4(460149),
     /* 460110 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 460113 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460117 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460121 */   GIM_Try, /*On fail goto*//*Label 9177*/ GIMT_Encode4(460136), // Rule ID 1017 //
     /* 460126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460129 */     // (AArch64rev64:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)  =>  (REV64v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 460129 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 460134 */     GIR_RootConstrainSelectedInstOperands,
     /* 460135 */     // GIR_Coverage, 1017,
     /* 460135 */     GIR_Done,
     /* 460136 */   // Label 9177: @460136
     /* 460136 */   GIM_Try, /*On fail goto*//*Label 9178*/ GIMT_Encode4(460148), // Rule ID 5038 //
     /* 460141 */     // (AArch64rev64:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)  =>  (REV64v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn)
     /* 460141 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v4i32),
     /* 460146 */     GIR_RootConstrainSelectedInstOperands,
     /* 460147 */     // GIR_Coverage, 5038,
     /* 460147 */     GIR_Done,
     /* 460148 */   // Label 9178: @460148
     /* 460148 */   GIM_Reject,
     /* 460149 */ // Label 9176: @460149
     /* 460149 */ GIM_Reject,
     /* 460150 */ // Label 9166: @460150
     /* 460150 */ GIM_Try, /*On fail goto*//*Label 9179*/ GIMT_Encode4(460176), // Rule ID 1012 //
     /* 460155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460158 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 460161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460165 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460169 */   // (AArch64rev64:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)  =>  (REV64v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 460169 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i8),
     /* 460174 */   GIR_RootConstrainSelectedInstOperands,
     /* 460175 */   // GIR_Coverage, 1012,
     /* 460175 */   GIR_Done,
     /* 460176 */ // Label 9179: @460176
     /* 460176 */ GIM_Reject,
     /* 460177 */ // Label 9167: @460177
     /* 460177 */ GIM_Try, /*On fail goto*//*Label 9180*/ GIMT_Encode4(460221),
     /* 460182 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 460185 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460189 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460193 */   GIM_Try, /*On fail goto*//*Label 9181*/ GIMT_Encode4(460208), // Rule ID 1015 //
     /* 460198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460201 */     // (AArch64rev64:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)  =>  (REV64v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 460201 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 460206 */     GIR_RootConstrainSelectedInstOperands,
     /* 460207 */     // GIR_Coverage, 1015,
     /* 460207 */     GIR_Done,
     /* 460208 */   // Label 9181: @460208
     /* 460208 */   GIM_Try, /*On fail goto*//*Label 9182*/ GIMT_Encode4(460220), // Rule ID 5036 //
     /* 460213 */     // (AArch64rev64:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)  =>  (REV64v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn)
     /* 460213 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v8i16),
     /* 460218 */     GIR_RootConstrainSelectedInstOperands,
     /* 460219 */     // GIR_Coverage, 5036,
     /* 460219 */     GIR_Done,
     /* 460220 */   // Label 9182: @460220
     /* 460220 */   GIM_Reject,
     /* 460221 */ // Label 9180: @460221
     /* 460221 */ GIM_Reject,
     /* 460222 */ // Label 9168: @460222
     /* 460222 */ GIM_Try, /*On fail goto*//*Label 9183*/ GIMT_Encode4(460248), // Rule ID 1013 //
     /* 460227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 460233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460237 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460241 */   // (AArch64rev64:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)  =>  (REV64v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 460241 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::REV64v16i8),
     /* 460246 */   GIR_RootConstrainSelectedInstOperands,
     /* 460247 */   // GIR_Coverage, 1013,
     /* 460247 */   GIR_Done,
     /* 460248 */ // Label 9183: @460248
     /* 460248 */ GIM_Reject,
     /* 460249 */ // Label 9169: @460249
     /* 460249 */ GIM_Reject,
     /* 460250 */ // Label 149: @460250
     /* 460250 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 9190*/ GIMT_Encode4(460455),
     /* 460261 */ /*GILLT_s64*//*Label 9184*/ GIMT_Encode4(460293), GIMT_Encode4(0),
     /* 460269 */ /*GILLT_v2s32*//*Label 9185*/ GIMT_Encode4(460320),
     /* 460273 */ /*GILLT_v2s64*//*Label 9186*/ GIMT_Encode4(460347),
     /* 460277 */ /*GILLT_v4s16*//*Label 9187*/ GIMT_Encode4(460374),
     /* 460281 */ /*GILLT_v4s32*//*Label 9188*/ GIMT_Encode4(460401), GIMT_Encode4(0),
     /* 460289 */ /*GILLT_v8s16*//*Label 9189*/ GIMT_Encode4(460428),
     /* 460293 */ // Label 9184: @460293
     /* 460293 */ GIM_Try, /*On fail goto*//*Label 9191*/ GIMT_Encode4(460319), // Rule ID 1038 //
     /* 460298 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460301 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 460304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460308 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460312 */   // (AArch64saddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)  =>  (SADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 460312 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 460317 */   GIR_RootConstrainSelectedInstOperands,
     /* 460318 */   // GIR_Coverage, 1038,
     /* 460318 */   GIR_Done,
     /* 460319 */ // Label 9191: @460319
     /* 460319 */ GIM_Reject,
     /* 460320 */ // Label 9185: @460320
     /* 460320 */ GIM_Try, /*On fail goto*//*Label 9192*/ GIMT_Encode4(460346), // Rule ID 1034 //
     /* 460325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 460331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460335 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460339 */   // (AArch64saddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 460339 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i16_v2i32),
     /* 460344 */   GIR_RootConstrainSelectedInstOperands,
     /* 460345 */   // GIR_Coverage, 1034,
     /* 460345 */   GIR_Done,
     /* 460346 */ // Label 9192: @460346
     /* 460346 */ GIM_Reject,
     /* 460347 */ // Label 9186: @460347
     /* 460347 */ GIM_Try, /*On fail goto*//*Label 9193*/ GIMT_Encode4(460373), // Rule ID 1040 //
     /* 460352 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460355 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 460358 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460362 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460366 */   // (AArch64saddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 460366 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv4i32_v2i64),
     /* 460371 */   GIR_RootConstrainSelectedInstOperands,
     /* 460372 */   // GIR_Coverage, 1040,
     /* 460372 */   GIR_Done,
     /* 460373 */ // Label 9193: @460373
     /* 460373 */ GIM_Reject,
     /* 460374 */ // Label 9187: @460374
     /* 460374 */ GIM_Try, /*On fail goto*//*Label 9194*/ GIMT_Encode4(460400), // Rule ID 1030 //
     /* 460379 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 460385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460389 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460393 */   // (AArch64saddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)  =>  (SADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 460393 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i8_v4i16),
     /* 460398 */   GIR_RootConstrainSelectedInstOperands,
     /* 460399 */   // GIR_Coverage, 1030,
     /* 460399 */   GIR_Done,
     /* 460400 */ // Label 9194: @460400
     /* 460400 */ GIM_Reject,
     /* 460401 */ // Label 9188: @460401
     /* 460401 */ GIM_Try, /*On fail goto*//*Label 9195*/ GIMT_Encode4(460427), // Rule ID 1036 //
     /* 460406 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460409 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 460412 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460416 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460420 */   // (AArch64saddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 460420 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv8i16_v4i32),
     /* 460425 */   GIR_RootConstrainSelectedInstOperands,
     /* 460426 */   // GIR_Coverage, 1036,
     /* 460426 */   GIR_Done,
     /* 460427 */ // Label 9195: @460427
     /* 460427 */ GIM_Reject,
     /* 460428 */ // Label 9189: @460428
     /* 460428 */ GIM_Try, /*On fail goto*//*Label 9196*/ GIMT_Encode4(460454), // Rule ID 1032 //
     /* 460433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 460436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 460439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460443 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460447 */   // (AArch64saddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)  =>  (SADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 460447 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv16i8_v8i16),
     /* 460452 */   GIR_RootConstrainSelectedInstOperands,
     /* 460453 */   // GIR_Coverage, 1032,
     /* 460453 */   GIR_Done,
     /* 460454 */ // Label 9196: @460454
     /* 460454 */ GIM_Reject,
     /* 460455 */ // Label 9190: @460455
     /* 460455 */ GIM_Reject,
     /* 460456 */ // Label 150: @460456
     /* 460456 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 9199*/ GIMT_Encode4(460854),
     /* 460467 */ /*GILLT_v2s64*//*Label 9197*/ GIMT_Encode4(460479), GIMT_Encode4(0),
     /* 460475 */ /*GILLT_v4s32*//*Label 9198*/ GIMT_Encode4(460617),
     /* 460479 */ // Label 9197: @460479
     /* 460479 */ GIM_Try, /*On fail goto*//*Label 9200*/ GIMT_Encode4(460538), // Rule ID 6495 //
     /* 460484 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 460487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460491 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460495 */   // (AArch64saddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (SADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 460495 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 460498 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i32v),
     /* 460502 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460507 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460511 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460513 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 460516 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460518 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 460521 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460524 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 460527 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460532 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460537 */   // GIR_Coverage, 6495,
     /* 460537 */   GIR_EraseRootFromParent_Done,
     /* 460538 */ // Label 9200: @460538
     /* 460538 */ GIM_Try, /*On fail goto*//*Label 9201*/ GIMT_Encode4(460616), // Rule ID 6617 //
     /* 460543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 460546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460550 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460554 */   // (AArch64saddlv:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (SADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 460554 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 460557 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::SADDLPv2i32_v1i64),
     /* 460561 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460566 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460570 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 460572 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 460575 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 460579 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460584 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460586 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 460589 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460591 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460594 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 460597 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 460600 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460605 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460610 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460615 */   // GIR_Coverage, 6617,
     /* 460615 */   GIR_EraseRootFromParent_Done,
     /* 460616 */ // Label 9201: @460616
     /* 460616 */ GIM_Reject,
     /* 460617 */ // Label 9198: @460617
     /* 460617 */ GIM_Try, /*On fail goto*//*Label 9202*/ GIMT_Encode4(460676), // Rule ID 6491 //
     /* 460622 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 460625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460629 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460633 */   // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
     /* 460633 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 460636 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i8v),
     /* 460640 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460645 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460649 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460651 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 460654 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460656 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 460659 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460662 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 460665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460670 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 460675 */   // GIR_Coverage, 6491,
     /* 460675 */   GIR_EraseRootFromParent_Done,
     /* 460676 */ // Label 9202: @460676
     /* 460676 */ GIM_Try, /*On fail goto*//*Label 9203*/ GIMT_Encode4(460735), // Rule ID 6492 //
     /* 460681 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 460684 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460688 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460692 */   // (AArch64saddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
     /* 460692 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 460695 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv4i16v),
     /* 460699 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460704 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460708 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460710 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 460713 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460715 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 460718 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460721 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 460724 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460729 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 460734 */   // GIR_Coverage, 6492,
     /* 460734 */   GIR_EraseRootFromParent_Done,
     /* 460735 */ // Label 9203: @460735
     /* 460735 */ GIM_Try, /*On fail goto*//*Label 9204*/ GIMT_Encode4(460794), // Rule ID 6493 //
     /* 460740 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 460743 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460747 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460751 */   // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
     /* 460751 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 460754 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv16i8v),
     /* 460758 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460763 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460767 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 460772 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460774 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 460777 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460780 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 460783 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460788 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 460793 */   // GIR_Coverage, 6493,
     /* 460793 */   GIR_EraseRootFromParent_Done,
     /* 460794 */ // Label 9204: @460794
     /* 460794 */ GIM_Try, /*On fail goto*//*Label 9205*/ GIMT_Encode4(460853), // Rule ID 6494 //
     /* 460799 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 460802 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460806 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460810 */   // (AArch64saddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (SADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
     /* 460810 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 460813 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::SADDLVv8i16v),
     /* 460817 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 460822 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 460826 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 460828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 460831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 460833 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 460836 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 460839 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 460842 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460847 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 460852 */   // GIR_Coverage, 6494,
     /* 460852 */   GIR_EraseRootFromParent_Done,
     /* 460853 */ // Label 9205: @460853
     /* 460853 */ GIM_Reject,
     /* 460854 */ // Label 9199: @460854
     /* 460854 */ GIM_Reject,
     /* 460855 */ // Label 151: @460855
     /* 460855 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 9210*/ GIMT_Encode4(461224),
     /* 460866 */ /*GILLT_v2s32*//*Label 9206*/ GIMT_Encode4(460926), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 460878 */ /*GILLT_v4s32*//*Label 9207*/ GIMT_Encode4(461046), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 460910 */ /*GILLT_nxv2s64*//*Label 9208*/ GIMT_Encode4(461166), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 460922 */ /*GILLT_nxv4s32*//*Label 9209*/ GIMT_Encode4(461195),
     /* 460926 */ // Label 9206: @460926
     /* 460926 */ GIM_Try, /*On fail goto*//*Label 9211*/ GIMT_Encode4(461045),
     /* 460931 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 460934 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 460937 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 460940 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460944 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460948 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 460952 */   GIM_Try, /*On fail goto*//*Label 9212*/ GIMT_Encode4(461025), // Rule ID 26 //
     /* 460957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 460960 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 460964 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 460968 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 460972 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 460976 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 460980 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 460984 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 460988 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 460993 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 460997 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 461001 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 461005 */     // MIs[3] Operand 1
     /* 461005 */     // No operand predicates
     /* 461005 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 461007 */     // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 461007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev8i8),
     /* 461010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 461012 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 461014 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 461016 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 461020 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 461023 */     GIR_RootConstrainSelectedInstOperands,
     /* 461024 */     // GIR_Coverage, 26,
     /* 461024 */     GIR_EraseRootFromParent_Done,
     /* 461025 */   // Label 9212: @461025
     /* 461025 */   GIM_Try, /*On fail goto*//*Label 9213*/ GIMT_Encode4(461044), // Rule ID 22 //
     /* 461030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 461033 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461037 */     // (AArch64sdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 461037 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv8i8),
     /* 461042 */     GIR_RootConstrainSelectedInstOperands,
     /* 461043 */     // GIR_Coverage, 22,
     /* 461043 */     GIR_Done,
     /* 461044 */   // Label 9213: @461044
     /* 461044 */   GIM_Reject,
     /* 461045 */ // Label 9211: @461045
     /* 461045 */ GIM_Reject,
     /* 461046 */ // Label 9207: @461046
     /* 461046 */ GIM_Try, /*On fail goto*//*Label 9214*/ GIMT_Encode4(461165),
     /* 461051 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461054 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 461057 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 461060 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461064 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461068 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461072 */   GIM_Try, /*On fail goto*//*Label 9215*/ GIMT_Encode4(461145), // Rule ID 27 //
     /* 461077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 461080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 461084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 461088 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461092 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 461096 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 461100 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461104 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 461108 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461113 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 461117 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 461121 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 461125 */     // MIs[3] Operand 1
     /* 461125 */     // No operand predicates
     /* 461125 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 461127 */     // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (SDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 461127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SDOTlanev16i8),
     /* 461130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 461132 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 461134 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 461136 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 461140 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 461143 */     GIR_RootConstrainSelectedInstOperands,
     /* 461144 */     // GIR_Coverage, 27,
     /* 461144 */     GIR_EraseRootFromParent_Done,
     /* 461145 */   // Label 9215: @461145
     /* 461145 */   GIM_Try, /*On fail goto*//*Label 9216*/ GIMT_Encode4(461164), // Rule ID 23 //
     /* 461150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 461153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461157 */     // (AArch64sdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (SDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 461157 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOTv16i8),
     /* 461162 */     GIR_RootConstrainSelectedInstOperands,
     /* 461163 */     // GIR_Coverage, 23,
     /* 461163 */     GIR_Done,
     /* 461164 */   // Label 9216: @461164
     /* 461164 */   GIM_Reject,
     /* 461165 */ // Label 9214: @461165
     /* 461165 */ GIM_Reject,
     /* 461166 */ // Label 9208: @461166
     /* 461166 */ GIM_Try, /*On fail goto*//*Label 9217*/ GIMT_Encode4(461194), // Rule ID 3051 //
     /* 461171 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 461174 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 461177 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 461180 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 461183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461187 */   // (AArch64sdot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (SDOT_ZZZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 461187 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_HtoD),
     /* 461192 */   GIR_RootConstrainSelectedInstOperands,
     /* 461193 */   // GIR_Coverage, 3051,
     /* 461193 */   GIR_Done,
     /* 461194 */ // Label 9217: @461194
     /* 461194 */ GIM_Reject,
     /* 461195 */ // Label 9209: @461195
     /* 461195 */ GIM_Try, /*On fail goto*//*Label 9218*/ GIMT_Encode4(461223), // Rule ID 3050 //
     /* 461200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 461203 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 461206 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 461209 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 461212 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461216 */   // (AArch64sdot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (SDOT_ZZZ_BtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 461216 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SDOT_ZZZ_BtoS),
     /* 461221 */   GIR_RootConstrainSelectedInstOperands,
     /* 461222 */   // GIR_Coverage, 3050,
     /* 461222 */   GIR_Done,
     /* 461223 */ // Label 9218: @461223
     /* 461223 */ GIM_Reject,
     /* 461224 */ // Label 9210: @461224
     /* 461224 */ GIM_Reject,
     /* 461225 */ // Label 152: @461225
     /* 461225 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 9222*/ GIMT_Encode4(461341),
     /* 461236 */ /*GILLT_s16*//*Label 9219*/ GIMT_Encode4(461248),
     /* 461240 */ /*GILLT_s32*//*Label 9220*/ GIMT_Encode4(461279),
     /* 461244 */ /*GILLT_s64*//*Label 9221*/ GIMT_Encode4(461310),
     /* 461248 */ // Label 9219: @461248
     /* 461248 */ GIM_Try, /*On fail goto*//*Label 9223*/ GIMT_Encode4(461278), // Rule ID 1700 //
     /* 461253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 461256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 461259 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 461263 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 461267 */   // (AArch64sitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (SCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 461267 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i16),
     /* 461272 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 461276 */   GIR_RootConstrainSelectedInstOperands,
     /* 461277 */   // GIR_Coverage, 1700,
     /* 461277 */   GIR_Done,
     /* 461278 */ // Label 9223: @461278
     /* 461278 */ GIM_Reject,
     /* 461279 */ // Label 9220: @461279
     /* 461279 */ GIM_Try, /*On fail goto*//*Label 9224*/ GIMT_Encode4(461309), // Rule ID 1699 //
     /* 461284 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 461287 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 461290 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 461294 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 461298 */   // (AArch64sitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (SCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 461298 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i32),
     /* 461303 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 461307 */   GIR_RootConstrainSelectedInstOperands,
     /* 461308 */   // GIR_Coverage, 1699,
     /* 461308 */   GIR_Done,
     /* 461309 */ // Label 9224: @461309
     /* 461309 */ GIM_Reject,
     /* 461310 */ // Label 9221: @461310
     /* 461310 */ GIM_Try, /*On fail goto*//*Label 9225*/ GIMT_Encode4(461340), // Rule ID 1698 //
     /* 461315 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 461318 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 461321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461325 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461329 */   // (AArch64sitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (SCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 461329 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SCVTFv1i64),
     /* 461334 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 461338 */   GIR_RootConstrainSelectedInstOperands,
     /* 461339 */   // GIR_Coverage, 1698,
     /* 461339 */   GIR_Done,
     /* 461340 */ // Label 9225: @461340
     /* 461340 */ GIM_Reject,
     /* 461341 */ // Label 9222: @461341
     /* 461341 */ GIM_Reject,
     /* 461342 */ // Label 153: @461342
     /* 461342 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 9238*/ GIMT_Encode4(461909),
     /* 461353 */ /*GILLT_s64*//*Label 9226*/ GIMT_Encode4(461437), GIMT_Encode4(0),
     /* 461361 */ /*GILLT_v2s32*//*Label 9227*/ GIMT_Encode4(461479),
     /* 461365 */ /*GILLT_v2s64*//*Label 9228*/ GIMT_Encode4(461521),
     /* 461369 */ /*GILLT_v4s16*//*Label 9229*/ GIMT_Encode4(461563),
     /* 461373 */ /*GILLT_v4s32*//*Label 9230*/ GIMT_Encode4(461605),
     /* 461377 */ /*GILLT_v8s8*//*Label 9231*/ GIMT_Encode4(461647),
     /* 461381 */ /*GILLT_v8s16*//*Label 9232*/ GIMT_Encode4(461689),
     /* 461385 */ /*GILLT_v16s8*//*Label 9233*/ GIMT_Encode4(461731), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 461405 */ /*GILLT_nxv2s64*//*Label 9234*/ GIMT_Encode4(461773), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 461417 */ /*GILLT_nxv4s32*//*Label 9235*/ GIMT_Encode4(461807), GIMT_Encode4(0),
     /* 461425 */ /*GILLT_nxv8s16*//*Label 9236*/ GIMT_Encode4(461841), GIMT_Encode4(0),
     /* 461433 */ /*GILLT_nxv16s8*//*Label 9237*/ GIMT_Encode4(461875),
     /* 461437 */ // Label 9226: @461437
     /* 461437 */ GIM_Try, /*On fail goto*//*Label 9239*/ GIMT_Encode4(461478), // Rule ID 2139 //
     /* 461442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461445 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 461448 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 461451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461455 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461459 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461463 */   // MIs[0] imm
     /* 461463 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461466 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 461471 */   // (AArch64vsli:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461471 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLId),
     /* 461476 */   GIR_RootConstrainSelectedInstOperands,
     /* 461477 */   // GIR_Coverage, 2139,
     /* 461477 */   GIR_Done,
     /* 461478 */ // Label 9239: @461478
     /* 461478 */ GIM_Reject,
     /* 461479 */ // Label 9227: @461479
     /* 461479 */ GIM_Try, /*On fail goto*//*Label 9240*/ GIMT_Encode4(461520), // Rule ID 2198 //
     /* 461484 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461487 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 461490 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 461493 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461497 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461501 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461505 */   // MIs[0] imm
     /* 461505 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461508 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 461513 */   // (AArch64vsli:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461513 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv2i32_shift),
     /* 461518 */   GIR_RootConstrainSelectedInstOperands,
     /* 461519 */   // GIR_Coverage, 2198,
     /* 461519 */   GIR_Done,
     /* 461520 */ // Label 9240: @461520
     /* 461520 */ GIM_Reject,
     /* 461521 */ // Label 9228: @461521
     /* 461521 */ GIM_Try, /*On fail goto*//*Label 9241*/ GIMT_Encode4(461562), // Rule ID 2200 //
     /* 461526 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461529 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 461532 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 461535 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461539 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461543 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461547 */   // MIs[0] imm
     /* 461547 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461550 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 461555 */   // (AArch64vsli:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SLIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461555 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv2i64_shift),
     /* 461560 */   GIR_RootConstrainSelectedInstOperands,
     /* 461561 */   // GIR_Coverage, 2200,
     /* 461561 */   GIR_Done,
     /* 461562 */ // Label 9241: @461562
     /* 461562 */ GIM_Reject,
     /* 461563 */ // Label 9229: @461563
     /* 461563 */ GIM_Try, /*On fail goto*//*Label 9242*/ GIMT_Encode4(461604), // Rule ID 2196 //
     /* 461568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461571 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 461574 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 461577 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461581 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461585 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461589 */   // MIs[0] imm
     /* 461589 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461592 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 461597 */   // (AArch64vsli:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461597 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv4i16_shift),
     /* 461602 */   GIR_RootConstrainSelectedInstOperands,
     /* 461603 */   // GIR_Coverage, 2196,
     /* 461603 */   GIR_Done,
     /* 461604 */ // Label 9242: @461604
     /* 461604 */ GIM_Reject,
     /* 461605 */ // Label 9230: @461605
     /* 461605 */ GIM_Try, /*On fail goto*//*Label 9243*/ GIMT_Encode4(461646), // Rule ID 2199 //
     /* 461610 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461613 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461616 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 461619 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461623 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461627 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461631 */   // MIs[0] imm
     /* 461631 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461634 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 461639 */   // (AArch64vsli:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SLIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461639 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv4i32_shift),
     /* 461644 */   GIR_RootConstrainSelectedInstOperands,
     /* 461645 */   // GIR_Coverage, 2199,
     /* 461645 */   GIR_Done,
     /* 461646 */ // Label 9243: @461646
     /* 461646 */ GIM_Reject,
     /* 461647 */ // Label 9231: @461647
     /* 461647 */ GIM_Try, /*On fail goto*//*Label 9244*/ GIMT_Encode4(461688), // Rule ID 2194 //
     /* 461652 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461655 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 461658 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 461661 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461665 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461669 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 461673 */   // MIs[0] imm
     /* 461673 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461676 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 461681 */   // (AArch64vsli:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461681 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv8i8_shift),
     /* 461686 */   GIR_RootConstrainSelectedInstOperands,
     /* 461687 */   // GIR_Coverage, 2194,
     /* 461687 */   GIR_Done,
     /* 461688 */ // Label 9244: @461688
     /* 461688 */ GIM_Reject,
     /* 461689 */ // Label 9232: @461689
     /* 461689 */ GIM_Try, /*On fail goto*//*Label 9245*/ GIMT_Encode4(461730), // Rule ID 2197 //
     /* 461694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461697 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 461700 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 461703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461707 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461711 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461715 */   // MIs[0] imm
     /* 461715 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461718 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 461723 */   // (AArch64vsli:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SLIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461723 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv8i16_shift),
     /* 461728 */   GIR_RootConstrainSelectedInstOperands,
     /* 461729 */   // GIR_Coverage, 2197,
     /* 461729 */   GIR_Done,
     /* 461730 */ // Label 9245: @461730
     /* 461730 */ GIM_Reject,
     /* 461731 */ // Label 9233: @461731
     /* 461731 */ GIM_Try, /*On fail goto*//*Label 9246*/ GIMT_Encode4(461772), // Rule ID 2195 //
     /* 461736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 461742 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 461745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461749 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461753 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461757 */   // MIs[0] imm
     /* 461757 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461760 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 461765 */   // (AArch64vsli:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SLIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 461765 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLIv16i8_shift),
     /* 461770 */   GIR_RootConstrainSelectedInstOperands,
     /* 461771 */   // GIR_Coverage, 2195,
     /* 461771 */   GIR_Done,
     /* 461772 */ // Label 9246: @461772
     /* 461772 */ GIM_Reject,
     /* 461773 */ // Label 9234: @461773
     /* 461773 */ GIM_Try, /*On fail goto*//*Label 9247*/ GIMT_Encode4(461806), // Rule ID 3117 //
     /* 461778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 461781 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 461784 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 461787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461791 */   // MIs[0] Op3
     /* 461791 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461794 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 461799 */   // (AArch64vsli:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$Op3)  =>  (SLI_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$Op3)
     /* 461799 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLI_ZZI_D),
     /* 461804 */   GIR_RootConstrainSelectedInstOperands,
     /* 461805 */   // GIR_Coverage, 3117,
     /* 461805 */   GIR_Done,
     /* 461806 */ // Label 9247: @461806
     /* 461806 */ GIM_Reject,
     /* 461807 */ // Label 9235: @461807
     /* 461807 */ GIM_Try, /*On fail goto*//*Label 9248*/ GIMT_Encode4(461840), // Rule ID 3116 //
     /* 461812 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 461815 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 461818 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 461821 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461825 */   // MIs[0] Op3
     /* 461825 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461828 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 461833 */   // (AArch64vsli:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op3)  =>  (SLI_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$Op3)
     /* 461833 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLI_ZZI_S),
     /* 461838 */   GIR_RootConstrainSelectedInstOperands,
     /* 461839 */   // GIR_Coverage, 3116,
     /* 461839 */   GIR_Done,
     /* 461840 */ // Label 9248: @461840
     /* 461840 */ GIM_Reject,
     /* 461841 */ // Label 9236: @461841
     /* 461841 */ GIM_Try, /*On fail goto*//*Label 9249*/ GIMT_Encode4(461874), // Rule ID 3115 //
     /* 461846 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 461849 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 461852 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 461855 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461859 */   // MIs[0] Op3
     /* 461859 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461862 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 461867 */   // (AArch64vsli:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op3)  =>  (SLI_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$Op3)
     /* 461867 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLI_ZZI_H),
     /* 461872 */   GIR_RootConstrainSelectedInstOperands,
     /* 461873 */   // GIR_Coverage, 3115,
     /* 461873 */   GIR_Done,
     /* 461874 */ // Label 9249: @461874
     /* 461874 */ GIM_Reject,
     /* 461875 */ // Label 9237: @461875
     /* 461875 */ GIM_Try, /*On fail goto*//*Label 9250*/ GIMT_Encode4(461908), // Rule ID 3114 //
     /* 461880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 461883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 461886 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 461889 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 461893 */   // MIs[0] Op3
     /* 461893 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 461896 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 461901 */   // (AArch64vsli:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op3)  =>  (SLI_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$Op3)
     /* 461901 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SLI_ZZI_B),
     /* 461906 */   GIR_RootConstrainSelectedInstOperands,
     /* 461907 */   // GIR_Coverage, 3114,
     /* 461907 */   GIR_Done,
     /* 461908 */ // Label 9250: @461908
     /* 461908 */ GIM_Reject,
     /* 461909 */ // Label 9238: @461909
     /* 461909 */ GIM_Reject,
     /* 461910 */ // Label 154: @461910
     /* 461910 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 9254*/ GIMT_Encode4(463142),
     /* 461921 */ /*GILLT_v2s64*//*Label 9251*/ GIMT_Encode4(461941), GIMT_Encode4(0),
     /* 461929 */ /*GILLT_v4s32*//*Label 9252*/ GIMT_Encode4(462502), GIMT_Encode4(0),
     /* 461937 */ /*GILLT_v8s16*//*Label 9253*/ GIMT_Encode4(463063),
     /* 461941 */ // Label 9251: @461941
     /* 461941 */ GIM_Try, /*On fail goto*//*Label 9255*/ GIMT_Encode4(462501),
     /* 461946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 461949 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 461952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461956 */   GIM_Try, /*On fail goto*//*Label 9256*/ GIMT_Encode4(462048), // Rule ID 2085 //
     /* 461961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 461964 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 461968 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 461972 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461976 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 461980 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 461984 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 461988 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 461992 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 461997 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462001 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462005 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462009 */     // MIs[3] Operand 1
     /* 462009 */     // No operand predicates
     /* 462009 */     // MIs[1] Operand 2
     /* 462009 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 462020 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462022 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 462029 */     // (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (SMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_indexed),
     /* 462032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462034 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462039 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462043 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462046 */     GIR_RootConstrainSelectedInstOperands,
     /* 462047 */     // GIR_Coverage, 2085,
     /* 462047 */     GIR_EraseRootFromParent_Done,
     /* 462048 */   // Label 9256: @462048
     /* 462048 */   GIM_Try, /*On fail goto*//*Label 9257*/ GIMT_Encode4(462140), // Rule ID 14542 //
     /* 462053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462068 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462072 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 462076 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462080 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462084 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462089 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462093 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462097 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462101 */     // MIs[3] Operand 1
     /* 462101 */     // No operand predicates
     /* 462101 */     // MIs[1] Operand 2
     /* 462101 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 462112 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462114 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 462121 */     // (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (SMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_indexed),
     /* 462124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462126 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462131 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462135 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462138 */     GIR_RootConstrainSelectedInstOperands,
     /* 462139 */     // GIR_Coverage, 14542,
     /* 462139 */     GIR_EraseRootFromParent_Done,
     /* 462140 */   // Label 9257: @462140
     /* 462140 */   GIM_Try, /*On fail goto*//*Label 9258*/ GIMT_Encode4(462226), // Rule ID 14540 //
     /* 462145 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462148 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462152 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462156 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462160 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 462168 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462172 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462176 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462181 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462185 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462189 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462193 */     // MIs[3] Operand 1
     /* 462193 */     // No operand predicates
     /* 462193 */     // MIs[1] Operand 2
     /* 462193 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 462204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462208 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462210 */     // (AArch64smull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 462213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462215 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 462217 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462221 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462224 */     GIR_RootConstrainSelectedInstOperands,
     /* 462225 */     // GIR_Coverage, 14540,
     /* 462225 */     GIR_EraseRootFromParent_Done,
     /* 462226 */   // Label 9258: @462226
     /* 462226 */   GIM_Try, /*On fail goto*//*Label 9259*/ GIMT_Encode4(462312), // Rule ID 2083 //
     /* 462231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462234 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462238 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 462242 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462246 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 462258 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462262 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462266 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462271 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462275 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462279 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462283 */     // MIs[3] Operand 1
     /* 462283 */     // No operand predicates
     /* 462283 */     // MIs[1] Operand 2
     /* 462283 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 462294 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462296 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 462299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462301 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 462303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462307 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462310 */     GIR_RootConstrainSelectedInstOperands,
     /* 462311 */     // GIR_Coverage, 2083,
     /* 462311 */     GIR_EraseRootFromParent_Done,
     /* 462312 */   // Label 9259: @462312
     /* 462312 */   GIM_Try, /*On fail goto*//*Label 9260*/ GIMT_Encode4(462351), // Rule ID 1772 //
     /* 462317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462320 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 462327 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 462334 */     // (AArch64smull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (SMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 462334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i32_v2i64),
     /* 462337 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462339 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462344 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 462349 */     GIR_RootConstrainSelectedInstOperands,
     /* 462350 */     // GIR_Coverage, 1772,
     /* 462350 */     GIR_EraseRootFromParent_Done,
     /* 462351 */   // Label 9260: @462351
     /* 462351 */   GIM_Try, /*On fail goto*//*Label 9261*/ GIMT_Encode4(462414), // Rule ID 14541 //
     /* 462356 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462359 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462363 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 462367 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462371 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 462375 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462380 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 462384 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462388 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462392 */     // MIs[2] Operand 1
     /* 462392 */     // No operand predicates
     /* 462392 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462396 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 462398 */     // (AArch64smull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462398 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 462401 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462403 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 462405 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 462409 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 462412 */     GIR_RootConstrainSelectedInstOperands,
     /* 462413 */     // GIR_Coverage, 14541,
     /* 462413 */     GIR_EraseRootFromParent_Done,
     /* 462414 */   // Label 9261: @462414
     /* 462414 */   GIM_Try, /*On fail goto*//*Label 9262*/ GIMT_Encode4(462477), // Rule ID 2084 //
     /* 462419 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462422 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462426 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 462430 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 462434 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 462438 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 462442 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462447 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 462451 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462455 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 462459 */     // MIs[2] Operand 1
     /* 462459 */     // No operand predicates
     /* 462459 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 462461 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (SMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_indexed),
     /* 462464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462466 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 462468 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 462472 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 462475 */     GIR_RootConstrainSelectedInstOperands,
     /* 462476 */     // GIR_Coverage, 2084,
     /* 462476 */     GIR_EraseRootFromParent_Done,
     /* 462477 */   // Label 9262: @462477
     /* 462477 */   GIM_Try, /*On fail goto*//*Label 9263*/ GIMT_Encode4(462500), // Rule ID 1771 //
     /* 462482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462485 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462489 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462493 */     // (AArch64smull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (SMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 462493 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv2i32_v2i64),
     /* 462498 */     GIR_RootConstrainSelectedInstOperands,
     /* 462499 */     // GIR_Coverage, 1771,
     /* 462499 */     GIR_Done,
     /* 462500 */   // Label 9263: @462500
     /* 462500 */   GIM_Reject,
     /* 462501 */ // Label 9255: @462501
     /* 462501 */ GIM_Reject,
     /* 462502 */ // Label 9252: @462502
     /* 462502 */ GIM_Try, /*On fail goto*//*Label 9264*/ GIMT_Encode4(463062),
     /* 462507 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 462510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 462513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 462517 */   GIM_Try, /*On fail goto*//*Label 9265*/ GIMT_Encode4(462609), // Rule ID 2082 //
     /* 462522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462525 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 462529 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462533 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462537 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462541 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462545 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462549 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462553 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 462558 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462562 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462566 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 462570 */     // MIs[3] Operand 1
     /* 462570 */     // No operand predicates
     /* 462570 */     // MIs[1] Operand 2
     /* 462570 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 462581 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462583 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 462590 */     // (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (SMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_indexed),
     /* 462593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462595 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462600 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462604 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462607 */     GIR_RootConstrainSelectedInstOperands,
     /* 462608 */     // GIR_Coverage, 2082,
     /* 462608 */     GIR_EraseRootFromParent_Done,
     /* 462609 */   // Label 9265: @462609
     /* 462609 */   GIM_Try, /*On fail goto*//*Label 9266*/ GIMT_Encode4(462701), // Rule ID 14539 //
     /* 462614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462625 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462629 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462633 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462637 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462641 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462645 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 462650 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462654 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462658 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 462662 */     // MIs[3] Operand 1
     /* 462662 */     // No operand predicates
     /* 462662 */     // MIs[1] Operand 2
     /* 462662 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 462673 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462675 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 462682 */     // (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (SMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_indexed),
     /* 462685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462687 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462692 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462696 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462699 */     GIR_RootConstrainSelectedInstOperands,
     /* 462700 */     // GIR_Coverage, 14539,
     /* 462700 */     GIR_EraseRootFromParent_Done,
     /* 462701 */   // Label 9266: @462701
     /* 462701 */   GIM_Try, /*On fail goto*//*Label 9267*/ GIMT_Encode4(462787), // Rule ID 14537 //
     /* 462706 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462709 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462713 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462717 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462721 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462725 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462729 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462733 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462737 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 462742 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462746 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462750 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 462754 */     // MIs[3] Operand 1
     /* 462754 */     // No operand predicates
     /* 462754 */     // MIs[1] Operand 2
     /* 462754 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 462765 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462769 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462771 */     // (AArch64smull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 462774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462776 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 462778 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462782 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462785 */     GIR_RootConstrainSelectedInstOperands,
     /* 462786 */     // GIR_Coverage, 14537,
     /* 462786 */     GIR_EraseRootFromParent_Done,
     /* 462787 */   // Label 9267: @462787
     /* 462787 */   GIM_Try, /*On fail goto*//*Label 9268*/ GIMT_Encode4(462873), // Rule ID 2080 //
     /* 462792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462795 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462799 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 462803 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 462807 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462811 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 462815 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462819 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462823 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 462827 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 462832 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 462836 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462840 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 462844 */     // MIs[3] Operand 1
     /* 462844 */     // No operand predicates
     /* 462844 */     // MIs[1] Operand 2
     /* 462844 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 462855 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 462857 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462857 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 462860 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462862 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 462864 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 462868 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 462871 */     GIR_RootConstrainSelectedInstOperands,
     /* 462872 */     // GIR_Coverage, 2080,
     /* 462872 */     GIR_EraseRootFromParent_Done,
     /* 462873 */   // Label 9268: @462873
     /* 462873 */   GIM_Try, /*On fail goto*//*Label 9269*/ GIMT_Encode4(462912), // Rule ID 1770 //
     /* 462878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462881 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 462888 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 462895 */     // (AArch64smull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (SMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 462895 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i16_v4i32),
     /* 462898 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462900 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 462905 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 462910 */     GIR_RootConstrainSelectedInstOperands,
     /* 462911 */     // GIR_Coverage, 1770,
     /* 462911 */     GIR_EraseRootFromParent_Done,
     /* 462912 */   // Label 9269: @462912
     /* 462912 */   GIM_Try, /*On fail goto*//*Label 9270*/ GIMT_Encode4(462975), // Rule ID 14538 //
     /* 462917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 462924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462928 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462932 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 462936 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 462941 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 462945 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 462949 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 462953 */     // MIs[2] Operand 1
     /* 462953 */     // No operand predicates
     /* 462953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462957 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 462959 */     // (AArch64smull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 462959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 462962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 462964 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 462966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 462970 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 462973 */     GIR_RootConstrainSelectedInstOperands,
     /* 462974 */     // GIR_Coverage, 14538,
     /* 462974 */     GIR_EraseRootFromParent_Done,
     /* 462975 */   // Label 9270: @462975
     /* 462975 */   GIM_Try, /*On fail goto*//*Label 9271*/ GIMT_Encode4(463038), // Rule ID 2081 //
     /* 462980 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 462983 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 462987 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 462991 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 462995 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 462999 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 463003 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 463008 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 463012 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 463016 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 463020 */     // MIs[2] Operand 1
     /* 463020 */     // No operand predicates
     /* 463020 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 463022 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (SMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 463022 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_indexed),
     /* 463025 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 463027 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 463029 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 463033 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 463036 */     GIR_RootConstrainSelectedInstOperands,
     /* 463037 */     // GIR_Coverage, 2081,
     /* 463037 */     GIR_EraseRootFromParent_Done,
     /* 463038 */   // Label 9271: @463038
     /* 463038 */   GIM_Try, /*On fail goto*//*Label 9272*/ GIMT_Encode4(463061), // Rule ID 1769 //
     /* 463043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463046 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463054 */     // (AArch64smull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (SMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 463054 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv4i16_v4i32),
     /* 463059 */     GIR_RootConstrainSelectedInstOperands,
     /* 463060 */     // GIR_Coverage, 1769,
     /* 463060 */     GIR_Done,
     /* 463061 */   // Label 9272: @463061
     /* 463061 */   GIM_Reject,
     /* 463062 */ // Label 9264: @463062
     /* 463062 */ GIM_Reject,
     /* 463063 */ // Label 9253: @463063
     /* 463063 */ GIM_Try, /*On fail goto*//*Label 9273*/ GIMT_Encode4(463141),
     /* 463068 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 463071 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 463074 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463078 */   GIM_Try, /*On fail goto*//*Label 9274*/ GIMT_Encode4(463117), // Rule ID 1768 //
     /* 463083 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463086 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 463093 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 463100 */     // (AArch64smull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (SMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 463100 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SMULLv16i8_v8i16),
     /* 463103 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 463105 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 463110 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 463115 */     GIR_RootConstrainSelectedInstOperands,
     /* 463116 */     // GIR_Coverage, 1768,
     /* 463116 */     GIR_EraseRootFromParent_Done,
     /* 463117 */   // Label 9274: @463117
     /* 463117 */   GIM_Try, /*On fail goto*//*Label 9275*/ GIMT_Encode4(463140), // Rule ID 1767 //
     /* 463122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463125 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463129 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463133 */     // (AArch64smull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (SMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 463133 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SMULLv8i8_v8i16),
     /* 463138 */     GIR_RootConstrainSelectedInstOperands,
     /* 463139 */     // GIR_Coverage, 1767,
     /* 463139 */     GIR_Done,
     /* 463140 */   // Label 9275: @463140
     /* 463140 */   GIM_Reject,
     /* 463141 */ // Label 9273: @463141
     /* 463141 */ GIM_Reject,
     /* 463142 */ // Label 9254: @463142
     /* 463142 */ GIM_Reject,
     /* 463143 */ // Label 155: @463143
     /* 463143 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 9285*/ GIMT_Encode4(463530),
     /* 463154 */ /*GILLT_s32*//*Label 9276*/ GIMT_Encode4(463194),
     /* 463158 */ /*GILLT_s64*//*Label 9277*/ GIMT_Encode4(463229), GIMT_Encode4(0),
     /* 463166 */ /*GILLT_v2s32*//*Label 9278*/ GIMT_Encode4(463285),
     /* 463170 */ /*GILLT_v2s64*//*Label 9279*/ GIMT_Encode4(463320),
     /* 463174 */ /*GILLT_v4s16*//*Label 9280*/ GIMT_Encode4(463355),
     /* 463178 */ /*GILLT_v4s32*//*Label 9281*/ GIMT_Encode4(463390),
     /* 463182 */ /*GILLT_v8s8*//*Label 9282*/ GIMT_Encode4(463425),
     /* 463186 */ /*GILLT_v8s16*//*Label 9283*/ GIMT_Encode4(463460),
     /* 463190 */ /*GILLT_v16s8*//*Label 9284*/ GIMT_Encode4(463495),
     /* 463194 */ // Label 9276: @463194
     /* 463194 */ GIM_Try, /*On fail goto*//*Label 9286*/ GIMT_Encode4(463228), // Rule ID 2142 //
     /* 463199 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463202 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 463205 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 463209 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 463213 */   // MIs[0] imm
     /* 463213 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463216 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 463221 */   // (AArch64sqshlui:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SQSHLUs:{ *:[i32] } FPR32:{ *:[i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463221 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUs),
     /* 463226 */   GIR_RootConstrainSelectedInstOperands,
     /* 463227 */   // GIR_Coverage, 2142,
     /* 463227 */   GIR_Done,
     /* 463228 */ // Label 9286: @463228
     /* 463228 */ GIM_Reject,
     /* 463229 */ // Label 9277: @463229
     /* 463229 */ GIM_Try, /*On fail goto*//*Label 9287*/ GIMT_Encode4(463284),
     /* 463234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 463237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463241 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463245 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463248 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 463253 */   GIM_Try, /*On fail goto*//*Label 9288*/ GIMT_Encode4(463268), // Rule ID 2143 //
     /* 463258 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463261 */     // (AArch64sqshlui:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SQSHLUd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463261 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUd),
     /* 463266 */     GIR_RootConstrainSelectedInstOperands,
     /* 463267 */     // GIR_Coverage, 2143,
     /* 463267 */     GIR_Done,
     /* 463268 */   // Label 9288: @463268
     /* 463268 */   GIM_Try, /*On fail goto*//*Label 9289*/ GIMT_Encode4(463283), // Rule ID 2610 //
     /* 463273 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463276 */     // (AArch64sqshlui:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SQSHLUd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)
     /* 463276 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUd),
     /* 463281 */     GIR_RootConstrainSelectedInstOperands,
     /* 463282 */     // GIR_Coverage, 2610,
     /* 463282 */     GIR_Done,
     /* 463283 */   // Label 9289: @463283
     /* 463283 */   GIM_Reject,
     /* 463284 */ // Label 9287: @463284
     /* 463284 */ GIM_Reject,
     /* 463285 */ // Label 9278: @463285
     /* 463285 */ GIM_Try, /*On fail goto*//*Label 9290*/ GIMT_Encode4(463319), // Rule ID 2211 //
     /* 463290 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463293 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 463296 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463300 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463304 */   // MIs[0] imm
     /* 463304 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463307 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 463312 */   // (AArch64sqshlui:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SQSHLUv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463312 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv2i32_shift),
     /* 463317 */   GIR_RootConstrainSelectedInstOperands,
     /* 463318 */   // GIR_Coverage, 2211,
     /* 463318 */   GIR_Done,
     /* 463319 */ // Label 9290: @463319
     /* 463319 */ GIM_Reject,
     /* 463320 */ // Label 9279: @463320
     /* 463320 */ GIM_Try, /*On fail goto*//*Label 9291*/ GIMT_Encode4(463354), // Rule ID 2213 //
     /* 463325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 463331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463335 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463339 */   // MIs[0] imm
     /* 463339 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463342 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL64),
     /* 463347 */   // (AArch64sqshlui:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL64>>:$imm)  =>  (SQSHLUv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463347 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv2i64_shift),
     /* 463352 */   GIR_RootConstrainSelectedInstOperands,
     /* 463353 */   // GIR_Coverage, 2213,
     /* 463353 */   GIR_Done,
     /* 463354 */ // Label 9291: @463354
     /* 463354 */ GIM_Reject,
     /* 463355 */ // Label 9280: @463355
     /* 463355 */ GIM_Try, /*On fail goto*//*Label 9292*/ GIMT_Encode4(463389), // Rule ID 2209 //
     /* 463360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 463366 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463370 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463374 */   // MIs[0] imm
     /* 463374 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463377 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 463382 */   // (AArch64sqshlui:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SQSHLUv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463382 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv4i16_shift),
     /* 463387 */   GIR_RootConstrainSelectedInstOperands,
     /* 463388 */   // GIR_Coverage, 2209,
     /* 463388 */   GIR_Done,
     /* 463389 */ // Label 9292: @463389
     /* 463389 */ GIM_Reject,
     /* 463390 */ // Label 9281: @463390
     /* 463390 */ GIM_Try, /*On fail goto*//*Label 9293*/ GIMT_Encode4(463424), // Rule ID 2212 //
     /* 463395 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463398 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 463401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463409 */   // MIs[0] imm
     /* 463409 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463412 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL32),
     /* 463417 */   // (AArch64sqshlui:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL32>>:$imm)  =>  (SQSHLUv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463417 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv4i32_shift),
     /* 463422 */   GIR_RootConstrainSelectedInstOperands,
     /* 463423 */   // GIR_Coverage, 2212,
     /* 463423 */   GIR_Done,
     /* 463424 */ // Label 9293: @463424
     /* 463424 */ GIM_Reject,
     /* 463425 */ // Label 9282: @463425
     /* 463425 */ GIM_Try, /*On fail goto*//*Label 9294*/ GIMT_Encode4(463459), // Rule ID 2207 //
     /* 463430 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463433 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 463436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463440 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463444 */   // MIs[0] imm
     /* 463444 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463447 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 463452 */   // (AArch64sqshlui:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SQSHLUv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463452 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv8i8_shift),
     /* 463457 */   GIR_RootConstrainSelectedInstOperands,
     /* 463458 */   // GIR_Coverage, 2207,
     /* 463458 */   GIR_Done,
     /* 463459 */ // Label 9294: @463459
     /* 463459 */ GIM_Reject,
     /* 463460 */ // Label 9283: @463460
     /* 463460 */ GIM_Try, /*On fail goto*//*Label 9295*/ GIMT_Encode4(463494), // Rule ID 2210 //
     /* 463465 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463468 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 463471 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463475 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463479 */   // MIs[0] imm
     /* 463479 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463482 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL16),
     /* 463487 */   // (AArch64sqshlui:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL16>>:$imm)  =>  (SQSHLUv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463487 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv8i16_shift),
     /* 463492 */   GIR_RootConstrainSelectedInstOperands,
     /* 463493 */   // GIR_Coverage, 2210,
     /* 463493 */   GIR_Done,
     /* 463494 */ // Label 9295: @463494
     /* 463494 */ GIM_Reject,
     /* 463495 */ // Label 9284: @463495
     /* 463495 */ GIM_Try, /*On fail goto*//*Label 9296*/ GIMT_Encode4(463529), // Rule ID 2208 //
     /* 463500 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463503 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 463506 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463510 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463514 */   // MIs[0] imm
     /* 463514 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 463517 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftL8),
     /* 463522 */   // (AArch64sqshlui:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftL8>>:$imm)  =>  (SQSHLUv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463522 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SQSHLUv16i8_shift),
     /* 463527 */   GIR_RootConstrainSelectedInstOperands,
     /* 463528 */   // GIR_Coverage, 2208,
     /* 463528 */   GIR_Done,
     /* 463529 */ // Label 9296: @463529
     /* 463529 */ GIM_Reject,
     /* 463530 */ // Label 9285: @463530
     /* 463530 */ GIM_Reject,
     /* 463531 */ // Label 156: @463531
     /* 463531 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(24), /*)*//*default:*//*Label 9309*/ GIMT_Encode4(464098),
     /* 463542 */ /*GILLT_s64*//*Label 9297*/ GIMT_Encode4(463626), GIMT_Encode4(0),
     /* 463550 */ /*GILLT_v2s32*//*Label 9298*/ GIMT_Encode4(463668),
     /* 463554 */ /*GILLT_v2s64*//*Label 9299*/ GIMT_Encode4(463710),
     /* 463558 */ /*GILLT_v4s16*//*Label 9300*/ GIMT_Encode4(463752),
     /* 463562 */ /*GILLT_v4s32*//*Label 9301*/ GIMT_Encode4(463794),
     /* 463566 */ /*GILLT_v8s8*//*Label 9302*/ GIMT_Encode4(463836),
     /* 463570 */ /*GILLT_v8s16*//*Label 9303*/ GIMT_Encode4(463878),
     /* 463574 */ /*GILLT_v16s8*//*Label 9304*/ GIMT_Encode4(463920), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 463594 */ /*GILLT_nxv2s64*//*Label 9305*/ GIMT_Encode4(463962), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 463606 */ /*GILLT_nxv4s32*//*Label 9306*/ GIMT_Encode4(463996), GIMT_Encode4(0),
     /* 463614 */ /*GILLT_nxv8s16*//*Label 9307*/ GIMT_Encode4(464030), GIMT_Encode4(0),
     /* 463622 */ /*GILLT_nxv16s8*//*Label 9308*/ GIMT_Encode4(464064),
     /* 463626 */ // Label 9297: @463626
     /* 463626 */ GIM_Try, /*On fail goto*//*Label 9310*/ GIMT_Encode4(463667), // Rule ID 2148 //
     /* 463631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463634 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 463637 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 463640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463644 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463648 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463652 */   // MIs[0] imm
     /* 463652 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463655 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 463660 */   // (AArch64vsri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRId:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rd, FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463660 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRId),
     /* 463665 */   GIR_RootConstrainSelectedInstOperands,
     /* 463666 */   // GIR_Coverage, 2148,
     /* 463666 */   GIR_Done,
     /* 463667 */ // Label 9310: @463667
     /* 463667 */ GIM_Reject,
     /* 463668 */ // Label 9298: @463668
     /* 463668 */ GIM_Try, /*On fail goto*//*Label 9311*/ GIMT_Encode4(463709), // Rule ID 2231 //
     /* 463673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463676 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 463679 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 463682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463686 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463690 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463694 */   // MIs[0] imm
     /* 463694 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463697 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 463702 */   // (AArch64vsri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463702 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv2i32_shift),
     /* 463707 */   GIR_RootConstrainSelectedInstOperands,
     /* 463708 */   // GIR_Coverage, 2231,
     /* 463708 */   GIR_Done,
     /* 463709 */ // Label 9311: @463709
     /* 463709 */ GIM_Reject,
     /* 463710 */ // Label 9299: @463710
     /* 463710 */ GIM_Try, /*On fail goto*//*Label 9312*/ GIMT_Encode4(463751), // Rule ID 2233 //
     /* 463715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 463721 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 463724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463728 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463732 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463736 */   // MIs[0] imm
     /* 463736 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463739 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 463744 */   // (AArch64vsri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRIv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rd, V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463744 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv2i64_shift),
     /* 463749 */   GIR_RootConstrainSelectedInstOperands,
     /* 463750 */   // GIR_Coverage, 2233,
     /* 463750 */   GIR_Done,
     /* 463751 */ // Label 9312: @463751
     /* 463751 */ GIM_Reject,
     /* 463752 */ // Label 9300: @463752
     /* 463752 */ GIM_Try, /*On fail goto*//*Label 9313*/ GIMT_Encode4(463793), // Rule ID 2229 //
     /* 463757 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463760 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 463763 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 463766 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463770 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463774 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463778 */   // MIs[0] imm
     /* 463778 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463781 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 463786 */   // (AArch64vsri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rd, V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463786 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv4i16_shift),
     /* 463791 */   GIR_RootConstrainSelectedInstOperands,
     /* 463792 */   // GIR_Coverage, 2229,
     /* 463792 */   GIR_Done,
     /* 463793 */ // Label 9313: @463793
     /* 463793 */ GIM_Reject,
     /* 463794 */ // Label 9301: @463794
     /* 463794 */ GIM_Try, /*On fail goto*//*Label 9314*/ GIMT_Encode4(463835), // Rule ID 2232 //
     /* 463799 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463802 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 463805 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 463808 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463812 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463816 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463820 */   // MIs[0] imm
     /* 463820 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463823 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 463828 */   // (AArch64vsri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRIv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463828 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv4i32_shift),
     /* 463833 */   GIR_RootConstrainSelectedInstOperands,
     /* 463834 */   // GIR_Coverage, 2232,
     /* 463834 */   GIR_Done,
     /* 463835 */ // Label 9314: @463835
     /* 463835 */ GIM_Reject,
     /* 463836 */ // Label 9302: @463836
     /* 463836 */ GIM_Try, /*On fail goto*//*Label 9315*/ GIMT_Encode4(463877), // Rule ID 2227 //
     /* 463841 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463844 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 463847 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 463850 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463854 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463858 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 463862 */   // MIs[0] imm
     /* 463862 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463865 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 463870 */   // (AArch64vsri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rd, V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463870 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv8i8_shift),
     /* 463875 */   GIR_RootConstrainSelectedInstOperands,
     /* 463876 */   // GIR_Coverage, 2227,
     /* 463876 */   GIR_Done,
     /* 463877 */ // Label 9315: @463877
     /* 463877 */ GIM_Reject,
     /* 463878 */ // Label 9303: @463878
     /* 463878 */ GIM_Try, /*On fail goto*//*Label 9316*/ GIMT_Encode4(463919), // Rule ID 2230 //
     /* 463883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463886 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 463889 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 463892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463896 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463900 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463904 */   // MIs[0] imm
     /* 463904 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463907 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 463912 */   // (AArch64vsri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRIv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rd, V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463912 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv8i16_shift),
     /* 463917 */   GIR_RootConstrainSelectedInstOperands,
     /* 463918 */   // GIR_Coverage, 2230,
     /* 463918 */   GIR_Done,
     /* 463919 */ // Label 9316: @463919
     /* 463919 */ GIM_Reject,
     /* 463920 */ // Label 9304: @463920
     /* 463920 */ GIM_Try, /*On fail goto*//*Label 9317*/ GIMT_Encode4(463961), // Rule ID 2228 //
     /* 463925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 463928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 463931 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 463934 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463938 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463942 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 463946 */   // MIs[0] imm
     /* 463946 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463949 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 463954 */   // (AArch64vsri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRIv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rd, V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 463954 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRIv16i8_shift),
     /* 463959 */   GIR_RootConstrainSelectedInstOperands,
     /* 463960 */   // GIR_Coverage, 2228,
     /* 463960 */   GIR_Done,
     /* 463961 */ // Label 9317: @463961
     /* 463961 */ GIM_Reject,
     /* 463962 */ // Label 9305: @463962
     /* 463962 */ GIM_Try, /*On fail goto*//*Label 9318*/ GIMT_Encode4(463995), // Rule ID 3121 //
     /* 463967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 463970 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 463973 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 463976 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 463980 */   // MIs[0] Op3
     /* 463980 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 463983 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 463988 */   // (AArch64vsri:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)  =>  (SRI_ZZI_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$Op3)
     /* 463988 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRI_ZZI_D),
     /* 463993 */   GIR_RootConstrainSelectedInstOperands,
     /* 463994 */   // GIR_Coverage, 3121,
     /* 463994 */   GIR_Done,
     /* 463995 */ // Label 9318: @463995
     /* 463995 */ GIM_Reject,
     /* 463996 */ // Label 9306: @463996
     /* 463996 */ GIM_Try, /*On fail goto*//*Label 9319*/ GIMT_Encode4(464029), // Rule ID 3120 //
     /* 464001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 464004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 464007 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 464010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464014 */   // MIs[0] Op3
     /* 464014 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 464017 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 464022 */   // (AArch64vsri:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)  =>  (SRI_ZZI_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$Op3)
     /* 464022 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRI_ZZI_S),
     /* 464027 */   GIR_RootConstrainSelectedInstOperands,
     /* 464028 */   // GIR_Coverage, 3120,
     /* 464028 */   GIR_Done,
     /* 464029 */ // Label 9319: @464029
     /* 464029 */ GIM_Reject,
     /* 464030 */ // Label 9307: @464030
     /* 464030 */ GIM_Try, /*On fail goto*//*Label 9320*/ GIMT_Encode4(464063), // Rule ID 3119 //
     /* 464035 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 464038 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 464041 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 464044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464048 */   // MIs[0] Op3
     /* 464048 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 464051 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 464056 */   // (AArch64vsri:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)  =>  (SRI_ZZI_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$Op3)
     /* 464056 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRI_ZZI_H),
     /* 464061 */   GIR_RootConstrainSelectedInstOperands,
     /* 464062 */   // GIR_Coverage, 3119,
     /* 464062 */   GIR_Done,
     /* 464063 */ // Label 9320: @464063
     /* 464063 */ GIM_Reject,
     /* 464064 */ // Label 9308: @464064
     /* 464064 */ GIM_Try, /*On fail goto*//*Label 9321*/ GIMT_Encode4(464097), // Rule ID 3118 //
     /* 464069 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE2_or_SME),
     /* 464072 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 464075 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 464078 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464082 */   // MIs[0] Op3
     /* 464082 */   GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 464085 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 464090 */   // (AArch64vsri:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)  =>  (SRI_ZZI_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$Op3)
     /* 464090 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRI_ZZI_B),
     /* 464095 */   GIR_RootConstrainSelectedInstOperands,
     /* 464096 */   // GIR_Coverage, 3118,
     /* 464096 */   GIR_Done,
     /* 464097 */ // Label 9321: @464097
     /* 464097 */ GIM_Reject,
     /* 464098 */ // Label 9309: @464098
     /* 464098 */ GIM_Reject,
     /* 464099 */ // Label 157: @464099
     /* 464099 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 9330*/ GIMT_Encode4(464447),
     /* 464110 */ /*GILLT_s64*//*Label 9322*/ GIMT_Encode4(464146), GIMT_Encode4(0),
     /* 464118 */ /*GILLT_v2s32*//*Label 9323*/ GIMT_Encode4(464202),
     /* 464122 */ /*GILLT_v2s64*//*Label 9324*/ GIMT_Encode4(464237),
     /* 464126 */ /*GILLT_v4s16*//*Label 9325*/ GIMT_Encode4(464272),
     /* 464130 */ /*GILLT_v4s32*//*Label 9326*/ GIMT_Encode4(464307),
     /* 464134 */ /*GILLT_v8s8*//*Label 9327*/ GIMT_Encode4(464342),
     /* 464138 */ /*GILLT_v8s16*//*Label 9328*/ GIMT_Encode4(464377),
     /* 464142 */ /*GILLT_v16s8*//*Label 9329*/ GIMT_Encode4(464412),
     /* 464146 */ // Label 9322: @464146
     /* 464146 */ GIM_Try, /*On fail goto*//*Label 9331*/ GIMT_Encode4(464201),
     /* 464151 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 464154 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464158 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464162 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464165 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 464170 */   GIM_Try, /*On fail goto*//*Label 9332*/ GIMT_Encode4(464185), // Rule ID 2149 //
     /* 464175 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464178 */     // (AArch64srshri:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464178 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRd),
     /* 464183 */     GIR_RootConstrainSelectedInstOperands,
     /* 464184 */     // GIR_Coverage, 2149,
     /* 464184 */     GIR_Done,
     /* 464185 */   // Label 9332: @464185
     /* 464185 */   GIM_Try, /*On fail goto*//*Label 9333*/ GIMT_Encode4(464200), // Rule ID 2608 //
     /* 464190 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464193 */     // (AArch64srshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 464193 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRd),
     /* 464198 */     GIR_RootConstrainSelectedInstOperands,
     /* 464199 */     // GIR_Coverage, 2608,
     /* 464199 */     GIR_Done,
     /* 464200 */   // Label 9333: @464200
     /* 464200 */   GIM_Reject,
     /* 464201 */ // Label 9331: @464201
     /* 464201 */ GIM_Reject,
     /* 464202 */ // Label 9323: @464202
     /* 464202 */ GIM_Try, /*On fail goto*//*Label 9334*/ GIMT_Encode4(464236), // Rule ID 2238 //
     /* 464207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464210 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 464213 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464217 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464221 */   // MIs[0] imm
     /* 464221 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464224 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 464229 */   // (AArch64srshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464229 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv2i32_shift),
     /* 464234 */   GIR_RootConstrainSelectedInstOperands,
     /* 464235 */   // GIR_Coverage, 2238,
     /* 464235 */   GIR_Done,
     /* 464236 */ // Label 9334: @464236
     /* 464236 */ GIM_Reject,
     /* 464237 */ // Label 9324: @464237
     /* 464237 */ GIM_Try, /*On fail goto*//*Label 9335*/ GIMT_Encode4(464271), // Rule ID 2240 //
     /* 464242 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464245 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 464248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464252 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464256 */   // MIs[0] imm
     /* 464256 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464259 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 464264 */   // (AArch64srshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SRSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464264 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv2i64_shift),
     /* 464269 */   GIR_RootConstrainSelectedInstOperands,
     /* 464270 */   // GIR_Coverage, 2240,
     /* 464270 */   GIR_Done,
     /* 464271 */ // Label 9335: @464271
     /* 464271 */ GIM_Reject,
     /* 464272 */ // Label 9325: @464272
     /* 464272 */ GIM_Try, /*On fail goto*//*Label 9336*/ GIMT_Encode4(464306), // Rule ID 2236 //
     /* 464277 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464280 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 464283 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464287 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464291 */   // MIs[0] imm
     /* 464291 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464294 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 464299 */   // (AArch64srshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464299 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv4i16_shift),
     /* 464304 */   GIR_RootConstrainSelectedInstOperands,
     /* 464305 */   // GIR_Coverage, 2236,
     /* 464305 */   GIR_Done,
     /* 464306 */ // Label 9336: @464306
     /* 464306 */ GIM_Reject,
     /* 464307 */ // Label 9326: @464307
     /* 464307 */ GIM_Try, /*On fail goto*//*Label 9337*/ GIMT_Encode4(464341), // Rule ID 2239 //
     /* 464312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 464318 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464322 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464326 */   // MIs[0] imm
     /* 464326 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464329 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 464334 */   // (AArch64srshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SRSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464334 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv4i32_shift),
     /* 464339 */   GIR_RootConstrainSelectedInstOperands,
     /* 464340 */   // GIR_Coverage, 2239,
     /* 464340 */   GIR_Done,
     /* 464341 */ // Label 9337: @464341
     /* 464341 */ GIM_Reject,
     /* 464342 */ // Label 9327: @464342
     /* 464342 */ GIM_Try, /*On fail goto*//*Label 9338*/ GIMT_Encode4(464376), // Rule ID 2234 //
     /* 464347 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464350 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 464353 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464357 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464361 */   // MIs[0] imm
     /* 464361 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464364 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 464369 */   // (AArch64srshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464369 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv8i8_shift),
     /* 464374 */   GIR_RootConstrainSelectedInstOperands,
     /* 464375 */   // GIR_Coverage, 2234,
     /* 464375 */   GIR_Done,
     /* 464376 */ // Label 9338: @464376
     /* 464376 */ GIM_Reject,
     /* 464377 */ // Label 9328: @464377
     /* 464377 */ GIM_Try, /*On fail goto*//*Label 9339*/ GIMT_Encode4(464411), // Rule ID 2237 //
     /* 464382 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464385 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 464388 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464392 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464396 */   // MIs[0] imm
     /* 464396 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464399 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 464404 */   // (AArch64srshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SRSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464404 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv8i16_shift),
     /* 464409 */   GIR_RootConstrainSelectedInstOperands,
     /* 464410 */   // GIR_Coverage, 2237,
     /* 464410 */   GIR_Done,
     /* 464411 */ // Label 9339: @464411
     /* 464411 */ GIM_Reject,
     /* 464412 */ // Label 9329: @464412
     /* 464412 */ GIM_Try, /*On fail goto*//*Label 9340*/ GIMT_Encode4(464446), // Rule ID 2235 //
     /* 464417 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 464423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464431 */   // MIs[0] imm
     /* 464431 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 464434 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 464439 */   // (AArch64srshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SRSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 464439 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SRSHRv16i8_shift),
     /* 464444 */   GIR_RootConstrainSelectedInstOperands,
     /* 464445 */   // GIR_Coverage, 2235,
     /* 464445 */   GIR_Done,
     /* 464446 */ // Label 9340: @464446
     /* 464446 */ GIM_Reject,
     /* 464447 */ // Label 9330: @464447
     /* 464447 */ GIM_Reject,
     /* 464448 */ // Label 158: @464448
     /* 464448 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9359*/ GIMT_Encode4(465227),
     /* 464459 */ /*GILLT_v2s32*//*Label 9341*/ GIMT_Encode4(464535),
     /* 464463 */ /*GILLT_v2s64*//*Label 9342*/ GIMT_Encode4(464590),
     /* 464467 */ /*GILLT_v4s16*//*Label 9343*/ GIMT_Encode4(464645),
     /* 464471 */ /*GILLT_v4s32*//*Label 9344*/ GIMT_Encode4(464700),
     /* 464475 */ /*GILLT_v8s8*//*Label 9345*/ GIMT_Encode4(464755),
     /* 464479 */ /*GILLT_v8s16*//*Label 9346*/ GIMT_Encode4(464789),
     /* 464483 */ /*GILLT_v16s8*//*Label 9347*/ GIMT_Encode4(464844), GIMT_Encode4(0),
     /* 464491 */ /*GILLT_nxv2s1*//*Label 9348*/ GIMT_Encode4(464878),
     /* 464495 */ /*GILLT_nxv2s16*//*Label 9349*/ GIMT_Encode4(464904),
     /* 464499 */ /*GILLT_nxv2s32*//*Label 9350*/ GIMT_Encode4(464930),
     /* 464503 */ /*GILLT_nxv2s64*//*Label 9351*/ GIMT_Encode4(464956),
     /* 464507 */ /*GILLT_nxv4s1*//*Label 9352*/ GIMT_Encode4(465003),
     /* 464511 */ /*GILLT_nxv4s16*//*Label 9353*/ GIMT_Encode4(465029),
     /* 464515 */ /*GILLT_nxv4s32*//*Label 9354*/ GIMT_Encode4(465055),
     /* 464519 */ /*GILLT_nxv8s1*//*Label 9355*/ GIMT_Encode4(465102),
     /* 464523 */ /*GILLT_nxv8s16*//*Label 9356*/ GIMT_Encode4(465128),
     /* 464527 */ /*GILLT_nxv16s1*//*Label 9357*/ GIMT_Encode4(465175),
     /* 464531 */ /*GILLT_nxv16s8*//*Label 9358*/ GIMT_Encode4(465201),
     /* 464535 */ // Label 9341: @464535
     /* 464535 */ GIM_Try, /*On fail goto*//*Label 9360*/ GIMT_Encode4(464589),
     /* 464540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 464543 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 464546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464550 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464554 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464558 */   GIM_Try, /*On fail goto*//*Label 9361*/ GIMT_Encode4(464573), // Rule ID 1905 //
     /* 464563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464566 */     // (AArch64trn1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (TRN1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 464566 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
     /* 464571 */     GIR_RootConstrainSelectedInstOperands,
     /* 464572 */     // GIR_Coverage, 1905,
     /* 464572 */     GIR_Done,
     /* 464573 */   // Label 9361: @464573
     /* 464573 */   GIM_Try, /*On fail goto*//*Label 9362*/ GIMT_Encode4(464588), // Rule ID 2534 //
     /* 464578 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464581 */     // (AArch64trn1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (TRN1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 464581 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i32),
     /* 464586 */     GIR_RootConstrainSelectedInstOperands,
     /* 464587 */     // GIR_Coverage, 2534,
     /* 464587 */     GIR_Done,
     /* 464588 */   // Label 9362: @464588
     /* 464588 */   GIM_Reject,
     /* 464589 */ // Label 9360: @464589
     /* 464589 */ GIM_Reject,
     /* 464590 */ // Label 9342: @464590
     /* 464590 */ GIM_Try, /*On fail goto*//*Label 9363*/ GIMT_Encode4(464644),
     /* 464595 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 464598 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 464601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464605 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464609 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464613 */   GIM_Try, /*On fail goto*//*Label 9364*/ GIMT_Encode4(464628), // Rule ID 1907 //
     /* 464618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464621 */     // (AArch64trn1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (TRN1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 464621 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
     /* 464626 */     GIR_RootConstrainSelectedInstOperands,
     /* 464627 */     // GIR_Coverage, 1907,
     /* 464627 */     GIR_Done,
     /* 464628 */   // Label 9364: @464628
     /* 464628 */   GIM_Try, /*On fail goto*//*Label 9365*/ GIMT_Encode4(464643), // Rule ID 2536 //
     /* 464633 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464636 */     // (AArch64trn1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (TRN1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 464636 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v2i64),
     /* 464641 */     GIR_RootConstrainSelectedInstOperands,
     /* 464642 */     // GIR_Coverage, 2536,
     /* 464642 */     GIR_Done,
     /* 464643 */   // Label 9365: @464643
     /* 464643 */   GIM_Reject,
     /* 464644 */ // Label 9363: @464644
     /* 464644 */ GIM_Reject,
     /* 464645 */ // Label 9343: @464645
     /* 464645 */ GIM_Try, /*On fail goto*//*Label 9366*/ GIMT_Encode4(464699),
     /* 464650 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 464653 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 464656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464660 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464664 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464668 */   GIM_Try, /*On fail goto*//*Label 9367*/ GIMT_Encode4(464683), // Rule ID 1903 //
     /* 464673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464676 */     // (AArch64trn1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (TRN1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 464676 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
     /* 464681 */     GIR_RootConstrainSelectedInstOperands,
     /* 464682 */     // GIR_Coverage, 1903,
     /* 464682 */     GIR_Done,
     /* 464683 */   // Label 9367: @464683
     /* 464683 */   GIM_Try, /*On fail goto*//*Label 9368*/ GIMT_Encode4(464698), // Rule ID 2532 //
     /* 464688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464691 */     // (AArch64trn1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (TRN1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 464691 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i16),
     /* 464696 */     GIR_RootConstrainSelectedInstOperands,
     /* 464697 */     // GIR_Coverage, 2532,
     /* 464697 */     GIR_Done,
     /* 464698 */   // Label 9368: @464698
     /* 464698 */   GIM_Reject,
     /* 464699 */ // Label 9366: @464699
     /* 464699 */ GIM_Reject,
     /* 464700 */ // Label 9344: @464700
     /* 464700 */ GIM_Try, /*On fail goto*//*Label 9369*/ GIMT_Encode4(464754),
     /* 464705 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 464708 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 464711 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464715 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464719 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464723 */   GIM_Try, /*On fail goto*//*Label 9370*/ GIMT_Encode4(464738), // Rule ID 1906 //
     /* 464728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464731 */     // (AArch64trn1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (TRN1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 464731 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
     /* 464736 */     GIR_RootConstrainSelectedInstOperands,
     /* 464737 */     // GIR_Coverage, 1906,
     /* 464737 */     GIR_Done,
     /* 464738 */   // Label 9370: @464738
     /* 464738 */   GIM_Try, /*On fail goto*//*Label 9371*/ GIMT_Encode4(464753), // Rule ID 2535 //
     /* 464743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464746 */     // (AArch64trn1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (TRN1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 464746 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v4i32),
     /* 464751 */     GIR_RootConstrainSelectedInstOperands,
     /* 464752 */     // GIR_Coverage, 2535,
     /* 464752 */     GIR_Done,
     /* 464753 */   // Label 9371: @464753
     /* 464753 */   GIM_Reject,
     /* 464754 */ // Label 9369: @464754
     /* 464754 */ GIM_Reject,
     /* 464755 */ // Label 9345: @464755
     /* 464755 */ GIM_Try, /*On fail goto*//*Label 9372*/ GIMT_Encode4(464788), // Rule ID 1901 //
     /* 464760 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464763 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 464766 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 464769 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464773 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464777 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 464781 */   // (AArch64trn1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (TRN1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 464781 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i8),
     /* 464786 */   GIR_RootConstrainSelectedInstOperands,
     /* 464787 */   // GIR_Coverage, 1901,
     /* 464787 */   GIR_Done,
     /* 464788 */ // Label 9372: @464788
     /* 464788 */ GIM_Reject,
     /* 464789 */ // Label 9346: @464789
     /* 464789 */ GIM_Try, /*On fail goto*//*Label 9373*/ GIMT_Encode4(464843),
     /* 464794 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 464797 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 464800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464804 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464808 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464812 */   GIM_Try, /*On fail goto*//*Label 9374*/ GIMT_Encode4(464827), // Rule ID 1904 //
     /* 464817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464820 */     // (AArch64trn1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (TRN1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 464820 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
     /* 464825 */     GIR_RootConstrainSelectedInstOperands,
     /* 464826 */     // GIR_Coverage, 1904,
     /* 464826 */     GIR_Done,
     /* 464827 */   // Label 9374: @464827
     /* 464827 */   GIM_Try, /*On fail goto*//*Label 9375*/ GIMT_Encode4(464842), // Rule ID 2533 //
     /* 464832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464835 */     // (AArch64trn1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (TRN1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 464835 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v8i16),
     /* 464840 */     GIR_RootConstrainSelectedInstOperands,
     /* 464841 */     // GIR_Coverage, 2533,
     /* 464841 */     GIR_Done,
     /* 464842 */   // Label 9375: @464842
     /* 464842 */   GIM_Reject,
     /* 464843 */ // Label 9373: @464843
     /* 464843 */ GIM_Reject,
     /* 464844 */ // Label 9347: @464844
     /* 464844 */ GIM_Try, /*On fail goto*//*Label 9376*/ GIMT_Encode4(464877), // Rule ID 1902 //
     /* 464849 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 464852 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 464855 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 464858 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464862 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464866 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 464870 */   // (AArch64trn1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (TRN1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 464870 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1v16i8),
     /* 464875 */   GIR_RootConstrainSelectedInstOperands,
     /* 464876 */   // GIR_Coverage, 1902,
     /* 464876 */   GIR_Done,
     /* 464877 */ // Label 9376: @464877
     /* 464877 */ GIM_Reject,
     /* 464878 */ // Label 9348: @464878
     /* 464878 */ GIM_Try, /*On fail goto*//*Label 9377*/ GIMT_Encode4(464903), // Rule ID 9699 //
     /* 464883 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 464886 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 464889 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 464892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 464896 */   // (AArch64trn1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (TRN1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 464896 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_D),
     /* 464901 */   GIR_RootConstrainSelectedInstOperands,
     /* 464902 */   // GIR_Coverage, 9699,
     /* 464902 */   GIR_Done,
     /* 464903 */ // Label 9377: @464903
     /* 464903 */ GIM_Reject,
     /* 464904 */ // Label 9349: @464904
     /* 464904 */ GIM_Try, /*On fail goto*//*Label 9378*/ GIMT_Encode4(464929), // Rule ID 9675 //
     /* 464909 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 464912 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 464915 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 464918 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464922 */   // (AArch64trn1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 464922 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 464927 */   GIR_RootConstrainSelectedInstOperands,
     /* 464928 */   // GIR_Coverage, 9675,
     /* 464928 */   GIR_Done,
     /* 464929 */ // Label 9378: @464929
     /* 464929 */ GIM_Reject,
     /* 464930 */ // Label 9350: @464930
     /* 464930 */ GIM_Try, /*On fail goto*//*Label 9379*/ GIMT_Encode4(464955), // Rule ID 9676 //
     /* 464935 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 464938 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 464941 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 464944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464948 */   // (AArch64trn1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 464948 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 464953 */   GIR_RootConstrainSelectedInstOperands,
     /* 464954 */   // GIR_Coverage, 9676,
     /* 464954 */   GIR_Done,
     /* 464955 */ // Label 9379: @464955
     /* 464955 */ GIM_Reject,
     /* 464956 */ // Label 9351: @464956
     /* 464956 */ GIM_Try, /*On fail goto*//*Label 9380*/ GIMT_Encode4(465002),
     /* 464961 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 464964 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 464967 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 464971 */   GIM_Try, /*On fail goto*//*Label 9381*/ GIMT_Encode4(464986), // Rule ID 9671 //
     /* 464976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 464979 */     // (AArch64trn1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 464979 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 464984 */     GIR_RootConstrainSelectedInstOperands,
     /* 464985 */     // GIR_Coverage, 9671,
     /* 464985 */     GIR_Done,
     /* 464986 */   // Label 9381: @464986
     /* 464986 */   GIM_Try, /*On fail goto*//*Label 9382*/ GIMT_Encode4(465001), // Rule ID 9677 //
     /* 464991 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 464994 */     // (AArch64trn1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 464994 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_D),
     /* 464999 */     GIR_RootConstrainSelectedInstOperands,
     /* 465000 */     // GIR_Coverage, 9677,
     /* 465000 */     GIR_Done,
     /* 465001 */   // Label 9382: @465001
     /* 465001 */   GIM_Reject,
     /* 465002 */ // Label 9380: @465002
     /* 465002 */ GIM_Reject,
     /* 465003 */ // Label 9352: @465003
     /* 465003 */ GIM_Try, /*On fail goto*//*Label 9383*/ GIMT_Encode4(465028), // Rule ID 9698 //
     /* 465008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 465014 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 465017 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465021 */   // (AArch64trn1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (TRN1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 465021 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_S),
     /* 465026 */   GIR_RootConstrainSelectedInstOperands,
     /* 465027 */   // GIR_Coverage, 9698,
     /* 465027 */   GIR_Done,
     /* 465028 */ // Label 9383: @465028
     /* 465028 */ GIM_Reject,
     /* 465029 */ // Label 9353: @465029
     /* 465029 */ GIM_Try, /*On fail goto*//*Label 9384*/ GIMT_Encode4(465054), // Rule ID 9673 //
     /* 465034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465037 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 465040 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 465043 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465047 */   // (AArch64trn1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 465047 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 465052 */   GIR_RootConstrainSelectedInstOperands,
     /* 465053 */   // GIR_Coverage, 9673,
     /* 465053 */   GIR_Done,
     /* 465054 */ // Label 9384: @465054
     /* 465054 */ GIM_Reject,
     /* 465055 */ // Label 9354: @465055
     /* 465055 */ GIM_Try, /*On fail goto*//*Label 9385*/ GIMT_Encode4(465101),
     /* 465060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 465063 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 465066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465070 */   GIM_Try, /*On fail goto*//*Label 9386*/ GIMT_Encode4(465085), // Rule ID 9670 //
     /* 465075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465078 */     // (AArch64trn1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 465078 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 465083 */     GIR_RootConstrainSelectedInstOperands,
     /* 465084 */     // GIR_Coverage, 9670,
     /* 465084 */     GIR_Done,
     /* 465085 */   // Label 9386: @465085
     /* 465085 */   GIM_Try, /*On fail goto*//*Label 9387*/ GIMT_Encode4(465100), // Rule ID 9674 //
     /* 465090 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465093 */     // (AArch64trn1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 465093 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_S),
     /* 465098 */     GIR_RootConstrainSelectedInstOperands,
     /* 465099 */     // GIR_Coverage, 9674,
     /* 465099 */     GIR_Done,
     /* 465100 */   // Label 9387: @465100
     /* 465100 */   GIM_Reject,
     /* 465101 */ // Label 9385: @465101
     /* 465101 */ GIM_Reject,
     /* 465102 */ // Label 9355: @465102
     /* 465102 */ GIM_Try, /*On fail goto*//*Label 9388*/ GIMT_Encode4(465127), // Rule ID 9697 //
     /* 465107 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465110 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 465113 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 465116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465120 */   // (AArch64trn1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (TRN1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 465120 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_H),
     /* 465125 */   GIR_RootConstrainSelectedInstOperands,
     /* 465126 */   // GIR_Coverage, 9697,
     /* 465126 */   GIR_Done,
     /* 465127 */ // Label 9388: @465127
     /* 465127 */ GIM_Reject,
     /* 465128 */ // Label 9356: @465128
     /* 465128 */ GIM_Try, /*On fail goto*//*Label 9389*/ GIMT_Encode4(465174),
     /* 465133 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 465136 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 465139 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465143 */   GIM_Try, /*On fail goto*//*Label 9390*/ GIMT_Encode4(465158), // Rule ID 9669 //
     /* 465148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465151 */     // (AArch64trn1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 465151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
     /* 465156 */     GIR_RootConstrainSelectedInstOperands,
     /* 465157 */     // GIR_Coverage, 9669,
     /* 465157 */     GIR_Done,
     /* 465158 */   // Label 9390: @465158
     /* 465158 */   GIM_Try, /*On fail goto*//*Label 9391*/ GIMT_Encode4(465173), // Rule ID 9672 //
     /* 465163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465166 */     // (AArch64trn1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 465166 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_H),
     /* 465171 */     GIR_RootConstrainSelectedInstOperands,
     /* 465172 */     // GIR_Coverage, 9672,
     /* 465172 */     GIR_Done,
     /* 465173 */   // Label 9391: @465173
     /* 465173 */   GIM_Reject,
     /* 465174 */ // Label 9389: @465174
     /* 465174 */ GIM_Reject,
     /* 465175 */ // Label 9357: @465175
     /* 465175 */ GIM_Try, /*On fail goto*//*Label 9392*/ GIMT_Encode4(465200), // Rule ID 2448 //
     /* 465180 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465183 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 465186 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 465189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465193 */   // (AArch64trn1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 465193 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_PPP_B),
     /* 465198 */   GIR_RootConstrainSelectedInstOperands,
     /* 465199 */   // GIR_Coverage, 2448,
     /* 465199 */   GIR_Done,
     /* 465200 */ // Label 9392: @465200
     /* 465200 */ GIM_Reject,
     /* 465201 */ // Label 9358: @465201
     /* 465201 */ GIM_Try, /*On fail goto*//*Label 9393*/ GIMT_Encode4(465226), // Rule ID 9668 //
     /* 465206 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465209 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 465212 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 465215 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465219 */   // (AArch64trn1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 465219 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN1_ZZZ_B),
     /* 465224 */   GIR_RootConstrainSelectedInstOperands,
     /* 465225 */   // GIR_Coverage, 9668,
     /* 465225 */   GIR_Done,
     /* 465226 */ // Label 9393: @465226
     /* 465226 */ GIM_Reject,
     /* 465227 */ // Label 9359: @465227
     /* 465227 */ GIM_Reject,
     /* 465228 */ // Label 159: @465228
     /* 465228 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9412*/ GIMT_Encode4(466007),
     /* 465239 */ /*GILLT_v2s32*//*Label 9394*/ GIMT_Encode4(465315),
     /* 465243 */ /*GILLT_v2s64*//*Label 9395*/ GIMT_Encode4(465370),
     /* 465247 */ /*GILLT_v4s16*//*Label 9396*/ GIMT_Encode4(465425),
     /* 465251 */ /*GILLT_v4s32*//*Label 9397*/ GIMT_Encode4(465480),
     /* 465255 */ /*GILLT_v8s8*//*Label 9398*/ GIMT_Encode4(465535),
     /* 465259 */ /*GILLT_v8s16*//*Label 9399*/ GIMT_Encode4(465569),
     /* 465263 */ /*GILLT_v16s8*//*Label 9400*/ GIMT_Encode4(465624), GIMT_Encode4(0),
     /* 465271 */ /*GILLT_nxv2s1*//*Label 9401*/ GIMT_Encode4(465658),
     /* 465275 */ /*GILLT_nxv2s16*//*Label 9402*/ GIMT_Encode4(465684),
     /* 465279 */ /*GILLT_nxv2s32*//*Label 9403*/ GIMT_Encode4(465710),
     /* 465283 */ /*GILLT_nxv2s64*//*Label 9404*/ GIMT_Encode4(465736),
     /* 465287 */ /*GILLT_nxv4s1*//*Label 9405*/ GIMT_Encode4(465783),
     /* 465291 */ /*GILLT_nxv4s16*//*Label 9406*/ GIMT_Encode4(465809),
     /* 465295 */ /*GILLT_nxv4s32*//*Label 9407*/ GIMT_Encode4(465835),
     /* 465299 */ /*GILLT_nxv8s1*//*Label 9408*/ GIMT_Encode4(465882),
     /* 465303 */ /*GILLT_nxv8s16*//*Label 9409*/ GIMT_Encode4(465908),
     /* 465307 */ /*GILLT_nxv16s1*//*Label 9410*/ GIMT_Encode4(465955),
     /* 465311 */ /*GILLT_nxv16s8*//*Label 9411*/ GIMT_Encode4(465981),
     /* 465315 */ // Label 9394: @465315
     /* 465315 */ GIM_Try, /*On fail goto*//*Label 9413*/ GIMT_Encode4(465369),
     /* 465320 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 465323 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 465326 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465330 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465334 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465338 */   GIM_Try, /*On fail goto*//*Label 9414*/ GIMT_Encode4(465353), // Rule ID 1912 //
     /* 465343 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465346 */     // (AArch64trn2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (TRN2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 465346 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
     /* 465351 */     GIR_RootConstrainSelectedInstOperands,
     /* 465352 */     // GIR_Coverage, 1912,
     /* 465352 */     GIR_Done,
     /* 465353 */   // Label 9414: @465353
     /* 465353 */   GIM_Try, /*On fail goto*//*Label 9415*/ GIMT_Encode4(465368), // Rule ID 6068 //
     /* 465358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465361 */     // (AArch64trn2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (TRN2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 465361 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i32),
     /* 465366 */     GIR_RootConstrainSelectedInstOperands,
     /* 465367 */     // GIR_Coverage, 6068,
     /* 465367 */     GIR_Done,
     /* 465368 */   // Label 9415: @465368
     /* 465368 */   GIM_Reject,
     /* 465369 */ // Label 9413: @465369
     /* 465369 */ GIM_Reject,
     /* 465370 */ // Label 9395: @465370
     /* 465370 */ GIM_Try, /*On fail goto*//*Label 9416*/ GIMT_Encode4(465424),
     /* 465375 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 465378 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 465381 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465385 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465389 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465393 */   GIM_Try, /*On fail goto*//*Label 9417*/ GIMT_Encode4(465408), // Rule ID 1914 //
     /* 465398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465401 */     // (AArch64trn2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (TRN2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 465401 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
     /* 465406 */     GIR_RootConstrainSelectedInstOperands,
     /* 465407 */     // GIR_Coverage, 1914,
     /* 465407 */     GIR_Done,
     /* 465408 */   // Label 9417: @465408
     /* 465408 */   GIM_Try, /*On fail goto*//*Label 9418*/ GIMT_Encode4(465423), // Rule ID 6070 //
     /* 465413 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465416 */     // (AArch64trn2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (TRN2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 465416 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v2i64),
     /* 465421 */     GIR_RootConstrainSelectedInstOperands,
     /* 465422 */     // GIR_Coverage, 6070,
     /* 465422 */     GIR_Done,
     /* 465423 */   // Label 9418: @465423
     /* 465423 */   GIM_Reject,
     /* 465424 */ // Label 9416: @465424
     /* 465424 */ GIM_Reject,
     /* 465425 */ // Label 9396: @465425
     /* 465425 */ GIM_Try, /*On fail goto*//*Label 9419*/ GIMT_Encode4(465479),
     /* 465430 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 465433 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 465436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465440 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465444 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465448 */   GIM_Try, /*On fail goto*//*Label 9420*/ GIMT_Encode4(465463), // Rule ID 1910 //
     /* 465453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465456 */     // (AArch64trn2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (TRN2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 465456 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
     /* 465461 */     GIR_RootConstrainSelectedInstOperands,
     /* 465462 */     // GIR_Coverage, 1910,
     /* 465462 */     GIR_Done,
     /* 465463 */   // Label 9420: @465463
     /* 465463 */   GIM_Try, /*On fail goto*//*Label 9421*/ GIMT_Encode4(465478), // Rule ID 6066 //
     /* 465468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465471 */     // (AArch64trn2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (TRN2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 465471 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i16),
     /* 465476 */     GIR_RootConstrainSelectedInstOperands,
     /* 465477 */     // GIR_Coverage, 6066,
     /* 465477 */     GIR_Done,
     /* 465478 */   // Label 9421: @465478
     /* 465478 */   GIM_Reject,
     /* 465479 */ // Label 9419: @465479
     /* 465479 */ GIM_Reject,
     /* 465480 */ // Label 9397: @465480
     /* 465480 */ GIM_Try, /*On fail goto*//*Label 9422*/ GIMT_Encode4(465534),
     /* 465485 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 465488 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 465491 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465495 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465499 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465503 */   GIM_Try, /*On fail goto*//*Label 9423*/ GIMT_Encode4(465518), // Rule ID 1913 //
     /* 465508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465511 */     // (AArch64trn2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (TRN2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 465511 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
     /* 465516 */     GIR_RootConstrainSelectedInstOperands,
     /* 465517 */     // GIR_Coverage, 1913,
     /* 465517 */     GIR_Done,
     /* 465518 */   // Label 9423: @465518
     /* 465518 */   GIM_Try, /*On fail goto*//*Label 9424*/ GIMT_Encode4(465533), // Rule ID 6069 //
     /* 465523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465526 */     // (AArch64trn2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (TRN2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 465526 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v4i32),
     /* 465531 */     GIR_RootConstrainSelectedInstOperands,
     /* 465532 */     // GIR_Coverage, 6069,
     /* 465532 */     GIR_Done,
     /* 465533 */   // Label 9424: @465533
     /* 465533 */   GIM_Reject,
     /* 465534 */ // Label 9422: @465534
     /* 465534 */ GIM_Reject,
     /* 465535 */ // Label 9398: @465535
     /* 465535 */ GIM_Try, /*On fail goto*//*Label 9425*/ GIMT_Encode4(465568), // Rule ID 1908 //
     /* 465540 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 465546 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 465549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465553 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465557 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 465561 */   // (AArch64trn2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (TRN2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 465561 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i8),
     /* 465566 */   GIR_RootConstrainSelectedInstOperands,
     /* 465567 */   // GIR_Coverage, 1908,
     /* 465567 */   GIR_Done,
     /* 465568 */ // Label 9425: @465568
     /* 465568 */ GIM_Reject,
     /* 465569 */ // Label 9399: @465569
     /* 465569 */ GIM_Try, /*On fail goto*//*Label 9426*/ GIMT_Encode4(465623),
     /* 465574 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 465577 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 465580 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465584 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465588 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465592 */   GIM_Try, /*On fail goto*//*Label 9427*/ GIMT_Encode4(465607), // Rule ID 1911 //
     /* 465597 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465600 */     // (AArch64trn2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (TRN2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 465600 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
     /* 465605 */     GIR_RootConstrainSelectedInstOperands,
     /* 465606 */     // GIR_Coverage, 1911,
     /* 465606 */     GIR_Done,
     /* 465607 */   // Label 9427: @465607
     /* 465607 */   GIM_Try, /*On fail goto*//*Label 9428*/ GIMT_Encode4(465622), // Rule ID 6067 //
     /* 465612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465615 */     // (AArch64trn2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (TRN2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 465615 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v8i16),
     /* 465620 */     GIR_RootConstrainSelectedInstOperands,
     /* 465621 */     // GIR_Coverage, 6067,
     /* 465621 */     GIR_Done,
     /* 465622 */   // Label 9428: @465622
     /* 465622 */   GIM_Reject,
     /* 465623 */ // Label 9426: @465623
     /* 465623 */ GIM_Reject,
     /* 465624 */ // Label 9400: @465624
     /* 465624 */ GIM_Try, /*On fail goto*//*Label 9429*/ GIMT_Encode4(465657), // Rule ID 1909 //
     /* 465629 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 465632 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 465635 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 465638 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465642 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465646 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 465650 */   // (AArch64trn2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (TRN2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 465650 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2v16i8),
     /* 465655 */   GIR_RootConstrainSelectedInstOperands,
     /* 465656 */   // GIR_Coverage, 1909,
     /* 465656 */   GIR_Done,
     /* 465657 */ // Label 9429: @465657
     /* 465657 */ GIM_Reject,
     /* 465658 */ // Label 9401: @465658
     /* 465658 */ GIM_Try, /*On fail goto*//*Label 9430*/ GIMT_Encode4(465683), // Rule ID 9702 //
     /* 465663 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465666 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 465669 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 465672 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465676 */   // (AArch64trn2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (TRN2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 465676 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_D),
     /* 465681 */   GIR_RootConstrainSelectedInstOperands,
     /* 465682 */   // GIR_Coverage, 9702,
     /* 465682 */   GIR_Done,
     /* 465683 */ // Label 9430: @465683
     /* 465683 */ GIM_Reject,
     /* 465684 */ // Label 9402: @465684
     /* 465684 */ GIM_Try, /*On fail goto*//*Label 9431*/ GIMT_Encode4(465709), // Rule ID 9685 //
     /* 465689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465692 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 465695 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 465698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465702 */   // (AArch64trn2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 465702 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 465707 */   GIR_RootConstrainSelectedInstOperands,
     /* 465708 */   // GIR_Coverage, 9685,
     /* 465708 */   GIR_Done,
     /* 465709 */ // Label 9431: @465709
     /* 465709 */ GIM_Reject,
     /* 465710 */ // Label 9403: @465710
     /* 465710 */ GIM_Try, /*On fail goto*//*Label 9432*/ GIMT_Encode4(465735), // Rule ID 9686 //
     /* 465715 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465718 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 465721 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 465724 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465728 */   // (AArch64trn2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 465728 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 465733 */   GIR_RootConstrainSelectedInstOperands,
     /* 465734 */   // GIR_Coverage, 9686,
     /* 465734 */   GIR_Done,
     /* 465735 */ // Label 9432: @465735
     /* 465735 */ GIM_Reject,
     /* 465736 */ // Label 9404: @465736
     /* 465736 */ GIM_Try, /*On fail goto*//*Label 9433*/ GIMT_Encode4(465782),
     /* 465741 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 465744 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 465747 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465751 */   GIM_Try, /*On fail goto*//*Label 9434*/ GIMT_Encode4(465766), // Rule ID 9681 //
     /* 465756 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465759 */     // (AArch64trn2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 465759 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 465764 */     GIR_RootConstrainSelectedInstOperands,
     /* 465765 */     // GIR_Coverage, 9681,
     /* 465765 */     GIR_Done,
     /* 465766 */   // Label 9434: @465766
     /* 465766 */   GIM_Try, /*On fail goto*//*Label 9435*/ GIMT_Encode4(465781), // Rule ID 9687 //
     /* 465771 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465774 */     // (AArch64trn2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (TRN2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 465774 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_D),
     /* 465779 */     GIR_RootConstrainSelectedInstOperands,
     /* 465780 */     // GIR_Coverage, 9687,
     /* 465780 */     GIR_Done,
     /* 465781 */   // Label 9435: @465781
     /* 465781 */   GIM_Reject,
     /* 465782 */ // Label 9433: @465782
     /* 465782 */ GIM_Reject,
     /* 465783 */ // Label 9405: @465783
     /* 465783 */ GIM_Try, /*On fail goto*//*Label 9436*/ GIMT_Encode4(465808), // Rule ID 9701 //
     /* 465788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465791 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 465794 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 465797 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465801 */   // (AArch64trn2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (TRN2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 465801 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_S),
     /* 465806 */   GIR_RootConstrainSelectedInstOperands,
     /* 465807 */   // GIR_Coverage, 9701,
     /* 465807 */   GIR_Done,
     /* 465808 */ // Label 9436: @465808
     /* 465808 */ GIM_Reject,
     /* 465809 */ // Label 9406: @465809
     /* 465809 */ GIM_Try, /*On fail goto*//*Label 9437*/ GIMT_Encode4(465834), // Rule ID 9683 //
     /* 465814 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465817 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 465820 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 465823 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465827 */   // (AArch64trn2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 465827 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 465832 */   GIR_RootConstrainSelectedInstOperands,
     /* 465833 */   // GIR_Coverage, 9683,
     /* 465833 */   GIR_Done,
     /* 465834 */ // Label 9437: @465834
     /* 465834 */ GIM_Reject,
     /* 465835 */ // Label 9407: @465835
     /* 465835 */ GIM_Try, /*On fail goto*//*Label 9438*/ GIMT_Encode4(465881),
     /* 465840 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 465843 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 465846 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465850 */   GIM_Try, /*On fail goto*//*Label 9439*/ GIMT_Encode4(465865), // Rule ID 9680 //
     /* 465855 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465858 */     // (AArch64trn2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 465858 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 465863 */     GIR_RootConstrainSelectedInstOperands,
     /* 465864 */     // GIR_Coverage, 9680,
     /* 465864 */     GIR_Done,
     /* 465865 */   // Label 9439: @465865
     /* 465865 */   GIM_Try, /*On fail goto*//*Label 9440*/ GIMT_Encode4(465880), // Rule ID 9684 //
     /* 465870 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465873 */     // (AArch64trn2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (TRN2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 465873 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_S),
     /* 465878 */     GIR_RootConstrainSelectedInstOperands,
     /* 465879 */     // GIR_Coverage, 9684,
     /* 465879 */     GIR_Done,
     /* 465880 */   // Label 9440: @465880
     /* 465880 */   GIM_Reject,
     /* 465881 */ // Label 9438: @465881
     /* 465881 */ GIM_Reject,
     /* 465882 */ // Label 9408: @465882
     /* 465882 */ GIM_Try, /*On fail goto*//*Label 9441*/ GIMT_Encode4(465907), // Rule ID 9700 //
     /* 465887 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465890 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 465893 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 465896 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465900 */   // (AArch64trn2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (TRN2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 465900 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_H),
     /* 465905 */   GIR_RootConstrainSelectedInstOperands,
     /* 465906 */   // GIR_Coverage, 9700,
     /* 465906 */   GIR_Done,
     /* 465907 */ // Label 9441: @465907
     /* 465907 */ GIM_Reject,
     /* 465908 */ // Label 9409: @465908
     /* 465908 */ GIM_Try, /*On fail goto*//*Label 9442*/ GIMT_Encode4(465954),
     /* 465913 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 465916 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 465919 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465923 */   GIM_Try, /*On fail goto*//*Label 9443*/ GIMT_Encode4(465938), // Rule ID 9679 //
     /* 465928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465931 */     // (AArch64trn2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (TRN2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 465931 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
     /* 465936 */     GIR_RootConstrainSelectedInstOperands,
     /* 465937 */     // GIR_Coverage, 9679,
     /* 465937 */     GIR_Done,
     /* 465938 */   // Label 9443: @465938
     /* 465938 */   GIM_Try, /*On fail goto*//*Label 9444*/ GIMT_Encode4(465953), // Rule ID 9682 //
     /* 465943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465946 */     // (AArch64trn2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (TRN2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 465946 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_H),
     /* 465951 */     GIR_RootConstrainSelectedInstOperands,
     /* 465952 */     // GIR_Coverage, 9682,
     /* 465952 */     GIR_Done,
     /* 465953 */   // Label 9444: @465953
     /* 465953 */   GIM_Reject,
     /* 465954 */ // Label 9442: @465954
     /* 465954 */ GIM_Reject,
     /* 465955 */ // Label 9410: @465955
     /* 465955 */ GIM_Try, /*On fail goto*//*Label 9445*/ GIMT_Encode4(465980), // Rule ID 2452 //
     /* 465960 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 465966 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 465969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 465973 */   // (AArch64trn2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (TRN2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 465973 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_PPP_B),
     /* 465978 */   GIR_RootConstrainSelectedInstOperands,
     /* 465979 */   // GIR_Coverage, 2452,
     /* 465979 */   GIR_Done,
     /* 465980 */ // Label 9445: @465980
     /* 465980 */ GIM_Reject,
     /* 465981 */ // Label 9411: @465981
     /* 465981 */ GIM_Try, /*On fail goto*//*Label 9446*/ GIMT_Encode4(466006), // Rule ID 9678 //
     /* 465986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 465989 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 465992 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 465995 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 465999 */   // (AArch64trn2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (TRN2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 465999 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::TRN2_ZZZ_B),
     /* 466004 */   GIR_RootConstrainSelectedInstOperands,
     /* 466005 */   // GIR_Coverage, 9678,
     /* 466005 */   GIR_Done,
     /* 466006 */ // Label 9446: @466006
     /* 466006 */ GIM_Reject,
     /* 466007 */ // Label 9412: @466007
     /* 466007 */ GIM_Reject,
     /* 466008 */ // Label 160: @466008
     /* 466008 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(11), /*)*//*default:*//*Label 9453*/ GIMT_Encode4(466213),
     /* 466019 */ /*GILLT_s64*//*Label 9447*/ GIMT_Encode4(466051), GIMT_Encode4(0),
     /* 466027 */ /*GILLT_v2s32*//*Label 9448*/ GIMT_Encode4(466078),
     /* 466031 */ /*GILLT_v2s64*//*Label 9449*/ GIMT_Encode4(466105),
     /* 466035 */ /*GILLT_v4s16*//*Label 9450*/ GIMT_Encode4(466132),
     /* 466039 */ /*GILLT_v4s32*//*Label 9451*/ GIMT_Encode4(466159), GIMT_Encode4(0),
     /* 466047 */ /*GILLT_v8s16*//*Label 9452*/ GIMT_Encode4(466186),
     /* 466051 */ // Label 9447: @466051
     /* 466051 */ GIM_Try, /*On fail goto*//*Label 9454*/ GIMT_Encode4(466077), // Rule ID 1099 //
     /* 466056 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466059 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 466062 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466066 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466070 */   // (AArch64uaddlp_n:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)  =>  (UADDLPv2i32_v1i64:{ *:[v1i64] } V64:{ *:[v2i32] }:$Rn)
     /* 466070 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 466075 */   GIR_RootConstrainSelectedInstOperands,
     /* 466076 */   // GIR_Coverage, 1099,
     /* 466076 */   GIR_Done,
     /* 466077 */ // Label 9454: @466077
     /* 466077 */ GIM_Reject,
     /* 466078 */ // Label 9448: @466078
     /* 466078 */ GIM_Try, /*On fail goto*//*Label 9455*/ GIMT_Encode4(466104), // Rule ID 1095 //
     /* 466083 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466086 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 466089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466093 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466097 */   // (AArch64uaddlp_n:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)  =>  (UADDLPv4i16_v2i32:{ *:[v2i32] } V64:{ *:[v4i16] }:$Rn)
     /* 466097 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i16_v2i32),
     /* 466102 */   GIR_RootConstrainSelectedInstOperands,
     /* 466103 */   // GIR_Coverage, 1095,
     /* 466103 */   GIR_Done,
     /* 466104 */ // Label 9455: @466104
     /* 466104 */ GIM_Reject,
     /* 466105 */ // Label 9449: @466105
     /* 466105 */ GIM_Try, /*On fail goto*//*Label 9456*/ GIMT_Encode4(466131), // Rule ID 1101 //
     /* 466110 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466113 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 466116 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466120 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466124 */   // (AArch64uaddlp_n:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (UADDLPv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)
     /* 466124 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv4i32_v2i64),
     /* 466129 */   GIR_RootConstrainSelectedInstOperands,
     /* 466130 */   // GIR_Coverage, 1101,
     /* 466130 */   GIR_Done,
     /* 466131 */ // Label 9456: @466131
     /* 466131 */ GIM_Reject,
     /* 466132 */ // Label 9450: @466132
     /* 466132 */ GIM_Try, /*On fail goto*//*Label 9457*/ GIMT_Encode4(466158), // Rule ID 1091 //
     /* 466137 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466140 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 466143 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466147 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466151 */   // (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)  =>  (UADDLPv8i8_v4i16:{ *:[v4i16] } V64:{ *:[v8i8] }:$Rn)
     /* 466151 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i8_v4i16),
     /* 466156 */   GIR_RootConstrainSelectedInstOperands,
     /* 466157 */   // GIR_Coverage, 1091,
     /* 466157 */   GIR_Done,
     /* 466158 */ // Label 9457: @466158
     /* 466158 */ GIM_Reject,
     /* 466159 */ // Label 9451: @466159
     /* 466159 */ GIM_Try, /*On fail goto*//*Label 9458*/ GIMT_Encode4(466185), // Rule ID 1097 //
     /* 466164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 466170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466174 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466178 */   // (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (UADDLPv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)
     /* 466178 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv8i16_v4i32),
     /* 466183 */   GIR_RootConstrainSelectedInstOperands,
     /* 466184 */   // GIR_Coverage, 1097,
     /* 466184 */   GIR_Done,
     /* 466185 */ // Label 9458: @466185
     /* 466185 */ GIM_Reject,
     /* 466186 */ // Label 9452: @466186
     /* 466186 */ GIM_Try, /*On fail goto*//*Label 9459*/ GIMT_Encode4(466212), // Rule ID 1093 //
     /* 466191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 466194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 466197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466201 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466205 */   // (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)  =>  (UADDLPv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn)
     /* 466205 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv16i8_v8i16),
     /* 466210 */   GIR_RootConstrainSelectedInstOperands,
     /* 466211 */   // GIR_Coverage, 1093,
     /* 466211 */   GIR_Done,
     /* 466212 */ // Label 9459: @466212
     /* 466212 */ GIM_Reject,
     /* 466213 */ // Label 9453: @466213
     /* 466213 */ GIM_Reject,
     /* 466214 */ // Label 161: @466214
     /* 466214 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(9), /*)*//*default:*//*Label 9462*/ GIMT_Encode4(467080),
     /* 466225 */ /*GILLT_v2s64*//*Label 9460*/ GIMT_Encode4(466237), GIMT_Encode4(0),
     /* 466233 */ /*GILLT_v4s32*//*Label 9461*/ GIMT_Encode4(466531),
     /* 466237 */ // Label 9460: @466237
     /* 466237 */ GIM_Try, /*On fail goto*//*Label 9463*/ GIMT_Encode4(466319), // Rule ID 6481 //
     /* 466242 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 466245 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466249 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466253 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 466257 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 466260 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 466265 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 466269 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466274 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466276 */   // (AArch64uaddlv:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v4i32] } 750:{ *:[iPTR] }, V128:{ *:[v8i16] }:$op))  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
     /* 466276 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 466279 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 466283 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466288 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 466292 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466294 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466297 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466299 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466302 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466305 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 466308 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466313 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 466318 */   // GIR_Coverage, 6481,
     /* 466318 */   GIR_EraseRootFromParent_Done,
     /* 466319 */ // Label 9463: @466319
     /* 466319 */ GIM_Try, /*On fail goto*//*Label 9464*/ GIMT_Encode4(466393), // Rule ID 6480 //
     /* 466324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 466327 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466331 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466335 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 466339 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 466343 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466348 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466350 */   // (AArch64uaddlv:{ *:[v2i64] } (AArch64uaddlp_n:{ *:[v4i32] } V128:{ *:[v8i16] }:$op))  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$op), ssub:{ *:[i32] })
     /* 466350 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 466353 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 466357 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466362 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 466366 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466368 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466371 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466373 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466376 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466379 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 466382 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466387 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 466392 */   // GIR_Coverage, 6480,
     /* 466392 */   GIR_EraseRootFromParent_Done,
     /* 466393 */ // Label 9464: @466393
     /* 466393 */ GIM_Try, /*On fail goto*//*Label 9465*/ GIMT_Encode4(466452), // Rule ID 6490 //
     /* 466398 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 466401 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466405 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466409 */   // (AArch64uaddlv:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v2i64] } 0:{ *:[i64] }, (UADDLVv4i32v:{ *:[i64] } V128:{ *:[v4i32] }:$Rn), dsub:{ *:[i32] })
     /* 466409 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 466412 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i32v),
     /* 466416 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466421 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 466425 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466427 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466430 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466432 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466435 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466438 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 466441 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466446 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466451 */   // GIR_Coverage, 6490,
     /* 466451 */   GIR_EraseRootFromParent_Done,
     /* 466452 */ // Label 9465: @466452
     /* 466452 */ GIM_Try, /*On fail goto*//*Label 9466*/ GIMT_Encode4(466530), // Rule ID 6618 //
     /* 466457 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 466460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466464 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466468 */   // (AArch64uaddlv:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn)  =>  (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), (UADDLPv2i32_v1i64:{ *:[i64] } V64:{ *:[v2i32] }:$Rn), dsub:{ *:[i32] })
     /* 466468 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 466471 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AArch64::UADDLPv2i32_v1i64),
     /* 466475 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466480 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 466484 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 466486 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
     /* 466489 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 466493 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466498 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466500 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 466503 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466505 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466508 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 466511 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
     /* 466514 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466519 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466524 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466529 */   // GIR_Coverage, 6618,
     /* 466529 */   GIR_EraseRootFromParent_Done,
     /* 466530 */ // Label 9466: @466530
     /* 466530 */ GIM_Reject,
     /* 466531 */ // Label 9461: @466531
     /* 466531 */ GIM_Try, /*On fail goto*//*Label 9467*/ GIMT_Encode4(466613), // Rule ID 6483 //
     /* 466536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 466539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466543 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466547 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 466551 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 466554 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 466559 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 466563 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466568 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466570 */   // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v8i16] } 750:{ *:[iPTR] }, V128:{ *:[v16i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
     /* 466570 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466573 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 466577 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466582 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 466586 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466588 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466591 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466593 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466596 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466599 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 466602 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466607 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 466612 */   // GIR_Coverage, 6483,
     /* 466612 */   GIR_EraseRootFromParent_Done,
     /* 466613 */ // Label 9467: @466613
     /* 466613 */ GIM_Try, /*On fail goto*//*Label 9468*/ GIMT_Encode4(466695), // Rule ID 6485 //
     /* 466618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 466621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466625 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466629 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
     /* 466633 */   GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
     /* 466636 */   GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::aarch64_neon_uaddlp),
     /* 466641 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 466645 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466650 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466652 */   // (AArch64uaddlv:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i16] } 750:{ *:[iPTR] }, V64:{ *:[v8i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
     /* 466652 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466655 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 466659 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466664 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // op
     /* 466668 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466670 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466673 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466675 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466678 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466681 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 466684 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466689 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 466694 */   // GIR_Coverage, 6485,
     /* 466694 */   GIR_EraseRootFromParent_Done,
     /* 466695 */ // Label 9468: @466695
     /* 466695 */ GIM_Try, /*On fail goto*//*Label 9469*/ GIMT_Encode4(466769), // Rule ID 6482 //
     /* 466700 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 466703 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466707 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466711 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 466715 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 466719 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466724 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466726 */   // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v8i16] } V128:{ *:[v16i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$op), hsub:{ *:[i32] })
     /* 466726 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466729 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 466733 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466738 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 466742 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466749 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466752 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466755 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 466758 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466763 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 466768 */   // GIR_Coverage, 6482,
     /* 466768 */   GIR_EraseRootFromParent_Done,
     /* 466769 */ // Label 9469: @466769
     /* 466769 */ GIM_Try, /*On fail goto*//*Label 9470*/ GIMT_Encode4(466843), // Rule ID 6484 //
     /* 466774 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 466777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466781 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 466785 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_UADDLP),
     /* 466789 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 466793 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466798 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 466800 */   // (AArch64uaddlv:{ *:[v4i32] } (AArch64uaddlp_n:{ *:[v4i16] } V64:{ *:[v8i8] }:$op))  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$op), hsub:{ *:[i32] })
     /* 466800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 466807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466812 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // op
     /* 466816 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466818 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466821 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466823 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466826 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466829 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 466832 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466837 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 466842 */   // GIR_Coverage, 6484,
     /* 466842 */   GIR_EraseRootFromParent_Done,
     /* 466843 */ // Label 9470: @466843
     /* 466843 */ GIM_Try, /*On fail goto*//*Label 9471*/ GIMT_Encode4(466902), // Rule ID 6486 //
     /* 466848 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 466851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466855 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466859 */   // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v8i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i8v:{ *:[i16] } V64:{ *:[v8i8] }:$Rn), hsub:{ *:[i32] })
     /* 466859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i8v),
     /* 466866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466871 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 466875 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466880 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466882 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466885 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466888 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 466891 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466896 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 466901 */   // GIR_Coverage, 6486,
     /* 466901 */   GIR_EraseRootFromParent_Done,
     /* 466902 */ // Label 9471: @466902
     /* 466902 */ GIM_Try, /*On fail goto*//*Label 9472*/ GIMT_Encode4(466961), // Rule ID 6487 //
     /* 466907 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 466910 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466914 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 466918 */   // (AArch64uaddlv:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv4i16v:{ *:[i32] } V64:{ *:[v4i16] }:$Rn), ssub:{ *:[i32] })
     /* 466918 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 466921 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv4i16v),
     /* 466925 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466930 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 466934 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466939 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 466941 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 466944 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 466947 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 466950 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466955 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 466960 */   // GIR_Coverage, 6487,
     /* 466960 */   GIR_EraseRootFromParent_Done,
     /* 466961 */ // Label 9472: @466961
     /* 466961 */ GIM_Try, /*On fail goto*//*Label 9473*/ GIMT_Encode4(467020), // Rule ID 6488 //
     /* 466966 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 466969 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466973 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 466977 */   // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v16i8] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv16i8v:{ *:[i16] } V128:{ *:[v16i8] }:$Rn), hsub:{ *:[i32] })
     /* 466977 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
     /* 466980 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv16i8v),
     /* 466984 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 466989 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 466993 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 466995 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 466998 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 467000 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 467003 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 467006 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
     /* 467009 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467014 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 467019 */   // GIR_Coverage, 6488,
     /* 467019 */   GIR_EraseRootFromParent_Done,
     /* 467020 */ // Label 9473: @467020
     /* 467020 */ GIM_Try, /*On fail goto*//*Label 9474*/ GIMT_Encode4(467079), // Rule ID 6489 //
     /* 467025 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 467028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467032 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467036 */   // (AArch64uaddlv:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn)  =>  (SUBREG_TO_REG:{ *:[v4i32] } 0:{ *:[i64] }, (UADDLVv8i16v:{ *:[i32] } V128:{ *:[v8i16] }:$Rn), ssub:{ *:[i32] })
     /* 467036 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 467039 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AArch64::UADDLVv8i16v),
     /* 467043 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 467048 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Rn
     /* 467052 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 467054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
     /* 467057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 467059 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 467062 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 467065 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/18,
     /* 467068 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467073 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 467078 */   // GIR_Coverage, 6489,
     /* 467078 */   GIR_EraseRootFromParent_Done,
     /* 467079 */ // Label 9474: @467079
     /* 467079 */ GIM_Reject,
     /* 467080 */ // Label 9462: @467080
     /* 467080 */ GIM_Reject,
     /* 467081 */ // Label 162: @467081
     /* 467081 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 9479*/ GIMT_Encode4(467450),
     /* 467092 */ /*GILLT_v2s32*//*Label 9475*/ GIMT_Encode4(467152), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 467104 */ /*GILLT_v4s32*//*Label 9476*/ GIMT_Encode4(467272), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 467136 */ /*GILLT_nxv2s64*//*Label 9477*/ GIMT_Encode4(467392), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 467148 */ /*GILLT_nxv4s32*//*Label 9478*/ GIMT_Encode4(467421),
     /* 467152 */ // Label 9475: @467152
     /* 467152 */ GIM_Try, /*On fail goto*//*Label 9480*/ GIMT_Encode4(467271),
     /* 467157 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 467160 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 467163 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 467166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467170 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467174 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467178 */   GIM_Try, /*On fail goto*//*Label 9481*/ GIMT_Encode4(467251), // Rule ID 28 //
     /* 467183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 467186 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 467190 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 467194 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 467198 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467202 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467206 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467210 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467214 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467219 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467223 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467227 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467231 */     // MIs[3] Operand 1
     /* 467231 */     // No operand predicates
     /* 467231 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467233 */     // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev8i8),
     /* 467236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 467238 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 467240 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 467242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467246 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467249 */     GIR_RootConstrainSelectedInstOperands,
     /* 467250 */     // GIR_Coverage, 28,
     /* 467250 */     GIR_EraseRootFromParent_Done,
     /* 467251 */   // Label 9481: @467251
     /* 467251 */   GIM_Try, /*On fail goto*//*Label 9482*/ GIMT_Encode4(467270), // Rule ID 24 //
     /* 467256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 467259 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467263 */     // (AArch64udot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 467263 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv8i8),
     /* 467268 */     GIR_RootConstrainSelectedInstOperands,
     /* 467269 */     // GIR_Coverage, 24,
     /* 467269 */     GIR_Done,
     /* 467270 */   // Label 9482: @467270
     /* 467270 */   GIM_Reject,
     /* 467271 */ // Label 9480: @467271
     /* 467271 */ GIM_Reject,
     /* 467272 */ // Label 9476: @467272
     /* 467272 */ GIM_Try, /*On fail goto*//*Label 9483*/ GIMT_Encode4(467391),
     /* 467277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467280 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 467283 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 467286 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467290 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467294 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467298 */   GIM_Try, /*On fail goto*//*Label 9484*/ GIMT_Encode4(467371), // Rule ID 29 //
     /* 467303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 467306 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 467310 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 467314 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467318 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467322 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467326 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467330 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467334 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467339 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467343 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467347 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467351 */     // MIs[3] Operand 1
     /* 467351 */     // No operand predicates
     /* 467351 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467353 */     // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (UDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UDOTlanev16i8),
     /* 467356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 467358 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 467360 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 467362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467366 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467369 */     GIR_RootConstrainSelectedInstOperands,
     /* 467370 */     // GIR_Coverage, 29,
     /* 467370 */     GIR_EraseRootFromParent_Done,
     /* 467371 */   // Label 9484: @467371
     /* 467371 */   GIM_Try, /*On fail goto*//*Label 9485*/ GIMT_Encode4(467390), // Rule ID 25 //
     /* 467376 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
     /* 467379 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467383 */     // (AArch64udot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 467383 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOTv16i8),
     /* 467388 */     GIR_RootConstrainSelectedInstOperands,
     /* 467389 */     // GIR_Coverage, 25,
     /* 467389 */     GIR_Done,
     /* 467390 */   // Label 9485: @467390
     /* 467390 */   GIM_Reject,
     /* 467391 */ // Label 9483: @467391
     /* 467391 */ GIM_Reject,
     /* 467392 */ // Label 9477: @467392
     /* 467392 */ GIM_Try, /*On fail goto*//*Label 9486*/ GIMT_Encode4(467420), // Rule ID 8326 //
     /* 467397 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 467400 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 467403 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 467406 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv8s16,
     /* 467409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 467413 */   // (AArch64udot:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2, nxv8i16:{ *:[nxv8i16] }:$Op3)  =>  (UDOT_ZZZ_HtoD:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv8i16] }:$Op2, ?:{ *:[nxv8i16] }:$Op3)
     /* 467413 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_HtoD),
     /* 467418 */   GIR_RootConstrainSelectedInstOperands,
     /* 467419 */   // GIR_Coverage, 8326,
     /* 467419 */   GIR_Done,
     /* 467420 */ // Label 9486: @467420
     /* 467420 */ GIM_Reject,
     /* 467421 */ // Label 9478: @467421
     /* 467421 */ GIM_Try, /*On fail goto*//*Label 9487*/ GIMT_Encode4(467449), // Rule ID 8325 //
     /* 467426 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 467429 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 467432 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 467435 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 467438 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 467442 */   // (AArch64udot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (UDOT_ZZZ_BtoS:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 467442 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UDOT_ZZZ_BtoS),
     /* 467447 */   GIR_RootConstrainSelectedInstOperands,
     /* 467448 */   // GIR_Coverage, 8325,
     /* 467448 */   GIR_Done,
     /* 467449 */ // Label 9487: @467449
     /* 467449 */ GIM_Reject,
     /* 467450 */ // Label 9479: @467450
     /* 467450 */ GIM_Reject,
     /* 467451 */ // Label 163: @467451
     /* 467451 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(4), /*)*//*default:*//*Label 9491*/ GIMT_Encode4(467567),
     /* 467462 */ /*GILLT_s16*//*Label 9488*/ GIMT_Encode4(467474),
     /* 467466 */ /*GILLT_s32*//*Label 9489*/ GIMT_Encode4(467505),
     /* 467470 */ /*GILLT_s64*//*Label 9490*/ GIMT_Encode4(467536),
     /* 467474 */ // Label 9488: @467474
     /* 467474 */ GIM_Try, /*On fail goto*//*Label 9492*/ GIMT_Encode4(467504), // Rule ID 1711 //
     /* 467479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEONandIsStreamingSafe),
     /* 467482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 467485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 467489 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR16RegClassID),
     /* 467493 */   // (AArch64uitof:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)  =>  (UCVTFv1i16:{ *:[f16] } FPR16:{ *:[f16] }:$Rn)
     /* 467493 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i16),
     /* 467498 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 467502 */   GIR_RootConstrainSelectedInstOperands,
     /* 467503 */   // GIR_Coverage, 1711,
     /* 467503 */   GIR_Done,
     /* 467504 */ // Label 9492: @467504
     /* 467504 */ GIM_Reject,
     /* 467505 */ // Label 9489: @467505
     /* 467505 */ GIM_Try, /*On fail goto*//*Label 9493*/ GIMT_Encode4(467535), // Rule ID 1710 //
     /* 467510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 467513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 467516 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 467520 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR32RegClassID),
     /* 467524 */   // (AArch64uitof:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)  =>  (UCVTFv1i32:{ *:[f32] } FPR32:{ *:[f32] }:$Rn)
     /* 467524 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i32),
     /* 467529 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 467533 */   GIR_RootConstrainSelectedInstOperands,
     /* 467534 */   // GIR_Coverage, 1710,
     /* 467534 */   GIR_Done,
     /* 467535 */ // Label 9493: @467535
     /* 467535 */ GIM_Reject,
     /* 467536 */ // Label 9490: @467536
     /* 467536 */ GIM_Try, /*On fail goto*//*Label 9494*/ GIMT_Encode4(467566), // Rule ID 1709 //
     /* 467541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEONandIsStreamingSafe),
     /* 467544 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 467547 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467551 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467555 */   // (AArch64uitof:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)  =>  (UCVTFv1i64:{ *:[f64] } FPR64:{ *:[f64] }:$Rn)
     /* 467555 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UCVTFv1i64),
     /* 467560 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AArch64::FPCR),
     /* 467564 */   GIR_RootConstrainSelectedInstOperands,
     /* 467565 */   // GIR_Coverage, 1709,
     /* 467565 */   GIR_Done,
     /* 467566 */ // Label 9494: @467566
     /* 467566 */ GIM_Reject,
     /* 467567 */ // Label 9491: @467567
     /* 467567 */ GIM_Reject,
     /* 467568 */ // Label 164: @467568
     /* 467568 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(6), GIMT_Encode2(11), /*)*//*default:*//*Label 9498*/ GIMT_Encode4(468800),
     /* 467579 */ /*GILLT_v2s64*//*Label 9495*/ GIMT_Encode4(467599), GIMT_Encode4(0),
     /* 467587 */ /*GILLT_v4s32*//*Label 9496*/ GIMT_Encode4(468160), GIMT_Encode4(0),
     /* 467595 */ /*GILLT_v8s16*//*Label 9497*/ GIMT_Encode4(468721),
     /* 467599 */ // Label 9495: @467599
     /* 467599 */ GIM_Try, /*On fail goto*//*Label 9499*/ GIMT_Encode4(468159),
     /* 467604 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 467607 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 467610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467614 */   GIM_Try, /*On fail goto*//*Label 9500*/ GIMT_Encode4(467706), // Rule ID 2137 //
     /* 467619 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 467622 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 467626 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 467630 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467634 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467638 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467642 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467646 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467650 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467655 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467659 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467663 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467667 */     // MIs[3] Operand 1
     /* 467667 */     // No operand predicates
     /* 467667 */     // MIs[1] Operand 2
     /* 467667 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 467678 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467680 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 467687 */     // (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }))  =>  (UMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467687 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_indexed),
     /* 467690 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 467692 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 467697 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467701 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467704 */     GIR_RootConstrainSelectedInstOperands,
     /* 467705 */     // GIR_Coverage, 2137,
     /* 467705 */     GIR_EraseRootFromParent_Done,
     /* 467706 */   // Label 9500: @467706
     /* 467706 */   GIM_Try, /*On fail goto*//*Label 9501*/ GIMT_Encode4(467798), // Rule ID 14578 //
     /* 467711 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 467714 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 467718 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 467722 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467726 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467730 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467734 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467738 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467742 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467747 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467751 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467755 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467759 */     // MIs[3] Operand 1
     /* 467759 */     // No operand predicates
     /* 467759 */     // MIs[1] Operand 2
     /* 467759 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(2),
     /* 467770 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467772 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 467779 */     // (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 2:{ *:[i64] }), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn))  =>  (UMULLv4i32_indexed:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467779 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_indexed),
     /* 467782 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 467784 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 467789 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467793 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467796 */     GIR_RootConstrainSelectedInstOperands,
     /* 467797 */     // GIR_Coverage, 14578,
     /* 467797 */     GIR_EraseRootFromParent_Done,
     /* 467798 */   // Label 9501: @467798
     /* 467798 */   GIM_Try, /*On fail goto*//*Label 9502*/ GIMT_Encode4(467884), // Rule ID 14576 //
     /* 467803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 467806 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 467810 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 467814 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467818 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467822 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467826 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467830 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467834 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467839 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467843 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467847 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467851 */     // MIs[3] Operand 1
     /* 467851 */     // No operand predicates
     /* 467851 */     // MIs[1] Operand 2
     /* 467851 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 467862 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467866 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467868 */     // (AArch64umull:{ *:[v2i64] } (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }), V64:{ *:[v2i32] }:$Rn)  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 467871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 467873 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 467875 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467879 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467882 */     GIR_RootConstrainSelectedInstOperands,
     /* 467883 */     // GIR_Coverage, 14576,
     /* 467883 */     GIR_EraseRootFromParent_Done,
     /* 467884 */   // Label 9502: @467884
     /* 467884 */   GIM_Try, /*On fail goto*//*Label 9503*/ GIMT_Encode4(467970), // Rule ID 2135 //
     /* 467889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 467892 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 467896 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 467900 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 467904 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467908 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 467912 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 467916 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 467920 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 467924 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 467929 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 467933 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 467937 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 467941 */     // MIs[3] Operand 1
     /* 467941 */     // No operand predicates
     /* 467941 */     // MIs[1] Operand 2
     /* 467941 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 467952 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 467954 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (extract_subvector:{ *:[v2i32] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), 0:{ *:[i64] }))  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 467954 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 467957 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 467959 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 467961 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 467965 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 467968 */     GIR_RootConstrainSelectedInstOperands,
     /* 467969 */     // GIR_Coverage, 2135,
     /* 467969 */     GIR_EraseRootFromParent_Done,
     /* 467970 */   // Label 9503: @467970
     /* 467970 */   GIM_Try, /*On fail goto*//*Label 9504*/ GIMT_Encode4(468009), // Rule ID 1862 //
     /* 467975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 467978 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 467985 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v4i32),
     /* 467992 */     // (AArch64umull:{ *:[v2i64] } (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rn), (extract_high_v4i32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm))  =>  (UMULLv4i32_v2i64:{ *:[v2i64] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 467992 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i32_v2i64),
     /* 467995 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 467997 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 468002 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 468007 */     GIR_RootConstrainSelectedInstOperands,
     /* 468008 */     // GIR_Coverage, 1862,
     /* 468008 */     GIR_EraseRootFromParent_Done,
     /* 468009 */   // Label 9504: @468009
     /* 468009 */   GIM_Try, /*On fail goto*//*Label 9505*/ GIMT_Encode4(468072), // Rule ID 14577 //
     /* 468014 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468017 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 468021 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 468025 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 468029 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 468033 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468038 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 468042 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468046 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 468050 */     // MIs[2] Operand 1
     /* 468050 */     // No operand predicates
     /* 468050 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468054 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 468056 */     // (AArch64umull:{ *:[v2i64] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx), V64:{ *:[v2i32] }:$Rn)  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 468059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468061 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 468063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 468067 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 468070 */     GIR_RootConstrainSelectedInstOperands,
     /* 468071 */     // GIR_Coverage, 14577,
     /* 468071 */     GIR_EraseRootFromParent_Done,
     /* 468072 */   // Label 9505: @468072
     /* 468072 */   GIM_Try, /*On fail goto*//*Label 9506*/ GIMT_Encode4(468135), // Rule ID 2136 //
     /* 468077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468080 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468084 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 468088 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 468092 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 468096 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 468100 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468105 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 468109 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468113 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 468117 */     // MIs[2] Operand 1
     /* 468117 */     // No operand predicates
     /* 468117 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 468119 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx))  =>  (UMULLv2i32_indexed:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468119 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_indexed),
     /* 468122 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468124 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 468126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 468130 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 468133 */     GIR_RootConstrainSelectedInstOperands,
     /* 468134 */     // GIR_Coverage, 2136,
     /* 468134 */     GIR_EraseRootFromParent_Done,
     /* 468135 */   // Label 9506: @468135
     /* 468135 */   GIM_Try, /*On fail goto*//*Label 9507*/ GIMT_Encode4(468158), // Rule ID 1861 //
     /* 468140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468151 */     // (AArch64umull:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UMULLv2i32_v2i64:{ *:[v2i64] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 468151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv2i32_v2i64),
     /* 468156 */     GIR_RootConstrainSelectedInstOperands,
     /* 468157 */     // GIR_Coverage, 1861,
     /* 468157 */     GIR_Done,
     /* 468158 */   // Label 9507: @468158
     /* 468158 */   GIM_Reject,
     /* 468159 */ // Label 9499: @468159
     /* 468159 */ GIM_Reject,
     /* 468160 */ // Label 9496: @468160
     /* 468160 */ GIM_Try, /*On fail goto*//*Label 9508*/ GIMT_Encode4(468720),
     /* 468165 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 468168 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 468171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468175 */   GIM_Try, /*On fail goto*//*Label 9509*/ GIMT_Encode4(468267), // Rule ID 2134 //
     /* 468180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 468187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 468191 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468195 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 468199 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468203 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468207 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 468211 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468216 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 468220 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468224 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468228 */     // MIs[3] Operand 1
     /* 468228 */     // No operand predicates
     /* 468228 */     // MIs[1] Operand 2
     /* 468228 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 468239 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 468241 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 468248 */     // (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }))  =>  (UMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468248 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_indexed),
     /* 468251 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468253 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 468258 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 468262 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 468265 */     GIR_RootConstrainSelectedInstOperands,
     /* 468266 */     // GIR_Coverage, 2134,
     /* 468266 */     GIR_EraseRootFromParent_Done,
     /* 468267 */   // Label 9509: @468267
     /* 468267 */   GIM_Try, /*On fail goto*//*Label 9510*/ GIMT_Encode4(468359), // Rule ID 14575 //
     /* 468272 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468275 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 468279 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 468283 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468287 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 468291 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468295 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468299 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 468303 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468308 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 468312 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468316 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468320 */     // MIs[3] Operand 1
     /* 468320 */     // No operand predicates
     /* 468320 */     // MIs[1] Operand 2
     /* 468320 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4),
     /* 468331 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 468333 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 468340 */     // (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 4:{ *:[i64] }), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn))  =>  (UMULLv8i16_indexed:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_indexed),
     /* 468343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468345 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 468350 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 468354 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 468357 */     GIR_RootConstrainSelectedInstOperands,
     /* 468358 */     // GIR_Coverage, 14575,
     /* 468358 */     GIR_EraseRootFromParent_Done,
     /* 468359 */   // Label 9510: @468359
     /* 468359 */   GIM_Try, /*On fail goto*//*Label 9511*/ GIMT_Encode4(468445), // Rule ID 14573 //
     /* 468364 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468367 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 468371 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 468375 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468379 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 468383 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468387 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468391 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 468395 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468400 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 468404 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468408 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468412 */     // MIs[3] Operand 1
     /* 468412 */     // No operand predicates
     /* 468412 */     // MIs[1] Operand 2
     /* 468412 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 468423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468427 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 468429 */     // (AArch64umull:{ *:[v4i32] } (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }), V64:{ *:[v4i16] }:$Rn)  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468429 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 468432 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468434 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 468436 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 468440 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 468443 */     GIR_RootConstrainSelectedInstOperands,
     /* 468444 */     // GIR_Coverage, 14573,
     /* 468444 */     GIR_EraseRootFromParent_Done,
     /* 468445 */   // Label 9511: @468445
     /* 468445 */   GIM_Try, /*On fail goto*//*Label 9512*/ GIMT_Encode4(468531), // Rule ID 2132 //
     /* 468450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468453 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468457 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 468461 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_EXTRACT_SUBVECTOR),
     /* 468465 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468469 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 468473 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468477 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468481 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 468485 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468490 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 468494 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468498 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468502 */     // MIs[3] Operand 1
     /* 468502 */     // No operand predicates
     /* 468502 */     // MIs[1] Operand 2
     /* 468502 */     GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(0),
     /* 468513 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 468515 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (extract_subvector:{ *:[v4i16] } (AArch64duplane16:{ *:[v8i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), 0:{ *:[i64] }))  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468515 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 468518 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468520 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 468522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 468526 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 468529 */     GIR_RootConstrainSelectedInstOperands,
     /* 468530 */     // GIR_Coverage, 2132,
     /* 468530 */     GIR_EraseRootFromParent_Done,
     /* 468531 */   // Label 9512: @468531
     /* 468531 */   GIM_Try, /*On fail goto*//*Label 9513*/ GIMT_Encode4(468570), // Rule ID 1860 //
     /* 468536 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468539 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 468546 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v8i16),
     /* 468553 */     // (AArch64umull:{ *:[v4i32] } (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rn), (extract_high_v8i16:{ *:[v4i16] } V128:{ *:[v8i16] }:$Rm))  =>  (UMULLv8i16_v4i32:{ *:[v4i32] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 468553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i16_v4i32),
     /* 468556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468558 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 468563 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 468568 */     GIR_RootConstrainSelectedInstOperands,
     /* 468569 */     // GIR_Coverage, 1860,
     /* 468569 */     GIR_EraseRootFromParent_Done,
     /* 468570 */   // Label 9513: @468570
     /* 468570 */   GIM_Try, /*On fail goto*//*Label 9514*/ GIMT_Encode4(468633), // Rule ID 14574 //
     /* 468575 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468578 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 468582 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468586 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468590 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 468594 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468599 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 468603 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468607 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468611 */     // MIs[2] Operand 1
     /* 468611 */     // No operand predicates
     /* 468611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468615 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 468617 */     // (AArch64umull:{ *:[v4i32] } (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx), V64:{ *:[v4i16] }:$Rn)  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 468620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468622 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 468624 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 468628 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 468631 */     GIR_RootConstrainSelectedInstOperands,
     /* 468632 */     // GIR_Coverage, 14574,
     /* 468632 */     GIR_EraseRootFromParent_Done,
     /* 468633 */   // Label 9514: @468633
     /* 468633 */   GIM_Try, /*On fail goto*//*Label 9515*/ GIMT_Encode4(468696), // Rule ID 2133 //
     /* 468638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468641 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468645 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 468649 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AArch64::G_DUPLANE16),
     /* 468653 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 468657 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 468661 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128_loRegClassID),
     /* 468666 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 468670 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 468674 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexH),
     /* 468678 */     // MIs[2] Operand 1
     /* 468678 */     // No operand predicates
     /* 468678 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 468680 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, (AArch64duplane16:{ *:[v4i16] } V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexH>>:$idx))  =>  (UMULLv4i16_indexed:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V128_lo:{ *:[v8i16] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 468680 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_indexed),
     /* 468683 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468685 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 468687 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
     /* 468691 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // idx
     /* 468694 */     GIR_RootConstrainSelectedInstOperands,
     /* 468695 */     // GIR_Coverage, 2133,
     /* 468695 */     GIR_EraseRootFromParent_Done,
     /* 468696 */   // Label 9515: @468696
     /* 468696 */   GIM_Try, /*On fail goto*//*Label 9516*/ GIMT_Encode4(468719), // Rule ID 1859 //
     /* 468701 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468704 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468708 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468712 */     // (AArch64umull:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UMULLv4i16_v4i32:{ *:[v4i32] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 468712 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv4i16_v4i32),
     /* 468717 */     GIR_RootConstrainSelectedInstOperands,
     /* 468718 */     // GIR_Coverage, 1859,
     /* 468718 */     GIR_Done,
     /* 468719 */   // Label 9516: @468719
     /* 468719 */   GIM_Reject,
     /* 468720 */ // Label 9508: @468720
     /* 468720 */ GIM_Reject,
     /* 468721 */ // Label 9497: @468721
     /* 468721 */ GIM_Try, /*On fail goto*//*Label 9517*/ GIMT_Encode4(468799),
     /* 468726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 468729 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 468732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468736 */   GIM_Try, /*On fail goto*//*Label 9518*/ GIMT_Encode4(468775), // Rule ID 1858 //
     /* 468741 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468744 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 468751 */     GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_extract_high_v16i8),
     /* 468758 */     // (AArch64umull:{ *:[v8i16] } (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rn), (extract_high_v16i8:{ *:[v8i8] } V128:{ *:[v16i8] }:$Rm))  =>  (UMULLv16i8_v8i16:{ *:[v8i16] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 468758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::UMULLv16i8_v8i16),
     /* 468761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 468763 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // Rn
     /* 468768 */     GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // Rm
     /* 468773 */     GIR_RootConstrainSelectedInstOperands,
     /* 468774 */     // GIR_Coverage, 1858,
     /* 468774 */     GIR_EraseRootFromParent_Done,
     /* 468775 */   // Label 9518: @468775
     /* 468775 */   GIM_Try, /*On fail goto*//*Label 9519*/ GIMT_Encode4(468798), // Rule ID 1857 //
     /* 468780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468783 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468787 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468791 */     // (AArch64umull:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UMULLv8i8_v8i16:{ *:[v8i16] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 468791 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UMULLv8i8_v8i16),
     /* 468796 */     GIR_RootConstrainSelectedInstOperands,
     /* 468797 */     // GIR_Coverage, 1857,
     /* 468797 */     GIR_Done,
     /* 468798 */   // Label 9519: @468798
     /* 468798 */   GIM_Reject,
     /* 468799 */ // Label 9517: @468799
     /* 468799 */ GIM_Reject,
     /* 468800 */ // Label 9498: @468800
     /* 468800 */ GIM_Reject,
     /* 468801 */ // Label 165: @468801
     /* 468801 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 9528*/ GIMT_Encode4(469149),
     /* 468812 */ /*GILLT_s64*//*Label 9520*/ GIMT_Encode4(468848), GIMT_Encode4(0),
     /* 468820 */ /*GILLT_v2s32*//*Label 9521*/ GIMT_Encode4(468904),
     /* 468824 */ /*GILLT_v2s64*//*Label 9522*/ GIMT_Encode4(468939),
     /* 468828 */ /*GILLT_v4s16*//*Label 9523*/ GIMT_Encode4(468974),
     /* 468832 */ /*GILLT_v4s32*//*Label 9524*/ GIMT_Encode4(469009),
     /* 468836 */ /*GILLT_v8s8*//*Label 9525*/ GIMT_Encode4(469044),
     /* 468840 */ /*GILLT_v8s16*//*Label 9526*/ GIMT_Encode4(469079),
     /* 468844 */ /*GILLT_v16s8*//*Label 9527*/ GIMT_Encode4(469114),
     /* 468848 */ // Label 9520: @468848
     /* 468848 */ GIM_Try, /*On fail goto*//*Label 9529*/ GIMT_Encode4(468903),
     /* 468853 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 468856 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468860 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468864 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 468867 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 468872 */   GIM_Try, /*On fail goto*//*Label 9530*/ GIMT_Encode4(468887), // Rule ID 2158 //
     /* 468877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468880 */     // (AArch64urshri:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (URSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 468880 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRd),
     /* 468885 */     GIR_RootConstrainSelectedInstOperands,
     /* 468886 */     // GIR_Coverage, 2158,
     /* 468886 */     GIR_Done,
     /* 468887 */   // Label 9530: @468887
     /* 468887 */   GIM_Try, /*On fail goto*//*Label 9531*/ GIMT_Encode4(468902), // Rule ID 6930 //
     /* 468892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468895 */     // (AArch64urshri:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (URSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 468895 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRd),
     /* 468900 */     GIR_RootConstrainSelectedInstOperands,
     /* 468901 */     // GIR_Coverage, 6930,
     /* 468901 */     GIR_Done,
     /* 468902 */   // Label 9531: @468902
     /* 468902 */   GIM_Reject,
     /* 468903 */ // Label 9529: @468903
     /* 468903 */ GIM_Reject,
     /* 468904 */ // Label 9521: @468904
     /* 468904 */ GIM_Try, /*On fail goto*//*Label 9532*/ GIMT_Encode4(468938), // Rule ID 2297 //
     /* 468909 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468912 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 468915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468919 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468923 */   // MIs[0] imm
     /* 468923 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 468926 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 468931 */   // (AArch64urshri:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (URSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 468931 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv2i32_shift),
     /* 468936 */   GIR_RootConstrainSelectedInstOperands,
     /* 468937 */   // GIR_Coverage, 2297,
     /* 468937 */   GIR_Done,
     /* 468938 */ // Label 9532: @468938
     /* 468938 */ GIM_Reject,
     /* 468939 */ // Label 9522: @468939
     /* 468939 */ GIM_Try, /*On fail goto*//*Label 9533*/ GIMT_Encode4(468973), // Rule ID 2299 //
     /* 468944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468947 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 468950 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468954 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 468958 */   // MIs[0] imm
     /* 468958 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 468961 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 468966 */   // (AArch64urshri:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (URSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 468966 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv2i64_shift),
     /* 468971 */   GIR_RootConstrainSelectedInstOperands,
     /* 468972 */   // GIR_Coverage, 2299,
     /* 468972 */   GIR_Done,
     /* 468973 */ // Label 9533: @468973
     /* 468973 */ GIM_Reject,
     /* 468974 */ // Label 9523: @468974
     /* 468974 */ GIM_Try, /*On fail goto*//*Label 9534*/ GIMT_Encode4(469008), // Rule ID 2295 //
     /* 468979 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 468982 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 468985 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468989 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 468993 */   // MIs[0] imm
     /* 468993 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 468996 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 469001 */   // (AArch64urshri:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (URSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 469001 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv4i16_shift),
     /* 469006 */   GIR_RootConstrainSelectedInstOperands,
     /* 469007 */   // GIR_Coverage, 2295,
     /* 469007 */   GIR_Done,
     /* 469008 */ // Label 9534: @469008
     /* 469008 */ GIM_Reject,
     /* 469009 */ // Label 9524: @469009
     /* 469009 */ GIM_Try, /*On fail goto*//*Label 9535*/ GIMT_Encode4(469043), // Rule ID 2298 //
     /* 469014 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469017 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469024 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469028 */   // MIs[0] imm
     /* 469028 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 469031 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 469036 */   // (AArch64urshri:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (URSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 469036 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv4i32_shift),
     /* 469041 */   GIR_RootConstrainSelectedInstOperands,
     /* 469042 */   // GIR_Coverage, 2298,
     /* 469042 */   GIR_Done,
     /* 469043 */ // Label 9535: @469043
     /* 469043 */ GIM_Reject,
     /* 469044 */ // Label 9525: @469044
     /* 469044 */ GIM_Try, /*On fail goto*//*Label 9536*/ GIMT_Encode4(469078), // Rule ID 2293 //
     /* 469049 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469052 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 469055 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469059 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469063 */   // MIs[0] imm
     /* 469063 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 469066 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 469071 */   // (AArch64urshri:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (URSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 469071 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv8i8_shift),
     /* 469076 */   GIR_RootConstrainSelectedInstOperands,
     /* 469077 */   // GIR_Coverage, 2293,
     /* 469077 */   GIR_Done,
     /* 469078 */ // Label 9536: @469078
     /* 469078 */ GIM_Reject,
     /* 469079 */ // Label 9526: @469079
     /* 469079 */ GIM_Try, /*On fail goto*//*Label 9537*/ GIMT_Encode4(469113), // Rule ID 2296 //
     /* 469084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 469090 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469094 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469098 */   // MIs[0] imm
     /* 469098 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 469101 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 469106 */   // (AArch64urshri:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (URSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 469106 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv8i16_shift),
     /* 469111 */   GIR_RootConstrainSelectedInstOperands,
     /* 469112 */   // GIR_Coverage, 2296,
     /* 469112 */   GIR_Done,
     /* 469113 */ // Label 9537: @469113
     /* 469113 */ GIM_Reject,
     /* 469114 */ // Label 9527: @469114
     /* 469114 */ GIM_Try, /*On fail goto*//*Label 9538*/ GIMT_Encode4(469148), // Rule ID 2294 //
     /* 469119 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469122 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 469125 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469129 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469133 */   // MIs[0] imm
     /* 469133 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 469136 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 469141 */   // (AArch64urshri:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (URSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 469141 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::URSHRv16i8_shift),
     /* 469146 */   GIR_RootConstrainSelectedInstOperands,
     /* 469147 */   // GIR_Coverage, 2294,
     /* 469147 */   GIR_Done,
     /* 469148 */ // Label 9538: @469148
     /* 469148 */ GIM_Reject,
     /* 469149 */ // Label 9528: @469149
     /* 469149 */ GIM_Reject,
     /* 469150 */ // Label 166: @469150
     /* 469150 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(20), /*)*//*default:*//*Label 9542*/ GIMT_Encode4(469652),
     /* 469161 */ /*GILLT_v2s32*//*Label 9539*/ GIMT_Encode4(469221), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 469173 */ /*GILLT_v4s32*//*Label 9540*/ GIMT_Encode4(469422), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /* 469217 */ /*GILLT_nxv4s32*//*Label 9541*/ GIMT_Encode4(469623),
     /* 469221 */ // Label 9539: @469221
     /* 469221 */ GIM_Try, /*On fail goto*//*Label 9543*/ GIMT_Encode4(469421),
     /* 469226 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 469229 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 469232 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
     /* 469235 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469239 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469243 */   GIM_Try, /*On fail goto*//*Label 9544*/ GIMT_Encode4(469320), // Rule ID 37 //
     /* 469248 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469251 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 469255 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 469259 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 469263 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 469267 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 469271 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469275 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 469279 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469284 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 469288 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 469292 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 469296 */     // MIs[3] Operand 1
     /* 469296 */     // No operand predicates
     /* 469296 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469300 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 469302 */     // (AArch64usdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V64:{ *:[v8i8] }:$Rn)  =>  (SUDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 469302 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOTlanev8i8),
     /* 469305 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 469307 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 469309 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 469311 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 469315 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 469318 */     GIR_RootConstrainSelectedInstOperands,
     /* 469319 */     // GIR_Coverage, 37,
     /* 469319 */     GIR_EraseRootFromParent_Done,
     /* 469320 */   // Label 9544: @469320
     /* 469320 */   GIM_Try, /*On fail goto*//*Label 9545*/ GIMT_Encode4(469397), // Rule ID 35 //
     /* 469325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469332 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 469336 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 469340 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 469344 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 469348 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 469352 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469356 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 469360 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469365 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 469369 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 469373 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 469377 */     // MIs[3] Operand 1
     /* 469377 */     // No operand predicates
     /* 469377 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 469379 */     // (AArch64usdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, (bitconvert:{ *:[v8i8] } (AArch64duplane32:{ *:[v2i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (USDOTlanev8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 469379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTlanev8i8),
     /* 469382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 469384 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 469386 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 469388 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 469392 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 469395 */     GIR_RootConstrainSelectedInstOperands,
     /* 469396 */     // GIR_Coverage, 35,
     /* 469396 */     GIR_EraseRootFromParent_Done,
     /* 469397 */   // Label 9545: @469397
     /* 469397 */   GIM_Try, /*On fail goto*//*Label 9546*/ GIMT_Encode4(469420), // Rule ID 33 //
     /* 469402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469409 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469413 */     // (AArch64usdot:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (USDOTv8i8:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rd, V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 469413 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USDOTv8i8),
     /* 469418 */     GIR_RootConstrainSelectedInstOperands,
     /* 469419 */     // GIR_Coverage, 33,
     /* 469419 */     GIR_Done,
     /* 469420 */   // Label 9546: @469420
     /* 469420 */   GIM_Reject,
     /* 469421 */ // Label 9543: @469421
     /* 469421 */ GIM_Reject,
     /* 469422 */ // Label 9540: @469422
     /* 469422 */ GIM_Try, /*On fail goto*//*Label 9547*/ GIMT_Encode4(469622),
     /* 469427 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469430 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 469433 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 469436 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469440 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469444 */   GIM_Try, /*On fail goto*//*Label 9548*/ GIMT_Encode4(469521), // Rule ID 38 //
     /* 469449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 469456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 469460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469464 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 469468 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 469472 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469476 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 469480 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469485 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 469489 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 469493 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 469497 */     // MIs[3] Operand 1
     /* 469497 */     // No operand predicates
     /* 469497 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469501 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 469503 */     // (AArch64usdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)), V128:{ *:[v16i8] }:$Rn)  =>  (SUDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 469503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::SUDOTlanev16i8),
     /* 469506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 469508 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 469510 */     GIR_RootToRootCopy, /*OpIdx*/3, // Rn
     /* 469512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 469516 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 469519 */     GIR_RootConstrainSelectedInstOperands,
     /* 469520 */     // GIR_Coverage, 38,
     /* 469520 */     GIR_EraseRootFromParent_Done,
     /* 469521 */   // Label 9548: @469521
     /* 469521 */   GIM_Try, /*On fail goto*//*Label 9549*/ GIMT_Encode4(469598), // Rule ID 36 //
     /* 469526 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469533 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 469537 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
     /* 469541 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469545 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 469549 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(AArch64::G_DUPLANE32),
     /* 469553 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469557 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 469561 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469566 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 469570 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 469574 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_VectorIndexS),
     /* 469578 */     // MIs[3] Operand 1
     /* 469578 */     // No operand predicates
     /* 469578 */     GIM_CheckIsSafeToFold, /*NumInsns*/3,
     /* 469580 */     // (AArch64usdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, (bitconvert:{ *:[v16i8] } (AArch64duplane32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] })<<P:Predicate_VectorIndexS>>:$idx)))  =>  (USDOTlanev16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v4i32] }:$Rm, (imm:{ *:[i64] }):$idx)
     /* 469580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::USDOTlanev16i8),
     /* 469583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 469585 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rd
     /* 469587 */     GIR_RootToRootCopy, /*OpIdx*/2, // Rn
     /* 469589 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
     /* 469593 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // idx
     /* 469596 */     GIR_RootConstrainSelectedInstOperands,
     /* 469597 */     // GIR_Coverage, 36,
     /* 469597 */     GIR_EraseRootFromParent_Done,
     /* 469598 */   // Label 9549: @469598
     /* 469598 */   GIM_Try, /*On fail goto*//*Label 9550*/ GIMT_Encode4(469621), // Rule ID 34 //
     /* 469603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
     /* 469606 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469610 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469614 */     // (AArch64usdot:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (USDOTv16i8:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rd, V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 469614 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USDOTv16i8),
     /* 469619 */     GIR_RootConstrainSelectedInstOperands,
     /* 469620 */     // GIR_Coverage, 34,
     /* 469620 */     GIR_Done,
     /* 469621 */   // Label 9550: @469621
     /* 469621 */   GIM_Reject,
     /* 469622 */ // Label 9547: @469622
     /* 469622 */ GIM_Reject,
     /* 469623 */ // Label 9541: @469623
     /* 469623 */ GIM_Try, /*On fail goto*//*Label 9551*/ GIMT_Encode4(469651), // Rule ID 3542 //
     /* 469628 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8_HasSVE_or_SME),
     /* 469631 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 469634 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 469637 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_nxv16s8,
     /* 469640 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 469644 */   // (AArch64usdot:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2, nxv16i8:{ *:[nxv16i8] }:$Op3)  =>  (USDOT_ZZZ:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv16i8] }:$Op2, ?:{ *:[nxv16i8] }:$Op3)
     /* 469644 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USDOT_ZZZ),
     /* 469649 */   GIR_RootConstrainSelectedInstOperands,
     /* 469650 */   // GIR_Coverage, 3542,
     /* 469650 */   GIR_Done,
     /* 469651 */ // Label 9551: @469651
     /* 469651 */ GIM_Reject,
     /* 469652 */ // Label 9542: @469652
     /* 469652 */ GIM_Reject,
     /* 469653 */ // Label 167: @469653
     /* 469653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9570*/ GIMT_Encode4(470432),
     /* 469664 */ /*GILLT_v2s32*//*Label 9552*/ GIMT_Encode4(469740),
     /* 469668 */ /*GILLT_v2s64*//*Label 9553*/ GIMT_Encode4(469795),
     /* 469672 */ /*GILLT_v4s16*//*Label 9554*/ GIMT_Encode4(469850),
     /* 469676 */ /*GILLT_v4s32*//*Label 9555*/ GIMT_Encode4(469905),
     /* 469680 */ /*GILLT_v8s8*//*Label 9556*/ GIMT_Encode4(469960),
     /* 469684 */ /*GILLT_v8s16*//*Label 9557*/ GIMT_Encode4(469994),
     /* 469688 */ /*GILLT_v16s8*//*Label 9558*/ GIMT_Encode4(470049), GIMT_Encode4(0),
     /* 469696 */ /*GILLT_nxv2s1*//*Label 9559*/ GIMT_Encode4(470083),
     /* 469700 */ /*GILLT_nxv2s16*//*Label 9560*/ GIMT_Encode4(470109),
     /* 469704 */ /*GILLT_nxv2s32*//*Label 9561*/ GIMT_Encode4(470135),
     /* 469708 */ /*GILLT_nxv2s64*//*Label 9562*/ GIMT_Encode4(470161),
     /* 469712 */ /*GILLT_nxv4s1*//*Label 9563*/ GIMT_Encode4(470208),
     /* 469716 */ /*GILLT_nxv4s16*//*Label 9564*/ GIMT_Encode4(470234),
     /* 469720 */ /*GILLT_nxv4s32*//*Label 9565*/ GIMT_Encode4(470260),
     /* 469724 */ /*GILLT_nxv8s1*//*Label 9566*/ GIMT_Encode4(470307),
     /* 469728 */ /*GILLT_nxv8s16*//*Label 9567*/ GIMT_Encode4(470333),
     /* 469732 */ /*GILLT_nxv16s1*//*Label 9568*/ GIMT_Encode4(470380),
     /* 469736 */ /*GILLT_nxv16s8*//*Label 9569*/ GIMT_Encode4(470406),
     /* 469740 */ // Label 9552: @469740
     /* 469740 */ GIM_Try, /*On fail goto*//*Label 9571*/ GIMT_Encode4(469794),
     /* 469745 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 469748 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 469751 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469755 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469759 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469763 */   GIM_Try, /*On fail goto*//*Label 9572*/ GIMT_Encode4(469778), // Rule ID 1919 //
     /* 469768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469771 */     // (AArch64uzp1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UZP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 469771 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
     /* 469776 */     GIR_RootConstrainSelectedInstOperands,
     /* 469777 */     // GIR_Coverage, 1919,
     /* 469777 */     GIR_Done,
     /* 469778 */   // Label 9572: @469778
     /* 469778 */   GIM_Try, /*On fail goto*//*Label 9573*/ GIMT_Encode4(469793), // Rule ID 6073 //
     /* 469783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469786 */     // (AArch64uzp1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (UZP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 469786 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i32),
     /* 469791 */     GIR_RootConstrainSelectedInstOperands,
     /* 469792 */     // GIR_Coverage, 6073,
     /* 469792 */     GIR_Done,
     /* 469793 */   // Label 9573: @469793
     /* 469793 */   GIM_Reject,
     /* 469794 */ // Label 9571: @469794
     /* 469794 */ GIM_Reject,
     /* 469795 */ // Label 9553: @469795
     /* 469795 */ GIM_Try, /*On fail goto*//*Label 9574*/ GIMT_Encode4(469849),
     /* 469800 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 469803 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 469806 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469810 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469814 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469818 */   GIM_Try, /*On fail goto*//*Label 9575*/ GIMT_Encode4(469833), // Rule ID 1921 //
     /* 469823 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469826 */     // (AArch64uzp1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UZP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 469826 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
     /* 469831 */     GIR_RootConstrainSelectedInstOperands,
     /* 469832 */     // GIR_Coverage, 1921,
     /* 469832 */     GIR_Done,
     /* 469833 */   // Label 9575: @469833
     /* 469833 */   GIM_Try, /*On fail goto*//*Label 9576*/ GIMT_Encode4(469848), // Rule ID 6075 //
     /* 469838 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469841 */     // (AArch64uzp1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (UZP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 469841 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v2i64),
     /* 469846 */     GIR_RootConstrainSelectedInstOperands,
     /* 469847 */     // GIR_Coverage, 6075,
     /* 469847 */     GIR_Done,
     /* 469848 */   // Label 9576: @469848
     /* 469848 */   GIM_Reject,
     /* 469849 */ // Label 9574: @469849
     /* 469849 */ GIM_Reject,
     /* 469850 */ // Label 9554: @469850
     /* 469850 */ GIM_Try, /*On fail goto*//*Label 9577*/ GIMT_Encode4(469904),
     /* 469855 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 469858 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 469861 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469865 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469869 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469873 */   GIM_Try, /*On fail goto*//*Label 9578*/ GIMT_Encode4(469888), // Rule ID 1917 //
     /* 469878 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469881 */     // (AArch64uzp1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UZP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 469881 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 469886 */     GIR_RootConstrainSelectedInstOperands,
     /* 469887 */     // GIR_Coverage, 1917,
     /* 469887 */     GIR_Done,
     /* 469888 */   // Label 9578: @469888
     /* 469888 */   GIM_Try, /*On fail goto*//*Label 9579*/ GIMT_Encode4(469903), // Rule ID 6071 //
     /* 469893 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469896 */     // (AArch64uzp1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (UZP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 469896 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i16),
     /* 469901 */     GIR_RootConstrainSelectedInstOperands,
     /* 469902 */     // GIR_Coverage, 6071,
     /* 469902 */     GIR_Done,
     /* 469903 */   // Label 9579: @469903
     /* 469903 */   GIM_Reject,
     /* 469904 */ // Label 9577: @469904
     /* 469904 */ GIM_Reject,
     /* 469905 */ // Label 9555: @469905
     /* 469905 */ GIM_Try, /*On fail goto*//*Label 9580*/ GIMT_Encode4(469959),
     /* 469910 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 469913 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 469916 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469920 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469924 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 469928 */   GIM_Try, /*On fail goto*//*Label 9581*/ GIMT_Encode4(469943), // Rule ID 1920 //
     /* 469933 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469936 */     // (AArch64uzp1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 469936 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 469941 */     GIR_RootConstrainSelectedInstOperands,
     /* 469942 */     // GIR_Coverage, 1920,
     /* 469942 */     GIR_Done,
     /* 469943 */   // Label 9581: @469943
     /* 469943 */   GIM_Try, /*On fail goto*//*Label 9582*/ GIMT_Encode4(469958), // Rule ID 6074 //
     /* 469948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469951 */     // (AArch64uzp1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (UZP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 469951 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v4i32),
     /* 469956 */     GIR_RootConstrainSelectedInstOperands,
     /* 469957 */     // GIR_Coverage, 6074,
     /* 469957 */     GIR_Done,
     /* 469958 */   // Label 9582: @469958
     /* 469958 */   GIM_Reject,
     /* 469959 */ // Label 9580: @469959
     /* 469959 */ GIM_Reject,
     /* 469960 */ // Label 9556: @469960
     /* 469960 */ GIM_Try, /*On fail goto*//*Label 9583*/ GIMT_Encode4(469993), // Rule ID 1915 //
     /* 469965 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 469968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 469971 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 469974 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469978 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469982 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 469986 */   // (AArch64uzp1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UZP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 469986 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i8),
     /* 469991 */   GIR_RootConstrainSelectedInstOperands,
     /* 469992 */   // GIR_Coverage, 1915,
     /* 469992 */   GIR_Done,
     /* 469993 */ // Label 9583: @469993
     /* 469993 */ GIM_Reject,
     /* 469994 */ // Label 9557: @469994
     /* 469994 */ GIM_Try, /*On fail goto*//*Label 9584*/ GIMT_Encode4(470048),
     /* 469999 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 470002 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 470005 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470009 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470013 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470017 */   GIM_Try, /*On fail goto*//*Label 9585*/ GIMT_Encode4(470032), // Rule ID 1918 //
     /* 470022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470025 */     // (AArch64uzp1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 470025 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 470030 */     GIR_RootConstrainSelectedInstOperands,
     /* 470031 */     // GIR_Coverage, 1918,
     /* 470031 */     GIR_Done,
     /* 470032 */   // Label 9585: @470032
     /* 470032 */   GIM_Try, /*On fail goto*//*Label 9586*/ GIMT_Encode4(470047), // Rule ID 6072 //
     /* 470037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470040 */     // (AArch64uzp1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (UZP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 470040 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v8i16),
     /* 470045 */     GIR_RootConstrainSelectedInstOperands,
     /* 470046 */     // GIR_Coverage, 6072,
     /* 470046 */     GIR_Done,
     /* 470047 */   // Label 9586: @470047
     /* 470047 */   GIM_Reject,
     /* 470048 */ // Label 9584: @470048
     /* 470048 */ GIM_Reject,
     /* 470049 */ // Label 9558: @470049
     /* 470049 */ GIM_Try, /*On fail goto*//*Label 9587*/ GIMT_Encode4(470082), // Rule ID 1916 //
     /* 470054 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470057 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 470060 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 470063 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470067 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470071 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470075 */   // (AArch64uzp1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 470075 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1v16i8),
     /* 470080 */   GIR_RootConstrainSelectedInstOperands,
     /* 470081 */   // GIR_Coverage, 1916,
     /* 470081 */   GIR_Done,
     /* 470082 */ // Label 9587: @470082
     /* 470082 */ GIM_Reject,
     /* 470083 */ // Label 9559: @470083
     /* 470083 */ GIM_Try, /*On fail goto*//*Label 9588*/ GIMT_Encode4(470108), // Rule ID 9693 //
     /* 470088 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470091 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 470094 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 470097 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 470101 */   // (AArch64uzp1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UZP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 470101 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_D),
     /* 470106 */   GIR_RootConstrainSelectedInstOperands,
     /* 470107 */   // GIR_Coverage, 9693,
     /* 470107 */   GIR_Done,
     /* 470108 */ // Label 9588: @470108
     /* 470108 */ GIM_Reject,
     /* 470109 */ // Label 9560: @470109
     /* 470109 */ GIM_Try, /*On fail goto*//*Label 9589*/ GIMT_Encode4(470134), // Rule ID 9655 //
     /* 470114 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470117 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 470120 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 470123 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470127 */   // (AArch64uzp1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 470127 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 470132 */   GIR_RootConstrainSelectedInstOperands,
     /* 470133 */   // GIR_Coverage, 9655,
     /* 470133 */   GIR_Done,
     /* 470134 */ // Label 9589: @470134
     /* 470134 */ GIM_Reject,
     /* 470135 */ // Label 9561: @470135
     /* 470135 */ GIM_Try, /*On fail goto*//*Label 9590*/ GIMT_Encode4(470160), // Rule ID 9656 //
     /* 470140 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 470146 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 470149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470153 */   // (AArch64uzp1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 470153 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 470158 */   GIR_RootConstrainSelectedInstOperands,
     /* 470159 */   // GIR_Coverage, 9656,
     /* 470159 */   GIR_Done,
     /* 470160 */ // Label 9590: @470160
     /* 470160 */ GIM_Reject,
     /* 470161 */ // Label 9562: @470161
     /* 470161 */ GIM_Try, /*On fail goto*//*Label 9591*/ GIMT_Encode4(470207),
     /* 470166 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 470169 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 470172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470176 */   GIM_Try, /*On fail goto*//*Label 9592*/ GIMT_Encode4(470191), // Rule ID 9651 //
     /* 470181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470184 */     // (AArch64uzp1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 470184 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 470189 */     GIR_RootConstrainSelectedInstOperands,
     /* 470190 */     // GIR_Coverage, 9651,
     /* 470190 */     GIR_Done,
     /* 470191 */   // Label 9592: @470191
     /* 470191 */   GIM_Try, /*On fail goto*//*Label 9593*/ GIMT_Encode4(470206), // Rule ID 9657 //
     /* 470196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470199 */     // (AArch64uzp1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 470199 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_D),
     /* 470204 */     GIR_RootConstrainSelectedInstOperands,
     /* 470205 */     // GIR_Coverage, 9657,
     /* 470205 */     GIR_Done,
     /* 470206 */   // Label 9593: @470206
     /* 470206 */   GIM_Reject,
     /* 470207 */ // Label 9591: @470207
     /* 470207 */ GIM_Reject,
     /* 470208 */ // Label 9563: @470208
     /* 470208 */ GIM_Try, /*On fail goto*//*Label 9594*/ GIMT_Encode4(470233), // Rule ID 9692 //
     /* 470213 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470216 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 470219 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 470222 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 470226 */   // (AArch64uzp1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UZP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 470226 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_S),
     /* 470231 */   GIR_RootConstrainSelectedInstOperands,
     /* 470232 */   // GIR_Coverage, 9692,
     /* 470232 */   GIR_Done,
     /* 470233 */ // Label 9594: @470233
     /* 470233 */ GIM_Reject,
     /* 470234 */ // Label 9564: @470234
     /* 470234 */ GIM_Try, /*On fail goto*//*Label 9595*/ GIMT_Encode4(470259), // Rule ID 9653 //
     /* 470239 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470242 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 470245 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 470248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470252 */   // (AArch64uzp1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 470252 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 470257 */   GIR_RootConstrainSelectedInstOperands,
     /* 470258 */   // GIR_Coverage, 9653,
     /* 470258 */   GIR_Done,
     /* 470259 */ // Label 9595: @470259
     /* 470259 */ GIM_Reject,
     /* 470260 */ // Label 9565: @470260
     /* 470260 */ GIM_Try, /*On fail goto*//*Label 9596*/ GIMT_Encode4(470306),
     /* 470265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 470268 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 470271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470275 */   GIM_Try, /*On fail goto*//*Label 9597*/ GIMT_Encode4(470290), // Rule ID 9650 //
     /* 470280 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470283 */     // (AArch64uzp1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 470283 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 470288 */     GIR_RootConstrainSelectedInstOperands,
     /* 470289 */     // GIR_Coverage, 9650,
     /* 470289 */     GIR_Done,
     /* 470290 */   // Label 9597: @470290
     /* 470290 */   GIM_Try, /*On fail goto*//*Label 9598*/ GIMT_Encode4(470305), // Rule ID 9654 //
     /* 470295 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470298 */     // (AArch64uzp1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 470298 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_S),
     /* 470303 */     GIR_RootConstrainSelectedInstOperands,
     /* 470304 */     // GIR_Coverage, 9654,
     /* 470304 */     GIR_Done,
     /* 470305 */   // Label 9598: @470305
     /* 470305 */   GIM_Reject,
     /* 470306 */ // Label 9596: @470306
     /* 470306 */ GIM_Reject,
     /* 470307 */ // Label 9566: @470307
     /* 470307 */ GIM_Try, /*On fail goto*//*Label 9599*/ GIMT_Encode4(470332), // Rule ID 9691 //
     /* 470312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 470318 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 470321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 470325 */   // (AArch64uzp1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UZP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 470325 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_H),
     /* 470330 */   GIR_RootConstrainSelectedInstOperands,
     /* 470331 */   // GIR_Coverage, 9691,
     /* 470331 */   GIR_Done,
     /* 470332 */ // Label 9599: @470332
     /* 470332 */ GIM_Reject,
     /* 470333 */ // Label 9567: @470333
     /* 470333 */ GIM_Try, /*On fail goto*//*Label 9600*/ GIMT_Encode4(470379),
     /* 470338 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 470341 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 470344 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470348 */   GIM_Try, /*On fail goto*//*Label 9601*/ GIMT_Encode4(470363), // Rule ID 9649 //
     /* 470353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470356 */     // (AArch64uzp1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 470356 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 470361 */     GIR_RootConstrainSelectedInstOperands,
     /* 470362 */     // GIR_Coverage, 9649,
     /* 470362 */     GIR_Done,
     /* 470363 */   // Label 9601: @470363
     /* 470363 */   GIM_Try, /*On fail goto*//*Label 9602*/ GIMT_Encode4(470378), // Rule ID 9652 //
     /* 470368 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470371 */     // (AArch64uzp1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 470371 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_H),
     /* 470376 */     GIR_RootConstrainSelectedInstOperands,
     /* 470377 */     // GIR_Coverage, 9652,
     /* 470377 */     GIR_Done,
     /* 470378 */   // Label 9602: @470378
     /* 470378 */   GIM_Reject,
     /* 470379 */ // Label 9600: @470379
     /* 470379 */ GIM_Reject,
     /* 470380 */ // Label 9568: @470380
     /* 470380 */ GIM_Try, /*On fail goto*//*Label 9603*/ GIMT_Encode4(470405), // Rule ID 2440 //
     /* 470385 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470388 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 470391 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 470394 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 470398 */   // (AArch64uzp1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 470398 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_PPP_B),
     /* 470403 */   GIR_RootConstrainSelectedInstOperands,
     /* 470404 */   // GIR_Coverage, 2440,
     /* 470404 */   GIR_Done,
     /* 470405 */ // Label 9603: @470405
     /* 470405 */ GIM_Reject,
     /* 470406 */ // Label 9569: @470406
     /* 470406 */ GIM_Try, /*On fail goto*//*Label 9604*/ GIMT_Encode4(470431), // Rule ID 9648 //
     /* 470411 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470414 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 470417 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 470420 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470424 */   // (AArch64uzp1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 470424 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP1_ZZZ_B),
     /* 470429 */   GIR_RootConstrainSelectedInstOperands,
     /* 470430 */   // GIR_Coverage, 9648,
     /* 470430 */   GIR_Done,
     /* 470431 */ // Label 9604: @470431
     /* 470431 */ GIM_Reject,
     /* 470432 */ // Label 9570: @470432
     /* 470432 */ GIM_Reject,
     /* 470433 */ // Label 168: @470433
     /* 470433 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9623*/ GIMT_Encode4(471212),
     /* 470444 */ /*GILLT_v2s32*//*Label 9605*/ GIMT_Encode4(470520),
     /* 470448 */ /*GILLT_v2s64*//*Label 9606*/ GIMT_Encode4(470575),
     /* 470452 */ /*GILLT_v4s16*//*Label 9607*/ GIMT_Encode4(470630),
     /* 470456 */ /*GILLT_v4s32*//*Label 9608*/ GIMT_Encode4(470685),
     /* 470460 */ /*GILLT_v8s8*//*Label 9609*/ GIMT_Encode4(470740),
     /* 470464 */ /*GILLT_v8s16*//*Label 9610*/ GIMT_Encode4(470774),
     /* 470468 */ /*GILLT_v16s8*//*Label 9611*/ GIMT_Encode4(470829), GIMT_Encode4(0),
     /* 470476 */ /*GILLT_nxv2s1*//*Label 9612*/ GIMT_Encode4(470863),
     /* 470480 */ /*GILLT_nxv2s16*//*Label 9613*/ GIMT_Encode4(470889),
     /* 470484 */ /*GILLT_nxv2s32*//*Label 9614*/ GIMT_Encode4(470915),
     /* 470488 */ /*GILLT_nxv2s64*//*Label 9615*/ GIMT_Encode4(470941),
     /* 470492 */ /*GILLT_nxv4s1*//*Label 9616*/ GIMT_Encode4(470988),
     /* 470496 */ /*GILLT_nxv4s16*//*Label 9617*/ GIMT_Encode4(471014),
     /* 470500 */ /*GILLT_nxv4s32*//*Label 9618*/ GIMT_Encode4(471040),
     /* 470504 */ /*GILLT_nxv8s1*//*Label 9619*/ GIMT_Encode4(471087),
     /* 470508 */ /*GILLT_nxv8s16*//*Label 9620*/ GIMT_Encode4(471113),
     /* 470512 */ /*GILLT_nxv16s1*//*Label 9621*/ GIMT_Encode4(471160),
     /* 470516 */ /*GILLT_nxv16s8*//*Label 9622*/ GIMT_Encode4(471186),
     /* 470520 */ // Label 9605: @470520
     /* 470520 */ GIM_Try, /*On fail goto*//*Label 9624*/ GIMT_Encode4(470574),
     /* 470525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 470528 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 470531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470535 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470539 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470543 */   GIM_Try, /*On fail goto*//*Label 9625*/ GIMT_Encode4(470558), // Rule ID 1926 //
     /* 470548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470551 */     // (AArch64uzp2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (UZP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 470551 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
     /* 470556 */     GIR_RootConstrainSelectedInstOperands,
     /* 470557 */     // GIR_Coverage, 1926,
     /* 470557 */     GIR_Done,
     /* 470558 */   // Label 9625: @470558
     /* 470558 */   GIM_Try, /*On fail goto*//*Label 9626*/ GIMT_Encode4(470573), // Rule ID 6078 //
     /* 470563 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470566 */     // (AArch64uzp2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (UZP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 470566 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i32),
     /* 470571 */     GIR_RootConstrainSelectedInstOperands,
     /* 470572 */     // GIR_Coverage, 6078,
     /* 470572 */     GIR_Done,
     /* 470573 */   // Label 9626: @470573
     /* 470573 */   GIM_Reject,
     /* 470574 */ // Label 9624: @470574
     /* 470574 */ GIM_Reject,
     /* 470575 */ // Label 9606: @470575
     /* 470575 */ GIM_Try, /*On fail goto*//*Label 9627*/ GIMT_Encode4(470629),
     /* 470580 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 470583 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 470586 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470590 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470594 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470598 */   GIM_Try, /*On fail goto*//*Label 9628*/ GIMT_Encode4(470613), // Rule ID 1928 //
     /* 470603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470606 */     // (AArch64uzp2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (UZP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 470606 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
     /* 470611 */     GIR_RootConstrainSelectedInstOperands,
     /* 470612 */     // GIR_Coverage, 1928,
     /* 470612 */     GIR_Done,
     /* 470613 */   // Label 9628: @470613
     /* 470613 */   GIM_Try, /*On fail goto*//*Label 9629*/ GIMT_Encode4(470628), // Rule ID 6080 //
     /* 470618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470621 */     // (AArch64uzp2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (UZP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 470621 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v2i64),
     /* 470626 */     GIR_RootConstrainSelectedInstOperands,
     /* 470627 */     // GIR_Coverage, 6080,
     /* 470627 */     GIR_Done,
     /* 470628 */   // Label 9629: @470628
     /* 470628 */   GIM_Reject,
     /* 470629 */ // Label 9627: @470629
     /* 470629 */ GIM_Reject,
     /* 470630 */ // Label 9607: @470630
     /* 470630 */ GIM_Try, /*On fail goto*//*Label 9630*/ GIMT_Encode4(470684),
     /* 470635 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 470638 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 470641 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470645 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470649 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470653 */   GIM_Try, /*On fail goto*//*Label 9631*/ GIMT_Encode4(470668), // Rule ID 1924 //
     /* 470658 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470661 */     // (AArch64uzp2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (UZP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 470661 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
     /* 470666 */     GIR_RootConstrainSelectedInstOperands,
     /* 470667 */     // GIR_Coverage, 1924,
     /* 470667 */     GIR_Done,
     /* 470668 */   // Label 9631: @470668
     /* 470668 */   GIM_Try, /*On fail goto*//*Label 9632*/ GIMT_Encode4(470683), // Rule ID 6076 //
     /* 470673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470676 */     // (AArch64uzp2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (UZP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 470676 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i16),
     /* 470681 */     GIR_RootConstrainSelectedInstOperands,
     /* 470682 */     // GIR_Coverage, 6076,
     /* 470682 */     GIR_Done,
     /* 470683 */   // Label 9632: @470683
     /* 470683 */   GIM_Reject,
     /* 470684 */ // Label 9630: @470684
     /* 470684 */ GIM_Reject,
     /* 470685 */ // Label 9608: @470685
     /* 470685 */ GIM_Try, /*On fail goto*//*Label 9633*/ GIMT_Encode4(470739),
     /* 470690 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 470693 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 470696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470700 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470704 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470708 */   GIM_Try, /*On fail goto*//*Label 9634*/ GIMT_Encode4(470723), // Rule ID 1927 //
     /* 470713 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470716 */     // (AArch64uzp2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 470716 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 470721 */     GIR_RootConstrainSelectedInstOperands,
     /* 470722 */     // GIR_Coverage, 1927,
     /* 470722 */     GIR_Done,
     /* 470723 */   // Label 9634: @470723
     /* 470723 */   GIM_Try, /*On fail goto*//*Label 9635*/ GIMT_Encode4(470738), // Rule ID 6079 //
     /* 470728 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470731 */     // (AArch64uzp2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (UZP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 470731 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v4i32),
     /* 470736 */     GIR_RootConstrainSelectedInstOperands,
     /* 470737 */     // GIR_Coverage, 6079,
     /* 470737 */     GIR_Done,
     /* 470738 */   // Label 9635: @470738
     /* 470738 */   GIM_Reject,
     /* 470739 */ // Label 9633: @470739
     /* 470739 */ GIM_Reject,
     /* 470740 */ // Label 9609: @470740
     /* 470740 */ GIM_Try, /*On fail goto*//*Label 9636*/ GIMT_Encode4(470773), // Rule ID 1922 //
     /* 470745 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470748 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 470751 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 470754 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470758 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470762 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 470766 */   // (AArch64uzp2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (UZP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 470766 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i8),
     /* 470771 */   GIR_RootConstrainSelectedInstOperands,
     /* 470772 */   // GIR_Coverage, 1922,
     /* 470772 */   GIR_Done,
     /* 470773 */ // Label 9636: @470773
     /* 470773 */ GIM_Reject,
     /* 470774 */ // Label 9610: @470774
     /* 470774 */ GIM_Try, /*On fail goto*//*Label 9637*/ GIMT_Encode4(470828),
     /* 470779 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 470782 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 470785 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470789 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470793 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470797 */   GIM_Try, /*On fail goto*//*Label 9638*/ GIMT_Encode4(470812), // Rule ID 1925 //
     /* 470802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470805 */     // (AArch64uzp2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 470805 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 470810 */     GIR_RootConstrainSelectedInstOperands,
     /* 470811 */     // GIR_Coverage, 1925,
     /* 470811 */     GIR_Done,
     /* 470812 */   // Label 9638: @470812
     /* 470812 */   GIM_Try, /*On fail goto*//*Label 9639*/ GIMT_Encode4(470827), // Rule ID 6077 //
     /* 470817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470820 */     // (AArch64uzp2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (UZP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 470820 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v8i16),
     /* 470825 */     GIR_RootConstrainSelectedInstOperands,
     /* 470826 */     // GIR_Coverage, 6077,
     /* 470826 */     GIR_Done,
     /* 470827 */   // Label 9639: @470827
     /* 470827 */   GIM_Reject,
     /* 470828 */ // Label 9637: @470828
     /* 470828 */ GIM_Reject,
     /* 470829 */ // Label 9611: @470829
     /* 470829 */ GIM_Try, /*On fail goto*//*Label 9640*/ GIMT_Encode4(470862), // Rule ID 1923 //
     /* 470834 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 470837 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 470840 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 470843 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470847 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470851 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 470855 */   // (AArch64uzp2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (UZP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 470855 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2v16i8),
     /* 470860 */   GIR_RootConstrainSelectedInstOperands,
     /* 470861 */   // GIR_Coverage, 1923,
     /* 470861 */   GIR_Done,
     /* 470862 */ // Label 9640: @470862
     /* 470862 */ GIM_Reject,
     /* 470863 */ // Label 9612: @470863
     /* 470863 */ GIM_Try, /*On fail goto*//*Label 9641*/ GIMT_Encode4(470888), // Rule ID 9696 //
     /* 470868 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470871 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 470874 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 470877 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 470881 */   // (AArch64uzp2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (UZP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 470881 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_D),
     /* 470886 */   GIR_RootConstrainSelectedInstOperands,
     /* 470887 */   // GIR_Coverage, 9696,
     /* 470887 */   GIR_Done,
     /* 470888 */ // Label 9641: @470888
     /* 470888 */ GIM_Reject,
     /* 470889 */ // Label 9613: @470889
     /* 470889 */ GIM_Try, /*On fail goto*//*Label 9642*/ GIMT_Encode4(470914), // Rule ID 9665 //
     /* 470894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 470900 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 470903 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470907 */   // (AArch64uzp2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 470907 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 470912 */   GIR_RootConstrainSelectedInstOperands,
     /* 470913 */   // GIR_Coverage, 9665,
     /* 470913 */   GIR_Done,
     /* 470914 */ // Label 9642: @470914
     /* 470914 */ GIM_Reject,
     /* 470915 */ // Label 9614: @470915
     /* 470915 */ GIM_Try, /*On fail goto*//*Label 9643*/ GIMT_Encode4(470940), // Rule ID 9666 //
     /* 470920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 470926 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 470929 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470933 */   // (AArch64uzp2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 470933 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 470938 */   GIR_RootConstrainSelectedInstOperands,
     /* 470939 */   // GIR_Coverage, 9666,
     /* 470939 */   GIR_Done,
     /* 470940 */ // Label 9643: @470940
     /* 470940 */ GIM_Reject,
     /* 470941 */ // Label 9615: @470941
     /* 470941 */ GIM_Try, /*On fail goto*//*Label 9644*/ GIMT_Encode4(470987),
     /* 470946 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 470949 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 470952 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 470956 */   GIM_Try, /*On fail goto*//*Label 9645*/ GIMT_Encode4(470971), // Rule ID 9661 //
     /* 470961 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470964 */     // (AArch64uzp2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 470964 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 470969 */     GIR_RootConstrainSelectedInstOperands,
     /* 470970 */     // GIR_Coverage, 9661,
     /* 470970 */     GIR_Done,
     /* 470971 */   // Label 9645: @470971
     /* 470971 */   GIM_Try, /*On fail goto*//*Label 9646*/ GIMT_Encode4(470986), // Rule ID 9667 //
     /* 470976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470979 */     // (AArch64uzp2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (UZP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 470979 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_D),
     /* 470984 */     GIR_RootConstrainSelectedInstOperands,
     /* 470985 */     // GIR_Coverage, 9667,
     /* 470985 */     GIR_Done,
     /* 470986 */   // Label 9646: @470986
     /* 470986 */   GIM_Reject,
     /* 470987 */ // Label 9644: @470987
     /* 470987 */ GIM_Reject,
     /* 470988 */ // Label 9616: @470988
     /* 470988 */ GIM_Try, /*On fail goto*//*Label 9647*/ GIMT_Encode4(471013), // Rule ID 9695 //
     /* 470993 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 470996 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 470999 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 471002 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 471006 */   // (AArch64uzp2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (UZP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 471006 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_S),
     /* 471011 */   GIR_RootConstrainSelectedInstOperands,
     /* 471012 */   // GIR_Coverage, 9695,
     /* 471012 */   GIR_Done,
     /* 471013 */ // Label 9647: @471013
     /* 471013 */ GIM_Reject,
     /* 471014 */ // Label 9617: @471014
     /* 471014 */ GIM_Try, /*On fail goto*//*Label 9648*/ GIMT_Encode4(471039), // Rule ID 9663 //
     /* 471019 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471022 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 471025 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 471028 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 471032 */   // (AArch64uzp2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 471032 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 471037 */   GIR_RootConstrainSelectedInstOperands,
     /* 471038 */   // GIR_Coverage, 9663,
     /* 471038 */   GIR_Done,
     /* 471039 */ // Label 9648: @471039
     /* 471039 */ GIM_Reject,
     /* 471040 */ // Label 9618: @471040
     /* 471040 */ GIM_Try, /*On fail goto*//*Label 9649*/ GIMT_Encode4(471086),
     /* 471045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 471048 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 471051 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 471055 */   GIM_Try, /*On fail goto*//*Label 9650*/ GIMT_Encode4(471070), // Rule ID 9660 //
     /* 471060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471063 */     // (AArch64uzp2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 471063 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 471068 */     GIR_RootConstrainSelectedInstOperands,
     /* 471069 */     // GIR_Coverage, 9660,
     /* 471069 */     GIR_Done,
     /* 471070 */   // Label 9650: @471070
     /* 471070 */   GIM_Try, /*On fail goto*//*Label 9651*/ GIMT_Encode4(471085), // Rule ID 9664 //
     /* 471075 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471078 */     // (AArch64uzp2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (UZP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 471078 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_S),
     /* 471083 */     GIR_RootConstrainSelectedInstOperands,
     /* 471084 */     // GIR_Coverage, 9664,
     /* 471084 */     GIR_Done,
     /* 471085 */   // Label 9651: @471085
     /* 471085 */   GIM_Reject,
     /* 471086 */ // Label 9649: @471086
     /* 471086 */ GIM_Reject,
     /* 471087 */ // Label 9619: @471087
     /* 471087 */ GIM_Try, /*On fail goto*//*Label 9652*/ GIMT_Encode4(471112), // Rule ID 9694 //
     /* 471092 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471095 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 471098 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 471101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 471105 */   // (AArch64uzp2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (UZP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 471105 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_H),
     /* 471110 */   GIR_RootConstrainSelectedInstOperands,
     /* 471111 */   // GIR_Coverage, 9694,
     /* 471111 */   GIR_Done,
     /* 471112 */ // Label 9652: @471112
     /* 471112 */ GIM_Reject,
     /* 471113 */ // Label 9620: @471113
     /* 471113 */ GIM_Try, /*On fail goto*//*Label 9653*/ GIMT_Encode4(471159),
     /* 471118 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 471121 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 471124 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 471128 */   GIM_Try, /*On fail goto*//*Label 9654*/ GIMT_Encode4(471143), // Rule ID 9659 //
     /* 471133 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471136 */     // (AArch64uzp2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (UZP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 471136 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
     /* 471141 */     GIR_RootConstrainSelectedInstOperands,
     /* 471142 */     // GIR_Coverage, 9659,
     /* 471142 */     GIR_Done,
     /* 471143 */   // Label 9654: @471143
     /* 471143 */   GIM_Try, /*On fail goto*//*Label 9655*/ GIMT_Encode4(471158), // Rule ID 9662 //
     /* 471148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471151 */     // (AArch64uzp2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (UZP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 471151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_H),
     /* 471156 */     GIR_RootConstrainSelectedInstOperands,
     /* 471157 */     // GIR_Coverage, 9662,
     /* 471157 */     GIR_Done,
     /* 471158 */   // Label 9655: @471158
     /* 471158 */   GIM_Reject,
     /* 471159 */ // Label 9653: @471159
     /* 471159 */ GIM_Reject,
     /* 471160 */ // Label 9621: @471160
     /* 471160 */ GIM_Try, /*On fail goto*//*Label 9656*/ GIMT_Encode4(471185), // Rule ID 2444 //
     /* 471165 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471168 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 471171 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 471174 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 471178 */   // (AArch64uzp2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (UZP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 471178 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_PPP_B),
     /* 471183 */   GIR_RootConstrainSelectedInstOperands,
     /* 471184 */   // GIR_Coverage, 2444,
     /* 471184 */   GIR_Done,
     /* 471185 */ // Label 9656: @471185
     /* 471185 */ GIM_Reject,
     /* 471186 */ // Label 9622: @471186
     /* 471186 */ GIM_Try, /*On fail goto*//*Label 9657*/ GIMT_Encode4(471211), // Rule ID 9658 //
     /* 471191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 471194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 471197 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 471200 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 471204 */   // (AArch64uzp2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (UZP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 471204 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::UZP2_ZZZ_B),
     /* 471209 */   GIR_RootConstrainSelectedInstOperands,
     /* 471210 */   // GIR_Coverage, 9658,
     /* 471210 */   GIR_Done,
     /* 471211 */ // Label 9657: @471211
     /* 471211 */ GIM_Reject,
     /* 471212 */ // Label 9623: @471212
     /* 471212 */ GIM_Reject,
     /* 471213 */ // Label 169: @471213
     /* 471213 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 9666*/ GIMT_Encode4(471811),
     /* 471224 */ /*GILLT_s64*//*Label 9658*/ GIMT_Encode4(471260), GIMT_Encode4(0),
     /* 471232 */ /*GILLT_v2s32*//*Label 9659*/ GIMT_Encode4(471349),
     /* 471236 */ /*GILLT_v2s64*//*Label 9660*/ GIMT_Encode4(471415),
     /* 471240 */ /*GILLT_v4s16*//*Label 9661*/ GIMT_Encode4(471481),
     /* 471244 */ /*GILLT_v4s32*//*Label 9662*/ GIMT_Encode4(471547),
     /* 471248 */ /*GILLT_v8s8*//*Label 9663*/ GIMT_Encode4(471613),
     /* 471252 */ /*GILLT_v8s16*//*Label 9664*/ GIMT_Encode4(471679),
     /* 471256 */ /*GILLT_v16s8*//*Label 9665*/ GIMT_Encode4(471745),
     /* 471260 */ // Label 9658: @471260
     /* 471260 */ GIM_Try, /*On fail goto*//*Label 9667*/ GIMT_Encode4(471348),
     /* 471265 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 471268 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471272 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471276 */   GIM_Try, /*On fail goto*//*Label 9668*/ GIMT_Encode4(471301), // Rule ID 5828 //
     /* 471281 */     // MIs[0] Operand 2
     /* 471281 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
     /* 471292 */     // (AArch64vashr:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn, 63:{ *:[i32] })  =>  (CMLTv1i64rz:{ *:[v1i64] } V64:{ *:[v1i64] }:$Rn)
     /* 471292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv1i64rz),
     /* 471295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471297 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471299 */     GIR_RootConstrainSelectedInstOperands,
     /* 471300 */     // GIR_Coverage, 5828,
     /* 471300 */     GIR_EraseRootFromParent_Done,
     /* 471301 */   // Label 9668: @471301
     /* 471301 */   GIM_Try, /*On fail goto*//*Label 9669*/ GIMT_Encode4(471324), // Rule ID 2151 //
     /* 471306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471309 */     // MIs[0] imm
     /* 471309 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471312 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 471317 */     // (AArch64vashr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471317 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
     /* 471322 */     GIR_RootConstrainSelectedInstOperands,
     /* 471323 */     // GIR_Coverage, 2151,
     /* 471323 */     GIR_Done,
     /* 471324 */   // Label 9669: @471324
     /* 471324 */   GIM_Try, /*On fail goto*//*Label 9670*/ GIMT_Encode4(471347), // Rule ID 6928 //
     /* 471329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471332 */     // MIs[0] imm
     /* 471332 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471335 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 471340 */     // (AArch64vashr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 471340 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRd),
     /* 471345 */     GIR_RootConstrainSelectedInstOperands,
     /* 471346 */     // GIR_Coverage, 6928,
     /* 471346 */     GIR_Done,
     /* 471347 */   // Label 9670: @471347
     /* 471347 */   GIM_Reject,
     /* 471348 */ // Label 9667: @471348
     /* 471348 */ GIM_Reject,
     /* 471349 */ // Label 9659: @471349
     /* 471349 */ GIM_Try, /*On fail goto*//*Label 9671*/ GIMT_Encode4(471414),
     /* 471354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 471357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471361 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471365 */   GIM_Try, /*On fail goto*//*Label 9672*/ GIMT_Encode4(471390), // Rule ID 4963 //
     /* 471370 */     // MIs[0] Operand 2
     /* 471370 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
     /* 471381 */     // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, 31:{ *:[i32] })  =>  (CMLTv2i32rz:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn)
     /* 471381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i32rz),
     /* 471384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471386 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471388 */     GIR_RootConstrainSelectedInstOperands,
     /* 471389 */     // GIR_Coverage, 4963,
     /* 471389 */     GIR_EraseRootFromParent_Done,
     /* 471390 */   // Label 9672: @471390
     /* 471390 */   GIM_Try, /*On fail goto*//*Label 9673*/ GIMT_Encode4(471413), // Rule ID 2258 //
     /* 471395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471398 */     // MIs[0] imm
     /* 471398 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471401 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 471406 */     // (AArch64vashr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SSHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471406 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i32_shift),
     /* 471411 */     GIR_RootConstrainSelectedInstOperands,
     /* 471412 */     // GIR_Coverage, 2258,
     /* 471412 */     GIR_Done,
     /* 471413 */   // Label 9673: @471413
     /* 471413 */   GIM_Reject,
     /* 471414 */ // Label 9671: @471414
     /* 471414 */ GIM_Reject,
     /* 471415 */ // Label 9660: @471415
     /* 471415 */ GIM_Try, /*On fail goto*//*Label 9674*/ GIMT_Encode4(471480),
     /* 471420 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 471423 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471427 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471431 */   GIM_Try, /*On fail goto*//*Label 9675*/ GIMT_Encode4(471456), // Rule ID 4967 //
     /* 471436 */     // MIs[0] Operand 2
     /* 471436 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(63),
     /* 471447 */     // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, 63:{ *:[i32] })  =>  (CMLTv2i64rz:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn)
     /* 471447 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv2i64rz),
     /* 471450 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471452 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471454 */     GIR_RootConstrainSelectedInstOperands,
     /* 471455 */     // GIR_Coverage, 4967,
     /* 471455 */     GIR_EraseRootFromParent_Done,
     /* 471456 */   // Label 9675: @471456
     /* 471456 */   GIM_Try, /*On fail goto*//*Label 9676*/ GIMT_Encode4(471479), // Rule ID 2260 //
     /* 471461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471464 */     // MIs[0] imm
     /* 471464 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471467 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 471472 */     // (AArch64vashr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (SSHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471472 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv2i64_shift),
     /* 471477 */     GIR_RootConstrainSelectedInstOperands,
     /* 471478 */     // GIR_Coverage, 2260,
     /* 471478 */     GIR_Done,
     /* 471479 */   // Label 9676: @471479
     /* 471479 */   GIM_Reject,
     /* 471480 */ // Label 9674: @471480
     /* 471480 */ GIM_Reject,
     /* 471481 */ // Label 9661: @471481
     /* 471481 */ GIM_Try, /*On fail goto*//*Label 9677*/ GIMT_Encode4(471546),
     /* 471486 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 471489 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471493 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471497 */   GIM_Try, /*On fail goto*//*Label 9678*/ GIMT_Encode4(471522), // Rule ID 4962 //
     /* 471502 */     // MIs[0] Operand 2
     /* 471502 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 471513 */     // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, 15:{ *:[i32] })  =>  (CMLTv4i16rz:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn)
     /* 471513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i16rz),
     /* 471516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471518 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471520 */     GIR_RootConstrainSelectedInstOperands,
     /* 471521 */     // GIR_Coverage, 4962,
     /* 471521 */     GIR_EraseRootFromParent_Done,
     /* 471522 */   // Label 9678: @471522
     /* 471522 */   GIM_Try, /*On fail goto*//*Label 9679*/ GIMT_Encode4(471545), // Rule ID 2256 //
     /* 471527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471530 */     // MIs[0] imm
     /* 471530 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471533 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 471538 */     // (AArch64vashr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SSHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471538 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i16_shift),
     /* 471543 */     GIR_RootConstrainSelectedInstOperands,
     /* 471544 */     // GIR_Coverage, 2256,
     /* 471544 */     GIR_Done,
     /* 471545 */   // Label 9679: @471545
     /* 471545 */   GIM_Reject,
     /* 471546 */ // Label 9677: @471546
     /* 471546 */ GIM_Reject,
     /* 471547 */ // Label 9662: @471547
     /* 471547 */ GIM_Try, /*On fail goto*//*Label 9680*/ GIMT_Encode4(471612),
     /* 471552 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 471555 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471559 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471563 */   GIM_Try, /*On fail goto*//*Label 9681*/ GIMT_Encode4(471588), // Rule ID 4966 //
     /* 471568 */     // MIs[0] Operand 2
     /* 471568 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(31),
     /* 471579 */     // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, 31:{ *:[i32] })  =>  (CMLTv4i32rz:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn)
     /* 471579 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv4i32rz),
     /* 471582 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471584 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471586 */     GIR_RootConstrainSelectedInstOperands,
     /* 471587 */     // GIR_Coverage, 4966,
     /* 471587 */     GIR_EraseRootFromParent_Done,
     /* 471588 */   // Label 9681: @471588
     /* 471588 */   GIM_Try, /*On fail goto*//*Label 9682*/ GIMT_Encode4(471611), // Rule ID 2259 //
     /* 471593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471596 */     // MIs[0] imm
     /* 471596 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471599 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 471604 */     // (AArch64vashr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (SSHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471604 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv4i32_shift),
     /* 471609 */     GIR_RootConstrainSelectedInstOperands,
     /* 471610 */     // GIR_Coverage, 2259,
     /* 471610 */     GIR_Done,
     /* 471611 */   // Label 9682: @471611
     /* 471611 */   GIM_Reject,
     /* 471612 */ // Label 9680: @471612
     /* 471612 */ GIM_Reject,
     /* 471613 */ // Label 9663: @471613
     /* 471613 */ GIM_Try, /*On fail goto*//*Label 9683*/ GIMT_Encode4(471678),
     /* 471618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 471621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471625 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471629 */   GIM_Try, /*On fail goto*//*Label 9684*/ GIMT_Encode4(471654), // Rule ID 4961 //
     /* 471634 */     // MIs[0] Operand 2
     /* 471634 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 471645 */     // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, 7:{ *:[i32] })  =>  (CMLTv8i8rz:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn)
     /* 471645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i8rz),
     /* 471648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471650 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471652 */     GIR_RootConstrainSelectedInstOperands,
     /* 471653 */     // GIR_Coverage, 4961,
     /* 471653 */     GIR_EraseRootFromParent_Done,
     /* 471654 */   // Label 9684: @471654
     /* 471654 */   GIM_Try, /*On fail goto*//*Label 9685*/ GIMT_Encode4(471677), // Rule ID 2254 //
     /* 471659 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471662 */     // MIs[0] imm
     /* 471662 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471665 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 471670 */     // (AArch64vashr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SSHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471670 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i8_shift),
     /* 471675 */     GIR_RootConstrainSelectedInstOperands,
     /* 471676 */     // GIR_Coverage, 2254,
     /* 471676 */     GIR_Done,
     /* 471677 */   // Label 9685: @471677
     /* 471677 */   GIM_Reject,
     /* 471678 */ // Label 9683: @471678
     /* 471678 */ GIM_Reject,
     /* 471679 */ // Label 9664: @471679
     /* 471679 */ GIM_Try, /*On fail goto*//*Label 9686*/ GIMT_Encode4(471744),
     /* 471684 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 471687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471691 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471695 */   GIM_Try, /*On fail goto*//*Label 9687*/ GIMT_Encode4(471720), // Rule ID 4965 //
     /* 471700 */     // MIs[0] Operand 2
     /* 471700 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(15),
     /* 471711 */     // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, 15:{ *:[i32] })  =>  (CMLTv8i16rz:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn)
     /* 471711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv8i16rz),
     /* 471714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471716 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471718 */     GIR_RootConstrainSelectedInstOperands,
     /* 471719 */     // GIR_Coverage, 4965,
     /* 471719 */     GIR_EraseRootFromParent_Done,
     /* 471720 */   // Label 9687: @471720
     /* 471720 */   GIM_Try, /*On fail goto*//*Label 9688*/ GIMT_Encode4(471743), // Rule ID 2257 //
     /* 471725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471728 */     // MIs[0] imm
     /* 471728 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471731 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 471736 */     // (AArch64vashr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (SSHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471736 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv8i16_shift),
     /* 471741 */     GIR_RootConstrainSelectedInstOperands,
     /* 471742 */     // GIR_Coverage, 2257,
     /* 471742 */     GIR_Done,
     /* 471743 */   // Label 9688: @471743
     /* 471743 */   GIM_Reject,
     /* 471744 */ // Label 9686: @471744
     /* 471744 */ GIM_Reject,
     /* 471745 */ // Label 9665: @471745
     /* 471745 */ GIM_Try, /*On fail goto*//*Label 9689*/ GIMT_Encode4(471810),
     /* 471750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 471753 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471757 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471761 */   GIM_Try, /*On fail goto*//*Label 9690*/ GIMT_Encode4(471786), // Rule ID 4964 //
     /* 471766 */     // MIs[0] Operand 2
     /* 471766 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(7),
     /* 471777 */     // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, 7:{ *:[i32] })  =>  (CMLTv16i8rz:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn)
     /* 471777 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AArch64::CMLTv16i8rz),
     /* 471780 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
     /* 471782 */     GIR_RootToRootCopy, /*OpIdx*/1, // Rn
     /* 471784 */     GIR_RootConstrainSelectedInstOperands,
     /* 471785 */     // GIR_Coverage, 4964,
     /* 471785 */     GIR_EraseRootFromParent_Done,
     /* 471786 */   // Label 9690: @471786
     /* 471786 */   GIM_Try, /*On fail goto*//*Label 9691*/ GIMT_Encode4(471809), // Rule ID 2255 //
     /* 471791 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471794 */     // MIs[0] imm
     /* 471794 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471797 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 471802 */     // (AArch64vashr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (SSHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471802 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::SSHRv16i8_shift),
     /* 471807 */     GIR_RootConstrainSelectedInstOperands,
     /* 471808 */     // GIR_Coverage, 2255,
     /* 471808 */     GIR_Done,
     /* 471809 */   // Label 9691: @471809
     /* 471809 */   GIM_Reject,
     /* 471810 */ // Label 9689: @471810
     /* 471810 */ GIM_Reject,
     /* 471811 */ // Label 9666: @471811
     /* 471811 */ GIM_Reject,
     /* 471812 */ // Label 170: @471812
     /* 471812 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(3), GIMT_Encode2(12), /*)*//*default:*//*Label 9700*/ GIMT_Encode4(472160),
     /* 471823 */ /*GILLT_s64*//*Label 9692*/ GIMT_Encode4(471859), GIMT_Encode4(0),
     /* 471831 */ /*GILLT_v2s32*//*Label 9693*/ GIMT_Encode4(471915),
     /* 471835 */ /*GILLT_v2s64*//*Label 9694*/ GIMT_Encode4(471950),
     /* 471839 */ /*GILLT_v4s16*//*Label 9695*/ GIMT_Encode4(471985),
     /* 471843 */ /*GILLT_v4s32*//*Label 9696*/ GIMT_Encode4(472020),
     /* 471847 */ /*GILLT_v8s8*//*Label 9697*/ GIMT_Encode4(472055),
     /* 471851 */ /*GILLT_v8s16*//*Label 9698*/ GIMT_Encode4(472090),
     /* 471855 */ /*GILLT_v16s8*//*Label 9699*/ GIMT_Encode4(472125),
     /* 471859 */ // Label 9692: @471859
     /* 471859 */ GIM_Try, /*On fail goto*//*Label 9701*/ GIMT_Encode4(471914),
     /* 471864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 471867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471871 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471875 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471878 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 471883 */   GIM_Try, /*On fail goto*//*Label 9702*/ GIMT_Encode4(471898), // Rule ID 2160 //
     /* 471888 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471891 */     // (AArch64vlshr:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRd:{ *:[i64] } FPR64:{ *:[i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471891 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
     /* 471896 */     GIR_RootConstrainSelectedInstOperands,
     /* 471897 */     // GIR_Coverage, 2160,
     /* 471897 */     GIR_Done,
     /* 471898 */   // Label 9702: @471898
     /* 471898 */   GIM_Try, /*On fail goto*//*Label 9703*/ GIMT_Encode4(471913), // Rule ID 6931 //
     /* 471903 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471906 */     // (AArch64vlshr:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRd:{ *:[v1i64] } FPR64:{ *:[v1i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)
     /* 471906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRd),
     /* 471911 */     GIR_RootConstrainSelectedInstOperands,
     /* 471912 */     // GIR_Coverage, 6931,
     /* 471912 */     GIR_Done,
     /* 471913 */   // Label 9703: @471913
     /* 471913 */   GIM_Reject,
     /* 471914 */ // Label 9701: @471914
     /* 471914 */ GIM_Reject,
     /* 471915 */ // Label 9693: @471915
     /* 471915 */ GIM_Try, /*On fail goto*//*Label 9704*/ GIMT_Encode4(471949), // Rule ID 2317 //
     /* 471920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 471926 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471930 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 471934 */   // MIs[0] imm
     /* 471934 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471937 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 471942 */   // (AArch64vlshr:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (USHRv2i32_shift:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471942 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i32_shift),
     /* 471947 */   GIR_RootConstrainSelectedInstOperands,
     /* 471948 */   // GIR_Coverage, 2317,
     /* 471948 */   GIR_Done,
     /* 471949 */ // Label 9704: @471949
     /* 471949 */ GIM_Reject,
     /* 471950 */ // Label 9694: @471950
     /* 471950 */ GIM_Try, /*On fail goto*//*Label 9705*/ GIMT_Encode4(471984), // Rule ID 2319 //
     /* 471955 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471958 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 471961 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471965 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 471969 */   // MIs[0] imm
     /* 471969 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 471972 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR64),
     /* 471977 */   // (AArch64vlshr:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR64>>:$imm)  =>  (USHRv2i64_shift:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 471977 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv2i64_shift),
     /* 471982 */   GIR_RootConstrainSelectedInstOperands,
     /* 471983 */   // GIR_Coverage, 2319,
     /* 471983 */   GIR_Done,
     /* 471984 */ // Label 9705: @471984
     /* 471984 */ GIM_Reject,
     /* 471985 */ // Label 9695: @471985
     /* 471985 */ GIM_Try, /*On fail goto*//*Label 9706*/ GIMT_Encode4(472019), // Rule ID 2315 //
     /* 471990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 471993 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 471996 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472000 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472004 */   // MIs[0] imm
     /* 472004 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 472007 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 472012 */   // (AArch64vlshr:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (USHRv4i16_shift:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 472012 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i16_shift),
     /* 472017 */   GIR_RootConstrainSelectedInstOperands,
     /* 472018 */   // GIR_Coverage, 2315,
     /* 472018 */   GIR_Done,
     /* 472019 */ // Label 9706: @472019
     /* 472019 */ GIM_Reject,
     /* 472020 */ // Label 9696: @472020
     /* 472020 */ GIM_Try, /*On fail goto*//*Label 9707*/ GIMT_Encode4(472054), // Rule ID 2318 //
     /* 472025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 472031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472035 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472039 */   // MIs[0] imm
     /* 472039 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 472042 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR32),
     /* 472047 */   // (AArch64vlshr:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR32>>:$imm)  =>  (USHRv4i32_shift:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 472047 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv4i32_shift),
     /* 472052 */   GIR_RootConstrainSelectedInstOperands,
     /* 472053 */   // GIR_Coverage, 2318,
     /* 472053 */   GIR_Done,
     /* 472054 */ // Label 9707: @472054
     /* 472054 */ GIM_Reject,
     /* 472055 */ // Label 9697: @472055
     /* 472055 */ GIM_Try, /*On fail goto*//*Label 9708*/ GIMT_Encode4(472089), // Rule ID 2313 //
     /* 472060 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472063 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 472066 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472070 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472074 */   // MIs[0] imm
     /* 472074 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 472077 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 472082 */   // (AArch64vlshr:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (USHRv8i8_shift:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 472082 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i8_shift),
     /* 472087 */   GIR_RootConstrainSelectedInstOperands,
     /* 472088 */   // GIR_Coverage, 2313,
     /* 472088 */   GIR_Done,
     /* 472089 */ // Label 9708: @472089
     /* 472089 */ GIM_Reject,
     /* 472090 */ // Label 9698: @472090
     /* 472090 */ GIM_Try, /*On fail goto*//*Label 9709*/ GIMT_Encode4(472124), // Rule ID 2316 //
     /* 472095 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472098 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 472101 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472105 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472109 */   // MIs[0] imm
     /* 472109 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 472112 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR16),
     /* 472117 */   // (AArch64vlshr:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR16>>:$imm)  =>  (USHRv8i16_shift:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 472117 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv8i16_shift),
     /* 472122 */   GIR_RootConstrainSelectedInstOperands,
     /* 472123 */   // GIR_Coverage, 2316,
     /* 472123 */   GIR_Done,
     /* 472124 */ // Label 9709: @472124
     /* 472124 */ GIM_Reject,
     /* 472125 */ // Label 9699: @472125
     /* 472125 */ GIM_Try, /*On fail goto*//*Label 9710*/ GIMT_Encode4(472159), // Rule ID 2314 //
     /* 472130 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472133 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 472136 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472140 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472144 */   // MIs[0] imm
     /* 472144 */   GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 472147 */   GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_vecshiftR8),
     /* 472152 */   // (AArch64vlshr:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] })<<P:Predicate_vecshiftR8>>:$imm)  =>  (USHRv16i8_shift:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, (timm:{ *:[i32] }):$imm)
     /* 472152 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::USHRv16i8_shift),
     /* 472157 */   GIR_RootConstrainSelectedInstOperands,
     /* 472158 */   // GIR_Coverage, 2314,
     /* 472158 */   GIR_Done,
     /* 472159 */ // Label 9710: @472159
     /* 472159 */ GIM_Reject,
     /* 472160 */ // Label 9700: @472160
     /* 472160 */ GIM_Reject,
     /* 472161 */ // Label 171: @472161
     /* 472161 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9729*/ GIMT_Encode4(472940),
     /* 472172 */ /*GILLT_v2s32*//*Label 9711*/ GIMT_Encode4(472248),
     /* 472176 */ /*GILLT_v2s64*//*Label 9712*/ GIMT_Encode4(472303),
     /* 472180 */ /*GILLT_v4s16*//*Label 9713*/ GIMT_Encode4(472358),
     /* 472184 */ /*GILLT_v4s32*//*Label 9714*/ GIMT_Encode4(472413),
     /* 472188 */ /*GILLT_v8s8*//*Label 9715*/ GIMT_Encode4(472468),
     /* 472192 */ /*GILLT_v8s16*//*Label 9716*/ GIMT_Encode4(472502),
     /* 472196 */ /*GILLT_v16s8*//*Label 9717*/ GIMT_Encode4(472557), GIMT_Encode4(0),
     /* 472204 */ /*GILLT_nxv2s1*//*Label 9718*/ GIMT_Encode4(472591),
     /* 472208 */ /*GILLT_nxv2s16*//*Label 9719*/ GIMT_Encode4(472617),
     /* 472212 */ /*GILLT_nxv2s32*//*Label 9720*/ GIMT_Encode4(472643),
     /* 472216 */ /*GILLT_nxv2s64*//*Label 9721*/ GIMT_Encode4(472669),
     /* 472220 */ /*GILLT_nxv4s1*//*Label 9722*/ GIMT_Encode4(472716),
     /* 472224 */ /*GILLT_nxv4s16*//*Label 9723*/ GIMT_Encode4(472742),
     /* 472228 */ /*GILLT_nxv4s32*//*Label 9724*/ GIMT_Encode4(472768),
     /* 472232 */ /*GILLT_nxv8s1*//*Label 9725*/ GIMT_Encode4(472815),
     /* 472236 */ /*GILLT_nxv8s16*//*Label 9726*/ GIMT_Encode4(472841),
     /* 472240 */ /*GILLT_nxv16s1*//*Label 9727*/ GIMT_Encode4(472888),
     /* 472244 */ /*GILLT_nxv16s8*//*Label 9728*/ GIMT_Encode4(472914),
     /* 472248 */ // Label 9711: @472248
     /* 472248 */ GIM_Try, /*On fail goto*//*Label 9730*/ GIMT_Encode4(472302),
     /* 472253 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 472256 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 472259 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472263 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472267 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472271 */   GIM_Try, /*On fail goto*//*Label 9731*/ GIMT_Encode4(472286), // Rule ID 1933 //
     /* 472276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472279 */     // (AArch64zip1:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ZIP1v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 472279 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 472284 */     GIR_RootConstrainSelectedInstOperands,
     /* 472285 */     // GIR_Coverage, 1933,
     /* 472285 */     GIR_Done,
     /* 472286 */   // Label 9731: @472286
     /* 472286 */   GIM_Try, /*On fail goto*//*Label 9732*/ GIMT_Encode4(472301), // Rule ID 6083 //
     /* 472291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472294 */     // (AArch64zip1:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (ZIP1v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 472294 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i32),
     /* 472299 */     GIR_RootConstrainSelectedInstOperands,
     /* 472300 */     // GIR_Coverage, 6083,
     /* 472300 */     GIR_Done,
     /* 472301 */   // Label 9732: @472301
     /* 472301 */   GIM_Reject,
     /* 472302 */ // Label 9730: @472302
     /* 472302 */ GIM_Reject,
     /* 472303 */ // Label 9712: @472303
     /* 472303 */ GIM_Try, /*On fail goto*//*Label 9733*/ GIMT_Encode4(472357),
     /* 472308 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 472311 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 472314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472318 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472322 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472326 */   GIM_Try, /*On fail goto*//*Label 9734*/ GIMT_Encode4(472341), // Rule ID 1935 //
     /* 472331 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472334 */     // (AArch64zip1:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ZIP1v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 472334 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
     /* 472339 */     GIR_RootConstrainSelectedInstOperands,
     /* 472340 */     // GIR_Coverage, 1935,
     /* 472340 */     GIR_Done,
     /* 472341 */   // Label 9734: @472341
     /* 472341 */   GIM_Try, /*On fail goto*//*Label 9735*/ GIMT_Encode4(472356), // Rule ID 6085 //
     /* 472346 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472349 */     // (AArch64zip1:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (ZIP1v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 472349 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v2i64),
     /* 472354 */     GIR_RootConstrainSelectedInstOperands,
     /* 472355 */     // GIR_Coverage, 6085,
     /* 472355 */     GIR_Done,
     /* 472356 */   // Label 9735: @472356
     /* 472356 */   GIM_Reject,
     /* 472357 */ // Label 9733: @472357
     /* 472357 */ GIM_Reject,
     /* 472358 */ // Label 9713: @472358
     /* 472358 */ GIM_Try, /*On fail goto*//*Label 9736*/ GIMT_Encode4(472412),
     /* 472363 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 472366 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 472369 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472373 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472377 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472381 */   GIM_Try, /*On fail goto*//*Label 9737*/ GIMT_Encode4(472396), // Rule ID 1931 //
     /* 472386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472389 */     // (AArch64zip1:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ZIP1v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 472389 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 472394 */     GIR_RootConstrainSelectedInstOperands,
     /* 472395 */     // GIR_Coverage, 1931,
     /* 472395 */     GIR_Done,
     /* 472396 */   // Label 9737: @472396
     /* 472396 */   GIM_Try, /*On fail goto*//*Label 9738*/ GIMT_Encode4(472411), // Rule ID 6081 //
     /* 472401 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472404 */     // (AArch64zip1:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (ZIP1v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 472404 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i16),
     /* 472409 */     GIR_RootConstrainSelectedInstOperands,
     /* 472410 */     // GIR_Coverage, 6081,
     /* 472410 */     GIR_Done,
     /* 472411 */   // Label 9738: @472411
     /* 472411 */   GIM_Reject,
     /* 472412 */ // Label 9736: @472412
     /* 472412 */ GIM_Reject,
     /* 472413 */ // Label 9714: @472413
     /* 472413 */ GIM_Try, /*On fail goto*//*Label 9739*/ GIMT_Encode4(472467),
     /* 472418 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 472421 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 472424 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472428 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472432 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472436 */   GIM_Try, /*On fail goto*//*Label 9740*/ GIMT_Encode4(472451), // Rule ID 1934 //
     /* 472441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472444 */     // (AArch64zip1:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ZIP1v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 472444 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
     /* 472449 */     GIR_RootConstrainSelectedInstOperands,
     /* 472450 */     // GIR_Coverage, 1934,
     /* 472450 */     GIR_Done,
     /* 472451 */   // Label 9740: @472451
     /* 472451 */   GIM_Try, /*On fail goto*//*Label 9741*/ GIMT_Encode4(472466), // Rule ID 6084 //
     /* 472456 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472459 */     // (AArch64zip1:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (ZIP1v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 472459 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v4i32),
     /* 472464 */     GIR_RootConstrainSelectedInstOperands,
     /* 472465 */     // GIR_Coverage, 6084,
     /* 472465 */     GIR_Done,
     /* 472466 */   // Label 9741: @472466
     /* 472466 */   GIM_Reject,
     /* 472467 */ // Label 9739: @472467
     /* 472467 */ GIM_Reject,
     /* 472468 */ // Label 9715: @472468
     /* 472468 */ GIM_Try, /*On fail goto*//*Label 9742*/ GIMT_Encode4(472501), // Rule ID 1929 //
     /* 472473 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472476 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 472479 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 472482 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472486 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472490 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 472494 */   // (AArch64zip1:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ZIP1v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 472494 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i8),
     /* 472499 */   GIR_RootConstrainSelectedInstOperands,
     /* 472500 */   // GIR_Coverage, 1929,
     /* 472500 */   GIR_Done,
     /* 472501 */ // Label 9742: @472501
     /* 472501 */ GIM_Reject,
     /* 472502 */ // Label 9716: @472502
     /* 472502 */ GIM_Try, /*On fail goto*//*Label 9743*/ GIMT_Encode4(472556),
     /* 472507 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 472510 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 472513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472517 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472521 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472525 */   GIM_Try, /*On fail goto*//*Label 9744*/ GIMT_Encode4(472540), // Rule ID 1932 //
     /* 472530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472533 */     // (AArch64zip1:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ZIP1v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 472533 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
     /* 472538 */     GIR_RootConstrainSelectedInstOperands,
     /* 472539 */     // GIR_Coverage, 1932,
     /* 472539 */     GIR_Done,
     /* 472540 */   // Label 9744: @472540
     /* 472540 */   GIM_Try, /*On fail goto*//*Label 9745*/ GIMT_Encode4(472555), // Rule ID 6082 //
     /* 472545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472548 */     // (AArch64zip1:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (ZIP1v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 472548 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v8i16),
     /* 472553 */     GIR_RootConstrainSelectedInstOperands,
     /* 472554 */     // GIR_Coverage, 6082,
     /* 472554 */     GIR_Done,
     /* 472555 */   // Label 9745: @472555
     /* 472555 */   GIM_Reject,
     /* 472556 */ // Label 9743: @472556
     /* 472556 */ GIM_Reject,
     /* 472557 */ // Label 9717: @472557
     /* 472557 */ GIM_Try, /*On fail goto*//*Label 9746*/ GIMT_Encode4(472590), // Rule ID 1930 //
     /* 472562 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 472565 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 472568 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 472571 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472575 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472579 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 472583 */   // (AArch64zip1:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ZIP1v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 472583 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1v16i8),
     /* 472588 */   GIR_RootConstrainSelectedInstOperands,
     /* 472589 */   // GIR_Coverage, 1930,
     /* 472589 */   GIR_Done,
     /* 472590 */ // Label 9746: @472590
     /* 472590 */ GIM_Reject,
     /* 472591 */ // Label 9718: @472591
     /* 472591 */ GIM_Try, /*On fail goto*//*Label 9747*/ GIMT_Encode4(472616), // Rule ID 3418 //
     /* 472596 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472599 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 472602 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 472605 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 472609 */   // (AArch64zip1:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (ZIP1_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 472609 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_D),
     /* 472614 */   GIR_RootConstrainSelectedInstOperands,
     /* 472615 */   // GIR_Coverage, 3418,
     /* 472615 */   GIR_Done,
     /* 472616 */ // Label 9747: @472616
     /* 472616 */ GIM_Reject,
     /* 472617 */ // Label 9719: @472617
     /* 472617 */ GIM_Try, /*On fail goto*//*Label 9748*/ GIMT_Encode4(472642), // Rule ID 2941 //
     /* 472622 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472625 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 472628 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 472631 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472635 */   // (AArch64zip1:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 472635 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 472640 */   GIR_RootConstrainSelectedInstOperands,
     /* 472641 */   // GIR_Coverage, 2941,
     /* 472641 */   GIR_Done,
     /* 472642 */ // Label 9748: @472642
     /* 472642 */ GIM_Reject,
     /* 472643 */ // Label 9720: @472643
     /* 472643 */ GIM_Try, /*On fail goto*//*Label 9749*/ GIMT_Encode4(472668), // Rule ID 2942 //
     /* 472648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 472654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 472657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472661 */   // (AArch64zip1:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 472661 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 472666 */   GIR_RootConstrainSelectedInstOperands,
     /* 472667 */   // GIR_Coverage, 2942,
     /* 472667 */   GIR_Done,
     /* 472668 */ // Label 9749: @472668
     /* 472668 */ GIM_Reject,
     /* 472669 */ // Label 9721: @472669
     /* 472669 */ GIM_Try, /*On fail goto*//*Label 9750*/ GIMT_Encode4(472715),
     /* 472674 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 472677 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 472680 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472684 */   GIM_Try, /*On fail goto*//*Label 9751*/ GIMT_Encode4(472699), // Rule ID 2937 //
     /* 472689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472692 */     // (AArch64zip1:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 472692 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 472697 */     GIR_RootConstrainSelectedInstOperands,
     /* 472698 */     // GIR_Coverage, 2937,
     /* 472698 */     GIR_Done,
     /* 472699 */   // Label 9751: @472699
     /* 472699 */   GIM_Try, /*On fail goto*//*Label 9752*/ GIMT_Encode4(472714), // Rule ID 2943 //
     /* 472704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472707 */     // (AArch64zip1:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP1_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 472707 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_D),
     /* 472712 */     GIR_RootConstrainSelectedInstOperands,
     /* 472713 */     // GIR_Coverage, 2943,
     /* 472713 */     GIR_Done,
     /* 472714 */   // Label 9752: @472714
     /* 472714 */   GIM_Reject,
     /* 472715 */ // Label 9750: @472715
     /* 472715 */ GIM_Reject,
     /* 472716 */ // Label 9722: @472716
     /* 472716 */ GIM_Try, /*On fail goto*//*Label 9753*/ GIMT_Encode4(472741), // Rule ID 3417 //
     /* 472721 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472724 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 472727 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 472730 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 472734 */   // (AArch64zip1:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (ZIP1_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 472734 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_S),
     /* 472739 */   GIR_RootConstrainSelectedInstOperands,
     /* 472740 */   // GIR_Coverage, 3417,
     /* 472740 */   GIR_Done,
     /* 472741 */ // Label 9753: @472741
     /* 472741 */ GIM_Reject,
     /* 472742 */ // Label 9723: @472742
     /* 472742 */ GIM_Try, /*On fail goto*//*Label 9754*/ GIMT_Encode4(472767), // Rule ID 2939 //
     /* 472747 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472750 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 472753 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 472756 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472760 */   // (AArch64zip1:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 472760 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 472765 */   GIR_RootConstrainSelectedInstOperands,
     /* 472766 */   // GIR_Coverage, 2939,
     /* 472766 */   GIR_Done,
     /* 472767 */ // Label 9754: @472767
     /* 472767 */ GIM_Reject,
     /* 472768 */ // Label 9724: @472768
     /* 472768 */ GIM_Try, /*On fail goto*//*Label 9755*/ GIMT_Encode4(472814),
     /* 472773 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 472776 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 472779 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472783 */   GIM_Try, /*On fail goto*//*Label 9756*/ GIMT_Encode4(472798), // Rule ID 2936 //
     /* 472788 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472791 */     // (AArch64zip1:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 472791 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 472796 */     GIR_RootConstrainSelectedInstOperands,
     /* 472797 */     // GIR_Coverage, 2936,
     /* 472797 */     GIR_Done,
     /* 472798 */   // Label 9756: @472798
     /* 472798 */   GIM_Try, /*On fail goto*//*Label 9757*/ GIMT_Encode4(472813), // Rule ID 2940 //
     /* 472803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472806 */     // (AArch64zip1:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP1_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 472806 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_S),
     /* 472811 */     GIR_RootConstrainSelectedInstOperands,
     /* 472812 */     // GIR_Coverage, 2940,
     /* 472812 */     GIR_Done,
     /* 472813 */   // Label 9757: @472813
     /* 472813 */   GIM_Reject,
     /* 472814 */ // Label 9755: @472814
     /* 472814 */ GIM_Reject,
     /* 472815 */ // Label 9725: @472815
     /* 472815 */ GIM_Try, /*On fail goto*//*Label 9758*/ GIMT_Encode4(472840), // Rule ID 3416 //
     /* 472820 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472823 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 472826 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 472829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 472833 */   // (AArch64zip1:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (ZIP1_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 472833 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_H),
     /* 472838 */   GIR_RootConstrainSelectedInstOperands,
     /* 472839 */   // GIR_Coverage, 3416,
     /* 472839 */   GIR_Done,
     /* 472840 */ // Label 9758: @472840
     /* 472840 */ GIM_Reject,
     /* 472841 */ // Label 9726: @472841
     /* 472841 */ GIM_Try, /*On fail goto*//*Label 9759*/ GIMT_Encode4(472887),
     /* 472846 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 472849 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 472852 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472856 */   GIM_Try, /*On fail goto*//*Label 9760*/ GIMT_Encode4(472871), // Rule ID 2935 //
     /* 472861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472864 */     // (AArch64zip1:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP1_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 472864 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
     /* 472869 */     GIR_RootConstrainSelectedInstOperands,
     /* 472870 */     // GIR_Coverage, 2935,
     /* 472870 */     GIR_Done,
     /* 472871 */   // Label 9760: @472871
     /* 472871 */   GIM_Try, /*On fail goto*//*Label 9761*/ GIMT_Encode4(472886), // Rule ID 2938 //
     /* 472876 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472879 */     // (AArch64zip1:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP1_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 472879 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_H),
     /* 472884 */     GIR_RootConstrainSelectedInstOperands,
     /* 472885 */     // GIR_Coverage, 2938,
     /* 472885 */     GIR_Done,
     /* 472886 */   // Label 9761: @472886
     /* 472886 */   GIM_Reject,
     /* 472887 */ // Label 9759: @472887
     /* 472887 */ GIM_Reject,
     /* 472888 */ // Label 9727: @472888
     /* 472888 */ GIM_Try, /*On fail goto*//*Label 9762*/ GIMT_Encode4(472913), // Rule ID 2432 //
     /* 472893 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472896 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 472899 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 472902 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 472906 */   // (AArch64zip1:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP1_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 472906 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_PPP_B),
     /* 472911 */   GIR_RootConstrainSelectedInstOperands,
     /* 472912 */   // GIR_Coverage, 2432,
     /* 472912 */   GIR_Done,
     /* 472913 */ // Label 9762: @472913
     /* 472913 */ GIM_Reject,
     /* 472914 */ // Label 9728: @472914
     /* 472914 */ GIM_Try, /*On fail goto*//*Label 9763*/ GIMT_Encode4(472939), // Rule ID 2934 //
     /* 472919 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 472922 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 472925 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 472928 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 472932 */   // (AArch64zip1:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP1_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 472932 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP1_ZZZ_B),
     /* 472937 */   GIR_RootConstrainSelectedInstOperands,
     /* 472938 */   // GIR_Coverage, 2934,
     /* 472938 */   GIR_Done,
     /* 472939 */ // Label 9763: @472939
     /* 472939 */ GIM_Reject,
     /* 472940 */ // Label 9729: @472940
     /* 472940 */ GIM_Reject,
     /* 472941 */ // Label 172: @472941
     /* 472941 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(24), /*)*//*default:*//*Label 9782*/ GIMT_Encode4(473720),
     /* 472952 */ /*GILLT_v2s32*//*Label 9764*/ GIMT_Encode4(473028),
     /* 472956 */ /*GILLT_v2s64*//*Label 9765*/ GIMT_Encode4(473083),
     /* 472960 */ /*GILLT_v4s16*//*Label 9766*/ GIMT_Encode4(473138),
     /* 472964 */ /*GILLT_v4s32*//*Label 9767*/ GIMT_Encode4(473193),
     /* 472968 */ /*GILLT_v8s8*//*Label 9768*/ GIMT_Encode4(473248),
     /* 472972 */ /*GILLT_v8s16*//*Label 9769*/ GIMT_Encode4(473282),
     /* 472976 */ /*GILLT_v16s8*//*Label 9770*/ GIMT_Encode4(473337), GIMT_Encode4(0),
     /* 472984 */ /*GILLT_nxv2s1*//*Label 9771*/ GIMT_Encode4(473371),
     /* 472988 */ /*GILLT_nxv2s16*//*Label 9772*/ GIMT_Encode4(473397),
     /* 472992 */ /*GILLT_nxv2s32*//*Label 9773*/ GIMT_Encode4(473423),
     /* 472996 */ /*GILLT_nxv2s64*//*Label 9774*/ GIMT_Encode4(473449),
     /* 473000 */ /*GILLT_nxv4s1*//*Label 9775*/ GIMT_Encode4(473496),
     /* 473004 */ /*GILLT_nxv4s16*//*Label 9776*/ GIMT_Encode4(473522),
     /* 473008 */ /*GILLT_nxv4s32*//*Label 9777*/ GIMT_Encode4(473548),
     /* 473012 */ /*GILLT_nxv8s1*//*Label 9778*/ GIMT_Encode4(473595),
     /* 473016 */ /*GILLT_nxv8s16*//*Label 9779*/ GIMT_Encode4(473621),
     /* 473020 */ /*GILLT_nxv16s1*//*Label 9780*/ GIMT_Encode4(473668),
     /* 473024 */ /*GILLT_nxv16s8*//*Label 9781*/ GIMT_Encode4(473694),
     /* 473028 */ // Label 9764: @473028
     /* 473028 */ GIM_Try, /*On fail goto*//*Label 9783*/ GIMT_Encode4(473082),
     /* 473033 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
     /* 473036 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
     /* 473039 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473043 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473047 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473051 */   GIM_Try, /*On fail goto*//*Label 9784*/ GIMT_Encode4(473066), // Rule ID 1940 //
     /* 473056 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473059 */     // (AArch64zip2:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)  =>  (ZIP2v2i32:{ *:[v2i32] } V64:{ *:[v2i32] }:$Rn, V64:{ *:[v2i32] }:$Rm)
     /* 473059 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 473064 */     GIR_RootConstrainSelectedInstOperands,
     /* 473065 */     // GIR_Coverage, 1940,
     /* 473065 */     GIR_Done,
     /* 473066 */   // Label 9784: @473066
     /* 473066 */   GIM_Try, /*On fail goto*//*Label 9785*/ GIMT_Encode4(473081), // Rule ID 6088 //
     /* 473071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473074 */     // (AArch64zip2:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)  =>  (ZIP2v2i32:{ *:[v2f32] } V64:{ *:[v2f32] }:$Rn, V64:{ *:[v2f32] }:$Rm)
     /* 473074 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i32),
     /* 473079 */     GIR_RootConstrainSelectedInstOperands,
     /* 473080 */     // GIR_Coverage, 6088,
     /* 473080 */     GIR_Done,
     /* 473081 */   // Label 9785: @473081
     /* 473081 */   GIM_Reject,
     /* 473082 */ // Label 9783: @473082
     /* 473082 */ GIM_Reject,
     /* 473083 */ // Label 9765: @473083
     /* 473083 */ GIM_Try, /*On fail goto*//*Label 9786*/ GIMT_Encode4(473137),
     /* 473088 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 473091 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 473094 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473098 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473102 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473106 */   GIM_Try, /*On fail goto*//*Label 9787*/ GIMT_Encode4(473121), // Rule ID 1942 //
     /* 473111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473114 */     // (AArch64zip2:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)  =>  (ZIP2v2i64:{ *:[v2i64] } V128:{ *:[v2i64] }:$Rn, V128:{ *:[v2i64] }:$Rm)
     /* 473114 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
     /* 473119 */     GIR_RootConstrainSelectedInstOperands,
     /* 473120 */     // GIR_Coverage, 1942,
     /* 473120 */     GIR_Done,
     /* 473121 */   // Label 9787: @473121
     /* 473121 */   GIM_Try, /*On fail goto*//*Label 9788*/ GIMT_Encode4(473136), // Rule ID 6090 //
     /* 473126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473129 */     // (AArch64zip2:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)  =>  (ZIP2v2i64:{ *:[v2f64] } V128:{ *:[v2f64] }:$Rn, V128:{ *:[v2f64] }:$Rm)
     /* 473129 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v2i64),
     /* 473134 */     GIR_RootConstrainSelectedInstOperands,
     /* 473135 */     // GIR_Coverage, 6090,
     /* 473135 */     GIR_Done,
     /* 473136 */   // Label 9788: @473136
     /* 473136 */   GIM_Reject,
     /* 473137 */ // Label 9786: @473137
     /* 473137 */ GIM_Reject,
     /* 473138 */ // Label 9766: @473138
     /* 473138 */ GIM_Try, /*On fail goto*//*Label 9789*/ GIMT_Encode4(473192),
     /* 473143 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
     /* 473146 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
     /* 473149 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473153 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473157 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473161 */   GIM_Try, /*On fail goto*//*Label 9790*/ GIMT_Encode4(473176), // Rule ID 1938 //
     /* 473166 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473169 */     // (AArch64zip2:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)  =>  (ZIP2v4i16:{ *:[v4i16] } V64:{ *:[v4i16] }:$Rn, V64:{ *:[v4i16] }:$Rm)
     /* 473169 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 473174 */     GIR_RootConstrainSelectedInstOperands,
     /* 473175 */     // GIR_Coverage, 1938,
     /* 473175 */     GIR_Done,
     /* 473176 */   // Label 9790: @473176
     /* 473176 */   GIM_Try, /*On fail goto*//*Label 9791*/ GIMT_Encode4(473191), // Rule ID 6086 //
     /* 473181 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473184 */     // (AArch64zip2:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)  =>  (ZIP2v4i16:{ *:[v4f16] } V64:{ *:[v4f16] }:$Rn, V64:{ *:[v4f16] }:$Rm)
     /* 473184 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i16),
     /* 473189 */     GIR_RootConstrainSelectedInstOperands,
     /* 473190 */     // GIR_Coverage, 6086,
     /* 473190 */     GIR_Done,
     /* 473191 */   // Label 9791: @473191
     /* 473191 */   GIM_Reject,
     /* 473192 */ // Label 9789: @473192
     /* 473192 */ GIM_Reject,
     /* 473193 */ // Label 9767: @473193
     /* 473193 */ GIM_Try, /*On fail goto*//*Label 9792*/ GIMT_Encode4(473247),
     /* 473198 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 473201 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 473204 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473208 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473212 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473216 */   GIM_Try, /*On fail goto*//*Label 9793*/ GIMT_Encode4(473231), // Rule ID 1941 //
     /* 473221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473224 */     // (AArch64zip2:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)  =>  (ZIP2v4i32:{ *:[v4i32] } V128:{ *:[v4i32] }:$Rn, V128:{ *:[v4i32] }:$Rm)
     /* 473224 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
     /* 473229 */     GIR_RootConstrainSelectedInstOperands,
     /* 473230 */     // GIR_Coverage, 1941,
     /* 473230 */     GIR_Done,
     /* 473231 */   // Label 9793: @473231
     /* 473231 */   GIM_Try, /*On fail goto*//*Label 9794*/ GIMT_Encode4(473246), // Rule ID 6089 //
     /* 473236 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473239 */     // (AArch64zip2:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)  =>  (ZIP2v4i32:{ *:[v4f32] } V128:{ *:[v4f32] }:$Rn, V128:{ *:[v4f32] }:$Rm)
     /* 473239 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v4i32),
     /* 473244 */     GIR_RootConstrainSelectedInstOperands,
     /* 473245 */     // GIR_Coverage, 6089,
     /* 473245 */     GIR_Done,
     /* 473246 */   // Label 9794: @473246
     /* 473246 */   GIM_Reject,
     /* 473247 */ // Label 9792: @473247
     /* 473247 */ GIM_Reject,
     /* 473248 */ // Label 9768: @473248
     /* 473248 */ GIM_Try, /*On fail goto*//*Label 9795*/ GIMT_Encode4(473281), // Rule ID 1936 //
     /* 473253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
     /* 473259 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
     /* 473262 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473266 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473270 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR64RegClassID),
     /* 473274 */   // (AArch64zip2:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)  =>  (ZIP2v8i8:{ *:[v8i8] } V64:{ *:[v8i8] }:$Rn, V64:{ *:[v8i8] }:$Rm)
     /* 473274 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i8),
     /* 473279 */   GIR_RootConstrainSelectedInstOperands,
     /* 473280 */   // GIR_Coverage, 1936,
     /* 473280 */   GIR_Done,
     /* 473281 */ // Label 9795: @473281
     /* 473281 */ GIM_Reject,
     /* 473282 */ // Label 9769: @473282
     /* 473282 */ GIM_Try, /*On fail goto*//*Label 9796*/ GIMT_Encode4(473336),
     /* 473287 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 473290 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 473293 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473297 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473301 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473305 */   GIM_Try, /*On fail goto*//*Label 9797*/ GIMT_Encode4(473320), // Rule ID 1939 //
     /* 473310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473313 */     // (AArch64zip2:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)  =>  (ZIP2v8i16:{ *:[v8i16] } V128:{ *:[v8i16] }:$Rn, V128:{ *:[v8i16] }:$Rm)
     /* 473313 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
     /* 473318 */     GIR_RootConstrainSelectedInstOperands,
     /* 473319 */     // GIR_Coverage, 1939,
     /* 473319 */     GIR_Done,
     /* 473320 */   // Label 9797: @473320
     /* 473320 */   GIM_Try, /*On fail goto*//*Label 9798*/ GIMT_Encode4(473335), // Rule ID 6087 //
     /* 473325 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473328 */     // (AArch64zip2:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)  =>  (ZIP2v8i16:{ *:[v8f16] } V128:{ *:[v8f16] }:$Rn, V128:{ *:[v8f16] }:$Rm)
     /* 473328 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v8i16),
     /* 473333 */     GIR_RootConstrainSelectedInstOperands,
     /* 473334 */     // GIR_Coverage, 6087,
     /* 473334 */     GIR_Done,
     /* 473335 */   // Label 9798: @473335
     /* 473335 */   GIM_Reject,
     /* 473336 */ // Label 9796: @473336
     /* 473336 */ GIM_Reject,
     /* 473337 */ // Label 9770: @473337
     /* 473337 */ GIM_Try, /*On fail goto*//*Label 9799*/ GIMT_Encode4(473370), // Rule ID 1937 //
     /* 473342 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
     /* 473345 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 473348 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 473351 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473355 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473359 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AArch64::FPR128RegClassID),
     /* 473363 */   // (AArch64zip2:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)  =>  (ZIP2v16i8:{ *:[v16i8] } V128:{ *:[v16i8] }:$Rn, V128:{ *:[v16i8] }:$Rm)
     /* 473363 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2v16i8),
     /* 473368 */   GIR_RootConstrainSelectedInstOperands,
     /* 473369 */   // GIR_Coverage, 1937,
     /* 473369 */   GIR_Done,
     /* 473370 */ // Label 9799: @473370
     /* 473370 */ GIM_Reject,
     /* 473371 */ // Label 9771: @473371
     /* 473371 */ GIM_Try, /*On fail goto*//*Label 9800*/ GIMT_Encode4(473396), // Rule ID 9690 //
     /* 473376 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473379 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s1,
     /* 473382 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s1,
     /* 473385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 473389 */   // (AArch64zip2:{ *:[nxv2i1] } nxv2i1:{ *:[nxv2i1] }:$Op1, nxv2i1:{ *:[nxv2i1] }:$Op2)  =>  (ZIP2_PPP_D:{ *:[nxv2i1] } ?:{ *:[nxv2i1] }:$Op1, ?:{ *:[nxv2i1] }:$Op2)
     /* 473389 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_D),
     /* 473394 */   GIR_RootConstrainSelectedInstOperands,
     /* 473395 */   // GIR_Coverage, 9690,
     /* 473395 */   GIR_Done,
     /* 473396 */ // Label 9800: @473396
     /* 473396 */ GIM_Reject,
     /* 473397 */ // Label 9772: @473397
     /* 473397 */ GIM_Try, /*On fail goto*//*Label 9801*/ GIMT_Encode4(473422), // Rule ID 9645 //
     /* 473402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473405 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s16,
     /* 473408 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s16,
     /* 473411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473415 */   // (AArch64zip2:{ *:[nxv2f16] } nxv2f16:{ *:[nxv2f16] }:$Op1, nxv2f16:{ *:[nxv2f16] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f16] } ?:{ *:[nxv2f16] }:$Op1, ?:{ *:[nxv2f16] }:$Op2)
     /* 473415 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 473420 */   GIR_RootConstrainSelectedInstOperands,
     /* 473421 */   // GIR_Coverage, 9645,
     /* 473421 */   GIR_Done,
     /* 473422 */ // Label 9801: @473422
     /* 473422 */ GIM_Reject,
     /* 473423 */ // Label 9773: @473423
     /* 473423 */ GIM_Try, /*On fail goto*//*Label 9802*/ GIMT_Encode4(473448), // Rule ID 9646 //
     /* 473428 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473431 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s32,
     /* 473434 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s32,
     /* 473437 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473441 */   // (AArch64zip2:{ *:[nxv2f32] } nxv2f32:{ *:[nxv2f32] }:$Op1, nxv2f32:{ *:[nxv2f32] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f32] } ?:{ *:[nxv2f32] }:$Op1, ?:{ *:[nxv2f32] }:$Op2)
     /* 473441 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 473446 */   GIR_RootConstrainSelectedInstOperands,
     /* 473447 */   // GIR_Coverage, 9646,
     /* 473447 */   GIR_Done,
     /* 473448 */ // Label 9802: @473448
     /* 473448 */ GIM_Reject,
     /* 473449 */ // Label 9774: @473449
     /* 473449 */ GIM_Try, /*On fail goto*//*Label 9803*/ GIMT_Encode4(473495),
     /* 473454 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv2s64,
     /* 473457 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv2s64,
     /* 473460 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473464 */   GIM_Try, /*On fail goto*//*Label 9804*/ GIMT_Encode4(473479), // Rule ID 9641 //
     /* 473469 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473472 */     // (AArch64zip2:{ *:[nxv2i64] } nxv2i64:{ *:[nxv2i64] }:$Op1, nxv2i64:{ *:[nxv2i64] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2i64] } ?:{ *:[nxv2i64] }:$Op1, ?:{ *:[nxv2i64] }:$Op2)
     /* 473472 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 473477 */     GIR_RootConstrainSelectedInstOperands,
     /* 473478 */     // GIR_Coverage, 9641,
     /* 473478 */     GIR_Done,
     /* 473479 */   // Label 9804: @473479
     /* 473479 */   GIM_Try, /*On fail goto*//*Label 9805*/ GIMT_Encode4(473494), // Rule ID 9647 //
     /* 473484 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473487 */     // (AArch64zip2:{ *:[nxv2f64] } nxv2f64:{ *:[nxv2f64] }:$Op1, nxv2f64:{ *:[nxv2f64] }:$Op2)  =>  (ZIP2_ZZZ_D:{ *:[nxv2f64] } ?:{ *:[nxv2f64] }:$Op1, ?:{ *:[nxv2f64] }:$Op2)
     /* 473487 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_D),
     /* 473492 */     GIR_RootConstrainSelectedInstOperands,
     /* 473493 */     // GIR_Coverage, 9647,
     /* 473493 */     GIR_Done,
     /* 473494 */   // Label 9805: @473494
     /* 473494 */   GIM_Reject,
     /* 473495 */ // Label 9803: @473495
     /* 473495 */ GIM_Reject,
     /* 473496 */ // Label 9775: @473496
     /* 473496 */ GIM_Try, /*On fail goto*//*Label 9806*/ GIMT_Encode4(473521), // Rule ID 9689 //
     /* 473501 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473504 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s1,
     /* 473507 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s1,
     /* 473510 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 473514 */   // (AArch64zip2:{ *:[nxv4i1] } nxv4i1:{ *:[nxv4i1] }:$Op1, nxv4i1:{ *:[nxv4i1] }:$Op2)  =>  (ZIP2_PPP_S:{ *:[nxv4i1] } ?:{ *:[nxv4i1] }:$Op1, ?:{ *:[nxv4i1] }:$Op2)
     /* 473514 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_S),
     /* 473519 */   GIR_RootConstrainSelectedInstOperands,
     /* 473520 */   // GIR_Coverage, 9689,
     /* 473520 */   GIR_Done,
     /* 473521 */ // Label 9806: @473521
     /* 473521 */ GIM_Reject,
     /* 473522 */ // Label 9776: @473522
     /* 473522 */ GIM_Try, /*On fail goto*//*Label 9807*/ GIMT_Encode4(473547), // Rule ID 9643 //
     /* 473527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473530 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s16,
     /* 473533 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s16,
     /* 473536 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473540 */   // (AArch64zip2:{ *:[nxv4f16] } nxv4f16:{ *:[nxv4f16] }:$Op1, nxv4f16:{ *:[nxv4f16] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4f16] } ?:{ *:[nxv4f16] }:$Op1, ?:{ *:[nxv4f16] }:$Op2)
     /* 473540 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 473545 */   GIR_RootConstrainSelectedInstOperands,
     /* 473546 */   // GIR_Coverage, 9643,
     /* 473546 */   GIR_Done,
     /* 473547 */ // Label 9807: @473547
     /* 473547 */ GIM_Reject,
     /* 473548 */ // Label 9777: @473548
     /* 473548 */ GIM_Try, /*On fail goto*//*Label 9808*/ GIMT_Encode4(473594),
     /* 473553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv4s32,
     /* 473556 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv4s32,
     /* 473559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473563 */   GIM_Try, /*On fail goto*//*Label 9809*/ GIMT_Encode4(473578), // Rule ID 9640 //
     /* 473568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473571 */     // (AArch64zip2:{ *:[nxv4i32] } nxv4i32:{ *:[nxv4i32] }:$Op1, nxv4i32:{ *:[nxv4i32] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4i32] } ?:{ *:[nxv4i32] }:$Op1, ?:{ *:[nxv4i32] }:$Op2)
     /* 473571 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 473576 */     GIR_RootConstrainSelectedInstOperands,
     /* 473577 */     // GIR_Coverage, 9640,
     /* 473577 */     GIR_Done,
     /* 473578 */   // Label 9809: @473578
     /* 473578 */   GIM_Try, /*On fail goto*//*Label 9810*/ GIMT_Encode4(473593), // Rule ID 9644 //
     /* 473583 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473586 */     // (AArch64zip2:{ *:[nxv4f32] } nxv4f32:{ *:[nxv4f32] }:$Op1, nxv4f32:{ *:[nxv4f32] }:$Op2)  =>  (ZIP2_ZZZ_S:{ *:[nxv4f32] } ?:{ *:[nxv4f32] }:$Op1, ?:{ *:[nxv4f32] }:$Op2)
     /* 473586 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_S),
     /* 473591 */     GIR_RootConstrainSelectedInstOperands,
     /* 473592 */     // GIR_Coverage, 9644,
     /* 473592 */     GIR_Done,
     /* 473593 */   // Label 9810: @473593
     /* 473593 */   GIM_Reject,
     /* 473594 */ // Label 9808: @473594
     /* 473594 */ GIM_Reject,
     /* 473595 */ // Label 9778: @473595
     /* 473595 */ GIM_Try, /*On fail goto*//*Label 9811*/ GIMT_Encode4(473620), // Rule ID 9688 //
     /* 473600 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473603 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s1,
     /* 473606 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s1,
     /* 473609 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 473613 */   // (AArch64zip2:{ *:[nxv8i1] } nxv8i1:{ *:[nxv8i1] }:$Op1, nxv8i1:{ *:[nxv8i1] }:$Op2)  =>  (ZIP2_PPP_H:{ *:[nxv8i1] } ?:{ *:[nxv8i1] }:$Op1, ?:{ *:[nxv8i1] }:$Op2)
     /* 473613 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_H),
     /* 473618 */   GIR_RootConstrainSelectedInstOperands,
     /* 473619 */   // GIR_Coverage, 9688,
     /* 473619 */   GIR_Done,
     /* 473620 */ // Label 9811: @473620
     /* 473620 */ GIM_Reject,
     /* 473621 */ // Label 9779: @473621
     /* 473621 */ GIM_Try, /*On fail goto*//*Label 9812*/ GIMT_Encode4(473667),
     /* 473626 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv8s16,
     /* 473629 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv8s16,
     /* 473632 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473636 */   GIM_Try, /*On fail goto*//*Label 9813*/ GIMT_Encode4(473651), // Rule ID 9639 //
     /* 473641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473644 */     // (AArch64zip2:{ *:[nxv8i16] } nxv8i16:{ *:[nxv8i16] }:$Op1, nxv8i16:{ *:[nxv8i16] }:$Op2)  =>  (ZIP2_ZZZ_H:{ *:[nxv8i16] } ?:{ *:[nxv8i16] }:$Op1, ?:{ *:[nxv8i16] }:$Op2)
     /* 473644 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
     /* 473649 */     GIR_RootConstrainSelectedInstOperands,
     /* 473650 */     // GIR_Coverage, 9639,
     /* 473650 */     GIR_Done,
     /* 473651 */   // Label 9813: @473651
     /* 473651 */   GIM_Try, /*On fail goto*//*Label 9814*/ GIMT_Encode4(473666), // Rule ID 9642 //
     /* 473656 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473659 */     // (AArch64zip2:{ *:[nxv8f16] } nxv8f16:{ *:[nxv8f16] }:$Op1, nxv8f16:{ *:[nxv8f16] }:$Op2)  =>  (ZIP2_ZZZ_H:{ *:[nxv8f16] } ?:{ *:[nxv8f16] }:$Op1, ?:{ *:[nxv8f16] }:$Op2)
     /* 473659 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_H),
     /* 473664 */     GIR_RootConstrainSelectedInstOperands,
     /* 473665 */     // GIR_Coverage, 9642,
     /* 473665 */     GIR_Done,
     /* 473666 */   // Label 9814: @473666
     /* 473666 */   GIM_Reject,
     /* 473667 */ // Label 9812: @473667
     /* 473667 */ GIM_Reject,
     /* 473668 */ // Label 9780: @473668
     /* 473668 */ GIM_Try, /*On fail goto*//*Label 9815*/ GIMT_Encode4(473693), // Rule ID 2436 //
     /* 473673 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473676 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s1,
     /* 473679 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s1,
     /* 473682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::PPRRegClassID),
     /* 473686 */   // (AArch64zip2:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)  =>  (ZIP2_PPP_B:{ *:[nxv16i1] } nxv16i1:{ *:[nxv16i1] }:$Pn, nxv16i1:{ *:[nxv16i1] }:$Pm)
     /* 473686 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_PPP_B),
     /* 473691 */   GIR_RootConstrainSelectedInstOperands,
     /* 473692 */   // GIR_Coverage, 2436,
     /* 473692 */   GIR_Done,
     /* 473693 */ // Label 9815: @473693
     /* 473693 */ GIM_Reject,
     /* 473694 */ // Label 9781: @473694
     /* 473694 */ GIM_Try, /*On fail goto*//*Label 9816*/ GIMT_Encode4(473719), // Rule ID 9638 //
     /* 473699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSVE_or_SME),
     /* 473702 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_nxv16s8,
     /* 473705 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_nxv16s8,
     /* 473708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AArch64::ZPRRegClassID),
     /* 473712 */   // (AArch64zip2:{ *:[nxv16i8] } nxv16i8:{ *:[nxv16i8] }:$Op1, nxv16i8:{ *:[nxv16i8] }:$Op2)  =>  (ZIP2_ZZZ_B:{ *:[nxv16i8] } ?:{ *:[nxv16i8] }:$Op1, ?:{ *:[nxv16i8] }:$Op2)
     /* 473712 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AArch64::ZIP2_ZZZ_B),
     /* 473717 */   GIR_RootConstrainSelectedInstOperands,
     /* 473718 */   // GIR_Coverage, 9638,
     /* 473718 */   GIR_Done,
     /* 473719 */ // Label 9816: @473719
     /* 473719 */ GIM_Reject,
     /* 473720 */ // Label 9782: @473720
     /* 473720 */ GIM_Reject,
     /* 473721 */ // Label 173: @473721
     /* 473721 */ GIM_Reject,
     /* 473722 */ }; // Size: 473722 bytes
  return MatchTable0;
}
#undef GIMT_Encode2
#undef GIMT_Encode4
#undef GIMT_Encode8

#endif // ifdef GET_GLOBALISEL_IMPL

#ifdef GET_GLOBALISEL_PREDICATES_DECL
PredicateBitset AvailableModuleFeatures;
mutable PredicateBitset AvailableFunctionFeatures;
PredicateBitset getAvailableFeatures() const {
  return AvailableModuleFeatures | AvailableFunctionFeatures;
}
PredicateBitset
computeAvailableModuleFeatures(const AArch64Subtarget *Subtarget) const;
PredicateBitset
computeAvailableFunctionFeatures(const AArch64Subtarget *Subtarget,
                                 const MachineFunction *MF) const;
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
#ifdef GET_GLOBALISEL_PREDICATES_INIT
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
AvailableFunctionFeatures()
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
